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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-19 09:24:04 -04:00
parent 3139d37610
commit e9dfa828fe
33 changed files with 998 additions and 1022 deletions
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4
hw/rtl/generic_cache/VX_cache_dram_req_arb.v
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@@ -102,7 +102,7 @@ module VX_cache_dram_req_arb #(
wire dfqq_pop = !dwb_valid && dfqq_req && !dram_req_full; // If no dwb, and dfqq has valids, then pop
wire dfqq_push = (|per_bank_dram_fill_req_valid);
VX_cache_dfq_queue vx_cache_dfq_queue(
VX_cache_dfq_queue cache_dfq_queue(
.clk (clk),
.reset (reset),
.dfqq_push (dfqq_push),
@@ -121,7 +121,7 @@ module VX_cache_dram_req_arb #(
VX_generic_priority_encoder #(
.N(NUM_BANKS)
) vx_sel_dwb (
) sel_dwb (
.valids(use_wb_valid),
.index (dwb_bank),
.found (dwb_valid)