wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Update needed

Browse Source 
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
This commit is contained in:
trmontgomery
2020-02-18 19:42:10 -05:00
parent 7abd355b05 28ce40eebf
commit e997494d41
43 changed files with 699 additions and 288 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
rtl/Makefile
View File

@@ -33,7 +33,7 @@ VERILATOR:
VERILATORnoWarnings:
echo "#define VCD_OFF" > simulate/tb_debug.h
verilator $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) $(CF) $(WNO)
verilator $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) $(CF) $(WNO) $(DEB)
compdebug:
echo "#define VCD_OUTPUT" > simulate/tb_debug.h

24
rtl/VX_back_end.v
View File

@@ -32,7 +32,7 @@ assign VX_writeback_inter.wb_warp_num = VX_writeback_temp.wb_warp_num;
VX_mw_wb_inter VX_mw_wb();
wire no_slot_mem;
wire no_slot_mem;
VX_mem_req_inter VX_exe_mem_req();
@@ -55,6 +55,8 @@ VX_gpu_inst_req_inter VX_gpu_inst_req();
// CSR unit inputs
VX_csr_req_inter VX_csr_req();
VX_csr_wb_inter VX_csr_wb();
wire no_slot_csr;
wire stall_gpr_csr;
VX_gpr_stage VX_gpr_stage(
.clk (clk),
@@ -67,6 +69,7 @@ VX_gpr_stage VX_gpr_stage(
.VX_lsu_req (VX_lsu_req),
.VX_gpu_inst_req (VX_gpu_inst_req),
.VX_csr_req (VX_csr_req),
.stall_gpr_csr (stall_gpr_csr),
// End new
.memory_delay (out_mem_delay),
.gpr_stage_delay (gpr_stage_delay)
@@ -100,9 +103,19 @@ VX_gpgpu_inst VX_gpgpu_inst(
.VX_warp_ctl (VX_warp_ctl)
);
VX_csr_wrapper VX_csr_wrapper(
.VX_csr_req(VX_csr_req),
.VX_csr_wb (VX_csr_wb)
// VX_csr_wrapper VX_csr_wrapper(
// .VX_csr_req(VX_csr_req),
// .VX_csr_wb (VX_csr_wb)
// );
VX_csr_pipe VX_csr_pipe(
.clk (clk),
.reset (reset),
.no_slot_csr (no_slot_csr),
.VX_csr_req (VX_csr_req),
.VX_writeback(VX_writeback_temp),
.VX_csr_wb (VX_csr_wb),
.stall_gpr_csr(stall_gpr_csr)
);
VX_writeback VX_wb(
@@ -113,7 +126,8 @@ VX_writeback VX_wb(
.VX_csr_wb (VX_csr_wb),
.VX_writeback_inter(VX_writeback_temp),
.no_slot_mem (no_slot_mem)
.no_slot_mem (no_slot_mem),
.no_slot_csr (no_slot_csr)
);
endmodule

82
rtl/VX_csr_data.v Normal file
View File

@@ -0,0 +1,82 @@
`include "../VX_define.v"
module VX_csr_data (
input wire clk, // Clock
input wire reset,
input wire[11:0] in_read_csr_address,
input wire in_write_valid,
input wire[31:0] in_write_csr_data,
input wire[11:0] in_write_csr_address,
output wire[31:0] out_read_csr_data,
// For instruction retire counting
input wire in_writeback_valid
);
// wire[`NT_M1:0][31:0] thread_ids;
// wire[`NT_M1:0][31:0] warp_ids;
// genvar cur_t;
// for (cur_t = 0; cur_t < `NT; cur_t = cur_t + 1) begin
// assign thread_ids[cur_t] = cur_t;
// end
// genvar cur_tw;
// for (cur_tw = 0; cur_tw < `NT; cur_tw = cur_tw + 1) begin
// assign warp_ids[cur_tw] = {{(31-`NW_M1){1'b0}}, in_read_warp_num};
// end
reg[11:0] csr[1023:0];
reg[63:0] cycle;
reg[63:0] instret;
wire read_cycle;
wire read_cycleh;
wire read_instret;
wire read_instreth;
assign read_cycle = in_read_csr_address == 12'hC00;
assign read_cycleh = in_read_csr_address == 12'hC80;
assign read_instret = in_read_csr_address == 12'hC02;
assign read_instreth = in_read_csr_address == 12'hC82;
// wire thread_select = in_read_csr_address == 12'h20;
// wire warp_select = in_read_csr_address == 12'h21;
// assign out_read_csr_data = thread_select ? thread_ids :
// warp_select ? warp_ids :
// 0;
integer curr_e;
always @(posedge clk or posedge reset) begin
if (reset) begin
for (curr_e = 0; curr_e < 1024; curr_e=curr_e+1) begin
assign csr[curr_e] = 0;
end
cycle <= 0;
instret <= 0;
end else begin
cycle <= cycle + 1;
if (in_write_valid) begin
csr[in_write_csr_address] <= in_write_csr_data[11:0];
end
if (in_writeback_valid) begin
instret <= instret + 1;
end
end
end
assign out_read_csr_data = read_cycle ? cycle[31:0] :
read_cycleh ? cycle[63:32] :
read_instret ? instret[31:0] :
read_instreth ? instret[63:32] :
{{20{1'b0}}, csr[in_read_csr_address]};
endmodule

105
rtl/VX_csr_pipe.v Normal file
View File

@@ -0,0 +1,105 @@
module VX_csr_pipe (
input wire clk, // Clock
input wire reset,
input wire no_slot_csr,
VX_csr_req_inter VX_csr_req,
VX_wb_inter VX_writeback,
VX_csr_wb_inter VX_csr_wb,
output wire stall_gpr_csr
);
wire[`NT_M1:0] valid_s2;
wire[`NW_M1:0] warp_num_s2;
wire[4:0] rd_s2;
wire[1:0] wb_s2;
wire[4:0] alu_op_s2;
wire is_csr_s2;
wire[11:0] csr_address_s2;
wire[31:0] csr_read_data_s2;
wire[31:0] csr_updated_data_s2;
wire[31:0] csr_read_data_unqual;
wire[31:0] csr_read_data;
assign stall_gpr_csr = no_slot_csr && VX_csr_req.is_csr && |(VX_csr_req.valid);
assign csr_read_data = (csr_address_s2 == VX_csr_req.csr_address) ? csr_updated_data_s2 : csr_read_data_unqual;
wire writeback = |VX_writeback.wb_valid;
VX_csr_data VX_csr_data(
.clk (clk),
.reset (reset),
.in_read_csr_address (VX_csr_req.csr_address),
.in_write_valid (is_csr_s2),
.in_write_csr_data (csr_updated_data_s2),
.in_write_csr_address(csr_address_s2),
.out_read_csr_data (csr_read_data_unqual),
.in_writeback_valid (writeback)
);
reg[31:0] csr_updated_data;
always @(*) begin
case(VX_csr_req.alu_op)
`CSR_ALU_RW: csr_updated_data = VX_csr_req.csr_mask;
`CSR_ALU_RS: csr_updated_data = csr_read_data | VX_csr_req.csr_mask;
`CSR_ALU_RC: csr_updated_data = csr_read_data & (32'hFFFFFFFF - VX_csr_req.csr_mask);
default: csr_updated_data = 32'hdeadbeef;
endcase
end
wire zero = 0;
VX_generic_register #(.N(`NT + `NW_M1 + 1 + 5 + 2 + 5 + 12 + 64)) csr_reg_s2 (
.clk (clk),
.reset(reset),
.stall(no_slot_csr),
.flush(zero),
.in ({VX_csr_req.valid, VX_csr_req.warp_num, VX_csr_req.rd, VX_csr_req.wb, VX_csr_req.is_csr, VX_csr_req.csr_address, csr_read_data , csr_updated_data }),
.out ({valid_s2 , warp_num_s2 , rd_s2 , wb_s2 , is_csr_s2 , csr_address_s2 , csr_read_data_s2, csr_updated_data_s2})
);
wire[`NT_M1:0][31:0] final_csr_data;
wire[`NT_M1:0][31:0] thread_ids;
wire[`NT_M1:0][31:0] warp_ids;
wire[`NT_M1:0][31:0] csr_vec_read_data_s2;
genvar cur_t;
for (cur_t = 0; cur_t < `NT; cur_t = cur_t + 1) begin
assign thread_ids[cur_t] = cur_t;
end
genvar cur_tw;
for (cur_tw = 0; cur_tw < `NT; cur_tw = cur_tw + 1) begin
assign warp_ids[cur_tw] = {{(31-`NW_M1){1'b0}}, warp_num_s2};
end
genvar cur_v;
for (cur_v = 0; cur_v < `NT; cur_v = cur_v + 1) begin
assign csr_vec_read_data_s2[cur_v] = csr_read_data_s2;
end
wire thread_select = csr_address_s2 == 12'h20;
wire warp_select = csr_address_s2 == 12'h21;
assign final_csr_data = thread_select ? thread_ids :
warp_select ? warp_ids :
csr_vec_read_data_s2;
assign VX_csr_wb.valid = valid_s2;
assign VX_csr_wb.warp_num = warp_num_s2;
assign VX_csr_wb.rd = rd_s2;
assign VX_csr_wb.wb = wb_s2;
assign VX_csr_wb.csr_result = final_csr_data;
endmodule

3
rtl/VX_decode.v
View File

@@ -119,7 +119,8 @@ module VX_decode(
assign is_auipc = (curr_opcode == `AUIPC_INST);
assign is_csr = (curr_opcode == `SYS_INST) && (func3 != 0);
assign is_csr_immed = (is_csr) && (func3[2] == 1);
assign is_e_inst = (curr_opcode == `SYS_INST) && (func3 == 0);
// assign is_e_inst = (curr_opcode == `SYS_INST) && (func3 == 0);
assign is_e_inst = in_instruction == 32'h00000073;
assign is_gpgpu = (curr_opcode == `GPGPU_INST);

10
rtl/VX_define.v
View File

@@ -12,7 +12,7 @@
// `define SYN 1
// `define ASIC 1
`define SYN_FUNC 1
// `define SYN_FUNC 1
`define NUM_BARRIERS 4
@@ -128,14 +128,16 @@
// `define PARAM
// oooooo
//Cache configurations
//Cache configurations
//Bytes
`define ICACHE_SIZE 1024
`define ICACHE_SIZE 4096
`define ICACHE_WAYS 2
//Bytes
`define ICACHE_BLOCK 16
`define ICACHE_BANKS 1
`define ICACHE_BLOCK 64
`define ICACHE_BANKS 4
`define ICACHE_LOG_NUM_BANKS `CLOG2(`ICACHE_BANKS)
`define ICACHE_NUM_WORDS_PER_BLOCK (`ICACHE_BLOCK / (`ICACHE_BANKS * 4))

19
rtl/VX_gpr_stage.v
View File

@@ -7,6 +7,7 @@ module VX_gpr_stage (
input wire schedule_delay,
input wire memory_delay,
input wire stall_gpr_csr,
output wire gpr_stage_delay,
// inputs
@@ -93,7 +94,7 @@ module VX_gpr_stage (
wire stall_lsu = memory_delay;
wire flush_lsu = schedule_delay && !stall_lsu;
assign gpr_stage_delay = stall_lsu;
assign gpr_stage_delay = stall_lsu || (stall_gpr_csr && VX_bckE_req.is_csr && (|VX_bckE_req.valid));
`ifdef ASIC
wire delayed_lsu_last_cycle;
@@ -166,13 +167,13 @@ module VX_gpr_stage (
assign VX_gpu_inst_req.a_reg_data = real_base_address;
assign VX_gpu_inst_req.rd2 = real_store_data;
VX_generic_register #(.N(`NW_M1 + 1 + `NT + 53)) csr_reg(
VX_generic_register #(.N(`NW_M1 + 1 + `NT + 58)) csr_reg(
.clk (clk),
.reset(reset),
.stall(stall_rest),
.stall(stall_gpr_csr),
.flush(flush_rest),
.in ({VX_csr_req_temp.valid, VX_csr_req_temp.warp_num, VX_csr_req_temp.rd, VX_csr_req_temp.wb, VX_csr_req_temp.is_csr, VX_csr_req_temp.csr_address, VX_csr_req_temp.csr_immed, VX_csr_req_temp.csr_mask}),
.out ({VX_csr_req.valid , VX_csr_req.warp_num , VX_csr_req.rd , VX_csr_req.wb , VX_csr_req.is_csr , VX_csr_req.csr_address , VX_csr_req.csr_immed , VX_csr_req.csr_mask })
.in ({VX_csr_req_temp.valid, VX_csr_req_temp.warp_num, VX_csr_req_temp.rd, VX_csr_req_temp.wb, VX_csr_req_temp.alu_op, VX_csr_req_temp.is_csr, VX_csr_req_temp.csr_address, VX_csr_req_temp.csr_immed, VX_csr_req_temp.csr_mask}),
.out ({VX_csr_req.valid , VX_csr_req.warp_num , VX_csr_req.rd , VX_csr_req.wb , VX_csr_req.alu_op , VX_csr_req.is_csr , VX_csr_req.csr_address , VX_csr_req.csr_immed , VX_csr_req.csr_mask })
);
@@ -208,13 +209,13 @@ module VX_gpr_stage (
.out ({VX_gpu_inst_req.valid , VX_gpu_inst_req.warp_num , VX_gpu_inst_req.is_wspawn , VX_gpu_inst_req.is_tmc , VX_gpu_inst_req.is_split , VX_gpu_inst_req.is_barrier , VX_gpu_inst_req.pc_next , VX_gpu_inst_req.a_reg_data , VX_gpu_inst_req.rd2 })
);
VX_generic_register #(.N(`NW_M1 + 1 + `NT + 53)) csr_reg(
VX_generic_register #(.N(`NW_M1 + 1 + `NT + 58)) csr_reg(
.clk (clk),
.reset(reset),
.stall(stall_rest),
.stall(stall_gpr_csr),
.flush(flush_rest),
.in ({VX_csr_req_temp.valid, VX_csr_req_temp.warp_num, VX_csr_req_temp.rd, VX_csr_req_temp.wb, VX_csr_req_temp.is_csr, VX_csr_req_temp.csr_address, VX_csr_req_temp.csr_immed, VX_csr_req_temp.csr_mask}),
.out ({VX_csr_req.valid , VX_csr_req.warp_num , VX_csr_req.rd , VX_csr_req.wb , VX_csr_req.is_csr , VX_csr_req.csr_address , VX_csr_req.csr_immed , VX_csr_req.csr_mask })
.in ({VX_csr_req_temp.valid, VX_csr_req_temp.warp_num, VX_csr_req_temp.rd, VX_csr_req_temp.wb, VX_csr_req_temp.alu_op, VX_csr_req_temp.is_csr, VX_csr_req_temp.csr_address, VX_csr_req_temp.csr_immed, VX_csr_req_temp.csr_mask}),
.out ({VX_csr_req.valid , VX_csr_req.warp_num , VX_csr_req.rd , VX_csr_req.wb , VX_csr_req.alu_op , VX_csr_req.is_csr , VX_csr_req.csr_address , VX_csr_req.csr_immed , VX_csr_req.csr_mask })
);
`endif

1
rtl/VX_inst_multiplex.v
View File

@@ -82,6 +82,7 @@ module VX_inst_multiplex (
assign VX_csr_req.warp_num = VX_bckE_req.warp_num;
assign VX_csr_req.rd = VX_bckE_req.rd;
assign VX_csr_req.wb = VX_bckE_req.wb;
assign VX_csr_req.alu_op = VX_bckE_req.alu_op;
assign VX_csr_req.is_csr = VX_bckE_req.is_csr;
assign VX_csr_req.csr_address = VX_bckE_req.csr_address;
assign VX_csr_req.csr_immed = VX_bckE_req.csr_immed;

11
rtl/VX_writeback.v
View File

@@ -14,7 +14,8 @@ module VX_writeback (
// Actual WB to GPR
VX_wb_inter VX_writeback_inter,
output wire no_slot_mem
output wire no_slot_mem,
output wire no_slot_csr
);
@@ -26,6 +27,7 @@ module VX_writeback (
assign no_slot_mem = mem_wb && (exec_wb || csr_wb);
assign no_slot_csr = csr_wb && (exec_wb);
assign VX_writeback_tempp.write_data = exec_wb ? VX_inst_exec_wb.alu_result :
csr_wb ? VX_csr_wb.csr_result :
@@ -85,6 +87,13 @@ module VX_writeback (
.out ({use_wb_data , VX_writeback_inter.wb_valid, VX_writeback_inter.rd, VX_writeback_inter.wb, VX_writeback_inter.wb_warp_num, VX_writeback_inter.wb_pc})
);
reg[31:0] last_data_wb;
always @(posedge clk) begin
if ((|VX_writeback_inter.wb_valid) && (VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd == 28)) begin
last_data_wb <= use_wb_data[0];
end
end
`ifdef SYN
assign VX_writeback_inter.write_data = prev_is_mem ? VX_writeback_tempp.write_data : use_wb_data;
`else

20
rtl/Vortex.v
View File

@@ -44,6 +44,26 @@ module Vortex
);
reg[31:0] icache_banks = `ICACHE_BANKS;
reg[31:0] icache_num_words_per_block = `ICACHE_NUM_WORDS_PER_BLOCK;
reg[31:0] dcache_banks = `DCACHE_BANKS;
reg[31:0] dcache_num_words_per_block = `DCACHE_NUM_WORDS_PER_BLOCK;
reg[31:0] number_threads = `NT;
reg[31:0] number_warps = `NW;
always @(posedge clk) begin
icache_banks <= icache_banks;
icache_num_words_per_block <= icache_num_words_per_block;
dcache_banks <= dcache_banks;
dcache_num_words_per_block <= dcache_num_words_per_block;
number_threads <= number_threads;
number_warps <= number_warps;
end
wire memory_delay;
wire gpr_stage_delay;

2
rtl/interfaces/VX_csr_req_inter.v
View File

@@ -11,7 +11,7 @@ interface VX_csr_req_inter ();
wire[`NW_M1:0] warp_num;
wire[4:0] rd;
wire[1:0] wb;
wire[4:0] alu_op;
wire is_csr;
wire[11:0] csr_address;
wire csr_immed;

4
rtl/simulate/VX_define.h
View File

@@ -3,8 +3,8 @@
#define NW 8
// #define CACHE_NUM_BANKS 8
// #define CACHE_WORDS_PER_BLOCK 4
#define CACHE_NUM_BANKS 8
#define CACHE_WORDS_PER_BLOCK 4
#define R_INST 51
#define L_INST 3

5
rtl/simulate/ram.h
View File

@@ -167,11 +167,12 @@ uint32_t hToI(char *c, uint32_t size) {
void loadHexImpl(char * path,RAM* mem) {
void loadHexImpl(const char *path, RAM* mem) {
mem->clear();
FILE *fp = fopen(&path[0], "r");
FILE *fp = fopen(path, "r");
if(fp == 0){
printf("Path not found %s\n", path);
return;
// std::cout << path << " not found" << std::endl;
}
//Preload 0x0 <-> 0x80000000 jumps

141
rtl/simulate/test_bench.cpp
View File

@@ -12,83 +12,94 @@ int main(int argc, char **argv)
Verilated::traceEverOn(true);
#define ALL_TESTS
#ifdef ALL_TESTS
bool passed = true;
std::string tests[NUM_TESTS] = {
"../../emulator/riscv_tests/rv32ui-p-add.hex",
"../../emulator/riscv_tests/rv32ui-p-addi.hex",
"../../emulator/riscv_tests/rv32ui-p-and.hex",
"../../emulator/riscv_tests/rv32ui-p-andi.hex",
"../../emulator/riscv_tests/rv32ui-p-auipc.hex",
"../../emulator/riscv_tests/rv32ui-p-beq.hex",
"../../emulator/riscv_tests/rv32ui-p-bge.hex",
"../../emulator/riscv_tests/rv32ui-p-bgeu.hex",
"../../emulator/riscv_tests/rv32ui-p-blt.hex",
"../../emulator/riscv_tests/rv32ui-p-bltu.hex",
"../../emulator/riscv_tests/rv32ui-p-bne.hex",
"../../emulator/riscv_tests/rv32ui-p-jal.hex",
"../../emulator/riscv_tests/rv32ui-p-jalr.hex",
"../../emulator/riscv_tests/rv32ui-p-lb.hex",
"../../emulator/riscv_tests/rv32ui-p-lbu.hex",
"../../emulator/riscv_tests/rv32ui-p-lh.hex",
"../../emulator/riscv_tests/rv32ui-p-lhu.hex",
"../../emulator/riscv_tests/rv32ui-p-lui.hex",
"../../emulator/riscv_tests/rv32ui-p-lw.hex",
"../../emulator/riscv_tests/rv32ui-p-or.hex",
"../../emulator/riscv_tests/rv32ui-p-ori.hex",
"../../emulator/riscv_tests/rv32ui-p-sb.hex",
"../../emulator/riscv_tests/rv32ui-p-sh.hex",
"../../emulator/riscv_tests/rv32ui-p-simple.hex",
"../../emulator/riscv_tests/rv32ui-p-sll.hex",
"../../emulator/riscv_tests/rv32ui-p-slli.hex",
"../../emulator/riscv_tests/rv32ui-p-slt.hex",
"../../emulator/riscv_tests/rv32ui-p-slti.hex",
"../../emulator/riscv_tests/rv32ui-p-sltiu.hex",
"../../emulator/riscv_tests/rv32ui-p-sltu.hex",
"../../emulator/riscv_tests/rv32ui-p-sra.hex",
"../../emulator/riscv_tests/rv32ui-p-srai.hex",
"../../emulator/riscv_tests/rv32ui-p-srl.hex",
"../../emulator/riscv_tests/rv32ui-p-srli.hex",
"../../emulator/riscv_tests/rv32ui-p-sub.hex",
"../../emulator/riscv_tests/rv32ui-p-sw.hex",
"../../emulator/riscv_tests/rv32ui-p-xor.hex",
"../../emulator/riscv_tests/rv32ui-p-xori.hex",
"../../emulator/riscv_tests/rv32um-p-div.hex",
"../../emulator/riscv_tests/rv32um-p-divu.hex",
"../../emulator/riscv_tests/rv32um-p-mul.hex",
"../../emulator/riscv_tests/rv32um-p-mulh.hex",
"../../emulator/riscv_tests/rv32um-p-mulhsu.hex",
"../../emulator/riscv_tests/rv32um-p-mulhu.hex",
"../../emulator/riscv_tests/rv32um-p-rem.hex",
"../../emulator/riscv_tests/rv32um-p-remu.hex"
};
// bool passed = true;
// std::string tests[NUM_TESTS] = {
// "../../emulator/riscv_tests/rv32ui-p-add.hex",
// "../../emulator/riscv_tests/rv32ui-p-addi.hex",
// "../../emulator/riscv_tests/rv32ui-p-and.hex",
// "../../emulator/riscv_tests/rv32ui-p-andi.hex",
// "../../emulator/riscv_tests/rv32ui-p-auipc.hex",
// "../../emulator/riscv_tests/rv32ui-p-beq.hex",
// "../../emulator/riscv_tests/rv32ui-p-bge.hex",
// "../../emulator/riscv_tests/rv32ui-p-bgeu.hex",
// "../../emulator/riscv_tests/rv32ui-p-blt.hex",
// "../../emulator/riscv_tests/rv32ui-p-bltu.hex",
// "../../emulator/riscv_tests/rv32ui-p-bne.hex",
// "../../emulator/riscv_tests/rv32ui-p-jal.hex",
// "../../emulator/riscv_tests/rv32ui-p-jalr.hex",
// "../../emulator/riscv_tests/rv32ui-p-lb.hex",
// "../../emulator/riscv_tests/rv32ui-p-lbu.hex",
// "../../emulator/riscv_tests/rv32ui-p-lh.hex",
// "../../emulator/riscv_tests/rv32ui-p-lhu.hex",
// "../../emulator/riscv_tests/rv32ui-p-lui.hex",
// "../../emulator/riscv_tests/rv32ui-p-lw.hex",
// "../../emulator/riscv_tests/rv32ui-p-or.hex",
// "../../emulator/riscv_tests/rv32ui-p-ori.hex",
// "../../emulator/riscv_tests/rv32ui-p-sb.hex",
// "../../emulator/riscv_tests/rv32ui-p-sh.hex",
// "../../emulator/riscv_tests/rv32ui-p-simple.hex",
// "../../emulator/riscv_tests/rv32ui-p-sll.hex",
// "../../emulator/riscv_tests/rv32ui-p-slli.hex",
// "../../emulator/riscv_tests/rv32ui-p-slt.hex",
// "../../emulator/riscv_tests/rv32ui-p-slti.hex",
// "../../emulator/riscv_tests/rv32ui-p-sltiu.hex",
// "../../emulator/riscv_tests/rv32ui-p-sltu.hex",
// "../../emulator/riscv_tests/rv32ui-p-sra.hex",
// "../../emulator/riscv_tests/rv32ui-p-srai.hex",
// "../../emulator/riscv_tests/rv32ui-p-srl.hex",
// "../../emulator/riscv_tests/rv32ui-p-srli.hex",
// "../../emulator/riscv_tests/rv32ui-p-sub.hex",
// "../../emulator/riscv_tests/rv32ui-p-sw.hex",
// "../../emulator/riscv_tests/rv32ui-p-xor.hex",
// "../../emulator/riscv_tests/rv32ui-p-xori.hex",
// "../../emulator/riscv_tests/rv32um-p-div.hex",
// "../../emulator/riscv_tests/rv32um-p-divu.hex",
// "../../emulator/riscv_tests/rv32um-p-mul.hex",
// "../../emulator/riscv_tests/rv32um-p-mulh.hex",
// "../../emulator/riscv_tests/rv32um-p-mulhsu.hex",
// "../../emulator/riscv_tests/rv32um-p-mulhu.hex",
// "../../emulator/riscv_tests/rv32um-p-rem.hex",
// "../../emulator/riscv_tests/rv32um-p-remu.hex"
// };
for (std::string s : tests) {
Vortex v;
// for (int ii = 0; ii < NUM_TESTS; ii++)
// // for (int ii = 5; ii < 6; ii++)
// {
// std::cout << "TESTING: " << tests[ii] << '\n';
// Vortex v;
// bool curr = v.simulate(tests[ii]);
std::cerr << s << std::endl;
// if ( curr) std::cerr << GREEN << "Test Passed: " << tests[ii] << std::endl;
// if (!curr) std::cerr << RED << "Test Failed: " << tests[ii] << std::endl;
// passed = passed && curr;
bool curr = v.simulate(s);
if ( curr) std::cerr << GREEN << "Test Passed: " << s << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << s << std::endl;
passed = passed && curr;
}
// std::cerr << DEFAULT;
// }
if( passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n";
if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n";
// if( passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n";
// if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n";
return !passed;
#else
// char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex";
char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex";
Vortex v;
char testing[] = "../../kernel/vortex_test.hex";
const char *testing;
if (argc >= 2) {
testing = argv[1];
} else {
testing = "../../kernel/vortex_test.hex";
}
std::cerr << testing << std::endl;
bool curr = v.simulate(testing);
if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << testing << std::endl;
return 0;
return !curr;
#endif
}

202
rtl/simulate/test_bench.h
View File

@@ -46,8 +46,10 @@ class Vortex
VVortex * vortex;
unsigned start_pc;
bool refill;
unsigned refill_addr;
bool refill_d;
unsigned refill_addr_d;
bool refill_i;
unsigned refill_addr_i;
long int curr_cycle;
bool stop;
bool unit_test;
@@ -100,7 +102,7 @@ Vortex::~Vortex()
void Vortex::ProcessFile(void)
{
loadHexImpl("../../kernel/vortex_test.hex", &this->ram);
loadHexImpl(this->instruction_file_name.c_str(), &this->ram);
}
void Vortex::print_stats(bool cycle_test)
@@ -154,38 +156,66 @@ void Vortex::print_stats(bool cycle_test)
bool Vortex::ibus_driver()
{
////////////////////// IBUS //////////////////////
unsigned new_PC;
bool stop = false;
uint32_t curr_inst = 0;
vortex->i_m_ready_i = false;
curr_inst = 0xdeadbeef;
new_PC = vortex->icache_request_pc_address;
ram.getWord(new_PC, &curr_inst);
vortex->icache_response_instruction = curr_inst;
// std::cout << std::hex << "IReq: " << vortex->icache_request_pc_address << "\tResp: " << curr_inst << "\n";
// printf("\n\n---------------------------------------------\n(%x) Inst: %x\n", new_PC, curr_inst);
// printf("\n");
////////////////////// IBUS //////////////////////
////////////////////// STATS //////////////////////
if (((((unsigned int)curr_inst) != 0) && (((unsigned int)curr_inst) != 0xffffffff)))
{
++stats_dynamic_inst;
stop = false;
} else
{
// printf("Ibus requesting stop: %x\n", curr_inst);
stop = true;
// int dcache_num_words_per_block
if (refill_i)
{
refill_i = false;
vortex->i_m_ready_i = true;
for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__icache_banks; curr_bank++)
{
for (int curr_word = 0; curr_word < vortex->Vortex__DOT__icache_num_words_per_block; curr_word++)
{
unsigned curr_index = (curr_word * vortex->Vortex__DOT__icache_banks) + curr_bank;
unsigned curr_addr = refill_addr_i + (4*curr_index);
unsigned curr_value;
ram.getWord(curr_addr, &curr_value);
vortex->i_m_readdata_i[curr_bank][curr_word] = curr_value;
}
}
}
else
{
if (vortex->o_m_valid_i)
{
if (vortex->o_m_read_or_write_i)
{
// fprintf(stderr, "++++++++++++++++++++++++++++++++\n");
unsigned base_addr = vortex->o_m_evict_addr_i;
for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__icache_banks; curr_bank++)
{
for (int curr_word = 0; curr_word < vortex->Vortex__DOT__icache_num_words_per_block; curr_word++)
{
unsigned curr_index = (curr_word * vortex->Vortex__DOT__icache_banks) + curr_bank;
unsigned curr_addr = base_addr + (4*curr_index);
unsigned curr_value = vortex->o_m_writedata_i[curr_bank][curr_word];
ram.writeWord( curr_addr, &curr_value);
}
}
}
// Respond next cycle
refill_i = true;
refill_addr_i = vortex->o_m_read_addr_i;
}
}
}
return stop;
return false;
}
@@ -197,6 +227,7 @@ void Vortex::io_handler()
char c = (char) data_write;
std::cerr << c;
// std::cout << c;
}
}
@@ -204,75 +235,62 @@ void Vortex::io_handler()
bool Vortex::dbus_driver()
{
// printf("****************************\n");
vortex->i_m_ready_d = false;
vortex->i_m_ready = 0;
for (int i = 0; i < CACHE_NUM_BANKS; i++)
{
for (int j = 0; j < CACHE_WORDS_PER_BLOCK; j++)
// int dcache_num_words_per_block
if (refill_d)
{
vortex->i_m_readdata[i][j] = 0;
}
}
refill_d = false;
vortex->i_m_ready_d = true;
if (this->refill)
{
this->refill = false;
vortex->i_m_ready = 1;
for (int curr_e = 0; curr_e < (CACHE_NUM_BANKS*CACHE_WORDS_PER_BLOCK); curr_e++)
{
unsigned new_addr = this->refill_addr + (4*curr_e);
unsigned addr_without_byte = new_addr >> 2;
unsigned bank_num = addr_without_byte & 0x7;
unsigned addr_wihtout_bank = addr_without_byte >> 3;
unsigned offset_num = addr_wihtout_bank & 0x3;
unsigned value;
ram.getWord(new_addr, &value);
// printf("-------- (%x) i_m_readdata[%d][%d] (%d) = %d\n", new_addr, bank_num, offset_num, curr_e, value);
vortex->i_m_readdata[bank_num][offset_num] = value;
}
}
else
{
if (vortex->o_m_valid)
{
// printf("Valid o_m_valid\n");
if (vortex->o_m_read_or_write)
for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__dcache_banks; curr_bank++)
{
// printf("Valid write\n");
for (int curr_e = 0; curr_e < (CACHE_NUM_BANKS*CACHE_WORDS_PER_BLOCK); curr_e++)
for (int curr_word = 0; curr_word < vortex->Vortex__DOT__dcache_num_words_per_block; curr_word++)
{
unsigned new_addr = vortex->o_m_evict_addr + (4*curr_e);
unsigned curr_index = (curr_word * vortex->Vortex__DOT__dcache_banks) + curr_bank;
unsigned curr_addr = refill_addr_d + (4*curr_index);
unsigned curr_value;
ram.getWord(curr_addr, &curr_value);
unsigned addr_without_byte = new_addr >> 2;
unsigned bank_num = addr_without_byte & 0x7;
unsigned addr_wihtout_bank = addr_without_byte >> 3;
unsigned offset_num = addr_wihtout_bank & 0x3;
vortex->i_m_readdata_d[curr_bank][curr_word] = curr_value;
unsigned new_value = vortex->o_m_writedata[bank_num][offset_num];
ram.writeWord( new_addr, &new_value);
// printf("+++++++ (%x) writeback[%d][%d] (%d) = %d\n", new_addr, bank_num, offset_num, curr_e, new_value);
// printf("+++++++ (%x) i_m_readdata[%d][%d] (%d) = %d\n", new_addr, bank_num, offset_num, curr_e, value);
}
}
// Respond next cycle
this->refill = true;
this->refill_addr = vortex->o_m_read_addr;
}
else
{
if (vortex->o_m_valid_d)
{
if (vortex->o_m_read_or_write_d)
{
// fprintf(stderr, "++++++++++++++++++++++++++++++++\n");
unsigned base_addr = vortex->o_m_evict_addr_d;
for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__dcache_banks; curr_bank++)
{
for (int curr_word = 0; curr_word < vortex->Vortex__DOT__dcache_num_words_per_block; curr_word++)
{
unsigned curr_index = (curr_word * vortex->Vortex__DOT__dcache_banks) + curr_bank;
unsigned curr_addr = base_addr + (4*curr_index);
unsigned curr_value = vortex->o_m_writedata_d[curr_bank][curr_word];
ram.writeWord( curr_addr, &curr_value);
}
}
}
// Respond next cycle
refill_d = true;
refill_addr_d = vortex->o_m_read_addr_d;
}
}
}
@@ -397,7 +415,9 @@ bool Vortex::simulate(std::string file_to_simulate)
std::cerr << "New Total Cycles: " << (this->stats_total_cycles) << "\n";
// int status = (unsigned int) vortex->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[28][0] & 0xf;
int status = (unsigned int) vortex->Vortex__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb & 0xf;
// std::cout << "Last wb: " << std::hex << ((unsigned int) vortex->Vortex__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb) << "\n";
// std::cout << "Something: " << result << '\n';
@@ -408,6 +428,6 @@ bool Vortex::simulate(std::string file_to_simulate)
// return (status == 1);
return (1 == 1);
return (status == 1);
// return (1 == 1);
}