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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-20 12:09:30 -04:00
parent e8072bab77
commit e8a4923eb4
53 changed files with 79 additions and 1988 deletions
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2
hw/syn/yosys/diagram.ys
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@@ -1,5 +1,5 @@
# load design
read_verilog -sv -I../../rtl -I../../rtl/interfaces -I../../rtl/cache -I../../rtl/generic_cache -I../../rtl/shared_memory -I../../rtl/pipe_regs -I../../rtl/compat ../../rtl/Vortex.v
read_verilog -sv -I../../rtl -I../../rtl/libs -I../../rtl/interfaces -I../../rtl/cache -I../../rtl/shared_memory -I../../rtl/pipe_regs ../../rtl/Vortex.v
# dump diagram
show

2
hw/syn/yosys/synthesis.ys
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@@ -1,5 +1,5 @@
# load design
read_verilog -sv -I../../rtl -I../../rtl/interfaces -I../../rtl/cache -I../../rtl/generic_cache -I../../rtl/shared_memory -I../../rtl/pipe_regs -I../../rtl/compat ../../rtl/Vortex.v
read_verilog -sv -I../../rtl -I../../rtl/libs -I../../rtl/interfaces -I../../rtl/cache -I../../rtl/shared_memory -I../../rtl/pipe_regs ../../rtl/Vortex.v
# high-level synthesis
proc; opt; fsm;; memory -nomap; opt