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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-20 12:09:30 -04:00
parent e8072bab77
commit e8a4923eb4
53 changed files with 79 additions and 1988 deletions
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2
hw/syn/quartus/top/Makefile
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@@ -57,7 +57,7 @@ smart.log: $(PROJECT_FILES)
# Project initialization
$(PROJECT_FILES):
$(QUARTUS_ROOT)/quartus/bin/quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc vortex.sdc -inc "..;../interfaces;../pipe_regs;../cache;../generic_cache;../shared_memory;../compat"
$(QUARTUS_ROOT)/quartus/bin/quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc vortex.sdc -inc "..;../libs;../interfaces;../pipe_regs;../cache;../shared_memory"
syn.chg:
$(STAMP) syn.chg

2
hw/syn/quartus/vx_cache/Makefile
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@@ -1,6 +1,6 @@
PROJECT = VX_cache
TOP_LEVEL_ENTITY = VX_cache
SRC_FILE = ../../../rtl/generic_cache/VX_cache.v
SRC_FILE = ../../../rtl/cache/VX_cache.v
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
QUARTUS_ROOT ?= /tools/reconfig/intel/18.0