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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-20 12:09:30 -04:00
parent e8072bab77
commit e8a4923eb4
53 changed files with 79 additions and 1988 deletions
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2
hw/rtl/interfaces/VX_gpu_dcache_dram_req_if.v
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@@ -1,7 +1,7 @@
`ifndef VX_GPU_DRAM_DCACHE_REQ
`define VX_GPU_DRAM_DCACHE_REQ
`include "../generic_cache/VX_cache_config.vh"
`include "../cache/VX_cache_config.vh"
interface VX_gpu_dcache_dram_req_if #(
parameter BANK_LINE_WORDS = 2

2
hw/rtl/interfaces/VX_gpu_dcache_dram_rsp_if.v
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@@ -1,7 +1,7 @@
`ifndef VX_GPU_DRAM_DCACHE_RSP
`define VX_GPU_DRAM_DCACHE_RSP
`include "../generic_cache/VX_cache_config.vh"
`include "../cache/VX_cache_config.vh"
interface VX_gpu_dcache_dram_rsp_if #(
parameter BANK_LINE_WORDS = 2

2
hw/rtl/interfaces/VX_gpu_dcache_req_if.v
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@@ -1,7 +1,7 @@
`ifndef VX_GPU_DCACHE_REQ
`define VX_GPU_DCACHE_REQ
`include "../generic_cache/VX_cache_config.vh"
`include "../cache/VX_cache_config.vh"
interface VX_gpu_dcache_req_if #(
parameter NUM_REQUESTS = 32

2
hw/rtl/interfaces/VX_gpu_dcache_rsp_if.v
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@@ -1,7 +1,7 @@
`ifndef VX_GPU_DCACHE_RSP
`define VX_GPU_DCACHE_RSP
`include "../generic_cache/VX_cache_config.vh"
`include "../cache/VX_cache_config.vh"
interface VX_gpu_dcache_rsp_if #(
parameter NUM_REQUESTS = 32

2
hw/rtl/interfaces/VX_gpu_dcache_snp_req_if.v
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@@ -1,7 +1,7 @@
`ifndef VX_GPU_SNP_REQ
`define VX_GPU_SNP_REQ
`include "../generic_cache/VX_cache_config.vh"
`include "../cache/VX_cache_config.vh"
interface VX_gpu_dcache_snp_req_if ();
// Snoop Req

2
hw/rtl/interfaces/VX_gpu_snp_req_rsp_if.v
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@@ -1,7 +1,7 @@
`ifndef VX_GPU_SNP_REQ_RSP
`define VX_GPU_SNP_REQ_RSP
`include "../generic_cache/VX_cache_config.vh"
`include "../cache/VX_cache_config.vh"
interface VX_gpu_snp_req_rsp_if ();