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FPU area optimization sharing fmadd hard block

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This commit is contained in:
Blaise Tine
2020-12-27 17:31:10 -08:00
parent 25df233005
commit e83c4638a0
15 changed files with 111 additions and 856 deletions
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67
hw/rtl/fp_cores/altera/arria10/acl_fadd.sv
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@@ -1,67 +0,0 @@
// -------------------------------------------------------------------------
// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273)
// Quartus Prime development tool and MATLAB/Simulink Interface
//
// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly
// subject to the terms and conditions of the Intel FPGA Software License
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by Intel
// and sold by Intel or its authorized distributors. Please refer to the
// applicable agreement for further details.
// ---------------------------------------------------------------------------
// SystemVerilog created from acl_fadd
// SystemVerilog created on Sun Dec 27 09:47:20 2020
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module acl_fadd (
input wire [31:0] a,
input wire [31:0] b,
input wire [0:0] en,
output wire [31:0] q,
input wire clk,
input wire areset
);
wire [31:0] fpAddTest_impl_ax0;
wire [31:0] fpAddTest_impl_ay0;
wire [31:0] fpAddTest_impl_q0;
wire fpAddTest_impl_reset0;
wire fpAddTest_impl_fpAddTest_impl_ena0;
// fpAddTest_impl(FPCOLUMN,5)@0
// out q0@3
assign fpAddTest_impl_ax0 = b;
assign fpAddTest_impl_ay0 = a;
assign fpAddTest_impl_reset0 = areset;
assign fpAddTest_impl_fpAddTest_impl_ena0 = en[0];
twentynm_fp_mac #(
.operation_mode("sp_add"),
.ax_clock("0"),
.ay_clock("0"),
.adder_input_clock("0"),
.output_clock("0")
) fpAddTest_impl_DSP0 (
.aclr({ fpAddTest_impl_reset0, fpAddTest_impl_reset0 }),
.clk({1'b0,1'b0,clk}),
.ena({ 1'b0, 1'b0, fpAddTest_impl_fpAddTest_impl_ena0 }),
.ax(fpAddTest_impl_ax0),
.ay(fpAddTest_impl_ay0),
.resulta(fpAddTest_impl_q0),
.accumulate(),
.az(),
.chainin(),
.chainout()
);
// xOut(GPOUT,4)@3
assign q = fpAddTest_impl_q0;
endmodule

75
hw/rtl/fp_cores/altera/arria10/acl_fmsub.sv
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@@ -1,75 +0,0 @@
// -------------------------------------------------------------------------
// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273)
// Quartus Prime development tool and MATLAB/Simulink Interface
//
// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly
// subject to the terms and conditions of the Intel FPGA Software License
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by Intel
// and sold by Intel or its authorized distributors. Please refer to the
// applicable agreement for further details.
// ---------------------------------------------------------------------------
// SystemVerilog created from acl_fmsub
// SystemVerilog created on Sun Dec 27 07:07:02 2020
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module acl_fmsub (
input wire [31:0] a,
input wire [31:0] b,
input wire [31:0] c,
input wire [0:0] en,
output wire [31:0] q,
input wire clk,
input wire areset
);
wire [31:0] fpMultAddTest_impl_ax0;
wire [31:0] fpMultAddTest_impl_ay0;
wire [31:0] fpMultAddTest_impl_az0;
wire [31:0] fpMultAddTest_impl_q0;
wire fpMultAddTest_impl_reset0;
wire fpMultAddTest_impl_fpMultAddTest_impl_ena0;
// fpMultAddTest_impl(FPCOLUMN,5)@0
// out q0@4
assign fpMultAddTest_impl_ax0 = c;
assign fpMultAddTest_impl_ay0 = b;
assign fpMultAddTest_impl_az0 = a;
assign fpMultAddTest_impl_reset0 = areset;
assign fpMultAddTest_impl_fpMultAddTest_impl_ena0 = en[0];
twentynm_fp_mac #(
.operation_mode("sp_mult_add"),
.adder_subtract("true"),
.use_chainin("false"),
.ax_clock("0"),
.ay_clock("0"),
.az_clock("0"),
.mult_pipeline_clock("0"),
.adder_input_clock("0"),
.ax_chainin_pl_clock("0"),
.output_clock("0")
) fpMultAddTest_impl_DSP0 (
.aclr({ fpMultAddTest_impl_reset0, fpMultAddTest_impl_reset0 }),
.clk({1'b0,1'b0,clk}),
.ena({ 1'b0, 1'b0, fpMultAddTest_impl_fpMultAddTest_impl_ena0 }),
.ax(fpMultAddTest_impl_ax0),
.ay(fpMultAddTest_impl_ay0),
.az(fpMultAddTest_impl_az0),
.resulta(fpMultAddTest_impl_q0),
.accumulate(),
.chainin(),
.chainout()
);
// xOut(GPOUT,4)@4
assign q = fpMultAddTest_impl_q0;
endmodule

67
hw/rtl/fp_cores/altera/arria10/acl_fmul.sv
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@@ -1,67 +0,0 @@
// -------------------------------------------------------------------------
// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273)
// Quartus Prime development tool and MATLAB/Simulink Interface
//
// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly
// subject to the terms and conditions of the Intel FPGA Software License
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by Intel
// and sold by Intel or its authorized distributors. Please refer to the
// applicable agreement for further details.
// ---------------------------------------------------------------------------
// SystemVerilog created from acl_fmul
// SystemVerilog created on Sun Dec 27 09:47:20 2020
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module acl_fmul (
input wire [31:0] a,
input wire [31:0] b,
input wire [0:0] en,
output wire [31:0] q,
input wire clk,
input wire areset
);
wire [31:0] fpMulTest_impl_ay0;
wire [31:0] fpMulTest_impl_az0;
wire [31:0] fpMulTest_impl_q0;
wire fpMulTest_impl_reset0;
wire fpMulTest_impl_fpMulTest_impl_ena0;
// fpMulTest_impl(FPCOLUMN,5)@0
// out q0@3
assign fpMulTest_impl_ay0 = b;
assign fpMulTest_impl_az0 = a;
assign fpMulTest_impl_reset0 = areset;
assign fpMulTest_impl_fpMulTest_impl_ena0 = en[0];
twentynm_fp_mac #(
.operation_mode("sp_mult"),
.ay_clock("0"),
.az_clock("0"),
.mult_pipeline_clock("0"),
.output_clock("0")
) fpMulTest_impl_DSP0 (
.aclr({ fpMulTest_impl_reset0, fpMulTest_impl_reset0 }),
.clk({1'b0,1'b0,clk}),
.ena({ 1'b0, 1'b0, fpMulTest_impl_fpMulTest_impl_ena0 }),
.ay(fpMulTest_impl_ay0),
.az(fpMulTest_impl_az0),
.resulta(fpMulTest_impl_q0),
.accumulate(),
.ax(),
.chainin(),
.chainout()
);
// xOut(GPOUT,4)@3
assign q = fpMulTest_impl_q0;
endmodule

68
hw/rtl/fp_cores/altera/arria10/acl_fsub.sv
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@@ -1,68 +0,0 @@
// -------------------------------------------------------------------------
// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273)
// Quartus Prime development tool and MATLAB/Simulink Interface
//
// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly
// subject to the terms and conditions of the Intel FPGA Software License
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by Intel
// and sold by Intel or its authorized distributors. Please refer to the
// applicable agreement for further details.
// ---------------------------------------------------------------------------
// SystemVerilog created from acl_fsub
// SystemVerilog created on Sun Dec 27 09:47:20 2020
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module acl_fsub (
input wire [31:0] a,
input wire [31:0] b,
input wire [0:0] en,
output wire [31:0] q,
input wire clk,
input wire areset
);
wire [31:0] fpSubTest_impl_ax0;
wire [31:0] fpSubTest_impl_ay0;
wire [31:0] fpSubTest_impl_q0;
wire fpSubTest_impl_reset0;
wire fpSubTest_impl_fpSubTest_impl_ena0;
// fpSubTest_impl(FPCOLUMN,5)@0
// out q0@3
assign fpSubTest_impl_ax0 = b;
assign fpSubTest_impl_ay0 = a;
assign fpSubTest_impl_reset0 = areset;
assign fpSubTest_impl_fpSubTest_impl_ena0 = en[0];
twentynm_fp_mac #(
.operation_mode("sp_add"),
.adder_subtract("true"),
.ax_clock("0"),
.ay_clock("0"),
.adder_input_clock("0"),
.output_clock("0")
) fpSubTest_impl_DSP0 (
.aclr({ fpSubTest_impl_reset0, fpSubTest_impl_reset0 }),
.clk({1'b0,1'b0,clk}),
.ena({ 1'b0, 1'b0, fpSubTest_impl_fpSubTest_impl_ena0 }),
.ax(fpSubTest_impl_ax0),
.ay(fpSubTest_impl_ay0),
.resulta(fpSubTest_impl_q0),
.accumulate(),
.az(),
.chainin(),
.chainout()
);
// xOut(GPOUT,4)@3
assign q = fpSubTest_impl_q0;
endmodule

3
hw/rtl/fp_cores/altera/arria10/acl_gen.sh
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@@ -18,9 +18,6 @@ FBITS="f$(($EXP_BITS + $MAN_BITS + 1))"
echo Generating IP cores for $FBITS
{
$CMD -name "$PREFIX"_fadd -frequency 250 FPAdd $EXP_BITS $MAN_BITS
$CMD -name "$PREFIX"_fsub -frequency 250 FPSub $EXP_BITS $MAN_BITS
$CMD -name "$PREFIX"_fmul -frequency 250 FPMul $EXP_BITS $MAN_BITS
$CMD -name "$PREFIX"_fmadd -frequency 250 FPMultAdd $EXP_BITS $MAN_BITS
$CMD -name "$PREFIX"_fdiv -frequency 250 FPDiv $EXP_BITS $MAN_BITS 0
$CMD -name "$PREFIX"_fsqrt -frequency 250 FPSqrt $EXP_BITS $MAN_BITS

68
hw/rtl/fp_cores/altera/stratix10/acl_fadd.sv
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@@ -1,68 +0,0 @@
// -------------------------------------------------------------------------
// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277)
// Quartus Prime development tool and MATLAB/Simulink Interface
//
// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly
// subject to the terms and conditions of the Intel FPGA Software License
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by Intel
// and sold by Intel or its authorized distributors. Please refer to the
// applicable agreement for further details.
// ---------------------------------------------------------------------------
// SystemVerilog created from acl_fadd
// SystemVerilog created on Sun Dec 27 09:48:57 2020
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module acl_fadd (
input wire [31:0] a,
input wire [31:0] b,
input wire [0:0] en,
output wire [31:0] q,
input wire clk,
input wire areset
);
wire fpAddTest_impl_reset0;
wire fpAddTest_impl_ena0;
wire [31:0] fpAddTest_impl_ax0;
wire [31:0] fpAddTest_impl_ay0;
wire [31:0] fpAddTest_impl_q0;
// fpAddTest_impl(FPCOLUMN,5)@0
// out q0@3
assign fpAddTest_impl_ax0 = b;
assign fpAddTest_impl_ay0 = a;
assign fpAddTest_impl_reset0 = areset;
assign fpAddTest_impl_ena0 = en[0] | fpAddTest_impl_reset0;
fourteennm_fp_mac #(
.operation_mode("sp_add"),
.ax_clock("0"),
.ay_clock("0"),
.adder_input_clock("0"),
.output_clock("0"),
.clear_type("sclr")
) fpAddTest_impl_DSP0 (
.clk({1'b0,1'b0,clk}),
.ena({ 1'b0, 1'b0, fpAddTest_impl_ena0 }),
.clr({ fpAddTest_impl_reset0, fpAddTest_impl_reset0 }),
.ax(fpAddTest_impl_ax0),
.ay(fpAddTest_impl_ay0),
.resulta(fpAddTest_impl_q0),
.accumulate(),
.az(),
.chainin(),
.chainout()
);
// xOut(GPOUT,4)@3
assign q = fpAddTest_impl_q0;
endmodule

75
hw/rtl/fp_cores/altera/stratix10/acl_fmsub.sv
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@@ -1,75 +0,0 @@
// -------------------------------------------------------------------------
// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277)
// Quartus Prime development tool and MATLAB/Simulink Interface
//
// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly
// subject to the terms and conditions of the Intel FPGA Software License
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by Intel
// and sold by Intel or its authorized distributors. Please refer to the
// applicable agreement for further details.
// ---------------------------------------------------------------------------
// SystemVerilog created from acl_fmsub
// SystemVerilog created on Sun Dec 27 07:06:39 2020
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module acl_fmsub (
input wire [31:0] a,
input wire [31:0] b,
input wire [31:0] c,
input wire [0:0] en,
output wire [31:0] q,
input wire clk,
input wire areset
);
wire fpMultAddTest_impl_reset0;
wire fpMultAddTest_impl_ena0;
wire [31:0] fpMultAddTest_impl_ax0;
wire [31:0] fpMultAddTest_impl_ay0;
wire [31:0] fpMultAddTest_impl_az0;
wire [31:0] fpMultAddTest_impl_q0;
// fpMultAddTest_impl(FPCOLUMN,5)@0
// out q0@4
assign fpMultAddTest_impl_ax0 = c;
assign fpMultAddTest_impl_ay0 = b;
assign fpMultAddTest_impl_az0 = a;
assign fpMultAddTest_impl_reset0 = areset;
assign fpMultAddTest_impl_ena0 = en[0] | fpMultAddTest_impl_reset0;
fourteennm_fp_mac #(
.operation_mode("sp_mult_add"),
.adder_subtract("true"),
.ax_clock("0"),
.ay_clock("0"),
.az_clock("0"),
.mult_2nd_pipeline_clock("0"),
.adder_input_clock("0"),
.ax_chainin_pl_clock("0"),
.output_clock("0"),
.clear_type("sclr")
) fpMultAddTest_impl_DSP0 (
.clk({1'b0,1'b0,clk}),
.ena({ 1'b0, 1'b0, fpMultAddTest_impl_ena0 }),
.clr({ fpMultAddTest_impl_reset0, fpMultAddTest_impl_reset0 }),
.ax(fpMultAddTest_impl_ax0),
.ay(fpMultAddTest_impl_ay0),
.az(fpMultAddTest_impl_az0),
.resulta(fpMultAddTest_impl_q0),
.accumulate(),
.chainin(),
.chainout()
);
// xOut(GPOUT,4)@4
assign q = fpMultAddTest_impl_q0;
endmodule

68
hw/rtl/fp_cores/altera/stratix10/acl_fmul.sv
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@@ -1,68 +0,0 @@
// -------------------------------------------------------------------------
// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277)
// Quartus Prime development tool and MATLAB/Simulink Interface
//
// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly
// subject to the terms and conditions of the Intel FPGA Software License
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by Intel
// and sold by Intel or its authorized distributors. Please refer to the
// applicable agreement for further details.
// ---------------------------------------------------------------------------
// SystemVerilog created from acl_fmul
// SystemVerilog created on Sun Dec 27 09:48:57 2020
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module acl_fmul (
input wire [31:0] a,
input wire [31:0] b,
input wire [0:0] en,
output wire [31:0] q,
input wire clk,
input wire areset
);
wire fpMulTest_impl_reset0;
wire fpMulTest_impl_ena0;
wire [31:0] fpMulTest_impl_ay0;
wire [31:0] fpMulTest_impl_az0;
wire [31:0] fpMulTest_impl_q0;
// fpMulTest_impl(FPCOLUMN,5)@0
// out q0@3
assign fpMulTest_impl_ay0 = b;
assign fpMulTest_impl_az0 = a;
assign fpMulTest_impl_reset0 = areset;
assign fpMulTest_impl_ena0 = en[0] | fpMulTest_impl_reset0;
fourteennm_fp_mac #(
.operation_mode("sp_mult"),
.ay_clock("0"),
.az_clock("0"),
.mult_2nd_pipeline_clock("0"),
.output_clock("0"),
.clear_type("sclr")
) fpMulTest_impl_DSP0 (
.clk({1'b0,1'b0,clk}),
.ena({ 1'b0, 1'b0, fpMulTest_impl_ena0 }),
.clr({ fpMulTest_impl_reset0, fpMulTest_impl_reset0 }),
.ay(fpMulTest_impl_ay0),
.az(fpMulTest_impl_az0),
.resulta(fpMulTest_impl_q0),
.accumulate(),
.ax(),
.chainin(),
.chainout()
);
// xOut(GPOUT,4)@3
assign q = fpMulTest_impl_q0;
endmodule

69
hw/rtl/fp_cores/altera/stratix10/acl_fsub.sv
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@@ -1,69 +0,0 @@
// -------------------------------------------------------------------------
// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277)
// Quartus Prime development tool and MATLAB/Simulink Interface
//
// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly
// subject to the terms and conditions of the Intel FPGA Software License
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by Intel
// and sold by Intel or its authorized distributors. Please refer to the
// applicable agreement for further details.
// ---------------------------------------------------------------------------
// SystemVerilog created from acl_fsub
// SystemVerilog created on Sun Dec 27 09:48:57 2020
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module acl_fsub (
input wire [31:0] a,
input wire [31:0] b,
input wire [0:0] en,
output wire [31:0] q,
input wire clk,
input wire areset
);
wire fpSubTest_impl_reset0;
wire fpSubTest_impl_ena0;
wire [31:0] fpSubTest_impl_ax0;
wire [31:0] fpSubTest_impl_ay0;
wire [31:0] fpSubTest_impl_q0;
// fpSubTest_impl(FPCOLUMN,5)@0
// out q0@3
assign fpSubTest_impl_ax0 = b;
assign fpSubTest_impl_ay0 = a;
assign fpSubTest_impl_reset0 = areset;
assign fpSubTest_impl_ena0 = en[0] | fpSubTest_impl_reset0;
fourteennm_fp_mac #(
.operation_mode("sp_add"),
.adder_subtract("true"),
.ax_clock("0"),
.ay_clock("0"),
.adder_input_clock("0"),
.output_clock("0"),
.clear_type("sclr")
) fpSubTest_impl_DSP0 (
.clk({1'b0,1'b0,clk}),
.ena({ 1'b0, 1'b0, fpSubTest_impl_ena0 }),
.clr({ fpSubTest_impl_reset0, fpSubTest_impl_reset0 }),
.ax(fpSubTest_impl_ax0),
.ay(fpSubTest_impl_ay0),
.resulta(fpSubTest_impl_q0),
.accumulate(),
.az(),
.chainin(),
.chainout()
);
// xOut(GPOUT,4)@3
assign q = fpSubTest_impl_q0;
endmodule

3
hw/rtl/fp_cores/altera/stratix10/acl_gen.sh
View File

@@ -18,9 +18,6 @@ FBITS="f$(($EXP_BITS + $MAN_BITS + 1))"
echo Generating IP cores for $FBITS
{
$CMD -name "$PREFIX"_fadd -frequency 250 FPAdd $EXP_BITS $MAN_BITS
$CMD -name "$PREFIX"_fsub -frequency 250 FPSub $EXP_BITS $MAN_BITS
$CMD -name "$PREFIX"_fmul -frequency 250 FPMul $EXP_BITS $MAN_BITS
$CMD -name "$PREFIX"_fmadd -frequency 250 FPMultAdd $EXP_BITS $MAN_BITS
$CMD -name "$PREFIX"_fdiv -frequency 250 FPDiv $EXP_BITS $MAN_BITS 0
$CMD -name "$PREFIX"_fsqrt -frequency 250 FPSqrt $EXP_BITS $MAN_BITS