Fix issues quartus synthesis issues

2020-02-18 13:24:18 -05:00
parent d71f8fcc73
commit e76d05f7ce
6 changed files with 15 additions and 10 deletions
--- a/rtl/VX_csr_pipe.v
+++ b/rtl/VX_csr_pipe.v
@@ -1,3 +1,4 @@
+`include "VX_define.v"

 module VX_csr_pipe (
 	input wire clk,    // Clock
@@ -102,4 +103,4 @@ module VX_csr_pipe (
 	assign VX_csr_wb.wb         = wb_s2;
 	assign VX_csr_wb.csr_result = final_csr_data;

-endmodule
+endmodule