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Fix issues quartus synthesis issues

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This commit is contained in:
wgulian3
2020-02-18 13:24:18 -05:00
parent d71f8fcc73
commit e76d05f7ce
6 changed files with 15 additions and 10 deletions
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10
rtl/VX_alu.v
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@@ -28,8 +28,8 @@ module VX_alu(
.PIPELINE(div_pipeline_len)
) unsigned_div (
.clock(clk),
.aclr(0),
.clken(1), // TODO this could be disabled on inactive instructions
.aclr(1'b0),
.clken(1'b1), // TODO this could be disabled on inactive instructions
.numer(ALU_in1),
.denom(ALU_in2),
.quotient(unsigned_div_result),
@@ -45,8 +45,8 @@ module VX_alu(
.PIPELINE(div_pipeline_len)
) signed_div (
.clock(clk),
.aclr(0),
.clken(1), // TODO this could be disabled on inactive instructions
.aclr(1'b0),
.clken(1'b1), // TODO this could be disabled on inactive instructions
.numer(ALU_in1),
.denom(ALU_in2),
.quotient(signed_div_result),
@@ -209,4 +209,4 @@ module VX_alu(
end
`endif
endmodule : VX_alu
endmodule : VX_alu