Merge branch 'graphics' of https://github.com/vortexgpgpu/vortex-dev into graphics
This commit is contained in:
@@ -8,14 +8,17 @@ module VX_tex_format #(
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input wire [`TEX_FORMAT_BITS-1:0] format,
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output wire [`NUM_COLOR_CHANNEL-1:0] color_enable,
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output wire [NUM_TEXELS-1:0][63:0] formatted_texel
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output wire [NUM_TEXELS-1:0][63:0] formatted_lerp_texel,
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output wire [31:0] formatted_pt_texel
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);
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`UNUSED_PARAM (CORE_ID)
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reg [`NUM_COLOR_CHANNEL-1:0] color_enable_r;
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reg [NUM_TEXELS-1:0][63:0] formatted_texel_r;
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reg [NUM_TEXELS-1:0][63:0] formatted_texel_r;
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reg [31:0] formatted_pt_r;
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always @(*) begin
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// bilerp/trilerp input
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for (integer i = 0; i<NUM_TEXELS ;i++ ) begin
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case (format)
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`TEX_FORMAT_R5G6B5: begin
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@@ -32,7 +35,31 @@ module VX_tex_format #(
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formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(texel_data[i][11:8]);
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formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(texel_data[i][15:12]);
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if (i == 0)
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color_enable_r = 4'b0111;
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color_enable_r = 4'b1111;
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end
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`TEX_FORMAT_L8A8: begin
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formatted_texel_r[i][07:00] = `TEX_COLOR_BITS'(texel_data[i][7:0]);
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formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(texel_data[i][15:8]);
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formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(0);
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formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(0);
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if (i == 0)
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color_enable_r = 4'b0011;
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end
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`TEX_FORMAT_A8: begin
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formatted_texel_r[i][07:00] = `TEX_COLOR_BITS'(texel_data[i][7:0]);
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formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(0);
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formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(0);
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formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(0);
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if (i == 0)
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color_enable_r = 4'b0001;
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end
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`TEX_FORMAT_L8: begin
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formatted_texel_r[i][07:00] = `TEX_COLOR_BITS'(texel_data[i][7:0]);
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formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(0);
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formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(0);
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formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(0);
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if (i == 0)
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color_enable_r = 4'b0001;
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end
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default: begin // `TEX_FORMAT_R8G8B8A8:
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formatted_texel_r[i][07:00] = `TEX_COLOR_BITS'(texel_data[i][7:0]);
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@@ -44,12 +71,55 @@ module VX_tex_format #(
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end
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endcase
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end
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// pt sampling direct output
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case (format)
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`TEX_FORMAT_R5G6B5: begin
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formatted_pt_r[07:00] = {`TEX_COLOR_BITS{1'b1}};
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formatted_pt_r[15:08] = `TEX_COLOR_BITS'(texel_data[0][4:0]);
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formatted_pt_r[23:16] = `TEX_COLOR_BITS'(texel_data[0][10:5]);
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formatted_pt_r[31:24] = `TEX_COLOR_BITS'(texel_data[0][15:11]);
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end
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`TEX_FORMAT_R4G4B4A4: begin
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formatted_pt_r[07:00] = `TEX_COLOR_BITS'(texel_data[0][3:0]);
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formatted_pt_r[15:08] = `TEX_COLOR_BITS'(texel_data[0][7:4]);
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formatted_pt_r[23:16] = `TEX_COLOR_BITS'(texel_data[0][11:8]);
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formatted_pt_r[31:24] = `TEX_COLOR_BITS'(texel_data[0][15:12]);
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end
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`TEX_FORMAT_L8A8: begin
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formatted_pt_r[07:00] = `TEX_COLOR_BITS'(texel_data[0][7:0]);
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formatted_pt_r[15:08] = `TEX_COLOR_BITS'(texel_data[0][15:8]);
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formatted_pt_r[23:16] = `TEX_COLOR_BITS'(0);
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formatted_pt_r[31:24] = `TEX_COLOR_BITS'(0);
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end
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`TEX_FORMAT_A8: begin
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formatted_pt_r[07:00] = `TEX_COLOR_BITS'(texel_data[0][7:0]);
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formatted_pt_r[15:08] = `TEX_COLOR_BITS'(0);
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formatted_pt_r[23:16] = `TEX_COLOR_BITS'(0);
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formatted_pt_r[31:24] = `TEX_COLOR_BITS'(0);
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end
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`TEX_FORMAT_L8: begin
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formatted_pt_r[07:00] = `TEX_COLOR_BITS'(texel_data[0][7:0]);
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formatted_pt_r[15:08] = `TEX_COLOR_BITS'(0);
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formatted_pt_r[23:16] = `TEX_COLOR_BITS'(0);
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formatted_pt_r[31:24] = `TEX_COLOR_BITS'(0);
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end
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default: begin // `TEX_FORMAT_R8G8B8A8:
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formatted_pt_r[07:00] = `TEX_COLOR_BITS'(texel_data[0][7:0]);
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formatted_pt_r[15:08] = `TEX_COLOR_BITS'(texel_data[0][15:8]);
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formatted_pt_r[23:16] = `TEX_COLOR_BITS'(texel_data[0][23:16]);
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formatted_pt_r[31:24] = `TEX_COLOR_BITS'(texel_data[0][31:24]);
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end
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endcase
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end
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assign color_enable = color_enable_r;
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assign formatted_pt_texel = formatted_pt_r;
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for (genvar i = 0; i < NUM_TEXELS; i++) begin
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assign formatted_texel[i] = formatted_texel_r[i] & 64'h00ff00ff00ff00ff;
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assign formatted_lerp_texel[i] = formatted_texel_r[i] & 64'h00ff00ff00ff00ff;
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end
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endmodule
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@@ -34,13 +34,14 @@ module VX_tex_sampler #(
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`UNUSED_PARAM (CORE_ID)
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wire [`NUM_THREADS-1:0][31:0] req_data;
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wire [`NUM_THREADS-1:0][31:0] req_data_bilerp;
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wire stall_out;
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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wire [31:0] req_data_bilerp;
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wire [3:0][63:0] formatted_data;
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wire [31:0] formatted_pt_data;
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wire [`NUM_COLOR_CHANNEL-1:0] color_enable;
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VX_tex_format #(
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@@ -51,7 +52,8 @@ module VX_tex_sampler #(
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.format (req_format),
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.color_enable (color_enable),
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.formatted_texel(formatted_data)
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.formatted_lerp_texel(formatted_data),
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.formatted_pt_texel(formatted_pt_data)
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);
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VX_tex_bilerp #(
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@@ -63,13 +65,11 @@ module VX_tex_sampler #(
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.color_enable (color_enable),
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.texels (formatted_data),
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.sampled_data (req_data_bilerp[i])
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.sampled_data (req_data_bilerp)
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);
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end
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assign req_data[i] = (req_filter == `TEX_FILTER_BITS'(0)) ? formatted_pt_data : req_data_bilerp;
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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assign req_data[i] = (req_filter == `TEX_FILTER_BITS'(0)) ? req_texels[i][0] : req_data_bilerp[i];
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end
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assign stall_out = rsp_valid && ~rsp_ready;
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