Parameterization working
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78
rtl/cache/VX_cache_data_per_index.v
vendored
78
rtl/cache/VX_cache_data_per_index.v
vendored
@@ -3,33 +3,36 @@
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`include "../VX_define.v"
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module VX_cache_data_per_index
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/*#(
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parameter CACHE_SIZE = 4096, // Bytes
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parameter CACHE_WAYS = 1,
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parameter CACHE_BLOCK = 128, // Bytes
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parameter CACHE_BANKS = 8,
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parameter NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4)
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)*/
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#(
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parameter CACHE_WAYS = 1,
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parameter NUM_IND = 8,
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parameter CACHE_WAY_INDEX = 1,
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parameter NUM_WORDS_PER_BLOCK = 4,
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parameter TAG_SIZE_START = 0,
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parameter TAG_SIZE_END = 16,
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parameter IND_SIZE_START = 0,
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parameter IND_SIZE_END = 7
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)
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(
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input wire clk, // Clock
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input wire rst,
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input wire valid_in,
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// Addr
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input wire[`DCACHE_IND_SIZE_RNG] addr,
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input wire[IND_SIZE_END:IND_SIZE_START] addr,
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// WE
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input wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][3:0] we,
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input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we,
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input wire evict,
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input wire[`DCACHE_WAY_INDEX-1:0] way_to_update,
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input wire[CACHE_WAY_INDEX-1:0] way_to_update,
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// Data
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input wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data
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input wire[`DCACHE_TAG_SIZE_RNG] tag_write,
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input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data
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input wire[TAG_SIZE_END:TAG_SIZE_START] tag_write,
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output wire[`DCACHE_TAG_SIZE_RNG] tag_use,
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output wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] data_use,
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output wire[TAG_SIZE_END:TAG_SIZE_START] tag_use,
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output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use,
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output wire valid_use,
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output wire dirty_use,
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output wire[`DCACHE_WAY_INDEX-1:0] way
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output wire[CACHE_WAY_INDEX-1:0] way
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);
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//localparam NUMBER_BANKS = CACHE_BANKS;
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@@ -37,30 +40,30 @@ module VX_cache_data_per_index
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// localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4);
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//localparam NUMBER_INDEXES = `DCACHE_NUM_IND;
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wire [`DCACHE_WAYS-1:0][`DCACHE_TAG_SIZE_RNG] tag_use_per_way;
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wire [`DCACHE_WAYS-1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] data_use_per_way;
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wire [`DCACHE_WAYS-1:0] valid_use_per_way;
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wire [`DCACHE_WAYS-1:0] dirty_use_per_way;
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wire [`DCACHE_WAYS-1:0] hit_per_way;
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reg [`DCACHE_NUM_IND-1:0][`DCACHE_WAY_INDEX-1:0] eviction_way_index;
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wire [`DCACHE_WAYS-1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][3:0] we_per_way;
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wire [`DCACHE_WAYS-1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] data_write_per_way;
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wire [`DCACHE_WAYS-1:0] write_from_mem_per_way;
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wire [CACHE_WAYS-1:0][TAG_SIZE_END:TAG_SIZE_START] tag_use_per_way;
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wire [CACHE_WAYS-1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] data_use_per_way;
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wire [CACHE_WAYS-1:0] valid_use_per_way;
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wire [CACHE_WAYS-1:0] dirty_use_per_way;
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wire [CACHE_WAYS-1:0] hit_per_way;
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reg [NUM_IND-1:0][CACHE_WAY_INDEX-1:0] eviction_way_index;
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wire [CACHE_WAYS-1:0][NUM_WORDS_PER_BLOCK-1:0][3:0] we_per_way;
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wire [CACHE_WAYS-1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] data_write_per_way;
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wire [CACHE_WAYS-1:0] write_from_mem_per_way;
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wire invalid_found;
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wire [`DCACHE_WAY_INDEX-1:0] way_index;
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wire [`DCACHE_WAY_INDEX-1:0] invalid_index;
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wire [CACHE_WAY_INDEX-1:0] way_index;
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wire [CACHE_WAY_INDEX-1:0] invalid_index;
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if(`DCACHE_WAYS != 1) begin
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VX_generic_priority_encoder #(.N(`DCACHE_WAYS)) valid_index
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if(CACHE_WAYS != 1) begin
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VX_generic_priority_encoder #(.N(CACHE_WAYS)) valid_index
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(
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.valids(~valid_use_per_way),
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.index (invalid_index),
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.found (invalid_found)
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);
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VX_generic_priority_encoder #(.N(`DCACHE_WAYS)) way_indexing
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VX_generic_priority_encoder #(.N(CACHE_WAYS)) way_indexing
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(
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.valids(hit_per_way),
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.index (way_index),
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@@ -90,19 +93,20 @@ module VX_cache_data_per_index
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genvar ways;
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for(ways=0; ways < `DCACHE_WAYS; ways = ways + 1) begin
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for(ways=0; ways < CACHE_WAYS; ways = ways + 1) begin
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assign hit_per_way[ways] = ((valid_use_per_way[ways] == 1'b1) && (tag_use_per_way[ways] == tag_write)) ? 1'b1 : 0;
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assign we_per_way[ways] = (evict == 1'b1) || (update == 1'b1) ? ((ways == way_to_update) ? (we) : 0) : 0;
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assign data_write_per_way[ways] = (evict == 1'b1) || (update == 1'b1) ? ((ways == way_to_update) ? data_write : 0) : 0;
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assign write_from_mem_per_way[ways] = (evict == 1'b1) ? ((ways == way_to_update) ? 1 : 0) : 0;
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/*VX_cache_data #(
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.CACHE_SIZE(`CACHE_SIZE),
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.CACHE_WAYS(`DCACHE_WAYS),
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.CACHE_BLOCK(`CACHE_BLOCK),
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.CACHE_BANKS(`CACHE_BANKS)) data_structures(*/
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VX_cache_data data_structures(
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VX_cache_data #(
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.NUM_IND (NUM_IND),
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.NUM_WORDS_PER_BLOCK (NUM_WORDS_PER_BLOCK),
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.TAG_SIZE_START (TAG_SIZE_START),
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.TAG_SIZE_END (TAG_SIZE_END),
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.IND_SIZE_START (IND_SIZE_START),
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.IND_SIZE_END (IND_SIZE_END)) data_structures(
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.clk (clk),
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.rst (rst),
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// Inputs
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@@ -124,7 +128,7 @@ module VX_cache_data_per_index
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eviction_way_index <= 0;
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end else begin
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if(miss && dirty_use && valid_use && !evict && valid_in) begin // can be either evict or invalid cache entries
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if((eviction_way_index[addr]+1) == `DCACHE_WAYS) begin
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if((eviction_way_index[addr]+1) == CACHE_WAYS) begin
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eviction_way_index[addr] <= 0;
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end else begin
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eviction_way_index[addr] <= (eviction_way_index[addr] + 1);
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