diff --git a/.gitmodules b/.gitmodules index dd60e98f..96aeefdb 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,6 @@ [submodule "hw/rtl/fp_cores/fpnew"] path = hw/rtl/fp_cores/fpnew url = https://github.com/pulp-platform/fpnew.git +[submodule "sim/common/softfloat"] + path = sim/common/softfloat + url = https://github.com/ucb-bar/berkeley-softfloat-3.git diff --git a/.travis.yml b/.travis.yml index a9d614d1..9fbe9bac 100644 --- a/.travis.yml +++ b/.travis.yml @@ -30,22 +30,25 @@ jobs: include: - stage: test name: coverage - script: cp -r $PWD ../build1 && cd ../build1 && ./ci/regression.sh -coverage + script: cp -r $PWD ../build1 && cd ../build1 && ./ci/travis_run.py ./ci/regression.sh -coverage - stage: test name: cluster - script: cp -r $PWD ../build2 && cd ../build2 && ./ci/regression.sh -cluster + script: cp -r $PWD ../build2 && cd ../build2 && ./ci/travis_run.py ./ci/regression.sh -cluster - stage: test name: debug - script: cp -r $PWD ../build3 && cd ../build3 && ./ci/regression.sh -debug + script: cp -r $PWD ../build3 && cd ../build3 && ./ci/travis_run.py ./ci/regression.sh -debug - stage: test name: config - script: cp -r $PWD ../build4 && cd ../build4 && ./ci/regression.sh -config + script: cp -r $PWD ../build4 && cd ../build4 && ./ci/travis_run.py ./ci/regression.sh -config - stage: test - name: stress - script: cp -r $PWD ../build5 && cd ../build5 && ./ci/regression.sh -stress + name: stress0 + script: cp -r $PWD ../build5 && cd ../build5 && ./ci/travis_run.py ./ci/regression.sh -stress0 + - stage: test + name: stress1 + script: cp -r $PWD ../build6 && cd ../build6 && ./ci/travis_run.py ./ci/regression.sh -stress1 - stage: test name: compiler - script: cp -r $PWD ../build6 && cd ../build6 && ./ci/test_compiler.sh + script: cp -r $PWD ../build7 && cd ../build7 && ./ci/travis_run.py ./ci/test_compiler.sh after_success: # Gather code coverage diff --git a/Makefile b/Makefile index 6ce9408d..859c597d 100644 --- a/Makefile +++ b/Makefile @@ -1,14 +1,13 @@ - all: $(MAKE) -C hw + $(MAKE) -C sim $(MAKE) -C driver $(MAKE) -C runtime - $(MAKE) -C simX $(MAKE) -C tests clean: $(MAKE) -C hw clean + $(MAKE) -C sim clean $(MAKE) -C driver clean - $(MAKE) -C simX clean $(MAKE) -C runtime clean $(MAKE) -C tests clean \ No newline at end of file diff --git a/README.md b/README.md index cc6239fb..76bbd380 100644 --- a/README.md +++ b/README.md @@ -8,7 +8,11 @@ Vortex is a full-system RISCV-based GPGPU processor. ## Specifications - Support RISC-V RV32IMF ISA -- Scalability: 1 to 32 cores with optional L2 and L3 caches +- Performance: + - 1024 total threads running at 250 MHz + - 128 Gflops of compute bandwidth + - 16 GB/s of memory bandwidth +- Scalability: up to 64 cores with optional L2 and L3 caches - Software: OpenCL 1.2 Support - Supported FPGAs: - Intel Arria 10 @@ -20,11 +24,11 @@ Vortex is a full-system RISCV-based GPGPU processor. - `hw`: Hardware sources. -- `driver`: Host driver software. +- `driver`: Host drivers repository. - `runtime`: Kernel Runtime software. -- `simX`: Cycle-approximate simulator. +- `sim`: Simulators repository. - `tests`: Tests repository. diff --git a/ci/blackbox.sh b/ci/blackbox.sh index be5ce2a4..f14acec2 100755 --- a/ci/blackbox.sh +++ b/ci/blackbox.sh @@ -20,6 +20,7 @@ L3=0 DEBUG=0 SCOPE=0 HAS_ARGS=0 +DEBUG_LEVEL=1 for i in "$@" do @@ -88,28 +89,19 @@ done case $DRIVER in rtlsim) DRIVER_PATH=$VORTEX_HOME/driver/rtlsim - DRIVER_EXTRA= - CLEAN_TOKEN=clean ;; vlsim) - DRIVER_PATH=$VORTEX_HOME/driver/opae - DRIVER_EXTRA=vlsim - CLEAN_TOKEN=clean-vlsim + DRIVER_PATH=$VORTEX_HOME/driver/vlsim ;; asesim) - DRIVER_PATH=$VORTEX_HOME/driver/opae - DRIVER_EXTRA=asesim - CLEAN_TOKEN=clean-asesim + DRIVER_PATH=$VORTEX_HOME/driver/asesim ;; fpga) - DRIVER_PATH=$VORTEX_HOME/driver/opae - DRIVER_EXTRA=fpga - CLEAN_TOKEN=clean-fpga + DRIVER_PATH=$VORTEX_HOME/driver/fpga ;; simx) DRIVER_PATH=$VORTEX_HOME/driver/simx - DRIVER_EXTRA= - CLEAN_TOKEN=clean + DEBUG_LEVEL=3 ;; *) echo "invalid driver: $DRIVER" @@ -132,7 +124,7 @@ CONFIGS="-DNUM_CLUSTERS=$CLUSTERS -DNUM_CORES=$CORES -DNUM_WARPS=$WARPS -DNUM_TH echo "CONFIGS=$CONFIGS" -make -C $DRIVER_PATH $CLEAN_TOKEN +make -C $DRIVER_PATH clean status=0 @@ -140,9 +132,9 @@ if [ $DEBUG -eq 1 ] then if [ $SCOPE -eq 1 ] then - DEBUG=1 SCOPE=1 CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH $DRIVER_EXTRA + DEBUG=$DEBUG_LEVEL SCOPE=1 CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH else - DEBUG=1 CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH $DRIVER_EXTRA + DEBUG=$DEBUG_LEVEL CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH fi if [ $HAS_ARGS -eq 1 ] @@ -161,9 +153,9 @@ then else if [ $SCOPE -eq 1 ] then - SCOPE=1 CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH $DRIVER_EXTRA + SCOPE=1 CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH else - CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH $DRIVER_EXTRA + CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH fi if [ $HAS_ARGS -eq 1 ] diff --git a/ci/prebuilt.sh b/ci/prebuilt.sh index 4198b2e8..cc9ff3dd 100755 --- a/ci/prebuilt.sh +++ b/ci/prebuilt.sh @@ -3,9 +3,13 @@ # exit when any command fails set -e -OS_DIR=ubuntu/bionic -SRCDIR=/opt -DESTDIR=. +OS_DIR=${OS_DIR:-'ubuntu/bionic'} +SRCDIR=${SRCDIR:-'/opt'} +DESTDIR=${DESTDIR:-'.'} + +echo "OS_DIR=${OS_DIR}" +echo "SRCDIR=${SRCDIR}" +echo "DESTDIR=${DESTDIR}" riscv() { diff --git a/ci/regression.sh b/ci/regression.sh index 9561ae6c..24954616 100755 --- a/ci/regression.sh +++ b/ci/regression.sh @@ -3,7 +3,7 @@ # exit when any command fails set -e -# build sources +# ensure build make -s coverage() @@ -27,17 +27,17 @@ cluster() echo "begin clustering tests..." # warp/threads configurations -./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=1 --warps=2 --threads=8 --app=demo -./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=1 --warps=8 --threads=2 --app=demo +./ci/blackbox.sh --driver=rtlsim --cores=1 --warps=2 --threads=8 --app=demo +./ci/blackbox.sh --driver=rtlsim --cores=1 --warps=8 --threads=2 --app=demo # cores clustering -./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=1 --clusters=1 --app=demo --args="-n1" -./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --app=demo --args="-n1" +./ci/blackbox.sh --driver=rtlsim --cores=1 --clusters=1 --app=demo --args="-n1" +./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --app=demo --args="-n1" # L2/L3 -./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=demo --args="-n1" -./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l3cache --app=demo --args="-n1" -./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l2cache --l3cache --app=io_addr --args="-n1" +./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=demo --args="-n1" +./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l3cache --app=demo --args="-n1" +./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l2cache --l3cache --app=io_addr --args="-n1" echo "clustering tests done!" } @@ -46,9 +46,9 @@ debug() { echo "begin debugging tests..." -./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=1 --perf --app=demo --args="-n1" -./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=1 --debug --app=demo --args="-n1" -./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=1 --scope --app=basic --args="-t0 -n1" +./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --perf --app=demo --args="-n1" +./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --debug --app=demo --args="-n1" +./ci/blackbox.sh --driver=vlsim --cores=1 --scope --app=basic --args="-t0 -n1" echo "debugging tests done!" } @@ -75,13 +75,21 @@ FPU_CORE=FPU_DEFAULT ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=dogfood # using FPNEW FPU core FPU_CORE=FPU_FPNEW ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=dogfood +# using AXI bus +AXI_BUS=1 ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=demo + +# adjust l1 block size to match l2 +CONFIGS="-DMEM_BLOCK_SIZE=16 -DL1_BLOCK_SIZE=16" ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=io_addr --args="-n1" + # test cache banking -CONFIGS="-DDNUM_BANKS=1" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=demo -CONFIGS="-DDNUM_BANKS=2" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=demo +CONFIGS="-DDNUM_BANKS=1" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=io_addr +CONFIGS="-DDNUM_BANKS=2" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=io_addr # test cache multi-porting -CONFIGS="-DDNUM_PORTS=2" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=demo -CONFIGS="-DDNUM_PORTS=4" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=demo +CONFIGS="-DDNUM_PORTS=2" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=io_addr +CONFIGS="-DDNUM_PORTS=2" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=demo --debug --args="-n1" +CONFIGS="-DL2_NUM_PORTS=2 -DDNUM_PORTS=2" ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=io_addr +CONFIGS="-DL2_NUM_PORTS=4 -DDNUM_PORTS=4" ./ci/blackbox.sh --driver=rtlsim --cores=4 --l2cache --app=io_addr # test 128-bit MEM block CONFIGS=-DMEM_BLOCK_SIZE=16 ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo @@ -95,51 +103,70 @@ CONFIGS="-DPLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH=27" ./ci/blackbox.sh --driver= # test 128-bit DRAM block CONFIGS="-DPLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH=128 -DPLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH=28 -DPLATFORM_PARAM_LOCAL_MEMORY_BANKS=1" ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo -# test verilator reset values -CONFIGS="-DVERILATOR_RESET_VALUE=0" ./ci/blackbox.sh --driver=vlsim --cores=4 --app=sgemm -CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=vlsim --cores=4 --app=sgemm - # test long memory latency CONFIGS="-DMEM_LATENCY=100 -DMEM_RQ_SIZE=4 -DMEM_STALLS_MODULO=4" ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo echo "configuration tests done!" } -stress() +stress0() { -echo "begin stress tests..." +echo "begin stress0 tests..." -./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --clusters=2 --l3cache --app=sgemm --args="-n256" +# test verilator reset values +CONFIGS="-DVERILATOR_RESET_VALUE=0" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=sgemm +CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=sgemm +FPU_CORE=FPU_DEFAULT CONFIGS="-DVERILATOR_RESET_VALUE=0" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=dogfood +FPU_CORE=FPU_DEFAULT CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=dogfood +CONFIGS="-DVERILATOR_RESET_VALUE=0" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=io_addr +CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=io_addr +CONFIGS="-DVERILATOR_RESET_VALUE=0" ./ci/blackbox.sh --driver=vlsim --cores=4 --app=printf +CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=vlsim --cores=4 --app=printf -echo "stress tests done!" +echo "stress0 tests done!" +} + +stress1() +{ +echo "begin stress1 tests..." + +./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --clusters=2 --l3cache --app=sgemm --args="-n256" + +echo "stress1 tests done!" } usage() { - echo "usage: regression [-coverage] [-cluster] [-debug] [-config] [-stress] [-all] [-h|--help]" + echo "usage: regression [-coverage] [-cluster] [-debug] [-config] [-stress[#n]] [-all] [-h|--help]" } while [ "$1" != "" ]; do case $1 in -coverage ) coverage - ;; + ;; -cluster ) cluster - ;; + ;; -debug ) debug - ;; + ;; -config ) config ;; - -stress ) stress + -stress0 ) stress0 + ;; + -stress1 ) stress1 + ;; + -stress ) stress0 + stress1 ;; -all ) coverage cluster debug config - stress - ;; + stress0 + stress1 + ;; -h | --help ) usage exit - ;; + ;; * ) usage exit 1 esac diff --git a/doc/codebase.md b/doc/codebase.md index 4f4db1fc..5a33920f 100644 --- a/doc/codebase.md +++ b/doc/codebase.md @@ -7,25 +7,30 @@ The directory/file layout of the Vortex codebase is as followed: - `cache`: cache subsystem code - `fp_cores`: floating point unit code - `interfaces`: interfaces for inter-module communication - - `libs`: general-purpose modules (i.e., encoder, arbiter, ...) + - `libs`: general-purpose RTL modules - `syn`: synthesis directory - `opae`: OPAE synthesis scripts - `quartus`: Quartus synthesis scripts - `synopsys`: Synopsys synthesis scripts + - `modelsim`: Modelsim synthesis scripts - `yosys`: Yosys synthesis scripts - - `simulate`: baseline RTL simulator (used by RTLSIM) - `unit_tests`: unit tests for some hardware components -- `driver`: Host driver software +- `driver`: host drivers repository - `include`: Vortex driver public headers - - `opae`: software driver that uses Intel OPAE - - `vlsim`: software driver that simulates Full RTL (include AFU) - - `rtlsim`: software driver that simulates processor RTL + - `stub`: Vortex stub driver library + - `fpga`: software driver that uses Intel OPAE FPGA + - `asesim`: software driver that uses Intel ASE simulator + - `vlsim`: software driver that uses vlsim simulator + - `rtlsim`: software driver that uses rtlsim simulator - `simx`: software driver that uses simX simulator -- `runtime`: Kernel runtime software +- `runtime`: kernel runtime software - `include`: Vortex runtime public headers - `linker`: linker file for compiling kernels - `src`: runtime implementation -- `simX`: cycle approximate simulator for vortex +- `sim`: + - `vlsim`: AFU RTL simulator + - `rtlsim`: processor RTL simulator + - `simX`: cycle approximate simulator for vortex - `tests`: tests repository. - `runtime`: runtime tests - `regression`: regression tests diff --git a/driver/Makefile b/driver/Makefile index 58de93a2..8899c0cc 100644 --- a/driver/Makefile +++ b/driver/Makefile @@ -1,10 +1,16 @@ -all: stub rtlsim simx opae +all: stub rtlsim simx vlsim stub: $(MAKE) -C stub -opae: - $(MAKE) -C opae +fpga: + $(MAKE) -C fpga + +asesim: + $(MAKE) -C asesim + +vlsim: + $(MAKE) -C vlsim rtlsim: $(MAKE) -C rtlsim @@ -14,8 +20,10 @@ simx: clean: $(MAKE) clean -C stub - $(MAKE) clean -C opae + $(MAKE) clean -C fpga + $(MAKE) clean -C asesim + $(MAKE) clean -C vlsim $(MAKE) clean -C rtlsim $(MAKE) clean -C simx -.PHONY: all stub opae rtlsim simx clean \ No newline at end of file +.PHONY: all stub fpga asesim vlsim rtlsim simx clean \ No newline at end of file diff --git a/driver/asesim/Makefile b/driver/asesim/Makefile new file mode 100644 index 00000000..c3077e06 --- /dev/null +++ b/driver/asesim/Makefile @@ -0,0 +1,74 @@ +OPAE_HOME ?= /tools/opae/1.4.0 + +RTL_DIR=../../hw/rtl + +SCRIPT_DIR=../../hw/scripts + +OPAE_SYN_DIR=../../hw/syn/opae + +CXXFLAGS += -std=c++11 -O2 -DNDEBUG -Wall -Wextra -pedantic -Wfatal-errors +#CXXFLAGS += -std=c++11 -O0 -g -Wall -Wextra -pedantic -Wfatal-errors + +CXXFLAGS += -I. -I../include -I../../hw -I$(OPAE_HOME)/include -I$(OPAE_SYN_DIR) + +LDFLAGS += -L$(OPAE_HOME)/lib -luuid -lopae-c-ase + +# stack execution protection +LDFLAGS +=-z noexecstack + +# data relocation and projection +LDFLAGS +=-z relro -z now + +# stack buffer overrun detection +CXXFLAGS +=-fstack-protector + +# Position independent code +CXXFLAGS += -fPIC + +# Add external configuration +CXXFLAGS += $(CONFIGS) + +# Dump perf stats +CXXFLAGS += -DDUMP_PERF_STATS + +LDFLAGS += -shared + +PROJECT = libvortex.so + +SRCS = ../common/opae.cpp ../common/vx_utils.cpp + +# Enable scope analyzer +ifdef SCOPE + CXXFLAGS += -DSCOPE + SRCS += ../common/vx_scope.cpp + SCOPE_H = scope-defs.h +endif + +# Enable perf counters +ifdef PERF + CXXFLAGS += -DPERF_ENABLE +endif + +all: $(PROJECT) + +$(OPAE_SYN_DIR)/vortex_afu.h: + $(MAKE) -C $(OPAE_SYN_DIR) vortex_afu.h + +scope-defs.h: $(SCRIPT_DIR)/scope.json + $(SCRIPT_DIR)/scope.py $(CONFIGS) -cc scope-defs.h -vl $(RTL_DIR)/scope-defs.vh $(SCRIPT_DIR)/scope.json + +# generate scope data +scope: scope-defs.h + +$(PROJECT): $(SRCS) $(OPAE_SYN_DIR)/vortex_afu.h $(SCOPE_H) + $(CXX) $(CXXFLAGS) -DUSE_ASE $(SRCS) $(LDFLAGS) -o $(PROJECT) + +.depend: $(SRCS) + $(CXX) $(CXXFLAGS) -MM $(SRCS) > .depend; + +clean: + rm -rf $(PROJECT) *.o .depend scope-defs.h + +ifneq ($(MAKECMDGOALS),clean) + -include .depend +endif diff --git a/driver/opae/vortex.cpp b/driver/common/opae.cpp similarity index 95% rename from driver/opae/vortex.cpp rename to driver/common/opae.cpp index 960d7cbe..de6e0fbb 100755 --- a/driver/opae/vortex.cpp +++ b/driver/common/opae.cpp @@ -8,12 +8,13 @@ #include #include #include +#include #if defined(USE_FPGA) || defined(USE_ASE) #include #include #elif defined(USE_VLSIM) -#include "vlsim/fpga.h" +#include #endif #include @@ -78,6 +79,34 @@ inline bool is_aligned(size_t addr, size_t alignment) { /////////////////////////////////////////////////////////////////////////////// +#ifdef DUMP_PERF_STATS +class AutoPerfDump { +private: + std::list devices_; + +public: + AutoPerfDump() {} + + ~AutoPerfDump() { + for (auto device : devices_) { + vx_dump_perf(device, stdout); + } + } + + void add_device(vx_device_h device) { + devices_.push_back(device); + } + + void remove_device(vx_device_h device) { + devices_.remove(device); + } +}; + +AutoPerfDump gAutoPerfDump; +#endif + +/////////////////////////////////////////////////////////////////////////////// + extern int vx_dev_caps(vx_device_h hdevice, unsigned caps_id, unsigned *value) { if (nullptr == hdevice) return -1; @@ -223,6 +252,10 @@ extern int vx_dev_open(vx_device_h* hdevice) { *hdevice = device; +#ifdef DUMP_PERF_STATS + gAutoPerfDump.add_device(*hdevice); +#endif + return 0; } @@ -237,7 +270,8 @@ extern int vx_dev_close(vx_device_h hdevice) { #endif #ifdef DUMP_PERF_STATS - vx_dump_perf(device, stdout); + gAutoPerfDump.remove_device(hdevice); + vx_dump_perf(hdevice, stdout); #endif fpgaClose(device->fpga); diff --git a/driver/opae/vx_scope.cpp b/driver/common/vx_scope.cpp similarity index 98% rename from driver/opae/vx_scope.cpp rename to driver/common/vx_scope.cpp index eb192250..9e855d5b 100644 --- a/driver/opae/vx_scope.cpp +++ b/driver/common/vx_scope.cpp @@ -1,3 +1,4 @@ +#include "vx_scope.h" #include #include #include @@ -7,17 +8,9 @@ #include #include #include - -#ifdef USE_VLSIM -#include "vlsim/fpga.h" -#else -#include -#endif - #include -#include "vx_scope.h" -#include "vortex_afu.h" -#include "scope-defs.h" +#include +#include #define FRAME_FLUSH_SIZE 100 diff --git a/driver/opae/vx_scope.h b/driver/common/vx_scope.h similarity index 71% rename from driver/opae/vx_scope.h rename to driver/common/vx_scope.h index bb8cad19..dfc53520 100644 --- a/driver/opae/vx_scope.h +++ b/driver/common/vx_scope.h @@ -1,5 +1,13 @@ #pragma once +#include + +#ifdef USE_VLSIM +#include +#else +#include +#endif + #if defined(USE_FPGA) #define HANG_TIMEOUT 60 #else diff --git a/driver/fpga/Makefile b/driver/fpga/Makefile new file mode 100644 index 00000000..a2771ecb --- /dev/null +++ b/driver/fpga/Makefile @@ -0,0 +1,76 @@ +OPAE_HOME ?= /tools/opae/1.4.0 + +RTL_DIR=../../hw/rtl + +SCRIPT_DIR=../../hw/scripts + +OPAE_SYN_DIR=../../hw/syn/opae + +CXXFLAGS += -std=c++11 -O2 -DNDEBUG -Wall -Wextra -pedantic -Wfatal-errors +#CXXFLAGS += -std=c++11 -O0 -g -Wall -Wextra -pedantic -Wfatal-errors + +CXXFLAGS += -I. -I../include -I../../hw -I$(OPAE_HOME)/include -I$(OPAE_SYN_DIR) + +LDFLAGS += -L$(OPAE_HOME)/lib -luuid -lopae-c + +#SCOPE=1 + +# stack execution protection +LDFLAGS +=-z noexecstack + +# data relocation and projection +LDFLAGS +=-z relro -z now + +# stack buffer overrun detection +CXXFLAGS +=-fstack-protector + +# Position independent code +CXXFLAGS += -fPIC + +# Add external configuration +CXXFLAGS += $(CONFIGS) + +# Dump perf stats +CXXFLAGS += -DDUMP_PERF_STATS + +LDFLAGS += -shared + +PROJECT = libvortex.so + +SRCS = ../common/opae.cpp ../common/vx_utils.cpp + +# Enable scope analyzer +ifdef SCOPE + CXXFLAGS += -DSCOPE + SRCS += ../common/vx_scope.cpp + SCOPE_H = scope-defs.h +endif + +# Enable perf counters +ifdef PERF + CXXFLAGS += -DPERF_ENABLE +endif + +all: $(PROJECT) + +$(OPAE_SYN_DIR)/vortex_afu.h: + $(MAKE) -C $(OPAE_SYN_DIR) vortex_afu.h + +scope-defs.h: $(SCRIPT_DIR)/scope.json + $(SCRIPT_DIR)/scope.py $(CONFIGS) -cc scope-defs.h -vl $(RTL_DIR)/scope-defs.vh $(SCRIPT_DIR)/scope.json + +# generate scope data +scope: scope-defs.h + +$(PROJECT): $(SRCS) $(OPAE_SYN_DIR)/vortex_afu.h $(SCOPE_H) + $(CXX) $(CXXFLAGS) -DUSE_FPGA $^ $(LDFLAGS) -o $(PROJECT) + +.depend: $(SRCS) + $(CXX) $(CXXFLAGS) -MM $(SRCS) > .depend; + +clean: + rm -rf $(PROJECT) *.o .depend scope-defs.h + +ifneq ($(MAKECMDGOALS),clean) + -include .depend +endif diff --git a/driver/opae/Makefile b/driver/opae/Makefile deleted file mode 100644 index 1a8c6051..00000000 --- a/driver/opae/Makefile +++ /dev/null @@ -1,116 +0,0 @@ -OPAE_HOME ?= /tools/opae/1.4.0 - -CXXFLAGS += -std=c++11 -O2 -DNDEBUG -Wall -Wextra -pedantic -Wfatal-errors -#CXXFLAGS += -std=c++11 -O0 -g -Wall -Wextra -pedantic -Wfatal-errors - -CXXFLAGS += -I../include -I$(OPAE_HOME)/include -I../../hw - -LDFLAGS += -L$(OPAE_HOME)/lib - -#SCOPE=1 - -# stack execution protection -LDFLAGS +=-z noexecstack - -# data relocation and projection -LDFLAGS +=-z relro -z now - -# stack buffer overrun detection -CXXFLAGS +=-fstack-protector - -# Position independent code -CXXFLAGS += -fPIC - -# Add external configuration -CXXFLAGS += $(CONFIGS) - -# Dump perf stats -CXXFLAGS += -DDUMP_PERF_STATS - -LDFLAGS += -shared - -FPGA_LIBS += -luuid -lopae-c - -ASE_LIBS += -luuid -lopae-c-ase - -VLSIM_LIBS += -lopae-c-vlsim - -ASE_DIR = ase - -VLSIM_DIR = vlsim - -RTL_DIR=../../hw/rtl - -SCRIPT_DIR=../../hw/scripts - -PROJECT = libvortex.so - -PROJECT_ASE = $(ASE_DIR)/libvortex.so - -PROJECT_VLSIM = $(VLSIM_DIR)/libvortex.so - -AFU_JSON_INFO = vortex_afu.h - -SRCS = vortex.cpp ../common/vx_utils.cpp - -# Enable scope analyzer -ifdef SCOPE - CXXFLAGS += -DSCOPE - SRCS += vx_scope.cpp - SCOPE_ENABLE = SCOPE=1 - SCOPE_H = scope-defs.h -endif - -# Enable perf counters -ifdef PERF - CXXFLAGS += -DPERF_ENABLE - PERF_ENABLE = PERF=1 -endif - -all: vlsim - -# AFU info from JSON file, including AFU UUID -json: ../../hw/opae/vortex_afu.json - afu_json_mgr json-info --afu-json=$^ --c-hdr=$@ - -scope-defs.h: $(SCRIPT_DIR)/scope.json - $(SCRIPT_DIR)/scope.py $(RTL_INCLUDE) $(CONFIGS) -cc scope-defs.h -vl $(RTL_DIR)/scope-defs.vh $(SCRIPT_DIR)/scope.json - -# generate scope data -scope: scope-defs.h - -vlsim-hw: $(SCOPE_H) - $(SCOPE_ENABLE) $(PERF_ENABLE) $(MAKE) -C vlsim - -fpga: $(SRCS) $(SCOPE_H) - $(CXX) $(CXXFLAGS) -DUSE_FPGA $^ $(LDFLAGS) $(FPGA_LIBS) -o $(PROJECT) - -asesim: $(SRCS) $(ASE_DIR) $(SCOPE_H) - $(CXX) $(CXXFLAGS) -DUSE_ASE $(SRCS) $(LDFLAGS) $(ASE_LIBS) -o $(PROJECT_ASE) - -vlsim: $(SRCS) vlsim-hw - $(CXX) $(CXXFLAGS) -DUSE_VLSIM $(SRCS) $(LDFLAGS) -L./vlsim $(VLSIM_LIBS) -o $(PROJECT_VLSIM) - -vortex.o: vortex.cpp - $(CXX) $(CXXFLAGS) -c vortex.cpp -o $@ - -$(ASE_DIR): - mkdir -p ase - -.depend: $(SRCS) - $(CXX) $(CXXFLAGS) -MM $(SRCS) > .depend; - -clean-fpga: - rm -rf $(PROJECT) *.o .depend - -clean-asesim: - rm -rf $(PROJECT_ASE) *.o .depend - -clean-vlsim: - $(MAKE) -C vlsim clean - -clean: clean-fpga clean-asesim clean-vlsim - -ifneq ($(MAKECMDGOALS),clean) - -include .depend -endif diff --git a/driver/opae/vlsim/Makefile b/driver/opae/vlsim/Makefile deleted file mode 100644 index 9dc04a86..00000000 --- a/driver/opae/vlsim/Makefile +++ /dev/null @@ -1,100 +0,0 @@ -CFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors -#CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors - -CFLAGS += -DUSE_VLSIM -fPIC -Wno-maybe-uninitialized -CFLAGS += -I../../../../hw - -# control RTL debug print states -DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE -DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_ICACHE -DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_DCACHE -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_BANK -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSHR -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_TAG -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_DATA -DBG_PRINT_FLAGS += -DDBG_PRINT_MEM -DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE -DBG_PRINT_FLAGS += -DDBG_PRINT_AVS -DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE -DBG_PRINT_FLAGS += -DDBG_PRINT_TEX - -DBG_FLAGS += $(DBG_PRINT_FLAGS) -DBG_FLAGS += -DDBG_CACHE_REQ_INFO - -CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=1 - -CFLAGS += $(CONFIGS) -CFLAGS += -DDUMP_PERF_STATS - -LDFLAGS += -shared -pthread -# LDFLAGS += -dynamiclib -pthread - -TOP = vortex_afu_shim - -RTL_DIR=../../../hw/rtl -DPI_DIR=../../../hw/dpi - -SRCS = fpga.cpp opae_sim.cpp -SRCS += $(DPI_DIR)/util_dpi.cpp $(DPI_DIR)/float_dpi.cpp - -FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(DPI_DIR) -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src -I$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(RTL_DIR)/fp_cores/fpnew/src -TEX_INCLUDE = -I$(RTL_DIR)/tex_unit -RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache $(FPU_INCLUDE) $(TEX_INCLUDE) -RTL_INCLUDE += -I$(RTL_DIR)/afu -I$(RTL_DIR)/afu/ccip - -VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic -VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO -VL_FLAGS += --x-initial unique --x-assign unique -VL_FLAGS += verilator.vlt -VL_FLAGS += $(CONFIGS) - -# Enable Verilator multithreaded simulation -#THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') -#VL_FLAGS += --threads $(THREADS) - -# Debugigng -ifdef DEBUG - VL_FLAGS += -DVCD_OUTPUT --trace --trace-structs $(DBG_FLAGS) - CFLAGS += -DVCD_OUTPUT $(DBG_FLAGS) -else - VL_FLAGS += -DNDEBUG - CFLAGS += -DNDEBUG -endif - -# Enable scope analyzer -ifdef SCOPE - VL_FLAGS += -DSCOPE - CFLAGS += -DSCOPE -endif - -# Enable perf counters -ifdef PERF - VL_FLAGS += -DPERF_ENABLE - CFLAGS += -DPERF_ENABLE -endif - -# use our OPAE shim -VL_FLAGS += -DNOPAE -CFLAGS += -DNOPAE - -# ALU backend -VL_FLAGS += -DIMUL_DPI -VL_FLAGS += -DIDIV_DPI - -# FPU backend -FPU_CORE ?= FPU_DPI -VL_FLAGS += -D$(FPU_CORE) - -PROJECT = libopae-c-vlsim.so - -all: $(PROJECT) - -vortex_afu.h : $(RTL_DIR)/afu/vortex_afu.vh - ../../../hw/scripts/gen_config.py -i $(RTL_DIR)/afu/vortex_afu.vh -o vortex_afu.h - -$(PROJECT): $(SRCS) vortex_afu.h - verilator --exe --cc $(TOP) --top-module $(TOP) $(RTL_INCLUDE) $(VL_FLAGS) $(SRCS) -CFLAGS '$(CFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT) - make -j -C obj_dir -f V$(TOP).mk - -clean: - rm -rf $(PROJECT) obj_dir ../scope-defs.h $(RTL_DIR)/scope-defs.vh vortex_afu.h diff --git a/driver/opae/vlsim/ram.h b/driver/opae/vlsim/ram.h deleted file mode 100644 index 0ddd3e47..00000000 --- a/driver/opae/vlsim/ram.h +++ /dev/null @@ -1,64 +0,0 @@ -#pragma once - -#include -#include - -class RAM { -private: - - mutable uint8_t *mem_[(1 << 12)]; - - uint8_t *get(uint32_t address) const { - uint32_t block_addr = address >> 20; - uint32_t block_offset = address & 0x000FFFFF; - if (mem_[block_addr] == NULL) { - mem_[block_addr] = new uint8_t[(1 << 20)]; - } - return mem_[block_addr] + block_offset; - } - -public: - - RAM() { - for (uint32_t i = 0; i < (1 << 12); i++) { - mem_[i] = NULL; - } - } - - ~RAM() { - this->clear(); - } - - size_t size() const { - return (1ull << 32); - } - - void clear() { - for (uint32_t i = 0; i < (1 << 12); i++) { - if (mem_[i]) { - delete [] mem_[i]; - mem_[i] = NULL; - } - } - } - - void read(uint32_t address, uint32_t length, uint8_t *data) const { - for (unsigned i = 0; i < length; i++) { - data[i] = *this->get(address + i); - } - } - - void write(uint32_t address, uint32_t length, const uint8_t *data) { - for (unsigned i = 0; i < length; i++) { - *this->get(address + i) = data[i]; - } - } - - uint8_t& operator[](uint32_t address) { - return *get(address); - } - - const uint8_t& operator[](uint32_t address) const { - return *get(address); - } -}; \ No newline at end of file diff --git a/driver/opae/vortex_afu.h b/driver/opae/vortex_afu.h deleted file mode 100644 index 40836450..00000000 --- a/driver/opae/vortex_afu.h +++ /dev/null @@ -1,24 +0,0 @@ -// -// Generated by afu_json_mgr from ../../hw/opae/vortex_afu.json -// - -#ifndef __AFU_JSON_INFO__ -#define __AFU_JSON_INFO__ - -#define AFU_ACCEL_NAME "vortex_afu" -#define AFU_ACCEL_UUID "35F9452B-25C2-434C-93D5-6F8C60DB361C" -#define AFU_IMAGE_CMD_MEM_READ 1 -#define AFU_IMAGE_CMD_MEM_WRITE 2 -#define AFU_IMAGE_CMD_RUN 3 -#define AFU_IMAGE_MMIO_CMD_TYPE 10 -#define AFU_IMAGE_MMIO_DATA_SIZE 16 -#define AFU_IMAGE_MMIO_IO_ADDR 12 -#define AFU_IMAGE_MMIO_MEM_ADDR 14 -#define AFU_IMAGE_MMIO_SCOPE_READ 20 -#define AFU_IMAGE_MMIO_SCOPE_WRITE 22 -#define AFU_IMAGE_MMIO_DEV_CAPS 24 -#define AFU_IMAGE_MMIO_STATUS 18 -#define AFU_IMAGE_POWER 0 -#define AFU_TOP_IFC "ccip_std_afu_avalon_mm" - -#endif // __AFU_JSON_INFO__ diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index 73081953..87bd7980 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -1,87 +1,38 @@ -CFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors -#CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors +RTLSIM_DIR = ../../sim/rtlsim -CFLAGS += -DUSE_RTLSIM -fPIC -Wno-maybe-uninitialized -CFLAGS += -I../../include -I../../../hw/simulate -I../../../hw +CXXFLAGS += -std=c++11 -O2 -DNDEBUG -Wall -Wextra -pedantic -Wfatal-errors +#CXXFLAGS += -std=c++11 -O0 -g -Wall -Wextra -pedantic -Wfatal-errors -# control RTL debug print states -DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE -DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_ICACHE -DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_DCACHE -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_BANK -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSHR -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_TAG -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_DATA -DBG_PRINT_FLAGS += -DDBG_PRINT_MEM -DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE -DBG_PRINT_FLAGS += -DDBG_PRINT_AVS -DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE -DBG_PRINT_FLAGS += -DDBG_PRINT_TEX +CXXFLAGS += -I../include -I../../hw -I$(RTLSIM_DIR) -I$(RTLSIM_DIR)/../common -DBG_FLAGS += $(DBG_PRINT_FLAGS) -DBG_FLAGS += -DDBG_CACHE_REQ_INFO +LDFLAGS += $(RTLSIM_DIR)/librtlsim.a -CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=1 +# Position independent code +CXXFLAGS += -fPIC -CFLAGS += $(CONFIGS) -CFLAGS += -DDUMP_PERF_STATS +# Add external configuration +CXXFLAGS += $(CONFIGS) + +# Dump perf stats +CXXFLAGS += -DDUMP_PERF_STATS LDFLAGS += -shared -pthread -#LDFLAGS += -dynamiclib -pthread -TOP = Vortex - -RTL_DIR = ../../hw/rtl -DPI_DIR = ../../hw/dpi - -SRCS = vortex.cpp ../common/vx_utils.cpp ../../hw/simulate/simulator.cpp -SRCS += $(DPI_DIR)/util_dpi.cpp $(DPI_DIR)/float_dpi.cpp - -FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(DPI_DIR) -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src -I$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(RTL_DIR)/fp_cores/fpnew/src -TEX_INCLUDE = -I$(RTL_DIR)/tex_unit -RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache $(FPU_INCLUDE) $(TEX_INCLUDE) - -VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic -VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO -VL_FLAGS += --x-initial unique --x-assign unique -VL_FLAGS += verilator.vlt -VL_FLAGS += $(CONFIGS) - -# Enable Verilator multithreaded simulation -#THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') -#VL_FLAGS += --threads $(THREADS) - -# Debugigng -ifdef DEBUG - VL_FLAGS += -DVCD_OUTPUT --trace --trace-structs $(DBG_FLAGS) - CFLAGS += -DVCD_OUTPUT $(DBG_FLAGS) -else - VL_FLAGS += -DNDEBUG - CFLAGS += -DNDEBUG -endif +SRCS = vortex.cpp ../common/vx_utils.cpp # Enable perf counters ifdef PERF - VL_FLAGS += -DPERF_ENABLE - CFLAGS += -DPERF_ENABLE + CXXFLAGS += -DPERF_ENABLE endif -# ALU backend -VL_FLAGS += -DIMUL_DPI -VL_FLAGS += -DIDIV_DPI - -# FPU backend -FPU_CORE ?= FPU_DPI -VL_FLAGS += -D$(FPU_CORE) - PROJECT = libvortex.so -# PROJECT = libvortex.dylib all: $(PROJECT) $(PROJECT): $(SRCS) - verilator --exe --cc $(TOP) --top-module $(TOP) $(RTL_INCLUDE) $(VL_FLAGS) $(SRCS) -CFLAGS '$(CFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT) - make -j -C obj_dir -f V$(TOP).mk + $(MAKE) -C $(RTLSIM_DIR) static + $(CXX) $(CXXFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT) clean: - rm -rf $(PROJECT) obj_dir + $(MAKE) -C $(RTLSIM_DIR) clean-static + rm -rf $(PROJECT) *.o .depend \ No newline at end of file diff --git a/driver/rtlsim/ram.h b/driver/rtlsim/ram.h deleted file mode 100644 index 0ddd3e47..00000000 --- a/driver/rtlsim/ram.h +++ /dev/null @@ -1,64 +0,0 @@ -#pragma once - -#include -#include - -class RAM { -private: - - mutable uint8_t *mem_[(1 << 12)]; - - uint8_t *get(uint32_t address) const { - uint32_t block_addr = address >> 20; - uint32_t block_offset = address & 0x000FFFFF; - if (mem_[block_addr] == NULL) { - mem_[block_addr] = new uint8_t[(1 << 20)]; - } - return mem_[block_addr] + block_offset; - } - -public: - - RAM() { - for (uint32_t i = 0; i < (1 << 12); i++) { - mem_[i] = NULL; - } - } - - ~RAM() { - this->clear(); - } - - size_t size() const { - return (1ull << 32); - } - - void clear() { - for (uint32_t i = 0; i < (1 << 12); i++) { - if (mem_[i]) { - delete [] mem_[i]; - mem_[i] = NULL; - } - } - } - - void read(uint32_t address, uint32_t length, uint8_t *data) const { - for (unsigned i = 0; i < length; i++) { - data[i] = *this->get(address + i); - } - } - - void write(uint32_t address, uint32_t length, const uint8_t *data) { - for (unsigned i = 0; i < length; i++) { - *this->get(address + i) = data[i]; - } - } - - uint8_t& operator[](uint32_t address) { - return *get(address); - } - - const uint8_t& operator[](uint32_t address) const { - return *get(address); - } -}; \ No newline at end of file diff --git a/driver/rtlsim/vortex.cpp b/driver/rtlsim/vortex.cpp index 544f0f15..64fcd72e 100644 --- a/driver/rtlsim/vortex.cpp +++ b/driver/rtlsim/vortex.cpp @@ -8,20 +8,15 @@ #include #include -#include +#include +#include #include -/////////////////////////////////////////////////////////////////////////////// - -inline size_t align_size(size_t size, size_t alignment) { - assert(0 == (alignment & (alignment - 1))); - return (size + alignment - 1) & ~(alignment - 1); -} +using namespace vortex; /////////////////////////////////////////////////////////////////////////////// class vx_device; - class vx_buffer { public: vx_buffer(size_t size, vx_device* device) @@ -59,7 +54,7 @@ private: class vx_device { public: - vx_device() { + vx_device() : ram_((1<<12), (1<<20)) { mem_allocation_ = ALLOC_BASE_ADDR; } @@ -84,16 +79,16 @@ public: if (dest_addr + asize > ram_.size()) return -1; - /*printf("VXDRV: upload %d bytes from 0x%lx to 0x%lx", size, (uint8_t*)src + src_offset, dest_addr); - if (size <= 1024) { - printf(": "); - for (int i = asize-1; i >= 0; --i) { - printf("%x", *((uint8_t*)src + src_offset + i)); + /*printf("VXDRV: upload %ld bytes from 0x%lx:", size, uintptr_t((uint8_t*)src + src_offset)); + for (int i = 0; i < (asize / CACHE_BLOCK_SIZE); ++i) { + printf("\n0x%08lx=", dest_addr + i * CACHE_BLOCK_SIZE); + for (int j = 0; j < CACHE_BLOCK_SIZE; ++j) { + printf("%02x", *((uint8_t*)src + src_offset + i * CACHE_BLOCK_SIZE + CACHE_BLOCK_SIZE - 1 - j)); } } printf("\n");*/ - ram_.write(dest_addr, asize, (const uint8_t*)src + src_offset); + ram_.write((const uint8_t*)src + src_offset, dest_addr, asize); return 0; } @@ -102,13 +97,13 @@ public: if (src_addr + asize > ram_.size()) return -1; - ram_.read(src_addr, asize, (uint8_t*)dest + dest_offset); + ram_.read((uint8_t*)dest + dest_offset, src_addr, asize); - /*printf("VXDRV: download %d bytes from 0x%lx to 0x%lx", size, src_addr, (uint8_t*)dest + dest_offset); - if (size <= 1024) { - printf(": "); - for (int i = asize-1; i >= 0; --i) { - printf("%x", *((uint8_t*)dest + dest_offset + i)); + /*printf("VXDRV: download %ld bytes to 0x%lx:", size, uintptr_t((uint8_t*)dest + dest_offset)); + for (int i = 0; i < (asize / CACHE_BLOCK_SIZE); ++i) { + printf("\n0x%08lx=", src_addr + i * CACHE_BLOCK_SIZE); + for (int j = 0; j < CACHE_BLOCK_SIZE; ++j) { + printf("%02x", *((uint8_t*)dest + dest_offset + i * CACHE_BLOCK_SIZE + CACHE_BLOCK_SIZE - 1 - j)); } } printf("\n");*/ @@ -154,6 +149,34 @@ private: /////////////////////////////////////////////////////////////////////////////// +#ifdef DUMP_PERF_STATS +class AutoPerfDump { +private: + std::list devices_; + +public: + AutoPerfDump() {} + + ~AutoPerfDump() { + for (auto device : devices_) { + vx_dump_perf(device, stdout); + } + } + + void add_device(vx_device_h device) { + devices_.push_back(device); + } + + void remove_device(vx_device_h device) { + devices_.remove(device); + } +}; + +AutoPerfDump gAutoPerfDump; +#endif + +/////////////////////////////////////////////////////////////////////////////// + extern int vx_dev_caps(vx_device_h hdevice, unsigned caps_id, unsigned *value) { if (nullptr == hdevice) return -1; @@ -198,6 +221,10 @@ extern int vx_dev_open(vx_device_h* hdevice) { *hdevice = new vx_device(); +#ifdef DUMP_PERF_STATS + gAutoPerfDump.add_device(*hdevice); +#endif + return 0; } @@ -208,7 +235,8 @@ extern int vx_dev_close(vx_device_h hdevice) { vx_device *device = ((vx_device*)hdevice); #ifdef DUMP_PERF_STATS - vx_dump_perf(device, stdout); + gAutoPerfDump.remove_device(hdevice); + vx_dump_perf(hdevice, stdout); #endif delete device; diff --git a/driver/simx/Makefile b/driver/simx/Makefile index 1a7cf33e..ba6f0284 100644 --- a/driver/simx/Makefile +++ b/driver/simx/Makefile @@ -1,37 +1,29 @@ -PROJECT = libvortex.so -#PROJECT = libvortex.dylib - -SIMX_DIR = ../../simX +SIMX_DIR = ../../sim/simX CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors #CXXFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors -CXXFLAGS += -DUSE_SIMX -fPIC -Wno-maybe-uninitialized -CXXFLAGS += -I../include -I../../hw -I$(SIMX_DIR) - -CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=1 - +CXXFLAGS += -fPIC -Wno-maybe-uninitialized +CXXFLAGS += -I../include -I../../hw -I$(SIMX_DIR) -I$(SIMX_DIR)/../common CXXFLAGS += $(CONFIGS) CXXFLAGS += -DDUMP_PERF_STATS LDFLAGS += -shared -pthread -#LDFLAGS += -dynamiclib -pthread +LDFLAGS += $(SIMX_DIR)/libsimX.a SRCS = vortex.cpp ../common/vx_utils.cpp -SRCS += $(SIMX_DIR)/util.cpp $(SIMX_DIR)/args.cpp $(SIMX_DIR)/mem.cpp $(SIMX_DIR)/pipeline.cpp $(SIMX_DIR)/warp.cpp $(SIMX_DIR)/core.cpp $(SIMX_DIR)/decode.cpp $(SIMX_DIR)/execute.cpp -# Debugigng -ifndef DEBUG - CXXFLAGS += -DNDEBUG -endif +PROJECT = libvortex.so all: $(PROJECT) $(PROJECT): $(SRCS) + $(MAKE) -C $(SIMX_DIR) static $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ .depend: $(SRCS) $(CXX) $(CXXFLAGS) -MM $^ > .depend; clean: + $(MAKE) -C $(SIMX_DIR) clean-static rm -rf $(PROJECT) *.o .depend \ No newline at end of file diff --git a/driver/simx/vortex.cpp b/driver/simx/vortex.cpp index d2a6ca76..5ad4242b 100644 --- a/driver/simx/vortex.cpp +++ b/driver/simx/vortex.cpp @@ -10,15 +10,11 @@ #include #include #include +#include -#define PAGE_SIZE 4096 +#define PAGE_SIZE 4096 -/////////////////////////////////////////////////////////////////////////////// - -inline size_t align_size(size_t size, size_t alignment) { - assert(0 == (alignment & (alignment - 1))); - return (size + alignment - 1) & ~(alignment - 1); -} +using namespace vortex; /////////////////////////////////////////////////////////////////////////////// @@ -74,7 +70,7 @@ public: mem_allocation_ = ALLOC_BASE_ADDR; mmu_.attach(ram_, 0, 0xffffffff); for (int i = 0; i < arch_.num_cores(); ++i) { - cores_[i] = std::make_shared(arch_, decoder_, mmu_, i); + cores_[i] = std::make_shared(arch_, decoder_, mmu_, i); } } @@ -101,7 +97,7 @@ public: if (dest_addr + asize > ram_.size()) return -1; - ram_.write(dest_addr, (const uint8_t*)src + src_offset, asize); + ram_.write((const uint8_t*)src + src_offset, dest_addr, asize); /*printf("VXDRV: upload %d bytes to 0x%x\n", size, dest_addr); for (int i = 0; i < size; i += 4) { @@ -116,7 +112,7 @@ public: if (src_addr + asize > ram_.size()) return -1; - ram_.read(src_addr, (uint8_t*)dest + dest_offset, asize); + ram_.read((uint8_t*)dest + dest_offset, src_addr, asize); /*printf("VXDRV: download %d bytes from 0x%x\n", size, src_addr); for (int i = 0; i < size; i += 4) { @@ -209,25 +205,57 @@ private: device->thread_proc(); } - vortex::ArchDef arch_; - vortex::Decoder decoder_; - vortex::MemoryUnit mmu_; - std::vector> cores_; + ArchDef arch_; + Decoder decoder_; + MemoryUnit mmu_; + std::vector> cores_; bool is_done_; bool is_running_; size_t mem_allocation_; std::thread thread_; - vortex::RAM ram_; + RAM ram_; std::mutex mutex_; }; /////////////////////////////////////////////////////////////////////////////// +#ifdef DUMP_PERF_STATS +class AutoPerfDump { +private: + std::list devices_; + +public: + AutoPerfDump() {} + + ~AutoPerfDump() { + for (auto device : devices_) { + vx_dump_perf(device, stdout); + } + } + + void add_device(vx_device_h device) { + devices_.push_back(device); + } + + void remove_device(vx_device_h device) { + devices_.remove(device); + } +}; + +AutoPerfDump gAutoPerfDump; +#endif + +/////////////////////////////////////////////////////////////////////////////// + extern int vx_dev_open(vx_device_h* hdevice) { if (nullptr == hdevice) return -1; - *hdevice = new vx_device(); + *hdevice = new vx_device(); + +#ifdef DUMP_PERF_STATS + gAutoPerfDump.add_device(*hdevice); +#endif return 0; } @@ -239,7 +267,8 @@ extern int vx_dev_close(vx_device_h hdevice) { vx_device *device = ((vx_device*)hdevice); #ifdef DUMP_PERF_STATS - vx_dump_perf(device, stdout); + gAutoPerfDump.remove_device(hdevice); + vx_dump_perf(hdevice, stdout); #endif delete device; diff --git a/driver/vlsim/Makefile b/driver/vlsim/Makefile new file mode 100644 index 00000000..58e8d566 --- /dev/null +++ b/driver/vlsim/Makefile @@ -0,0 +1,62 @@ +VLSIM_DIR = ../../sim/vlsim + +RTL_DIR=../../hw/rtl + +SCRIPT_DIR=../../hw/scripts + +CXXFLAGS += -std=c++11 -O2 -DNDEBUG -Wall -Wextra -pedantic -Wfatal-errors +#CXXFLAGS += -std=c++11 -O0 -g -Wall -Wextra -pedantic -Wfatal-errors + +CXXFLAGS += -I. -I../include -I../../hw -I$(VLSIM_DIR) + +LDFLAGS += $(VLSIM_DIR)/libopae-c-vlsim.a + +# Position independent code +CXXFLAGS += -fPIC + +# Add external configuration +CXXFLAGS += $(CONFIGS) + +# Dump perf stats +CXXFLAGS += -DDUMP_PERF_STATS + +LDFLAGS += -shared -pthread + +SRCS = ../common/opae.cpp ../common/vx_utils.cpp + +# Enable scope analyzer +ifdef SCOPE + CXXFLAGS += -DSCOPE + SRCS += ../common/vx_scope.cpp + SCOPE_H = scope-defs.h +endif + +# Enable perf counters +ifdef PERF + CXXFLAGS += -DPERF_ENABLE +endif + +PROJECT = libvortex.so + +all: $(PROJECT) + +scope-defs.h: $(SCRIPT_DIR)/scope.json + $(SCRIPT_DIR)/scope.py $(CONFIGS) -cc scope-defs.h -vl $(RTL_DIR)/scope-defs.vh $(SCRIPT_DIR)/scope.json + +# generate scope data +scope: scope-defs.h + +$(PROJECT): $(SRCS) $(SCOPE_H) + $(SCOPE_ENABLE) $(PERF_ENABLE) $(MAKE) -C $(VLSIM_DIR) static + $(CXX) $(CXXFLAGS) -DUSE_VLSIM $(SRCS) $(LDFLAGS) -o $(PROJECT) + +.depend: $(SRCS) + $(CXX) $(CXXFLAGS) -MM $(SRCS) > .depend; + +clean: + $(MAKE) -C $(VLSIM_DIR) clean-static + rm -rf $(PROJECT) *.o .depend scope-defs.h + +ifneq ($(MAKECMDGOALS),clean) + -include .depend +endif diff --git a/hw/Makefile b/hw/Makefile index 425e58d9..bb834e32 100644 --- a/hw/Makefile +++ b/hw/Makefile @@ -1,9 +1,12 @@ -.PHONY: build_config +RTL_DIR=./rtl +SCRIPT_DIR=./scripts -build_config: ./rtl/VX_config.vh - ./scripts/gen_config.py -i ./rtl/VX_config.vh -o ./VX_config.h - $(MAKE) -C simulate +all: VX_config.h + +VX_config.h: $(RTL_DIR)/VX_config.vh + $(SCRIPT_DIR)/gen_config.py -i $(RTL_DIR)/VX_config.vh -o VX_config.h clean: - rm -f ./VX_config.h - $(MAKE) -C simulate clean \ No newline at end of file + rm -f VX_config.h + +.PHONY: VX_config.h \ No newline at end of file diff --git a/hw/configs/.gitignore b/hw/configs/.gitignore deleted file mode 100644 index d628dca5..00000000 --- a/hw/configs/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -*.v -*.sh diff --git a/hw/configs/.gitkeep b/hw/configs/.gitkeep deleted file mode 100644 index e69de29b..00000000 diff --git a/hw/dpi/float_dpi.cpp b/hw/dpi/float_dpi.cpp index 70d49eae..7d78dde8 100644 --- a/hw/dpi/float_dpi.cpp +++ b/hw/dpi/float_dpi.cpp @@ -4,293 +4,168 @@ #include #include #include +#include #include "svdpi.h" #include "verilated_vpi.h" #include "VX_config.h" extern "C" { - void dpi_fadd(int a, int b, int frm, int* result, int* fflags); - void dpi_fsub(int a, int b, int frm, int* result, int* fflags); - void dpi_fmul(int a, int b, int frm, int* result, int* fflags); - void dpi_fmadd(int a, int b, int c, int frm, int* result, int* fflags); - void dpi_fmsub(int a, int b, int c, int frm, int* result, int* fflags); - void dpi_fnmadd(int a, int b, int c, int frm, int* result, int* fflags); - void dpi_fnmsub(int a, int b, int c, int frm, int* result, int* fflags); + void dpi_fadd(bool enable, int a, int b, const svBitVecVal* frm, int* result, svBitVecVal* fflags); + void dpi_fsub(bool enable, int a, int b, const svBitVecVal* frm, int* result, svBitVecVal* fflags); + void dpi_fmul(bool enable, int a, int b, const svBitVecVal* frm, int* result, svBitVecVal* fflags); + void dpi_fmadd(bool enable, int a, int b, int c, const svBitVecVal* frm, int* result, svBitVecVal* fflags); + void dpi_fmsub(bool enable, int a, int b, int c, const svBitVecVal* frm, int* result, svBitVecVal* fflags); + void dpi_fnmadd(bool enable, int a, int b, int c, const svBitVecVal* frm, int* result, svBitVecVal* fflags); + void dpi_fnmsub(bool enable, int a, int b, int c, const svBitVecVal* frm, int* result, svBitVecVal* fflags); - void dpi_fdiv(int a, int b, int frm, int* result, int* fflags); - void dpi_fsqrt(int a, int frm, int* result, int* fflags); + void dpi_fdiv(bool enable, int a, int b, const svBitVecVal* frm, int* result, svBitVecVal* fflags); + void dpi_fsqrt(bool enable, int a, const svBitVecVal* frm, int* result, svBitVecVal* fflags); - void dpi_ftoi(int a, int frm, int* result, int* fflags); - void dpi_ftou(int a, int frm, int* result, int* fflags); - void dpi_itof(int a, int frm, int* result, int* fflags); - void dpi_utof(int a, int frm, int* result, int* fflags); + void dpi_ftoi(bool enable, int a, const svBitVecVal* frm, int* result, svBitVecVal* fflags); + void dpi_ftou(bool enable, int a, const svBitVecVal* frm, int* result, svBitVecVal* fflags); + void dpi_itof(bool enable, int a, const svBitVecVal* frm, int* result, svBitVecVal* fflags); + void dpi_utof(bool enable, int a, const svBitVecVal* frm, int* result, svBitVecVal* fflags); - void dpi_fclss(int a, int* result); - void dpi_fsgnj(int a, int b, int* result); - void dpi_fsgnjn(int a, int b, int* result); - void dpi_fsgnjx(int a, int b, int* result); + void dpi_fclss(bool enable, int a, int* result); + void dpi_fsgnj(bool enable, int a, int b, int* result); + void dpi_fsgnjn(bool enable, int a, int b, int* result); + void dpi_fsgnjx(bool enable, int a, int b, int* result); - void dpi_flt(int a, int b, int* result, int* fflags); - void dpi_fle(int a, int b, int* result, int* fflags); - void dpi_feq(int a, int b, int* result, int* fflags); - void dpi_fmin(int a, int b, int* result, int* fflags); - void dpi_fmax(int a, int b, int* result, int* fflags); + void dpi_flt(bool enable, int a, int b, int* result, svBitVecVal* fflags); + void dpi_fle(bool enable, int a, int b, int* result, svBitVecVal* fflags); + void dpi_feq(bool enable, int a, int b, int* result, svBitVecVal* fflags); + void dpi_fmin(bool enable, int a, int b, int* result, svBitVecVal* fflags); + void dpi_fmax(bool enable, int a, int b, int* result, svBitVecVal* fflags); } -union Float_t { - float f; - int i; - struct { - uint32_t man : 23; - uint32_t exp : 8; - uint32_t sign : 1; - } parts; -}; - -void dpi_fadd(int a, int b, int frm, int* result, int* fflags) { - Float_t fa, fb, fr; - - fa.i = a; - fb.i = b; - fr.f = fa.f + fb.f; - - *result = fr.i; - *fflags = 0; +void dpi_fadd(bool enable, int a, int b, const svBitVecVal* frm, int* result, svBitVecVal* fflags) { + if (!enable) + return; + *result = rv_fadd(a, b, (*frm & 0x7), fflags); } -void dpi_fsub(int a, int b, int frm, int* result, int* fflags) { - Float_t fa, fb, fr; - - fa.i = a; - fb.i = b; - fr.f = fa.f - fb.f; - - *result = fr.i; - *fflags = 0; +void dpi_fsub(bool enable, int a, int b, const svBitVecVal* frm, int* result, svBitVecVal* fflags) { + if (!enable) + return; + *result = rv_fsub(a, b, (*frm & 0x7), fflags); } -void dpi_fmul(int a, int b, int frm, int* result, int* fflags) { - Float_t fa, fb, fr; - - fa.i = a; - fb.i = b; - fr.f = fa.f * fb.f; - - *result = fr.i; - *fflags = 0; +void dpi_fmul(bool enable, int a, int b, const svBitVecVal* frm, int* result, svBitVecVal* fflags) { + if (!enable) + return; + *result = rv_fmul(a, b, (*frm & 0x7), fflags); } -void dpi_fmadd(int a, int b, int c, int frm, int* result, int* fflags) { - Float_t fa, fb, fc, fr; - - fa.i = a; - fb.i = b; - fc.i = c; - fr.f = fa.f * fb.f + fc.f; - - *result = fr.i; - *fflags = 0; +void dpi_fmadd(bool enable, int a, int b, int c, const svBitVecVal* frm, int* result, svBitVecVal* fflags) { + if (!enable) + return; + *result = rv_fmadd(a, b, c, (*frm & 0x7), fflags); } -void dpi_fmsub(int a, int b, int c, int frm, int* result, int* fflags) { - Float_t fa, fb, fc, fr; - - fa.i = a; - fb.i = b; - fc.i = c; - fr.f = fa.f * fb.f - fc.f; - - *result = fr.i; - *fflags = 0; +void dpi_fmsub(bool enable, int a, int b, int c, const svBitVecVal* frm, int* result, svBitVecVal* fflags) { + if (!enable) + return; + *result = rv_fmsub(a, b, c, (*frm & 0x7), fflags); } -void dpi_fnmadd(int a, int b, int c, int frm, int* result, int* fflags) { - Float_t fa, fb, fc, fr; - - fa.i = a; - fb.i = b; - fc.i = c; - fr.f = -(fa.f * fb.f + fc.f); - - *result = fr.i; - *fflags = 0; +void dpi_fnmadd(bool enable, int a, int b, int c, const svBitVecVal* frm, int* result, svBitVecVal* fflags) { + if (!enable) + return; + *result = rv_fnmadd(a, b, c, (*frm & 0x7), fflags); } -void dpi_fnmsub(int a, int b, int c, int frm, int* result, int* fflags) { - Float_t fa, fb, fc, fr; - - fa.i = a; - fb.i = b; - fc.i = c; - fr.f = -(fa.f * fb.f - fc.f); - - *result = fr.i; - *fflags = 0; +void dpi_fnmsub(bool enable, int a, int b, int c, const svBitVecVal* frm, int* result, svBitVecVal* fflags) { + if (!enable) + return; + *result = rv_fnmsub(a, b, c, (*frm & 0x7), fflags); } -void dpi_fdiv(int a, int b, int frm, int* result, int* fflags) { - Float_t fa, fb, fr; - - fa.i = a; - fb.i = b; - fr.f = fa.f / fb.f; - - *result = fr.i; - *fflags = 0; +void dpi_fdiv(bool enable, int a, int b, const svBitVecVal* frm, int* result, svBitVecVal* fflags) { + if (!enable) + return; + *result = rv_fdiv(a, b, (*frm & 0x7), fflags); } -void dpi_fsqrt(int a, int frm, int* result, int* fflags) { - Float_t fa, fr; - - fa.i = a; - fr.f = sqrtf(fa.f); - - *result = fr.i; - *fflags = 0; +void dpi_fsqrt(bool enable, int a, const svBitVecVal* frm, int* result, svBitVecVal* fflags) { + if (!enable) + return; + *result = rv_fsqrt(a, (*frm & 0x7), fflags); } -void dpi_ftoi(int a, int frm, int* result, int* fflags) { - Float_t fa, fr; - - fa.i = a; - fr.i = int(fa.f); - - *result = fr.i; - *fflags = 0; +void dpi_ftoi(bool enable, int a, const svBitVecVal* frm, int* result, svBitVecVal* fflags) { + if (!enable) + return; + *result = rv_ftoi(a, (*frm & 0x7), fflags); } -void dpi_ftou(int a, int frm, int* result, int* fflags) { - Float_t fa, fr; - - fa.i = a; - fr.i = unsigned(fa.f); - - *result = fr.i; - *fflags = 0; +void dpi_ftou(bool enable, int a, const svBitVecVal* frm, int* result, svBitVecVal* fflags) { + if (!enable) + return; + *result = rv_ftou(a, (*frm & 0x7), fflags); } -void dpi_itof(int a, int frm, int* result, int* fflags) { - Float_t fa, fr; - - fr.f = (float)a; - - *result = fr.i; - *fflags = 0; +void dpi_itof(bool enable, int a, const svBitVecVal* frm, int* result, svBitVecVal* fflags) { + if (!enable) + return; + *result = rv_itof(a, (*frm & 0x7), fflags); } -void dpi_utof(int a, int frm, int* result, int* fflags) { - Float_t fa, fr; - - unsigned ua = a; - fr.f = (float)ua; - - *result = fr.i; - *fflags = 0; +void dpi_utof(bool enable, int a, const svBitVecVal* frm, int* result, svBitVecVal* fflags) { + if (!enable) + return; + *result = rv_utof(a, (*frm & 0x7), fflags); } -void dpi_flt(int a, int b, int* result, int* fflags) { - Float_t fa, fb, fr; - - fa.i = a; - fb.i = b; - fr.f = fa.f < fb.f; - - *result = fr.i; - *fflags = 0; +void dpi_flt(bool enable, int a, int b, int* result, svBitVecVal* fflags) { + if (!enable) + return; + *result = rv_flt(a, b, fflags); } -void dpi_fle(int a, int b, int* result, int* fflags) { - Float_t fa, fb, fr; - - fa.i = a; - fb.i = b; - fr.f = fa.f <= fb.f; - - *result = fr.i; - *fflags = 0; +void dpi_fle(bool enable, int a, int b, int* result, svBitVecVal* fflags) { + if (!enable) + return; + *result = rv_fle(a, b, fflags); } -void dpi_feq(int a, int b, int* result, int* fflags) { - Float_t fa, fb, fr; - - fa.i = a; - fb.i = b; - fr.f = fa.f == fb.f; - - *result = fr.i; - *fflags = 0; +void dpi_feq(bool enable, int a, int b, int* result, svBitVecVal* fflags) { + if (!enable) + return; + *result = rv_feq(a, b, fflags); } -void dpi_fmin(int a, int b, int* result, int* fflags) { - Float_t fa, fb, fr; - - fa.i = a; - fb.i = b; - fr.f = std::min(fa.f, fb.f); - - *result = fr.i; - *fflags = 0; +void dpi_fmin(bool enable, int a, int b, int* result, svBitVecVal* fflags) { + if (!enable) + return; + *result = rv_fmin(a, b, fflags); } -void dpi_fmax(int a, int b, int* result, int* fflags) { - Float_t fa, fb, fr; - - fa.i = a; - fb.i = b; - fr.f = std::max(fa.f, fb.f); - - *result = fr.i; - *fflags = 0; +void dpi_fmax(bool enable, int a, int b, int* result, svBitVecVal* fflags) { + if (!enable) + return; + *result = rv_fmax(a, b, fflags); } -void dpi_fclss(int a, int* result) { - - int r = 0; // clear all bits - - bool fsign = (a >> 31); - uint32_t expo = (a >> 23) & 0xFF; - uint32_t fraction = a & 0x7FFFFF; - - if ((expo == 0) && (fraction == 0)) { - r = fsign ? (1 << 3) : (1 << 4); // +/- 0 - } else if ((expo == 0) && (fraction != 0)) { - r = fsign ? (1 << 2) : (1 << 5); // +/- subnormal - } else if ((expo == 0xFF) && (fraction == 0)) { - r = fsign ? (1<<0) : (1<<7); // +/- infinity - } else if ((expo == 0xFF ) && (fraction != 0)) { - if (!fsign && (fraction == 0x00400000)) { - r = (1 << 9); // quiet NaN - } else { - r = (1 << 8); // signaling NaN - } - } else { - r = fsign ? (1 << 1) : (1 << 6); // +/- normal - } - - *result = r; +void dpi_fclss(bool enable, int a, int* result) { + if (!enable) + return; + *result = rv_fclss(a); } -void dpi_fsgnj(int a, int b, int* result) { - - int sign = b & 0x80000000; - int r = sign | (a & 0x7FFFFFFF); - - *result = r; +void dpi_fsgnj(bool enable, int a, int b, int* result) { + if (!enable) + return; + *result = rv_fsgnj(a, b); } -void dpi_fsgnjn(int a, int b, int* result) { - - int sign = ~b & 0x80000000; - int r = sign | (a & 0x7FFFFFFF); - - *result = r; +void dpi_fsgnjn(bool enable, int a, int b, int* result) { + if (!enable) + return; + *result = rv_fsgnjn(a, b); } -void dpi_fsgnjx(int a, int b, int* result) { - - int sign1 = a & 0x80000000; - int sign2 = b & 0x80000000; - int r = (sign1 ^ sign2) | (a & 0x7FFFFFFF); - - *result = r; +void dpi_fsgnjx(bool enable, int a, int b, int* result) { + if (!enable) + return; + *result = rv_fsgnjx(a, b); } \ No newline at end of file diff --git a/hw/dpi/float_dpi.vh b/hw/dpi/float_dpi.vh index bba4c891..968f8028 100644 --- a/hw/dpi/float_dpi.vh +++ b/hw/dpi/float_dpi.vh @@ -1,31 +1,31 @@ `ifndef FLOAT_DPI `define FLOAT_DPI -import "DPI-C" context function void dpi_fadd(input int a, input int b, input bit[2:0] frm, output int result, output bit[4:0] fflags); -import "DPI-C" context function void dpi_fsub(input int a, input int b, input bit[2:0] frm, output int result, output bit[4:0] fflags); -import "DPI-C" context function void dpi_fmul(input int a, input int b, input bit[2:0] frm, output int result, output bit[4:0] fflags); -import "DPI-C" context function void dpi_fmadd(input int a, input int b, input int c, input bit[2:0] frm, output int result, output bit[4:0] fflags); -import "DPI-C" context function void dpi_fmsub(input int a, input int b, input int c, input bit[2:0] frm, output int result, output bit[4:0] fflags); -import "DPI-C" context function void dpi_fnmadd(input int a, input int b, input int c, input bit[2:0] frm, output int result, output bit[4:0] fflags); -import "DPI-C" context function void dpi_fnmsub(input int a, input int b, input int c, input bit[2:0] frm, output int result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fadd(input logic enable, input int a, input int b, input bit[2:0] frm, output int result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fsub(input logic enable, input int a, input int b, input bit[2:0] frm, output int result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fmul(input logic enable, input int a, input int b, input bit[2:0] frm, output int result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fmadd(input logic enable, input int a, input int b, input int c, input bit[2:0] frm, output int result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fmsub(input logic enable, input int a, input int b, input int c, input bit[2:0] frm, output int result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fnmadd(input logic enable, input int a, input int b, input int c, input bit[2:0] frm, output int result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fnmsub(input logic enable, input int a, input int b, input int c, input bit[2:0] frm, output int result, output bit[4:0] fflags); -import "DPI-C" context function void dpi_fdiv(input int a, input int b, input bit[2:0] frm, output int result, output bit[4:0] fflags); -import "DPI-C" context function void dpi_fsqrt(input int a, input bit[2:0] frm, output int result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fdiv(input logic enable, input int a, input int b, input bit[2:0] frm, output int result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fsqrt(input logic enable, input int a, input bit[2:0] frm, output int result, output bit[4:0] fflags); -import "DPI-C" context function void dpi_ftoi(input int a, input bit[2:0] frm, output int result, output bit[4:0] fflags); -import "DPI-C" context function void dpi_ftou(input int a, input bit[2:0] frm, output int result, output bit[4:0] fflags); -import "DPI-C" context function void dpi_itof(input int a, input bit[2:0] frm, output int result, output bit[4:0] fflags); -import "DPI-C" context function void dpi_utof(input int a, input bit[2:0] frm, output int result, output bit[4:0] fflags); +import "DPI-C" function void dpi_ftoi(input logic enable, input int a, input bit[2:0] frm, output int result, output bit[4:0] fflags); +import "DPI-C" function void dpi_ftou(input logic enable, input int a, input bit[2:0] frm, output int result, output bit[4:0] fflags); +import "DPI-C" function void dpi_itof(input logic enable, input int a, input bit[2:0] frm, output int result, output bit[4:0] fflags); +import "DPI-C" function void dpi_utof(input logic enable, input int a, input bit[2:0] frm, output int result, output bit[4:0] fflags); -import "DPI-C" context function void dpi_fclss(input int a, output int result); -import "DPI-C" context function void dpi_fsgnj(input int a, input int b, output int result); -import "DPI-C" context function void dpi_fsgnjn(input int a, input int b, output int result); -import "DPI-C" context function void dpi_fsgnjx(input int a, input int b, output int result); +import "DPI-C" function void dpi_fclss(input logic enable, input int a, output int result); +import "DPI-C" function void dpi_fsgnj(input logic enable, input int a, input int b, output int result); +import "DPI-C" function void dpi_fsgnjn(input logic enable, input int a, input int b, output int result); +import "DPI-C" function void dpi_fsgnjx(input logic enable, input int a, input int b, output int result); -import "DPI-C" context function void dpi_flt(input int a, input int b, output int result, output bit[4:0] fflags); -import "DPI-C" context function void dpi_fle(input int a, input int b, output int result, output bit[4:0] fflags); -import "DPI-C" context function void dpi_feq(input int a, input int b, output int result, output bit[4:0] fflags); -import "DPI-C" context function void dpi_fmin(input int a, input int b, output int result, output bit[4:0] fflags); -import "DPI-C" context function void dpi_fmax(input int a, input int b, output int result, output bit[4:0] fflags); +import "DPI-C" function void dpi_flt(input logic enable, input int a, input int b, output int result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fle(input logic enable, input int a, input int b, output int result, output bit[4:0] fflags); +import "DPI-C" function void dpi_feq(input logic enable, input int a, input int b, output int result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fmin(input logic enable, input int a, input int b, output int result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fmax(input logic enable, input int a, input int b, output int result, output bit[4:0] fflags); `endif \ No newline at end of file diff --git a/hw/dpi/util_dpi.cpp b/hw/dpi/util_dpi.cpp index 9469bc6e..a8db1a53 100644 --- a/hw/dpi/util_dpi.cpp +++ b/hw/dpi/util_dpi.cpp @@ -9,13 +9,20 @@ #include "VX_config.h" extern "C" { - void dpi_imul(int a, int b, bool is_signed_a, bool is_signed_b, int* resultl, int* resulth); - void dpi_idiv(int a, int b, bool is_signed, int* quotient, int* remainder); + void dpi_imul(bool enable, int a, int b, bool is_signed_a, bool is_signed_b, int* resultl, int* resulth); + void dpi_idiv(bool enable, int a, int b, bool is_signed, int* quotient, int* remainder); int dpi_register(); void dpi_assert(int inst, bool cond, int delay); + + void dpi_trace(const char* format, ...); + void dpi_trace_start(); + void dpi_trace_stop(); } +bool sim_trace_enabled(); +void sim_trace_enable(bool enable); + class ShiftRegister { public: ShiftRegister() : init_(false), depth_(0) {} @@ -86,15 +93,18 @@ void dpi_assert(int inst, bool cond, int delay) { } } -void dpi_imul(int a, int b, bool is_signed_a, bool is_signed_b, int* resultl, int* resulth) { - uint64_t first = a; - uint64_t second = b; +void dpi_imul(bool enable, int a, int b, bool is_signed_a, bool is_signed_b, int* resultl, int* resulth) { + if (!enable) + return; - if (is_signed_a && (a & 0x80000000)) { + uint64_t first = *(uint32_t*)&a; + uint64_t second = *(uint32_t*)&b; + + if (is_signed_a && (first & 0x80000000)) { first |= 0xFFFFFFFF00000000; } - if (is_signed_b && (b & 0x80000000)) { + if (is_signed_b && (second & 0x80000000)) { second |= 0xFFFFFFFF00000000; } @@ -109,9 +119,12 @@ void dpi_imul(int a, int b, bool is_signed_a, bool is_signed_b, int* resultl, in *resulth = (result >> 32) & 0xFFFFFFFF; } -void dpi_idiv(int a, int b, bool is_signed, int* quotient, int* remainder) { - uint32_t dividen = a; - uint32_t divisor = b; +void dpi_idiv(bool enable, int a, int b, bool is_signed, int* quotient, int* remainder) { + if (!enable) + return; + + uint32_t dividen = *(uint32_t*)&a; + uint32_t divisor = *(uint32_t*)&b; if (is_signed) { if (b == 0) { @@ -133,4 +146,21 @@ void dpi_idiv(int a, int b, bool is_signed, int* quotient, int* remainder) { *remainder = dividen % divisor; } } +} + +void dpi_trace(const char* format, ...) { + if (!sim_trace_enabled()) + return; + va_list va; + va_start(va, format); + vprintf(format, va); + va_end(va); +} + +void dpi_trace_start() { + sim_trace_enable(true); +} + +void dpi_trace_stop() { + sim_trace_enable(false); } \ No newline at end of file diff --git a/hw/dpi/util_dpi.vh b/hw/dpi/util_dpi.vh index 553641a7..c1306ff4 100644 --- a/hw/dpi/util_dpi.vh +++ b/hw/dpi/util_dpi.vh @@ -1,10 +1,14 @@ `ifndef UTIL_DPI `define UTIL_DPI -import "DPI-C" context function void dpi_imul(input int a, input int b, input logic is_signed_a, input logic is_signed_b, output int resultl, output int resulth); -import "DPI-C" context function void dpi_idiv(input int a, input int b, input logic is_signed, output int quotient, output int remainder); +import "DPI-C" function void dpi_imul(input logic enable, input int a, input int b, input logic is_signed_a, input logic is_signed_b, output int resultl, output int resulth); +import "DPI-C" function void dpi_idiv(input logic enable, input int a, input int b, input logic is_signed, output int quotient, output int remainder); -import "DPI-C" context function int dpi_register(); -import "DPI-C" context function void dpi_assert(int inst, input logic cond, input int delay); +import "DPI-C" function int dpi_register(); +import "DPI-C" function void dpi_assert(int inst, input logic cond, input int delay); + +import "DPI-C" function void dpi_trace(input string format /*verilator sformat*/); +import "DPI-C" function void dpi_trace_start(); +import "DPI-C" function void dpi_trace_stop(); `endif \ No newline at end of file diff --git a/hw/rtl/VX_alu_unit.v b/hw/rtl/VX_alu_unit.sv similarity index 50% rename from hw/rtl/VX_alu_unit.v rename to hw/rtl/VX_alu_unit.sv index bb8068b8..129b1202 100644 --- a/hw/rtl/VX_alu_unit.v +++ b/hw/rtl/VX_alu_unit.sv @@ -3,15 +3,15 @@ module VX_alu_unit #( parameter CORE_ID = 0 ) ( - input wire clk, - input wire reset, + input wire clk, + input wire reset, // Inputs - VX_alu_req_if alu_req_if, + VX_alu_req_if.slave alu_req_if, // Outputs - VX_branch_ctl_if branch_ctl_if, - VX_commit_if alu_commit_if + VX_branch_ctl_if.master branch_ctl_if, + VX_commit_if.master alu_commit_if ); `UNUSED_PARAM (CORE_ID) @@ -22,15 +22,15 @@ module VX_alu_unit #( wire [`NUM_THREADS-1:0][31:0] shr_result; reg [`NUM_THREADS-1:0][31:0] msc_result; - wire stall_in, stall_out; + wire ready_in; `UNUSED_VAR (alu_req_if.op_mod) - wire is_br_op = `ALU_IS_BR(alu_req_if.op_mod); - wire [`ALU_BITS-1:0] alu_op = `ALU_OP(alu_req_if.op_type); - wire [`BR_BITS-1:0] br_op = `BR_OP(alu_req_if.op_type); - wire alu_signed = `ALU_SIGNED(alu_op); - wire [1:0] alu_op_class = `ALU_OP_CLASS(alu_op); - wire is_sub = (alu_op == `ALU_SUB); + wire is_br_op = `INST_ALU_IS_BR(alu_req_if.op_mod); + wire [`INST_ALU_BITS-1:0] alu_op = `INST_ALU_BITS'(alu_req_if.op_type); + wire [`INST_BR_BITS-1:0] br_op = `INST_BR_BITS'(alu_req_if.op_type); + wire alu_signed = `INST_ALU_SIGNED(alu_op); + wire [1:0] alu_op_class = `INST_ALU_OP_CLASS(alu_op); + wire is_sub = (alu_op == `INST_ALU_SUB); wire [`NUM_THREADS-1:0][31:0] alu_in1 = alu_req_if.rs1_data; wire [`NUM_THREADS-1:0][31:0] alu_in2 = alu_req_if.rs2_data; @@ -57,10 +57,10 @@ module VX_alu_unit #( for (genvar i = 0; i < `NUM_THREADS; i++) begin always @(*) begin case (alu_op) - `ALU_AND: msc_result[i] = alu_in1[i] & alu_in2_imm[i]; - `ALU_OR: msc_result[i] = alu_in1[i] | alu_in2_imm[i]; - `ALU_XOR: msc_result[i] = alu_in1[i] ^ alu_in2_imm[i]; - //`ALU_SLL, + `INST_ALU_AND: msc_result[i] = alu_in1[i] & alu_in2_imm[i]; + `INST_ALU_OR: msc_result[i] = alu_in1[i] | alu_in2_imm[i]; + `INST_ALU_XOR: msc_result[i] = alu_in1[i] ^ alu_in2_imm[i]; + //`INST_ALU_SLL, default: msc_result[i] = alu_in1[i] << alu_in2_imm[i][4:0]; endcase end @@ -81,7 +81,7 @@ module VX_alu_unit #( // branch - wire is_jal = is_br_op && (br_op == `BR_JAL || br_op == `BR_JALR); + wire is_jal = is_br_op && (br_op == `INST_BR_JAL || br_op == `INST_BR_JALR); wire [`NUM_THREADS-1:0][31:0] alu_jal_result = is_jal ? {`NUM_THREADS{alu_req_if.next_PC}} : alu_result; wire [31:0] br_dest = add_result[alu_req_if.tid]; @@ -90,24 +90,51 @@ module VX_alu_unit #( wire is_less = cmp_result[32]; wire is_equal = ~(| cmp_result[31:0]); - wire br_neg = `BR_NEG(br_op); - wire br_less = `BR_LESS(br_op); - wire br_static = `BR_STATIC(br_op); - wire br_taken = ((br_less ? is_less : is_equal) ^ br_neg) | br_static; - // output - wire result_valid; - wire [`NW_BITS-1:0] result_wid; - wire [`NUM_THREADS-1:0] result_tmask; - wire [31:0] result_PC; - wire [`NR_BITS-1:0] result_rd; - wire result_wb; - wire [`NUM_THREADS-1:0][31:0] result_data; - wire result_is_br; + wire alu_valid_in; + wire alu_ready_in; + wire alu_valid_out; + wire alu_ready_out; + wire [`NW_BITS-1:0] alu_wid; + wire [`NUM_THREADS-1:0] alu_tmask; + wire [31:0] alu_PC; + wire [`NR_BITS-1:0] alu_rd; + wire alu_wb; + wire [`NUM_THREADS-1:0][31:0] alu_data; + + wire [`INST_BR_BITS-1:0] br_op_r; + wire [31:0] br_dest_r; + wire is_less_r; + wire is_equal_r; + wire is_br_op_r; + + assign alu_ready_in = alu_ready_out || ~alu_valid_out; + + VX_pipe_register #( + .DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + `INST_BR_BITS + 1 + 1 + 32), + .RESETW (1) + ) pipe_reg ( + .clk (clk), + .reset (reset), + .enable (alu_ready_in), + .data_in ({alu_valid_in, alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.rd, alu_req_if.wb, alu_jal_result, is_br_op, br_op, is_less, is_equal, br_dest}), + .data_out ({alu_valid_out, alu_wid, alu_tmask, alu_PC, alu_rd, alu_wb, alu_data, is_br_op_r, br_op_r, is_less_r, is_equal_r, br_dest_r}) + ); + + `UNUSED_VAR (br_op_r) + wire br_neg = `INST_BR_NEG(br_op_r); + wire br_less = `INST_BR_LESS(br_op_r); + wire br_static = `INST_BR_STATIC(br_op_r); + + assign branch_ctl_if.valid = alu_valid_out && alu_ready_out && is_br_op_r; + assign branch_ctl_if.taken = ((br_less ? is_less_r : is_equal_r) ^ br_neg) | br_static; + assign branch_ctl_if.wid = alu_wid; + assign branch_ctl_if.dest = br_dest_r; `ifdef EXT_M_ENABLE + wire mul_valid_in; wire mul_ready_in; wire mul_valid_out; wire mul_ready_out; @@ -118,14 +145,14 @@ module VX_alu_unit #( wire mul_wb; wire [`NUM_THREADS-1:0][31:0] mul_data; - wire is_mul_op = `ALU_IS_MUL(alu_req_if.op_mod); - + wire [`INST_MUL_BITS-1:0] mul_op = `INST_MUL_BITS'(alu_req_if.op_type); + VX_muldiv muldiv ( .clk (clk), .reset (reset), // Inputs - .alu_op (`MUL_OP(alu_req_if.op_type)), + .alu_op (mul_op), .wid_in (alu_req_if.wid), .tmask_in (alu_req_if.tmask), .PC_in (alu_req_if.PC), @@ -143,69 +170,58 @@ module VX_alu_unit #( .data_out (mul_data), // handshake - .valid_in (alu_req_if.valid && is_mul_op), + .valid_in (mul_valid_in), .ready_in (mul_ready_in), .valid_out (mul_valid_out), .ready_out (mul_ready_out) ); - assign stall_in = (is_mul_op && ~mul_ready_in) - || (~is_mul_op && (mul_valid_out || stall_out)); - - assign mul_ready_out = ~stall_out; + wire is_mul_op = `INST_ALU_IS_MUL(alu_req_if.op_mod); - assign result_valid = mul_valid_out || (alu_req_if.valid && ~is_mul_op); - assign result_wid = mul_valid_out ? mul_wid : alu_req_if.wid; - assign result_tmask = mul_valid_out ? mul_tmask : alu_req_if.tmask; - assign result_PC = mul_valid_out ? mul_PC : alu_req_if.PC; - assign result_rd = mul_valid_out ? mul_rd : alu_req_if.rd; - assign result_wb = mul_valid_out ? mul_wb : alu_req_if.wb; - assign result_data = mul_valid_out ? mul_data : alu_jal_result; - assign result_is_br = ~mul_valid_out && is_br_op; + assign ready_in = is_mul_op ? mul_ready_in : alu_ready_in; + + assign alu_valid_in = alu_req_if.valid && ~is_mul_op; + assign mul_valid_in = alu_req_if.valid && is_mul_op; + + assign alu_commit_if.valid = alu_valid_out || mul_valid_out; + assign alu_commit_if.wid = alu_valid_out ? alu_wid : mul_wid; + assign alu_commit_if.tmask = alu_valid_out ? alu_tmask : mul_tmask; + assign alu_commit_if.PC = alu_valid_out ? alu_PC : mul_PC; + assign alu_commit_if.rd = alu_valid_out ? alu_rd : mul_rd; + assign alu_commit_if.wb = alu_valid_out ? alu_wb : mul_wb; + assign alu_commit_if.data = alu_valid_out ? alu_data : mul_data; + + assign alu_ready_out = alu_commit_if.ready; + assign mul_ready_out = alu_commit_if.ready & ~alu_valid_out; // ALU takes priority `else - assign stall_in = stall_out; + assign ready_in = alu_ready_in; - assign result_valid = alu_req_if.valid; - assign result_wid = alu_req_if.wid; - assign result_tmask = alu_req_if.tmask; - assign result_PC = alu_req_if.PC; - assign result_rd = alu_req_if.rd; - assign result_wb = alu_req_if.wb; - assign result_data = alu_jal_result; - assign result_is_br = is_br_op; + assign alu_valid_in = alu_req_if.valid; + + assign alu_commit_if.valid = alu_valid_out; + assign alu_commit_if.wid = alu_wid; + assign alu_commit_if.tmask = alu_tmask; + assign alu_commit_if.PC = alu_PC; + assign alu_commit_if.rd = alu_rd; + assign alu_commit_if.wb = alu_wb; + assign alu_commit_if.data = alu_data; + + assign alu_ready_out = alu_commit_if.ready; `endif - wire is_br_op_r; - - assign stall_out = ~alu_commit_if.ready && alu_commit_if.valid; - - VX_pipe_register #( - .DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + 1 + 32), - .RESETW (1) - ) pipe_reg ( - .clk (clk), - .reset (reset), - .enable (!stall_out), - .data_in ({result_valid, result_wid, result_tmask, result_PC, result_rd, result_wb, result_data, result_is_br, br_taken, br_dest}), - .data_out ({alu_commit_if.valid, alu_commit_if.wid, alu_commit_if.tmask, alu_commit_if.PC, alu_commit_if.rd, alu_commit_if.wb, alu_commit_if.data, is_br_op_r, branch_ctl_if.taken, branch_ctl_if.dest}) - ); - assign alu_commit_if.eop = 1'b1; - assign branch_ctl_if.valid = alu_commit_if.valid && alu_commit_if.ready && is_br_op_r; - assign branch_ctl_if.wid = alu_commit_if.wid; - // can accept new request? - assign alu_req_if.ready = ~stall_in; + assign alu_req_if.ready = ready_in; `ifdef DBG_PRINT_PIPELINE always @(posedge clk) begin if (branch_ctl_if.valid) begin - $display("%t: core%0d-branch: wid=%0d, PC=%0h, taken=%b, dest=%0h", $time, CORE_ID, - branch_ctl_if.wid, alu_commit_if.PC, branch_ctl_if.taken, branch_ctl_if.dest); + dpi_trace("%d: core%0d-branch: wid=%0d, PC=%0h, taken=%b, dest=%0h\n", + $time, CORE_ID, branch_ctl_if.wid, alu_commit_if.PC, branch_ctl_if.taken, branch_ctl_if.dest); end end `endif diff --git a/hw/rtl/VX_cluster.v b/hw/rtl/VX_cluster.sv similarity index 73% rename from hw/rtl/VX_cluster.v rename to hw/rtl/VX_cluster.sv index a8ed0870..be933ae6 100644 --- a/hw/rtl/VX_cluster.v +++ b/hw/rtl/VX_cluster.sv @@ -12,16 +12,16 @@ module VX_cluster #( // Memory request output wire mem_req_valid, output wire mem_req_rw, - output wire [`L2MEM_BYTEEN_WIDTH-1:0] mem_req_byteen, - output wire [`L2MEM_ADDR_WIDTH-1:0] mem_req_addr, - output wire [`L2MEM_DATA_WIDTH-1:0] mem_req_data, - output wire [`L2MEM_TAG_WIDTH-1:0] mem_req_tag, + output wire [`L2_MEM_BYTEEN_WIDTH-1:0] mem_req_byteen, + output wire [`L2_MEM_ADDR_WIDTH-1:0] mem_req_addr, + output wire [`L2_MEM_DATA_WIDTH-1:0] mem_req_data, + output wire [`L2_MEM_TAG_WIDTH-1:0] mem_req_tag, input wire mem_req_ready, // Memory response input wire mem_rsp_valid, - input wire [`L2MEM_DATA_WIDTH-1:0] mem_rsp_data, - input wire [`L2MEM_TAG_WIDTH-1:0] mem_rsp_tag, + input wire [`L2_MEM_DATA_WIDTH-1:0] mem_rsp_data, + input wire [`L2_MEM_TAG_WIDTH-1:0] mem_rsp_tag, output wire mem_rsp_ready, // Status @@ -31,15 +31,15 @@ module VX_cluster #( wire [`NUM_CORES-1:0] per_core_mem_req_valid; wire [`NUM_CORES-1:0] per_core_mem_req_rw; - wire [`NUM_CORES-1:0][`DMEM_BYTEEN_WIDTH-1:0] per_core_mem_req_byteen; - wire [`NUM_CORES-1:0][`DMEM_ADDR_WIDTH-1:0] per_core_mem_req_addr; - wire [`NUM_CORES-1:0][`DMEM_DATA_WIDTH-1:0] per_core_mem_req_data; - wire [`NUM_CORES-1:0][`XMEM_TAG_WIDTH-1:0] per_core_mem_req_tag; + wire [`NUM_CORES-1:0][`DCACHE_MEM_BYTEEN_WIDTH-1:0] per_core_mem_req_byteen; + wire [`NUM_CORES-1:0][`DCACHE_MEM_ADDR_WIDTH-1:0] per_core_mem_req_addr; + wire [`NUM_CORES-1:0][`DCACHE_MEM_DATA_WIDTH-1:0] per_core_mem_req_data; + wire [`NUM_CORES-1:0][`L1_MEM_TAG_WIDTH-1:0] per_core_mem_req_tag; wire [`NUM_CORES-1:0] per_core_mem_req_ready; wire [`NUM_CORES-1:0] per_core_mem_rsp_valid; - wire [`NUM_CORES-1:0][`DMEM_DATA_WIDTH-1:0] per_core_mem_rsp_data; - wire [`NUM_CORES-1:0][`XMEM_TAG_WIDTH-1:0] per_core_mem_rsp_tag; + wire [`NUM_CORES-1:0][`DCACHE_MEM_DATA_WIDTH-1:0] per_core_mem_rsp_data; + wire [`NUM_CORES-1:0][`L1_MEM_TAG_WIDTH-1:0] per_core_mem_rsp_tag; wire [`NUM_CORES-1:0] per_core_mem_rsp_ready; wire [`NUM_CORES-1:0] per_core_busy; @@ -69,7 +69,7 @@ module VX_cluster #( .mem_rsp_tag (per_core_mem_rsp_tag [i]), .mem_rsp_ready (per_core_mem_rsp_ready[i]), - .busy (per_core_busy [i]) + .busy (per_core_busy [i]) ); end @@ -83,21 +83,22 @@ module VX_cluster #( `RESET_RELAY (l2_reset); VX_cache #( - .CACHE_ID (`L2CACHE_ID), - .CACHE_SIZE (`L2CACHE_SIZE), - .CACHE_LINE_SIZE (`L2CACHE_LINE_SIZE), - .NUM_BANKS (`L2NUM_BANKS), - .WORD_SIZE (`L2WORD_SIZE), - .NUM_REQS (`L2NUM_REQS), - .CREQ_SIZE (`L2CREQ_SIZE), - .CRSQ_SIZE (`L2CRSQ_SIZE), - .MSHR_SIZE (`L2MSHR_SIZE), - .MRSQ_SIZE (`L2MRSQ_SIZE), - .MREQ_SIZE (`L2MREQ_SIZE), + .CACHE_ID (`L2_CACHE_ID), + .CACHE_SIZE (`L2_CACHE_SIZE), + .CACHE_LINE_SIZE (`L2_CACHE_LINE_SIZE), + .NUM_BANKS (`L2_NUM_BANKS), + .NUM_PORTS (`L2_NUM_PORTS), + .WORD_SIZE (`L2_WORD_SIZE), + .NUM_REQS (`L2_NUM_REQS), + .CREQ_SIZE (`L2_CREQ_SIZE), + .CRSQ_SIZE (`L2_CRSQ_SIZE), + .MSHR_SIZE (`L2_MSHR_SIZE), + .MRSQ_SIZE (`L2_MRSQ_SIZE), + .MREQ_SIZE (`L2_MREQ_SIZE), .WRITE_ENABLE (1), - .CORE_TAG_WIDTH (`XMEM_TAG_WIDTH), + .CORE_TAG_WIDTH (`L1_MEM_TAG_WIDTH), .CORE_TAG_ID_BITS (0), - .MEM_TAG_WIDTH (`L2MEM_TAG_WIDTH), + .MEM_TAG_WIDTH (`L2_MEM_TAG_WIDTH), .NC_ENABLE (1) ) l2cache ( `SCOPE_BIND_VX_cluster_l2cache @@ -143,16 +144,20 @@ module VX_cluster #( end else begin + `RESET_RELAY (mem_arb_reset); + VX_mem_arb #( - .NUM_REQS (`NUM_CORES), - .DATA_WIDTH (`L2MEM_DATA_WIDTH), - .ADDR_WIDTH (`L2MEM_ADDR_WIDTH), - .TAG_IN_WIDTH (`XMEM_TAG_WIDTH), - .BUFFERED_REQ (1), - .BUFFERED_RSP (1) + .NUM_REQS (`NUM_CORES), + .DATA_WIDTH (`DCACHE_MEM_DATA_WIDTH), + .ADDR_WIDTH (`DCACHE_MEM_ADDR_WIDTH), + .TAG_IN_WIDTH (`L1_MEM_TAG_WIDTH), + .TYPE ("R"), + .TAG_SEL_IDX (1), // Skip 0 for NC flag + .BUFFERED_REQ (1), + .BUFFERED_RSP (1) ) mem_arb ( .clk (clk), - .reset (reset), + .reset (mem_arb_reset), // Core request .req_valid_in (per_core_mem_req_valid), diff --git a/hw/rtl/VX_commit.sv b/hw/rtl/VX_commit.sv new file mode 100644 index 00000000..a8e1764b --- /dev/null +++ b/hw/rtl/VX_commit.sv @@ -0,0 +1,130 @@ +`include "VX_define.vh" + +module VX_commit #( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, + + // inputs + VX_commit_if.slave alu_commit_if, + VX_commit_if.slave ld_commit_if, + VX_commit_if.slave st_commit_if, + VX_commit_if.slave csr_commit_if, +`ifdef EXT_F_ENABLE + VX_commit_if.slave fpu_commit_if, +`endif + VX_commit_if.slave gpu_commit_if, + + // outputs + VX_writeback_if.master writeback_if, + VX_cmt_to_csr_if.master cmt_to_csr_if +); + // CSRs update + + wire alu_commit_fire = alu_commit_if.valid && alu_commit_if.ready; + wire ld_commit_fire = ld_commit_if.valid && ld_commit_if.ready; + wire st_commit_fire = st_commit_if.valid && st_commit_if.ready; + wire csr_commit_fire = csr_commit_if.valid && csr_commit_if.ready; +`ifdef EXT_F_ENABLE + wire fpu_commit_fire = fpu_commit_if.valid && fpu_commit_if.ready; +`endif + wire gpu_commit_fire = gpu_commit_if.valid && gpu_commit_if.ready; + + wire commit_fire = alu_commit_fire + || ld_commit_fire + || st_commit_fire + || csr_commit_fire + `ifdef EXT_F_ENABLE + || fpu_commit_fire + `endif + || gpu_commit_fire; + + wire [`NUM_THREADS-1:0] commit_tmask; + assign commit_tmask = alu_commit_fire ? alu_commit_if.tmask: + ld_commit_fire ? ld_commit_if.tmask: + st_commit_fire ? st_commit_if.tmask: + csr_commit_fire ? csr_commit_if.tmask: + `ifdef EXT_F_ENABLE + fpu_commit_fire ? fpu_commit_if.tmask: + `endif + /*gpu_commit_fire ?*/ gpu_commit_if.tmask; + + wire [$clog2(`NUM_THREADS+1)-1:0] commit_cnt; + `POP_COUNT(commit_cnt, commit_tmask); + + VX_pipe_register #( + .DATAW (1 + $clog2(`NUM_THREADS+1)), + .RESETW (1) + ) pipe_reg ( + .clk (clk), + .reset (reset), + .enable (1'b1), + .data_in ({commit_fire, commit_cnt}), + .data_out ({cmt_to_csr_if.valid, cmt_to_csr_if.commit_size}) + ); + + // Writeback + + VX_writeback #( + .CORE_ID(CORE_ID) + ) writeback ( + .clk (clk), + .reset (reset), + + .alu_commit_if (alu_commit_if), + .ld_commit_if (ld_commit_if), + .csr_commit_if (csr_commit_if), + `ifdef EXT_F_ENABLE + .fpu_commit_if (fpu_commit_if), + `endif + .writeback_if (writeback_if) + ); + + // store and gpu commits don't writeback + assign st_commit_if.ready = 1'b1; + assign gpu_commit_if.ready = 1'b1; + +`ifdef DBG_PRINT_PIPELINE + always @(posedge clk) begin + if (alu_commit_if.valid && alu_commit_if.ready) begin + dpi_trace("%d: core%0d-commit: wid=%0d, PC=%0h, ex=ALU, tmask=%b, wb=%0d, rd=%0d, data=", $time, CORE_ID, alu_commit_if.wid, alu_commit_if.PC, alu_commit_if.tmask, alu_commit_if.wb, alu_commit_if.rd); + `TRACE_ARRAY1D(alu_commit_if.data, `NUM_THREADS); + dpi_trace("\n"); + end + if (ld_commit_if.valid && ld_commit_if.ready) begin + dpi_trace("%d: core%0d-commit: wid=%0d, PC=%0h, ex=LSU, tmask=%b, wb=%0d, rd=%0d, data=", $time, CORE_ID, ld_commit_if.wid, ld_commit_if.PC, ld_commit_if.tmask, ld_commit_if.wb, ld_commit_if.rd); + `TRACE_ARRAY1D(ld_commit_if.data, `NUM_THREADS); + dpi_trace("\n"); + end + if (st_commit_if.valid && st_commit_if.ready) begin + dpi_trace("%d: core%0d-commit: wid=%0d, PC=%0h, ex=LSU, tmask=%b, wb=%0d, rd=%0d\n", $time, CORE_ID, st_commit_if.wid, st_commit_if.PC, st_commit_if.tmask, st_commit_if.wb, st_commit_if.rd); + end + if (csr_commit_if.valid && csr_commit_if.ready) begin + dpi_trace("%d: core%0d-commit: wid=%0d, PC=%0h, ex=CSR, tmask=%b, wb=%0d, rd=%0d, data=", $time, CORE_ID, csr_commit_if.wid, csr_commit_if.PC, csr_commit_if.tmask, csr_commit_if.wb, csr_commit_if.rd); + `TRACE_ARRAY1D(csr_commit_if.data, `NUM_THREADS); + dpi_trace("\n"); + end + `ifdef EXT_F_ENABLE + if (fpu_commit_if.valid && fpu_commit_if.ready) begin + dpi_trace("%d: core%0d-commit: wid=%0d, PC=%0h, ex=FPU, tmask=%b, wb=%0d, rd=%0d, data=", $time, CORE_ID, fpu_commit_if.wid, fpu_commit_if.PC, fpu_commit_if.tmask, fpu_commit_if.wb, fpu_commit_if.rd); + `TRACE_ARRAY1D(fpu_commit_if.data, `NUM_THREADS); + dpi_trace("\n"); + end + `endif + if (gpu_commit_if.valid && gpu_commit_if.ready) begin + dpi_trace("%d: core%0d-commit: wid=%0d, PC=%0h, ex=GPU, tmask=%b, wb=%0d, rd=%0d, data=", $time, CORE_ID, gpu_commit_if.wid, gpu_commit_if.PC, gpu_commit_if.tmask, gpu_commit_if.wb, gpu_commit_if.rd); + `TRACE_ARRAY1D(gpu_commit_if.data, `NUM_THREADS); + dpi_trace("\n"); + end + end +`endif + +endmodule + + + + + + + diff --git a/hw/rtl/VX_commit.v b/hw/rtl/VX_commit.v deleted file mode 100644 index b3ed5a6a..00000000 --- a/hw/rtl/VX_commit.v +++ /dev/null @@ -1,127 +0,0 @@ -`include "VX_define.vh" - -module VX_commit #( - parameter CORE_ID = 0 -) ( - input wire clk, - input wire reset, - - // inputs - VX_commit_if alu_commit_if, - VX_commit_if ld_commit_if, - VX_commit_if st_commit_if, - VX_commit_if csr_commit_if, - VX_commit_if fpu_commit_if, - VX_commit_if gpu_commit_if, - - // outputs - VX_writeback_if writeback_if, - VX_cmt_to_csr_if cmt_to_csr_if -); - localparam CMTW = $clog2(3*`NUM_THREADS+1); - - // CSRs update - - wire alu_commit_fire = alu_commit_if.valid && alu_commit_if.ready; - wire ld_commit_fire = ld_commit_if.valid && ld_commit_if.ready; - wire st_commit_fire = st_commit_if.valid && st_commit_if.ready; - wire csr_commit_fire = csr_commit_if.valid && csr_commit_if.ready; - wire fpu_commit_fire = fpu_commit_if.valid && fpu_commit_if.ready; - wire gpu_commit_fire = gpu_commit_if.valid && gpu_commit_if.ready; - - wire commit_fire = alu_commit_fire - || ld_commit_fire - || st_commit_fire - || csr_commit_fire - || fpu_commit_fire - || gpu_commit_fire; - - wire [`NUM_THREADS-1:0] commit_tmask1, commit_tmask2, commit_tmask3; - - assign commit_tmask1 = alu_commit_fire ? alu_commit_if.tmask: - ld_commit_fire ? ld_commit_if.tmask: - csr_commit_fire ? csr_commit_if.tmask: - fpu_commit_fire ? fpu_commit_if.tmask: - 0; - - assign commit_tmask2 = st_commit_fire ? st_commit_if.tmask : 0; - assign commit_tmask3 = gpu_commit_fire ? gpu_commit_if.tmask : 0; - - wire [CMTW-1:0] commit_size; - assign commit_size = $countones({commit_tmask3, commit_tmask2, commit_tmask1}); - - VX_pipe_register #( - .DATAW (1 + CMTW), - .RESETW (1) - ) pipe_reg ( - .clk (clk), - .reset (reset), - .enable (1'b1), - .data_in ({commit_fire, commit_size}), - .data_out ({cmt_to_csr_if.valid, cmt_to_csr_if.commit_size}) - ); - - // Writeback - - VX_writeback #( - .CORE_ID(CORE_ID) - ) writeback ( - .clk (clk), - .reset (reset), - - .alu_commit_if (alu_commit_if), - .ld_commit_if (ld_commit_if), - .csr_commit_if (csr_commit_if), - .fpu_commit_if (fpu_commit_if), - .gpu_commit_if (gpu_commit_if), - - .writeback_if (writeback_if) - ); - - // store doesn't writeback - assign st_commit_if.ready = 1'b1; - // assign gpu_commit_if.ready = 1'b1; - -`ifdef DBG_PRINT_PIPELINE - always @(posedge clk) begin - if (alu_commit_if.valid && alu_commit_if.ready) begin - $write("%t: core%0d-commit: wid=%0d, PC=%0h, ex=ALU, tmask=%b, wb=%0d, rd=%0d, data=", $time, CORE_ID, alu_commit_if.wid, alu_commit_if.PC, alu_commit_if.tmask, alu_commit_if.wb, alu_commit_if.rd); - `PRINT_ARRAY1D(alu_commit_if.data, `NUM_THREADS); - $write("\n"); - end - if (ld_commit_if.valid && ld_commit_if.ready) begin - $write("%t: core%0d-commit: wid=%0d, PC=%0h, ex=LSU, tmask=%b, wb=%0d, rd=%0d, data=", $time, CORE_ID, ld_commit_if.wid, ld_commit_if.PC, ld_commit_if.tmask, ld_commit_if.wb, ld_commit_if.rd); - `PRINT_ARRAY1D(ld_commit_if.data, `NUM_THREADS); - $write("\n"); - end - if (st_commit_if.valid && st_commit_if.ready) begin - $display("%t: core%0d-commit: wid=%0d, PC=%0h, ex=LSU, tmask=%b, wb=%0d, rd=%0d", $time, CORE_ID, st_commit_if.wid, st_commit_if.PC, st_commit_if.tmask, st_commit_if.wb, st_commit_if.rd); - end - if (csr_commit_if.valid && csr_commit_if.ready) begin - $write("%t: core%0d-commit: wid=%0d, PC=%0h, ex=CSR, tmask=%b, wb=%0d, rd=%0d, data=", $time, CORE_ID, csr_commit_if.wid, csr_commit_if.PC, csr_commit_if.tmask, csr_commit_if.wb, csr_commit_if.rd); - `PRINT_ARRAY1D(csr_commit_if.data, `NUM_THREADS); - $write("\n"); - end - if (fpu_commit_if.valid && fpu_commit_if.ready) begin - $write("%t: core%0d-commit: wid=%0d, PC=%0h, ex=FPU, tmask=%b, wb=%0d, rd=%0d, data=", $time, CORE_ID, fpu_commit_if.wid, fpu_commit_if.PC, fpu_commit_if.tmask, fpu_commit_if.wb, fpu_commit_if.rd); - `PRINT_ARRAY1D(fpu_commit_if.data, `NUM_THREADS); - $write("\n"); - end - if (gpu_commit_if.valid && gpu_commit_if.ready) begin - $write("%t: core%0d-commit: wid=%0d, PC=%0h, ex=GPU, tmask=%b, wb=%0d, rd=%0d, data=", $time, CORE_ID, gpu_commit_if.wid, gpu_commit_if.PC, gpu_commit_if.tmask, gpu_commit_if.wb, gpu_commit_if.rd); - `PRINT_ARRAY1D(gpu_commit_if.data, `NUM_THREADS); - $write("\n"); - end - end -`else - `UNUSED_VAR (fpu_commit_if.PC) -`endif - -endmodule - - - - - - - diff --git a/hw/rtl/VX_config.vh b/hw/rtl/VX_config.vh index 55f4c658..21191216 100644 --- a/hw/rtl/VX_config.vh +++ b/hw/rtl/VX_config.vh @@ -38,7 +38,7 @@ `endif `ifndef L1_BLOCK_SIZE -`define L1_BLOCK_SIZE (`NUM_THREADS * 4) +`define L1_BLOCK_SIZE ((`L2_ENABLE || `L3_ENABLE) ? 16 : `MEM_BLOCK_SIZE) `endif `ifndef STARTUP_ADDR @@ -227,6 +227,7 @@ `define CSR_LWID 12'hCC3 `define CSR_GWID `CSR_MHARTID `define CSR_GCID 12'hCC5 +`define CSR_TMASK 12'hCC4 // Machine SIMT CSRs `define CSR_NT 12'hFC0 @@ -250,6 +251,11 @@ // Pipeline Queues //////////////////////////////////////////////////////////// +// Size of Instruction Buffer +`ifndef IBUF_SIZE +`define IBUF_SIZE 2 +`endif + // Size of LSU Request Queue `ifndef LSUQ_SIZE `define LSUQ_SIZE (`NUM_WARPS * 2) @@ -268,28 +274,28 @@ `endif // Core Request Queue Size -`ifndef ICREQ_SIZE -`define ICREQ_SIZE 0 +`ifndef ICACHE_CREQ_SIZE +`define ICACHE_CREQ_SIZE 0 `endif // Core Response Queue Size -`ifndef ICRSQ_SIZE -`define ICRSQ_SIZE 2 +`ifndef ICACHE_CRSQ_SIZE +`define ICACHE_CRSQ_SIZE 2 `endif // Miss Handling Register Size -`ifndef IMSHR_SIZE -`define IMSHR_SIZE `NUM_WARPS +`ifndef ICACHE_MSHR_SIZE +`define ICACHE_MSHR_SIZE `NUM_WARPS `endif // Memory Request Queue Size -`ifndef IMREQ_SIZE -`define IMREQ_SIZE 4 +`ifndef ICACHE_MREQ_SIZE +`define ICACHE_MREQ_SIZE 4 `endif // Memory Response Queue Size -`ifndef IMRSQ_SIZE -`define IMRSQ_SIZE 0 +`ifndef ICACHE_MRSQ_SIZE +`define ICACHE_MRSQ_SIZE 0 `endif // Dcache Configurable Knobs ////////////////////////////////////////////////// @@ -300,38 +306,38 @@ `endif // Number of banks -`ifndef DNUM_BANKS -`define DNUM_BANKS `NUM_THREADS +`ifndef DCACHE_NUM_BANKS +`define DCACHE_NUM_BANKS `NUM_THREADS `endif -// Number of bank ports -`ifndef DNUM_PORTS -`define DNUM_PORTS 1 +// Number of ports per bank +`ifndef DCACHE_NUM_PORTS +`define DCACHE_NUM_PORTS 1 `endif // Core Request Queue Size -`ifndef DCREQ_SIZE -`define DCREQ_SIZE 0 +`ifndef DCACHE_CREQ_SIZE +`define DCACHE_CREQ_SIZE 0 `endif // Core Response Queue Size -`ifndef DCRSQ_SIZE -`define DCRSQ_SIZE 2 +`ifndef DCACHE_CRSQ_SIZE +`define DCACHE_CRSQ_SIZE 2 `endif // Miss Handling Register Size -`ifndef DMSHR_SIZE -`define DMSHR_SIZE `LSUQ_SIZE +`ifndef DCACHE_MSHR_SIZE +`define DCACHE_MSHR_SIZE `LSUQ_SIZE `endif // Memory Request Queue Size -`ifndef DMREQ_SIZE -`define DMREQ_SIZE 4 +`ifndef DCACHE_MREQ_SIZE +`define DCACHE_MREQ_SIZE 4 `endif // Memory Response Queue Size -`ifndef DMRSQ_SIZE -`define DMRSQ_SIZE 0 +`ifndef DCACHE_MRSQ_SIZE +`define DCACHE_MRSQ_SIZE 0 `endif // SM Configurable Knobs ////////////////////////////////////////////////////// @@ -348,92 +354,102 @@ `endif // Number of banks -`ifndef SNUM_BANKS -`define SNUM_BANKS `NUM_THREADS +`ifndef SMEM_NUM_BANKS +`define SMEM_NUM_BANKS `NUM_THREADS `endif // Core Request Queue Size -`ifndef SCREQ_SIZE -`define SCREQ_SIZE 2 +`ifndef SMEM_CREQ_SIZE +`define SMEM_CREQ_SIZE 2 `endif // Core Response Queue Size -`ifndef SCRSQ_SIZE -`define SCRSQ_SIZE 2 +`ifndef SMEM_CRSQ_SIZE +`define SMEM_CRSQ_SIZE 2 `endif // L2cache Configurable Knobs ///////////////////////////////////////////////// // Size of cache in bytes -`ifndef L2CACHE_SIZE -`define L2CACHE_SIZE 131072 +`ifndef L2_CACHE_SIZE +`define L2_CACHE_SIZE 131072 `endif // Number of banks -`ifndef L2NUM_BANKS -`define L2NUM_BANKS `MIN(`NUM_CORES, 4) +`ifndef L2_NUM_BANKS +`define L2_NUM_BANKS `MIN(`NUM_CORES, 4) +`endif + +// Number of ports per bank +`ifndef L2_NUM_PORTS +`define L2_NUM_PORTS 1 `endif // Core Request Queue Size -`ifndef L2CREQ_SIZE -`define L2CREQ_SIZE 0 +`ifndef L2_CREQ_SIZE +`define L2_CREQ_SIZE 0 `endif // Core Response Queue Size -`ifndef L2CRSQ_SIZE -`define L2CRSQ_SIZE 2 +`ifndef L2_CRSQ_SIZE +`define L2_CRSQ_SIZE 2 `endif // Miss Handling Register Size -`ifndef L2MSHR_SIZE -`define L2MSHR_SIZE 16 +`ifndef L2_MSHR_SIZE +`define L2_MSHR_SIZE 16 `endif // Memory Request Queue Size -`ifndef L2MREQ_SIZE -`define L2MREQ_SIZE 4 +`ifndef L2_MREQ_SIZE +`define L2_MREQ_SIZE 4 `endif // Memory Response Queue Size -`ifndef L2MRSQ_SIZE -`define L2MRSQ_SIZE 0 +`ifndef L2_MRSQ_SIZE +`define L2_MRSQ_SIZE 0 `endif // L3cache Configurable Knobs ///////////////////////////////////////////////// // Size of cache in bytes -`ifndef L3CACHE_SIZE -`define L3CACHE_SIZE 1048576 +`ifndef L3_CACHE_SIZE +`define L3_CACHE_SIZE 1048576 `endif // Number of banks -`ifndef L3NUM_BANKS -`define L3NUM_BANKS `MIN(`NUM_CLUSTERS, 4) +`ifndef L3_NUM_BANKS +`define L3_NUM_BANKS `MIN(`NUM_CLUSTERS, 4) +`endif + +// Number of ports per bank +`ifndef L3_NUM_PORTS +`define L3_NUM_PORTS 1 `endif // Core Request Queue Size -`ifndef L3CREQ_SIZE -`define L3CREQ_SIZE 0 +`ifndef L3_CREQ_SIZE +`define L3_CREQ_SIZE 0 `endif // Core Response Queue Size -`ifndef L3CRSQ_SIZE -`define L3CRSQ_SIZE 2 +`ifndef L3_CRSQ_SIZE +`define L3_CRSQ_SIZE 2 `endif // Miss Handling Register Size -`ifndef L3MSHR_SIZE -`define L3MSHR_SIZE 16 +`ifndef L3_MSHR_SIZE +`define L3_MSHR_SIZE 16 `endif // Memory Request Queue Size -`ifndef L3MREQ_SIZE -`define L3MREQ_SIZE 4 +`ifndef L3_MREQ_SIZE +`define L3_MREQ_SIZE 4 `endif // Memory Response Queue Size -`ifndef L3MRSQ_SIZE -`define L3MRSQ_SIZE 0 +`ifndef L3_MRSQ_SIZE +`define L3_MRSQ_SIZE 0 `endif `endif diff --git a/hw/rtl/VX_core.v b/hw/rtl/VX_core.sv similarity index 75% rename from hw/rtl/VX_core.v rename to hw/rtl/VX_core.sv index fcfdd524..d1cbbb6f 100644 --- a/hw/rtl/VX_core.v +++ b/hw/rtl/VX_core.sv @@ -12,16 +12,16 @@ module VX_core #( // Memory request output wire mem_req_valid, output wire mem_req_rw, - output wire [`DMEM_BYTEEN_WIDTH-1:0] mem_req_byteen, - output wire [`DMEM_ADDR_WIDTH-1:0] mem_req_addr, - output wire [`DMEM_DATA_WIDTH-1:0] mem_req_data, - output wire [`XMEM_TAG_WIDTH-1:0] mem_req_tag, + output wire [`DCACHE_MEM_BYTEEN_WIDTH-1:0] mem_req_byteen, + output wire [`DCACHE_MEM_ADDR_WIDTH-1:0] mem_req_addr, + output wire [`DCACHE_MEM_DATA_WIDTH-1:0] mem_req_data, + output wire [`L1_MEM_TAG_WIDTH-1:0] mem_req_tag, input wire mem_req_ready, // Memory reponse input wire mem_rsp_valid, - input wire [`DMEM_DATA_WIDTH-1:0] mem_rsp_data, - input wire [`XMEM_TAG_WIDTH-1:0] mem_rsp_tag, + input wire [`DCACHE_MEM_DATA_WIDTH-1:0] mem_rsp_data, + input wire [`L1_MEM_TAG_WIDTH-1:0] mem_rsp_tag, output wire mem_rsp_ready, // Status @@ -32,14 +32,14 @@ module VX_core #( `endif VX_mem_req_if #( - .DATA_WIDTH (`DMEM_DATA_WIDTH), - .ADDR_WIDTH (`DMEM_ADDR_WIDTH), - .TAG_WIDTH (`XMEM_TAG_WIDTH) + .DATA_WIDTH (`DCACHE_MEM_DATA_WIDTH), + .ADDR_WIDTH (`DCACHE_MEM_ADDR_WIDTH), + .TAG_WIDTH (`L1_MEM_TAG_WIDTH) ) mem_req_if(); VX_mem_rsp_if #( - .DATA_WIDTH (`DMEM_DATA_WIDTH), - .TAG_WIDTH (`XMEM_TAG_WIDTH) + .DATA_WIDTH (`DCACHE_MEM_DATA_WIDTH), + .TAG_WIDTH (`L1_MEM_TAG_WIDTH) ) mem_rsp_if(); assign mem_req_valid = mem_req_if.valid; @@ -58,25 +58,25 @@ module VX_core #( //-- VX_dcache_req_if #( - .NUM_REQS (`DNUM_REQS), - .WORD_SIZE (`DWORD_SIZE), - .TAG_WIDTH (`DCORE_TAG_WIDTH) + .NUM_REQS (`DCACHE_NUM_REQS), + .WORD_SIZE (`DCACHE_WORD_SIZE), + .TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH) ) dcache_req_if(); VX_dcache_rsp_if #( - .NUM_REQS (`DNUM_REQS), - .WORD_SIZE (`DWORD_SIZE), - .TAG_WIDTH (`DCORE_TAG_WIDTH) + .NUM_REQS (`DCACHE_NUM_REQS), + .WORD_SIZE (`DCACHE_WORD_SIZE), + .TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH) ) dcache_rsp_if(); VX_icache_req_if #( - .WORD_SIZE (`IWORD_SIZE), - .TAG_WIDTH (`ICORE_TAG_WIDTH) + .WORD_SIZE (`ICACHE_WORD_SIZE), + .TAG_WIDTH (`ICACHE_CORE_TAG_WIDTH) ) icache_req_if(); VX_icache_rsp_if #( - .WORD_SIZE (`IWORD_SIZE), - .TAG_WIDTH (`ICORE_TAG_WIDTH) + .WORD_SIZE (`ICACHE_WORD_SIZE), + .TAG_WIDTH (`ICACHE_CORE_TAG_WIDTH) ) icache_rsp_if(); VX_pipeline #( diff --git a/hw/rtl/VX_csr_data.v b/hw/rtl/VX_csr_data.sv similarity index 84% rename from hw/rtl/VX_csr_data.v rename to hw/rtl/VX_csr_data.sv index 4507816e..53954e91 100644 --- a/hw/rtl/VX_csr_data.v +++ b/hw/rtl/VX_csr_data.sv @@ -7,15 +7,18 @@ module VX_csr_data #( input wire reset, `ifdef PERF_ENABLE - VX_perf_memsys_if perf_memsys_if, - VX_perf_pipeline_if perf_pipeline_if, + VX_perf_memsys_if.slave perf_memsys_if, + VX_perf_pipeline_if.slave perf_pipeline_if, `endif - VX_cmt_to_csr_if cmt_to_csr_if, - VX_fpu_to_csr_if fpu_to_csr_if, + VX_cmt_to_csr_if.slave cmt_to_csr_if, + VX_fetch_to_csr_if.slave fetch_to_csr_if, +`ifdef EXT_F_ENABLE + VX_fpu_to_csr_if.slave fpu_to_csr_if, +`endif `ifdef EXT_TEX_ENABLE - VX_tex_csr_if tex_csr_if, + VX_tex_csr_if.slave tex_csr_if, `endif input wire read_enable, @@ -30,6 +33,8 @@ module VX_csr_data #( input wire busy ); + import fpu_types::*; + reg [`CSR_WIDTH-1:0] csr_satp; reg [`CSR_WIDTH-1:0] csr_mstatus; reg [`CSR_WIDTH-1:0] csr_medeleg; @@ -42,38 +47,40 @@ module VX_csr_data #( reg [63:0] csr_cycle; reg [63:0] csr_instret; - reg [`NUM_WARPS-1:0][`FRM_BITS+`FFG_BITS-1:0] fcsr; - - always @(posedge clk) begin + reg [`NUM_WARPS-1:0][`INST_FRM_BITS+`FFLAGS_BITS-1:0] fcsr; + always @(posedge clk) begin + `ifdef EXT_F_ENABLE if (reset) begin fcsr <= '0; - end - + end if (fpu_to_csr_if.write_enable) begin - fcsr[fpu_to_csr_if.write_wid][`FFG_BITS-1:0] <= fcsr[fpu_to_csr_if.write_wid][`FFG_BITS-1:0] - | fpu_to_csr_if.write_fflags; + fcsr[fpu_to_csr_if.write_wid][`FFLAGS_BITS-1:0] <= fcsr[fpu_to_csr_if.write_wid][`FFLAGS_BITS-1:0] + | fpu_to_csr_if.write_fflags; end - + `endif if (write_enable) begin case (write_addr) - `CSR_FFLAGS: fcsr[write_wid][`FFG_BITS-1:0] <= write_data[`FFG_BITS-1:0]; - `CSR_FRM: fcsr[write_wid][`FRM_BITS+`FFG_BITS-1:`FFG_BITS] <= write_data[`FRM_BITS-1:0]; - `CSR_FCSR: fcsr[write_wid] <= write_data[`FFG_BITS+`FRM_BITS-1:0]; + `CSR_FFLAGS: fcsr[write_wid][`FFLAGS_BITS-1:0] <= write_data[`FFLAGS_BITS-1:0]; + `CSR_FRM: fcsr[write_wid][`INST_FRM_BITS+`FFLAGS_BITS-1:`FFLAGS_BITS] <= write_data[`INST_FRM_BITS-1:0]; + `CSR_FCSR: fcsr[write_wid] <= write_data[`FFLAGS_BITS+`INST_FRM_BITS-1:0]; - `CSR_SATP: csr_satp <= write_data[`CSR_WIDTH-1:0]; - `CSR_MSTATUS: csr_mstatus <= write_data[`CSR_WIDTH-1:0]; - `CSR_MEDELEG: csr_medeleg <= write_data[`CSR_WIDTH-1:0]; - `CSR_MIDELEG: csr_mideleg <= write_data[`CSR_WIDTH-1:0]; - `CSR_MIE: csr_mie <= write_data[`CSR_WIDTH-1:0]; - `CSR_MTVEC: csr_mtvec <= write_data[`CSR_WIDTH-1:0]; - `CSR_MEPC: csr_mepc <= write_data[`CSR_WIDTH-1:0]; - `CSR_PMPCFG0: csr_pmpcfg[0] <= write_data[`CSR_WIDTH-1:0]; - `CSR_PMPADDR0: csr_pmpaddr[0] <= write_data[`CSR_WIDTH-1:0]; + `CSR_SATP: csr_satp <= write_data; + + `CSR_MSTATUS: csr_mstatus <= write_data; + `CSR_MEDELEG: csr_medeleg <= write_data; + `CSR_MIDELEG: csr_mideleg <= write_data; + `CSR_MIE: csr_mie <= write_data; + `CSR_MTVEC: csr_mtvec <= write_data; + + `CSR_MEPC: csr_mepc <= write_data; + + `CSR_PMPCFG0: csr_pmpcfg[0] <= write_data; + `CSR_PMPADDR0: csr_pmpaddr[0] <= write_data; default: begin assert (write_addr >= `CSR_TEX_BEGIN(0) && write_addr < `CSR_TEX_BEGIN(`CSR_TEX_STATES)) - else $error("%t: invalid CSR write address: %0h", $time, write_addr); + else `ASSERT(~write_enable, ("%t: invalid CSR write address: %0h", $time, write_addr)); end endcase end @@ -109,8 +116,8 @@ module VX_csr_data #( read_data_r = 'x; read_addr_valid_r = 1; case (read_addr) - `CSR_FFLAGS : read_data_r = 32'(fcsr[read_wid][`FFG_BITS-1:0]); - `CSR_FRM : read_data_r = 32'(fcsr[read_wid][`FRM_BITS+`FFG_BITS-1:`FFG_BITS]); + `CSR_FFLAGS : read_data_r = 32'(fcsr[read_wid][`FFLAGS_BITS-1:0]); + `CSR_FRM : read_data_r = 32'(fcsr[read_wid][`INST_FRM_BITS+`FFLAGS_BITS-1:`FFLAGS_BITS]); `CSR_FCSR : read_data_r = 32'(fcsr[read_wid]); `CSR_WTID , @@ -120,6 +127,9 @@ module VX_csr_data #( /*`CSR_MHARTID ,*/ `CSR_GWID : read_data_r = CORE_ID * `NUM_WARPS + 32'(read_wid); `CSR_GCID : read_data_r = CORE_ID; + + `CSR_TMASK : read_data_r = 32'(fetch_to_csr_if.thread_masks[read_wid]); + `CSR_NT : read_data_r = `NUM_THREADS; `CSR_NW : read_data_r = `NUM_WARPS; `CSR_NC : read_data_r = `NUM_CORES * `NUM_CLUSTERS; @@ -223,7 +233,9 @@ module VX_csr_data #( `RUNTIME_ASSERT(~read_enable || read_addr_valid_r, ("invalid CSR read address: %0h", read_addr)) assign read_data = read_data_r; - - assign fpu_to_csr_if.read_frm = fcsr[fpu_to_csr_if.read_wid][`FRM_BITS+`FFG_BITS-1:`FFG_BITS]; + +`ifdef EXT_F_ENABLE + assign fpu_to_csr_if.read_frm = fcsr[fpu_to_csr_if.read_wid][`INST_FRM_BITS+`FFLAGS_BITS-1:`FFLAGS_BITS]; +`endif endmodule \ No newline at end of file diff --git a/hw/rtl/VX_csr_unit.v b/hw/rtl/VX_csr_unit.sv similarity index 82% rename from hw/rtl/VX_csr_unit.v rename to hw/rtl/VX_csr_unit.sv index 581c99e7..cfa89687 100644 --- a/hw/rtl/VX_csr_unit.v +++ b/hw/rtl/VX_csr_unit.sv @@ -3,28 +3,29 @@ module VX_csr_unit #( parameter CORE_ID = 0 ) ( - input wire clk, - input wire reset, + input wire clk, + input wire reset, `ifdef PERF_ENABLE - VX_perf_memsys_if perf_memsys_if, - VX_perf_pipeline_if perf_pipeline_if, + VX_perf_memsys_if.slave perf_memsys_if, + VX_perf_pipeline_if.slave perf_pipeline_if, `endif - VX_cmt_to_csr_if cmt_to_csr_if, - VX_fpu_to_csr_if fpu_to_csr_if, - -`ifdef EXT_TEX_ENABLE - VX_tex_csr_if tex_csr_if, -`endif + VX_cmt_to_csr_if.slave cmt_to_csr_if, + VX_fetch_to_csr_if.slave fetch_to_csr_if, + VX_csr_req_if.slave csr_req_if, + VX_commit_if.master csr_commit_if, - VX_csr_req_if csr_req_if, - VX_commit_if csr_commit_if, +`ifdef EXT_F_ENABLE + VX_fpu_to_csr_if.slave fpu_to_csr_if, + input wire[`NUM_WARPS-1:0] fpu_pending, +`endif +`ifdef EXT_TEX_ENABLE + VX_tex_csr_if.slave tex_csr_if, +`endif - input wire busy, - - input wire[`NUM_WARPS-1:0] fpu_pending, - output wire[`NUM_WARPS-1:0] pending + output wire[`NUM_WARPS-1:0] pending, + input wire busy ); wire csr_we_s1; wire [`CSR_ADDR_BITS-1:0] csr_addr_s1; @@ -33,7 +34,7 @@ module VX_csr_unit #( wire write_enable = csr_commit_if.valid && csr_we_s1; - wire [31:0] csr_req_data = csr_req_if.use_imm ? 32'(csr_req_if.rs1) : csr_req_if.rs1_data; + wire [31:0] csr_req_data = csr_req_if.use_imm ? 32'(csr_req_if.imm) : csr_req_if.rs1_data; VX_csr_data #( .CORE_ID(CORE_ID) @@ -45,6 +46,8 @@ module VX_csr_unit #( .perf_pipeline_if (perf_pipeline_if), `endif .cmt_to_csr_if (cmt_to_csr_if), + .fetch_to_csr_if(fetch_to_csr_if), + `ifdef EXT_F_ENABLE .fpu_to_csr_if (fpu_to_csr_if), `ifdef EXT_TEX_ENABLE .tex_csr_if (tex_csr_if), @@ -72,21 +75,25 @@ module VX_csr_unit #( always @(*) begin csr_we_s0_unqual = (csr_req_data != 0); case (csr_req_if.op_type) - `CSR_RW: begin + `INST_CSR_RW: begin csr_updated_data = csr_req_data; csr_we_s0_unqual = 1; end - `CSR_RS: begin + `INST_CSR_RS: begin csr_updated_data = csr_read_data_qual | csr_req_data; end - //`CSR_RC + //`INST_CSR_RC default: begin csr_updated_data = csr_read_data_qual & ~csr_req_data; end endcase end +`ifdef EXT_F_ENABLE wire stall_in = fpu_pending[csr_req_if.wid]; +`else + wire stall_in = 0; +`endif wire csr_req_valid = csr_req_if.valid && !stall_in; diff --git a/hw/rtl/VX_decode.v b/hw/rtl/VX_decode.sv similarity index 67% rename from hw/rtl/VX_decode.v rename to hw/rtl/VX_decode.sv index 0304830a..7d97bbcc 100644 --- a/hw/rtl/VX_decode.v +++ b/hw/rtl/VX_decode.sv @@ -1,16 +1,17 @@ `include "VX_define.vh" +`ifdef DBG_PRINT_PIPELINE `include "VX_print_instr.vh" +`endif `ifdef EXT_F_ENABLE - `define USED_IREG(r) \ - used_regs[{1'b0, r}] = 1 + `define USED_IREG(r) \ + r``_r = {1'b0, ``r} - `define USED_FREG(r) \ - r``_r[5] = 1; \ - used_regs[{1'b1, r}] = 1 + `define USED_FREG(r) \ + r``_r = {1'b1, ``r} `else `define USED_IREG(r) \ - used_regs[r] = 1 + r``_r = ``r `endif module VX_decode #( @@ -20,25 +21,24 @@ module VX_decode #( input wire reset, // inputs - VX_ifetch_rsp_if ifetch_rsp_if, + VX_ifetch_rsp_if.slave ifetch_rsp_if, // outputs - VX_decode_if decode_if, - VX_wstall_if wstall_if, - VX_join_if join_if + VX_decode_if.master decode_if, + VX_wstall_if.master wstall_if, + VX_join_if.master join_if ); `UNUSED_PARAM (CORE_ID) `UNUSED_VAR (clk) `UNUSED_VAR (reset) reg [`EX_BITS-1:0] ex_type; - reg [`OP_BITS-1:0] op_type; - reg [`MOD_BITS-1:0] op_mod; + reg [`INST_OP_BITS-1:0] op_type; + reg [`INST_MOD_BITS-1:0] op_mod; reg [`NR_BITS-1:0] rd_r, rs1_r, rs2_r, rs3_r; reg [31:0] imm; reg use_rd, use_PC, use_imm; reg is_join, is_wstall; - reg [`NUM_REGS-1:0] used_regs; wire [31:0] instr = ifetch_rsp_if.data; wire [6:0] opcode = instr[6:0]; @@ -58,36 +58,37 @@ module VX_decode #( wire [12:0] b_imm = {instr[31], instr[7], instr[30:25], instr[11:8], 1'b0}; wire [20:0] jal_imm = {instr[31], instr[19:12], instr[20], instr[30:21], 1'b0}; wire [11:0] jalr_imm = {func7, rs2}; + + `UNUSED_VAR (rs3) always @(*) begin ex_type = 0; op_type = 'x; op_mod = 0; - rd_r = `NR_BITS'(rd); - rs1_r = `NR_BITS'(rs1); - rs2_r = `NR_BITS'(rs2); - rs3_r = `NR_BITS'(rs3); + rd_r = 0; + rs1_r = 0; + rs2_r = 0; + rs3_r = 0; imm = 'x; use_imm = 0; use_PC = 0; use_rd = 0; is_join = 0; is_wstall = 0; - used_regs = 0; case (opcode) `INST_I: begin ex_type = `EX_ALU; case (func3) - 3'h0: op_type = `OP_BITS'(`ALU_ADD); - 3'h1: op_type = `OP_BITS'(`ALU_SLL); - 3'h2: op_type = `OP_BITS'(`ALU_SLT); - 3'h3: op_type = `OP_BITS'(`ALU_SLTU); - 3'h4: op_type = `OP_BITS'(`ALU_XOR); - 3'h5: op_type = (func7[5]) ? `OP_BITS'(`ALU_SRA) : `OP_BITS'(`ALU_SRL); - 3'h6: op_type = `OP_BITS'(`ALU_OR); - 3'h7: op_type = `OP_BITS'(`ALU_AND); + 3'h0: op_type = `INST_OP_BITS'(`INST_ALU_ADD); + 3'h1: op_type = `INST_OP_BITS'(`INST_ALU_SLL); + 3'h2: op_type = `INST_OP_BITS'(`INST_ALU_SLT); + 3'h3: op_type = `INST_OP_BITS'(`INST_ALU_SLTU); + 3'h4: op_type = `INST_OP_BITS'(`INST_ALU_XOR); + 3'h5: op_type = (func7[5]) ? `INST_OP_BITS'(`INST_ALU_SRA) : `INST_OP_BITS'(`INST_ALU_SRL); + 3'h6: op_type = `INST_OP_BITS'(`INST_ALU_OR); + 3'h7: op_type = `INST_OP_BITS'(`INST_ALU_AND); default:; endcase use_rd = 1; @@ -101,14 +102,14 @@ module VX_decode #( `ifdef EXT_F_ENABLE if (func7[0]) begin case (func3) - 3'h0: op_type = `OP_BITS'(`MUL_MUL); - 3'h1: op_type = `OP_BITS'(`MUL_MULH); - 3'h2: op_type = `OP_BITS'(`MUL_MULHSU); - 3'h3: op_type = `OP_BITS'(`MUL_MULHU); - 3'h4: op_type = `OP_BITS'(`MUL_DIV); - 3'h5: op_type = `OP_BITS'(`MUL_DIVU); - 3'h6: op_type = `OP_BITS'(`MUL_REM); - 3'h7: op_type = `OP_BITS'(`MUL_REMU); + 3'h0: op_type = `INST_OP_BITS'(`INST_MUL_MUL); + 3'h1: op_type = `INST_OP_BITS'(`INST_MUL_MULH); + 3'h2: op_type = `INST_OP_BITS'(`INST_MUL_MULHSU); + 3'h3: op_type = `INST_OP_BITS'(`INST_MUL_MULHU); + 3'h4: op_type = `INST_OP_BITS'(`INST_MUL_DIV); + 3'h5: op_type = `INST_OP_BITS'(`INST_MUL_DIVU); + 3'h6: op_type = `INST_OP_BITS'(`INST_MUL_REM); + 3'h7: op_type = `INST_OP_BITS'(`INST_MUL_REMU); default:; endcase op_mod = 2; @@ -116,14 +117,14 @@ module VX_decode #( `endif begin case (func3) - 3'h0: op_type = (func7[5]) ? `OP_BITS'(`ALU_SUB) : `OP_BITS'(`ALU_ADD); - 3'h1: op_type = `OP_BITS'(`ALU_SLL); - 3'h2: op_type = `OP_BITS'(`ALU_SLT); - 3'h3: op_type = `OP_BITS'(`ALU_SLTU); - 3'h4: op_type = `OP_BITS'(`ALU_XOR); - 3'h5: op_type = (func7[5]) ? `OP_BITS'(`ALU_SRA) : `OP_BITS'(`ALU_SRL); - 3'h6: op_type = `OP_BITS'(`ALU_OR); - 3'h7: op_type = `OP_BITS'(`ALU_AND); + 3'h0: op_type = (func7[5]) ? `INST_OP_BITS'(`INST_ALU_SUB) : `INST_OP_BITS'(`INST_ALU_ADD); + 3'h1: op_type = `INST_OP_BITS'(`INST_ALU_SLL); + 3'h2: op_type = `INST_OP_BITS'(`INST_ALU_SLT); + 3'h3: op_type = `INST_OP_BITS'(`INST_ALU_SLTU); + 3'h4: op_type = `INST_OP_BITS'(`INST_ALU_XOR); + 3'h5: op_type = (func7[5]) ? `INST_OP_BITS'(`INST_ALU_SRA) : `INST_OP_BITS'(`INST_ALU_SRL); + 3'h6: op_type = `INST_OP_BITS'(`INST_ALU_OR); + 3'h7: op_type = `INST_OP_BITS'(`INST_ALU_AND); default:; endcase end @@ -134,7 +135,7 @@ module VX_decode #( end `INST_LUI: begin ex_type = `EX_ALU; - op_type = `OP_BITS'(`ALU_LUI); + op_type = `INST_OP_BITS'(`INST_ALU_LUI); use_rd = 1; use_imm = 1; imm = {upper_imm, 12'(0)}; @@ -143,7 +144,7 @@ module VX_decode #( end `INST_AUIPC: begin ex_type = `EX_ALU; - op_type = `OP_BITS'(`ALU_AUIPC); + op_type = `INST_OP_BITS'(`INST_ALU_AUIPC); use_rd = 1; use_imm = 1; use_PC = 1; @@ -152,7 +153,7 @@ module VX_decode #( end `INST_JAL: begin ex_type = `EX_ALU; - op_type = `OP_BITS'(`BR_JAL); + op_type = `INST_OP_BITS'(`INST_BR_JAL); op_mod = 1; use_rd = 1; use_imm = 1; @@ -163,7 +164,7 @@ module VX_decode #( end `INST_JALR: begin ex_type = `EX_ALU; - op_type = `OP_BITS'(`BR_JALR); + op_type = `INST_OP_BITS'(`INST_BR_JALR); op_mod = 1; use_rd = 1; use_imm = 1; @@ -175,12 +176,12 @@ module VX_decode #( `INST_B: begin ex_type = `EX_ALU; case (func3) - 3'h0: op_type = `OP_BITS'(`BR_EQ); - 3'h1: op_type = `OP_BITS'(`BR_NE); - 3'h4: op_type = `OP_BITS'(`BR_LT); - 3'h5: op_type = `OP_BITS'(`BR_GE); - 3'h6: op_type = `OP_BITS'(`BR_LTU); - 3'h7: op_type = `OP_BITS'(`BR_GEU); + 3'h0: op_type = `INST_OP_BITS'(`INST_BR_EQ); + 3'h1: op_type = `INST_OP_BITS'(`INST_BR_NE); + 3'h4: op_type = `INST_OP_BITS'(`INST_BR_LT); + 3'h5: op_type = `INST_OP_BITS'(`INST_BR_GE); + 3'h6: op_type = `INST_OP_BITS'(`INST_BR_LTU); + 3'h7: op_type = `INST_OP_BITS'(`INST_BR_GEU); default:; endcase op_mod = 1; @@ -193,35 +194,37 @@ module VX_decode #( end `INST_F: begin ex_type = `EX_LSU; - op_mod = `MOD_BITS'(!func3[0]); // data fence + op_type = `INST_OP_BITS'(func3[0]); + op_mod = `INST_MOD_BITS'(1); end `INST_SYS : begin if (func3[1:0] != 0) begin ex_type = `EX_CSR; - op_type = `OP_BITS'(func3[1:0]); + op_type = `INST_OP_BITS'(func3[1:0]); use_rd = 1; use_imm = func3[2]; - imm = 32'(u_12); // addr + imm[`CSR_ADDR_BITS-1:0] = u_12; // addr `USED_IREG (rd); if (func3[2]) begin - rs1_r = `NR_BITS'(rs1); // imm + imm[`CSR_ADDR_BITS +: `NRI_BITS] = rs1; // imm end else begin `USED_IREG (rs1); end end else begin ex_type = `EX_ALU; case (u_12) - 12'h000: op_type = `OP_BITS'(`BR_ECALL); - 12'h001: op_type = `OP_BITS'(`BR_EBREAK); - 12'h302: op_type = `OP_BITS'(`BR_MRET); - 12'h102: op_type = `OP_BITS'(`BR_SRET); - 12'h7B2: op_type = `OP_BITS'(`BR_DRET); + 12'h000: op_type = `INST_OP_BITS'(`INST_BR_ECALL); + 12'h001: op_type = `INST_OP_BITS'(`INST_BR_EBREAK); + 12'h302: op_type = `INST_OP_BITS'(`INST_BR_MRET); + 12'h102: op_type = `INST_OP_BITS'(`INST_BR_SRET); + 12'h7B2: op_type = `INST_OP_BITS'(`INST_BR_DRET); default:; endcase op_mod = 1; use_rd = 1; use_imm = 1; use_PC = 1; + is_wstall = 1; imm = 32'd4; `USED_IREG (rd); end @@ -231,7 +234,7 @@ module VX_decode #( `endif `INST_L: begin ex_type = `EX_LSU; - op_type = `OP_BITS'({1'b0, func3}); + op_type = `INST_OP_BITS'({1'b0, func3}); use_rd = 1; imm = {{20{u_12[11]}}, u_12}; `ifdef EXT_F_ENABLE @@ -247,7 +250,7 @@ module VX_decode #( `endif `INST_S: begin ex_type = `EX_LSU; - op_type = `OP_BITS'({1'b1, func3}); + op_type = `INST_OP_BITS'({1'b1, func3}); imm = {{20{s_imm[11]}}, s_imm}; `USED_IREG (rs1); `ifdef EXT_F_ENABLE @@ -263,7 +266,7 @@ module VX_decode #( `INST_FNMSUB, `INST_FNMADD: begin ex_type = `EX_FPU; - op_type = `OP_BITS'(opcode[3:0]); + op_type = `INST_OP_BITS'(opcode[3:0]); op_mod = func3; use_rd = 1; `USED_FREG (rd); @@ -280,35 +283,35 @@ module VX_decode #( 7'h04, // FSUB 7'h08, // FMUL 7'h0C: begin // FDIV - op_type = `OP_BITS'(func7[3:0]); + op_type = `INST_OP_BITS'(func7[3:0]); `USED_FREG (rd); `USED_FREG (rs1); `USED_FREG (rs2); end 7'h2C: begin - op_type = `OP_BITS'(`FPU_SQRT); + op_type = `INST_OP_BITS'(`INST_FPU_SQRT); `USED_FREG (rd); `USED_FREG (rs1); end 7'h50: begin - op_type = `OP_BITS'(`FPU_CMP); + op_type = `INST_OP_BITS'(`INST_FPU_CMP); `USED_IREG (rd); `USED_FREG (rs1); `USED_FREG (rs2); end 7'h60: begin - op_type = (instr[20]) ? `OP_BITS'(`FPU_CVTWUS) : `OP_BITS'(`FPU_CVTWS); + op_type = (instr[20]) ? `INST_OP_BITS'(`INST_FPU_CVTWUS) : `INST_OP_BITS'(`INST_FPU_CVTWS); `USED_IREG (rd); `USED_FREG (rs1); end 7'h68: begin - op_type = (instr[20]) ? `OP_BITS'(`FPU_CVTSWU) : `OP_BITS'(`FPU_CVTSW); + op_type = (instr[20]) ? `INST_OP_BITS'(`INST_FPU_CVTSWU) : `INST_OP_BITS'(`INST_FPU_CVTSW); `USED_FREG (rd); `USED_IREG (rs1); end 7'h10: begin // FSGNJ=0, FSGNJN=1, FSGNJX=2 - op_type = `OP_BITS'(`FPU_MISC); + op_type = `INST_OP_BITS'(`INST_FPU_MISC); op_mod = {1'b0, func3[1:0]}; `USED_FREG (rd); `USED_FREG (rs1); @@ -316,7 +319,7 @@ module VX_decode #( end 7'h14: begin // FMIN=3, FMAX=4 - op_type = `OP_BITS'(`FPU_MISC); + op_type = `INST_OP_BITS'(`INST_FPU_MISC); op_mod = func3[0] ? 4 : 3; `USED_FREG (rd); `USED_FREG (rs1); @@ -325,10 +328,10 @@ module VX_decode #( 7'h70: begin if (func3[0]) begin // FCLASS - op_type = `OP_BITS'(`FPU_CLASS); + op_type = `INST_OP_BITS'(`INST_FPU_CLASS); end else begin // FMV.X.W=5 - op_type = `OP_BITS'(`FPU_MISC); + op_type = `INST_OP_BITS'(`INST_FPU_MISC); op_mod = 5; end `USED_IREG (rd); @@ -336,7 +339,7 @@ module VX_decode #( end 7'h78: begin // FMV.W.X=6 - op_type = `OP_BITS'(`FPU_MISC); + op_type = `INST_OP_BITS'(`INST_FPU_MISC); op_mod = 6; `USED_FREG (rd); `USED_IREG (rs1); @@ -349,26 +352,26 @@ module VX_decode #( ex_type = `EX_GPU; case (func3) 3'h0: begin - op_type = `OP_BITS'(`GPU_TMC); + op_type = rs2[0] ? `INST_OP_BITS'(`INST_GPU_PRED) : `INST_OP_BITS'(`INST_GPU_TMC); is_wstall = 1; `USED_IREG (rs1); end 3'h1: begin - op_type = `OP_BITS'(`GPU_WSPAWN); + op_type = `INST_OP_BITS'(`INST_GPU_WSPAWN); `USED_IREG (rs1); `USED_IREG (rs2); end 3'h2: begin - op_type = `OP_BITS'(`GPU_SPLIT); + op_type = `INST_OP_BITS'(`INST_GPU_SPLIT); is_wstall = 1; `USED_IREG (rs1); end 3'h3: begin - op_type = `OP_BITS'(`GPU_JOIN); + op_type = `INST_OP_BITS'(`INST_GPU_JOIN); is_join = 1; end 3'h4: begin - op_type = `OP_BITS'(`GPU_BAR); + op_type = `INST_OP_BITS'(`INST_GPU_BAR); is_wstall = 1; `USED_IREG (rs1); `USED_IREG (rs2); @@ -410,7 +413,6 @@ module VX_decode #( assign decode_if.imm = imm; assign decode_if.use_PC = use_PC; assign decode_if.use_imm = use_imm; - assign decode_if.used_regs = used_regs; /////////////////////////////////////////////////////////////////////////// @@ -419,19 +421,20 @@ module VX_decode #( assign join_if.valid = ifetch_rsp_fire && is_join; assign join_if.wid = ifetch_rsp_if.wid; - assign wstall_if.valid = ifetch_rsp_fire && is_wstall; + assign wstall_if.valid = ifetch_rsp_fire; assign wstall_if.wid = ifetch_rsp_if.wid; + assign wstall_if.stalled = is_wstall; assign ifetch_rsp_if.ready = decode_if.ready; `ifdef DBG_PRINT_PIPELINE always @(posedge clk) begin if (decode_if.valid && decode_if.ready) begin - $write("%t: core%0d-decode: wid=%0d, PC=%0h, ex=", $time, CORE_ID, decode_if.wid, decode_if.PC); + dpi_trace("%d: core%0d-decode: wid=%0d, PC=%0h, ex=", $time, CORE_ID, decode_if.wid, decode_if.PC); print_ex_type(decode_if.ex_type); - $write(", op="); + dpi_trace(", op="); print_ex_op(decode_if.ex_type, decode_if.op_type, decode_if.op_mod); - $write(", mod=%0d, tmask=%b, wb=%b, rd=%0d, rs1=%0d, rs2=%0d, rs3=%0d, imm=%0h, use_pc=%b, use_imm=%b, use_regs=%b\n", decode_if.op_mod, decode_if.tmask, decode_if.wb, decode_if.rd, decode_if.rs1, decode_if.rs2, decode_if.rs3, decode_if.imm, decode_if.use_PC, decode_if.use_imm, decode_if.used_regs); + dpi_trace(", mod=%0d, tmask=%b, wb=%b, rd=%0d, rs1=%0d, rs2=%0d, rs3=%0d, imm=%0h, use_pc=%b, use_imm=%b\n", decode_if.op_mod, decode_if.tmask, decode_if.wb, decode_if.rd, decode_if.rs1, decode_if.rs2, decode_if.rs3, decode_if.imm, decode_if.use_PC, decode_if.use_imm); end end `endif diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index a5a77de5..a8ad5d4f 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -14,14 +14,16 @@ `define NB_BITS `LOG2UP(`NUM_BARRIERS) -`define REQS_BITS `LOG2UP(NUM_REQS) +`define NUM_IREGS 32 + +`define NRI_BITS `LOG2UP(`NUM_IREGS) `define NTEX_BITS `LOG2UP(`NUM_TEX_UNITS) `ifdef EXT_F_ENABLE -`define NUM_REGS 64 +`define NUM_REGS (2 * `NUM_IREGS) `else -`define NUM_REGS 32 +`define NUM_REGS `NUM_IREGS `endif `define NR_BITS `LOG2UP(`NUM_REGS) @@ -34,6 +36,16 @@ /////////////////////////////////////////////////////////////////////////////// +`define EX_NOP 3'h0 +`define EX_ALU 3'h1 +`define EX_LSU 3'h2 +`define EX_CSR 3'h3 +`define EX_FPU 3'h4 +`define EX_GPU 3'h5 +`define EX_BITS 3 + +/////////////////////////////////////////////////////////////////////////////// + `define INST_LUI 7'b0110111 `define INST_AUIPC 7'b0010111 `define INST_JAL 7'b1101111 @@ -60,139 +72,126 @@ /////////////////////////////////////////////////////////////////////////////// -`define FRM_RNE 3'b000 // round to nearest even -`define FRM_RTZ 3'b001 // round to zero -`define FRM_RDN 3'b010 // round to -inf -`define FRM_RUP 3'b011 // round to +inf -`define FRM_RMM 3'b100 // round to nearest max magnitude -`define FRM_DYN 3'b111 // dynamic mode -`define FRM_BITS 3 +`define INST_FRM_RNE 3'b000 // round to nearest even +`define INST_FRM_RTZ 3'b001 // round to zero +`define INST_FRM_RDN 3'b010 // round to -inf +`define INST_FRM_RUP 3'b011 // round to +inf +`define INST_FRM_RMM 3'b100 // round to nearest max magnitude +`define INST_FRM_DYN 3'b111 // dynamic mode +`define INST_FRM_BITS 3 /////////////////////////////////////////////////////////////////////////////// -`define EX_NOP 3'h0 -`define EX_ALU 3'h1 -`define EX_LSU 3'h2 -`define EX_CSR 3'h3 -`define EX_FPU 3'h4 -`define EX_GPU 3'h5 -`define EX_BITS 3 - -`define NUM_EXS 6 -`define NE_BITS `LOG2UP(`NUM_EXS) +`define INST_OP_BITS 4 +`define INST_MOD_BITS 3 /////////////////////////////////////////////////////////////////////////////// -`define OP_BITS 4 -`define MOD_BITS 3 +`define INST_ALU_ADD 4'b0000 +`define INST_ALU_LUI 4'b0010 +`define INST_ALU_AUIPC 4'b0011 +`define INST_ALU_SLTU 4'b0100 +`define INST_ALU_SLT 4'b0101 +`define INST_ALU_SRL 4'b1000 +`define INST_ALU_SRA 4'b1001 +`define INST_ALU_SUB 4'b1011 +`define INST_ALU_AND 4'b1100 +`define INST_ALU_OR 4'b1101 +`define INST_ALU_XOR 4'b1110 +`define INST_ALU_SLL 4'b1111 +`define INST_ALU_OTHER 4'b0111 +`define INST_ALU_BITS 4 +`define INST_ALU_OP(x) x[`INST_ALU_BITS-1:0] +`define INST_ALU_OP_CLASS(x) x[3:2] +`define INST_ALU_SIGNED(x) x[0] +`define INST_ALU_IS_BR(x) x[0] +`define INST_ALU_IS_MUL(x) x[1] -`define ALU_ADD 4'b0000 -`define ALU_LUI 4'b0010 -`define ALU_AUIPC 4'b0011 -`define ALU_SLTU 4'b0100 -`define ALU_SLT 4'b0101 -`define ALU_SRL 4'b1000 -`define ALU_SRA 4'b1001 -`define ALU_SUB 4'b1011 -`define ALU_AND 4'b1100 -`define ALU_OR 4'b1101 -`define ALU_XOR 4'b1110 -`define ALU_SLL 4'b1111 -`define ALU_OTHER 4'b0111 -`define ALU_BITS 4 -`define ALU_OP(x) x[`ALU_BITS-1:0] -`define ALU_OP_CLASS(x) x[3:2] -`define ALU_SIGNED(x) x[0] -`define ALU_IS_BR(x) x[0] -`define ALU_IS_MUL(x) x[1] +`define INST_BR_EQ 4'b0000 +`define INST_BR_NE 4'b0010 +`define INST_BR_LTU 4'b0100 +`define INST_BR_GEU 4'b0110 +`define INST_BR_LT 4'b0101 +`define INST_BR_GE 4'b0111 +`define INST_BR_JAL 4'b1000 +`define INST_BR_JALR 4'b1001 +`define INST_BR_ECALL 4'b1010 +`define INST_BR_EBREAK 4'b1011 +`define INST_BR_MRET 4'b1100 +`define INST_BR_SRET 4'b1101 +`define INST_BR_DRET 4'b1110 +`define INST_BR_OTHER 4'b1111 +`define INST_BR_BITS 4 +`define INST_BR_NEG(x) x[1] +`define INST_BR_LESS(x) x[2] +`define INST_BR_STATIC(x) x[3] -`define BR_EQ 4'b0000 -`define BR_NE 4'b0010 -`define BR_LTU 4'b0100 -`define BR_GEU 4'b0110 -`define BR_LT 4'b0101 -`define BR_GE 4'b0111 -`define BR_JAL 4'b1000 -`define BR_JALR 4'b1001 -`define BR_ECALL 4'b1010 -`define BR_EBREAK 4'b1011 -`define BR_MRET 4'b1100 -`define BR_SRET 4'b1101 -`define BR_DRET 4'b1110 -`define BR_OTHER 4'b1111 -`define BR_BITS 4 -`define BR_OP(x) x[`BR_BITS-1:0] -`define BR_NEG(x) x[1] -`define BR_LESS(x) x[2] -`define BR_STATIC(x) x[3] +`define INST_MUL_MUL 3'h0 +`define INST_MUL_MULH 3'h1 +`define INST_MUL_MULHSU 3'h2 +`define INST_MUL_MULHU 3'h3 +`define INST_MUL_DIV 3'h4 +`define INST_MUL_DIVU 3'h5 +`define INST_MUL_REM 3'h6 +`define INST_MUL_REMU 3'h7 +`define INST_MUL_BITS 3 +`define INST_MUL_IS_DIV(x) x[2] -`define MUL_MUL 3'h0 -`define MUL_MULH 3'h1 -`define MUL_MULHSU 3'h2 -`define MUL_MULHU 3'h3 -`define MUL_DIV 3'h4 -`define MUL_DIVU 3'h5 -`define MUL_REM 3'h6 -`define MUL_REMU 3'h7 -`define MUL_BITS 3 -`define MUL_OP(x) x[`MUL_BITS-1:0] -`define MUL_IS_DIV(x) x[2] +`define INST_FMT_B 3'b000 +`define INST_FMT_H 3'b001 +`define INST_FMT_W 3'b010 +`define INST_FMT_BU 3'b100 +`define INST_FMT_HU 3'b101 -`define FMT_B 3'b000 -`define FMT_H 3'b001 -`define FMT_W 3'b010 -`define FMT_BU 3'b100 -`define FMT_HU 3'b101 +`define INST_LSU_LB 4'b0000 +`define INST_LSU_LH 4'b0001 +`define INST_LSU_LW 4'b0010 +`define INST_LSU_LBU 4'b0100 +`define INST_LSU_LHU 4'b0101 +`define INST_LSU_SB 4'b1000 +`define INST_LSU_SH 4'b1001 +`define INST_LSU_SW 4'b1010 +`define INST_LSU_BITS 4 +`define INST_LSU_FMT(x) x[2:0] +`define INST_LSU_WSIZE(x) x[1:0] +`define INST_LSU_IS_FENCE(x) x[0] -`define LSU_LB 4'b0000 -`define LSU_LH 4'b0001 -`define LSU_LW 4'b0010 -`define LSU_LBU 4'b0100 -`define LSU_LHU 4'b0101 -`define LSU_SB 4'b1000 -`define LSU_SH 4'b1001 -`define LSU_SW 4'b1010 -`define LSU_BITS 4 -`define LSU_FMT(x) x[2:0] -`define LSU_WSIZE(x) x[1:0] -`define LSU_OP(x) x[`LSU_BITS-1:0] -`define LSU_IS_FENCE(x) x[0] +`define INST_FENCE_BITS 1 +`define INST_FENCE_D 1'h0 +`define INST_FENCE_I 1'h1 -`define CSR_RW 2'h1 -`define CSR_RS 2'h2 -`define CSR_RC 2'h3 -`define CSR_OTHER 2'h0 -`define CSR_BITS 2 -`define CSR_OP(x) x[`CSR_BITS-1:0] +`define INST_CSR_RW 2'h1 +`define INST_CSR_RS 2'h2 +`define INST_CSR_RC 2'h3 +`define INST_CSR_OTHER 2'h0 +`define INST_CSR_BITS 2 -`define FPU_ADD 4'h0 -`define FPU_SUB 4'h4 -`define FPU_MUL 4'h8 -`define FPU_DIV 4'hC -`define FPU_CVTWS 4'h1 // FCVT.W.S -`define FPU_CVTWUS 4'h5 // FCVT.WU.S -`define FPU_CVTSW 4'h9 // FCVT.S.W -`define FPU_CVTSWU 4'hD // FCVT.S.WU -`define FPU_SQRT 4'h2 -`define FPU_CLASS 4'h6 -`define FPU_CMP 4'hA -`define FPU_MISC 4'hE // SGNJ, SGNJN, SGNJX, FMIN, FMAX, MVXW, MVWX -`define FPU_MADD 4'h3 -`define FPU_MSUB 4'h7 -`define FPU_NMSUB 4'hB -`define FPU_NMADD 4'hF -`define FPU_BITS 4 -`define FPU_OP(x) x[`FPU_BITS-1:0] +`define INST_FPU_ADD 4'h0 +`define INST_FPU_SUB 4'h4 +`define INST_FPU_MUL 4'h8 +`define INST_FPU_DIV 4'hC +`define INST_FPU_CVTWS 4'h1 // FCVT.W.S +`define INST_FPU_CVTWUS 4'h5 // FCVT.WU.S +`define INST_FPU_CVTSW 4'h9 // FCVT.S.W +`define INST_FPU_CVTSWU 4'hD // FCVT.S.WU +`define INST_FPU_SQRT 4'h2 +`define INST_FPU_CLASS 4'h6 +`define INST_FPU_CMP 4'hA +`define INST_FPU_MISC 4'hE // SGNJ, SGNJN, SGNJX, FMIN, FMAX, MVXW, MVWX +`define INST_FPU_MADD 4'h3 +`define INST_FPU_MSUB 4'h7 +`define INST_FPU_NMSUB 4'hB +`define INST_FPU_NMADD 4'hF +`define INST_FPU_BITS 4 -`define GPU_TMC 3'h0 -`define GPU_WSPAWN 3'h1 -`define GPU_SPLIT 3'h2 -`define GPU_JOIN 3'h3 -`define GPU_BAR 3'h4 -`define GPU_TEX 3'h5 -`define GPU_OTHER 3'h7 -`define GPU_BITS 3 -`define GPU_OP(x) x[`GPU_BITS-1:0] +`define INST_GPU_TMC 3'h0 +`define INST_GPU_WSPAWN 3'h1 +`define INST_GPU_SPLIT 3'h2 +`define INST_GPU_JOIN 3'h3 +`define INST_GPU_BAR 3'h4 +`define INST_GPU_PRED 3'h5 +`define INST_GPU_TEX 3'h6 +`define INST_GPU_BITS 3 /////////////////////////////////////////////////////////////////////////////// @@ -244,59 +243,44 @@ `endif // non-cacheable address bit -`define NC_ADDR_BITS 1 +`define NC_FLAG_BITS 1 ////////////////////////// Icache Configurable Knobs ////////////////////////// // Cache ID `define ICACHE_ID (32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 0) -// Block size in bytes -`define ICACHE_LINE_SIZE (`L2_ENABLE ? `L1_BLOCK_SIZE : `MEM_BLOCK_SIZE) - // Word size in bytes -`define IWORD_SIZE 4 +`define ICACHE_WORD_SIZE 4 -// Number of banks -`define INUM_BANKS 1 - -// Core request address bits -`define ICORE_ADDR_WIDTH (32-`CLOG2(`IWORD_SIZE)) - -// Core request byte enable bits -`define ICORE_BYTEEN_WIDTH `DWORD_SIZE +// Block size in bytes +`define ICACHE_LINE_SIZE `L1_BLOCK_SIZE // TAG sharing enable -`define ICORE_TAG_ID_BITS `NW_BITS +`define ICACHE_CORE_TAG_ID_BITS `NW_BITS // Core request tag bits -`define ICORE_TAG_WIDTH (`DBG_CACHE_REQ_MDATAW + `ICORE_TAG_ID_BITS) +`define ICACHE_CORE_TAG_WIDTH (`DBG_CACHE_REQ_MDATAW + `ICACHE_CORE_TAG_ID_BITS) // Memory request data bits -`define IMEM_DATA_WIDTH (`ICACHE_LINE_SIZE * 8) +`define ICACHE_MEM_DATA_WIDTH (`ICACHE_LINE_SIZE * 8) // Memory request address bits -`define IMEM_ADDR_WIDTH (32 - `CLOG2(`ICACHE_LINE_SIZE)) - -// Memory byte enable bits -`define IMEM_BYTEEN_WIDTH `ICACHE_LINE_SIZE +`define ICACHE_MEM_ADDR_WIDTH (32 - `CLOG2(`ICACHE_LINE_SIZE)) // Memory request tag bits -`define IMEM_TAG_WIDTH `IMEM_ADDR_WIDTH +`define ICACHE_MEM_TAG_WIDTH `CLOG2(`ICACHE_MSHR_SIZE) ////////////////////////// Dcache Configurable Knobs ////////////////////////// // Cache ID `define DCACHE_ID (32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 1) -// Block size in bytes -`define DCACHE_LINE_SIZE (`L2_ENABLE ? `L1_BLOCK_SIZE : `MEM_BLOCK_SIZE) - // Word size in bytes -`define DWORD_SIZE 4 +`define DCACHE_WORD_SIZE 4 -// Core request address bits -`define DCORE_ADDR_WIDTH (32-`CLOG2(`DWORD_SIZE)) +// Block size in bytes +`define DCACHE_LINE_SIZE `L1_BLOCK_SIZE // Core request tag bits `define LSUQ_ADDR_BITS `LOG2UP(`LSUQ_SIZE) @@ -304,126 +288,127 @@ `define LSU_TAG_ID_BITS (`LSUQ_ADDR_BITS + `NC_ADDR_BITS + `SM_ENABLE) `define TEX_TAG_ID_BITS (2) `define LSU_TEX_TAG_ID_BITS `MAX(`LSU_TAG_ID_BITS, `TEX_TAG_ID_BITS) -`define DCORE_TAG_ID_BITS (`LSU_TEX_TAG_ID_BITS + 1) +`define DCACHE_DCORE_TAG_ID_BITS (`LSU_TEX_TAG_ID_BITS + `NC_FLAG_BITS) `define LSU_DCACHE_TAG_BITS (`DBG_CACHE_REQ_MDATAW + `LSU_TAG_ID_BITS) `define TEX_DCACHE_TAG_BITS (`DBG_CACHE_REQ_MDATAW + `TEX_TAG_ID_BITS) `define LSU_TEX_DCACHE_TAG_BITS (`DBG_CACHE_REQ_MDATAW + `LSU_TEX_TAG_ID_BITS) `else -`define DCORE_TAG_ID_BITS (`LSUQ_ADDR_BITS + `NC_ADDR_BITS + `SM_ENABLE) +`define DCACHE_DCORE_TAG_ID_BITS (`LSUQ_ADDR_BITS + `NC_ADDR_BITS + `SM_ENABLE) `endif -`define DCORE_TAG_WIDTH (`DBG_CACHE_REQ_MDATAW + `DCORE_TAG_ID_BITS) +`define DCACHE_DCORE_TAG_WIDTH (`DBG_CACHE_REQ_MDATAW + `DCACHE_CORE_TAG_ID_BITS) // Memory request data bits -`define DMEM_DATA_WIDTH (`DCACHE_LINE_SIZE * 8) +`define DCACHE_MEM_DATA_WIDTH (`DCACHE_LINE_SIZE * 8) // Memory request address bits -`define DMEM_ADDR_WIDTH (32 - `CLOG2(`DCACHE_LINE_SIZE)) +`define DCACHE_MEM_ADDR_WIDTH (32 - `CLOG2(`DCACHE_LINE_SIZE)) // Memory byte enable bits -`define DMEM_BYTEEN_WIDTH `DCACHE_LINE_SIZE +`define DCACHE_MEM_BYTEEN_WIDTH `DCACHE_LINE_SIZE // Input request size -`define DNUM_REQS `NUM_THREADS +`define DCACHE_NUM_REQS `NUM_THREADS // Memory request tag bits -`define _DMEM_ADDR_RATIO_W $clog2(`DCACHE_LINE_SIZE / `DWORD_SIZE) -`define _DNC_MEM_TAG_WIDTH ($clog2(`DNUM_REQS) + `_DMEM_ADDR_RATIO_W + `DCORE_TAG_WIDTH) -`define DMEM_TAG_WIDTH `MAX((`DMEM_ADDR_WIDTH + `NC_ADDR_BITS), `_DNC_MEM_TAG_WIDTH) +`define _DMEM_ADDR_RATIO_W $clog2(`DCACHE_LINE_SIZE / `DCACHE_WORD_SIZE) +`define _DNC_MEM_TAG_WIDTH ($clog2(`DCACHE_NUM_REQS) + `_DMEM_ADDR_RATIO_W + `DCACHE_CORE_TAG_WIDTH) +`define DCACHE_MEM_TAG_WIDTH `MAX((`CLOG2(`DCACHE_NUM_BANKS) + `CLOG2(`DCACHE_MSHR_SIZE) + `NC_FLAG_BITS), `_DNC_MEM_TAG_WIDTH) + +// Merged D-cache/I-cache memory tag +`define L1_MEM_TAG_WIDTH (`MAX(`ICACHE_MEM_TAG_WIDTH, `DCACHE_MEM_TAG_WIDTH) + `CLOG2(2)) ////////////////////////// SM Configurable Knobs ////////////////////////////// // Cache ID -`define SCACHE_ID (32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 2) +`define SMEM_ID (32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 2) // Word size in bytes -`define SWORD_SIZE 4 +`define SMEM_WORD_SIZE 4 // bank address offset -`define SBANK_ADDR_OFFSET `CLOG2(`STACK_SIZE / `SWORD_SIZE) +`define SMEM_BANK_ADDR_OFFSET `CLOG2(`STACK_SIZE / `SMEM_WORD_SIZE) // Input request size -`define SNUM_REQS `NUM_THREADS +`define SMEM_NUM_REQS `NUM_THREADS ////////////////////////// L2cache Configurable Knobs ///////////////////////// // Cache ID -`define L2CACHE_ID (32'(`L3_ENABLE) + CLUSTER_ID) - -// Block size in bytes -`define L2CACHE_LINE_SIZE `MEM_BLOCK_SIZE +`define L2_CACHE_ID (32'(`L3_ENABLE) + CLUSTER_ID) // Word size in bytes -`define L2WORD_SIZE `DCACHE_LINE_SIZE +`define L2_WORD_SIZE `DCACHE_LINE_SIZE + +// Block size in bytes +`define L2_CACHE_LINE_SIZE ((`L2_ENABLE) ? `MEM_BLOCK_SIZE : `L2_WORD_SIZE) // Input request tag bits -`define L2CORE_TAG_WIDTH (`DCORE_TAG_WIDTH + `CLOG2(`NUM_CORES)) +`define L2_CORE_TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH + `CLOG2(`NUM_CORES)) // Memory request data bits -`define L2MEM_DATA_WIDTH (`L2CACHE_LINE_SIZE * 8) +`define L2_MEM_DATA_WIDTH (`L2_CACHE_LINE_SIZE * 8) // Memory request address bits -`define L2MEM_ADDR_WIDTH (32 - `CLOG2(`L2CACHE_LINE_SIZE)) +`define L2_MEM_ADDR_WIDTH (32 - `CLOG2(`L2_CACHE_LINE_SIZE)) // Memory byte enable bits -`define L2MEM_BYTEEN_WIDTH `L2CACHE_LINE_SIZE +`define L2_MEM_BYTEEN_WIDTH `L2_CACHE_LINE_SIZE // Input request size -`define L2NUM_REQS `NUM_CORES +`define L2_NUM_REQS `NUM_CORES // Memory request tag bits -`define _L2MEM_ADDR_RATIO_W $clog2(`L2CACHE_LINE_SIZE / `L2WORD_SIZE) -`define _L2NC_MEM_TAG_WIDTH ($clog2(`L2NUM_REQS) + `_L2MEM_ADDR_RATIO_W + `XMEM_TAG_WIDTH) -`define _L2MEM_TAG_WIDTH `MAX((`L2MEM_ADDR_WIDTH + `NC_ADDR_BITS), `_L2NC_MEM_TAG_WIDTH) -`define L2MEM_TAG_WIDTH (`L2_ENABLE ? `_L2MEM_TAG_WIDTH : (`XMEM_TAG_WIDTH + `CLOG2(`L2NUM_REQS))) +`define _L2_MEM_ADDR_RATIO_W $clog2(`L2_CACHE_LINE_SIZE / `L2_WORD_SIZE) +`define _L2_NC_MEM_TAG_WIDTH ($clog2(`L2_NUM_REQS) + `_L2_MEM_ADDR_RATIO_W + `L1_MEM_TAG_WIDTH) +`define _L2_MEM_TAG_WIDTH `MAX((`CLOG2(`L2_NUM_BANKS) + `CLOG2(`L2_MSHR_SIZE) + `NC_FLAG_BITS), `_L2_NC_MEM_TAG_WIDTH) +`define L2_MEM_TAG_WIDTH ((`L2_ENABLE) ? `_L2_MEM_TAG_WIDTH : (`L1_MEM_TAG_WIDTH + `CLOG2(`L2_NUM_REQS))) ////////////////////////// L3cache Configurable Knobs ///////////////////////// // Cache ID -`define L3CACHE_ID 0 - -// Block size in bytes -`define L3CACHE_LINE_SIZE `MEM_BLOCK_SIZE +`define L3_CACHE_ID 0 // Word size in bytes -`define L3WORD_SIZE `L2CACHE_LINE_SIZE +`define L3_WORD_SIZE `L2_CACHE_LINE_SIZE + +// Block size in bytes +`define L3_CACHE_LINE_SIZE ((`L3_ENABLE) ? `MEM_BLOCK_SIZE : `L3_WORD_SIZE) // Input request tag bits -`define L3CORE_TAG_WIDTH (`L2CORE_TAG_WIDTH + `CLOG2(`NUM_CLUSTERS)) +`define L3_CORE_TAG_WIDTH (`L2_CORE_TAG_WIDTH + `CLOG2(`NUM_CLUSTERS)) // Memory request data bits -`define L3MEM_DATA_WIDTH (`L3CACHE_LINE_SIZE * 8) +`define L3_MEM_DATA_WIDTH (`L3_CACHE_LINE_SIZE * 8) // Memory request address bits -`define L3MEM_ADDR_WIDTH (32 - `CLOG2(`L3CACHE_LINE_SIZE)) +`define L3_MEM_ADDR_WIDTH (32 - `CLOG2(`L3_CACHE_LINE_SIZE)) // Memory byte enable bits -`define L3MEM_BYTEEN_WIDTH `L3CACHE_LINE_SIZE +`define L3_MEM_BYTEEN_WIDTH `L3_CACHE_LINE_SIZE // Input request size -`define L3NUM_REQS `NUM_CLUSTERS +`define L3_NUM_REQS `NUM_CLUSTERS // Memory request tag bits -`define _L3MEM_ADDR_RATIO_W $clog2(`L3CACHE_LINE_SIZE / `L3WORD_SIZE) -`define _L3NC_MEM_TAG_WIDTH ($clog2(`L3NUM_REQS) + `_L3MEM_ADDR_RATIO_W + `L2MEM_TAG_WIDTH) -`define _L3MEM_TAG_WIDTH `MAX((`L3MEM_ADDR_WIDTH + `NC_ADDR_BITS), `_L3NC_MEM_TAG_WIDTH) -`define L3MEM_TAG_WIDTH (`L3_ENABLE ? `_L3MEM_TAG_WIDTH : (`L2MEM_TAG_WIDTH + `CLOG2(`L3NUM_REQS))) +`define _L3_MEM_ADDR_RATIO_W $clog2(`L3_CACHE_LINE_SIZE / `L3_WORD_SIZE) +`define _L3_NC_MEM_TAG_WIDTH ($clog2(`L3_NUM_REQS) + `_L3_MEM_ADDR_RATIO_W + `L2_MEM_TAG_WIDTH) +`define _L3_MEM_TAG_WIDTH `MAX((`CLOG2(`L3_NUM_BANKS) + `CLOG2(`L3_MSHR_SIZE) + `NC_FLAG_BITS), `_L3_NC_MEM_TAG_WIDTH) +`define L3_MEM_TAG_WIDTH ((`L3_ENABLE) ? `_L3_MEM_TAG_WIDTH : (`L2_MEM_TAG_WIDTH + `CLOG2(`L3_NUM_REQS))) /////////////////////////////////////////////////////////////////////////////// -`define VX_MEM_BYTEEN_WIDTH `L3MEM_BYTEEN_WIDTH -`define VX_MEM_ADDR_WIDTH `L3MEM_ADDR_WIDTH -`define VX_MEM_DATA_WIDTH `L3MEM_DATA_WIDTH -`define VX_MEM_TAG_WIDTH `L3MEM_TAG_WIDTH -`define VX_CORE_TAG_WIDTH `L3CORE_TAG_WIDTH +`define VX_MEM_BYTEEN_WIDTH `L3_MEM_BYTEEN_WIDTH +`define VX_MEM_ADDR_WIDTH `L3_MEM_ADDR_WIDTH +`define VX_MEM_DATA_WIDTH `L3_MEM_DATA_WIDTH +`define VX_MEM_TAG_WIDTH `L3_MEM_TAG_WIDTH +`define VX_CORE_TAG_WIDTH `L3_CORE_TAG_WIDTH `define VX_CSR_ID_WIDTH `LOG2UP(`NUM_CLUSTERS * `NUM_CORES) `define TO_FULL_ADDR(x) {x, (32-$bits(x))'(0)} -// Merged D-cache/I-cache memory tag -`define XMEM_TAG_WIDTH (`DMEM_TAG_WIDTH + `CLOG2(2)) +/////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////// - -`include "VX_types.vh" +`include "VX_fpu_types.vh" +`include "VX_gpu_types.vh" `endif diff --git a/hw/rtl/VX_execute.v b/hw/rtl/VX_execute.sv similarity index 80% rename from hw/rtl/VX_execute.v rename to hw/rtl/VX_execute.sv index 4480bde7..127e3f5e 100644 --- a/hw/rtl/VX_execute.v +++ b/hw/rtl/VX_execute.sv @@ -9,35 +9,42 @@ module VX_execute #( input wire reset, // Dcache interface - VX_dcache_req_if dcache_req_if, - VX_dcache_rsp_if dcache_rsp_if, + VX_dcache_req_if.master dcache_req_if, + VX_dcache_rsp_if.slave dcache_rsp_if, - // commit status - VX_cmt_to_csr_if cmt_to_csr_if, + // commit interface + VX_cmt_to_csr_if.slave cmt_to_csr_if, + + // fetch interface + VX_fetch_to_csr_if.slave fetch_to_csr_if, `ifdef PERF_ENABLE - VX_perf_memsys_if perf_memsys_if, - VX_perf_pipeline_if perf_pipeline_if, + VX_perf_memsys_if.slave perf_memsys_if, + VX_perf_pipeline_if.slave perf_pipeline_if, `endif // inputs - VX_alu_req_if alu_req_if, - VX_lsu_req_if lsu_req_if, - VX_csr_req_if csr_req_if, - VX_fpu_req_if fpu_req_if, - VX_gpu_req_if gpu_req_if, + VX_alu_req_if.slave alu_req_if, + VX_lsu_req_if.slave lsu_req_if, + VX_csr_req_if.slave csr_req_if, +`ifdef EXT_F_ENABLE + VX_fpu_req_if.slave fpu_req_if, +`endif + VX_gpu_req_if.slave gpu_req_if, // outputs - VX_branch_ctl_if branch_ctl_if, - VX_warp_ctl_if warp_ctl_if, - VX_commit_if alu_commit_if, - VX_commit_if ld_commit_if, - VX_commit_if st_commit_if, - VX_commit_if csr_commit_if, - VX_commit_if fpu_commit_if, - VX_commit_if gpu_commit_if, + VX_branch_ctl_if.master branch_ctl_if, + VX_warp_ctl_if.master warp_ctl_if, + VX_commit_if.master alu_commit_if, + VX_commit_if.master ld_commit_if, + VX_commit_if.master st_commit_if, + VX_commit_if.master csr_commit_if, +`ifdef EXT_F_ENABLE + VX_commit_if.master fpu_commit_if, +`endif + VX_commit_if.master gpu_commit_if, - input wire busy + input wire busy ); VX_fpu_to_csr_if fpu_to_csr_if(); @@ -178,8 +185,8 @@ module VX_execute #( .clk (clk), .reset (csr_reset), `ifdef PERF_ENABLE - .perf_memsys_if (perf_memsys_if), - .perf_pipeline_if (perf_pipeline_if), + .perf_memsys_if (perf_memsys_if), + .perf_pipeline_if(perf_pipeline_if), `endif .cmt_to_csr_if (cmt_to_csr_if), .fpu_to_csr_if (fpu_to_csr_if), @@ -188,8 +195,13 @@ module VX_execute #( `endif .csr_req_if (csr_req_if), .csr_commit_if (csr_commit_if), - .fpu_pending (fpu_pending), + `ifdef EXT_F_ENABLE + .fpu_to_csr_if (fpu_to_csr_if), + .fpu_pending (fpu_pending), .pending (csr_pending), + `else + `UNUSED_PIN (pending), + `endif .busy (busy) ); @@ -207,22 +219,6 @@ module VX_execute #( .csr_pending (csr_pending), .pending (fpu_pending) ); -`else - `UNUSED_VAR (csr_pending) - `UNUSED_VAR (fpu_to_csr_if.read_frm) - assign fpu_req_if.ready = 0; - assign fpu_commit_if.valid = 0; - assign fpu_commit_if.wid = 0; - assign fpu_commit_if.PC = 0; - assign fpu_commit_if.tmask = 0; - assign fpu_commit_if.wb = 0; - assign fpu_commit_if.rd = 0; - assign fpu_commit_if.data = 0; - assign fpu_to_csr_if.write_enable = 0; - assign fpu_to_csr_if.write_wid = 0; - assign fpu_to_csr_if.write_fflags = 0; - assign fpu_to_csr_if.read_wid = 0; - assign fpu_pending = 0; `endif VX_gpu_unit #( @@ -244,8 +240,8 @@ module VX_execute #( // special workaround to get RISC-V tests Pass/Fail status wire ebreak /* verilator public */; assign ebreak = alu_req_if.valid && alu_req_if.ready - && `ALU_IS_BR(alu_req_if.op_mod) - && (`BR_OP(alu_req_if.op_type) == `BR_EBREAK - || `BR_OP(alu_req_if.op_type) == `BR_ECALL); + && `INST_ALU_IS_BR(alu_req_if.op_mod) + && (`INST_BR_BITS'(alu_req_if.op_type) == `INST_BR_EBREAK + || `INST_BR_BITS'(alu_req_if.op_type) == `INST_BR_ECALL); endmodule \ No newline at end of file diff --git a/hw/rtl/VX_fetch.v b/hw/rtl/VX_fetch.sv similarity index 66% rename from hw/rtl/VX_fetch.v rename to hw/rtl/VX_fetch.sv index 5760beea..7db7faab 100644 --- a/hw/rtl/VX_fetch.v +++ b/hw/rtl/VX_fetch.sv @@ -9,19 +9,23 @@ module VX_fetch #( input wire reset, // Icache interface - VX_icache_req_if icache_req_if, - VX_icache_rsp_if icache_rsp_if, + VX_icache_req_if.master icache_req_if, + VX_icache_rsp_if.slave icache_rsp_if, // inputs - VX_wstall_if wstall_if, - VX_join_if join_if, - VX_branch_ctl_if branch_ctl_if, - VX_warp_ctl_if warp_ctl_if, + VX_wstall_if.slave wstall_if, + VX_join_if.slave join_if, + VX_branch_ctl_if.slave branch_ctl_if, + VX_warp_ctl_if.slave warp_ctl_if, // outputs - VX_ifetch_rsp_if ifetch_rsp_if, + VX_ifetch_rsp_if.master ifetch_rsp_if, - output wire busy + // csr interface + VX_fetch_to_csr_if.master fetch_to_csr_if, + + // busy status + output wire busy ); VX_ifetch_req_if ifetch_req_if(); @@ -32,13 +36,17 @@ module VX_fetch #( `SCOPE_BIND_VX_fetch_warp_sched .clk (clk), - .reset (reset), + .reset (reset), + .warp_ctl_if (warp_ctl_if), .wstall_if (wstall_if), .join_if (join_if), .branch_ctl_if (branch_ctl_if), + .ifetch_req_if (ifetch_req_if), - .ifetch_rsp_if (ifetch_rsp_if), + + .fetch_to_csr_if (fetch_to_csr_if), + .busy (busy) ); diff --git a/hw/rtl/VX_fpu_unit.v b/hw/rtl/VX_fpu_unit.sv similarity index 94% rename from hw/rtl/VX_fpu_unit.v rename to hw/rtl/VX_fpu_unit.sv index b6a575ff..7b0f07cc 100644 --- a/hw/rtl/VX_fpu_unit.v +++ b/hw/rtl/VX_fpu_unit.sv @@ -3,21 +3,18 @@ module VX_fpu_unit #( parameter CORE_ID = 0 ) ( - // inputs input wire clk, input wire reset, - // inputs - VX_fpu_req_if fpu_req_if, - - // outputs - VX_fpu_to_csr_if fpu_to_csr_if, - VX_commit_if fpu_commit_if, + VX_fpu_req_if.slave fpu_req_if, + VX_fpu_to_csr_if.master fpu_to_csr_if, + VX_commit_if.master fpu_commit_if, input wire[`NUM_WARPS-1:0] csr_pending, output wire[`NUM_WARPS-1:0] pending ); - + import fpu_types::*; + `UNUSED_PARAM (CORE_ID) localparam FPUQ_BITS = `LOG2UP(`FPUQ_SIZE); @@ -65,7 +62,7 @@ module VX_fpu_unit #( // resolve dynamic FRM from CSR assign fpu_to_csr_if.read_wid = fpu_req_if.wid; - wire [`FRM_BITS-1:0] fpu_frm = (fpu_req_if.op_mod == `FRM_DYN) ? fpu_to_csr_if.read_frm : fpu_req_if.op_mod; + wire [`INST_FRM_BITS-1:0] fpu_frm = (fpu_req_if.op_mod == `INST_FRM_DYN) ? fpu_to_csr_if.read_frm : fpu_req_if.op_mod; `ifdef FPU_DPI @@ -183,7 +180,7 @@ module VX_fpu_unit #( wire stall_out = ~fpu_commit_if.ready && fpu_commit_if.valid; VX_pipe_register #( - .DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + `FFG_BITS), + .DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + `FFLAGS_BITS), .RESETW (1) ) pipe_reg ( .clk (clk), diff --git a/hw/rtl/VX_gpr_ram_f.v b/hw/rtl/VX_gpr_ram_f.v deleted file mode 100644 index 68c2a69f..00000000 --- a/hw/rtl/VX_gpr_ram_f.v +++ /dev/null @@ -1,37 +0,0 @@ -`include "VX_define.vh" - -`TRACING_OFF - -module VX_gpr_ram_f #( - parameter DATAW = 1, - parameter DEPTH = 1, - parameter ADDRW = $clog2(DEPTH) -) ( - input wire clk, - input wire wren, - input wire [ADDRW-1:0] waddr, - input wire [DATAW-1:0] wdata, - input wire [ADDRW-1:0] raddr1, - input wire [ADDRW-1:0] raddr2, - input wire [ADDRW-1:0] raddr3, - output wire [DATAW-1:0] rdata1, - output wire [DATAW-1:0] rdata2, - output wire [DATAW-1:0] rdata3 -); - reg [DATAW-1:0] mem [DEPTH-1:0]; - - initial mem = '{default: 0}; - - always @(posedge clk) begin - if (wren) begin - mem [waddr] <= wdata; - end - end - - assign rdata1 = mem [raddr1]; - assign rdata2 = mem [raddr2]; - assign rdata3 = mem [raddr3]; - -endmodule - -`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/VX_gpr_ram_i.v b/hw/rtl/VX_gpr_ram_i.v deleted file mode 100644 index 6c96b871..00000000 --- a/hw/rtl/VX_gpr_ram_i.v +++ /dev/null @@ -1,34 +0,0 @@ -`include "VX_define.vh" - -`TRACING_OFF - -module VX_gpr_ram_i #( - parameter DATAW = 1, - parameter DEPTH = 1, - parameter ADDRW = $clog2(DEPTH) -) ( - input wire clk, - input wire wren, - input wire [ADDRW-1:0] waddr, - input wire [DATAW-1:0] wdata, - input wire [ADDRW-1:0] raddr1, - input wire [ADDRW-1:0] raddr2, - output wire [DATAW-1:0] rdata1, - output wire [DATAW-1:0] rdata2 -); - reg [DATAW-1:0] mem [DEPTH-1:0]; - - initial mem = '{default: 0}; - - always @(posedge clk) begin - if (wren) begin - mem [waddr] <= wdata; - end - end - - assign rdata1 = mem [raddr1]; - assign rdata2 = mem [raddr2]; - -endmodule - -`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/VX_gpr_stage.sv b/hw/rtl/VX_gpr_stage.sv new file mode 100644 index 00000000..05fc6248 --- /dev/null +++ b/hw/rtl/VX_gpr_stage.sv @@ -0,0 +1,91 @@ +`include "VX_define.vh" + +module VX_gpr_stage #( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, + + // inputs + VX_writeback_if.slave writeback_if, + VX_gpr_req_if.slave gpr_req_if, + + // outputs + VX_gpr_rsp_if.master gpr_rsp_if +); + + `UNUSED_PARAM (CORE_ID) + `UNUSED_VAR (reset) + + localparam RAM_SIZE = `NUM_WARPS * `NUM_REGS; + + // ensure r0 never gets written, which can happen before the reset + wire write_enable = writeback_if.valid && (writeback_if.rd != 0); + + wire [`NUM_THREADS-1:0] wren; + for (genvar i = 0; i < `NUM_THREADS; ++i) begin + assign wren[i] = write_enable && writeback_if.tmask[i]; + end + + wire [$clog2(RAM_SIZE)-1:0] waddr, raddr1, raddr2; + assign waddr = {writeback_if.wid, writeback_if.rd}; + assign raddr1 = {gpr_req_if.wid, gpr_req_if.rs1}; + assign raddr2 = {gpr_req_if.wid, gpr_req_if.rs2}; + + for (genvar i = 0; i < `NUM_THREADS; ++i) begin + VX_dp_ram #( + .DATAW (32), + .SIZE (RAM_SIZE), + .INIT_ENABLE (1), + .INIT_VALUE (0) + ) dp_ram1 ( + .clk (clk), + .wren (wren[i]), + .waddr (waddr), + .wdata (writeback_if.data[i]), + .raddr (raddr1), + .rdata (gpr_rsp_if.rs1_data[i]) + ); + + VX_dp_ram #( + .DATAW (32), + .SIZE (RAM_SIZE), + .INIT_ENABLE (1), + .INIT_VALUE (0) + ) dp_ram2 ( + .clk (clk), + .wren (wren[i]), + .waddr (waddr), + .wdata (writeback_if.data[i]), + .raddr (raddr2), + .rdata (gpr_rsp_if.rs2_data[i]) + ); + end + +`ifdef EXT_F_ENABLE + wire [$clog2(RAM_SIZE)-1:0] raddr3; + assign raddr3 = {gpr_req_if.wid, gpr_req_if.rs3}; + + for (genvar i = 0; i < `NUM_THREADS; ++i) begin + VX_dp_ram #( + .DATAW (32), + .SIZE (RAM_SIZE), + .INIT_ENABLE (1), + .INIT_VALUE (0) + ) dp_ram3 ( + .clk (clk), + .wren (wren[i]), + .waddr (waddr), + .wdata (writeback_if.data[i]), + .raddr (raddr3), + .rdata (gpr_rsp_if.rs3_data[i]) + ); + end +`else + `UNUSED_VAR (gpr_req_if.rs3) + assign gpr_rsp_if.rs3_data = 'x; +`endif + + assign writeback_if.ready = 1'b1; + +endmodule \ No newline at end of file diff --git a/hw/rtl/VX_gpr_stage.v b/hw/rtl/VX_gpr_stage.v deleted file mode 100644 index 9367dd75..00000000 --- a/hw/rtl/VX_gpr_stage.v +++ /dev/null @@ -1,87 +0,0 @@ -`include "VX_define.vh" - -module VX_gpr_stage #( - parameter CORE_ID = 0 -) ( - input wire clk, - input wire reset, - - // inputs - VX_writeback_if writeback_if, - VX_gpr_req_if gpr_req_if, - - // outputs - VX_gpr_rsp_if gpr_rsp_if -); - - `UNUSED_PARAM (CORE_ID) - `UNUSED_VAR (reset) - - // ensure r0 never gets written, which can happen before the reset - wire write_enable = writeback_if.valid && (writeback_if.rd != 0); - -`ifdef EXT_F_ENABLE - localparam RAM_DEPTH = `NUM_WARPS * `NUM_REGS; - wire [`NUM_THREADS-1:0][31:0] rdata1, rdata2, rdata3; - wire [$clog2(RAM_DEPTH)-1:0] waddr, raddr1, raddr2, raddr3; - - assign waddr = {writeback_if.wid, writeback_if.rd}; - assign raddr1 = {gpr_req_if.wid, gpr_req_if.rs1}; - assign raddr2 = {gpr_req_if.wid, gpr_req_if.rs2}; - assign raddr3 = {gpr_req_if.wid, gpr_req_if.rs3}; - - for (genvar i = 0; i < `NUM_THREADS; i++) begin - VX_gpr_ram_f #( - .DATAW (32), - .DEPTH (RAM_DEPTH) - ) gpr_ram_f ( - .clk (clk), - .wren (write_enable && writeback_if.tmask[i]), - .waddr (waddr), - .wdata (writeback_if.data[i]), - .raddr1 (raddr1), - .raddr2 (raddr2), - .raddr3 (raddr3), - .rdata1 (rdata1[i]), - .rdata2 (rdata2[i]), - .rdata3 (rdata3[i]) - ); - end - - assign gpr_rsp_if.rs1_data = rdata1; - assign gpr_rsp_if.rs2_data = rdata2; - assign gpr_rsp_if.rs3_data = rdata3; -`else - localparam RAM_DEPTH = `NUM_WARPS * `NUM_REGS; - wire [`NUM_THREADS-1:0][31:0] rdata1, rdata2; - wire [$clog2(RAM_DEPTH)-1:0] waddr, raddr1, raddr2; - - assign waddr = {writeback_if.wid, writeback_if.rd}; - assign raddr1 = {gpr_req_if.wid, gpr_req_if.rs1}; - assign raddr2 = {gpr_req_if.wid, gpr_req_if.rs2}; - `UNUSED_VAR (gpr_req_if.rs3) - - for (genvar i = 0; i < `NUM_THREADS; i++) begin - VX_gpr_ram_i #( - .DATAW (32), - .DEPTH (RAM_DEPTH) - ) gpr_ram_i ( - .clk (clk), - .wren (write_enable && writeback_if.tmask[i]), - .waddr (waddr), - .wdata (writeback_if.data[i]), - .raddr1 (raddr1), - .raddr2 (raddr2), - .rdata1 (rdata1[i]), - .rdata2 (rdata2[i]) - ); - end - - assign gpr_rsp_if.rs1_data = rdata1; - assign gpr_rsp_if.rs2_data = rdata2; - assign gpr_rsp_if.rs3_data = 0; -`endif - - assign writeback_if.ready = 1'b1; - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_gpu_types.vh b/hw/rtl/VX_gpu_types.vh new file mode 100644 index 00000000..857f2efc --- /dev/null +++ b/hw/rtl/VX_gpu_types.vh @@ -0,0 +1,43 @@ +`ifndef VX_GPU_TYPES +`define VX_GPU_TYPES + +`include "VX_define.vh" + +package gpu_types; + +typedef struct packed { + logic valid; + logic [`NUM_THREADS-1:0] tmask; +} gpu_tmc_t; + +`define GPU_TMC_BITS $bits(gpu_types::gpu_tmc_t) + +typedef struct packed { + logic valid; + logic [`NUM_WARPS-1:0] wmask; + logic [31:0] pc; +} gpu_wspawn_t; + +`define GPU_WSPAWN_BITS $bits(gpu_types::gpu_wspawn_t) + +typedef struct packed { + logic valid; + logic diverged; + logic [`NUM_THREADS-1:0] then_tmask; + logic [`NUM_THREADS-1:0] else_tmask; + logic [31:0] pc; +} gpu_split_t; + +`define GPU_SPLIT_BITS $bits(gpu_types::gpu_split_t) + +typedef struct packed { + logic valid; + logic [`NB_BITS-1:0] id; + logic [`NW_BITS-1:0] size_m1; +} gpu_barrier_t; + +`define GPU_BARRIER_BITS $bits(gpu_types::gpu_barrier_t) + +endpackage + +`endif \ No newline at end of file diff --git a/hw/rtl/VX_gpu_unit.v b/hw/rtl/VX_gpu_unit.sv similarity index 78% rename from hw/rtl/VX_gpu_unit.v rename to hw/rtl/VX_gpu_unit.sv index 658ba338..b632e722 100644 --- a/hw/rtl/VX_gpu_unit.v +++ b/hw/rtl/VX_gpu_unit.sv @@ -5,11 +5,11 @@ module VX_gpu_unit #( ) ( `SCOPE_IO_VX_gpu_unit - input wire clk, - input wire reset, + input wire clk, + input wire reset, // Inputs - VX_gpu_req_if gpu_req_if, + VX_gpu_req_if.slave gpu_req_if, `ifdef EXT_TEX_ENABLE VX_tex_csr_if tex_csr_if, @@ -19,9 +19,10 @@ module VX_gpu_unit #( `endif // Outputs - VX_warp_ctl_if warp_ctl_if, - VX_commit_if gpu_commit_if + VX_warp_ctl_if.master warp_ctl_if, + VX_commit_if.master gpu_commit_if ); + import gpu_types::*; `UNUSED_PARAM (CORE_ID) @@ -47,26 +48,32 @@ module VX_gpu_unit #( wire stall_in, stall_out; - wire is_wspawn = (gpu_req_if.op_type == `GPU_WSPAWN); - wire is_tmc = (gpu_req_if.op_type == `GPU_TMC); - wire is_split = (gpu_req_if.op_type == `GPU_SPLIT); - wire is_bar = (gpu_req_if.op_type == `GPU_BAR); + wire is_wspawn = (gpu_req_if.op_type == `INST_GPU_WSPAWN); + wire is_tmc = (gpu_req_if.op_type == `INST_GPU_TMC); + wire is_split = (gpu_req_if.op_type == `INST_GPU_SPLIT); + wire is_bar = (gpu_req_if.op_type == `INST_GPU_BAR); // tmc - wire [`NUM_THREADS-1:0] tmc_new_mask; for (genvar i = 0; i < `NUM_THREADS; i++) begin - assign tmc_new_mask[i] = (i < gpu_req_if.rs1_data[0]); - end - assign tmc.valid = is_tmc; - assign tmc.tmask = tmc_new_mask; + wire taken = (gpu_req_if.rs1_data[i] != 0); + assign taken_tmask[i] = gpu_req_if.tmask[i] & taken; + assign not_taken_tmask[i] = gpu_req_if.tmask[i] & ~taken; + end + + // tmc + + wire [`NUM_THREADS-1:0] pred_mask = (taken_tmask != 0) ? taken_tmask : gpu_req_if.tmask; + + assign tmc.valid = is_tmc || is_pred; + assign tmc.tmask = is_pred ? pred_mask : rs1_data[`NUM_THREADS-1:0]; // wspawn wire [31:0] wspawn_pc = gpu_req_if.rs2_data[0]; wire [`NUM_WARPS-1:0] wspawn_wmask; for (genvar i = 0; i < `NUM_WARPS; i++) begin - assign wspawn_wmask[i] = (i < gpu_req_if.rs1_data[0]); + assign wspawn_wmask[i] = (i < rs1_data); end assign wspawn.valid = is_wspawn; assign wspawn.wmask = wspawn_wmask; @@ -74,20 +81,11 @@ module VX_gpu_unit #( // split - wire [`NUM_THREADS-1:0] split_then_mask; - wire [`NUM_THREADS-1:0] split_else_mask; - - for (genvar i = 0; i < `NUM_THREADS; i++) begin - wire taken = gpu_req_if.rs1_data[i][0]; - assign split_then_mask[i] = gpu_req_if.tmask[i] & taken; - assign split_else_mask[i] = gpu_req_if.tmask[i] & ~taken; - end - - assign split.valid = is_split; - assign split.diverged = (| split_then_mask) && (| split_else_mask); - assign split.then_mask = split_then_mask; - assign split.else_mask = split_else_mask; - assign split.pc = gpu_req_if.next_PC; + assign split.valid = is_split; + assign split.diverged = (| taken_tmask) && (| not_taken_tmask); + assign split.then_tmask = taken_tmask; + assign split.else_tmask = not_taken_tmask; + assign split.pc = gpu_req_if.next_PC; // barrier @@ -200,9 +198,9 @@ module VX_gpu_unit #( `SCOPE_ASSIGN (gpu_rsp_valid, warp_ctl_if.valid); `SCOPE_ASSIGN (gpu_rsp_wid, warp_ctl_if.wid); - `SCOPE_ASSIGN (gpu_rsp_tmc, warp_ctl_if.tmc); - `SCOPE_ASSIGN (gpu_rsp_wspawn, warp_ctl_if.wspawn); - `SCOPE_ASSIGN (gpu_rsp_split, warp_ctl_if.split); - `SCOPE_ASSIGN (gpu_rsp_barrier, warp_ctl_if.barrier); + `SCOPE_ASSIGN (gpu_rsp_tmc, warp_ctl_if.tmc.valid); + `SCOPE_ASSIGN (gpu_rsp_wspawn, warp_ctl_if.wspawn.valid); + `SCOPE_ASSIGN (gpu_rsp_split, warp_ctl_if.split.valid); + `SCOPE_ASSIGN (gpu_rsp_barrier, warp_ctl_if.barrier.valid); endmodule \ No newline at end of file diff --git a/hw/rtl/VX_ibuffer.v b/hw/rtl/VX_ibuffer.sv similarity index 78% rename from hw/rtl/VX_ibuffer.v rename to hw/rtl/VX_ibuffer.sv index 80a33032..9b9fd397 100644 --- a/hw/rtl/VX_ibuffer.v +++ b/hw/rtl/VX_ibuffer.sv @@ -7,17 +7,16 @@ module VX_ibuffer #( input wire reset, // inputs - VX_decode_if decode_if, + VX_decode_if.slave decode_if, // outputs - VX_ibuffer_if ibuffer_if + VX_ibuffer_if.master ibuffer_if ); `UNUSED_PARAM (CORE_ID) - localparam DATAW = `NUM_THREADS + 32 + `EX_BITS + `OP_BITS + `FRM_BITS + 1 + (`NR_BITS * 4) + 32 + 1 + 1 + `NUM_REGS; - localparam SIZE = 3; - localparam ADDRW = $clog2(SIZE); + localparam DATAW = `NUM_THREADS + 32 + `EX_BITS + `INST_OP_BITS + `INST_FRM_BITS + 1 + (`NR_BITS * 4) + 32 + 1 + 1; + localparam ADDRW = $clog2(`IBUF_SIZE+1); localparam NWARPSW = $clog2(`NUM_WARPS+1); reg [`NUM_WARPS-1:0][ADDRW-1:0] used_r; @@ -36,14 +35,16 @@ module VX_ibuffer #( wire writing = enq_fire && (i == decode_if.wid); wire reading = deq_fire && (i == ibuffer_if.wid); - wire is_head_ptr = empty_r[i] || (alm_empty_r[i] && reading); + wire going_empty = empty_r[i] || (alm_empty_r[i] && reading); - VX_skid_buffer #( - .DATAW (DATAW) + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (`IBUF_SIZE), + .OUT_REG (1) ) queue ( .clk (clk), .reset (reset), - .valid_in (writing && !is_head_ptr), + .valid_in (writing && !going_empty), .data_in (q_data_in), .ready_out(reading), .data_out (q_data_prev[i]), @@ -63,7 +64,7 @@ module VX_ibuffer #( empty_r[i] <= 0; if (used_r[i] == 1) alm_empty_r[i] <= 0; - if (used_r[i] == ADDRW'(SIZE-1)) + if (used_r[i] == ADDRW'(`IBUF_SIZE)) full_r[i] <= 1; end end else if (reading) begin @@ -76,7 +77,7 @@ module VX_ibuffer #( used_r[i] <= used_r[i] + ADDRW'($signed(2'(writing) - 2'(reading))); end - if (writing && is_head_ptr) begin + if (writing && going_empty) begin q_data_out[i] <= q_data_in; end else if (reading) begin q_data_out[i] <= q_data_prev[i]; @@ -97,6 +98,8 @@ module VX_ibuffer #( reg [DATAW-1:0] deq_instr, deq_instr_n; reg [NWARPSW-1:0] num_warps; + `UNUSED_VAR (deq_instr) + // calculate valid table always @(*) begin valid_table_n = valid_table; @@ -114,11 +117,11 @@ module VX_ibuffer #( ) rr_arbiter ( .clk (clk), .reset (reset), - .enable (ibuffer_if.ready), .requests (valid_table_n), .grant_index (deq_wid_rr_n), - `UNUSED_PIN (grant_onehot), - `UNUSED_PIN (grant_valid) + `UNUSED_PIN (grant_valid), + `UNUSED_PIN (grant_onehot), + `UNUSED_PIN (enable) ); // schedule the next instruction to issue @@ -146,11 +149,10 @@ module VX_ibuffer #( valid_table <= 0; deq_valid <= 0; num_warps <= 0; - deq_wid_rr <= 0; end else begin valid_table <= valid_table_n; deq_valid <= deq_valid_n; - deq_wid_rr <= deq_wid_rr_n; + if (warp_added && !warp_removed) begin num_warps <= num_warps + NWARPSW'(1); @@ -159,42 +161,48 @@ module VX_ibuffer #( end end - deq_wid <= deq_wid_n; - deq_instr <= deq_instr_n; + deq_wid <= deq_wid_n; + deq_wid_rr <= deq_wid_rr_n; + deq_instr <= deq_instr_n; end assign decode_if.ready = ~q_full[decode_if.wid]; + assign q_data_in = {decode_if.tmask, decode_if.PC, decode_if.ex_type, decode_if.op_type, decode_if.op_mod, - decode_if.wb, + decode_if.wb, + decode_if.use_PC, + decode_if.use_imm, + decode_if.imm, decode_if.rd, decode_if.rs1, decode_if.rs2, - decode_if.rs3, - decode_if.imm, - decode_if.use_PC, - decode_if.use_imm, - decode_if.used_regs}; + decode_if.rs3}; assign ibuffer_if.valid = deq_valid; assign ibuffer_if.wid = deq_wid; - assign ibuffer_if.wid_n = deq_wid_n; assign {ibuffer_if.tmask, ibuffer_if.PC, ibuffer_if.ex_type, ibuffer_if.op_type, ibuffer_if.op_mod, - ibuffer_if.wb, + ibuffer_if.wb, + ibuffer_if.use_PC, + ibuffer_if.use_imm, + ibuffer_if.imm, ibuffer_if.rd, ibuffer_if.rs1, ibuffer_if.rs2, - ibuffer_if.rs3, - ibuffer_if.imm, - ibuffer_if.use_PC, - ibuffer_if.use_imm, - ibuffer_if.used_regs} = deq_instr; + ibuffer_if.rs3} = deq_instr; + + // scoreboard forwarding + assign ibuffer_if.wid_n = deq_wid_n; + assign ibuffer_if.rd_n = deq_instr_n[3*`NR_BITS +: `NR_BITS]; + assign ibuffer_if.rs1_n = deq_instr_n[2*`NR_BITS +: `NR_BITS]; + assign ibuffer_if.rs2_n = deq_instr_n[1*`NR_BITS +: `NR_BITS]; + assign ibuffer_if.rs3_n = deq_instr_n[0*`NR_BITS +: `NR_BITS]; endmodule \ No newline at end of file diff --git a/hw/rtl/VX_icache_stage.v b/hw/rtl/VX_icache_stage.sv similarity index 65% rename from hw/rtl/VX_icache_stage.v rename to hw/rtl/VX_icache_stage.sv index 537d759a..96ab2531 100644 --- a/hw/rtl/VX_icache_stage.v +++ b/hw/rtl/VX_icache_stage.sv @@ -5,24 +5,24 @@ module VX_icache_stage #( ) ( `SCOPE_IO_VX_icache_stage - input wire clk, - input wire reset, + input wire clk, + input wire reset, // Icache interface - VX_icache_req_if icache_req_if, - VX_icache_rsp_if icache_rsp_if, + VX_icache_req_if.master icache_req_if, + VX_icache_rsp_if.slave icache_rsp_if, // request - VX_ifetch_req_if ifetch_req_if, + VX_ifetch_req_if.slave ifetch_req_if, // reponse - VX_ifetch_rsp_if ifetch_rsp_if + VX_ifetch_rsp_if.master ifetch_rsp_if ); `UNUSED_PARAM (CORE_ID) `UNUSED_VAR (reset) - localparam OUTPUT_REG = 0; + localparam OUT_REG = 0; wire icache_req_fire = icache_req_if.valid && icache_req_if.ready; @@ -33,20 +33,21 @@ module VX_icache_stage #( wire [`NUM_THREADS-1:0] rsp_tmask; VX_dp_ram #( - .DATAW(32 + `NUM_THREADS), - .SIZE(`NUM_WARPS), - .FASTRAM(1) + .DATAW (32 + `NUM_THREADS), + .SIZE (`NUM_WARPS), + .LUTRAM (1) ) req_metadata ( - .clk(clk), - .waddr(req_tag), - .raddr(rsp_tag), - .wren(icache_req_fire), - .byteen(1'b1), - .rden(ifetch_rsp_if.valid), - .din({ifetch_req_if.PC, ifetch_req_if.tmask}), - .dout({rsp_PC, rsp_tmask}) + .clk (clk), + .wren (icache_req_fire), + .waddr (req_tag), + .wdata ({ifetch_req_if.PC, ifetch_req_if.tmask}), + .raddr (rsp_tag), + .rdata ({rsp_PC, rsp_tmask}) ); + `RUNTIME_ASSERT((!ifetch_req_if.valid || ifetch_req_if.PC >= `STARTUP_ADDR), + ("invalid PC=%0h, wid=%0d, tmask=%b", ifetch_req_if.PC, ifetch_req_if.wid, ifetch_req_if.tmask)) + // Icache Request assign icache_req_if.valid = ifetch_req_if.valid; assign icache_req_if.addr = ifetch_req_if.PC[31:2]; @@ -62,12 +63,12 @@ module VX_icache_stage #( wire [`NW_BITS-1:0] rsp_wid = rsp_tag; - wire stall_out = ~ifetch_rsp_if.ready && (0 == OUTPUT_REG && ifetch_rsp_if.valid); + wire stall_out = ~ifetch_rsp_if.ready && (0 == OUT_REG && ifetch_rsp_if.valid); VX_pipe_register #( .DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + 32), .RESETW (1), - .DEPTH (OUTPUT_REG) + .DEPTH (OUT_REG) ) pipe_reg ( .clk (clk), .reset (reset), @@ -90,10 +91,10 @@ module VX_icache_stage #( `ifdef DBG_PRINT_CORE_ICACHE always @(posedge clk) begin if (icache_req_if.valid && icache_req_if.ready) begin - $display("%t: I$%0d req: wid=%0d, PC=%0h", $time, CORE_ID, ifetch_req_if.wid, ifetch_req_if.PC); + dpi_trace("%d: I$%0d req: wid=%0d, PC=%0h\n", $time, CORE_ID, ifetch_req_if.wid, ifetch_req_if.PC); end if (ifetch_rsp_if.valid && ifetch_rsp_if.ready) begin - $display("%t: I$%0d rsp: wid=%0d, PC=%0h, data=%0h", $time, CORE_ID, ifetch_rsp_if.wid, ifetch_rsp_if.PC, ifetch_rsp_if.data); + dpi_trace("%d: I$%0d rsp: wid=%0d, PC=%0h, data=%0h\n", $time, CORE_ID, ifetch_rsp_if.wid, ifetch_rsp_if.PC, ifetch_rsp_if.data); end end `endif diff --git a/hw/rtl/VX_instr_demux.sv b/hw/rtl/VX_instr_demux.sv new file mode 100644 index 00000000..b761e9d9 --- /dev/null +++ b/hw/rtl/VX_instr_demux.sv @@ -0,0 +1,159 @@ +`include "VX_define.vh" + +module VX_instr_demux ( + input wire clk, + input wire reset, + + // inputs + VX_ibuffer_if.slave ibuffer_if, + VX_gpr_rsp_if.slave gpr_rsp_if, + + // outputs + VX_alu_req_if.master alu_req_if, + VX_lsu_req_if.master lsu_req_if, + VX_csr_req_if.master csr_req_if, +`ifdef EXT_F_ENABLE + VX_fpu_req_if.master fpu_req_if, +`endif + VX_gpu_req_if.master gpu_req_if +); + wire [`NT_BITS-1:0] tid; + wire alu_req_ready; + wire lsu_req_ready; + wire csr_req_ready; +`ifdef EXT_F_ENABLE + wire fpu_req_ready; +`endif + wire gpu_req_ready; + + VX_lzc #( + .N (`NUM_THREADS) + ) tid_select ( + .in_i (ibuffer_if.tmask), + .cnt_o (tid), + `UNUSED_PIN (valid_o) + ); + + wire [31:0] next_PC = ibuffer_if.PC + 4; + + // ALU unit + + wire alu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_ALU); + wire [`INST_ALU_BITS-1:0] alu_op_type = `INST_ALU_BITS'(ibuffer_if.op_type); + + VX_skid_buffer #( + .DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `INST_ALU_BITS + `INST_MOD_BITS + 32 + 1 + 1 + `NR_BITS + 1 + `NT_BITS + (2 * `NUM_THREADS * 32)), + .OUT_REG (1) + ) alu_buffer ( + .clk (clk), + .reset (reset), + .valid_in (alu_req_valid), + .ready_in (alu_req_ready), + .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, next_PC, alu_op_type, ibuffer_if.op_mod, ibuffer_if.imm, ibuffer_if.use_PC, ibuffer_if.use_imm, ibuffer_if.rd, ibuffer_if.wb, tid, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}), + .data_out ({alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.next_PC, alu_req_if.op_type, alu_req_if.op_mod, alu_req_if.imm, alu_req_if.use_PC, alu_req_if.use_imm, alu_req_if.rd, alu_req_if.wb, alu_req_if.tid, alu_req_if.rs1_data, alu_req_if.rs2_data}), + .valid_out (alu_req_if.valid), + .ready_out (alu_req_if.ready) + ); + + // lsu unit + + wire lsu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_LSU); + wire [`INST_LSU_BITS-1:0] lsu_op_type = `INST_LSU_BITS'(ibuffer_if.op_type); + wire lsu_is_fence = `INST_LSU_IS_FENCE(ibuffer_if.op_mod); + + VX_skid_buffer #( + .DATAW (`NW_BITS + `NUM_THREADS + 32 + `INST_LSU_BITS + 1 + 32 + `NR_BITS + 1 + (2 * `NUM_THREADS * 32)), + .OUT_REG (1) + ) lsu_buffer ( + .clk (clk), + .reset (reset), + .valid_in (lsu_req_valid), + .ready_in (lsu_req_ready), + .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, lsu_op_type, lsu_is_fence, ibuffer_if.imm, ibuffer_if.rd, ibuffer_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}), + .data_out ({lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.op_type, lsu_req_if.is_fence, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.base_addr, lsu_req_if.store_data}), + .valid_out (lsu_req_if.valid), + .ready_out (lsu_req_if.ready) + ); + + // csr unit + + wire csr_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_CSR); + wire [`INST_CSR_BITS-1:0] csr_op_type = `INST_CSR_BITS'(ibuffer_if.op_type); + wire [`CSR_ADDR_BITS-1:0] csr_addr = ibuffer_if.imm[`CSR_ADDR_BITS-1:0]; + wire [`NRI_BITS-1:0] csr_imm = ibuffer_if.imm[`CSR_ADDR_BITS +: `NRI_BITS]; + wire [31:0] csr_rs1_data = gpr_rsp_if.rs1_data[tid]; + + VX_skid_buffer #( + .DATAW (`NW_BITS + `NUM_THREADS + 32 + `INST_CSR_BITS + `CSR_ADDR_BITS + `NR_BITS + 1 + 1 + `NRI_BITS + 32), + .OUT_REG (1) + ) csr_buffer ( + .clk (clk), + .reset (reset), + .valid_in (csr_req_valid), + .ready_in (csr_req_ready), + .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, csr_op_type, csr_addr, ibuffer_if.rd, ibuffer_if.wb, ibuffer_if.use_imm, csr_imm, csr_rs1_data}), + .data_out ({csr_req_if.wid, csr_req_if.tmask, csr_req_if.PC, csr_req_if.op_type, csr_req_if.addr, csr_req_if.rd, csr_req_if.wb, csr_req_if.use_imm, csr_req_if.imm, csr_req_if.rs1_data}), + .valid_out (csr_req_if.valid), + .ready_out (csr_req_if.ready) + ); + + // fpu unit + +`ifdef EXT_F_ENABLE + wire fpu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_FPU); + wire [`INST_FPU_BITS-1:0] fpu_op_type = `INST_FPU_BITS'(ibuffer_if.op_type); + + VX_skid_buffer #( + .DATAW (`NW_BITS + `NUM_THREADS + 32 + `INST_FPU_BITS + `INST_MOD_BITS + `NR_BITS + 1 + (3 * `NUM_THREADS * 32)), + .OUT_REG (1) + ) fpu_buffer ( + .clk (clk), + .reset (reset), + .valid_in (fpu_req_valid), + .ready_in (fpu_req_ready), + .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, fpu_op_type, ibuffer_if.op_mod, ibuffer_if.rd, ibuffer_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data, gpr_rsp_if.rs3_data}), + .data_out ({fpu_req_if.wid, fpu_req_if.tmask, fpu_req_if.PC, fpu_req_if.op_type, fpu_req_if.op_mod, fpu_req_if.rd, fpu_req_if.wb, fpu_req_if.rs1_data, fpu_req_if.rs2_data, fpu_req_if.rs3_data}), + .valid_out (fpu_req_if.valid), + .ready_out (fpu_req_if.ready) + ); +`else + `UNUSED_VAR (gpr_rsp_if.rs3_data) +`endif + + // gpu unit + + wire gpu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_GPU); + wire [`INST_GPU_BITS-1:0] gpu_op_type = `INST_GPU_BITS'(ibuffer_if.op_type); + wire [31:0] gpu_rs2_data = gpr_rsp_if.rs2_data[tid]; + + VX_skid_buffer #( + .DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `INST_GPU_BITS + `NR_BITS + 1 + + `NT_BITS + (`NUM_THREADS * 32 + 32)), + .OUT_REG (1) + ) gpu_buffer ( + .clk (clk), + .reset (reset), + .valid_in (gpu_req_valid), + .ready_in (gpu_req_ready), + .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, next_PC, gpu_op_type, ibuffer_if.rd, ibuffer_if.wb, tid, gpr_rsp_if.rs1_data, gpu_rs2_data}), + .data_out ({gpu_req_if.wid, gpu_req_if.tmask, gpu_req_if.PC, gpu_req_if.next_PC, gpu_req_if.op_type, gpu_req_if.rd, gpu_req_if.wb, gpu_req_if.tid, gpu_req_if.rs1_data, gpu_req_if.rs2_data}), + .valid_out (gpu_req_if.valid), + .ready_out (gpu_req_if.ready) + ); + + // can take next request? + reg ready_r; + always @(*) begin + case (ibuffer_if.ex_type) + `EX_ALU: ready_r = alu_req_ready; + `EX_LSU: ready_r = lsu_req_ready; + `EX_CSR: ready_r = csr_req_ready; + `ifdef EXT_F_ENABLE + `EX_FPU: ready_r = fpu_req_ready; + `endif + `EX_GPU: ready_r = gpu_req_ready; + default: ready_r = 1'b1; // ignore NOPs + endcase + end + assign ibuffer_if.ready = ready_r; + +endmodule \ No newline at end of file diff --git a/hw/rtl/VX_instr_demux.v b/hw/rtl/VX_instr_demux.v deleted file mode 100644 index 45ddee81..00000000 --- a/hw/rtl/VX_instr_demux.v +++ /dev/null @@ -1,146 +0,0 @@ -`include "VX_define.vh" - -module VX_instr_demux ( - input wire clk, - input wire reset, - - // inputs - VX_ibuffer_if ibuffer_if, - VX_gpr_rsp_if gpr_rsp_if, - - // outputs - VX_alu_req_if alu_req_if, - VX_lsu_req_if lsu_req_if, - VX_csr_req_if csr_req_if, - VX_fpu_req_if fpu_req_if, - VX_gpu_req_if gpu_req_if -); - wire [`NT_BITS-1:0] tid; - wire alu_req_ready; - wire lsu_req_ready; - wire csr_req_ready; - wire fpu_req_ready; - wire gpu_req_ready; - - VX_priority_encoder #( - .N (`NUM_THREADS) - ) tid_select ( - .data_in (ibuffer_if.tmask), - .index (tid), - `UNUSED_PIN (onehot), - `UNUSED_PIN (valid_out) - ); - - wire [31:0] next_PC = ibuffer_if.PC + 4; - - // ALU unit - - wire alu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_ALU); - - VX_skid_buffer #( - .DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `ALU_BITS + `MOD_BITS + 32 + 1 + 1 + `NR_BITS + 1 + `NT_BITS + (2 * `NUM_THREADS * 32)), - .OUTPUT_REG (1) - ) alu_buffer ( - .clk (clk), - .reset (reset), - .valid_in (alu_req_valid), - .ready_in (alu_req_ready), - .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, next_PC, `ALU_OP(ibuffer_if.op_type), ibuffer_if.op_mod, ibuffer_if.imm, ibuffer_if.use_PC, ibuffer_if.use_imm, ibuffer_if.rd, ibuffer_if.wb, tid, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}), - .data_out ({alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.next_PC, alu_req_if.op_type, alu_req_if.op_mod, alu_req_if.imm, alu_req_if.use_PC, alu_req_if.use_imm, alu_req_if.rd, alu_req_if.wb, alu_req_if.tid, alu_req_if.rs1_data, alu_req_if.rs2_data}), - .valid_out (alu_req_if.valid), - .ready_out (alu_req_if.ready) - ); - - // lsu unit - - wire lsu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_LSU); - wire lsu_is_fence = `LSU_IS_FENCE(ibuffer_if.op_mod); - - VX_skid_buffer #( - .DATAW (`NW_BITS + `NUM_THREADS + 32 + `LSU_BITS + 1 + 32 + `NR_BITS + 1 + (2 * `NUM_THREADS * 32)), - .OUTPUT_REG (1) - ) lsu_buffer ( - .clk (clk), - .reset (reset), - .valid_in (lsu_req_valid), - .ready_in (lsu_req_ready), - .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, `LSU_OP(ibuffer_if.op_type), lsu_is_fence, ibuffer_if.imm, ibuffer_if.rd, ibuffer_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}), - .data_out ({lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.op_type, lsu_req_if.is_fence, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.base_addr, lsu_req_if.store_data}), - .valid_out (lsu_req_if.valid), - .ready_out (lsu_req_if.ready) - ); - - // csr unit - - wire csr_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_CSR); - - VX_skid_buffer #( - .DATAW (`NW_BITS + `NUM_THREADS + 32 + `CSR_BITS + `CSR_ADDR_BITS + `NR_BITS + 1 + 1 + `NR_BITS + 32), - .OUTPUT_REG (1) - ) csr_buffer ( - .clk (clk), - .reset (reset), - .valid_in (csr_req_valid), - .ready_in (csr_req_ready), - .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, `CSR_OP(ibuffer_if.op_type), ibuffer_if.imm[`CSR_ADDR_BITS-1:0], ibuffer_if.rd, ibuffer_if.wb, ibuffer_if.use_imm, ibuffer_if.rs1, gpr_rsp_if.rs1_data[0]}), - .data_out ({csr_req_if.wid, csr_req_if.tmask, csr_req_if.PC, csr_req_if.op_type, csr_req_if.addr, csr_req_if.rd, csr_req_if.wb, csr_req_if.use_imm, csr_req_if.rs1, csr_req_if.rs1_data}), - .valid_out (csr_req_if.valid), - .ready_out (csr_req_if.ready) - ); - - // fpu unit - -`ifdef EXT_F_ENABLE - wire fpu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_FPU); - - VX_skid_buffer #( - .DATAW (`NW_BITS + `NUM_THREADS + 32 + `FPU_BITS + `MOD_BITS + `NR_BITS + 1 + (3 * `NUM_THREADS * 32)), - .OUTPUT_REG (1) - ) fpu_buffer ( - .clk (clk), - .reset (reset), - .valid_in (fpu_req_valid), - .ready_in (fpu_req_ready), - .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, `FPU_OP(ibuffer_if.op_type), ibuffer_if.op_mod, ibuffer_if.rd, ibuffer_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data, gpr_rsp_if.rs3_data}), - .data_out ({fpu_req_if.wid, fpu_req_if.tmask, fpu_req_if.PC, fpu_req_if.op_type, fpu_req_if.op_mod, fpu_req_if.rd, fpu_req_if.wb, fpu_req_if.rs1_data, fpu_req_if.rs2_data, fpu_req_if.rs3_data}), - .valid_out (fpu_req_if.valid), - .ready_out (fpu_req_if.ready) - ); -`else - `UNUSED_VAR (gpr_rsp_if.rs3_data) - assign fpu_req_ready = 0; -`endif - - // gpu unit - - wire gpu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_GPU); - - VX_skid_buffer #( - .DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `GPU_BITS + `MOD_BITS + `NR_BITS + 1 + (3 * `NUM_THREADS * 32)), - .OUTPUT_REG (1) - ) gpu_buffer ( - .clk (clk), - .reset (reset), - .valid_in (gpu_req_valid), - .ready_in (gpu_req_ready), - .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, next_PC, `GPU_OP(ibuffer_if.op_type), ibuffer_if.op_mod, ibuffer_if.rd, ibuffer_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data, gpr_rsp_if.rs3_data}), - .data_out ({gpu_req_if.wid, gpu_req_if.tmask, gpu_req_if.PC, gpu_req_if.next_PC, gpu_req_if.op_type, gpu_req_if.op_mod, gpu_req_if.rd, gpu_req_if.wb, gpu_req_if.rs1_data, gpu_req_if.rs2_data, gpu_req_if.rs3_data}), - .valid_out (gpu_req_if.valid), - .ready_out (gpu_req_if.ready) - ); - - // can take next request? - reg ready_r; - always @(*) begin - case (ibuffer_if.ex_type) - `EX_ALU: ready_r = alu_req_ready; - `EX_LSU: ready_r = lsu_req_ready; - `EX_CSR: ready_r = csr_req_ready; - `EX_FPU: ready_r = fpu_req_ready; - `EX_GPU: ready_r = gpu_req_ready; - default: ready_r = 1'b1; // ignore NOPs - endcase - end - assign ibuffer_if.ready = ready_r; - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_ipdom_stack.v b/hw/rtl/VX_ipdom_stack.sv similarity index 73% rename from hw/rtl/VX_ipdom_stack.v rename to hw/rtl/VX_ipdom_stack.sv index 19608d99..2c0cc322 100644 --- a/hw/rtl/VX_ipdom_stack.v +++ b/hw/rtl/VX_ipdom_stack.sv @@ -6,11 +6,13 @@ module VX_ipdom_stack #( ) ( input wire clk, input wire reset, + input wire pair, input wire [WIDTH - 1:0] q1, input wire [WIDTH - 1:0] q2, output wire [WIDTH - 1:0] d, input wire push, input wire pop, + output wire index, output wire empty, output wire full ); @@ -38,32 +40,29 @@ module VX_ipdom_stack #( end VX_dp_ram #( - .DATAW(WIDTH * 2), - .SIZE(DEPTH), - .RWCHECK(1), - .FASTRAM(1) + .DATAW (WIDTH * 2), + .SIZE (DEPTH), + .LUTRAM (1) ) store ( - .clk(clk), - .waddr(wr_ptr), - .raddr(rd_ptr), - .wren(push), - .byteen(1'b1), - .rden(pop), - .din({q2, q1}), - .dout({d2, d1}) + .clk (clk), + .wren (push), + .waddr (wr_ptr), + .wdata ({q2, q1}), + .raddr (rd_ptr), + .rdata ({d2, d1}) ); always @(posedge clk) begin if (push) begin - is_part[wr_ptr] <= 0; + is_part[wr_ptr] <= ~pair; end else if (pop) begin is_part[rd_ptr] <= 1; end end - wire p = is_part[rd_ptr]; - assign d = p ? d1 : d2; - assign empty = ~(| wr_ptr); + assign index = is_part[rd_ptr]; + assign d = index ? d1 : d2; + assign empty = (ADDRW'(0) == wr_ptr); assign full = (ADDRW'(DEPTH-1) == wr_ptr); endmodule \ No newline at end of file diff --git a/hw/rtl/VX_issue.v b/hw/rtl/VX_issue.sv similarity index 58% rename from hw/rtl/VX_issue.v rename to hw/rtl/VX_issue.sv index 1edd07f6..04f8788b 100644 --- a/hw/rtl/VX_issue.v +++ b/hw/rtl/VX_issue.sv @@ -9,30 +9,76 @@ module VX_issue #( input wire reset, `ifdef PERF_ENABLE - VX_perf_pipeline_if perf_pipeline_if, + VX_perf_pipeline_if.master perf_pipeline_if, `endif - VX_decode_if decode_if, - VX_writeback_if writeback_if, + VX_decode_if.slave decode_if, + VX_writeback_if.slave writeback_if, - VX_alu_req_if alu_req_if, - VX_lsu_req_if lsu_req_if, - VX_csr_req_if csr_req_if, - VX_fpu_req_if fpu_req_if, - VX_gpu_req_if gpu_req_if + VX_alu_req_if.master alu_req_if, + VX_lsu_req_if.master lsu_req_if, + VX_csr_req_if.master csr_req_if, +`ifdef EXT_F_ENABLE + VX_fpu_req_if.master fpu_req_if, +`endif + VX_gpu_req_if.master gpu_req_if ); VX_ibuffer_if ibuffer_if(); - VX_ibuffer_if execute_if(); - VX_gpr_req_if gpr_req_if(); VX_gpr_rsp_if gpr_rsp_if(); - wire scoreboard_delay; + VX_gpr_req_if gpr_req_if(); + assign gpr_req_if.wid = ibuffer_if.wid; + assign gpr_req_if.rs1 = ibuffer_if.rs1; + assign gpr_req_if.rs2 = ibuffer_if.rs2; + assign gpr_req_if.rs3 = ibuffer_if.rs3; + + VX_writeback_if sboard_wb_if(); + assign sboard_wb_if.valid = writeback_if.valid; + assign sboard_wb_if.wid = writeback_if.wid; + assign sboard_wb_if.PC = writeback_if.PC; + assign sboard_wb_if.rd = writeback_if.rd; + assign sboard_wb_if.eop = writeback_if.eop; + assign sboard_wb_if.ready = writeback_if.ready; + + VX_ibuffer_if sboard_ib_if(); + assign sboard_ib_if.valid = ibuffer_if.valid && idmux_ib_if.ready; + assign sboard_ib_if.wid = ibuffer_if.wid; + assign sboard_ib_if.PC = ibuffer_if.PC; + assign sboard_ib_if.wb = ibuffer_if.wb; + assign sboard_ib_if.rd = ibuffer_if.rd; + assign sboard_ib_if.rd_n = ibuffer_if.rd_n; + assign sboard_ib_if.rs1_n = ibuffer_if.rs1_n; + assign sboard_ib_if.rs2_n = ibuffer_if.rs2_n; + assign sboard_ib_if.rs3_n = ibuffer_if.rs3_n; + assign sboard_ib_if.wid_n = ibuffer_if.wid_n; + + VX_ibuffer_if idmux_ib_if(); + assign idmux_ib_if.valid = ibuffer_if.valid && sboard_ib_if.ready; + assign idmux_ib_if.wid = ibuffer_if.wid; + assign idmux_ib_if.tmask = ibuffer_if.tmask; + assign idmux_ib_if.PC = ibuffer_if.PC; + assign idmux_ib_if.ex_type = ibuffer_if.ex_type; + assign idmux_ib_if.op_type = ibuffer_if.op_type; + assign idmux_ib_if.op_mod = ibuffer_if.op_mod; + assign idmux_ib_if.wb = ibuffer_if.wb; + assign idmux_ib_if.rd = ibuffer_if.rd; + assign idmux_ib_if.rs1 = ibuffer_if.rs1; + assign idmux_ib_if.imm = ibuffer_if.imm; + assign idmux_ib_if.use_PC = ibuffer_if.use_PC; + assign idmux_ib_if.use_imm = ibuffer_if.use_imm; + + // issue the instruction + assign ibuffer_if.ready = sboard_ib_if.ready && idmux_ib_if.ready; + + `RESET_RELAY (ibuf_reset); + `RESET_RELAY (gpr_reset); + `RESET_RELAY (demux_reset); VX_ibuffer #( .CORE_ID(CORE_ID) ) ibuffer ( .clk (clk), - .reset (reset), + .reset (ibuf_reset), .decode_if (decode_if), .ibuffer_if (ibuffer_if) ); @@ -42,54 +88,33 @@ module VX_issue #( ) scoreboard ( .clk (clk), .reset (reset), - .ibuffer_if (ibuffer_if), - .writeback_if(writeback_if), - .delay (scoreboard_delay) + .ibuffer_if (sboard_ib_if), + .writeback_if(sboard_wb_if) ); - - assign gpr_req_if.wid = ibuffer_if.wid; - assign gpr_req_if.rs1 = ibuffer_if.rs1; - assign gpr_req_if.rs2 = ibuffer_if.rs2; - assign gpr_req_if.rs3 = ibuffer_if.rs3; VX_gpr_stage #( .CORE_ID(CORE_ID) ) gpr_stage ( .clk (clk), - .reset (reset), + .reset (gpr_reset), .writeback_if (writeback_if), .gpr_req_if (gpr_req_if), .gpr_rsp_if (gpr_rsp_if) ); - assign execute_if.valid = ibuffer_if.valid && ~scoreboard_delay; - assign execute_if.wid = ibuffer_if.wid; - assign execute_if.tmask = ibuffer_if.tmask; - assign execute_if.PC = ibuffer_if.PC; - assign execute_if.ex_type = ibuffer_if.ex_type; - assign execute_if.op_type = ibuffer_if.op_type; - assign execute_if.op_mod = ibuffer_if.op_mod; - assign execute_if.wb = ibuffer_if.wb; - assign execute_if.rd = ibuffer_if.rd; - assign execute_if.rs1 = ibuffer_if.rs1; - assign execute_if.imm = ibuffer_if.imm; - assign execute_if.use_PC = ibuffer_if.use_PC; - assign execute_if.use_imm = ibuffer_if.use_imm; - VX_instr_demux instr_demux ( .clk (clk), - .reset (reset), - .ibuffer_if (execute_if), + .reset (demux_reset), + .ibuffer_if (idmux_ib_if), .gpr_rsp_if (gpr_rsp_if), .alu_req_if (alu_req_if), .lsu_req_if (lsu_req_if), .csr_req_if (csr_req_if), + `ifdef EXT_F_ENABLE .fpu_req_if (fpu_req_if), + `endif .gpu_req_if (gpu_req_if) - ); - - // issue the instruction - assign ibuffer_if.ready = !scoreboard_delay && execute_if.ready; + ); `SCOPE_ASSIGN (issue_fire, ibuffer_if.valid && ibuffer_if.ready); `SCOPE_ASSIGN (issue_wid, ibuffer_if.wid); @@ -106,8 +131,8 @@ module VX_issue #( `SCOPE_ASSIGN (issue_imm, ibuffer_if.imm); `SCOPE_ASSIGN (issue_use_pc, ibuffer_if.use_PC); `SCOPE_ASSIGN (issue_use_imm, ibuffer_if.use_imm); - `SCOPE_ASSIGN (scoreboard_delay, scoreboard_delay); - `SCOPE_ASSIGN (execute_delay, ~execute_if.ready); + `SCOPE_ASSIGN (scoreboard_delay, !sboard_wb_if.ready); + `SCOPE_ASSIGN (execute_delay, !idmux_ib_if.ready); `SCOPE_ASSIGN (gpr_rsp_a, gpr_rsp_if.rs1_data); `SCOPE_ASSIGN (gpr_rsp_b, gpr_rsp_if.rs2_data); `SCOPE_ASSIGN (gpr_rsp_c, gpr_rsp_if.rs3_data); @@ -145,7 +170,7 @@ module VX_issue #( if (decode_if.valid & !decode_if.ready) begin perf_ibf_stalls <= perf_ibf_stalls + `PERF_CTR_BITS'd1; end - if (ibuffer_if.valid & scoreboard_delay) begin + if (ibuffer_if.valid & !sboard_wb_if.ready) begin perf_scb_stalls <= perf_scb_stalls + `PERF_CTR_BITS'd1; end if (alu_req_if.valid & !alu_req_if.ready) begin @@ -182,46 +207,48 @@ module VX_issue #( `ifdef DBG_PRINT_PIPELINE always @(posedge clk) begin if (alu_req_if.valid && alu_req_if.ready) begin - $write("%t: core%0d-issue: wid=%0d, PC=%0h, ex=ALU, tmask=%b, rd=%0d, rs1_data=", + dpi_trace("%d: core%0d-issue: wid=%0d, PC=%0h, ex=ALU, tmask=%b, rd=%0d, rs1_data=", $time, CORE_ID, alu_req_if.wid, alu_req_if.PC, alu_req_if.tmask, alu_req_if.rd); - `PRINT_ARRAY1D(alu_req_if.rs1_data, `NUM_THREADS); - $write(", rs2_data="); - `PRINT_ARRAY1D(alu_req_if.rs2_data, `NUM_THREADS); - $write("\n"); + `TRACE_ARRAY1D(alu_req_if.rs1_data, `NUM_THREADS); + dpi_trace(", rs2_data="); + `TRACE_ARRAY1D(alu_req_if.rs2_data, `NUM_THREADS); + dpi_trace("\n"); end if (lsu_req_if.valid && lsu_req_if.ready) begin - $write("%t: core%0d-issue: wid=%0d, PC=%0h, ex=LSU, tmask=%b, rd=%0d, offset=%0h, addr=", + dpi_trace("%d: core%0d-issue: wid=%0d, PC=%0h, ex=LSU, tmask=%b, rd=%0d, offset=%0h, addr=", $time, CORE_ID, lsu_req_if.wid, lsu_req_if.PC, lsu_req_if.tmask, lsu_req_if.rd, lsu_req_if.offset); - `PRINT_ARRAY1D(lsu_req_if.base_addr, `NUM_THREADS); - $write(", data="); - `PRINT_ARRAY1D(lsu_req_if.store_data, `NUM_THREADS); - $write("\n"); + `TRACE_ARRAY1D(lsu_req_if.base_addr, `NUM_THREADS); + dpi_trace(", data="); + `TRACE_ARRAY1D(lsu_req_if.store_data, `NUM_THREADS); + dpi_trace("\n"); end if (csr_req_if.valid && csr_req_if.ready) begin - $write("%t: core%0d-issue: wid=%0d, PC=%0h, ex=CSR, tmask=%b, rd=%0d, addr=%0h, rs1_data=", + dpi_trace("%d: core%0d-issue: wid=%0d, PC=%0h, ex=CSR, tmask=%b, rd=%0d, addr=%0h, rs1_data=", $time, CORE_ID, csr_req_if.wid, csr_req_if.PC, csr_req_if.tmask, csr_req_if.rd, csr_req_if.addr); - `PRINT_ARRAY1D(csr_req_if.rs1_data, `NUM_THREADS); - $write("\n"); + `TRACE_ARRAY1D(csr_req_if.rs1_data, `NUM_THREADS); + dpi_trace("\n"); end + `ifdef EXT_F_ENABLE if (fpu_req_if.valid && fpu_req_if.ready) begin - $write("%t: core%0d-issue: wid=%0d, PC=%0h, ex=FPU, tmask=%b, rd=%0d, rs1_data=", + dpi_trace("%d: core%0d-issue: wid=%0d, PC=%0h, ex=FPU, tmask=%b, rd=%0d, rs1_data=", $time, CORE_ID, fpu_req_if.wid, fpu_req_if.PC, fpu_req_if.tmask, fpu_req_if.rd); - `PRINT_ARRAY1D(fpu_req_if.rs1_data, `NUM_THREADS); - $write(", rs2_data="); - `PRINT_ARRAY1D(fpu_req_if.rs2_data, `NUM_THREADS); - $write(", rs3_data="); - `PRINT_ARRAY1D(fpu_req_if.rs3_data, `NUM_THREADS); - $write("\n"); + `TRACE_ARRAY1D(fpu_req_if.rs1_data, `NUM_THREADS); + dpi_trace(", rs2_data="); + `TRACE_ARRAY1D(fpu_req_if.rs2_data, `NUM_THREADS); + dpi_trace(", rs3_data="); + `TRACE_ARRAY1D(fpu_req_if.rs3_data, `NUM_THREADS); + dpi_trace("\n"); end + `endif if (gpu_req_if.valid && gpu_req_if.ready) begin - $write("%t: core%0d-issue: wid=%0d, PC=%0h, ex=GPU, tmask=%b, rd=%0d, rs1_data=", + dpi_trace("%d: core%0d-issue: wid=%0d, PC=%0h, ex=GPU, tmask=%b, rd=%0d, rs1_data=", $time, CORE_ID, gpu_req_if.wid, gpu_req_if.PC, gpu_req_if.tmask, gpu_req_if.rd); - `PRINT_ARRAY1D(gpu_req_if.rs1_data, `NUM_THREADS); - $write(", rs2_data="); - `PRINT_ARRAY1D(gpu_req_if.rs2_data, `NUM_THREADS); - $write(", rs3_data="); - `PRINT_ARRAY1D(gpu_req_if.rs3_data, `NUM_THREADS); - $write("\n"); + `TRACE_ARRAY1D(gpu_req_if.rs1_data, `NUM_THREADS); + dpi_trace(", rs2_data="); + `TRACE_ARRAY1D(gpu_req_if.rs2_data, `NUM_THREADS); + dpi_trace(", rs3_data="); + `TRACE_ARRAY1D(gpu_req_if.rs3_data, `NUM_THREADS); + dpi_trace("\n"); end end `endif diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.sv similarity index 76% rename from hw/rtl/VX_lsu_unit.v rename to hw/rtl/VX_lsu_unit.sv index 31902302..11457d2f 100644 --- a/hw/rtl/VX_lsu_unit.v +++ b/hw/rtl/VX_lsu_unit.sv @@ -5,27 +5,26 @@ module VX_lsu_unit #( ) ( `SCOPE_IO_VX_lsu_unit - input wire clk, - input wire reset, + input wire clk, + input wire reset, // Dcache interface - VX_dcache_req_if dcache_req_if, - VX_dcache_rsp_if dcache_rsp_if, + VX_dcache_req_if.master dcache_req_if, + VX_dcache_rsp_if.slave dcache_rsp_if, // inputs - VX_lsu_req_if lsu_req_if, + VX_lsu_req_if.slave lsu_req_if, // outputs - VX_commit_if ld_commit_if, - VX_commit_if st_commit_if + VX_commit_if.master ld_commit_if, + VX_commit_if.master st_commit_if ); localparam MEM_ASHIFT = `CLOG2(`MEM_BLOCK_SIZE); localparam MEM_ADDRW = 32 - MEM_ASHIFT; - localparam REQ_ASHIFT = `CLOG2(`DWORD_SIZE); - localparam REQ_ADDRW = 32 - REQ_ASHIFT; + localparam REQ_ASHIFT = `CLOG2(`DCACHE_WORD_SIZE); - localparam ADDR_TYPEW = `NC_ADDR_BITS + `SM_ENABLE; + localparam ADDR_TYPEW = `NC_FLAG_BITS + `SM_ENABLE; `STATIC_ASSERT(0 == (`IO_BASE_ADDR % MEM_ASHIFT), ("invalid parameter")) `STATIC_ASSERT(0 == (`SMEM_BASE_ADDR % MEM_ASHIFT), ("invalid parameter")) @@ -34,7 +33,7 @@ module VX_lsu_unit #( wire req_valid; wire [`NUM_THREADS-1:0] req_tmask; wire [`NUM_THREADS-1:0][31:0] req_addr; - wire [`LSU_BITS-1:0] req_type; + wire [`INST_LSU_BITS-1:0] req_type; wire [`NUM_THREADS-1:0][31:0] req_data; wire [`NR_BITS-1:0] req_rd; wire req_wb; @@ -52,9 +51,9 @@ module VX_lsu_unit #( end // detect duplicate addresses - wire [`NUM_THREADS-1:0] addr_matches; - for (genvar i = 0; i < `NUM_THREADS; i++) begin - assign addr_matches[i] = (full_addr[0] == full_addr[i]) || ~lsu_req_if.tmask[i]; + wire [`NUM_THREADS-2:0] addr_matches; + for (genvar i = 0; i < (`NUM_THREADS-1); i++) begin + assign addr_matches[i] = (lsu_req_if.base_addr[i+1] == lsu_req_if.base_addr[0]) || ~lsu_req_if.tmask[i+1]; end wire lsu_is_dup = lsu_req_if.tmask[0] && (& addr_matches); @@ -81,7 +80,7 @@ module VX_lsu_unit #( wire lsu_valid = lsu_req_if.valid && ~fence_wait; VX_pipe_register #( - .DATAW (1 + 1 + `NW_BITS + `NUM_THREADS + 32 + (`NUM_THREADS * 32) + (`NUM_THREADS * ADDR_TYPEW) + `LSU_BITS + `NR_BITS + 1 + (`NUM_THREADS * 32)), + .DATAW (1 + 1 + `NW_BITS + `NUM_THREADS + 32 + (`NUM_THREADS * 32) + (`NUM_THREADS * ADDR_TYPEW) + `INST_LSU_BITS + `NR_BITS + 1 + (`NUM_THREADS * 32)), .RESETW (1) ) req_pipe_reg ( .clk (clk), @@ -98,7 +97,7 @@ module VX_lsu_unit #( wire [31:0] rsp_pc; wire [`NR_BITS-1:0] rsp_rd; wire rsp_wb; - wire [`LSU_BITS-1:0] rsp_type; + wire [`INST_LSU_BITS-1:0] rsp_type; wire rsp_is_dup; `UNUSED_VAR (rsp_type) @@ -120,11 +119,12 @@ module VX_lsu_unit #( wire [`NUM_THREADS-1:0] dcache_req_fire = dcache_req_if.valid & dcache_req_if.ready; - wire dcache_req_fire_any = (| dcache_req_fire); - wire dcache_rsp_fire = dcache_rsp_if.valid && dcache_rsp_if.ready; - wire mbuf_push = dcache_req_fire_any + wire [`NUM_THREADS-1:0] req_tmask_dup = req_tmask & {{(`NUM_THREADS-1){~req_is_dup}}, 1'b1}; + + wire mbuf_push = ~mbuf_full + && (| ({`NUM_THREADS{req_valid}} & req_tmask_dup & dcache_req_if.ready)) && is_req_start // first submission only && req_wb; // loads only @@ -134,8 +134,8 @@ module VX_lsu_unit #( `UNUSED_VAR (dcache_rsp_if.tag) VX_index_buffer #( - .DATAW (`NW_BITS + 32 + `NUM_THREADS + `NR_BITS + 1 + `LSU_BITS + (`NUM_THREADS * REQ_ASHIFT) + 1), - .SIZE (`LSUQ_SIZE) + .DATAW (`NW_BITS + 32 + `NUM_THREADS + `NR_BITS + 1 + `INST_LSU_BITS + (`NUM_THREADS * REQ_ASHIFT) + 1), + .SIZE (`LSUQ_SIZE) ) req_metadata ( .clk (clk), .reset (reset), @@ -150,9 +150,7 @@ module VX_lsu_unit #( .empty (mbuf_empty) ); - wire [`NUM_THREADS-1:0] req_tmask_dup = req_tmask & {{(`NUM_THREADS-1){~req_is_dup}}, 1'b1}; - - wire req_ready_all = &(dcache_req_if.ready | req_sent_mask | ~req_tmask_dup); + wire dcache_req_ready = &(dcache_req_if.ready | req_sent_mask | ~req_tmask_dup); wire [`NUM_THREADS-1:0] req_sent_mask_n = req_sent_mask | dcache_req_fire; @@ -161,7 +159,7 @@ module VX_lsu_unit #( req_sent_mask <= 0; is_req_start <= 1; end else begin - if (req_ready_all) begin + if (dcache_req_ready) begin req_sent_mask <= 0; is_req_start <= 1; end else begin @@ -204,7 +202,7 @@ module VX_lsu_unit #( always @(*) begin mem_req_byteen = {4{req_wb}}; - case (`LSU_WSIZE(req_type)) + case (`INST_LSU_WSIZE(req_type)) 0: mem_req_byteen[req_offset[i]] = 1; 1: begin mem_req_byteen[req_offset[i]] = 1; @@ -237,11 +235,11 @@ module VX_lsu_unit #( `endif end - assign ready_in = req_dep_ready && req_ready_all; + assign ready_in = req_dep_ready && dcache_req_ready; // send store commit - wire is_store_rsp = req_valid && ~req_wb && req_ready_all; + wire is_store_rsp = req_valid && ~req_wb && dcache_req_ready; assign st_commit_if.valid = is_store_rsp; assign st_commit_if.wid = req_wid; @@ -263,11 +261,11 @@ module VX_lsu_unit #( wire [7:0] rsp_data8 = rsp_offset[i][0] ? rsp_data16[15:8] : rsp_data16[7:0]; always @(*) begin - case (`LSU_FMT(rsp_type)) - `FMT_B: rsp_data[i] = 32'(signed'(rsp_data8)); - `FMT_H: rsp_data[i] = 32'(signed'(rsp_data16)); - `FMT_BU: rsp_data[i] = 32'(unsigned'(rsp_data8)); - `FMT_HU: rsp_data[i] = 32'(unsigned'(rsp_data16)); + case (`INST_LSU_FMT(rsp_type)) + `INST_FMT_B: rsp_data[i] = 32'(signed'(rsp_data8)); + `INST_FMT_H: rsp_data[i] = 32'(signed'(rsp_data16)); + `INST_FMT_BU: rsp_data[i] = 32'(unsigned'(rsp_data8)); + `INST_FMT_HU: rsp_data[i] = 32'(unsigned'(rsp_data16)); default: rsp_data[i] = rsp_data32; endcase end @@ -307,7 +305,7 @@ module VX_lsu_unit #( `SCOPE_ASSIGN (dcache_rsp_tag, mbuf_raddr); `ifndef SYNTHESIS - reg [`LSUQ_SIZE-1:0][(`NW_BITS + 32 + 64 + 1)-1:0] pending_reqs; + reg [`LSUQ_SIZE-1:0][(`NW_BITS + 32 + `NR_BITS + 64 + 1)-1:0] pending_reqs; wire [63:0] delay_timeout = 10000 * (1 ** (`L2_ENABLE + `L3_ENABLE)); always @(posedge clk) begin @@ -315,7 +313,7 @@ module VX_lsu_unit #( pending_reqs <= '0; end begin if (mbuf_push) begin - pending_reqs[mbuf_waddr] <= {req_wid, req_pc, $time, 1'b1}; + pending_reqs[mbuf_waddr] <= {req_wid, req_pc, req_rd, $time, 1'b1}; end if (mbuf_pop) begin pending_reqs[mbuf_raddr] <= '0; @@ -324,40 +322,42 @@ module VX_lsu_unit #( for (integer i = 0; i < `LSUQ_SIZE; ++i) begin if (pending_reqs[i][0]) begin - assert(($time - pending_reqs[i][1 +: 64]) < delay_timeout) else - $error("%t: *** D$%0d response timeout: wid=%0d, PC=%0h", $time, CORE_ID, pending_reqs[i][1+64+32 +: `NW_BITS], pending_reqs[i][1+64 +: 32]); + `ASSERT(($time - pending_reqs[i][1 +: 64]) < delay_timeout, + ("%t: *** D$%0d response timeout: remaining=%b, wid=%0d, PC=%0h, rd=%0d", + $time, CORE_ID, rsp_rem_mask[i], pending_reqs[i][1+64+32+`NR_BITS +: `NW_BITS], pending_reqs[i][1+64+`NR_BITS +: 32], pending_reqs[i][1+64 +: `NR_BITS])); end end end `endif `ifdef DBG_PRINT_CORE_DCACHE - always @(posedge clk) begin - if (lsu_req_if.valid && fence_wait) begin - $display("%t: *** D$%0d fence wait", $time, CORE_ID); + wire dcache_req_fire_any = (| dcache_req_fire); + always @(posedge clk) begin + if (lsu_req_if.valid && fence_wait) begin + dpi_trace("%d: *** D$%0d fence wait\n", $time, CORE_ID); end if (dcache_req_fire_any) begin if (dcache_req_if.rw[0]) begin - $write("%t: D$%0d Wr Req: wid=%0d, PC=%0h, tmask=%b, addr=", $time, CORE_ID, req_wid, req_pc, dcache_req_fire); - `PRINT_ARRAY1D(req_addr, `NUM_THREADS); - $write(", tag=%0h, byteen=%0h, type=", req_tag, dcache_req_if.byteen); - `PRINT_ARRAY1D(req_addr_type, `NUM_THREADS); - $write(", data="); - `PRINT_ARRAY1D(dcache_req_if.data, `NUM_THREADS); - $write("\n"); + dpi_trace("%d: D$%0d Wr Req: wid=%0d, PC=%0h, tmask=%b, addr=", $time, CORE_ID, req_wid, req_pc, dcache_req_fire); + `TRACE_ARRAY1D(req_addr, `NUM_THREADS); + dpi_trace(", tag=%0h, byteen=%0h, type=", req_tag, dcache_req_if.byteen); + `TRACE_ARRAY1D(req_addr_type, `NUM_THREADS); + dpi_trace(", data="); + `TRACE_ARRAY1D(dcache_req_if.data, `NUM_THREADS); + dpi_trace("\n"); end else begin - $write("%t: D$%0d Rd Req: wid=%0d, PC=%0h, tmask=%b, addr=", $time, CORE_ID, req_wid, req_pc, dcache_req_fire); - `PRINT_ARRAY1D(req_addr, `NUM_THREADS); - $write(", tag=%0h, byteen=%0h, type=", req_tag, dcache_req_if.byteen); - `PRINT_ARRAY1D(req_addr_type, `NUM_THREADS); - $write(", rd=%0d, is_dup=%b\n", req_rd, req_is_dup); + dpi_trace("%d: D$%0d Rd Req: wid=%0d, PC=%0h, tmask=%b, addr=", $time, CORE_ID, req_wid, req_pc, dcache_req_fire); + `TRACE_ARRAY1D(req_addr, `NUM_THREADS); + dpi_trace(", tag=%0h, byteen=%0h, type=", req_tag, dcache_req_if.byteen); + `TRACE_ARRAY1D(req_addr_type, `NUM_THREADS); + dpi_trace(", rd=%0d, is_dup=%b\n", req_rd, req_is_dup); end end if (dcache_rsp_fire) begin - $write("%t: D$%0d Rsp: wid=%0d, PC=%0h, tmask=%b, tag=%0h, rd=%0d, data=", + dpi_trace("%d: D$%0d Rsp: wid=%0d, PC=%0h, tmask=%b, tag=%0h, rd=%0d, data=", $time, CORE_ID, rsp_wid, rsp_pc, dcache_rsp_if.tmask, mbuf_raddr, rsp_rd); - `PRINT_ARRAY1D(dcache_rsp_if.data, `NUM_THREADS); - $write(", is_dup=%b\n", rsp_is_dup); + `TRACE_ARRAY1D(dcache_rsp_if.data, `NUM_THREADS); + dpi_trace(", is_dup=%b\n", rsp_is_dup); end end `endif diff --git a/hw/rtl/VX_mem_arb.v b/hw/rtl/VX_mem_arb.sv similarity index 96% rename from hw/rtl/VX_mem_arb.v rename to hw/rtl/VX_mem_arb.sv index 2864684e..5a410476 100644 --- a/hw/rtl/VX_mem_arb.v +++ b/hw/rtl/VX_mem_arb.sv @@ -8,11 +8,11 @@ module VX_mem_arb #( parameter TAG_SEL_IDX = 0, parameter BUFFERED_REQ = 0, parameter BUFFERED_RSP = 0, - parameter TYPE = "R", + parameter TYPE = "P", - localparam DATA_SIZE = (DATA_WIDTH / 8), - localparam LOG_NUM_REQS = `CLOG2(NUM_REQS), - localparam TAG_OUT_WIDTH = TAG_IN_WIDTH + LOG_NUM_REQS + parameter DATA_SIZE = (DATA_WIDTH / 8), + parameter LOG_NUM_REQS = `CLOG2(NUM_REQS), + parameter TAG_OUT_WIDTH = TAG_IN_WIDTH + LOG_NUM_REQS ) ( input wire clk, input wire reset, diff --git a/hw/rtl/VX_mem_unit.v b/hw/rtl/VX_mem_unit.sv similarity index 71% rename from hw/rtl/VX_mem_unit.v rename to hw/rtl/VX_mem_unit.sv index 73e60433..7c53ccc8 100644 --- a/hw/rtl/VX_mem_unit.v +++ b/hw/rtl/VX_mem_unit.sv @@ -5,24 +5,24 @@ module VX_mem_unit # ( ) ( `SCOPE_IO_VX_mem_unit - input wire clk, - input wire reset, + input wire clk, + input wire reset, `ifdef PERF_ENABLE - VX_perf_memsys_if perf_memsys_if, + VX_perf_memsys_if.master perf_memsys_if, `endif // Core <-> Dcache - VX_dcache_req_if dcache_req_if, - VX_dcache_rsp_if dcache_rsp_if, + VX_dcache_req_if.slave dcache_req_if, + VX_dcache_rsp_if.master dcache_rsp_if, // Core <-> Icache - VX_icache_req_if icache_req_if, - VX_icache_rsp_if icache_rsp_if, + VX_icache_req_if.slave icache_req_if, + VX_icache_rsp_if.master icache_rsp_if, // Memory - VX_mem_req_if mem_req_if, - VX_mem_rsp_if mem_rsp_if + VX_mem_req_if.master mem_req_if, + VX_mem_rsp_if.slave mem_rsp_if ); `ifdef PERF_ENABLE @@ -30,58 +30,59 @@ module VX_mem_unit # ( `endif VX_mem_req_if #( - .DATA_WIDTH (`IMEM_DATA_WIDTH), - .ADDR_WIDTH (`IMEM_ADDR_WIDTH), - .TAG_WIDTH (`IMEM_TAG_WIDTH) + .DATA_WIDTH (`ICACHE_MEM_DATA_WIDTH), + .ADDR_WIDTH (`ICACHE_MEM_ADDR_WIDTH), + .TAG_WIDTH (`ICACHE_MEM_TAG_WIDTH) ) icache_mem_req_if(); VX_mem_rsp_if #( - .DATA_WIDTH (`IMEM_DATA_WIDTH), - .TAG_WIDTH (`IMEM_TAG_WIDTH) + .DATA_WIDTH (`ICACHE_MEM_DATA_WIDTH), + .TAG_WIDTH (`ICACHE_MEM_TAG_WIDTH) ) icache_mem_rsp_if(); VX_mem_req_if #( - .DATA_WIDTH (`DMEM_DATA_WIDTH), - .ADDR_WIDTH (`DMEM_ADDR_WIDTH), - .TAG_WIDTH (`DMEM_TAG_WIDTH) + .DATA_WIDTH (`DCACHE_MEM_DATA_WIDTH), + .ADDR_WIDTH (`DCACHE_MEM_ADDR_WIDTH), + .TAG_WIDTH (`DCACHE_MEM_TAG_WIDTH) ) dcache_mem_req_if(); VX_mem_rsp_if #( - .DATA_WIDTH (`DMEM_DATA_WIDTH), - .TAG_WIDTH (`DMEM_TAG_WIDTH) + .DATA_WIDTH (`DCACHE_MEM_DATA_WIDTH), + .TAG_WIDTH (`DCACHE_MEM_TAG_WIDTH) ) dcache_mem_rsp_if(); VX_dcache_req_if #( - .NUM_REQS (`DNUM_REQS), - .WORD_SIZE (`DWORD_SIZE), - .TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE) + .NUM_REQS (`DCACHE_NUM_REQS), + .WORD_SIZE (`DCACHE_WORD_SIZE), + .TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH-`SM_ENABLE) ) dcache_req_tmp_if(); VX_dcache_rsp_if #( - .NUM_REQS (`DNUM_REQS), - .WORD_SIZE (`DWORD_SIZE), - .TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE) + .NUM_REQS (`DCACHE_NUM_REQS), + .WORD_SIZE (`DCACHE_WORD_SIZE), + .TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH-`SM_ENABLE) ) dcache_rsp_tmp_if(); `RESET_RELAY (icache_reset); `RESET_RELAY (dcache_reset); + `RESET_RELAY (mem_arb_reset); VX_cache #( .CACHE_ID (`ICACHE_ID), .CACHE_SIZE (`ICACHE_SIZE), .CACHE_LINE_SIZE (`ICACHE_LINE_SIZE), - .NUM_BANKS (`INUM_BANKS), - .WORD_SIZE (`IWORD_SIZE), + .NUM_BANKS (1), + .WORD_SIZE (`ICACHE_WORD_SIZE), .NUM_REQS (1), - .CREQ_SIZE (`ICREQ_SIZE), - .CRSQ_SIZE (`ICRSQ_SIZE), - .MSHR_SIZE (`IMSHR_SIZE), - .MRSQ_SIZE (`IMRSQ_SIZE), - .MREQ_SIZE (`IMREQ_SIZE), + .CREQ_SIZE (`ICACHE_CREQ_SIZE), + .CRSQ_SIZE (`ICACHE_CRSQ_SIZE), + .MSHR_SIZE (`ICACHE_MSHR_SIZE), + .MRSQ_SIZE (`ICACHE_MRSQ_SIZE), + .MREQ_SIZE (`ICACHE_MREQ_SIZE), .WRITE_ENABLE (0), - .CORE_TAG_WIDTH (`ICORE_TAG_WIDTH), - .CORE_TAG_ID_BITS (`ICORE_TAG_ID_BITS), - .MEM_TAG_WIDTH (`IMEM_TAG_WIDTH) + .CORE_TAG_WIDTH (`ICACHE_CORE_TAG_WIDTH), + .CORE_TAG_ID_BITS (`ICACHE_CORE_TAG_ID_BITS), + .MEM_TAG_WIDTH (`ICACHE_MEM_TAG_WIDTH) ) icache ( `SCOPE_BIND_VX_mem_unit_icache @@ -91,7 +92,7 @@ module VX_mem_unit # ( // Core request .core_req_valid (icache_req_if.valid), .core_req_rw (1'b0), - .core_req_byteen ({`IWORD_SIZE{1'b1}}), + .core_req_byteen ('b0), .core_req_addr (icache_req_if.addr), .core_req_data ('x), .core_req_tag (icache_req_if.tag), @@ -128,19 +129,19 @@ module VX_mem_unit # ( .CACHE_ID (`DCACHE_ID), .CACHE_SIZE (`DCACHE_SIZE), .CACHE_LINE_SIZE (`DCACHE_LINE_SIZE), - .NUM_BANKS (`DNUM_BANKS), - .NUM_PORTS (`DNUM_PORTS), - .WORD_SIZE (`DWORD_SIZE), - .NUM_REQS (`DNUM_REQS), - .CREQ_SIZE (`DCREQ_SIZE), - .CRSQ_SIZE (`DCRSQ_SIZE), - .MSHR_SIZE (`DMSHR_SIZE), - .MRSQ_SIZE (`DMRSQ_SIZE), - .MREQ_SIZE (`DMREQ_SIZE), + .NUM_BANKS (`DCACHE_NUM_BANKS), + .NUM_PORTS (`DCACHE_NUM_PORTS), + .WORD_SIZE (`DCACHE_WORD_SIZE), + .NUM_REQS (`DCACHE_NUM_REQS), + .CREQ_SIZE (`DCACHE_CREQ_SIZE), + .CRSQ_SIZE (`DCACHE_CRSQ_SIZE), + .MSHR_SIZE (`DCACHE_MSHR_SIZE), + .MRSQ_SIZE (`DCACHE_MRSQ_SIZE), + .MREQ_SIZE (`DCACHE_MREQ_SIZE), .WRITE_ENABLE (1), - .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE), - .CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS-`SM_ENABLE), - .MEM_TAG_WIDTH (`DMEM_TAG_WIDTH), + .CORE_TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH-`SM_ENABLE), + .CORE_TAG_ID_BITS (`DCACHE_CORE_TAG_ID_BITS-`SM_ENABLE), + .MEM_TAG_WIDTH (`DCACHE_MEM_TAG_WIDTH), .NC_ENABLE (1) ) dcache ( `SCOPE_BIND_VX_mem_unit_dcache @@ -186,28 +187,31 @@ module VX_mem_unit # ( if (`SM_ENABLE) begin VX_dcache_req_if #( - .NUM_REQS (`DNUM_REQS), - .WORD_SIZE (`DWORD_SIZE), - .TAG_WIDTH (`DCORE_TAG_WIDTH-1) + .NUM_REQS (`DCACHE_NUM_REQS), + .WORD_SIZE (`DCACHE_WORD_SIZE), + .TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH-`SM_ENABLE) ) smem_req_if(); VX_dcache_rsp_if #( - .NUM_REQS (`DNUM_REQS), - .WORD_SIZE (`DWORD_SIZE), - .TAG_WIDTH (`DCORE_TAG_WIDTH-1) + .NUM_REQS (`DCACHE_NUM_REQS), + .WORD_SIZE (`DCACHE_WORD_SIZE), + .TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH-`SM_ENABLE) ) smem_rsp_if(); - VX_smem_arb #( + `RESET_RELAY (smem_arb_reset); + `RESET_RELAY (smem_reset); + + VX_smem_arb #( .NUM_REQS (2), .LANES (`NUM_THREADS), .DATA_SIZE (4), - .TAG_IN_WIDTH (`DCORE_TAG_WIDTH), - .TYPE ("X"), + .TAG_IN_WIDTH (`DCACHE_CORE_TAG_WIDTH), + .TYPE ("P"), .BUFFERED_REQ (2), .BUFFERED_RSP (1) ) smem_arb ( .clk (clk), - .reset (reset), + .reset (smem_arb_reset), // input request .req_valid_in (dcache_req_if.valid), @@ -242,19 +246,17 @@ module VX_mem_unit # ( .rsp_ready_out (dcache_rsp_if.ready) ); - `RESET_RELAY (smem_reset); - VX_shared_mem #( - .CACHE_ID (`SCACHE_ID), + .CACHE_ID (`SMEM_ID), .CACHE_SIZE (`SMEM_SIZE), - .NUM_BANKS (`SNUM_BANKS), - .WORD_SIZE (`SWORD_SIZE), - .NUM_REQS (`SNUM_REQS), - .CREQ_SIZE (`SCREQ_SIZE), - .CRSQ_SIZE (`SCRSQ_SIZE), - .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH-1), - .CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS-1), - .BANK_ADDR_OFFSET (`SBANK_ADDR_OFFSET) + .NUM_BANKS (`SMEM_NUM_BANKS), + .WORD_SIZE (`SMEM_WORD_SIZE), + .NUM_REQS (`SMEM_NUM_REQS), + .CREQ_SIZE (`SMEM_CREQ_SIZE), + .CRSQ_SIZE (`SMEM_CRSQ_SIZE), + .CORE_TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH-`SM_ENABLE), + .CORE_TAG_ID_BITS (`DCACHE_CORE_TAG_ID_BITS-`SM_ENABLE), + .BANK_ADDR_OFFSET (`SMEM_BANK_ADDR_OFFSET) ) smem ( .clk (clk), .reset (smem_reset), @@ -281,13 +283,20 @@ module VX_mem_unit # ( ); end else begin // core to D-cache request - assign dcache_req_tmp_if.valid = dcache_req_if.valid; - assign dcache_req_tmp_if.addr = dcache_req_if.addr; - assign dcache_req_tmp_if.rw = dcache_req_if.rw; - assign dcache_req_tmp_if.byteen = dcache_req_if.byteen; - assign dcache_req_tmp_if.data = dcache_req_if.data; - assign dcache_req_tmp_if.tag = dcache_req_if.tag; - assign dcache_req_if.ready = dcache_req_tmp_if.ready; + for (genvar i = 0; i < `DCACHE_NUM_REQS; ++i) begin + VX_skid_buffer #( + .DATAW ((32-`CLOG2(`DCACHE_WORD_SIZE)) + 1 + `DCACHE_WORD_SIZE + (8*`DCACHE_WORD_SIZE) + `DCACHE_CORE_TAG_WIDTH) + ) req_buf ( + .clk (clk), + .reset (reset), + .valid_in (dcache_req_if.valid[i]), + .data_in ({dcache_req_if.addr[i], dcache_req_if.rw[i], dcache_req_if.byteen[i], dcache_req_if.data[i], dcache_req_if.tag[i]}), + .ready_in (dcache_req_if.ready[i]), + .valid_out (dcache_req_tmp_if.valid[i]), + .data_out ({dcache_req_tmp_if.addr[i], dcache_req_tmp_if.rw[i], dcache_req_tmp_if.byteen[i], dcache_req_tmp_if.data[i], dcache_req_tmp_if.tag[i]}), + .ready_out (dcache_req_tmp_if.ready[i]) + ); + end // D-cache to core reponse assign dcache_rsp_if.valid = dcache_rsp_tmp_if.valid; @@ -297,21 +306,23 @@ module VX_mem_unit # ( assign dcache_rsp_tmp_if.ready = dcache_rsp_if.ready; end - wire [`DMEM_TAG_WIDTH-1:0] icache_mem_req_tag = `DMEM_TAG_WIDTH'(icache_mem_req_if.tag); - wire [`DMEM_TAG_WIDTH-1:0] icache_mem_rsp_tag; - assign icache_mem_rsp_if.tag = icache_mem_rsp_tag[`IMEM_TAG_WIDTH-1:0]; + wire [`DCACHE_MEM_TAG_WIDTH-1:0] icache_mem_req_tag = `DCACHE_MEM_TAG_WIDTH'(icache_mem_req_if.tag); + wire [`DCACHE_MEM_TAG_WIDTH-1:0] icache_mem_rsp_tag; + assign icache_mem_rsp_if.tag = icache_mem_rsp_tag[`ICACHE_MEM_TAG_WIDTH-1:0]; `UNUSED_VAR (icache_mem_rsp_tag) VX_mem_arb #( .NUM_REQS (2), - .DATA_WIDTH (`DMEM_DATA_WIDTH), - .ADDR_WIDTH (`DMEM_ADDR_WIDTH), - .TAG_IN_WIDTH (`DMEM_TAG_WIDTH), + .DATA_WIDTH (`DCACHE_MEM_DATA_WIDTH), + .ADDR_WIDTH (`DCACHE_MEM_ADDR_WIDTH), + .TAG_IN_WIDTH (`DCACHE_MEM_TAG_WIDTH), + .TYPE ("R"), + .TAG_SEL_IDX (1), // Skip 0 for NC flag .BUFFERED_REQ (1), .BUFFERED_RSP (2) ) mem_arb ( .clk (clk), - .reset (reset), + .reset (mem_arb_reset), // Source request .req_valid_in ({dcache_mem_req_if.valid, icache_mem_req_if.valid}), diff --git a/hw/rtl/VX_muldiv.v b/hw/rtl/VX_muldiv.sv similarity index 88% rename from hw/rtl/VX_muldiv.v rename to hw/rtl/VX_muldiv.sv index 189d596f..5cd13f5c 100644 --- a/hw/rtl/VX_muldiv.v +++ b/hw/rtl/VX_muldiv.sv @@ -1,15 +1,11 @@ `include "VX_define.vh" -`ifndef SYNTHESIS -`include "util_dpi.vh" -`endif - module VX_muldiv ( input wire clk, input wire reset, // Inputs - input wire [`MUL_BITS-1:0] alu_op, + input wire [`INST_MUL_BITS-1:0] alu_op, input wire [`NW_BITS-1:0] wid_in, input wire [`NUM_THREADS-1:0] tmask_in, input wire [31:0] PC_in, @@ -33,7 +29,7 @@ module VX_muldiv ( input wire ready_out ); - wire is_div_op = `MUL_IS_DIV(alu_op); + wire is_div_op = `INST_MUL_IS_DIV(alu_op); wire [`NUM_THREADS-1:0][31:0] mul_result; wire [`NW_BITS-1:0] mul_wid_out; @@ -48,18 +44,20 @@ module VX_muldiv ( wire mul_valid_in = valid_in && !is_div_op; wire mul_ready_in = ~stall_out || ~mul_valid_out; - wire is_mulh_in = (alu_op != `MUL_MUL); - wire is_signed_mul_a = (alu_op != `MUL_MULHU); - wire is_signed_mul_b = (alu_op != `MUL_MULHU && alu_op != `MUL_MULHSU); + wire is_mulh_in = (alu_op != `INST_MUL_MUL); + wire is_signed_mul_a = (alu_op != `INST_MUL_MULHU); + wire is_signed_mul_b = (alu_op != `INST_MUL_MULHU && alu_op != `INST_MUL_MULHSU); `ifdef IMUL_DPI - wire [`NUM_THREADS-1:0][31:0] mul_result_tmp; + wire [`NUM_THREADS-1:0][31:0] mul_result_tmp; + + wire mul_fire_in = mul_valid_in && mul_ready_in; for (genvar i = 0; i < `NUM_THREADS; i++) begin wire [31:0] mul_resultl, mul_resulth; always @(*) begin - dpi_imul (alu_in1[i], alu_in2[i], is_signed_mul_a, is_signed_mul_b, mul_resultl, mul_resulth); + dpi_imul (mul_fire_in, alu_in1[i], alu_in2[i], is_signed_mul_a, is_signed_mul_b, mul_resultl, mul_resulth); end assign mul_result_tmp[i] = is_mulh_in ? mul_resulth : mul_resultl; end @@ -83,9 +81,9 @@ module VX_muldiv ( for (genvar i = 0; i < `NUM_THREADS; i++) begin wire [32:0] mul_in1 = {is_signed_mul_a & alu_in1[i][31], alu_in1[i]}; wire [32:0] mul_in2 = {is_signed_mul_b & alu_in2[i][31], alu_in2[i]}; - `IGNORE_WARNINGS_BEGIN + `IGNORE_UNUSED_BEGIN wire [65:0] mul_result_tmp; - `IGNORE_WARNINGS_END + `IGNORE_UNUSED_END VX_multiplier #( .WIDTHA (33), @@ -127,8 +125,8 @@ module VX_muldiv ( wire [`NR_BITS-1:0] div_rd_out; wire div_wb_out; - wire is_rem_op_in = (alu_op == `MUL_REM) || (alu_op == `MUL_REMU); - wire is_signed_div = (alu_op == `MUL_DIV) || (alu_op == `MUL_REM); + wire is_rem_op_in = (alu_op == `INST_MUL_REM) || (alu_op == `INST_MUL_REMU); + wire is_signed_div = (alu_op == `INST_MUL_DIV) || (alu_op == `INST_MUL_REM); wire div_valid_in = valid_in && is_div_op; wire div_ready_out = ~stall_out && ~mul_valid_out; // arbitration prioritizes MUL wire div_ready_in; @@ -137,11 +135,13 @@ module VX_muldiv ( `ifdef IDIV_DPI wire [`NUM_THREADS-1:0][31:0] div_result_tmp; + + wire div_fire_in = div_valid_in && div_ready_in; for (genvar i = 0; i < `NUM_THREADS; i++) begin wire [31:0] div_quotient, div_remainder; always @(*) begin - dpi_idiv (alu_in1[i], alu_in2[i], is_signed_div, div_quotient, div_remainder); + dpi_idiv (div_fire_in, alu_in1[i], alu_in2[i], is_signed_div, div_quotient, div_remainder); end assign div_result_tmp[i] = is_rem_op_in ? div_remainder : div_quotient; end diff --git a/hw/rtl/VX_pipeline.v b/hw/rtl/VX_pipeline.sv similarity index 87% rename from hw/rtl/VX_pipeline.v rename to hw/rtl/VX_pipeline.sv index b53a1e52..8bbc7ead 100644 --- a/hw/rtl/VX_pipeline.v +++ b/hw/rtl/VX_pipeline.sv @@ -15,30 +15,30 @@ module VX_pipeline #( output wire [`NUM_THREADS-1:0][3:0] dcache_req_byteen, output wire [`NUM_THREADS-1:0][29:0] dcache_req_addr, output wire [`NUM_THREADS-1:0][31:0] dcache_req_data, - output wire [`NUM_THREADS-1:0][`DCORE_TAG_WIDTH-1:0] dcache_req_tag, + output wire [`NUM_THREADS-1:0][`DCACHE_CORE_TAG_WIDTH-1:0] dcache_req_tag, input wire [`NUM_THREADS-1:0] dcache_req_ready, // Dcache core reponse input wire dcache_rsp_valid, input wire [`NUM_THREADS-1:0] dcache_rsp_tmask, input wire [`NUM_THREADS-1:0][31:0] dcache_rsp_data, - input wire [`DCORE_TAG_WIDTH-1:0] dcache_rsp_tag, + input wire [`DCACHE_CORE_TAG_WIDTH-1:0] dcache_rsp_tag, output wire dcache_rsp_ready, // Icache core request output wire icache_req_valid, output wire [29:0] icache_req_addr, - output wire [`ICORE_TAG_WIDTH-1:0] icache_req_tag, + output wire [`ICACHE_CORE_TAG_WIDTH-1:0] icache_req_tag, input wire icache_req_ready, // Icache core response input wire icache_rsp_valid, input wire [31:0] icache_rsp_data, - input wire [`ICORE_TAG_WIDTH-1:0] icache_rsp_tag, + input wire [`ICACHE_CORE_TAG_WIDTH-1:0] icache_rsp_tag, output wire icache_rsp_ready, `ifdef PERF_ENABLE - VX_perf_memsys_if perf_memsys_if, + VX_perf_memsys_if.slave perf_memsys_if, `endif // Status @@ -51,7 +51,7 @@ module VX_pipeline #( VX_dcache_req_if #( .NUM_REQS (`NUM_THREADS), .WORD_SIZE (4), - .TAG_WIDTH (`DCORE_TAG_WIDTH) + .TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH) ) dcache_req_if(); assign dcache_req_valid = dcache_req_if.valid; @@ -69,7 +69,7 @@ module VX_pipeline #( VX_dcache_rsp_if #( .NUM_REQS (`NUM_THREADS), .WORD_SIZE (4), - .TAG_WIDTH (`DCORE_TAG_WIDTH) + .TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH) ) dcache_rsp_if(); assign dcache_rsp_if.valid = dcache_rsp_valid; @@ -84,7 +84,7 @@ module VX_pipeline #( VX_icache_req_if #( .WORD_SIZE (4), - .TAG_WIDTH (`ICORE_TAG_WIDTH) + .TAG_WIDTH (`ICACHE_CORE_TAG_WIDTH) ) icache_req_if(); assign icache_req_valid = icache_req_if.valid; @@ -98,7 +98,7 @@ module VX_pipeline #( VX_icache_rsp_if #( .WORD_SIZE (4), - .TAG_WIDTH (`ICORE_TAG_WIDTH) + .TAG_WIDTH (`ICACHE_CORE_TAG_WIDTH) ) icache_rsp_if(); assign icache_rsp_if.valid = icache_rsp_valid; @@ -108,18 +108,18 @@ module VX_pipeline #( /////////////////////////////////////////////////////////////////////////// - VX_cmt_to_csr_if #( - .SIZE ($clog2(3*`NUM_THREADS+1)) - ) cmt_to_csr_if(); - + VX_fetch_to_csr_if fetch_to_csr_if(); + VX_cmt_to_csr_if cmt_to_csr_if(); VX_decode_if decode_if(); VX_branch_ctl_if branch_ctl_if(); VX_warp_ctl_if warp_ctl_if(); VX_ifetch_rsp_if ifetch_rsp_if(); VX_alu_req_if alu_req_if(); VX_lsu_req_if lsu_req_if(); - VX_csr_req_if csr_req_if(); + VX_csr_req_if csr_req_if(); +`ifdef EXT_F_ENABLE VX_fpu_req_if fpu_req_if(); +`endif VX_gpu_req_if gpu_req_if(); VX_writeback_if writeback_if(); VX_wstall_if wstall_if(); @@ -128,7 +128,9 @@ module VX_pipeline #( VX_commit_if ld_commit_if(); VX_commit_if st_commit_if(); VX_commit_if csr_commit_if(); +`ifdef EXT_F_ENABLE VX_commit_if fpu_commit_if(); +`endif VX_commit_if gpu_commit_if(); `ifdef PERF_ENABLE @@ -154,6 +156,7 @@ module VX_pipeline #( .warp_ctl_if (warp_ctl_if), .branch_ctl_if (branch_ctl_if), .ifetch_rsp_if (ifetch_rsp_if), + .fetch_to_csr_if(fetch_to_csr_if), .busy (busy) ); @@ -186,7 +189,9 @@ module VX_pipeline #( .alu_req_if (alu_req_if), .lsu_req_if (lsu_req_if), .csr_req_if (csr_req_if), + `ifdef EXT_F_ENABLE .fpu_req_if (fpu_req_if), + `endif .gpu_req_if (gpu_req_if) ); @@ -206,12 +211,15 @@ module VX_pipeline #( .dcache_req_if (dcache_req_if), .dcache_rsp_if (dcache_rsp_if), - .cmt_to_csr_if (cmt_to_csr_if), + .cmt_to_csr_if (cmt_to_csr_if), + .fetch_to_csr_if(fetch_to_csr_if), .alu_req_if (alu_req_if), .lsu_req_if (lsu_req_if), .csr_req_if (csr_req_if), + `ifdef EXT_F_ENABLE .fpu_req_if (fpu_req_if), + `endif .gpu_req_if (gpu_req_if), .warp_ctl_if (warp_ctl_if), @@ -220,7 +228,9 @@ module VX_pipeline #( .ld_commit_if (ld_commit_if), .st_commit_if (st_commit_if), .csr_commit_if (csr_commit_if), + `ifdef EXT_F_ENABLE .fpu_commit_if (fpu_commit_if), + `endif .gpu_commit_if (gpu_commit_if), .busy (busy) @@ -236,7 +246,9 @@ module VX_pipeline #( .ld_commit_if (ld_commit_if), .st_commit_if (st_commit_if), .csr_commit_if (csr_commit_if), + `ifdef EXT_F_ENABLE .fpu_commit_if (fpu_commit_if), + `endif .gpu_commit_if (gpu_commit_if), .writeback_if (writeback_if), diff --git a/hw/rtl/VX_platform.vh b/hw/rtl/VX_platform.vh index 9c1ae729..38ccd4fa 100644 --- a/hw/rtl/VX_platform.vh +++ b/hw/rtl/VX_platform.vh @@ -1,10 +1,16 @@ `ifndef VX_PLATFORM `define VX_PLATFORM +`ifndef SYNTHESIS +`include "util_dpi.vh" +`endif + `include "VX_scope.vh" /////////////////////////////////////////////////////////////////////////////// +`ifndef SYNTHESIS + `ifndef NDEBUG `define DEBUG_BLOCK(x) /* verilator lint_off UNUSED */ \ x \ @@ -13,9 +19,9 @@ `define DEBUG_BLOCK(x) `endif -`define DEBUG_BEGIN /* verilator lint_off UNUSED */ +`define IGNORE_UNUSED_BEGIN /* verilator lint_off UNUSED */ -`define DEBUG_END /* verilator lint_on UNUSED */ +`define IGNORE_UNUSED_END /* verilator lint_on UNUSED */ `define IGNORE_WARNINGS_BEGIN /* verilator lint_off UNUSED */ \ /* verilator lint_off PINCONNECTEMPTY */ \ @@ -23,7 +29,8 @@ /* verilator lint_off UNOPTFLAT */ \ /* verilator lint_off UNDRIVEN */ \ /* verilator lint_off DECLFILENAME */ \ - /* verilator lint_off IMPLICIT */ + /* verilator lint_off IMPLICIT */ \ + /* verilator lint_off IMPORTSTAR */ `define IGNORE_WARNINGS_END /* verilator lint_on UNUSED */ \ /* verilator lint_on PINCONNECTEMPTY */ \ @@ -31,7 +38,8 @@ /* verilator lint_on UNOPTFLAT */ \ /* verilator lint_on UNDRIVEN */ \ /* verilator lint_on DECLFILENAME */ \ - /* verilator lint_on IMPLICIT */ + /* verilator lint_on IMPLICIT */ \ + /* verilator lint_on IMPORTSTAR */ `define UNUSED_PARAM(x) /* verilator lint_off UNUSED */ \ localparam __``x = x; \ @@ -43,7 +51,11 @@ . x () \ /* verilator lint_on PINCONNECTEMPTY */ -`define STRINGIFY(x) `"x`" +`define ERROR(msg) \ + $error msg + +`define ASSERT(cond, msg) \ + assert(cond) else $error msg `define STATIC_ASSERT(cond, msg) \ generate \ @@ -51,41 +63,61 @@ endgenerate `define RUNTIME_ASSERT(cond, msg) \ - always @(posedge clk) \ + always @(posedge clk) begin \ assert(cond) else $error msg; \ + end `define TRACING_ON /* verilator tracing_on */ `define TRACING_OFF /* verilator tracing_off */ -`define RESET_RELAY(signal) \ - wire signal; \ - VX_reset_relay __``signal ( \ - .clk (clk), \ - .reset (reset), \ - .reset_o (signal) \ - ) +`else // SYNTHESIS + +`define DEBUG_BLOCK(x) +`define IGNORE_UNUSED_BEGIN +`define IGNORE_UNUSED_END +`define IGNORE_WARNINGS_BEGIN +`define IGNORE_WARNINGS_END +`define UNUSED_PARAM(x) +`define UNUSED_VAR(x) +`define UNUSED_PIN(x) . x () +`define ERROR(msg) +`define ASSERT(cond, msg) if (cond); +`define STATIC_ASSERT(cond, msg) +`define RUNTIME_ASSERT(cond, msg) +`define TRACING_ON +`define TRACING_OFF + +`endif // SYNTHESIS /////////////////////////////////////////////////////////////////////////////// +`ifdef QUARTUS `define USE_FAST_BRAM (* ramstyle = "MLAB, no_rw_check" *) `define NO_RW_RAM_CHECK (* altera_attribute = "-name add_pass_through_logic_to_inferred_rams off" *) `define DISABLE_BRAM (* ramstyle = "logic" *) +`define PRESERVE_REG (* preserve *) +`else +`define USE_FAST_BRAM +`define NO_RW_RAM_CHECK +`define DISABLE_BRAM +`define PRESERVE_REG +`endif /////////////////////////////////////////////////////////////////////////////// +`define STRINGIFY(x) `"x`" + `define CLOG2(x) $clog2(x) `define FLOG2(x) ($clog2(x) - (((1 << $clog2(x)) > (x)) ? 1 : 0)) `define LOG2UP(x) (((x) > 1) ? $clog2(x) : 1) `define ISPOW2(x) (((x) != 0) && (0 == ((x) & ((x) - 1)))) -`define ABS(x) (($signed(x) < 0) ? (-$signed(x)) : x); +`define ABS(x) (($signed(x) < 0) ? (-$signed(x)) : (x)); -`define MIN(x, y) ((x < y) ? (x) : (y)) -`define MAX(x, y) ((x > y) ? (x) : (y)) +`define MIN(x, y) (((x) < (y)) ? (x) : (y)) +`define MAX(x, y) (((x) > (y)) ? (x) : (y)) -`define UP(x) (((x) > 0) ? x : 1) - -`define SAFE_RNG(h, l) `MAX(h,l) : l +`define UP(x) (((x) > 0) ? (x) : 1) `define RTRIM(x, s) x[$bits(x)-1:($bits(x)-s)] @@ -112,25 +144,41 @@ end \ $write("}") -`define PRINT_ARRAY1D(a, m) \ - $write("{"); \ +`define TRACE_ARRAY1D(a, m) \ + dpi_trace("{"); \ for (integer i = (m-1); i >= 0; --i) begin \ - if (i != (m-1)) $write(", "); \ - $write("0x%0h", a[i]); \ + if (i != (m-1)) dpi_trace(", "); \ + dpi_trace("0x%0h", a[i]); \ end \ - $write("}"); \ + dpi_trace("}"); \ -`define PRINT_ARRAY2D(a, m, n) \ - $write("{"); \ +`define TRACE_ARRAY2D(a, m, n) \ + dpi_trace("{"); \ for (integer i = n-1; i >= 0; --i) begin \ - if (i != (n-1)) $write(", "); \ - $write("{"); \ + if (i != (n-1)) dpi_trace(", "); \ + dpi_trace("{"); \ for (integer j = (m-1); j >= 0; --j) begin \ - if (j != (m-1)) $write(", "); \ - $write("0x%0h", a[i][j]); \ + if (j != (m-1)) dpi_trace(", "); \ + dpi_trace("0x%0h", a[i][j]); \ end \ - $write("}"); \ + dpi_trace("}"); \ end \ - $write("}") + dpi_trace("}") + +`define RESET_RELAY(signal) \ + wire signal; \ + VX_reset_relay __``signal ( \ + .clk (clk), \ + .reset (reset), \ + .reset_o (signal) \ + ) + +`define POP_COUNT(out, in) \ + VX_popcount #( \ + .N ($bits(in)) \ + ) __``out ( \ + .in_i (in), \ + .cnt_o (out) \ + ) `endif \ No newline at end of file diff --git a/hw/rtl/VX_print_instr.vh b/hw/rtl/VX_print_instr.vh index 88d47707..5b9aa63a 100644 --- a/hw/rtl/VX_print_instr.vh +++ b/hw/rtl/VX_print_instr.vh @@ -7,132 +7,141 @@ task print_ex_type ( input [`EX_BITS-1:0] ex_type ); case (ex_type) - `EX_ALU: $write("ALU"); - `EX_LSU: $write("LSU"); - `EX_CSR: $write("CSR"); - `EX_FPU: $write("FPU"); - `EX_GPU: $write("GPU"); - default: $write("NOP"); + `EX_ALU: dpi_trace("ALU"); + `EX_LSU: dpi_trace("LSU"); + `EX_CSR: dpi_trace("CSR"); + `EX_FPU: dpi_trace("FPU"); + `EX_GPU: dpi_trace("GPU"); + default: dpi_trace("NOP"); endcase endtask task print_ex_op ( input [`EX_BITS-1:0] ex_type, - input [`OP_BITS-1:0] op_type, - input [`MOD_BITS-1:0] op_mod + input [`INST_OP_BITS-1:0] op_type, + input [`INST_MOD_BITS-1:0] op_mod ); case (ex_type) `EX_ALU: begin - if (`ALU_IS_BR(op_mod)) begin - case (`BR_BITS'(op_type)) - `BR_EQ: $write("BEQ"); - `BR_NE: $write("BNE"); - `BR_LT: $write("BLT"); - `BR_GE: $write("BGE"); - `BR_LTU: $write("BLTU"); - `BR_GEU: $write("BGEU"); - `BR_JAL: $write("JAL"); - `BR_JALR: $write("JALR"); - `BR_ECALL: $write("ECALL"); - `BR_EBREAK:$write("EBREAK"); - `BR_MRET: $write("MRET"); - `BR_SRET: $write("SRET"); - `BR_DRET: $write("DRET"); - default: $write("?"); + if (`INST_ALU_IS_BR(op_mod)) begin + case (`INST_BR_BITS'(op_type)) + `INST_BR_EQ: dpi_trace("BEQ"); + `INST_BR_NE: dpi_trace("BNE"); + `INST_BR_LT: dpi_trace("BLT"); + `INST_BR_GE: dpi_trace("BGE"); + `INST_BR_LTU: dpi_trace("BLTU"); + `INST_BR_GEU: dpi_trace("BGEU"); + `INST_BR_JAL: dpi_trace("JAL"); + `INST_BR_JALR: dpi_trace("JALR"); + `INST_BR_ECALL: dpi_trace("ECALL"); + `INST_BR_EBREAK:dpi_trace("EBREAK"); + `INST_BR_MRET: dpi_trace("MRET"); + `INST_BR_SRET: dpi_trace("SRET"); + `INST_BR_DRET: dpi_trace("DRET"); + default: dpi_trace("?"); endcase - end else if (`ALU_IS_MUL(op_mod)) begin - case (`MUL_BITS'(op_type)) - `MUL_MUL: $write("MUL"); - `MUL_MULH: $write("MULH"); - `MUL_MULHSU:$write("MULHSU"); - `MUL_MULHU: $write("MULHU"); - `MUL_DIV: $write("DIV"); - `MUL_DIVU: $write("DIVU"); - `MUL_REM: $write("REM"); - `MUL_REMU: $write("REMU"); - default: $write("?"); + end else if (`INST_ALU_IS_MUL(op_mod)) begin + case (`INST_MUL_BITS'(op_type)) + `INST_MUL_MUL: dpi_trace("MUL"); + `INST_MUL_MULH: dpi_trace("MULH"); + `INST_MUL_MULHSU:dpi_trace("MULHSU"); + `INST_MUL_MULHU: dpi_trace("MULHU"); + `INST_MUL_DIV: dpi_trace("DIV"); + `INST_MUL_DIVU: dpi_trace("DIVU"); + `INST_MUL_REM: dpi_trace("REM"); + `INST_MUL_REMU: dpi_trace("REMU"); + default: dpi_trace("?"); endcase end else begin - case (`ALU_BITS'(op_type)) - `ALU_ADD: $write("ADD"); - `ALU_SUB: $write("SUB"); - `ALU_SLL: $write("SLL"); - `ALU_SRL: $write("SRL"); - `ALU_SRA: $write("SRA"); - `ALU_SLT: $write("SLT"); - `ALU_SLTU: $write("SLTU"); - `ALU_XOR: $write("XOR"); - `ALU_OR: $write("OR"); - `ALU_AND: $write("AND"); - `ALU_LUI: $write("LUI"); - `ALU_AUIPC: $write("AUIPC"); - default: $write("?"); + case (`INST_ALU_BITS'(op_type)) + `INST_ALU_ADD: dpi_trace("ADD"); + `INST_ALU_SUB: dpi_trace("SUB"); + `INST_ALU_SLL: dpi_trace("SLL"); + `INST_ALU_SRL: dpi_trace("SRL"); + `INST_ALU_SRA: dpi_trace("SRA"); + `INST_ALU_SLT: dpi_trace("SLT"); + `INST_ALU_SLTU: dpi_trace("SLTU"); + `INST_ALU_XOR: dpi_trace("XOR"); + `INST_ALU_OR: dpi_trace("OR"); + `INST_ALU_AND: dpi_trace("AND"); + `INST_ALU_LUI: dpi_trace("LUI"); + `INST_ALU_AUIPC: dpi_trace("AUIPC"); + default: dpi_trace("?"); endcase end end `EX_LSU: begin - case (`LSU_BITS'(op_type)) - `LSU_LB: $write("LB"); - `LSU_LH: $write("LH"); - `LSU_LW: $write("LW"); - `LSU_LBU:$write("LBU"); - `LSU_LHU:$write("LHU"); - `LSU_SB: $write("SB"); - `LSU_SH: $write("SH"); - `LSU_SW: $write("SW"); - default: $write("?"); - endcase + if (op_mod == 0) begin + case (`INST_LSU_BITS'(op_type)) + `INST_LSU_LB: dpi_trace("LB"); + `INST_LSU_LH: dpi_trace("LH"); + `INST_LSU_LW: dpi_trace("LW"); + `INST_LSU_LBU:dpi_trace("LBU"); + `INST_LSU_LHU:dpi_trace("LHU"); + `INST_LSU_SB: dpi_trace("SB"); + `INST_LSU_SH: dpi_trace("SH"); + `INST_LSU_SW: dpi_trace("SW"); + default: dpi_trace("?"); + endcase + end else if (op_mod == 1) begin + case (`INST_FENCE_BITS'(op_type)) + `INST_FENCE_D: dpi_trace("DFENCE"); + `INST_FENCE_I: dpi_trace("IFENCE"); + default: dpi_trace("?"); + endcase + end end `EX_CSR: begin - case (`CSR_BITS'(op_type)) - `CSR_RW: $write("CSRW"); - `CSR_RS: $write("CSRS"); - `CSR_RC: $write("CSRC"); - default: $write("?"); + case (`INST_CSR_BITS'(op_type)) + `INST_CSR_RW: dpi_trace("CSRW"); + `INST_CSR_RS: dpi_trace("CSRS"); + `INST_CSR_RC: dpi_trace("CSRC"); + default: dpi_trace("?"); endcase end `EX_FPU: begin - case (`FPU_BITS'(op_type)) - `FPU_ADD: $write("ADD"); - `FPU_SUB: $write("SUB"); - `FPU_MUL: $write("MUL"); - `FPU_DIV: $write("DIV"); - `FPU_SQRT: $write("SQRT"); - `FPU_MADD: $write("MADD"); - `FPU_NMSUB: $write("NMSUB"); - `FPU_NMADD: $write("NMADD"); - `FPU_CVTWS: $write("CVTWS"); - `FPU_CVTWUS:$write("CVTWUS"); - `FPU_CVTSW: $write("CVTSW"); - `FPU_CVTSWU:$write("CVTSWU"); - `FPU_CLASS: $write("CLASS"); - `FPU_CMP: $write("CMP"); - `FPU_MISC: begin + case (`INST_FPU_BITS'(op_type)) + `INST_FPU_ADD: dpi_trace("ADD"); + `INST_FPU_SUB: dpi_trace("SUB"); + `INST_FPU_MUL: dpi_trace("MUL"); + `INST_FPU_DIV: dpi_trace("DIV"); + `INST_FPU_SQRT: dpi_trace("SQRT"); + `INST_FPU_MADD: dpi_trace("MADD"); + `INST_FPU_NMSUB: dpi_trace("NMSUB"); + `INST_FPU_NMADD: dpi_trace("NMADD"); + `INST_FPU_CVTWS: dpi_trace("CVTWS"); + `INST_FPU_CVTWUS:dpi_trace("CVTWUS"); + `INST_FPU_CVTSW: dpi_trace("CVTSW"); + `INST_FPU_CVTSWU:dpi_trace("CVTSWU"); + `INST_FPU_CLASS: dpi_trace("CLASS"); + `INST_FPU_CMP: dpi_trace("CMP"); + `INST_FPU_MISC: begin case (op_mod) - 0: $write("SGNJ"); - 1: $write("SGNJN"); - 2: $write("SGNJX"); - 3: $write("MIN"); - 4: $write("MAX"); - 5: $write("MVXW"); - 6: $write("MVWX"); + 0: dpi_trace("SGNJ"); + 1: dpi_trace("SGNJN"); + 2: dpi_trace("SGNJX"); + 3: dpi_trace("MIN"); + 4: dpi_trace("MAX"); + 5: dpi_trace("MVXW"); + 6: dpi_trace("MVWX"); endcase end - default: $write("?"); + default: dpi_trace("?"); endcase end `EX_GPU: begin - case (`GPU_BITS'(op_type)) - `GPU_TMC: $write("TMC"); - `GPU_WSPAWN:$write("WSPAWN"); - `GPU_SPLIT: $write("SPLIT"); - `GPU_JOIN: $write("JOIN"); - `GPU_BAR: $write("BAR"); - `GPU_TEX: $write("TEX"); - default: $write("?"); + case (`INST_GPU_BITS'(op_type)) + `INST_GPU_TMC: dpi_trace("TMC"); + `INST_GPU_WSPAWN:dpi_trace("WSPAWN"); + `INST_GPU_SPLIT: dpi_trace("SPLIT"); + `INST_GPU_JOIN: dpi_trace("JOIN"); + `INST_GPU_BAR: dpi_trace("BAR"); + `INST_GPU_PRED: dpi_trace("PRED"); + `INST_GPU_TEX: dpi_trace("TEX"); + default: dpi_trace("?"); endcase end - default: $write("?"); + default: dpi_trace("?"); endcase endtask diff --git a/hw/rtl/VX_scoreboard.sv b/hw/rtl/VX_scoreboard.sv new file mode 100644 index 00000000..9503ecdf --- /dev/null +++ b/hw/rtl/VX_scoreboard.sv @@ -0,0 +1,84 @@ +`include "VX_define.vh" + +module VX_scoreboard #( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, + + VX_ibuffer_if.scoreboard ibuffer_if, + VX_writeback_if.scoreboard writeback_if +); + reg [`NUM_WARPS-1:0][`NUM_REGS-1:0] inuse_regs, inuse_regs_n; + + wire reserve_reg = ibuffer_if.valid && ibuffer_if.ready && ibuffer_if.wb; + + wire release_reg = writeback_if.valid && writeback_if.ready && writeback_if.eop; + + always @(*) begin + inuse_regs_n = inuse_regs; + if (reserve_reg) begin + inuse_regs_n[ibuffer_if.wid][ibuffer_if.rd] = 1; + end + if (release_reg) begin + inuse_regs_n[writeback_if.wid][writeback_if.rd] = 0; + end + end + + always @(posedge clk) begin + if (reset) begin + inuse_regs <= '0; + end else begin + inuse_regs <= inuse_regs_n; + end + end + + reg deq_inuse_rd, deq_inuse_rs1, deq_inuse_rs2, deq_inuse_rs3; + + always @(posedge clk) begin + deq_inuse_rd <= inuse_regs_n[ibuffer_if.wid_n][ibuffer_if.rd_n]; + deq_inuse_rs1 <= inuse_regs_n[ibuffer_if.wid_n][ibuffer_if.rs1_n]; + deq_inuse_rs2 <= inuse_regs_n[ibuffer_if.wid_n][ibuffer_if.rs2_n]; + deq_inuse_rs3 <= inuse_regs_n[ibuffer_if.wid_n][ibuffer_if.rs3_n]; + end + + assign writeback_if.ready = 1'b1; + + assign ibuffer_if.ready = ~(deq_inuse_rd + | deq_inuse_rs1 + | deq_inuse_rs2 + | deq_inuse_rs3); + + `UNUSED_VAR (writeback_if.PC) + + reg [31:0] deadlock_ctr; + wire [31:0] deadlock_timeout = 10000 * (1 ** (`L2_ENABLE + `L3_ENABLE)); + always @(posedge clk) begin + if (reset) begin + deadlock_ctr <= 0; + end else begin + `ifdef DBG_PRINT_PIPELINE + if (ibuffer_if.valid && ~ibuffer_if.ready) begin + dpi_trace("%d: *** core%0d-stall: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b\n", + $time, CORE_ID, ibuffer_if.wid, ibuffer_if.PC, ibuffer_if.rd, ibuffer_if.wb, + deq_inuse_rd, deq_inuse_rs1, deq_inuse_rs2, deq_inuse_rs3); + end + `endif + if (release_reg) begin + `ASSERT(inuse_regs[writeback_if.wid][writeback_if.rd] != 0, + ("%t: *** core%0d: invalid writeback register: wid=%0d, PC=%0h, rd=%0d", + $time, CORE_ID, writeback_if.wid, writeback_if.PC, writeback_if.rd)); + end + if (ibuffer_if.valid && ~ibuffer_if.ready) begin + deadlock_ctr <= deadlock_ctr + 1; + `ASSERT(deadlock_ctr < deadlock_timeout, + ("%t: *** core%0d-deadlock: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b", + $time, CORE_ID, ibuffer_if.wid, ibuffer_if.PC, ibuffer_if.rd, ibuffer_if.wb, + deq_inuse_rd, deq_inuse_rs1, deq_inuse_rs2, deq_inuse_rs3)); + end else if (ibuffer_if.valid && ibuffer_if.ready) begin + deadlock_ctr <= 0; + end + end + end + +endmodule \ No newline at end of file diff --git a/hw/rtl/VX_scoreboard.v b/hw/rtl/VX_scoreboard.v deleted file mode 100644 index 24ad1c37..00000000 --- a/hw/rtl/VX_scoreboard.v +++ /dev/null @@ -1,71 +0,0 @@ -`include "VX_define.vh" - -module VX_scoreboard #( - parameter CORE_ID = 0 -) ( - input wire clk, - input wire reset, - - VX_ibuffer_if ibuffer_if, - VX_writeback_if writeback_if, - output wire delay -); - reg [`NUM_WARPS-1:0][`NUM_REGS-1:0] inuse_regs, inuse_regs_n; - - reg [`NUM_REGS-1:0] deq_inuse_regs; - - assign delay = |(deq_inuse_regs & ibuffer_if.used_regs); - - wire reserve_reg = ibuffer_if.valid && ibuffer_if.ready && ibuffer_if.wb; - - wire release_reg = writeback_if.valid && writeback_if.ready && writeback_if.eop; - - always @(*) begin - inuse_regs_n = inuse_regs; - if (reserve_reg) begin - inuse_regs_n[ibuffer_if.wid][ibuffer_if.rd] = 1; - end - if (release_reg) begin - inuse_regs_n[writeback_if.wid][writeback_if.rd] = 0; - end - end - - always @(posedge clk) begin - if (reset) begin - inuse_regs <= '0; - end else begin - inuse_regs <= inuse_regs_n; - end - deq_inuse_regs <= inuse_regs_n[ibuffer_if.wid_n]; - end - - reg [31:0] deadlock_ctr; - wire [31:0] deadlock_timeout = 10000 * (1 ** (`L2_ENABLE + `L3_ENABLE)); - always @(posedge clk) begin - if (reset) begin - deadlock_ctr <= 0; - end else begin - `ifdef DBG_PRINT_PIPELINE - if (ibuffer_if.valid && ~ibuffer_if.ready) begin - $display("%t: *** core%0d-stall: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b", - $time, CORE_ID, ibuffer_if.wid, ibuffer_if.PC, ibuffer_if.rd, ibuffer_if.wb, - deq_inuse_regs[ibuffer_if.rd], deq_inuse_regs[ibuffer_if.rs1], deq_inuse_regs[ibuffer_if.rs2], deq_inuse_regs[ibuffer_if.rs3]); - end - `endif - if (release_reg) begin - assert(inuse_regs[writeback_if.wid][writeback_if.rd] != 0) - else $error("%t: *** core%0d: invalid writeback register: wid=%0d, PC=%0h, rd=%0d", - $time, CORE_ID, writeback_if.wid, writeback_if.PC, writeback_if.rd); - end - if (ibuffer_if.valid && ~ibuffer_if.ready) begin - deadlock_ctr <= deadlock_ctr + 1; - assert(deadlock_ctr < deadlock_timeout) else $error("%t: *** core%0d-deadlock: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b", - $time, CORE_ID, ibuffer_if.wid, ibuffer_if.PC, ibuffer_if.rd, ibuffer_if.wb, - deq_inuse_regs[ibuffer_if.rd], deq_inuse_regs[ibuffer_if.rs1], deq_inuse_regs[ibuffer_if.rs2], deq_inuse_regs[ibuffer_if.rs3]); - end else if (ibuffer_if.valid && ibuffer_if.ready) begin - deadlock_ctr <= 0; - end - end - end - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_smem_arb.v b/hw/rtl/VX_smem_arb.sv similarity index 96% rename from hw/rtl/VX_smem_arb.v rename to hw/rtl/VX_smem_arb.sv index 45033f5c..24d64ff1 100644 --- a/hw/rtl/VX_smem_arb.v +++ b/hw/rtl/VX_smem_arb.sv @@ -8,12 +8,12 @@ module VX_smem_arb #( parameter TAG_SEL_IDX = 0, parameter BUFFERED_REQ = 0, parameter BUFFERED_RSP = 0, - parameter TYPE = "R", + parameter TYPE = "P", - localparam ADDR_WIDTH = (32-`CLOG2(DATA_SIZE)), - localparam DATA_WIDTH = (8 * DATA_SIZE), - localparam LOG_NUM_REQS = `CLOG2(NUM_REQS), - localparam TAG_OUT_WIDTH = TAG_IN_WIDTH - LOG_NUM_REQS + parameter ADDR_WIDTH = (32-`CLOG2(DATA_SIZE)), + parameter DATA_WIDTH = (8 * DATA_SIZE), + parameter LOG_NUM_REQS = `CLOG2(NUM_REQS), + parameter TAG_OUT_WIDTH = TAG_IN_WIDTH - LOG_NUM_REQS ) ( input wire clk, input wire reset, diff --git a/hw/rtl/VX_types.vh b/hw/rtl/VX_types.vh deleted file mode 100644 index c5b1dce6..00000000 --- a/hw/rtl/VX_types.vh +++ /dev/null @@ -1,59 +0,0 @@ -`ifndef VX_TYPES -`define VX_TYPES - -`include "VX_define.vh" - -typedef struct packed { - logic is_normal; - logic is_zero; - logic is_subnormal; - logic is_inf; - logic is_nan; - logic is_quiet; - logic is_signaling; -} fp_type_t; - -typedef struct packed { - logic NV; // 4-Invalid - logic DZ; // 3-Divide by zero - logic OF; // 2-Overflow - logic UF; // 1-Underflow - logic NX; // 0-Inexact -} fflags_t; - -`define FFG_BITS $bits(fflags_t) - -typedef struct packed { - logic valid; - logic [`NUM_THREADS-1:0] tmask; -} gpu_tmc_t; - -`define GPU_TMC_BITS (1+`NUM_THREADS) - -typedef struct packed { - logic valid; - logic [`NUM_WARPS-1:0] wmask; - logic [31:0] pc; -} gpu_wspawn_t; - -`define GPU_WSPAWN_BITS (1+`NUM_WARPS+32) - -typedef struct packed { - logic valid; - logic diverged; - logic [`NUM_THREADS-1:0] then_mask; - logic [`NUM_THREADS-1:0] else_mask; - logic [31:0] pc; -} gpu_split_t; - -`define GPU_SPLIT_BITS (1+1+`NUM_THREADS+`NUM_THREADS+32) - -typedef struct packed { - logic valid; - logic [`NB_BITS-1:0] id; - logic [`NW_BITS-1:0] size_m1; -} gpu_barrier_t; - -`define GPU_BARRIER_BITS (1+`NB_BITS+`NW_BITS) - -`endif \ No newline at end of file diff --git a/hw/rtl/VX_warp_sched.sv b/hw/rtl/VX_warp_sched.sv new file mode 100644 index 00000000..9495c001 --- /dev/null +++ b/hw/rtl/VX_warp_sched.sv @@ -0,0 +1,246 @@ +`include "VX_define.vh" + +module VX_warp_sched #( + parameter CORE_ID = 0 +) ( + `SCOPE_IO_VX_warp_sched + + input wire clk, + input wire reset, + + VX_warp_ctl_if.slave warp_ctl_if, + VX_wstall_if.slave wstall_if, + VX_join_if.slave join_if, + VX_branch_ctl_if.slave branch_ctl_if, + + VX_ifetch_req_if.master ifetch_req_if, + + VX_fetch_to_csr_if.master fetch_to_csr_if, + + output wire busy +); + + `UNUSED_PARAM (CORE_ID) + + wire join_else; + wire [31:0] join_pc; + wire [`NUM_THREADS-1:0] join_tmask; + + reg [`NUM_WARPS-1:0] active_warps, active_warps_n; // real active warps (updated when a warp is activated or disabled) + reg [`NUM_WARPS-1:0] stalled_warps; // asserted when a branch/gpgpu instructions are issued + + reg [`NUM_WARPS-1:0][`NUM_THREADS-1:0] thread_masks; + reg [`NUM_WARPS-1:0][31:0] warp_pcs; + + // barriers + reg [`NUM_BARRIERS-1:0][`NUM_WARPS-1:0] barrier_masks; // warps waiting on barrier + wire reached_barrier_limit; // the expected number of warps reached the barrier + + // wspawn + reg [31:0] wspawn_pc; + reg [`NUM_WARPS-1:0] use_wspawn; + + wire [`NW_BITS-1:0] schedule_wid; + wire [`NUM_THREADS-1:0] schedule_tmask; + wire [31:0] schedule_pc; + wire schedule_valid; + wire warp_scheduled; + + wire ifetch_req_fire = ifetch_req_if.valid && ifetch_req_if.ready; + + wire tmc_active = (warp_ctl_if.tmc.tmask != 0); + + always @(*) begin + active_warps_n = active_warps; + if (warp_ctl_if.valid && warp_ctl_if.wspawn.valid) begin + active_warps_n = warp_ctl_if.wspawn.wmask; + end + if (warp_ctl_if.valid && warp_ctl_if.tmc.valid) begin + active_warps_n[warp_ctl_if.wid] = tmc_active; + end + end + + always @(posedge clk) begin + if (reset) begin + barrier_masks <= 0; + use_wspawn <= 0; + stalled_warps <= 0; + warp_pcs <= '0; + active_warps <= '0; + thread_masks <= '0; + + // activate first warp + warp_pcs[0] <= `STARTUP_ADDR; + active_warps[0] <= '1; + thread_masks[0] <= '1; + end else begin + if (warp_ctl_if.valid && warp_ctl_if.wspawn.valid) begin + use_wspawn <= warp_ctl_if.wspawn.wmask & (~`NUM_WARPS'(1)); + wspawn_pc <= warp_ctl_if.wspawn.pc; + end + + if (warp_ctl_if.valid && warp_ctl_if.barrier.valid) begin + stalled_warps[warp_ctl_if.wid] <= 0; + if (reached_barrier_limit) begin + barrier_masks[warp_ctl_if.barrier.id] <= 0; + end else begin + barrier_masks[warp_ctl_if.barrier.id][warp_ctl_if.wid] <= 1; + end + end + + if (warp_ctl_if.valid && warp_ctl_if.tmc.valid) begin + thread_masks[warp_ctl_if.wid] <= warp_ctl_if.tmc.tmask; + stalled_warps[warp_ctl_if.wid] <= 0; + end + + if (warp_ctl_if.valid && warp_ctl_if.split.valid) begin + stalled_warps[warp_ctl_if.wid] <= 0; + if (warp_ctl_if.split.diverged) begin + thread_masks[warp_ctl_if.wid] <= warp_ctl_if.split.then_tmask; + end + end + + // Branch + if (branch_ctl_if.valid) begin + if (branch_ctl_if.taken) begin + warp_pcs[branch_ctl_if.wid] <= branch_ctl_if.dest; + end + stalled_warps[branch_ctl_if.wid] <= 0; + end + + if (warp_scheduled) begin + // stall the warp until decode stage + stalled_warps[schedule_wid] <= 1; + + // release wspawn + use_wspawn[schedule_wid] <= 0; + if (use_wspawn[schedule_wid]) begin + thread_masks[schedule_wid] <= 1; + end + end + + if (ifetch_req_fire) begin + warp_pcs[ifetch_req_if.wid] <= ifetch_req_if.PC + 4; + end + + if (wstall_if.valid) begin + stalled_warps[wstall_if.wid] <= wstall_if.stalled; + end + + // join handling + if (join_if.valid) begin + if (join_else) begin + warp_pcs[join_if.wid] <= join_pc; + end + thread_masks[join_if.wid] <= join_tmask; + end + + active_warps <= active_warps_n; + end + end + + // export thread mask register + assign fetch_to_csr_if.thread_masks = thread_masks; + + // calculate active barrier status + +`IGNORE_UNUSED_BEGIN + wire [`NW_BITS:0] active_barrier_count; +`IGNORE_UNUSED_END + wire [`NUM_WARPS-1:0] barrier_mask = barrier_masks[warp_ctl_if.barrier.id]; + `POP_COUNT(active_barrier_count, barrier_mask); + + assign reached_barrier_limit = (active_barrier_count[`NW_BITS-1:0] == warp_ctl_if.barrier.size_m1); + + reg [`NUM_WARPS-1:0] barrier_stalls; + always @(*) begin + barrier_stalls = barrier_masks[0]; + for (integer i = 1; i < `NUM_BARRIERS; ++i) begin + barrier_stalls |= barrier_masks[i]; + end + end + + // split/join stack management + + wire [(32+`NUM_THREADS)-1:0] ipdom_data [`NUM_WARPS-1:0]; + wire ipdom_index [`NUM_WARPS-1:0]; + + for (genvar i = 0; i < `NUM_WARPS; i++) begin + wire push = warp_ctl_if.valid + && warp_ctl_if.split.valid + && (i == warp_ctl_if.wid); + + wire pop = join_if.valid && (i == join_if.wid); + + wire [`NUM_THREADS-1:0] else_tmask = warp_ctl_if.split.else_tmask; + wire [`NUM_THREADS-1:0] orig_tmask = thread_masks[warp_ctl_if.wid]; + + wire [(32+`NUM_THREADS)-1:0] q_else = {warp_ctl_if.split.pc, else_tmask}; + wire [(32+`NUM_THREADS)-1:0] q_end = {32'b0, orig_tmask}; + + VX_ipdom_stack #( + .WIDTH (32+`NUM_THREADS), + .DEPTH (2 ** (`NT_BITS+1)) + ) ipdom_stack ( + .clk (clk), + .reset (reset), + .push (push), + .pop (pop), + .pair (warp_ctl_if.split.diverged), + .q1 (q_end), + .q2 (q_else), + .d (ipdom_data[i]), + .index (ipdom_index[i]), + `UNUSED_PIN (empty), + `UNUSED_PIN (full) + ); + end + + assign {join_pc, join_tmask} = ipdom_data[join_if.wid]; + assign join_else = ~ipdom_index[join_if.wid]; + + // schedule the next ready warp + + wire [`NUM_WARPS-1:0] ready_warps = active_warps & ~(stalled_warps | barrier_stalls); + + VX_lzc #( + .N (`NUM_WARPS) + ) wid_select ( + .in_i (ready_warps), + .cnt_o (schedule_wid), + .valid_o (schedule_valid) + ); + + wire [`NUM_WARPS-1:0][(`NUM_THREADS + 32)-1:0] schedule_data; + for (genvar i = 0; i < `NUM_WARPS; ++i) begin + assign schedule_data[i] = {(use_wspawn[i] ? `NUM_THREADS'(1) : thread_masks[i]), + (use_wspawn[i] ? wspawn_pc : warp_pcs[i])}; + end + + assign {schedule_tmask, schedule_pc} = schedule_data[schedule_wid]; + + wire stall_out = ~ifetch_req_if.ready && ifetch_req_if.valid; + + assign warp_scheduled = schedule_valid && ~stall_out; + + VX_pipe_register #( + .DATAW (1 + `NUM_THREADS + 32 + `NW_BITS), + .RESETW (1) + ) pipe_reg ( + .clk (clk), + .reset (reset), + .enable (!stall_out), + .data_in ({schedule_valid, schedule_tmask, schedule_pc, schedule_wid}), + .data_out ({ifetch_req_if.valid, ifetch_req_if.tmask, ifetch_req_if.PC, ifetch_req_if.wid}) + ); + + assign busy = (active_warps != 0); + + `SCOPE_ASSIGN (wsched_scheduled, warp_scheduled); + `SCOPE_ASSIGN (wsched_active_warps, active_warps); + `SCOPE_ASSIGN (wsched_stalled_warps, stalled_warps); + `SCOPE_ASSIGN (wsched_schedule_wid, schedule_wid); + `SCOPE_ASSIGN (wsched_schedule_tmask, schedule_tmask); + `SCOPE_ASSIGN (wsched_schedule_pc, schedule_pc); + +endmodule \ No newline at end of file diff --git a/hw/rtl/VX_warp_sched.v b/hw/rtl/VX_warp_sched.v deleted file mode 100644 index 03b8a9ce..00000000 --- a/hw/rtl/VX_warp_sched.v +++ /dev/null @@ -1,254 +0,0 @@ -`include "VX_define.vh" - -module VX_warp_sched #( - parameter CORE_ID = 0 -) ( - `SCOPE_IO_VX_warp_sched - - input wire clk, - input wire reset, - - VX_warp_ctl_if warp_ctl_if, - VX_wstall_if wstall_if, - VX_join_if join_if, - VX_branch_ctl_if branch_ctl_if, - - VX_ifetch_rsp_if ifetch_rsp_if, - VX_ifetch_req_if ifetch_req_if, - - output wire busy -); - - `UNUSED_PARAM (CORE_ID) - - wire join_else; - wire [31:0] join_pc; - wire [`NUM_THREADS-1:0] join_tm; - - reg [`NUM_WARPS-1:0] active_warps, active_warps_n; // real active warps (updated when a warp is activated or disabled) - reg [`NUM_WARPS-1:0] schedule_table, schedule_table_n; // enforces round-robin, barrier, and non-speculating branches - reg [`NUM_WARPS-1:0] stalled_warps; // asserted when a branch/gpgpu instructions are issued - - // Lock warp until instruction decode to resolve branches - reg [`NUM_WARPS-1:0] fetch_lock; - - reg [`NUM_THREADS-1:0] thread_masks [`NUM_WARPS-1:0]; - reg [31:0] warp_pcs [`NUM_WARPS-1:0]; - - // barriers - reg [`NUM_WARPS-1:0] barrier_stall_mask [`NUM_BARRIERS-1:0]; // warps waiting on barrier - wire reached_barrier_limit; // the expected number of warps reached the barrier - - // wspawn - reg [31:0] use_wspawn_pc; - reg [`NUM_WARPS-1:0] use_wspawn; - reg [`NW_BITS-1:0] scheduled_warp; - wire warp_scheduled; - - wire ifetch_rsp_fire = ifetch_rsp_if.valid && ifetch_rsp_if.ready; - - always @(*) begin - active_warps_n = active_warps; - if (warp_ctl_if.valid && warp_ctl_if.wspawn.valid) begin - active_warps_n = warp_ctl_if.wspawn.wmask; - end - if (warp_ctl_if.valid && warp_ctl_if.tmc.valid) begin - active_warps_n[warp_ctl_if.wid] = (warp_ctl_if.tmc.tmask != 0); - end - end - - always @(*) begin - schedule_table_n = schedule_table; - if (warp_ctl_if.valid && warp_ctl_if.tmc.valid) begin - schedule_table_n[warp_ctl_if.wid] = (warp_ctl_if.tmc.tmask != 0); - end - if (warp_scheduled) begin // remove scheduled warp (round-robin) - schedule_table_n[scheduled_warp] = 0; - end - end - - always @(posedge clk) begin - if (reset) begin - for (integer i = 0; i < `NUM_BARRIERS; i++) begin - barrier_stall_mask[i] <= 0; - end - - use_wspawn_pc <= 0; - use_wspawn <= 0; - warp_pcs[0] <= `STARTUP_ADDR; - active_warps[0] <= 1; // Activating first warp - schedule_table[0] <= 1; // set first warp as ready - thread_masks[0] <= 1; // Activating first thread in first warp - stalled_warps <= 0; - fetch_lock <= 0; - - for (integer i = 1; i < `NUM_WARPS; i++) begin - warp_pcs[i] <= 0; - active_warps[i] <= 0; - schedule_table[i] <= 0; - thread_masks[i] <= 0; - end - end else begin - if (warp_ctl_if.valid && warp_ctl_if.wspawn.valid) begin - use_wspawn <= warp_ctl_if.wspawn.wmask & (~`NUM_WARPS'(1)); - use_wspawn_pc <= warp_ctl_if.wspawn.pc; - end - - if (warp_ctl_if.valid && warp_ctl_if.barrier.valid) begin - stalled_warps[warp_ctl_if.wid] <= 0; - if (reached_barrier_limit) begin - barrier_stall_mask[warp_ctl_if.barrier.id] <= 0; - end else begin - barrier_stall_mask[warp_ctl_if.barrier.id][warp_ctl_if.wid] <= 1; - end - end else if (warp_ctl_if.valid && warp_ctl_if.tmc.valid) begin - thread_masks[warp_ctl_if.wid] <= warp_ctl_if.tmc.tmask; - stalled_warps[warp_ctl_if.wid] <= 0; - end else if (warp_ctl_if.valid && warp_ctl_if.split.valid) begin - stalled_warps[warp_ctl_if.wid] <= 0; - if (warp_ctl_if.split.diverged) begin - thread_masks[warp_ctl_if.wid] <= warp_ctl_if.split.then_mask; - end - end - - if (use_wspawn[scheduled_warp] && warp_scheduled) begin - use_wspawn[scheduled_warp] <= 0; - thread_masks[scheduled_warp] <= 1; - end - - // Stalling the scheduling of warps - if (wstall_if.valid) begin - stalled_warps[wstall_if.wid] <= 1; - end - - // Branch - if (branch_ctl_if.valid) begin - if (branch_ctl_if.taken) begin - warp_pcs[branch_ctl_if.wid] <= branch_ctl_if.dest; - end - stalled_warps[branch_ctl_if.wid] <= 0; - end - - // Lock warp until instruction decode to resolve branches - if (warp_scheduled) begin - fetch_lock[scheduled_warp] <= 1; - end - if (ifetch_rsp_fire) begin - fetch_lock[ifetch_rsp_if.wid] <= 0; - warp_pcs[ifetch_rsp_if.wid] <= ifetch_rsp_if.PC + 4; - end - - // join handling - if (join_if.valid) begin - if (join_else) begin - warp_pcs[join_if.wid] <= join_pc; - end - thread_masks[join_if.wid] <= join_tm; - end - - active_warps <= active_warps_n; - - // reset 'schedule_table' when it goes to zero - schedule_table <= (| schedule_table_n) ? schedule_table_n : active_warps_n; - end - end - - // calculate active barrier status - -`IGNORE_WARNINGS_BEGIN - wire [`NW_BITS:0] active_barrier_count; -`IGNORE_WARNINGS_END - assign active_barrier_count = $countones(barrier_stall_mask[warp_ctl_if.barrier.id]); - - assign reached_barrier_limit = (active_barrier_count[`NW_BITS-1:0] == warp_ctl_if.barrier.size_m1); - - reg [`NUM_WARPS-1:0] total_barrier_stall; - always @(*) begin - total_barrier_stall = barrier_stall_mask[0]; - for (integer i = 1; i < `NUM_BARRIERS; ++i) begin - total_barrier_stall |= barrier_stall_mask[i]; - end - end - - // split/join stack management - - wire [(1+32+`NUM_THREADS-1):0] ipdom [`NUM_WARPS-1:0]; - - for (genvar i = 0; i < `NUM_WARPS; i++) begin - wire push = warp_ctl_if.valid - && warp_ctl_if.split.valid - && (i == warp_ctl_if.wid); - - wire pop = join_if.valid && (i == join_if.wid); - - wire [`NUM_THREADS-1:0] else_mask = warp_ctl_if.split.diverged ? warp_ctl_if.split.else_mask : thread_masks[warp_ctl_if.wid]; - wire [(1+32+`NUM_THREADS-1):0] q_end = {1'b0, 32'b0, thread_masks[warp_ctl_if.wid]}; - wire [(1+32+`NUM_THREADS-1):0] q_else = {1'b1, warp_ctl_if.split.pc, else_mask}; - - VX_ipdom_stack #( - .WIDTH (1+32+`NUM_THREADS), - .DEPTH (2 ** (`NT_BITS+1)) - ) ipdom_stack ( - .clk (clk), - .reset (reset), - .push (push), - .pop (pop), - .q1 (q_end), - .q2 (q_else), - .d (ipdom[i]), - `UNUSED_PIN (empty), - `UNUSED_PIN (full) - ); - end - - assign {join_else, join_pc, join_tm} = ipdom [join_if.wid]; - - // calculate next warp schedule - - reg [`NUM_THREADS-1:0] thread_mask; - reg schedule_valid; - reg [31:0] warp_pc; - - wire [`NUM_WARPS-1:0] schedule_ready = schedule_table & ~(stalled_warps | total_barrier_stall | fetch_lock); - - always @(*) begin - schedule_valid = 0; - thread_mask = 'x; - warp_pc = 'x; - scheduled_warp = 'x; - for (integer i = 0; i < `NUM_WARPS; ++i) begin - if (schedule_ready[i]) begin - schedule_valid = 1; - thread_mask = use_wspawn[i] ? `NUM_THREADS'(1) : thread_masks[i]; - warp_pc = use_wspawn[i] ? use_wspawn_pc : warp_pcs[i]; - scheduled_warp = `NW_BITS'(i); - break; - end - end - end - - wire stall_out = ~ifetch_req_if.ready && ifetch_req_if.valid; - - assign warp_scheduled = schedule_valid && ~stall_out; - - VX_pipe_register #( - .DATAW (1 + `NUM_THREADS + 32 + `NW_BITS), - .RESETW (1) - ) pipe_reg ( - .clk (clk), - .reset (reset), - .enable (!stall_out), - .data_in ({warp_scheduled, thread_mask, warp_pc, scheduled_warp}), - .data_out ({ifetch_req_if.valid, ifetch_req_if.tmask, ifetch_req_if.PC, ifetch_req_if.wid}) - ); - - assign busy = (active_warps != 0); - - `SCOPE_ASSIGN (wsched_scheduled_warp, warp_scheduled); - `SCOPE_ASSIGN (wsched_active_warps, active_warps); - `SCOPE_ASSIGN (wsched_schedule_table, schedule_table); - `SCOPE_ASSIGN (wsched_schedule_ready, schedule_ready); - `SCOPE_ASSIGN (wsched_warp_to_schedule, scheduled_warp); - `SCOPE_ASSIGN (wsched_warp_pc, warp_pc); - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_writeback.sv b/hw/rtl/VX_writeback.sv new file mode 100644 index 00000000..f55c8401 --- /dev/null +++ b/hw/rtl/VX_writeback.sv @@ -0,0 +1,130 @@ +`include "VX_define.vh" + +module VX_writeback #( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, + + // inputs + VX_commit_if.slave alu_commit_if, + VX_commit_if.slave ld_commit_if, + VX_commit_if.slave csr_commit_if, + VX_commit_if.slave csr_commit_if, +`ifdef EXT_F_ENABLE + VX_commit_if.slave fpu_commit_if, +`endif + VX_commit_if.slave gpu_commit_if, + + // outputs + VX_writeback_if.master writeback_if +); + + `UNUSED_PARAM (CORE_ID) + + localparam DATAW = `NW_BITS + 32 + `NUM_THREADS + `NR_BITS + (`NUM_THREADS * 32) + 1; +`ifdef EXT_F_ENABLE +`ifdef EXT_TEX_ENABLE + localparam NUM_RSPS = 5; +`else + localparam NUM_RSPS = 4; +`endif +`else +`ifdef EXT_TEX_ENABLE + localparam NUM_RSPS = 4; +`else + localparam NUM_RSPS = 3; +`endif +`endif + + wire wb_valid; + wire [`NW_BITS-1:0] wb_wid; + wire [31:0] wb_PC; + wire [`NUM_THREADS-1:0] wb_tmask; + wire [`NR_BITS-1:0] wb_rd; + wire [`NUM_THREADS-1:0][31:0] wb_data; + wire wb_eop; + + wire [NUM_RSPS-1:0] rsp_valid; + wire [NUM_RSPS-1:0][DATAW-1:0] rsp_data; + wire [NUM_RSPS-1:0] rsp_ready; + wire stall; + + assign rsp_valid = { + csr_commit_if.valid && csr_commit_if.wb, + alu_commit_if.valid && alu_commit_if.wb, + `ifdef EXT_F_ENABLE + fpu_commit_if.valid && fpu_commit_if.wb, + `endif + ld_commit_if.valid && ld_commit_if.wb, + `ifdef EXT_TEX_ENABLE + gpu_commit_if.valid && gpu_commit_if.wb, + `ifend + }; + + assign rsp_data = { + {csr_commit_if.wid, csr_commit_if.PC, csr_commit_if.tmask, csr_commit_if.rd, csr_commit_if.data, csr_commit_if.eop}, + {alu_commit_if.wid, alu_commit_if.PC, alu_commit_if.tmask, alu_commit_if.rd, alu_commit_if.data, alu_commit_if.eop}, + `ifdef EXT_F_ENABLE + {fpu_commit_if.wid, fpu_commit_if.PC, fpu_commit_if.tmask, fpu_commit_if.rd, fpu_commit_if.data, fpu_commit_if.eop}, + `endif + { ld_commit_if.wid, ld_commit_if.PC, ld_commit_if.tmask, ld_commit_if.rd, ld_commit_if.data, ld_commit_if.eop}, + `ifdef EXT_TEX_ENABLE + {gpu_commit_if.wid, gpu_commit_if.PC, gpu_commit_if.tmask, gpu_commit_if.rd, gpu_commit_if.data, gpu_commit_if.eop}, + `endif + }; + + VX_stream_arbiter #( + .NUM_REQS (NUM_RSPS), + .DATAW (DATAW), + .TYPE ("P") + ) rsp_arb ( + .clk (clk), + .reset (reset), + .valid_in (rsp_valid), + .data_in (rsp_data), + .ready_in (rsp_ready), + .valid_out (wb_valid), + .data_out ({wb_wid, wb_PC, wb_tmask, wb_rd, wb_data, wb_eop}), + .ready_out (~stall) + ); + + assign ld_commit_if.ready = rsp_ready[0] || ~ld_commit_if.wb; +`ifdef EXT_F_ENABLE + assign fpu_commit_if.ready = rsp_ready[1] || ~fpu_commit_if.wb; + assign alu_commit_if.ready = rsp_ready[2] || ~alu_commit_if.wb; + assign csr_commit_if.ready = rsp_ready[3] || ~csr_commit_if.wb; +`ifdef EXT_TEX_ENABLE + assign gpu_commit_if.ready = rsp_ready[4] || ~gpu_commit_if.wb; +`endif +`else + assign alu_commit_if.ready = rsp_ready[1] || ~alu_commit_if.wb; + assign csr_commit_if.ready = rsp_ready[2] || ~csr_commit_if.wb; +`ifdef EXT_TEX_ENABLE + assign gpu_commit_if.ready = rsp_ready[3] || ~gpu_commit_if.wb; +`endif +`endif + + + assign stall = ~writeback_if.ready && writeback_if.valid; + + VX_pipe_register #( + .DATAW (1 + DATAW), + .RESETW (1) + ) pipe_reg ( + .clk (clk), + .reset (reset), + .enable (~stall), + .data_in ({wb_valid, wb_wid, wb_PC, wb_tmask, wb_rd, wb_data, wb_eop}), + .data_out ({writeback_if.valid, writeback_if.wid, writeback_if.PC, writeback_if.tmask, writeback_if.rd, writeback_if.data, writeback_if.eop}) + ); + + // special workaround to get RISC-V tests Pass/Fail status + reg [31:0] last_wb_value [`NUM_REGS-1:0] /* verilator public */; + always @(posedge clk) begin + if (writeback_if.valid && writeback_if.ready) begin + last_wb_value[writeback_if.rd] <= writeback_if.data[0]; + end + end + +endmodule \ No newline at end of file diff --git a/hw/rtl/VX_writeback.v b/hw/rtl/VX_writeback.v deleted file mode 100644 index 424dc147..00000000 --- a/hw/rtl/VX_writeback.v +++ /dev/null @@ -1,90 +0,0 @@ -`include "VX_define.vh" - -module VX_writeback #( - parameter CORE_ID = 0 -) ( - input wire clk, - input wire reset, - - // inputs - VX_commit_if alu_commit_if, - VX_commit_if ld_commit_if, - VX_commit_if csr_commit_if, - VX_commit_if fpu_commit_if, - VX_commit_if gpu_commit_if, - - // outputs - VX_writeback_if writeback_if -); - - `UNUSED_PARAM (CORE_ID) - - localparam DATAW = `NW_BITS + 32 + `NUM_THREADS + `NR_BITS + (`NUM_THREADS * 32) + 1; - - wire wb_valid; - wire [`NW_BITS-1:0] wb_wid; - wire [31:0] wb_PC; - wire [`NUM_THREADS-1:0] wb_tmask; - wire [`NR_BITS-1:0] wb_rd; - wire [`NUM_THREADS-1:0][31:0] wb_data; - wire wb_eop; - - wire [4:0][DATAW-1:0] rsp_data; - wire [4:0] rsp_ready; - wire stall; - - wire ld_valid = ld_commit_if.valid && ld_commit_if.wb; - wire fpu_valid = fpu_commit_if.valid && fpu_commit_if.wb; - wire csr_valid = csr_commit_if.valid && csr_commit_if.wb; - wire alu_valid = alu_commit_if.valid && alu_commit_if.wb; - wire gpu_valid = gpu_commit_if.valid && gpu_commit_if.wb; - - assign rsp_data[0] = { ld_commit_if.wid, ld_commit_if.PC, ld_commit_if.tmask, ld_commit_if.rd, ld_commit_if.data, ld_commit_if.eop}; - assign rsp_data[1] = {fpu_commit_if.wid, fpu_commit_if.PC, fpu_commit_if.tmask, fpu_commit_if.rd, fpu_commit_if.data, fpu_commit_if.eop}; - assign rsp_data[2] = {csr_commit_if.wid, csr_commit_if.PC, csr_commit_if.tmask, csr_commit_if.rd, csr_commit_if.data, csr_commit_if.eop}; - assign rsp_data[3] = {alu_commit_if.wid, alu_commit_if.PC, alu_commit_if.tmask, alu_commit_if.rd, alu_commit_if.data, alu_commit_if.eop}; - assign rsp_data[4] = {gpu_commit_if.wid, gpu_commit_if.PC, gpu_commit_if.tmask, gpu_commit_if.rd, gpu_commit_if.data, gpu_commit_if.eop}; - - VX_stream_arbiter #( - .NUM_REQS (5), - .DATAW (DATAW), - .TYPE ("X") - ) rsp_arb ( - .clk (clk), - .reset (reset), - .valid_in ({gpu_valid, alu_valid, csr_valid, fpu_valid, ld_valid}), - .data_in (rsp_data), - .ready_in (rsp_ready), - .valid_out (wb_valid), - .data_out ({wb_wid, wb_PC, wb_tmask, wb_rd, wb_data, wb_eop}), - .ready_out (~stall) - ); - - assign ld_commit_if.ready = rsp_ready[0] || ~ld_commit_if.wb; - assign fpu_commit_if.ready = rsp_ready[1] || ~fpu_commit_if.wb; - assign csr_commit_if.ready = rsp_ready[2] || ~csr_commit_if.wb; - assign alu_commit_if.ready = rsp_ready[3] || ~alu_commit_if.wb; - assign gpu_commit_if.ready = rsp_ready[4] || ~gpu_commit_if.wb; - - assign stall = ~writeback_if.ready && writeback_if.valid; - - VX_pipe_register #( - .DATAW (1 + DATAW), - .RESETW (1) - ) pipe_reg ( - .clk (clk), - .reset (reset), - .enable (~stall), - .data_in ({wb_valid, wb_wid, wb_PC, wb_tmask, wb_rd, wb_data, wb_eop}), - .data_out ({writeback_if.valid, writeback_if.wid, writeback_if.PC, writeback_if.tmask, writeback_if.rd, writeback_if.data, writeback_if.eop}) - ); - - // special workaround to get RISC-V tests Pass/Fail status - reg [31:0] last_wb_value [`NUM_REGS-1:0] /* verilator public */; - always @(posedge clk) begin - if (writeback_if.valid && writeback_if.ready) begin - last_wb_value[writeback_if.rd] <= writeback_if.data[0]; - end - end - -endmodule \ No newline at end of file diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.sv similarity index 78% rename from hw/rtl/Vortex.v rename to hw/rtl/Vortex.sv index 8fa952ed..03469568 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.sv @@ -29,15 +29,15 @@ module Vortex ( wire [`NUM_CLUSTERS-1:0] per_cluster_mem_req_valid; wire [`NUM_CLUSTERS-1:0] per_cluster_mem_req_rw; - wire [`NUM_CLUSTERS-1:0][`L2MEM_BYTEEN_WIDTH-1:0] per_cluster_mem_req_byteen; - wire [`NUM_CLUSTERS-1:0][`L2MEM_ADDR_WIDTH-1:0] per_cluster_mem_req_addr; - wire [`NUM_CLUSTERS-1:0][`L2MEM_DATA_WIDTH-1:0] per_cluster_mem_req_data; - wire [`NUM_CLUSTERS-1:0][`L2MEM_TAG_WIDTH-1:0] per_cluster_mem_req_tag; + wire [`NUM_CLUSTERS-1:0][`L2_MEM_BYTEEN_WIDTH-1:0] per_cluster_mem_req_byteen; + wire [`NUM_CLUSTERS-1:0][`L2_MEM_ADDR_WIDTH-1:0] per_cluster_mem_req_addr; + wire [`NUM_CLUSTERS-1:0][`L2_MEM_DATA_WIDTH-1:0] per_cluster_mem_req_data; + wire [`NUM_CLUSTERS-1:0][`L2_MEM_TAG_WIDTH-1:0] per_cluster_mem_req_tag; wire [`NUM_CLUSTERS-1:0] per_cluster_mem_req_ready; wire [`NUM_CLUSTERS-1:0] per_cluster_mem_rsp_valid; - wire [`NUM_CLUSTERS-1:0][`L2MEM_DATA_WIDTH-1:0] per_cluster_mem_rsp_data; - wire [`NUM_CLUSTERS-1:0][`L2MEM_TAG_WIDTH-1:0] per_cluster_mem_rsp_tag; + wire [`NUM_CLUSTERS-1:0][`L2_MEM_DATA_WIDTH-1:0] per_cluster_mem_rsp_data; + wire [`NUM_CLUSTERS-1:0][`L2_MEM_TAG_WIDTH-1:0] per_cluster_mem_rsp_tag; wire [`NUM_CLUSTERS-1:0] per_cluster_mem_rsp_ready; wire [`NUM_CLUSTERS-1:0] per_cluster_busy; @@ -81,21 +81,22 @@ module Vortex ( `RESET_RELAY (l3_reset); VX_cache #( - .CACHE_ID (`L3CACHE_ID), - .CACHE_SIZE (`L3CACHE_SIZE), - .CACHE_LINE_SIZE (`L3CACHE_LINE_SIZE), - .NUM_BANKS (`L3NUM_BANKS), - .WORD_SIZE (`L3WORD_SIZE), - .NUM_REQS (`L3NUM_REQS), - .CREQ_SIZE (`L3CREQ_SIZE), - .CRSQ_SIZE (`L3CRSQ_SIZE), - .MSHR_SIZE (`L3MSHR_SIZE), - .MRSQ_SIZE (`L3MRSQ_SIZE), - .MREQ_SIZE (`L3MREQ_SIZE), + .CACHE_ID (`L3_CACHE_ID), + .CACHE_SIZE (`L3_CACHE_SIZE), + .CACHE_LINE_SIZE (`L3_CACHE_LINE_SIZE), + .NUM_BANKS (`L3_NUM_BANKS), + .NUM_PORTS (`L3_NUM_PORTS), + .WORD_SIZE (`L3_WORD_SIZE), + .NUM_REQS (`L3_NUM_REQS), + .CREQ_SIZE (`L3_CREQ_SIZE), + .CRSQ_SIZE (`L3_CRSQ_SIZE), + .MSHR_SIZE (`L3_MSHR_SIZE), + .MRSQ_SIZE (`L3_MRSQ_SIZE), + .MREQ_SIZE (`L3_MREQ_SIZE), .WRITE_ENABLE (1), - .CORE_TAG_WIDTH (`L2MEM_TAG_WIDTH), + .CORE_TAG_WIDTH (`L2_MEM_TAG_WIDTH), .CORE_TAG_ID_BITS (0), - .MEM_TAG_WIDTH (`L3MEM_TAG_WIDTH), + .MEM_TAG_WIDTH (`L3_MEM_TAG_WIDTH), .NC_ENABLE (1) ) l3cache ( `SCOPE_BIND_Vortex_l3cache @@ -141,16 +142,19 @@ module Vortex ( end else begin + `RESET_RELAY (mem_arb_reset); + VX_mem_arb #( - .NUM_REQS (`NUM_CLUSTERS), - .DATA_WIDTH (`L3MEM_DATA_WIDTH), - .ADDR_WIDTH (`L3MEM_ADDR_WIDTH), - .TAG_IN_WIDTH (`L2MEM_TAG_WIDTH), - .BUFFERED_REQ (1), - .BUFFERED_RSP (1) + .NUM_REQS (`NUM_CLUSTERS), + .DATA_WIDTH (`L3_MEM_DATA_WIDTH), + .ADDR_WIDTH (`L3_MEM_ADDR_WIDTH), + .TAG_IN_WIDTH (`L2_MEM_TAG_WIDTH), + .TYPE ("R"), + .BUFFERED_REQ (1), + .BUFFERED_RSP (1) ) mem_arb ( .clk (clk), - .reset (reset), + .reset (mem_arb_reset), // Core request .req_valid_in (per_cluster_mem_req_valid), @@ -201,12 +205,12 @@ module Vortex ( always @(posedge clk) begin if (mem_req_valid && mem_req_ready) begin if (mem_req_rw) - $display("%t: MEM Wr Req: addr=%0h, tag=%0h, byteen=%0h data=%0h", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_tag, mem_req_byteen, mem_req_data); + dpi_trace("%d: MEM Wr Req: addr=%0h, tag=%0h, byteen=%0h data=%0h\n", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_tag, mem_req_byteen, mem_req_data); else - $display("%t: MEM Rd Req: addr=%0h, tag=%0h, byteen=%0h", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_tag, mem_req_byteen); + dpi_trace("%d: MEM Rd Req: addr=%0h, tag=%0h, byteen=%0h\n", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_tag, mem_req_byteen); end if (mem_rsp_valid && mem_rsp_ready) begin - $display("%t: MEM Rsp: tag=%0h, data=%0h", $time, mem_rsp_tag, mem_rsp_data); + dpi_trace("%d: MEM Rsp: tag=%0h, data=%0h\n", $time, mem_rsp_tag, mem_rsp_data); end end `endif diff --git a/hw/rtl/Vortex_axi.sv b/hw/rtl/Vortex_axi.sv new file mode 100644 index 00000000..000e0bcb --- /dev/null +++ b/hw/rtl/Vortex_axi.sv @@ -0,0 +1,165 @@ +`include "VX_define.vh" + +module Vortex_axi #( + parameter AXI_DATA_WIDTH = `VX_MEM_DATA_WIDTH, + parameter AXI_ADDR_WIDTH = 32, + parameter AXI_TID_WIDTH = `VX_MEM_TAG_WIDTH, + parameter AXI_STROBE_WIDTH = (`VX_MEM_DATA_WIDTH / 8) +)( + // Clock + input wire clk, + input wire reset, + + // AXI write request address channel + output wire [AXI_TID_WIDTH-1:0] m_axi_awid, + output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr, + output wire [7:0] m_axi_awlen, + output wire [2:0] m_axi_awsize, + output wire [1:0] m_axi_awburst, + output wire m_axi_awlock, + output wire [3:0] m_axi_awcache, + output wire [2:0] m_axi_awprot, + output wire [3:0] m_axi_awqos, + output wire m_axi_awvalid, + input wire m_axi_awready, + + // AXI write request data channel + output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata, + output wire [AXI_STROBE_WIDTH-1:0] m_axi_wstrb, + output wire m_axi_wlast, + output wire m_axi_wvalid, + input wire m_axi_wready, + + // AXI write response channel + input wire [AXI_TID_WIDTH-1:0] m_axi_bid, + input wire [1:0] m_axi_bresp, + input wire m_axi_bvalid, + output wire m_axi_bready, + + // AXI read request channel + output wire [AXI_TID_WIDTH-1:0] m_axi_arid, + output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr, + output wire [7:0] m_axi_arlen, + output wire [2:0] m_axi_arsize, + output wire [1:0] m_axi_arburst, + output wire m_axi_arlock, + output wire [3:0] m_axi_arcache, + output wire [2:0] m_axi_arprot, + output wire [3:0] m_axi_arqos, + output wire m_axi_arvalid, + input wire m_axi_arready, + + // AXI read response channel + input wire [AXI_TID_WIDTH-1:0] m_axi_rid, + input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata, + input wire [1:0] m_axi_rresp, + input wire m_axi_rlast, + input wire m_axi_rvalid, + output wire m_axi_rready, + + // Status + output wire busy +); + wire mem_req_valid; + wire mem_req_rw; + wire [`VX_MEM_BYTEEN_WIDTH-1:0] mem_req_byteen; + wire [`VX_MEM_ADDR_WIDTH-1:0] mem_req_addr; + wire [`VX_MEM_DATA_WIDTH-1:0] mem_req_data; + wire [`VX_MEM_TAG_WIDTH-1:0] mem_req_tag; + wire mem_req_ready; + + wire mem_rsp_valid; + wire [`VX_MEM_DATA_WIDTH-1:0] mem_rsp_data; + wire [`VX_MEM_TAG_WIDTH-1:0] mem_rsp_tag; + wire mem_rsp_ready; + + VX_axi_adapter #( + .VX_DATA_WIDTH (`VX_MEM_DATA_WIDTH), + .VX_ADDR_WIDTH (`VX_MEM_ADDR_WIDTH), + .VX_TAG_WIDTH (`VX_MEM_TAG_WIDTH), + .VX_BYTEEN_WIDTH (AXI_STROBE_WIDTH), + .AXI_DATA_WIDTH (AXI_DATA_WIDTH), + .AXI_ADDR_WIDTH (AXI_ADDR_WIDTH), + .AXI_TID_WIDTH (AXI_TID_WIDTH), + .AXI_STROBE_WIDTH (AXI_STROBE_WIDTH) + ) axi_adapter ( + .clk (clk), + .reset (reset), + + .mem_req_valid (mem_req_valid), + .mem_req_rw (mem_req_rw), + .mem_req_byteen (mem_req_byteen), + .mem_req_addr (mem_req_addr), + .mem_req_data (mem_req_data), + .mem_req_tag (mem_req_tag), + .mem_req_ready (mem_req_ready), + + .mem_rsp_valid (mem_rsp_valid), + .mem_rsp_data (mem_rsp_data), + .mem_rsp_tag (mem_rsp_tag), + .mem_rsp_ready (mem_rsp_ready), + + .m_axi_awid (m_axi_awid), + .m_axi_awaddr (m_axi_awaddr), + .m_axi_awlen (m_axi_awlen), + .m_axi_awsize (m_axi_awsize), + .m_axi_awburst (m_axi_awburst), + .m_axi_awlock (m_axi_awlock), + .m_axi_awcache (m_axi_awcache), + .m_axi_awprot (m_axi_awprot), + .m_axi_awqos (m_axi_awqos), + .m_axi_awvalid (m_axi_awvalid), + .m_axi_awready (m_axi_awready), + + .m_axi_wdata (m_axi_wdata), + .m_axi_wstrb (m_axi_wstrb), + .m_axi_wlast (m_axi_wlast), + .m_axi_wvalid (m_axi_wvalid), + .m_axi_wready (m_axi_wready), + + .m_axi_bid (m_axi_bid), + .m_axi_bresp (m_axi_bresp), + .m_axi_bvalid (m_axi_bvalid), + .m_axi_bready (m_axi_bready), + + .m_axi_arid (m_axi_arid), + .m_axi_araddr (m_axi_araddr), + .m_axi_arlen (m_axi_arlen), + .m_axi_arsize (m_axi_arsize), + .m_axi_arburst (m_axi_arburst), + .m_axi_arlock (m_axi_arlock), + .m_axi_arcache (m_axi_arcache), + .m_axi_arprot (m_axi_arprot), + .m_axi_arqos (m_axi_arqos), + .m_axi_arvalid (m_axi_arvalid), + .m_axi_arready (m_axi_arready), + + .m_axi_rid (m_axi_rid), + .m_axi_rdata (m_axi_rdata), + .m_axi_rresp (m_axi_rresp), + .m_axi_rlast (m_axi_rlast), + .m_axi_rvalid (m_axi_rvalid), + .m_axi_rready (m_axi_rready) + ); + + Vortex vortex ( + .clk (clk), + .reset (reset), + + .mem_req_valid (mem_req_valid), + .mem_req_rw (mem_req_rw), + .mem_req_byteen (mem_req_byteen), + .mem_req_addr (mem_req_addr), + .mem_req_data (mem_req_data), + .mem_req_tag (mem_req_tag), + .mem_req_ready (mem_req_ready), + + .mem_rsp_valid (mem_rsp_valid), + .mem_rsp_data (mem_rsp_data), + .mem_rsp_tag (mem_rsp_tag), + .mem_rsp_ready (mem_rsp_ready), + + .busy (busy) + ); + +endmodule \ No newline at end of file diff --git a/hw/rtl/afu/VX_avs_wrapper.v b/hw/rtl/afu/VX_avs_wrapper.sv similarity index 61% rename from hw/rtl/afu/VX_avs_wrapper.v rename to hw/rtl/afu/VX_avs_wrapper.sv index cdefcec1..d6aaf890 100644 --- a/hw/rtl/afu/VX_avs_wrapper.v +++ b/hw/rtl/afu/VX_avs_wrapper.sv @@ -1,17 +1,15 @@ `include "VX_define.vh" -module VX_avs_wrapper #( - parameter NUM_BANKS = 1, +module VX_avs_wrapper #( parameter AVS_DATA_WIDTH = 1, parameter AVS_ADDR_WIDTH = 1, parameter AVS_BURST_WIDTH = 1, - parameter AVS_BANKS = 1, + parameter AVS_BANKS = 1, parameter REQ_TAG_WIDTH = 1, parameter RD_QUEUE_SIZE = 1, parameter AVS_BYTEENW = (AVS_DATA_WIDTH / 8), - parameter RD_QUEUE_ADDR_WIDTH = $clog2(RD_QUEUE_SIZE+1), - parameter AVS_BANKS_BITS = $clog2(AVS_BANKS) + parameter RD_QUEUE_ADDR_WIDTH = $clog2(RD_QUEUE_SIZE+1) ) ( input wire clk, input wire reset, @@ -32,47 +30,46 @@ module VX_avs_wrapper #( input wire mem_rsp_ready, // AVS bus - output wire [AVS_DATA_WIDTH-1:0] avs_writedata [NUM_BANKS], - input wire [AVS_DATA_WIDTH-1:0] avs_readdata [NUM_BANKS], - output wire [AVS_ADDR_WIDTH-1:0] avs_address [NUM_BANKS], - input wire avs_waitrequest [NUM_BANKS], - output wire avs_write [NUM_BANKS], - output wire avs_read [NUM_BANKS], - output wire [AVS_BYTEENW-1:0] avs_byteenable [NUM_BANKS], - output wire [AVS_BURST_WIDTH-1:0] avs_burstcount [NUM_BANKS], - input avs_readdatavalid [NUM_BANKS] + output wire [AVS_DATA_WIDTH-1:0] avs_writedata [AVS_BANKS], + input wire [AVS_DATA_WIDTH-1:0] avs_readdata [AVS_BANKS], + output wire [AVS_ADDR_WIDTH-1:0] avs_address [AVS_BANKS], + input wire avs_waitrequest [AVS_BANKS], + output wire avs_write [AVS_BANKS], + output wire avs_read [AVS_BANKS], + output wire [AVS_BYTEENW-1:0] avs_byteenable [AVS_BANKS], + output wire [AVS_BURST_WIDTH-1:0] avs_burstcount [AVS_BANKS], + input avs_readdatavalid [AVS_BANKS] ); - localparam BANK_ADDRW = `LOG2UP(NUM_BANKS); - localparam OUTPUT_REG = (NUM_BANKS > 2); + localparam BANK_ADDRW = `LOG2UP(AVS_BANKS); // Requests handling - wire [NUM_BANKS-1:0] avs_reqq_push, avs_reqq_pop, avs_reqq_ready; - wire [NUM_BANKS-1:0][REQ_TAG_WIDTH-1:0] avs_reqq_tag_out; - wire [NUM_BANKS-1:0] req_queue_going_full; - wire [NUM_BANKS-1:0][RD_QUEUE_ADDR_WIDTH-1:0] req_queue_size; + wire [AVS_BANKS-1:0] avs_reqq_push, avs_reqq_pop, avs_reqq_ready; + wire [AVS_BANKS-1:0][REQ_TAG_WIDTH-1:0] avs_reqq_tag_out; + wire [AVS_BANKS-1:0] req_queue_going_full; + wire [AVS_BANKS-1:0][RD_QUEUE_ADDR_WIDTH-1:0] req_queue_size; wire [BANK_ADDRW-1:0] req_bank_sel; - if (NUM_BANKS >= 2) begin + if (AVS_BANKS >= 2) begin assign req_bank_sel = mem_req_addr[BANK_ADDRW-1:0]; end else begin assign req_bank_sel = 0; end - for (genvar i = 0; i < NUM_BANKS; i++) begin + for (genvar i = 0; i < AVS_BANKS; i++) begin assign avs_reqq_ready[i] = !req_queue_going_full[i] && !avs_waitrequest[i]; assign avs_reqq_push[i] = mem_req_valid && !mem_req_rw && avs_reqq_ready[i] && (req_bank_sel == i); end - for (genvar i = 0; i < NUM_BANKS; i++) begin + for (genvar i = 0; i < AVS_BANKS; i++) begin VX_pending_size #( .SIZE (RD_QUEUE_SIZE) ) pending_size ( .clk (clk), .reset (reset), - .push (avs_reqq_push[i]), - .pop (avs_reqq_pop[i]), + .incr (avs_reqq_push[i]), + .decr (avs_reqq_pop[i]), .full (req_queue_going_full[i]), .size (req_queue_size[i]), `UNUSED_PIN (empty) @@ -80,9 +77,8 @@ module VX_avs_wrapper #( `UNUSED_VAR (req_queue_size) VX_fifo_queue #( - .DATAW (REQ_TAG_WIDTH), - .SIZE (RD_QUEUE_SIZE), - .OUTPUT_REG (!OUTPUT_REG) + .DATAW (REQ_TAG_WIDTH), + .SIZE (RD_QUEUE_SIZE) ) rd_req_queue ( .clk (clk), .reset (reset), @@ -98,7 +94,7 @@ module VX_avs_wrapper #( ); end - for (genvar i = 0; i < NUM_BANKS; i++) begin + for (genvar i = 0; i < AVS_BANKS; i++) begin assign avs_read[i] = mem_req_valid && !mem_req_rw && !req_queue_going_full[i] && (req_bank_sel == i); assign avs_write[i] = mem_req_valid && mem_req_rw && !req_queue_going_full[i] && (req_bank_sel == i); assign avs_address[i] = mem_req_addr; @@ -107,7 +103,7 @@ module VX_avs_wrapper #( assign avs_burstcount[i] = AVS_BURST_WIDTH'(1); end - if (NUM_BANKS >= 2) begin + if (AVS_BANKS >= 2) begin assign mem_req_ready = avs_reqq_ready[req_bank_sel]; end else begin assign mem_req_ready = avs_reqq_ready; @@ -115,18 +111,17 @@ module VX_avs_wrapper #( // Responses handling - wire [NUM_BANKS-1:0] rsp_arb_valid_in; - wire [NUM_BANKS-1:0][AVS_DATA_WIDTH+REQ_TAG_WIDTH-1:0] rsp_arb_data_in; - wire [NUM_BANKS-1:0] rsp_arb_ready_in; + wire [AVS_BANKS-1:0] rsp_arb_valid_in; + wire [AVS_BANKS-1:0][AVS_DATA_WIDTH+REQ_TAG_WIDTH-1:0] rsp_arb_data_in; + wire [AVS_BANKS-1:0] rsp_arb_ready_in; - wire [NUM_BANKS-1:0][AVS_DATA_WIDTH-1:0] avs_rspq_data_out; - wire [NUM_BANKS-1:0] avs_rspq_empty; + wire [AVS_BANKS-1:0][AVS_DATA_WIDTH-1:0] avs_rspq_data_out; + wire [AVS_BANKS-1:0] avs_rspq_empty; - for (genvar i = 0; i < NUM_BANKS; i++) begin + for (genvar i = 0; i < AVS_BANKS; i++) begin VX_fifo_queue #( - .DATAW (AVS_DATA_WIDTH), - .SIZE (RD_QUEUE_SIZE), - .OUTPUT_REG (!OUTPUT_REG) + .DATAW (AVS_DATA_WIDTH), + .SIZE (RD_QUEUE_SIZE) ) rd_rsp_queue ( .clk (clk), .reset (reset), @@ -140,18 +135,18 @@ module VX_avs_wrapper #( `UNUSED_PIN (alm_full), `UNUSED_PIN (size) ); - end + end - for (genvar i = 0; i < NUM_BANKS; i++) begin + for (genvar i = 0; i < AVS_BANKS; i++) begin assign rsp_arb_valid_in[i] = !avs_rspq_empty[i]; assign rsp_arb_data_in[i] = {avs_rspq_data_out[i], avs_reqq_tag_out[i]}; assign avs_reqq_pop[i] = rsp_arb_valid_in[i] && rsp_arb_ready_in[i]; end VX_stream_arbiter #( - .NUM_REQS (NUM_BANKS), + .NUM_REQS (AVS_BANKS), .DATAW (AVS_DATA_WIDTH + REQ_TAG_WIDTH), - .BUFFERED (OUTPUT_REG ? 1 : 0) + .TYPE ("R") ) rsp_arb ( .clk (clk), .reset (reset), @@ -166,13 +161,14 @@ module VX_avs_wrapper #( `ifdef DBG_PRINT_AVS always @(posedge clk) begin if (mem_req_valid && mem_req_ready) begin - if (mem_req_rw) - $display("%t: AVS Wr Req: addr=%0h, byteen=%0h, tag=%0h, data=%0h", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_byteen, mem_req_tag, mem_req_data); - else - $display("%t: AVS Rd Req: addr=%0h, byteen=%0h, tag=%0h, pending=%0d", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_byteen, mem_req_tag, req_queue_size); + if (mem_req_rw) begin + dpi_trace("%d: AVS Wr Req: addr=%0h, byteen=%0h, tag=%0h, data=%0h\n", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_byteen, mem_req_tag, mem_req_data); + end else begin + dpi_trace("%d: AVS Rd Req: addr=%0h, byteen=%0h, tag=%0h, pending=%0d\n", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_byteen, mem_req_tag, req_queue_size); + end end if (mem_rsp_valid && mem_rsp_ready) begin - $display("%t: AVS Rd Rsp: tag=%0h, data=%0h, pending=%0d", $time, mem_rsp_tag, mem_rsp_data, req_queue_size); + dpi_trace("%d: AVS Rd Rsp: tag=%0h, data=%0h, pending=%0d\n", $time, mem_rsp_tag, mem_rsp_data, req_queue_size); end end `endif diff --git a/hw/rtl/afu/VX_to_mem.v b/hw/rtl/afu/VX_to_mem.sv similarity index 100% rename from hw/rtl/afu/VX_to_mem.v rename to hw/rtl/afu/VX_to_mem.sv diff --git a/hw/rtl/afu/vortex_afu.sv b/hw/rtl/afu/vortex_afu.sv index 1a084490..6d1e2488 100644 --- a/hw/rtl/afu/vortex_afu.sv +++ b/hw/rtl/afu/vortex_afu.sv @@ -47,9 +47,10 @@ localparam CCI_ADDR_WIDTH = 32 - $clog2(CCI_DATA_SIZE); localparam AVS_RD_QUEUE_SIZE = 4; -localparam _AVS_REQ_TAGW_VX = `VX_MEM_TAG_WIDTH + $clog2(LMEM_DATA_WIDTH) - $clog2(`VX_MEM_DATA_WIDTH); -localparam AVS_REQ_TAGW_VX = `MAX(`VX_MEM_TAG_WIDTH, _AVS_REQ_TAGW_VX); -localparam AVS_REQ_TAGW_CCI = `MAX(CCI_ADDR_WIDTH, CCI_ADDR_WIDTH + $clog2(LMEM_DATA_WIDTH) - $clog2(CCI_DATA_WIDTH)); +localparam AVS_REQ_TAGW_VX_ = `VX_MEM_TAG_WIDTH + $clog2(LMEM_DATA_WIDTH) - $clog2(`VX_MEM_DATA_WIDTH); +localparam AVS_REQ_TAGW_VX = `MAX(`VX_MEM_TAG_WIDTH, AVS_REQ_TAGW_VX_); +localparam AVS_REQ_TAGW_CCI_ = CCI_ADDR_WIDTH + $clog2(LMEM_DATA_WIDTH) - $clog2(CCI_DATA_WIDTH); +localparam AVS_REQ_TAGW_CCI = `MAX(CCI_ADDR_WIDTH, AVS_REQ_TAGW_CCI_); localparam AVS_REQ_TAGW = `MAX(AVS_REQ_TAGW_VX, AVS_REQ_TAGW_CCI); localparam CCI_RD_WINDOW_SIZE = 8; @@ -94,7 +95,7 @@ localparam STATE_WIDTH = $clog2(STATE_MAX_VALUE); wire [127:0] afu_id = `AFU_ACCEL_UUID; -wire [63:0] dev_caps = {16'(`NUM_THREADS), 16'(`NUM_WARPS), 16'(`NUM_CORES), 16'(`IMPLEMENTATION_ID)}; +wire [63:0] dev_caps = {16'(`NUM_THREADS), 16'(`NUM_WARPS), 16'(`NUM_CORES * `NUM_CLUSTERS), 16'(`IMPLEMENTATION_ID)}; reg [STATE_WIDTH-1:0] state; @@ -131,9 +132,9 @@ wire cmd_scope_write; // MMIO controller //////////////////////////////////////////////////////////// -`IGNORE_WARNINGS_BEGIN +`IGNORE_UNUSED_BEGIN t_ccip_c0_ReqMmioHdr mmio_hdr; -`IGNORE_WARNINGS_END +`IGNORE_UNUSED_END assign mmio_hdr = t_ccip_c0_ReqMmioHdr'(cp2af_sRxPort.c0.hdr); `STATIC_ASSERT(($bits(t_ccip_c0_ReqMmioHdr)-$bits(mmio_hdr.address)) == 12, ("Oops!")) @@ -150,21 +151,6 @@ assign cmd_scope_write = cp2af_sRxPort.c0.mmioWrValid && (MMIO_SCOPE_WRITE == mm wire [COUT_QUEUE_DATAW-1:0] cout_q_dout; wire cout_q_full, cout_q_empty; -/* -`DEBUG_BEGIN -wire cp2af_sRxPort_c0_mmioWrValid = cp2af_sRxPort.c0.mmioWrValid; -wire cp2af_sRxPort_c0_mmioRdValid = cp2af_sRxPort.c0.mmioRdValid; -wire cp2af_sRxPort_c0_rspValid = cp2af_sRxPort.c0.rspValid; -wire cp2af_sRxPort_c1_rspValid = cp2af_sRxPort.c1.rspValid; -wire cp2af_sRxPort_c0TxAlmFull = cp2af_sRxPort.c0TxAlmFull; -wire cp2af_sRxPort_c1TxAlmFull = cp2af_sRxPort.c1TxAlmFull; -wire[$bits(mmio_hdr.address)-1:0] mmio_hdr_address = mmio_hdr.address; -wire[$bits(mmio_hdr.length)-1:0] mmio_hdr_length = mmio_hdr.length; -wire[$bits(mmio_hdr.tid)-1:0] mmio_hdr_tid = mmio_hdr.tid; -wire[$bits(cp2af_sRxPort.c0.hdr.mdata)-1:0] cp2af_sRxPort_c0_hdr_mdata = cp2af_sRxPort.c0.hdr.mdata; -`DEBUG_END -*/ - wire [2:0] cmd_type = (cp2af_sRxPort.c0.mmioWrValid && (MMIO_CMD_TYPE == mmio_hdr.address)) ? 3'(cp2af_sRxPort.c0.data) : 3'h0; @@ -201,36 +187,36 @@ always @(posedge clk) begin MMIO_IO_ADDR: begin cmd_io_addr <= t_ccip_clAddr'(cp2af_sRxPort.c0.data); `ifdef DBG_PRINT_OPAE - $display("%t: MMIO_IO_ADDR: addr=%0h, data=0x%0h", $time, mmio_hdr.address, t_ccip_clAddr'(cp2af_sRxPort.c0.data)); + dpi_trace("%d: MMIO_IO_ADDR: addr=%0h, data=0x%0h\n", $time, mmio_hdr.address, t_ccip_clAddr'(cp2af_sRxPort.c0.data)); `endif end MMIO_MEM_ADDR: begin cmd_mem_addr <= $bits(cmd_mem_addr)'(cp2af_sRxPort.c0.data); `ifdef DBG_PRINT_OPAE - $display("%t: MMIO_MEM_ADDR: addr=%0h, data=0x%0h", $time, mmio_hdr.address, $bits(cmd_mem_addr)'(cp2af_sRxPort.c0.data)); + dpi_trace("%d: MMIO_MEM_ADDR: addr=%0h, data=0x%0h\n", $time, mmio_hdr.address, $bits(cmd_mem_addr)'(cp2af_sRxPort.c0.data)); `endif end MMIO_DATA_SIZE: begin cmd_data_size <= $bits(cmd_data_size)'(cp2af_sRxPort.c0.data); `ifdef DBG_PRINT_OPAE - $display("%t: MMIO_DATA_SIZE: addr=%0h, data=%0d", $time, mmio_hdr.address, $bits(cmd_data_size)'(cp2af_sRxPort.c0.data)); + dpi_trace("%d: MMIO_DATA_SIZE: addr=%0h, data=%0d\n", $time, mmio_hdr.address, $bits(cmd_data_size)'(cp2af_sRxPort.c0.data)); `endif end MMIO_CMD_TYPE: begin `ifdef DBG_PRINT_OPAE - $display("%t: MMIO_CMD_TYPE: addr=%0h, data=%0d", $time, mmio_hdr.address, $bits(cmd_type)'(cp2af_sRxPort.c0.data)); + dpi_trace("%d: MMIO_CMD_TYPE: addr=%0h, data=%0d\n", $time, mmio_hdr.address, $bits(cmd_type)'(cp2af_sRxPort.c0.data)); `endif end `ifdef SCOPE MMIO_SCOPE_WRITE: begin `ifdef DBG_PRINT_OPAE - $display("%t: MMIO_SCOPE_WRITE: addr=%0h, data=%0h", $time, mmio_hdr.address, 64'(cp2af_sRxPort.c0.data)); + dpi_trace("%d: MMIO_SCOPE_WRITE: addr=%0h, data=%0h\n", $time, mmio_hdr.address, 64'(cp2af_sRxPort.c0.data)); `endif end `endif default: begin `ifdef DBG_PRINT_OPAE - $display("%t: Unknown MMIO Wr: addr=%0h, data=%0h", $time, mmio_hdr.address, $bits(cmd_data_size)'(cp2af_sRxPort.c0.data)); + dpi_trace("%d: Unknown MMIO Wr: addr=%0h, data=%0h\n", $time, mmio_hdr.address, $bits(cmd_data_size)'(cp2af_sRxPort.c0.data)); `endif end endcase @@ -258,7 +244,7 @@ always @(posedge clk) begin mmio_tx.data <= 64'({cout_q_dout, !cout_q_empty, 8'(state)}); `ifdef DBG_PRINT_OPAE if (state != STATE_WIDTH'(mmio_tx.data)) begin - $display("%t: MMIO_STATUS: addr=%0h, state=%0d", $time, mmio_hdr.address, state); + dpi_trace("%d: MMIO_STATUS: addr=%0h, state=%0d\n", $time, mmio_hdr.address, state); end `endif end @@ -266,20 +252,20 @@ always @(posedge clk) begin MMIO_SCOPE_READ: begin mmio_tx.data <= cmd_scope_rdata; `ifdef DBG_PRINT_OPAE - $display("%t: MMIO_SCOPE_READ: addr=%0h, data=%0h", $time, mmio_hdr.address, cmd_scope_rdata); + dpi_trace("%d: MMIO_SCOPE_READ: addr=%0h, data=%0h\n", $time, mmio_hdr.address, cmd_scope_rdata); `endif end `endif MMIO_DEV_CAPS: begin mmio_tx.data <= dev_caps; `ifdef DBG_PRINT_OPAE - $display("%t: MMIO_DEV_CAPS: addr=%0h, data=%0h", $time, mmio_hdr.address, dev_caps); + dpi_trace("%d: MMIO_DEV_CAPS: addr=%0h, data=%0h\n", $time, mmio_hdr.address, dev_caps); `endif end default: begin mmio_tx.data <= 64'h0; `ifdef DBG_PRINT_OPAE - $display("%t: Unknown MMIO Rd: addr=%0h", $time, mmio_hdr.address); + dpi_trace("%d: Unknown MMIO Rd: addr=%0h\n", $time, mmio_hdr.address); `endif end endcase @@ -313,19 +299,19 @@ always @(posedge clk) begin case (cmd_type) CMD_MEM_READ: begin `ifdef DBG_PRINT_OPAE - $display("%t: STATE READ: ia=%0h addr=%0h size=%0d", $time, cmd_io_addr, cmd_mem_addr, cmd_data_size); + dpi_trace("%d: STATE READ: ia=%0h addr=%0h size=%0d\n", $time, cmd_io_addr, cmd_mem_addr, cmd_data_size); `endif state <= STATE_READ; end CMD_MEM_WRITE: begin `ifdef DBG_PRINT_OPAE - $display("%t: STATE WRITE: ia=%0h addr=%0h size=%0d", $time, cmd_io_addr, cmd_mem_addr, cmd_data_size); + dpi_trace("%d: STATE WRITE: ia=%0h addr=%0h size=%0d\n", $time, cmd_io_addr, cmd_mem_addr, cmd_data_size); `endif state <= STATE_WRITE; end CMD_RUN: begin `ifdef DBG_PRINT_OPAE - $display("%t: STATE START", $time); + dpi_trace("%d: STATE START\n", $time); `endif vx_reset <= 1; state <= STATE_START; @@ -340,7 +326,7 @@ always @(posedge clk) begin if (cmd_read_done) begin state <= STATE_IDLE; `ifdef DBG_PRINT_OPAE - $display("%t: STATE IDLE", $time); + dpi_trace("%d: STATE IDLE\n", $time); `endif end end @@ -349,7 +335,7 @@ always @(posedge clk) begin if (cmd_write_done) begin state <= STATE_IDLE; `ifdef DBG_PRINT_OPAE - $display("%t: STATE IDLE", $time); + dpi_trace("%d: STATE IDLE\n", $time); `endif end end @@ -361,7 +347,7 @@ always @(posedge clk) begin vx_started <= 0; state <= STATE_IDLE; `ifdef DBG_PRINT_OPAE - $display("%t: STATE IDLE", $time); + dpi_trace("%d: STATE IDLE\n", $time); `endif end end else begin @@ -527,17 +513,19 @@ t_local_mem_data mem_rsp_data; wire [AVS_REQ_TAGW:0] mem_rsp_tag; wire mem_rsp_ready; +`RESET_RELAY (mem_arb_reset); + VX_mem_arb #( .NUM_REQS (2), .DATA_WIDTH (LMEM_DATA_WIDTH), .ADDR_WIDTH (LMEM_ADDR_WIDTH), .TAG_IN_WIDTH (AVS_REQ_TAGW), - .BUFFERED_REQ (0), - .BUFFERED_RSP (0), - .TYPE ("X") + .TYPE ("P"), + .BUFFERED_REQ (2), + .BUFFERED_RSP (2) ) mem_arb ( .clk (clk), - .reset (reset), + .reset (mem_arb_reset), // Source request .req_valid_in ({vx_mem_req_arb_valid, cci_mem_req_arb_valid}), @@ -572,8 +560,9 @@ VX_mem_arb #( //-- +`RESET_RELAY (avs_wrapper_reset); + VX_avs_wrapper #( - .NUM_BANKS (NUM_LOCAL_MEM_BANKS), .AVS_DATA_WIDTH (LMEM_DATA_WIDTH), .AVS_ADDR_WIDTH (LMEM_ADDR_WIDTH), .AVS_BURST_WIDTH (LMEM_BURST_CTRW), @@ -582,7 +571,7 @@ VX_avs_wrapper #( .RD_QUEUE_SIZE (AVS_RD_QUEUE_SIZE) ) avs_wrapper ( .clk (clk), - .reset (reset), + .reset (avs_wrapper_reset), // Memory request .mem_req_valid (mem_req_valid), @@ -657,8 +646,8 @@ VX_pending_size #( ) cci_rd_pending_size ( .clk (clk), .reset (reset), - .push (cci_rd_req_fire), - .pop (cci_rdq_pop), + .incr (cci_rd_req_fire), + .decr (cci_rdq_pop), .full (cci_pending_reads_full), .size (cci_pending_reads), `UNUSED_PIN (empty) @@ -712,7 +701,7 @@ always @(posedge clk) begin cci_rd_req_addr <= cci_rd_req_addr + 1; cci_rd_req_ctr <= cci_rd_req_ctr + 1; `ifdef DBG_PRINT_OPAE - $display("%t: CCI Rd Req: addr=%0h, tag=%0h, rem=%0d, pending=%0d", $time, cci_rd_req_addr, cci_rd_req_tag, (cmd_data_size - cci_rd_req_ctr - 1), cci_pending_reads); + dpi_trace("%d: CCI Rd Req: addr=%0h, tag=%0h, rem=%0d, pending=%0d\n", $time, cci_rd_req_addr, cci_rd_req_tag, (cmd_data_size - cci_rd_req_ctr - 1), cci_pending_reads); `endif end @@ -722,13 +711,13 @@ always @(posedge clk) begin cci_mem_wr_req_addr_base <= cci_mem_wr_req_addr_base + CCI_ADDR_WIDTH'(CCI_RD_WINDOW_SIZE); end `ifdef DBG_PRINT_OPAE - $display("%t: CCI Rd Rsp: idx=%0d, ctr=%0d, data=%0h", $time, cci_rd_rsp_tag, cci_rd_rsp_ctr, cp2af_sRxPort.c0.data); + dpi_trace("%d: CCI Rd Rsp: idx=%0d, ctr=%0d, data=%0h\n", $time, cci_rd_rsp_tag, cci_rd_rsp_ctr, cp2af_sRxPort.c0.data); `endif end if (cci_rdq_pop) begin `ifdef DBG_PRINT_OPAE - $display("%t: CCI Rd Queue Pop: pending=%0d", $time, cci_pending_reads); + dpi_trace("%d: CCI Rd Queue Pop: pending=%0d\n", $time, cci_pending_reads); `endif end @@ -740,13 +729,15 @@ always @(posedge clk) begin end end +`RESET_RELAY (cci_rdq_reset); + VX_fifo_queue #( - .DATAW (CCI_RD_QUEUE_DATAW), - .SIZE (CCI_RD_QUEUE_SIZE), - .OUTPUT_REG (1) + .DATAW (CCI_RD_QUEUE_DATAW), + .SIZE (CCI_RD_QUEUE_SIZE), + .OUT_REG (1) ) cci_rd_req_queue ( .clk (clk), - .reset (reset), + .reset (cci_rdq_reset), .push (cci_rdq_push), .pop (cci_rdq_pop), .data_in (cci_rdq_din), @@ -814,8 +805,8 @@ VX_pending_size #( ) cci_wr_pending_size ( .clk (clk), .reset (reset), - .push (cci_mem_rd_rsp_fire), - .pop (cci_wr_rsp_fire), + .incr (cci_mem_rd_rsp_fire), + .decr (cci_wr_rsp_fire), .empty (cci_pending_writes_empty), .full (cci_pending_writes_full), .size (cci_pending_writes) @@ -861,19 +852,19 @@ begin cci_wr_req_data <= t_ccip_clData'(cci_mem_rsp_data); if (cci_wr_req_fire) begin - assert(cci_wr_req_ctr != 0); + `ASSERT(cci_wr_req_ctr != 0, ("runtime error")); cci_wr_req_ctr <= cci_wr_req_ctr - CCI_ADDR_WIDTH'(1); if (cci_wr_req_ctr == CCI_ADDR_WIDTH'(1)) begin cci_wr_req_done <= 1; end `ifdef DBG_PRINT_OPAE - $display("%t: CCI Wr Req: addr=%0h, rem=%0d, pending=%0d, data=%0h", $time, cci_wr_req_addr, (cci_wr_req_ctr - 1), cci_pending_writes, af2cp_sTxPort.c1.data); + dpi_trace("%d: CCI Wr Req: addr=%0h, rem=%0d, pending=%0d, data=%0h\n", $time, cci_wr_req_addr, (cci_wr_req_ctr - 1), cci_pending_writes, af2cp_sTxPort.c1.data); `endif end if (cci_wr_rsp_fire) begin `ifdef DBG_PRINT_OPAE - $display("%t: CCI Wr Rsp: pending=%0d", $time, cci_pending_writes); + dpi_trace("%d: CCI Wr Rsp: pending=%0d\n", $time, cci_pending_writes); `endif end end @@ -890,11 +881,11 @@ assign cci_mem_req_tag = cci_mem_req_rw ? cci_mem_wr_req_ctr : cci_mem_rd_req_ assign cmd_run_done = !vx_busy; -Vortex #() vortex ( +Vortex vortex ( `SCOPE_BIND_afu_vortex .clk (clk), - .reset (reset | vx_reset), + .reset (reset || vx_reset), // Memory request .mem_req_valid (vx_mem_req_valid), @@ -1013,6 +1004,8 @@ VX_fifo_queue #( wire scope_changed = `SCOPE_TRIGGER; +`RESET_RELAY (scope_reset); + VX_scope #( .DATAW ($bits({`SCOPE_DATA_LIST,`SCOPE_UPDATE_LIST})), .BUSW (64), @@ -1020,7 +1013,7 @@ VX_scope #( .UPDW ($bits({`SCOPE_UPDATE_LIST})) ) scope ( .clk (clk), - .reset (reset), + .reset (scope_reset), .start (1'b0), .stop (1'b0), .changed (scope_changed), diff --git a/hw/rtl/cache/VX_bank.sv b/hw/rtl/cache/VX_bank.sv new file mode 100644 index 00000000..1f05ae04 --- /dev/null +++ b/hw/rtl/cache/VX_bank.sv @@ -0,0 +1,548 @@ +`include "VX_cache_define.vh" + +module VX_bank #( + parameter CACHE_ID = 0, + parameter BANK_ID = 0, + + // Number of Word requests per cycle + parameter NUM_REQS = 1, + + // Size of cache in bytes + parameter CACHE_SIZE = 1, + // Size of line inside a bank in bytes + parameter CACHE_LINE_SIZE = 1, + // Number of bankS + parameter NUM_BANKS = 1, + // Number of ports per banks + parameter NUM_PORTS = 1, + // Size of a word in bytes + parameter WORD_SIZE = 1, + + // Core Request Queue Size + parameter CREQ_SIZE = 1, + // Core Response Queue Size + parameter CRSQ_SIZE = 1, + // Miss Reserv Queue Knob + parameter MSHR_SIZE = 1, + // Memory Request Queue Size + parameter MREQ_SIZE = 1, + + // Enable cache writeable + parameter WRITE_ENABLE = 1, + + // core request tag size + parameter CORE_TAG_WIDTH = 1, + + // size of tag id in core request tag + parameter CORE_TAG_ID_BITS = 0, + + // bank offset from beginning of index range + parameter BANK_ADDR_OFFSET = 0, + + parameter MSHR_ADDR_WIDTH = $clog2(MSHR_SIZE), + parameter WORD_SELECT_BITS = `UP(`WORD_SELECT_BITS) +) ( + `SCOPE_IO_VX_bank + + input wire clk, + input wire reset, + +`ifdef PERF_ENABLE + output wire perf_read_misses, + output wire perf_write_misses, + output wire perf_mshr_stalls, + output wire perf_pipe_stalls, +`endif + + // Core Request + input wire core_req_valid, + input wire [NUM_PORTS-1:0] core_req_pmask, + input wire [NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] core_req_wsel, + input wire [NUM_PORTS-1:0][WORD_SIZE-1:0] core_req_byteen, + input wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] core_req_data, + input wire [NUM_PORTS-1:0][`REQS_BITS-1:0] core_req_tid, + input wire [NUM_PORTS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag, + input wire core_req_rw, + input wire [`LINE_ADDR_WIDTH-1:0] core_req_addr, + output wire core_req_ready, + + // Core Response + output wire core_rsp_valid, + output wire [NUM_PORTS-1:0] core_rsp_pmask, + output wire [NUM_PORTS-1:0][`REQS_BITS-1:0] core_rsp_tid, + output wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] core_rsp_data, + output wire [NUM_PORTS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag, + input wire core_rsp_ready, + + // Memory request + output wire mem_req_valid, + output wire mem_req_rw, + output wire [NUM_PORTS-1:0] mem_req_pmask, + output wire [NUM_PORTS-1:0][WORD_SIZE-1:0] mem_req_byteen, + output wire [NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] mem_req_wsel, + output wire [`LINE_ADDR_WIDTH-1:0] mem_req_addr, + output wire [MSHR_ADDR_WIDTH-1:0] mem_req_id, + output wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] mem_req_data, + input wire mem_req_ready, + + // Memory response + input wire mem_rsp_valid, + input wire [MSHR_ADDR_WIDTH-1:0] mem_rsp_id, + input wire [`CACHE_LINE_WIDTH-1:0] mem_rsp_data, + output wire mem_rsp_ready, + + // flush + input wire flush_enable, + input wire [`LINE_SELECT_BITS-1:0] flush_addr +); + + `UNUSED_PARAM (CORE_TAG_ID_BITS) + +`ifdef DBG_CACHE_REQ_INFO +`IGNORE_UNUSED_BEGIN + wire [31:0] debug_pc_sel, debug_pc_st0, debug_pc_st1; + wire [`NW_BITS-1:0] debug_wid_sel, debug_wid_st0, debug_wid_st1; +`IGNORE_UNUSED_END +`endif + + wire [NUM_PORTS-1:0] creq_pmask; + wire [NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] creq_wsel; + wire [NUM_PORTS-1:0][WORD_SIZE-1:0] creq_byteen; + wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] creq_data; + wire [NUM_PORTS-1:0][`REQS_BITS-1:0] creq_tid; + wire [NUM_PORTS-1:0][CORE_TAG_WIDTH-1:0] creq_tag; + wire creq_rw; + wire [`LINE_ADDR_WIDTH-1:0] creq_addr; + + wire creq_valid, creq_ready; + + VX_elastic_buffer #( + .DATAW (1 + `LINE_ADDR_WIDTH + NUM_PORTS * (1 + WORD_SELECT_BITS + WORD_SIZE + `WORD_WIDTH + `REQS_BITS + CORE_TAG_WIDTH)), + .SIZE (CREQ_SIZE) + ) core_req_queue ( + .clk (clk), + .reset (reset), + .ready_in (core_req_ready), + .valid_in (core_req_valid), + .data_in ({core_req_rw, core_req_addr, core_req_pmask, core_req_wsel, core_req_byteen, core_req_data, core_req_tid, core_req_tag}), + .data_out ({creq_rw, creq_addr, creq_pmask, creq_wsel, creq_byteen, creq_data, creq_tid, creq_tag}), + .ready_out (creq_ready), + .valid_out (creq_valid) + ); + + wire mreq_alm_full; + wire [`LINE_ADDR_WIDTH-1:0] mem_rsp_addr; + wire crsq_valid, crsq_ready; + wire crsq_stall; + + wire mshr_valid; + wire mshr_ready; + wire [MSHR_ADDR_WIDTH-1:0] mshr_alloc_id; + wire mshr_alm_full; + wire [MSHR_ADDR_WIDTH-1:0] mshr_dequeue_id; + wire [`LINE_ADDR_WIDTH-1:0] mshr_addr; + wire [NUM_PORTS-1:0][CORE_TAG_WIDTH-1:0] mshr_tag; + wire [NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] mshr_wsel; + wire [NUM_PORTS-1:0][`REQS_BITS-1:0] mshr_tid; + wire [NUM_PORTS-1:0] mshr_pmask; + + wire [`LINE_ADDR_WIDTH-1:0] addr_st0, addr_st1; + wire is_read_st0, is_read_st1; + wire is_write_st0, is_write_st1; + wire [NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] wsel_st0, wsel_st1; + wire [NUM_PORTS-1:0][WORD_SIZE-1:0] byteen_st0, byteen_st1; + wire [NUM_PORTS-1:0][`REQS_BITS-1:0] req_tid_st0, req_tid_st1; + wire [NUM_PORTS-1:0] pmask_st0, pmask_st1; + wire [NUM_PORTS-1:0][CORE_TAG_WIDTH-1:0] tag_st0, tag_st1; + wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] rdata_st1; + wire [`CACHE_LINE_WIDTH-1:0] wdata_st0, wdata_st1; + wire [MSHR_ADDR_WIDTH-1:0] mshr_id_st0, mshr_id_st1; + wire valid_st0, valid_st1; + wire is_fill_st0, is_fill_st1; + wire is_mshr_st0, is_mshr_st1; + wire miss_st0, miss_st1; + wire is_flush_st0; + wire mshr_pending_st0, mshr_pending_st1; + + // prevent read-during-write hazard when accessing tags/data block RAMs + wire rdw_fill_hazard = valid_st0 && is_fill_st0; + wire rdw_write_hazard = valid_st0 && is_write_st0 && ~creq_rw; + + // determine which queue to pop next in priority order + wire mshr_grant = !flush_enable; + wire mshr_enable = mshr_grant && mshr_valid; + + wire mrsq_grant = !flush_enable && !mshr_enable; + wire mrsq_enable = mrsq_grant && mem_rsp_valid; + wire creq_grant = !flush_enable && !mshr_enable && !mrsq_enable; + + wire creq_enable = creq_grant && creq_valid; + + assign mshr_ready = mshr_grant + && !rdw_fill_hazard // prevent read-during-write hazard + && !crsq_stall; // ensure core_rsp_queue not full + + + assign mem_rsp_ready = mrsq_grant + && !crsq_stall; // ensure core_rsp_queue not full + + assign creq_ready = creq_grant + && !rdw_write_hazard // prevent read-during-write hazard + && !mreq_alm_full // ensure mem_req_queue not full + && !mshr_alm_full // ensure mshr not full + && !crsq_stall; // ensure core_rsp_queue not full + + wire flush_fire = flush_enable; + wire mshr_fire = mshr_valid && mshr_ready; + wire mem_rsp_fire = mem_rsp_valid && mem_rsp_ready; + wire creq_fire = creq_valid && creq_ready; + +`ifdef DBG_CACHE_REQ_INFO + if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin + assign {debug_wid_sel, debug_pc_sel} = mshr_enable ? mshr_tag[0][`CACHE_REQ_INFO_RNG] : creq_tag[0][`CACHE_REQ_INFO_RNG]; + end else begin + assign {debug_wid_sel, debug_pc_sel} = 0; + end +`endif + + wire [`CACHE_LINE_WIDTH-1:0] wdata_sel; + assign wdata_sel[(NUM_PORTS * `WORD_WIDTH)-1:0] = (mem_rsp_valid || !WRITE_ENABLE) ? mem_rsp_data[(NUM_PORTS * `WORD_WIDTH)-1:0] : creq_data; + for (genvar i = NUM_PORTS * `WORD_WIDTH; i < `CACHE_LINE_WIDTH; ++i) begin + assign wdata_sel[i] = mem_rsp_data[i]; + end + + VX_pipe_register #( + .DATAW (1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH + NUM_PORTS * (WORD_SELECT_BITS + WORD_SIZE + `REQS_BITS + 1 + CORE_TAG_WIDTH) + MSHR_ADDR_WIDTH), + .RESETW (1) + ) pipe_reg0 ( + .clk (clk), + .reset (reset), + .enable (!crsq_stall), + .data_in ({ + flush_fire || mshr_fire || mem_rsp_fire || creq_fire, + flush_enable, + mshr_enable, + mrsq_enable, + creq_enable && ~creq_rw, + creq_enable && creq_rw, + flush_enable ? `LINE_ADDR_WIDTH'(flush_addr) : (mshr_valid ? mshr_addr : (mem_rsp_valid ? mem_rsp_addr : creq_addr)), + wdata_sel, + mshr_valid ? mshr_wsel : creq_wsel, + creq_byteen, + mshr_valid ? mshr_tid : creq_tid, + mshr_valid ? mshr_pmask : creq_pmask, + mshr_valid ? mshr_tag : creq_tag, + mshr_valid ? mshr_dequeue_id : mem_rsp_id + }), + .data_out ({valid_st0, is_flush_st0, is_mshr_st0, is_fill_st0, is_read_st0, is_write_st0, addr_st0, wdata_st0, wsel_st0, byteen_st0, req_tid_st0, pmask_st0, tag_st0, mshr_id_st0}) + ); + +`ifdef DBG_CACHE_REQ_INFO + if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin + assign {debug_wid_st0, debug_pc_st0} = tag_st0[0][`CACHE_REQ_INFO_RNG]; + end else begin + assign {debug_wid_st0, debug_pc_st0} = 0; + end +`endif + + wire do_fill_st0 = valid_st0 && is_fill_st0; + wire do_flush_st0 = valid_st0 && is_flush_st0; + wire do_lookup_st0 = valid_st0 && ~(is_fill_st0 || is_flush_st0); + + wire tag_match_st0; + + VX_tag_access #( + .BANK_ID (BANK_ID), + .CACHE_ID (CACHE_ID), + .CACHE_SIZE (CACHE_SIZE), + .CACHE_LINE_SIZE (CACHE_LINE_SIZE), + .NUM_BANKS (NUM_BANKS), + .WORD_SIZE (WORD_SIZE), + .BANK_ADDR_OFFSET (BANK_ADDR_OFFSET) + ) tag_access ( + .clk (clk), + .reset (reset), + + `ifdef DBG_CACHE_REQ_INFO + .debug_pc (debug_pc_st0), + .debug_wid (debug_wid_st0), + `endif + .stall (crsq_stall), + + // read/Fill + .lookup (do_lookup_st0), + .addr (addr_st0), + .fill (do_fill_st0), + .flush (do_flush_st0), + .tag_match (tag_match_st0) + ); + + // we have a core request hit + assign miss_st0 = (is_read_st0 || is_write_st0) && ~tag_match_st0; + + wire [MSHR_ADDR_WIDTH-1:0] mshr_id_a_st0 = (is_read_st0 || is_write_st0) ? mshr_alloc_id : mshr_id_st0; + + VX_pipe_register #( + .DATAW (1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH + NUM_PORTS * (WORD_SELECT_BITS + WORD_SIZE + `REQS_BITS + 1 + CORE_TAG_WIDTH) + MSHR_ADDR_WIDTH + 1), + .RESETW (1) + ) pipe_reg1 ( + .clk (clk), + .reset (reset), + .enable (!crsq_stall), + .data_in ({valid_st0, is_mshr_st0, is_fill_st0, is_read_st0, is_write_st0, miss_st0, addr_st0, wdata_st0, wsel_st0, byteen_st0, req_tid_st0, pmask_st0, tag_st0, mshr_id_a_st0, mshr_pending_st0}), + .data_out ({valid_st1, is_mshr_st1, is_fill_st1, is_read_st1, is_write_st1, miss_st1, addr_st1, wdata_st1, wsel_st1, byteen_st1, req_tid_st1, pmask_st1, tag_st1, mshr_id_st1, mshr_pending_st1}) + ); + +`ifdef DBG_CACHE_REQ_INFO + if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin + assign {debug_wid_st1, debug_pc_st1} = tag_st1[0][`CACHE_REQ_INFO_RNG]; + end else begin + assign {debug_wid_st1, debug_pc_st1} = 0; + end +`endif + + wire do_read_st0 = valid_st0 && is_read_st0; + wire do_read_st1 = valid_st1 && is_read_st1; + wire do_fill_st1 = valid_st1 && is_fill_st1; + wire do_write_st1 = valid_st1 && is_write_st1; + wire do_mshr_st1 = valid_st1 && is_mshr_st1; + + wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] creq_data_st1 = wdata_st1[0 +: NUM_PORTS * `WORD_WIDTH]; + `UNUSED_VAR (wdata_st1) + + VX_data_access #( + .BANK_ID (BANK_ID), + .CACHE_ID (CACHE_ID), + .CACHE_SIZE (CACHE_SIZE), + .CACHE_LINE_SIZE(CACHE_LINE_SIZE), + .NUM_BANKS (NUM_BANKS), + .NUM_PORTS (NUM_PORTS), + .WORD_SIZE (WORD_SIZE), + .WRITE_ENABLE (WRITE_ENABLE) + ) data_access ( + .clk (clk), + .reset (reset), + + `ifdef DBG_CACHE_REQ_INFO + .debug_pc (debug_pc_st1), + .debug_wid (debug_wid_st1), + `endif + .stall (crsq_stall), + + .read (do_read_st1 || do_mshr_st1), + .fill (do_fill_st1), + .write (do_write_st1 && !miss_st1), + .addr (addr_st1), + .wsel (wsel_st1), + .pmask (pmask_st1), + .byteen (byteen_st1), + .fill_data (wdata_st1), + .write_data (creq_data_st1), + .read_data (rdata_st1) + ); + + wire mshr_allocate = do_read_st0 && !crsq_stall; + wire mshr_replay = do_fill_st0 && !crsq_stall; + wire mshr_lookup = mshr_allocate; + wire mshr_release = do_read_st1 && !miss_st1 && !crsq_stall; + + VX_pending_size #( + .SIZE (MSHR_SIZE) + ) mshr_pending_size ( + .clk (clk), + .reset (reset), + .incr (creq_fire && ~creq_rw), + .decr (mshr_fire || mshr_release), + .full (mshr_alm_full), + `UNUSED_PIN (size), + `UNUSED_PIN (empty) + ); + + VX_miss_resrv #( + .BANK_ID (BANK_ID), + .CACHE_ID (CACHE_ID), + .CACHE_LINE_SIZE (CACHE_LINE_SIZE), + .NUM_BANKS (NUM_BANKS), + .NUM_PORTS (NUM_PORTS), + .WORD_SIZE (WORD_SIZE), + .NUM_REQS (NUM_REQS), + .MSHR_SIZE (MSHR_SIZE), + .CORE_TAG_WIDTH (CORE_TAG_WIDTH) + ) miss_resrv ( + .clk (clk), + .reset (reset), + + `ifdef DBG_CACHE_REQ_INFO + .deq_debug_pc (debug_pc_sel), + .deq_debug_wid (debug_wid_sel), + .lkp_debug_pc (debug_pc_st0), + .lkp_debug_wid (debug_wid_st0), + .rel_debug_pc (debug_pc_st1), + .rel_debug_wid (debug_wid_st1), + `endif + + // allocate + .allocate_valid (mshr_allocate), + .allocate_addr (addr_st0), + .allocate_data ({wsel_st0, tag_st0, req_tid_st0, pmask_st0}), + .allocate_id (mshr_alloc_id), + `UNUSED_PIN (allocate_ready), + + // lookup + .lookup_valid (mshr_lookup), + .lookup_replay (mshr_replay), + .lookup_id (mshr_alloc_id), + .lookup_addr (addr_st0), + .lookup_match (mshr_pending_st0), + + // fill + .fill_valid (mem_rsp_fire), + .fill_id (mem_rsp_id), + .fill_addr (mem_rsp_addr), + + // dequeue + .dequeue_valid (mshr_valid), + .dequeue_id (mshr_dequeue_id), + .dequeue_addr (mshr_addr), + .dequeue_data ({mshr_wsel, mshr_tag, mshr_tid, mshr_pmask}), + .dequeue_ready (mshr_ready), + + // release + .release_valid (mshr_release), + .release_id (mshr_id_st1) + ); + + // Enqueue core response + + wire [NUM_PORTS-1:0] crsq_pmask; + wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] crsq_data; + wire [NUM_PORTS-1:0][`REQS_BITS-1:0] crsq_tid; + wire [NUM_PORTS-1:0][CORE_TAG_WIDTH-1:0] crsq_tag; + + assign crsq_valid = (do_read_st1 && !miss_st1) + || do_mshr_st1; + + assign crsq_stall = crsq_valid && !crsq_ready; + + assign crsq_pmask = pmask_st1; + assign crsq_tid = req_tid_st1; + assign crsq_data = rdata_st1; + assign crsq_tag = tag_st1; + + VX_elastic_buffer #( + .DATAW (NUM_PORTS * (CORE_TAG_WIDTH + 1 + `WORD_WIDTH + `REQS_BITS)), + .SIZE (CRSQ_SIZE), + .OUT_REG (1) + ) core_rsp_req ( + .clk (clk), + .reset (reset), + .valid_in (crsq_valid), + .data_in ({crsq_tag, crsq_pmask, crsq_data, crsq_tid}), + .ready_in (crsq_ready), + .valid_out (core_rsp_valid), + .data_out ({core_rsp_tag, core_rsp_pmask, core_rsp_data, core_rsp_tid}), + .ready_out (core_rsp_ready) + ); + + // Enqueue memory request + + wire mreq_push, mreq_pop, mreq_empty; + wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] mreq_data; + wire [NUM_PORTS-1:0][WORD_SIZE-1:0] mreq_byteen; + wire [NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] mreq_wsel; + wire [NUM_PORTS-1:0] mreq_pmask; + wire [`LINE_ADDR_WIDTH-1:0] mreq_addr; + wire [MSHR_ADDR_WIDTH-1:0] mreq_id; + wire mreq_rw; + + assign mreq_push = (do_read_st1 && miss_st1 && !mshr_pending_st1) + || do_write_st1; + + assign mreq_pop = mem_req_valid && mem_req_ready; + + assign mreq_rw = WRITE_ENABLE && is_write_st1; + assign mreq_addr = addr_st1; + assign mreq_id = mshr_id_st1; + assign mreq_pmask= pmask_st1; + assign mreq_wsel = wsel_st1; + assign mreq_byteen = byteen_st1; + assign mreq_data = creq_data_st1; + + VX_fifo_queue #( + .DATAW (1 + `LINE_ADDR_WIDTH + MSHR_ADDR_WIDTH + NUM_PORTS * (1 + WORD_SIZE + WORD_SELECT_BITS + `WORD_WIDTH)), + .SIZE (MREQ_SIZE), + .ALM_FULL (MREQ_SIZE-2), + .OUT_REG (1 == NUM_BANKS) + ) mem_req_queue ( + .clk (clk), + .reset (reset), + .push (mreq_push), + .pop (mreq_pop), + .data_in ({mreq_rw, mreq_addr, mreq_id, mreq_pmask, mreq_byteen, mreq_wsel, mreq_data}), + .data_out ({mem_req_rw, mem_req_addr, mem_req_id, mem_req_pmask, mem_req_byteen, mem_req_wsel, mem_req_data}), + .empty (mreq_empty), + .alm_full (mreq_alm_full), + `UNUSED_PIN (full), + `UNUSED_PIN (alm_empty), + `UNUSED_PIN (size) + ); + + assign mem_req_valid = !mreq_empty; + +/////////////////////////////////////////////////////////////////////////////// + + `SCOPE_ASSIGN (valid_st0, valid_st0); + `SCOPE_ASSIGN (valid_st1, valid_st1); + `SCOPE_ASSIGN (is_fill_st0, is_fill_st0); + `SCOPE_ASSIGN (is_mshr_st0, is_mshr_st0); + `SCOPE_ASSIGN (miss_st0, miss_st0); + `SCOPE_ASSIGN (crsq_stall, crsq_stall); + `SCOPE_ASSIGN (mreq_alm_full, mreq_alm_full); + `SCOPE_ASSIGN (mshr_alm_full, mshr_alm_full); + `SCOPE_ASSIGN (addr_st0, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID)); + `SCOPE_ASSIGN (addr_st1, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID)); + +`ifdef PERF_ENABLE + assign perf_read_misses = do_read_st1 && miss_st1; + assign perf_write_misses = do_write_st1 && miss_st1; + assign perf_pipe_stalls = crsq_stall || mreq_alm_full || mshr_alm_full; + assign perf_mshr_stalls = mshr_alm_full; +`endif + +`ifdef DBG_PRINT_CACHE_BANK + wire crsq_fire = crsq_valid && crsq_ready; + wire pipeline_stall = (mshr_valid || mem_rsp_valid || creq_valid) + && ~(mshr_fire || mem_rsp_fire || creq_fire); + + always @(posedge clk) begin + if (pipeline_stall) begin + dpi_trace("%d: *** cache%0d:%0d stall: crsq=%b, mreq=%b, mshr=%b\n", $time, CACHE_ID, BANK_ID, crsq_stall, mreq_alm_full, mshr_alm_full); + end + if (flush_enable) begin + dpi_trace("%d: cache%0d:%0d flush: addr=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(flush_addr, BANK_ID)); + end + if (mem_rsp_fire) begin + dpi_trace("%d: cache%0d:%0d fill-rsp: addr=%0h, id=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(mem_rsp_addr, BANK_ID), mem_rsp_id, mem_rsp_data); + end + if (mshr_fire) begin + dpi_trace("%d: cache%0d:%0d mshr-pop: addr=%0h, tag=%0h, pmask=%b, tid=%0d, wid=%0d, PC=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(mshr_addr, BANK_ID), mshr_tag, mshr_pmask, mshr_tid, debug_wid_sel, debug_pc_sel); + end + if (creq_fire) begin + if (creq_rw) + dpi_trace("%d: cache%0d:%0d core-wr-req: addr=%0h, tag=%0h, pmask=%b, tid=%0d, byteen=%b, data=%0h, wid=%0d, PC=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(creq_addr, BANK_ID), creq_tag, creq_pmask, creq_tid, creq_byteen, creq_data, debug_wid_sel, debug_pc_sel); + else + dpi_trace("%d: cache%0d:%0d core-rd-req: addr=%0h, tag=%0h, pmask=%b, tid=%0d, byteen=%b, wid=%0d, PC=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(creq_addr, BANK_ID), creq_tag, creq_pmask, creq_tid, creq_byteen, debug_wid_sel, debug_pc_sel); + end + if (crsq_fire) begin + dpi_trace("%d: cache%0d:%0d core-rsp: addr=%0h, tag=%0h, pmask=%b, tid=%0d, data=%0h, wid=%0d, PC=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID), crsq_tag, crsq_pmask, crsq_tid, crsq_data, debug_wid_st1, debug_pc_st1); + end + if (mreq_push) begin + if (is_write_st1) + dpi_trace("%d: cache%0d:%0d writeback: addr=%0h, data=%0h, byteen=%b, wid=%0d, PC=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(mreq_addr, BANK_ID), mreq_data, mreq_byteen, debug_wid_st1, debug_pc_st1); + else + dpi_trace("%d: cache%0d:%0d fill-req: addr=%0h, id=%0d, wid=%0d, PC=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(mreq_addr, BANK_ID), mreq_id, debug_wid_st1, debug_pc_st1); + end + end +`endif + +endmodule \ No newline at end of file diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v deleted file mode 100644 index e149340c..00000000 --- a/hw/rtl/cache/VX_bank.v +++ /dev/null @@ -1,585 +0,0 @@ -`include "VX_cache_define.vh" - -module VX_bank #( - parameter CACHE_ID = 0, - parameter BANK_ID = 0, - - // Number of Word requests per cycle - parameter NUM_REQS = 1, - - // Size of cache in bytes - parameter CACHE_SIZE = 1, - // Size of line inside a bank in bytes - parameter CACHE_LINE_SIZE = 1, - // Number of bankS - parameter NUM_BANKS = 1, - // Number of ports per banks - parameter NUM_PORTS = 1, - // Size of a word in bytes - parameter WORD_SIZE = 1, - - // Core Request Queue Size - parameter CREQ_SIZE = 1, - // Core Response Queue Size - parameter CRSQ_SIZE = 1, - // Miss Reserv Queue Knob - parameter MSHR_SIZE = 1, - // Memory Request Queue Size - parameter MREQ_SIZE = 1, - - // Enable cache writeable - parameter WRITE_ENABLE = 1, - - // core request tag size - parameter CORE_TAG_WIDTH = 1, - - // size of tag id in core request tag - parameter CORE_TAG_ID_BITS = 0, - - // bank offset from beginning of index range - parameter BANK_ADDR_OFFSET = 0 -) ( - `SCOPE_IO_VX_bank - - input wire clk, - input wire reset, - -`ifdef PERF_ENABLE - output wire perf_read_misses, - output wire perf_write_misses, - output wire perf_mshr_stalls, - output wire perf_pipe_stalls, -`endif - - // Core Request - input wire core_req_valid, - input wire [NUM_PORTS-1:0] core_req_pmask, - input wire [NUM_PORTS-1:0][`UP(`WORD_SELECT_BITS)-1:0] core_req_wsel, - input wire [NUM_PORTS-1:0][WORD_SIZE-1:0] core_req_byteen, - input wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] core_req_data, - input wire [NUM_PORTS-1:0][`REQS_BITS-1:0] core_req_tid, - input wire core_req_rw, - input wire [`LINE_ADDR_WIDTH-1:0] core_req_addr, - input wire [CORE_TAG_WIDTH-1:0] core_req_tag, - output wire core_req_ready, - - // Core Response - output wire core_rsp_valid, - output wire [NUM_PORTS-1:0] core_rsp_pmask, - output wire [NUM_PORTS-1:0][`REQS_BITS-1:0] core_rsp_tid, - output wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] core_rsp_data, - output wire [CORE_TAG_WIDTH-1:0] core_rsp_tag, - input wire core_rsp_ready, - - // Memory request - output wire mem_req_valid, - output wire mem_req_rw, - output wire [CACHE_LINE_SIZE-1:0] mem_req_byteen, - output wire [`LINE_ADDR_WIDTH-1:0] mem_req_addr, - output wire [`CACHE_LINE_WIDTH-1:0] mem_req_data, - input wire mem_req_ready, - - // Memory response - input wire mem_rsp_valid, - input wire [`LINE_ADDR_WIDTH-1:0] mem_rsp_addr, - input wire [`CACHE_LINE_WIDTH-1:0] mem_rsp_data, - output wire mem_rsp_ready, - - // flush - input wire flush_enable, - input wire [`LINE_SELECT_BITS-1:0] flush_addr -); - - `UNUSED_PARAM (CORE_TAG_ID_BITS) - -`ifdef DBG_CACHE_REQ_INFO -`IGNORE_WARNINGS_BEGIN - wire [31:0] debug_pc_sel, debug_pc_st0, debug_pc_st1; - wire [`NW_BITS-1:0] debug_wid_sel, debug_wid_st0, debug_wid_st1; -`IGNORE_WARNINGS_END -`endif - - wire [NUM_PORTS-1:0] creq_pmask; - wire [NUM_PORTS-1:0][`UP(`WORD_SELECT_BITS)-1:0] creq_wsel; - wire [NUM_PORTS-1:0][WORD_SIZE-1:0] creq_byteen; - wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] creq_data; - wire [NUM_PORTS-1:0][`REQS_BITS-1:0] creq_tid; - wire creq_rw; - wire [`LINE_ADDR_WIDTH-1:0] creq_addr; - wire [CORE_TAG_WIDTH-1:0] creq_tag; - - wire creq_out_valid, creq_out_ready; - - VX_elastic_buffer #( - .DATAW (CORE_TAG_WIDTH + 1 + `LINE_ADDR_WIDTH + (1 + `UP(`WORD_SELECT_BITS) + WORD_SIZE + `WORD_WIDTH + `REQS_BITS) * NUM_PORTS), - .SIZE (CREQ_SIZE), - .OUTPUT_REG (CREQ_SIZE > 2) - ) core_req_queue ( - .clk (clk), - .reset (reset), - .ready_in (core_req_ready), - .valid_in (core_req_valid), - .data_in ({core_req_tag, core_req_rw, core_req_addr, core_req_pmask, core_req_wsel, core_req_byteen, core_req_data, core_req_tid}), - .data_out ({creq_tag, creq_rw, creq_addr, creq_pmask, creq_wsel, creq_byteen, creq_data, creq_tid}), - .ready_out (creq_out_ready), - .valid_out (creq_out_valid) - ); - - wire mshr_alm_full; - wire mshr_pop; - wire mshr_valid; - wire [`LINE_ADDR_WIDTH-1:0] mshr_addr; - wire [CORE_TAG_WIDTH-1:0] mshr_tag; - wire [NUM_PORTS-1:0] mshr_pmask; - wire [NUM_PORTS-1:0][`UP(`WORD_SELECT_BITS)-1:0] mshr_wsel; - wire [NUM_PORTS-1:0][`REQS_BITS-1:0] mshr_tid; - - wire [`LINE_ADDR_WIDTH-1:0] addr_st0, addr_st1; - wire mem_rw_st0, mem_rw_st1; - wire [NUM_PORTS-1:0][`UP(`WORD_SELECT_BITS)-1:0] wsel_st0, wsel_st1; - wire [NUM_PORTS-1:0][WORD_SIZE-1:0] byteen_st0, byteen_st1; - wire [NUM_PORTS-1:0][`REQS_BITS-1:0] req_tid_st0, req_tid_st1; - wire [NUM_PORTS-1:0] pmask_st0, pmask_st1; - wire [`CACHE_LINE_WIDTH-1:0] rdata_st1; - wire [`CACHE_LINE_WIDTH-1:0] wdata_st0, wdata_st1; - wire [CORE_TAG_WIDTH-1:0] tag_st0, tag_st1; - wire valid_st0, valid_st1; - wire is_fill_st0, is_fill_st1; - wire is_mshr_st0, is_mshr_st1; - wire miss_st0, miss_st1; - wire prev_miss_dep_st0; - wire force_miss_st0, force_miss_st1; - wire not_same_prev_mshr_st0, not_same_prev_mshr_st1; - wire writeen_unqual_st0, writeen_unqual_st1; - wire incoming_fill_unqual_st0, incoming_fill_unqual_st1; - wire mshr_pending_st0; - wire is_flush_st0; - - wire crsq_in_valid, crsq_in_ready, crsq_in_stall; - wire mreq_alm_full; - - wire creq_out_fire = creq_out_valid && creq_out_ready; - wire crsq_in_fire = crsq_in_valid && crsq_in_ready; - - VX_pending_size #( - .SIZE (MSHR_SIZE) - ) mshr_pending_size ( - .clk (clk), - .reset (reset), - .push (creq_out_fire && !creq_rw), - .pop (crsq_in_fire), - .full (mshr_alm_full), - `UNUSED_PIN (empty), - `UNUSED_PIN (size) - ); - - // determine which queue to pop next in priority order - wire mshr_grant = !mreq_alm_full; // ensure memory request queue not full (deadlock prevention) - wire mshr_enable = mshr_grant && mshr_valid; - - wire mrsq_grant = !mshr_enable; - wire mrsq_enable = mrsq_grant && mem_rsp_valid; - - wire creq_grant = !mshr_enable && !mrsq_enable && !flush_enable; - - wire is_miss_st1 = (miss_st1 || force_miss_st1); - - assign mshr_pop = mshr_enable - && !(valid_st1 && is_mshr_st1 && is_miss_st1) // do not schedule another mshr request if the previous one missed - && !crsq_in_stall; // ensure core response ready - - assign creq_out_ready = creq_grant - && !mreq_alm_full // ensure memory request ready - && !mshr_alm_full // ensure mshr enqueue ready - && !crsq_in_stall; // ensure core response ready - - assign mem_rsp_ready = mrsq_grant - && !crsq_in_stall; // ensure core response ready - - wire mem_rsp_fire = mem_rsp_valid && mem_rsp_ready; - -`ifdef DBG_CACHE_REQ_INFO - if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin - assign {debug_wid_sel, debug_pc_sel} = mshr_enable ? mshr_tag[`CACHE_REQ_INFO_RNG] : creq_tag[`CACHE_REQ_INFO_RNG]; - end else begin - assign {debug_wid_sel, debug_pc_sel} = 0; - end -`endif - - wire [`CACHE_LINE_WIDTH-1:0] creq_line_data; - - if (`WORDS_PER_LINE > 1) begin - if (NUM_PORTS > 1) begin - reg [`CACHE_LINE_WIDTH-1:0] creq_line_data_r; - always @(*) begin - creq_line_data_r = 'x; - for (integer p = 0; p < NUM_PORTS; p++) begin - if (creq_pmask[p]) begin - creq_line_data_r[creq_wsel[p] * `WORD_WIDTH +: `WORD_WIDTH] = creq_data[p]; - end - end - end - assign creq_line_data = creq_line_data_r; - end else begin - assign creq_line_data = {`WORDS_PER_LINE{creq_data}}; - end - end else begin - assign creq_line_data = creq_data; - end - - VX_pipe_register #( - .DATAW (1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH + (`UP(`WORD_SELECT_BITS) + WORD_SIZE + `REQS_BITS + 1) * NUM_PORTS + CORE_TAG_WIDTH + 1), - .RESETW (1) - ) pipe_reg0 ( - .clk (clk), - .reset (reset), - .enable (!crsq_in_stall), - .data_in ({ - flush_enable || mshr_pop || mem_rsp_fire || creq_out_fire, - flush_enable, - mshr_enable, - mrsq_enable || flush_enable, - mshr_enable ? 1'b0 : creq_rw, - mshr_enable ? mshr_addr : (mem_rsp_valid ? mem_rsp_addr : (flush_enable ? `LINE_ADDR_WIDTH'(flush_addr) : creq_addr)), - (mem_rsp_valid || !WRITE_ENABLE) ? mem_rsp_data : creq_line_data, - mshr_enable ? mshr_wsel : creq_wsel, - creq_byteen, - mshr_enable ? mshr_tid : creq_tid, - mshr_enable ? mshr_pmask : creq_pmask, - mshr_enable ? mshr_tag : creq_tag - }), - .data_out ({valid_st0, is_flush_st0, is_mshr_st0, is_fill_st0, mem_rw_st0, addr_st0, wdata_st0, wsel_st0, byteen_st0, req_tid_st0, pmask_st0, tag_st0}) - ); - -`ifdef DBG_CACHE_REQ_INFO - if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin - assign {debug_wid_st0, debug_pc_st0} = tag_st0[`CACHE_REQ_INFO_RNG]; - end else begin - assign {debug_wid_st0, debug_pc_st0} = 0; - end -`endif - - wire do_lookup_st0 = valid_st0 && ~is_fill_st0; - wire do_fill_st0 = valid_st0 && is_fill_st0 && !crsq_in_stall; - - wire tag_match_st0; - - VX_tag_access #( - .BANK_ID (BANK_ID), - .CACHE_ID (CACHE_ID), - .CACHE_SIZE (CACHE_SIZE), - .CACHE_LINE_SIZE (CACHE_LINE_SIZE), - .NUM_BANKS (NUM_BANKS), - .WORD_SIZE (WORD_SIZE), - .BANK_ADDR_OFFSET (BANK_ADDR_OFFSET) - ) tag_access ( - .clk (clk), - .reset (reset), - - `ifdef DBG_CACHE_REQ_INFO - .debug_pc (debug_pc_st0), - .debug_wid (debug_wid_st0), - `endif - - // read/Fill - .lookup (do_lookup_st0), - .addr (addr_st0), - .fill (do_fill_st0), - .is_flush (is_flush_st0), - .tag_match (tag_match_st0) - ); - - // we had a miss with prior request for the current address - assign prev_miss_dep_st0 = valid_st1 && is_miss_st1 && (addr_st0 == addr_st1); - - // we have a core request hit - assign miss_st0 = !is_fill_st0 && !tag_match_st0; - - // force a miss to ensure commit order when a new request has pending previous requests to same block - // also force a miss for mshr requests when previous request was a missed - assign force_miss_st0 = (!is_fill_st0 && !is_mshr_st0 && (mshr_pending_st0 || prev_miss_dep_st0)) - || (is_mshr_st0 && valid_st1 && is_mshr_st1 && is_miss_st1); - - // previous mshr request doesn't have same address - assign not_same_prev_mshr_st0 = valid_st1 && is_mshr_st1 && (addr_st1 != addr_st0); - - // enable write when we have a fill request that is not redundant - assign writeen_unqual_st0 = is_fill_st0 && !tag_match_st0; - - // check if incoming memory response match current address - assign incoming_fill_unqual_st0 = mem_rsp_valid && (addr_st0 == mem_rsp_addr); - - VX_pipe_register #( - .DATAW (1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH + (`UP(`WORD_SELECT_BITS) + WORD_SIZE + `REQS_BITS + 1) * NUM_PORTS + CORE_TAG_WIDTH), - .RESETW (1) - ) pipe_reg1 ( - .clk (clk), - .reset (reset), - .enable (!crsq_in_stall), - .data_in ({valid_st0, is_mshr_st0, is_fill_st0, writeen_unqual_st0, incoming_fill_unqual_st0, miss_st0, force_miss_st0, mem_rw_st0, not_same_prev_mshr_st0, addr_st0, wdata_st0, wsel_st0, byteen_st0, req_tid_st0, pmask_st0, tag_st0}), - .data_out ({valid_st1, is_mshr_st1, is_fill_st1, writeen_unqual_st1, incoming_fill_unqual_st1, miss_st1, force_miss_st1, mem_rw_st1, not_same_prev_mshr_st1, addr_st1, wdata_st1, wsel_st1, byteen_st1, req_tid_st1, pmask_st1, tag_st1}) - ); - -`ifdef DBG_CACHE_REQ_INFO - if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin - assign {debug_wid_st1, debug_pc_st1} = tag_st1[`CACHE_REQ_INFO_RNG]; - end else begin - assign {debug_wid_st1, debug_pc_st1} = 0; - end -`endif - - wire writeen_st1 = (WRITE_ENABLE && !is_fill_st1 && mem_rw_st1 && ~is_miss_st1) - || writeen_unqual_st1; - - wire readen_st1 = !is_fill_st1 && !mem_rw_st1; - - wire crsq_push_st1 = readen_st1 && ~is_miss_st1; - - wire mshr_push_st1 = readen_st1 && is_miss_st1; - - wire incoming_fill_st1 = (mem_rsp_valid && (addr_st1 == mem_rsp_addr)) - || incoming_fill_unqual_st1; - - wire do_writeback_st1 = !is_fill_st1 && mem_rw_st1; - - wire mreq_push_st1 = (readen_st1 && miss_st1 && (~force_miss_st1 || not_same_prev_mshr_st1) && !incoming_fill_st1) - || do_writeback_st1; - - wire [`WORDS_PER_LINE-1:0][WORD_SIZE-1:0] line_byteen_st1; - - if (`WORDS_PER_LINE > 1) begin - reg [CACHE_LINE_SIZE-1:0] line_byteen_r; - always @(*) begin - line_byteen_r = 0; - for (integer p = 0; p < NUM_PORTS; p++) begin - if ((NUM_PORTS == 1) || pmask_st1[p]) begin - line_byteen_r[wsel_st1[p] * WORD_SIZE +: WORD_SIZE] = byteen_st1[p]; - end - end - end - assign line_byteen_st1 = line_byteen_r; - end else begin - assign line_byteen_st1 = byteen_st1; - end - - VX_data_access #( - .BANK_ID (BANK_ID), - .CACHE_ID (CACHE_ID), - .CACHE_SIZE (CACHE_SIZE), - .CACHE_LINE_SIZE(CACHE_LINE_SIZE), - .NUM_BANKS (NUM_BANKS), - .WORD_SIZE (WORD_SIZE), - .WRITE_ENABLE (WRITE_ENABLE) - ) data_access ( - .clk (clk), - .reset (reset), - - `ifdef DBG_CACHE_REQ_INFO - .debug_pc (debug_pc_st1), - .debug_wid (debug_wid_st1), - `endif - - .addr (addr_st1), - - // reading - .readen (valid_st1 && readen_st1), - .rdata (rdata_st1), - - // writing - .writeen (valid_st1 && writeen_st1), - .is_fill (is_fill_st1), - .byteen (line_byteen_st1), - .wdata (wdata_st1) - ); - - wire mshr_push = valid_st1 && mshr_push_st1; - wire mshr_dequeue = valid_st1 && is_mshr_st1 && !mshr_push_st1 && crsq_in_ready; - wire mshr_restore = is_mshr_st1; - - // push a missed request as 'ready' if it was a forced miss that actually had a hit - // or the fill request for this block is comming - wire mshr_init_ready_state = !miss_st1 || incoming_fill_unqual_st1; - - VX_miss_resrv #( - .BANK_ID (BANK_ID), - .CACHE_ID (CACHE_ID), - .CACHE_LINE_SIZE (CACHE_LINE_SIZE), - .NUM_BANKS (NUM_BANKS), - .NUM_PORTS (NUM_PORTS), - .WORD_SIZE (WORD_SIZE), - .NUM_REQS (NUM_REQS), - .MSHR_SIZE (MSHR_SIZE), - .ALM_FULL (MSHR_SIZE-2), - .CORE_TAG_WIDTH (CORE_TAG_WIDTH) - ) miss_resrv ( - .clk (clk), - .reset (reset), - - `ifdef DBG_CACHE_REQ_INFO - .deq_debug_pc (debug_pc_sel), - .deq_debug_wid (debug_wid_sel), - .enq_debug_pc (debug_pc_st1), - .enq_debug_wid (debug_wid_st1), - `endif - - // enqueue - .enqueue (mshr_push), - .enqueue_addr (addr_st1), - .enqueue_data ({wsel_st1, tag_st1, req_tid_st1, pmask_st1}), - .enqueue_is_mshr (mshr_restore), - .enqueue_as_ready (mshr_init_ready_state), - `UNUSED_PIN (enqueue_almfull), - `UNUSED_PIN (enqueue_full), - - // fill - .fill_start (mem_rsp_fire), - .fill_addr (mem_rsp_addr), - - // lookup - .lookup_addr (addr_st0), - .lookup_match (mshr_pending_st0), - .lookup_fill (do_fill_st0), - - // schedule - .schedule (mshr_pop), - .schedule_valid (mshr_valid), - .schedule_addr (mshr_addr), - .schedule_data ({mshr_wsel, mshr_tag, mshr_tid, mshr_pmask}), - - // dequeue - .dequeue (mshr_dequeue) - ); - - // Enqueue core response - - wire [NUM_PORTS-1:0] crsq_pmask; - wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] crsq_data; - wire [NUM_PORTS-1:0][`REQS_BITS-1:0] crsq_tid; - wire [CORE_TAG_WIDTH-1:0] crsq_tag; - - assign crsq_in_valid = valid_st1 && crsq_push_st1; - assign crsq_in_stall = crsq_in_valid && !crsq_in_ready; - - assign crsq_pmask = pmask_st1; - assign crsq_tid = req_tid_st1; - assign crsq_tag = tag_st1; - - if (`WORDS_PER_LINE > 1) begin - for (genvar p = 0; p < NUM_PORTS; ++p) begin - assign crsq_data[p] = rdata_st1[wsel_st1[p] * `WORD_WIDTH +: `WORD_WIDTH]; - end - end else begin - assign crsq_data = rdata_st1; - end - - VX_elastic_buffer #( - .DATAW (CORE_TAG_WIDTH + (1 + `WORD_WIDTH + `REQS_BITS) * NUM_PORTS), - .SIZE (CRSQ_SIZE), - .OUTPUT_REG (1 == NUM_BANKS) - ) core_rsp_req ( - .clk (clk), - .reset (reset), - .valid_in (crsq_in_valid), - .data_in ({crsq_tag, crsq_pmask, crsq_data, crsq_tid}), - .ready_in (crsq_in_ready), - .valid_out (core_rsp_valid), - .data_out ({core_rsp_tag, core_rsp_pmask, core_rsp_data, core_rsp_tid}), - .ready_out (core_rsp_ready) - ); - - // Enqueue memory request - - wire [CACHE_LINE_SIZE-1:0] mreq_byteen; - wire [`LINE_ADDR_WIDTH-1:0] mreq_addr; - wire [`CACHE_LINE_WIDTH-1:0] mreq_data; - wire mreq_push, mreq_pop, mreq_empty, mreq_rw; - - assign mreq_push = valid_st1 && mreq_push_st1; - - assign mreq_pop = mem_req_valid && mem_req_ready; - - assign mreq_rw = WRITE_ENABLE && do_writeback_st1; - assign mreq_byteen = mreq_rw ? line_byteen_st1 : {CACHE_LINE_SIZE{1'b1}}; - assign mreq_addr = addr_st1; - assign mreq_data = wdata_st1; - - VX_fifo_queue #( - .DATAW (1 + CACHE_LINE_SIZE + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH), - .SIZE (MREQ_SIZE), - .ALM_FULL (MREQ_SIZE-2) - ) mem_req_queue ( - .clk (clk), - .reset (reset), - .push (mreq_push), - .pop (mreq_pop), - .data_in ({mreq_rw, mreq_byteen, mreq_addr, mreq_data}), - .data_out ({mem_req_rw, mem_req_byteen, mem_req_addr, mem_req_data}), - .empty (mreq_empty), - .alm_full (mreq_alm_full), - `UNUSED_PIN (full), - `UNUSED_PIN (alm_empty), - `UNUSED_PIN (size) - ); - - assign mem_req_valid = !mreq_empty; - - `SCOPE_ASSIGN (valid_st0, valid_st0); - `SCOPE_ASSIGN (valid_st1, valid_st1); - `SCOPE_ASSIGN (is_fill_st0, is_fill_st0); - `SCOPE_ASSIGN (is_mshr_st0, is_mshr_st0); - `SCOPE_ASSIGN (miss_st0, miss_st0); - `SCOPE_ASSIGN (force_miss_st0, force_miss_st0); - `SCOPE_ASSIGN (mshr_push, mshr_push); - `SCOPE_ASSIGN (crsq_in_stall, crsq_in_stall); - `SCOPE_ASSIGN (mreq_alm_full, mreq_alm_full); - `SCOPE_ASSIGN (mshr_alm_full, mshr_alm_full); - `SCOPE_ASSIGN (addr_st0, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID)); - `SCOPE_ASSIGN (addr_st1, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID)); - -`ifdef PERF_ENABLE - assign perf_read_misses = valid_st1 && !is_fill_st1 && !is_mshr_st1 && miss_st1 && !mem_rw_st1; - assign perf_write_misses = valid_st1 && !is_fill_st1 && !is_mshr_st1 && miss_st1 && mem_rw_st1; - assign perf_pipe_stalls = crsq_in_stall || mreq_alm_full || mshr_alm_full; - assign perf_mshr_stalls = mshr_alm_full; -`endif - -`ifdef DBG_PRINT_CACHE_BANK - always @(posedge clk) begin - /*if (crsq_in_fire && (NUM_PORTS > 1) && $countones(crsq_pmask) > 1) begin - $display("%t: *** cache%0d:%0d multi-port-out: pmask=%b, addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, crsq_pmask, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID), crsq_tag); - end*/ - if (valid_st1 && !is_fill_st1 && miss_st1 && incoming_fill_st1) begin - $display("%t: *** cache%0d:%0d miss with incoming fill - addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID)); - assert(!is_mshr_st1); - end - if (crsq_in_stall || mreq_alm_full || mshr_alm_full) begin - $display("%t: *** cache%0d:%0d pipeline-stall: cwbq=%b, dwbq=%b, mshr=%b", $time, CACHE_ID, BANK_ID, crsq_in_stall, mreq_alm_full, mshr_alm_full); - end - if (flush_enable) begin - $display("%t: cache%0d:%0d flush: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(flush_addr, BANK_ID)); - end - if (mem_rsp_fire) begin - $display("%t: cache%0d:%0d fill-rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(mem_rsp_addr, BANK_ID), mem_rsp_data); - end - if (mshr_pop) begin - $display("%t: cache%0d:%0d mshr-pop: addr=%0h, tag=%0h, pmask=%b, tid=%0d, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(mshr_addr, BANK_ID), mshr_tag, mshr_pmask, mshr_tid, debug_wid_sel, debug_pc_sel); - end - if (creq_out_fire) begin - if (creq_rw) - $display("%t: cache%0d:%0d core-wr-req: addr=%0h, tag=%0h, pmask=%b, tid=%0d, byteen=%b, data=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(creq_addr, BANK_ID), creq_tag, creq_pmask, creq_tid, creq_byteen, creq_data, debug_wid_sel, debug_pc_sel); - else - $display("%t: cache%0d:%0d core-rd-req: addr=%0h, tag=%0h, pmask=%b, tid=%0d, byteen=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(creq_addr, BANK_ID), creq_tag, creq_pmask, creq_tid, creq_byteen, debug_wid_sel, debug_pc_sel); - end - if (crsq_in_fire) begin - $display("%t: cache%0d:%0d core-rsp: addr=%0h, tag=%0h, pmask=%b, tid=%0d, data=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID), crsq_tag, crsq_pmask, crsq_tid, crsq_data, debug_wid_st1, debug_pc_st1); - end - if (mreq_push) begin - if (do_writeback_st1) - $display("%t: cache%0d:%0d writeback: addr=%0h, data=%0h, byteen=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(mreq_addr, BANK_ID), mreq_data, mreq_byteen, debug_wid_st1, debug_pc_st1); - else - $display("%t: cache%0d:%0d fill-req: addr=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(mreq_addr, BANK_ID), debug_wid_st1, debug_pc_st1); - end - end -`endif - -endmodule \ No newline at end of file diff --git a/hw/rtl/cache/VX_cache.v b/hw/rtl/cache/VX_cache.sv similarity index 63% rename from hw/rtl/cache/VX_cache.v rename to hw/rtl/cache/VX_cache.sv index 9637e0b6..29e14892 100644 --- a/hw/rtl/cache/VX_cache.v +++ b/hw/rtl/cache/VX_cache.sv @@ -18,15 +18,15 @@ module VX_cache #( parameter WORD_SIZE = 4, // Core Request Queue Size - parameter CREQ_SIZE = 2, + parameter CREQ_SIZE = 0, // Core Response Queue Size parameter CRSQ_SIZE = 2, // Miss Reserv Queue Knob parameter MSHR_SIZE = 8, // Memory Response Queue Size - parameter MRSQ_SIZE = 4, + parameter MRSQ_SIZE = 0, // Memory Request Queue Size - parameter MREQ_SIZE = 2, + parameter MREQ_SIZE = 4, // Enable cache writeable parameter WRITE_ENABLE = 1, @@ -44,13 +44,15 @@ module VX_cache #( parameter BANK_ADDR_OFFSET = 0, // enable bypass for non-cacheable addresses - parameter NC_ENABLE = 0 + parameter NC_ENABLE = 0, + + parameter WORD_SELECT_BITS = `UP(`WORD_SELECT_BITS) ) ( `SCOPE_IO_VX_cache // PERF `ifdef PERF_ENABLE - VX_perf_cache_if perf_cache_if, + VX_perf_cache_if.master perf_cache_if, `endif input wire clk, @@ -91,6 +93,8 @@ module VX_cache #( `STATIC_ASSERT(NUM_BANKS <= NUM_REQS, ("invalid value")) `STATIC_ASSERT(NUM_PORTS <= NUM_BANKS, ("invalid value")) + localparam MSHR_ADDR_WIDTH = $clog2(MSHR_SIZE); + localparam MEM_TAG_IN_WIDTH = `BANK_SELECT_BITS + MSHR_ADDR_WIDTH; localparam CORE_TAG_X_WIDTH = CORE_TAG_WIDTH - NC_ENABLE; localparam CORE_TAG_ID_X_BITS = (CORE_TAG_ID_BITS != 0) ? (CORE_TAG_ID_BITS - NC_ENABLE) : CORE_TAG_ID_BITS; @@ -103,6 +107,117 @@ module VX_cache #( /////////////////////////////////////////////////////////////////////////// + wire mem_req_valid_sb; + wire mem_req_rw_sb; + wire [CACHE_LINE_SIZE-1:0] mem_req_byteen_sb; + wire [`MEM_ADDR_WIDTH-1:0] mem_req_addr_sb; + wire [`CACHE_LINE_WIDTH-1:0] mem_req_data_sb; + wire [MEM_TAG_WIDTH-1:0] mem_req_tag_sb; + wire mem_req_ready_sb; + + VX_skid_buffer #( + .DATAW (1+CACHE_LINE_SIZE+`MEM_ADDR_WIDTH+`CACHE_LINE_WIDTH+MEM_TAG_WIDTH), + .PASSTHRU (1 == NUM_BANKS) + ) mem_req_sbuf ( + .clk (clk), + .reset (reset), + .valid_in (mem_req_valid_sb), + .ready_in (mem_req_ready_sb), + .data_in ({mem_req_rw_sb, mem_req_byteen_sb, mem_req_addr_sb, mem_req_data_sb, mem_req_tag_sb}), + .data_out ({mem_req_rw, mem_req_byteen, mem_req_addr, mem_req_data, mem_req_tag}), + .valid_out (mem_req_valid), + .ready_out (mem_req_ready) + ); + + /////////////////////////////////////////////////////////////////////////// + + wire [`CORE_RSP_TAGS-1:0] core_rsp_valid_sb; + wire [NUM_REQS-1:0] core_rsp_tmask_sb; + wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data_sb; + wire [`CORE_RSP_TAGS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag_sb; + wire [`CORE_RSP_TAGS-1:0] core_rsp_ready_sb; + + if (CORE_TAG_ID_BITS != 0) begin + VX_skid_buffer #( + .DATAW (NUM_REQS + NUM_REQS*`WORD_WIDTH + CORE_TAG_WIDTH), + .PASSTHRU (1 == NUM_BANKS) + ) core_rsp_sbuf ( + .clk (clk), + .reset (reset), + .valid_in (core_rsp_valid_sb), + .ready_in (core_rsp_ready_sb), + .data_in ({core_rsp_tmask_sb, core_rsp_data_sb, core_rsp_tag_sb}), + .data_out ({core_rsp_tmask, core_rsp_data, core_rsp_tag}), + .valid_out (core_rsp_valid), + .ready_out (core_rsp_ready) + ); + end else begin + for (genvar i = 0; i < NUM_REQS; i++) begin + VX_skid_buffer #( + .DATAW (1 + `WORD_WIDTH + CORE_TAG_WIDTH), + .PASSTHRU (1 == NUM_BANKS) + ) core_rsp_sbuf ( + .clk (clk), + .reset (reset), + .valid_in (core_rsp_valid_sb[i]), + .ready_in (core_rsp_ready_sb[i]), + .data_in ({core_rsp_tmask_sb[i], core_rsp_data_sb[i], core_rsp_tag_sb[i]}), + .data_out ({core_rsp_tmask[i], core_rsp_data[i], core_rsp_tag[i]}), + .valid_out (core_rsp_valid[i]), + .ready_out (core_rsp_ready[i]) + ); + end + end + + + /////////////////////////////////////////////////////////////////////////// + + wire [NUM_PORTS-1:0][WORD_SIZE-1:0] mem_req_byteen_p; + wire [NUM_PORTS-1:0] mem_req_pmask_p; + wire [NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] mem_req_wsel_p; + wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] mem_req_data_p; + wire mem_req_rw_p; + + if (WRITE_ENABLE) begin + if (`WORDS_PER_LINE > 1) begin + reg [CACHE_LINE_SIZE-1:0] mem_req_byteen_r; + reg [`CACHE_LINE_WIDTH-1:0] mem_req_data_r; + + always @(*) begin + mem_req_byteen_r = 0; + mem_req_data_r = 'x; + for (integer i = 0; i < NUM_PORTS; ++i) begin + if ((1 == NUM_PORTS) || mem_req_pmask_p[i]) begin + mem_req_byteen_r[mem_req_wsel_p[i] * WORD_SIZE +: WORD_SIZE] = mem_req_byteen_p[i]; + mem_req_data_r[mem_req_wsel_p[i] * `WORD_WIDTH +: `WORD_WIDTH] = mem_req_data_p[i]; + end + end + end + + assign mem_req_rw_sb = mem_req_rw_p; + assign mem_req_byteen_sb = mem_req_byteen_r; + assign mem_req_data_sb = mem_req_data_r; + end else begin + `UNUSED_VAR (mem_req_pmask_p) + `UNUSED_VAR (mem_req_wsel_p) + assign mem_req_rw_sb = mem_req_rw_p; + assign mem_req_byteen_sb = mem_req_byteen_p; + assign mem_req_data_sb = mem_req_data_p; + end + end else begin + `UNUSED_VAR (mem_req_byteen_p) + `UNUSED_VAR (mem_req_pmask_p) + `UNUSED_VAR (mem_req_wsel_p) + `UNUSED_VAR (mem_req_data_p) + `UNUSED_VAR (mem_req_rw_p) + + assign mem_req_rw_sb = 0; + assign mem_req_byteen_sb = 'x; + assign mem_req_data_sb = 'x; + end + + /////////////////////////////////////////////////////////////////////////// + // Core request wire [NUM_REQS-1:0] core_req_valid_nc; wire [NUM_REQS-1:0] core_req_rw_nc; @@ -122,20 +237,23 @@ module VX_cache #( // Memory request wire mem_req_valid_nc; wire mem_req_rw_nc; - wire [CACHE_LINE_SIZE-1:0] mem_req_byteen_nc; wire [`MEM_ADDR_WIDTH-1:0] mem_req_addr_nc; - wire [`CACHE_LINE_WIDTH-1:0] mem_req_data_nc; - wire [`MEM_ADDR_WIDTH-1:0] mem_req_tag_nc; + wire [NUM_PORTS-1:0] mem_req_pmask_nc; + wire [NUM_PORTS-1:0][WORD_SIZE-1:0] mem_req_byteen_nc; + wire [NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] mem_req_wsel_nc; + wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] mem_req_data_nc; + wire [MEM_TAG_IN_WIDTH-1:0] mem_req_tag_nc; wire mem_req_ready_nc; // Memory response wire mem_rsp_valid_nc; wire [`CACHE_LINE_WIDTH-1:0] mem_rsp_data_nc; - wire [`MEM_ADDR_WIDTH-1:0] mem_rsp_tag_nc; - wire mem_rsp_ready_nc; + wire [MEM_TAG_IN_WIDTH-1:0] mem_rsp_tag_nc; + wire mem_rsp_ready_nc; if (NC_ENABLE) begin VX_nc_bypass #( + .NUM_PORTS (NUM_PORTS), .NUM_REQS (NUM_REQS), .NUM_RSP_TAGS (`CORE_RSP_TAGS), .NC_TAG_BIT (0), @@ -145,12 +263,12 @@ module VX_cache #( .CORE_TAG_IN_WIDTH (CORE_TAG_WIDTH), .MEM_ADDR_WIDTH (`MEM_ADDR_WIDTH), - .MEM_DATA_SIZE (CACHE_LINE_SIZE), - .MEM_TAG_IN_WIDTH (`MEM_ADDR_WIDTH), + .MEM_DATA_SIZE (CACHE_LINE_SIZE), + .MEM_TAG_IN_WIDTH (MEM_TAG_IN_WIDTH), .MEM_TAG_OUT_WIDTH (MEM_TAG_WIDTH) ) nc_bypass ( - .clk (clk), - .reset (reset), + .clk (clk), + .reset (reset), // Core request in .core_req_valid_in (core_req_valid), @@ -178,29 +296,33 @@ module VX_cache #( .core_rsp_ready_in (core_rsp_ready_nc), // Core response out - .core_rsp_valid_out (core_rsp_valid), - .core_rsp_tmask_out (core_rsp_tmask), - .core_rsp_data_out (core_rsp_data), - .core_rsp_tag_out (core_rsp_tag), - .core_rsp_ready_out (core_rsp_ready), + .core_rsp_valid_out (core_rsp_valid_sb), + .core_rsp_tmask_out (core_rsp_tmask_sb), + .core_rsp_data_out (core_rsp_data_sb), + .core_rsp_tag_out (core_rsp_tag_sb), + .core_rsp_ready_out (core_rsp_ready_sb), // Memory request in .mem_req_valid_in (mem_req_valid_nc), - .mem_req_rw_in (mem_req_rw_nc), - .mem_req_byteen_in (mem_req_byteen_nc), + .mem_req_rw_in (mem_req_rw_nc), .mem_req_addr_in (mem_req_addr_nc), + .mem_req_pmask_in (mem_req_pmask_nc), + .mem_req_byteen_in (mem_req_byteen_nc), + .mem_req_wsel_in (mem_req_wsel_nc), .mem_req_data_in (mem_req_data_nc), .mem_req_tag_in (mem_req_tag_nc), .mem_req_ready_in (mem_req_ready_nc), // Memory request out - .mem_req_valid_out (mem_req_valid), - .mem_req_rw_out (mem_req_rw), - .mem_req_byteen_out (mem_req_byteen), - .mem_req_addr_out (mem_req_addr), - .mem_req_data_out (mem_req_data), - .mem_req_tag_out (mem_req_tag), - .mem_req_ready_out (mem_req_ready), + .mem_req_valid_out (mem_req_valid_sb), + .mem_req_addr_out (mem_req_addr_sb), + .mem_req_rw_out (mem_req_rw_p), + .mem_req_pmask_out (mem_req_pmask_p), + .mem_req_byteen_out (mem_req_byteen_p), + .mem_req_wsel_out (mem_req_wsel_p), + .mem_req_data_out (mem_req_data_p), + .mem_req_tag_out (mem_req_tag_sb), + .mem_req_ready_out (mem_req_ready_sb), // Memory response in .mem_rsp_valid_in (mem_rsp_valid), @@ -223,19 +345,21 @@ module VX_cache #( assign core_req_tag_nc = core_req_tag; assign core_req_ready = core_req_ready_nc; - assign core_rsp_valid = core_rsp_valid_nc; - assign core_rsp_tmask = core_rsp_tmask_nc; - assign core_rsp_data = core_rsp_data_nc; - assign core_rsp_tag = core_rsp_tag_nc; - assign core_rsp_ready_nc = core_rsp_ready; + assign core_rsp_valid_sb = core_rsp_valid_nc; + assign core_rsp_tmask_sb = core_rsp_tmask_nc; + assign core_rsp_data_sb = core_rsp_data_nc; + assign core_rsp_tag_sb = core_rsp_tag_nc; + assign core_rsp_ready_nc = core_rsp_ready_sb; - assign mem_req_valid = mem_req_valid_nc; - assign mem_req_rw = mem_req_rw_nc; - assign mem_req_addr = mem_req_addr_nc; - assign mem_req_byteen = mem_req_byteen_nc; - assign mem_req_data = mem_req_data_nc; - assign mem_req_tag = mem_req_tag_nc; - assign mem_req_ready_nc = mem_req_ready; + assign mem_req_valid_sb = mem_req_valid_nc; + assign mem_req_addr_sb = mem_req_addr_nc; + assign mem_req_rw_p = mem_req_rw_nc; + assign mem_req_pmask_p = mem_req_pmask_nc; + assign mem_req_byteen_p = mem_req_byteen_nc; + assign mem_req_wsel_p = mem_req_wsel_nc; + assign mem_req_data_p = mem_req_data_nc; + assign mem_req_tag_sb = mem_req_tag_nc; + assign mem_req_ready_nc = mem_req_ready_sb; assign mem_rsp_valid_nc = mem_rsp_valid; assign mem_rsp_data_nc = mem_rsp_data; @@ -246,17 +370,19 @@ module VX_cache #( /////////////////////////////////////////////////////////////////////////// wire [`CACHE_LINE_WIDTH-1:0] mem_rsp_data_qual; - wire [`MEM_ADDR_WIDTH-1:0] mem_rsp_tag_qual; + wire [MEM_TAG_IN_WIDTH-1:0] mem_rsp_tag_qual; wire mrsq_out_valid, mrsq_out_ready; + + `RESET_RELAY (mrsq_reset); VX_elastic_buffer #( - .DATAW (`MEM_ADDR_WIDTH + `CACHE_LINE_WIDTH), - .SIZE (MRSQ_SIZE), - .OUTPUT_REG (MRSQ_SIZE > 2) + .DATAW (MEM_TAG_IN_WIDTH + `CACHE_LINE_WIDTH), + .SIZE (MRSQ_SIZE), + .OUT_REG (MRSQ_SIZE > 2) ) mem_rsp_queue ( .clk (clk), - .reset (reset), + .reset (mrsq_reset), .ready_in (mem_rsp_ready_nc), .valid_in (mem_rsp_valid_nc), .data_in ({mem_rsp_tag_nc, mem_rsp_data_nc}), @@ -272,13 +398,15 @@ module VX_cache #( wire [`LINE_SELECT_BITS-1:0] flush_addr; wire flush_enable; + `RESET_RELAY (flush_reset); + VX_flush_ctrl #( .CACHE_SIZE (CACHE_SIZE), .CACHE_LINE_SIZE (CACHE_LINE_SIZE), .NUM_BANKS (NUM_BANKS) ) flush_ctrl ( .clk (clk), - .reset (reset), + .reset (flush_reset), .addr_out (flush_addr), .valid_out (flush_enable) ); @@ -287,36 +415,38 @@ module VX_cache #( wire [NUM_BANKS-1:0] per_bank_core_req_valid; wire [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_req_pmask; - wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`UP(`WORD_SELECT_BITS)-1:0] per_bank_core_req_wsel; + wire [NUM_BANKS-1:0][NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] per_bank_core_req_wsel; wire [NUM_BANKS-1:0][NUM_PORTS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen; wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data; wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid; + wire [NUM_BANKS-1:0][NUM_PORTS-1:0][CORE_TAG_X_WIDTH-1:0] per_bank_core_req_tag; wire [NUM_BANKS-1:0] per_bank_core_req_rw; - wire [NUM_BANKS-1:0][`LINE_ADDR_WIDTH-1:0] per_bank_core_req_addr; - wire [NUM_BANKS-1:0][CORE_TAG_X_WIDTH-1:0] per_bank_core_req_tag; + wire [NUM_BANKS-1:0][`LINE_ADDR_WIDTH-1:0] per_bank_core_req_addr; wire [NUM_BANKS-1:0] per_bank_core_req_ready; wire [NUM_BANKS-1:0] per_bank_core_rsp_valid; wire [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_rsp_pmask; wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`WORD_WIDTH-1:0] per_bank_core_rsp_data; wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`REQS_BITS-1:0] per_bank_core_rsp_tid; - wire [NUM_BANKS-1:0][CORE_TAG_X_WIDTH-1:0] per_bank_core_rsp_tag; + wire [NUM_BANKS-1:0][NUM_PORTS-1:0][CORE_TAG_X_WIDTH-1:0] per_bank_core_rsp_tag; wire [NUM_BANKS-1:0] per_bank_core_rsp_ready; wire [NUM_BANKS-1:0] per_bank_mem_req_valid; wire [NUM_BANKS-1:0] per_bank_mem_req_rw; - wire [NUM_BANKS-1:0][CACHE_LINE_SIZE-1:0] per_bank_mem_req_byteen; + wire [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_mem_req_pmask; + wire [NUM_BANKS-1:0][NUM_PORTS-1:0][WORD_SIZE-1:0] per_bank_mem_req_byteen; + wire [NUM_BANKS-1:0][NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] per_bank_mem_req_wsel; wire [NUM_BANKS-1:0][`MEM_ADDR_WIDTH-1:0] per_bank_mem_req_addr; - wire [NUM_BANKS-1:0][`CACHE_LINE_WIDTH-1:0] per_bank_mem_req_data; + wire [NUM_BANKS-1:0][MSHR_ADDR_WIDTH-1:0] per_bank_mem_req_id; + wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`WORD_WIDTH-1:0] per_bank_mem_req_data; wire [NUM_BANKS-1:0] per_bank_mem_req_ready; wire [NUM_BANKS-1:0] per_bank_mem_rsp_ready; if (NUM_BANKS == 1) begin - `UNUSED_VAR (mem_rsp_tag_qual) assign mrsq_out_ready = per_bank_mem_rsp_ready; end else begin - assign mrsq_out_ready = per_bank_mem_rsp_ready[`MEM_ADDR_BANK(mem_rsp_tag_qual)]; + assign mrsq_out_ready = per_bank_mem_rsp_ready[`MEM_TAG_TO_BANK_ID(mem_rsp_tag_qual)]; end VX_core_req_bank_sel #( @@ -358,31 +488,34 @@ module VX_cache #( for (genvar i = 0; i < NUM_BANKS; i++) begin wire curr_bank_core_req_valid; wire [NUM_PORTS-1:0] curr_bank_core_req_pmask; - wire [NUM_PORTS-1:0][`UP(`WORD_SELECT_BITS)-1:0] curr_bank_core_req_wsel; + wire [NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] curr_bank_core_req_wsel; wire [NUM_PORTS-1:0][WORD_SIZE-1:0] curr_bank_core_req_byteen; wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] curr_bank_core_req_data; - wire [NUM_PORTS-1:0][`REQS_BITS-1:0] curr_bank_core_req_tid; + wire [NUM_PORTS-1:0][`REQS_BITS-1:0] curr_bank_core_req_tid; + wire [NUM_PORTS-1:0][CORE_TAG_X_WIDTH-1:0] curr_bank_core_req_tag; wire curr_bank_core_req_rw; - wire [`LINE_ADDR_WIDTH-1:0] curr_bank_core_req_addr; - wire [CORE_TAG_X_WIDTH-1:0] curr_bank_core_req_tag; + wire [`LINE_ADDR_WIDTH-1:0] curr_bank_core_req_addr; wire curr_bank_core_req_ready; wire curr_bank_core_rsp_valid; wire [NUM_PORTS-1:0] curr_bank_core_rsp_pmask; wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] curr_bank_core_rsp_data; wire [NUM_PORTS-1:0][`REQS_BITS-1:0] curr_bank_core_rsp_tid; - wire [CORE_TAG_X_WIDTH-1:0] curr_bank_core_rsp_tag; + wire [NUM_PORTS-1:0][CORE_TAG_X_WIDTH-1:0] curr_bank_core_rsp_tag; wire curr_bank_core_rsp_ready; wire curr_bank_mem_req_valid; wire curr_bank_mem_req_rw; - wire [CACHE_LINE_SIZE-1:0] curr_bank_mem_req_byteen; + wire [NUM_PORTS-1:0] curr_bank_mem_req_pmask; + wire [NUM_PORTS-1:0][WORD_SIZE-1:0] curr_bank_mem_req_byteen; + wire [NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] curr_bank_mem_req_wsel; wire [`LINE_ADDR_WIDTH-1:0] curr_bank_mem_req_addr; - wire[`CACHE_LINE_WIDTH-1:0] curr_bank_mem_req_data; + wire [MSHR_ADDR_WIDTH-1:0] curr_bank_mem_req_id; + wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] curr_bank_mem_req_data; wire curr_bank_mem_req_ready; - wire curr_bank_mem_rsp_valid; - wire [`LINE_ADDR_WIDTH-1:0] curr_bank_mem_rsp_addr; + wire curr_bank_mem_rsp_valid; + wire [MSHR_ADDR_WIDTH-1:0] curr_bank_mem_rsp_id; wire [`CACHE_LINE_WIDTH-1:0] curr_bank_mem_rsp_data; wire curr_bank_mem_rsp_ready; @@ -407,27 +540,31 @@ module VX_cache #( assign per_bank_core_rsp_data [i] = curr_bank_core_rsp_data; // Memory request - assign per_bank_mem_req_valid[i] = curr_bank_mem_req_valid; - assign per_bank_mem_req_rw[i] = curr_bank_mem_req_rw; + assign per_bank_mem_req_valid[i] = curr_bank_mem_req_valid; + assign per_bank_mem_req_rw[i] = curr_bank_mem_req_rw; + assign per_bank_mem_req_pmask[i] = curr_bank_mem_req_pmask; assign per_bank_mem_req_byteen[i] = curr_bank_mem_req_byteen; + assign per_bank_mem_req_wsel[i] = curr_bank_mem_req_wsel; if (NUM_BANKS == 1) begin assign per_bank_mem_req_addr[i] = curr_bank_mem_req_addr; end else begin assign per_bank_mem_req_addr[i] = `LINE_TO_MEM_ADDR(curr_bank_mem_req_addr, i); end + assign per_bank_mem_req_id[i] = curr_bank_mem_req_id; assign per_bank_mem_req_data[i] = curr_bank_mem_req_data; - assign curr_bank_mem_req_ready = per_bank_mem_req_ready[i]; + assign curr_bank_mem_req_ready = per_bank_mem_req_ready[i]; // Memory response if (NUM_BANKS == 1) begin - assign curr_bank_mem_rsp_valid = mrsq_out_valid; - assign curr_bank_mem_rsp_addr = mem_rsp_tag_qual; + assign curr_bank_mem_rsp_valid = mrsq_out_valid; end else begin - assign curr_bank_mem_rsp_valid = mrsq_out_valid && (`MEM_ADDR_BANK(mem_rsp_tag_qual) == i); - assign curr_bank_mem_rsp_addr = `MEM_TO_LINE_ADDR(mem_rsp_tag_qual); + assign curr_bank_mem_rsp_valid = mrsq_out_valid && (`MEM_TAG_TO_BANK_ID(mem_rsp_tag_qual) == i); end + assign curr_bank_mem_rsp_id = `MEM_TAG_TO_REQ_ID(mem_rsp_tag_qual); assign curr_bank_mem_rsp_data = mem_rsp_data_qual; assign per_bank_mem_rsp_ready[i] = curr_bank_mem_rsp_ready; + + `RESET_RELAY (bank_reset); VX_bank #( .BANK_ID (i), @@ -450,7 +587,7 @@ module VX_cache #( `SCOPE_BIND_VX_cache_bank(i) .clk (clk), - .reset (reset), + .reset (bank_reset), `ifdef PERF_ENABLE .perf_read_misses (perf_read_miss_per_bank[i]), @@ -482,14 +619,17 @@ module VX_cache #( // Memory request .mem_req_valid (curr_bank_mem_req_valid), .mem_req_rw (curr_bank_mem_req_rw), + .mem_req_pmask (curr_bank_mem_req_pmask), .mem_req_byteen (curr_bank_mem_req_byteen), + .mem_req_wsel (curr_bank_mem_req_wsel), .mem_req_addr (curr_bank_mem_req_addr), + .mem_req_id (curr_bank_mem_req_id), .mem_req_data (curr_bank_mem_req_data), .mem_req_ready (curr_bank_mem_req_ready), // Memory response .mem_rsp_valid (curr_bank_mem_rsp_valid), - .mem_rsp_addr (curr_bank_mem_rsp_addr), + .mem_rsp_id (curr_bank_mem_rsp_id), .mem_rsp_data (curr_bank_mem_rsp_data), .mem_rsp_ready (curr_bank_mem_rsp_ready), @@ -523,53 +663,66 @@ module VX_cache #( .core_rsp_ready (core_rsp_ready_nc) ); - wire [NUM_BANKS-1:0][(`MEM_ADDR_WIDTH + 1 + CACHE_LINE_SIZE + `CACHE_LINE_WIDTH)-1:0] data_in; - for (genvar i = 0; i < NUM_BANKS; i++) begin - assign data_in[i] = {per_bank_mem_req_addr[i], per_bank_mem_req_rw[i], per_bank_mem_req_byteen[i], per_bank_mem_req_data[i]}; + wire [NUM_BANKS-1:0][(`MEM_ADDR_WIDTH + MSHR_ADDR_WIDTH + 1 + NUM_PORTS * (1 + WORD_SIZE + WORD_SELECT_BITS + `WORD_WIDTH))-1:0] data_in; + for (genvar i = 0; i < NUM_BANKS; ++i) begin + assign data_in[i] = {per_bank_mem_req_addr[i], per_bank_mem_req_id[i], per_bank_mem_req_rw[i], per_bank_mem_req_pmask[i], per_bank_mem_req_byteen[i], per_bank_mem_req_wsel[i], per_bank_mem_req_data[i]}; end + wire [MSHR_ADDR_WIDTH-1:0] mem_req_id; + + `RESET_RELAY (mreq_reset); + VX_stream_arbiter #( .NUM_REQS (NUM_BANKS), - .DATAW (`MEM_ADDR_WIDTH + 1 + CACHE_LINE_SIZE + `CACHE_LINE_WIDTH), - .BUFFERED (1) + .DATAW (`MEM_ADDR_WIDTH + MSHR_ADDR_WIDTH + 1 + NUM_PORTS * (1 + WORD_SIZE + WORD_SELECT_BITS + `WORD_WIDTH)), + .TYPE ("R") ) mem_req_arb ( .clk (clk), - .reset (reset), + .reset (mreq_reset), .valid_in (per_bank_mem_req_valid), .data_in (data_in), .ready_in (per_bank_mem_req_ready), .valid_out (mem_req_valid_nc), - .data_out ({mem_req_addr_nc, mem_req_rw_nc, mem_req_byteen_nc, mem_req_data_nc}), + .data_out ({mem_req_addr_nc, mem_req_id, mem_req_rw_nc, mem_req_pmask_nc, mem_req_byteen_nc, mem_req_wsel_nc, mem_req_data_nc}), .ready_out (mem_req_ready_nc) ); - assign mem_req_tag_nc = mem_req_addr_nc; + if (NUM_BANKS == 1) begin + assign mem_req_tag_nc = MEM_TAG_IN_WIDTH'(mem_req_id); + end else begin + assign mem_req_tag_nc = MEM_TAG_IN_WIDTH'({`MEM_ADDR_TO_BANK_ID(mem_req_addr_nc), mem_req_id}); + end `ifdef PERF_ENABLE // per cycle: core_reads, core_writes - reg [($clog2(NUM_REQS+1)-1):0] perf_core_reads_per_cycle; - reg [($clog2(NUM_REQS+1)-1):0] perf_core_writes_per_cycle; - reg [($clog2(NUM_REQS+1)-1):0] perf_crsp_stall_per_cycle; + wire [$clog2(NUM_REQS+1)-1:0] perf_core_reads_per_cycle; + wire [$clog2(NUM_REQS+1)-1:0] perf_core_writes_per_cycle; + wire [$clog2(NUM_REQS+1)-1:0] perf_crsp_stall_per_cycle; - assign perf_core_reads_per_cycle = $countones(core_req_valid & core_req_ready & ~core_req_rw); - assign perf_core_writes_per_cycle = $countones(core_req_valid & core_req_ready & core_req_rw); + wire [NUM_REQS-1:0] perf_core_reads_per_mask = core_req_valid & core_req_ready & ~core_req_rw; + wire [NUM_REQS-1:0] perf_core_writes_per_mask = core_req_valid & core_req_ready & core_req_rw; + + `POP_COUNT(perf_core_reads_per_cycle, perf_core_reads_per_mask); + `POP_COUNT(perf_core_writes_per_cycle, perf_core_writes_per_mask); if (CORE_TAG_ID_BITS != 0) begin - assign perf_crsp_stall_per_cycle = $countones(core_rsp_tmask & {NUM_REQS{core_rsp_valid && ~core_rsp_ready}}); + wire [NUM_REQS-1:0] perf_crsp_stall_per_mask = core_rsp_tmask & {NUM_REQS{core_rsp_valid && ~core_rsp_ready}}; + `POP_COUNT(perf_crsp_stall_per_cycle, perf_crsp_stall_per_mask); end else begin - assign perf_crsp_stall_per_cycle = $countones(core_rsp_valid & ~core_rsp_ready); + wire [NUM_REQS-1:0] perf_crsp_stall_per_mask = core_rsp_valid & ~core_rsp_ready; + `POP_COUNT(perf_crsp_stall_per_cycle, perf_crsp_stall_per_mask); end // per cycle: read misses, write misses, msrq stalls, pipeline stalls - reg [($clog2(NUM_BANKS+1)-1):0] perf_read_miss_per_cycle; - reg [($clog2(NUM_BANKS+1)-1):0] perf_write_miss_per_cycle; - reg [($clog2(NUM_BANKS+1)-1):0] perf_mshr_stall_per_cycle; - reg [($clog2(NUM_BANKS+1)-1):0] perf_pipe_stall_per_cycle; + wire [$clog2(NUM_BANKS+1)-1:0] perf_read_miss_per_cycle; + wire [$clog2(NUM_BANKS+1)-1:0] perf_write_miss_per_cycle; + wire [$clog2(NUM_BANKS+1)-1:0] perf_mshr_stall_per_cycle; + wire [$clog2(NUM_BANKS+1)-1:0] perf_pipe_stall_per_cycle; - assign perf_read_miss_per_cycle = $countones(perf_read_miss_per_bank); - assign perf_write_miss_per_cycle = $countones(perf_write_miss_per_bank); - assign perf_mshr_stall_per_cycle = $countones(perf_mshr_stall_per_bank); - assign perf_pipe_stall_per_cycle = $countones(perf_pipe_stall_per_bank); + `POP_COUNT(perf_read_miss_per_cycle, perf_read_miss_per_bank); + `POP_COUNT(perf_write_miss_per_cycle, perf_write_miss_per_bank); + `POP_COUNT(perf_mshr_stall_per_cycle, perf_mshr_stall_per_bank); + `POP_COUNT(perf_pipe_stall_per_cycle, perf_pipe_stall_per_bank); reg [`PERF_CTR_BITS-1:0] perf_core_reads; reg [`PERF_CTR_BITS-1:0] perf_core_writes; diff --git a/hw/rtl/cache/VX_cache_define.vh b/hw/rtl/cache/VX_cache_define.vh index 410b24a8..c0709cce 100644 --- a/hw/rtl/cache/VX_cache_define.vh +++ b/hw/rtl/cache/VX_cache_define.vh @@ -9,8 +9,10 @@ `define REQS_BITS `LOG2UP(NUM_REQS) -// tag valid tid word_sel -`define MSHR_DATA_WIDTH (CORE_TAG_WIDTH + (1 + `REQS_BITS + `UP(`WORD_SELECT_BITS)) * NUM_PORTS) +`define PORTS_BITS `LOG2UP(NUM_PORTS) + +// tag valid tid word_sel +`define MSHR_DATA_WIDTH ((CORE_TAG_WIDTH + 1 + `REQS_BITS + `UP(`WORD_SELECT_BITS)) * NUM_PORTS) `define WORD_WIDTH (8 * WORD_SIZE) @@ -57,14 +59,14 @@ `define CORE_RSP_TAGS ((CORE_TAG_ID_BITS != 0) ? 1 : NUM_REQS) -`define BANK_READY_COUNT ((SHARED_BANK_READY != 0) ? 1 : NUM_BANKS) - -`define MEM_ADDR_BANK(x) x[`BANK_SELECT_BITS+BANK_ADDR_OFFSET-1 : BANK_ADDR_OFFSET] - -`define MEM_TO_LINE_ADDR(x) x[`MEM_ADDR_WIDTH-1 : `BANK_SELECT_BITS] - `define LINE_TO_MEM_ADDR(x, i) {x, `BANK_SELECT_BITS'(i)} +`define MEM_ADDR_TO_BANK_ID(x) x[0 +: `BANK_SELECT_BITS] + +`define MEM_TAG_TO_REQ_ID(x) x[MSHR_ADDR_WIDTH-1:0] + +`define MEM_TAG_TO_BANK_ID(x) x[MSHR_ADDR_WIDTH +: `BANK_SELECT_BITS] + `define LINE_TO_BYTE_ADDR(x, i) {x, (32-$bits(x))'(i << (32-$bits(x)-`BANK_SELECT_BITS))} `define TO_FULL_ADDR(x) {x, (32-$bits(x))'(0)} diff --git a/hw/rtl/cache/VX_core_req_bank_sel.v b/hw/rtl/cache/VX_core_req_bank_sel.sv similarity index 77% rename from hw/rtl/cache/VX_core_req_bank_sel.v rename to hw/rtl/cache/VX_core_req_bank_sel.sv index 06824c33..01c9f12b 100644 --- a/hw/rtl/cache/VX_core_req_bank_sel.v +++ b/hw/rtl/cache/VX_core_req_bank_sel.sv @@ -16,9 +16,7 @@ module VX_core_req_bank_sel #( // core request tag size parameter CORE_TAG_WIDTH = 3, // bank offset from beginning of index range - parameter BANK_ADDR_OFFSET = 0, - // shared bank ready signal - parameter SHARED_BANK_READY = 0 + parameter BANK_ADDR_OFFSET = 0 ) ( input wire clk, input wire reset, @@ -43,8 +41,8 @@ module VX_core_req_bank_sel #( output wire [NUM_BANKS-1:0][NUM_PORTS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen, output wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data, output wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid, - output wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag, - input wire [`BANK_READY_COUNT-1:0] per_bank_core_req_ready + output wire [NUM_BANKS-1:0][NUM_PORTS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag, + input wire [NUM_BANKS-1:0] per_bank_core_req_ready ); `UNUSED_PARAM (CACHE_ID) `STATIC_ASSERT(NUM_BANKS <= NUM_REQS, ("invalid value")) @@ -80,9 +78,9 @@ module VX_core_req_bank_sel #( reg [NUM_BANKS-1:0][NUM_PORTS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen_r; reg [NUM_BANKS-1:0][NUM_PORTS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data_r; reg [NUM_BANKS-1:0][NUM_PORTS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid_r; + reg [NUM_BANKS-1:0][NUM_PORTS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag_r; reg [NUM_BANKS-1:0] per_bank_core_req_rw_r; reg [NUM_BANKS-1:0][`LINE_ADDR_WIDTH-1:0] per_bank_core_req_addr_r; - reg [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag_r; reg [NUM_REQS-1:0] core_req_ready_r; if (NUM_REQS > 1) begin @@ -101,7 +99,7 @@ module VX_core_req_bank_sel #( end end - for (genvar i = NUM_REQS-1; i >= 0; --i) begin + for (genvar i = 0; i < NUM_REQS; ++i) begin assign core_req_line_match[i] = (core_req_line_addr[i] == per_bank_line_addr_r[core_req_bid[i]]); end @@ -129,30 +127,19 @@ module VX_core_req_bank_sel #( per_bank_core_req_byteen_r[core_req_bid[i]][i % NUM_PORTS] = core_req_byteen[i]; per_bank_core_req_data_r[core_req_bid[i]][i % NUM_PORTS] = core_req_data[i]; per_bank_core_req_tid_r[core_req_bid[i]][i % NUM_PORTS] = `REQS_BITS'(i); + per_bank_core_req_tag_r[core_req_bid[i]][i % NUM_PORTS] = core_req_tag[i]; per_bank_core_req_rw_r[core_req_bid[i]] = core_req_rw[i]; per_bank_core_req_addr_r[core_req_bid[i]] = core_req_line_addr[i]; - per_bank_core_req_tag_r[core_req_bid[i]] = core_req_tag[i]; - req_select_table_r[core_req_bid[i]][i % NUM_PORTS] = (1 << i); end end end - if (SHARED_BANK_READY == 0) begin - always @(*) begin - for (integer i = 0; i < NUM_REQS; ++i) begin - core_req_ready_r[i] = per_bank_core_req_ready[core_req_bid[i]] - && core_req_line_match[i] - && req_select_table_r[core_req_bid[i]][i % NUM_PORTS][i]; - end - end - end else begin - always @(*) begin - for (integer i = 0; i < NUM_REQS; ++i) begin - core_req_ready_r[i] = per_bank_core_req_ready - && core_req_line_match[i] - && req_select_table_r[core_req_bid[i]][i % NUM_PORTS][i]; - end + always @(*) begin + for (integer i = 0; i < NUM_REQS; ++i) begin + core_req_ready_r[i] = per_bank_core_req_ready[core_req_bid[i]] + && core_req_line_match[i] + && req_select_table_r[core_req_bid[i]][i % NUM_PORTS][i]; end end @@ -177,32 +164,17 @@ module VX_core_req_bank_sel #( per_bank_core_req_byteen_r[core_req_bid[i]][i % NUM_PORTS] = core_req_byteen[i]; per_bank_core_req_data_r[core_req_bid[i]][i % NUM_PORTS] = core_req_data[i]; per_bank_core_req_tid_r[core_req_bid[i]][i % NUM_PORTS] = `REQS_BITS'(i); + per_bank_core_req_tag_r[core_req_bid[i]][i % NUM_PORTS] = core_req_tag[i]; per_bank_core_req_rw_r[core_req_bid[i]] = core_req_rw[i]; - per_bank_core_req_addr_r[core_req_bid[i]] = core_req_line_addr[i]; - per_bank_core_req_tag_r[core_req_bid[i]] = core_req_tag[i]; + per_bank_core_req_addr_r[core_req_bid[i]] = core_req_line_addr[i]; end end end - if (SHARED_BANK_READY == 0) begin - always @(*) begin - core_req_ready_r = 'x; - for (integer i = NUM_REQS-1; i >= 0; --i) begin - if (core_req_valid[i]) begin - core_req_ready_r[i] = per_bank_core_req_ready[core_req_bid[i]] - && core_req_line_match[i]; - end - end - end - end else begin - always @(*) begin - core_req_ready_r = 'x; - for (integer i = NUM_REQS-1; i >= 0; --i) begin - if (core_req_valid[i]) begin - core_req_ready_r[i] = per_bank_core_req_ready - && core_req_line_match[i]; - end - end + always @(*) begin + for (integer i = 0; i < NUM_REQS; ++i) begin + core_req_ready_r[i] = per_bank_core_req_ready[core_req_bid[i]] + && core_req_line_match[i]; end end end @@ -236,22 +208,11 @@ module VX_core_req_bank_sel #( end if (NUM_BANKS > 1) begin - if (SHARED_BANK_READY == 0) begin - always @(*) begin - core_req_ready_r = 0; - for (integer i = 0; i < NUM_BANKS; ++i) begin - if (per_bank_core_req_valid_r[i]) begin - core_req_ready_r[per_bank_core_req_tid_r[i]] = per_bank_core_req_ready[i]; - end - end - end - end else begin - always @(*) begin - core_req_ready_r = 0; - for (integer i = 0; i < NUM_BANKS; ++i) begin - if (per_bank_core_req_valid_r[i]) begin - core_req_ready_r[per_bank_core_req_tid_r[i]] = per_bank_core_req_ready; - end + always @(*) begin + core_req_ready_r = 0; + for (integer i = 0; i < NUM_BANKS; ++i) begin + if (per_bank_core_req_valid_r[i]) begin + core_req_ready_r[per_bank_core_req_tid_r[i]] = per_bank_core_req_ready[i]; end end end @@ -320,33 +281,26 @@ module VX_core_req_bank_sel #( `ifdef PERF_ENABLE reg [NUM_REQS-1:0] core_req_sel_r; - if (SHARED_BANK_READY == 0) begin - always @(*) begin - core_req_sel_r = 0; - for (integer i = 0; i < NUM_REQS; ++i) begin - if (core_req_valid[i]) begin - core_req_sel_r[i] = per_bank_core_req_ready[core_req_bid[i]]; - end - end - end - end else begin - always @(*) begin - core_req_sel_r = 0; - for (integer i = 0; i < NUM_REQS; ++i) begin - if (core_req_valid[i]) begin - core_req_sel_r[i] = per_bank_core_req_ready; - end + always @(*) begin + core_req_sel_r = 0; + for (integer i = 0; i < NUM_REQS; ++i) begin + if (core_req_valid[i]) begin + core_req_sel_r[i] = per_bank_core_req_ready[core_req_bid[i]]; end end end reg [`PERF_CTR_BITS-1:0] bank_stalls_r; + wire [$clog2(NUM_REQS+1)-1:0] bank_stall_cnt; + + wire [NUM_REQS-1:0] bank_stall_mask = core_req_sel_r & ~core_req_ready; + `POP_COUNT(bank_stall_cnt, bank_stall_mask); always @(posedge clk) begin if (reset) begin bank_stalls_r <= 0; end else begin - bank_stalls_r <= bank_stalls_r + `PERF_CTR_BITS'($countones(core_req_sel_r & ~core_req_ready)); + bank_stalls_r <= bank_stalls_r + `PERF_CTR_BITS'(bank_stall_cnt); end end diff --git a/hw/rtl/cache/VX_core_rsp_merge.sv b/hw/rtl/cache/VX_core_rsp_merge.sv new file mode 100644 index 00000000..b21f6085 --- /dev/null +++ b/hw/rtl/cache/VX_core_rsp_merge.sv @@ -0,0 +1,350 @@ +`include "VX_cache_define.vh" + +module VX_core_rsp_merge #( + parameter CACHE_ID = 0, + + // Number of Word requests per cycle + parameter NUM_REQS = 1, + // Number of banks + parameter NUM_BANKS = 1, + // Number of ports per banks + parameter NUM_PORTS = 1, + // Size of a word in bytes + parameter WORD_SIZE = 1, + // core request tag size + parameter CORE_TAG_WIDTH = 1, + // size of tag id in core request tag + parameter CORE_TAG_ID_BITS = 0, + // output register + parameter OUT_REG = 0 +) ( + input wire clk, + input wire reset, + + // Per Bank WB + input wire [NUM_BANKS-1:0] per_bank_core_rsp_valid, + input wire [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_rsp_pmask, + input wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`WORD_WIDTH-1:0] per_bank_core_rsp_data, + input wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`REQS_BITS-1:0] per_bank_core_rsp_tid, + input wire [NUM_BANKS-1:0][NUM_PORTS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_rsp_tag, + output wire [NUM_BANKS-1:0] per_bank_core_rsp_ready, + + // Core Response + output wire [`CORE_RSP_TAGS-1:0] core_rsp_valid, + output wire [NUM_REQS-1:0] core_rsp_tmask, + output wire [`CORE_RSP_TAGS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag, + output wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data, + input wire [`CORE_RSP_TAGS-1:0] core_rsp_ready +); + `UNUSED_PARAM (CACHE_ID) + + if (NUM_BANKS > 1) begin + + reg [NUM_REQS-1:0] core_rsp_valid_unqual; + reg [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data_unqual; + reg [NUM_BANKS-1:0] per_bank_core_rsp_ready_r; + + if (CORE_TAG_ID_BITS != 0) begin + + // The core response bus handles a single tag at the time + // We first need to select the current tag to process, + // then send all bank responses for that tag as a batch + + wire [CORE_TAG_WIDTH-1:0] core_rsp_tag_unqual; + wire core_rsp_ready_unqual; + + if (NUM_PORTS > 1) begin + + reg [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_rsp_sent_r, per_bank_core_rsp_sent; + wire [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_rsp_sent_n; + + for (genvar i = 0; i < NUM_BANKS; ++i) begin + assign per_bank_core_rsp_sent_n[i] = per_bank_core_rsp_sent_r[i] | per_bank_core_rsp_sent[i]; + end + + always @(posedge clk) begin + if (reset) begin + per_bank_core_rsp_sent_r <= '0; + end else begin + for (integer i = 0; i < NUM_BANKS; ++i) begin + if (per_bank_core_rsp_sent_n[i] == per_bank_core_rsp_pmask[i]) begin + per_bank_core_rsp_sent_r[i] <= '0; + end else begin + per_bank_core_rsp_sent_r[i] <= per_bank_core_rsp_sent_n[i]; + end + end + end + end + + wire [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_rsp_valid_p; + for (genvar i = 0; i < NUM_BANKS; ++i) begin + for (genvar p = 0; p < NUM_PORTS; ++p) begin + assign per_bank_core_rsp_valid_p[i][p] = per_bank_core_rsp_valid[i] + && per_bank_core_rsp_pmask[i][p] + && !per_bank_core_rsp_sent_r[i][p]; + end + end + + VX_find_first #( + .N (NUM_BANKS * NUM_PORTS), + .DATAW (CORE_TAG_WIDTH) + ) find_first ( + .valid_i (per_bank_core_rsp_valid_p), + .data_i (per_bank_core_rsp_tag), + .data_o (core_rsp_tag_unqual), + `UNUSED_PIN (valid_o) + ); + + always @(*) begin + core_rsp_valid_unqual = 0; + core_rsp_data_unqual = 'x; + per_bank_core_rsp_sent = 0; + + for (integer i = 0; i < NUM_BANKS; ++i) begin + for (integer p = 0; p < NUM_PORTS; ++p) begin + if (per_bank_core_rsp_valid[i] + && per_bank_core_rsp_pmask[i][p] + && !per_bank_core_rsp_sent_r[i][p] + && (per_bank_core_rsp_tag[i][p][CORE_TAG_ID_BITS-1:0] == core_rsp_tag_unqual[CORE_TAG_ID_BITS-1:0])) begin + core_rsp_valid_unqual[per_bank_core_rsp_tid[i][p]] = 1; + core_rsp_data_unqual[per_bank_core_rsp_tid[i][p]] = per_bank_core_rsp_data[i][p]; + per_bank_core_rsp_sent[i][p] = core_rsp_ready_unqual; + end + end + end + end + + always @(*) begin + for (integer i = 0; i < NUM_BANKS; ++i) begin + per_bank_core_rsp_ready_r[i] = (per_bank_core_rsp_sent_n[i] == per_bank_core_rsp_pmask[i]); + end + end + + end else begin + + `UNUSED_VAR (per_bank_core_rsp_pmask) + + VX_find_first #( + .N (NUM_BANKS), + .DATAW (CORE_TAG_WIDTH) + ) find_first ( + .valid_i (per_bank_core_rsp_valid), + .data_i (per_bank_core_rsp_tag), + .data_o (core_rsp_tag_unqual), + `UNUSED_PIN (valid_o) + ); + + always @(*) begin + core_rsp_valid_unqual = 0; + core_rsp_data_unqual = 'x; + per_bank_core_rsp_ready_r = 0; + + for (integer i = 0; i < NUM_BANKS; i++) begin + if (per_bank_core_rsp_valid[i] + && (per_bank_core_rsp_tag[i][0][CORE_TAG_ID_BITS-1:0] == core_rsp_tag_unqual[CORE_TAG_ID_BITS-1:0])) begin + core_rsp_valid_unqual[per_bank_core_rsp_tid[i]] = 1; + core_rsp_data_unqual[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i]; + per_bank_core_rsp_ready_r[i] = core_rsp_ready_unqual; + end + end + end + end + + wire core_rsp_valid_any = (| per_bank_core_rsp_valid); + + VX_skid_buffer #( + .DATAW (NUM_REQS + CORE_TAG_WIDTH + (NUM_REQS *`WORD_WIDTH)), + .PASSTHRU (0 == OUT_REG) + ) out_sbuf ( + .clk (clk), + .reset (reset), + .valid_in (core_rsp_valid_any), + .data_in ({core_rsp_valid_unqual, core_rsp_tag_unqual, core_rsp_data_unqual}), + .ready_in (core_rsp_ready_unqual), + .valid_out (core_rsp_valid), + .data_out ({core_rsp_tmask, core_rsp_tag, core_rsp_data}), + .ready_out (core_rsp_ready) + ); + + end else begin + + reg [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag_unqual; + wire [NUM_REQS-1:0] core_rsp_ready_unqual; + + if (NUM_PORTS > 1) begin + + reg [NUM_REQS-1:0][(`PORTS_BITS + `BANK_SELECT_BITS)-1:0] bank_select_table; + + reg [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_rsp_sent_r, per_bank_core_rsp_sent; + wire [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_rsp_sent_n; + + for (genvar i = 0; i < NUM_BANKS; ++i) begin + assign per_bank_core_rsp_sent_n[i] = per_bank_core_rsp_sent_r[i] | per_bank_core_rsp_sent[i]; + end + + always @(posedge clk) begin + if (reset) begin + per_bank_core_rsp_sent_r <= '0; + end else begin + for (integer i = 0; i < NUM_BANKS; ++i) begin + if (per_bank_core_rsp_sent_n[i] == per_bank_core_rsp_pmask[i]) begin + per_bank_core_rsp_sent_r[i] <= '0; + end else begin + per_bank_core_rsp_sent_r[i] <= per_bank_core_rsp_sent_n[i]; + end + end + end + end + + always @(*) begin + core_rsp_valid_unqual = '0; + core_rsp_tag_unqual = 'x; + core_rsp_data_unqual = 'x; + bank_select_table = 'x; + + for (integer i = NUM_BANKS-1; i >= 0; --i) begin + for (integer p = 0; p < NUM_PORTS; ++p) begin + if (per_bank_core_rsp_valid[i] + && per_bank_core_rsp_pmask[i][p] + && !per_bank_core_rsp_sent_r[i][p]) begin + core_rsp_valid_unqual[per_bank_core_rsp_tid[i][p]] = 1; + core_rsp_tag_unqual[per_bank_core_rsp_tid[i][p]] = per_bank_core_rsp_tag[i][p]; + core_rsp_data_unqual[per_bank_core_rsp_tid[i][p]] = per_bank_core_rsp_data[i][p]; + bank_select_table[per_bank_core_rsp_tid[i][p]] = {`PORTS_BITS'(p), `BANK_SELECT_BITS'(i)}; + end + end + end + end + + always @(*) begin + per_bank_core_rsp_sent = '0; + for (integer i = 0; i < NUM_REQS; i++) begin + if (core_rsp_valid_unqual[i]) begin + per_bank_core_rsp_sent[bank_select_table[i][0 +: `BANK_SELECT_BITS]][bank_select_table[i][`BANK_SELECT_BITS +: `PORTS_BITS]] = core_rsp_ready_unqual[i]; + end + end + end + + always @(*) begin + for (integer i = 0; i < NUM_BANKS; i++) begin + per_bank_core_rsp_ready_r[i] = (per_bank_core_rsp_sent_n[i] == per_bank_core_rsp_pmask[i]); + end + end + + end else begin + + `UNUSED_VAR (per_bank_core_rsp_pmask) + reg [NUM_REQS-1:0][NUM_BANKS-1:0] bank_select_table; + + always @(*) begin + core_rsp_valid_unqual = 0; + core_rsp_tag_unqual = 'x; + core_rsp_data_unqual = 'x; + bank_select_table = 'x; + + for (integer i = NUM_BANKS-1; i >= 0; --i) begin + if (per_bank_core_rsp_valid[i]) begin + core_rsp_valid_unqual[per_bank_core_rsp_tid[i]] = 1; + core_rsp_tag_unqual[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_tag[i]; + core_rsp_data_unqual[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i]; + bank_select_table[per_bank_core_rsp_tid[i]] = (1 << i); + end + end + end + + always @(*) begin + for (integer i = 0; i < NUM_BANKS; ++i) begin + per_bank_core_rsp_ready_r[i] = core_rsp_ready_unqual[per_bank_core_rsp_tid[i]] + && bank_select_table[per_bank_core_rsp_tid[i]][i]; + end + end + end + + for (genvar i = 0; i < NUM_REQS; i++) begin + VX_skid_buffer #( + .DATAW (CORE_TAG_WIDTH + `WORD_WIDTH), + .PASSTHRU (0 == OUT_REG) + ) out_sbuf ( + .clk (clk), + .reset (reset), + .valid_in (core_rsp_valid_unqual[i]), + .data_in ({core_rsp_tag_unqual[i], core_rsp_data_unqual[i]}), + .ready_in (core_rsp_ready_unqual[i]), + .valid_out (core_rsp_valid[i]), + .data_out ({core_rsp_tag[i],core_rsp_data[i]}), + .ready_out (core_rsp_ready[i]) + ); + end + + assign core_rsp_tmask = core_rsp_valid; + + end + + assign per_bank_core_rsp_ready = per_bank_core_rsp_ready_r; + + end else begin + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + `UNUSED_VAR (per_bank_core_rsp_pmask) + + if (NUM_REQS > 1) begin + + reg [`CORE_RSP_TAGS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag_unqual; + reg [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data_unqual; + + if (CORE_TAG_ID_BITS != 0) begin + + reg [NUM_REQS-1:0] core_rsp_tmask_unqual; + + always @(*) begin + core_rsp_tmask_unqual = 0; + core_rsp_tmask_unqual[per_bank_core_rsp_tid] = per_bank_core_rsp_valid; + + core_rsp_tag_unqual = per_bank_core_rsp_tag; + + core_rsp_data_unqual = 'x; + core_rsp_data_unqual[per_bank_core_rsp_tid] = per_bank_core_rsp_data; + end + + assign core_rsp_valid = per_bank_core_rsp_valid; + assign core_rsp_tmask = core_rsp_tmask_unqual; + assign per_bank_core_rsp_ready = core_rsp_ready; + + end else begin + + reg [`CORE_RSP_TAGS-1:0] core_rsp_valid_unqual; + + always @(*) begin + core_rsp_valid_unqual = 0; + core_rsp_valid_unqual[per_bank_core_rsp_tid] = per_bank_core_rsp_valid; + + core_rsp_tag_unqual = 'x; + core_rsp_tag_unqual[per_bank_core_rsp_tid] = per_bank_core_rsp_tag; + + core_rsp_data_unqual = 'x; + core_rsp_data_unqual[per_bank_core_rsp_tid] = per_bank_core_rsp_data; + end + + assign core_rsp_valid = core_rsp_valid_unqual; + assign core_rsp_tmask = core_rsp_valid_unqual; + assign per_bank_core_rsp_ready = core_rsp_ready[per_bank_core_rsp_tid]; + + end + + assign core_rsp_tag = core_rsp_tag_unqual; + assign core_rsp_data = core_rsp_data_unqual; + + end else begin + + `UNUSED_VAR(per_bank_core_rsp_tid) + assign core_rsp_valid = per_bank_core_rsp_valid; + assign core_rsp_tmask = per_bank_core_rsp_valid; + assign core_rsp_tag = per_bank_core_rsp_tag; + assign core_rsp_data = per_bank_core_rsp_data; + assign per_bank_core_rsp_ready = core_rsp_ready; + + end + end + +endmodule diff --git a/hw/rtl/cache/VX_core_rsp_merge.v b/hw/rtl/cache/VX_core_rsp_merge.v deleted file mode 100644 index 14823b0d..00000000 --- a/hw/rtl/cache/VX_core_rsp_merge.v +++ /dev/null @@ -1,239 +0,0 @@ -`include "VX_cache_define.vh" - -module VX_core_rsp_merge #( - parameter CACHE_ID = 0, - - // Number of Word requests per cycle - parameter NUM_REQS = 1, - // Number of banks - parameter NUM_BANKS = 1, - // Number of ports per banks - parameter NUM_PORTS = 1, - // Size of a word in bytes - parameter WORD_SIZE = 1, - // core request tag size - parameter CORE_TAG_WIDTH = 1, - // size of tag id in core request tag - parameter CORE_TAG_ID_BITS = 0 -) ( - input wire clk, - input wire reset, - - // Per Bank WB - input wire [NUM_BANKS-1:0] per_bank_core_rsp_valid, - input wire [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_rsp_pmask, - input wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`WORD_WIDTH-1:0] per_bank_core_rsp_data, - input wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`REQS_BITS-1:0] per_bank_core_rsp_tid, - input wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_rsp_tag, - output wire [NUM_BANKS-1:0] per_bank_core_rsp_ready, - - // Core Response - output wire [`CORE_RSP_TAGS-1:0] core_rsp_valid, - output wire [NUM_REQS-1:0] core_rsp_tmask, - output wire [`CORE_RSP_TAGS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag, - output wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data, - input wire [`CORE_RSP_TAGS-1:0] core_rsp_ready -); - `UNUSED_PARAM (CACHE_ID) - - if (NUM_BANKS > 1) begin - - reg [NUM_REQS-1:0] core_rsp_valid_unqual; - reg [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data_unqual; - reg [NUM_BANKS-1:0] core_rsp_bank_select; - - if (CORE_TAG_ID_BITS != 0) begin - - // The core response bus handles a single tag at the time - // We first need to select the current tag to process, - // then send all bank responses for that tag as a batch - - reg [CORE_TAG_WIDTH-1:0] core_rsp_tag_unqual; - wire core_rsp_ready_unqual; - - always @(*) begin - core_rsp_tag_unqual = 'x; - for (integer i = NUM_BANKS-1; i >= 0; --i) begin - if (per_bank_core_rsp_valid[i]) begin - core_rsp_tag_unqual = per_bank_core_rsp_tag[i]; - end - end - end - - if (NUM_PORTS > 1) begin - - always @(*) begin - core_rsp_valid_unqual = 0; - core_rsp_data_unqual = 'x; - core_rsp_bank_select = 0; - - for (integer i = 0; i < NUM_BANKS; i++) begin - for (integer p = 0; p < NUM_PORTS; p++) begin - if (per_bank_core_rsp_valid[i] - && per_bank_core_rsp_pmask[i][p] - && (per_bank_core_rsp_tag[i][CORE_TAG_ID_BITS-1:0] == core_rsp_tag_unqual[CORE_TAG_ID_BITS-1:0])) begin - core_rsp_valid_unqual[per_bank_core_rsp_tid[i][p]] = 1; - core_rsp_data_unqual[per_bank_core_rsp_tid[i][p]] = per_bank_core_rsp_data[i][p]; - core_rsp_bank_select[i] = core_rsp_ready_unqual; - end - end - end - end - - end else begin - - `UNUSED_VAR (per_bank_core_rsp_pmask) - - always @(*) begin - core_rsp_valid_unqual = 0; - core_rsp_data_unqual = 'x; - core_rsp_bank_select = 0; - - for (integer i = 0; i < NUM_BANKS; i++) begin - if (per_bank_core_rsp_valid[i] - && (per_bank_core_rsp_tag[i][CORE_TAG_ID_BITS-1:0] == core_rsp_tag_unqual[CORE_TAG_ID_BITS-1:0])) begin - core_rsp_valid_unqual[per_bank_core_rsp_tid[i]] = 1; - core_rsp_data_unqual[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i]; - core_rsp_bank_select[i] = core_rsp_ready_unqual; - end - end - end - - end - - wire core_rsp_valid_any = (| per_bank_core_rsp_valid); - - VX_skid_buffer #( - .DATAW (NUM_REQS + CORE_TAG_WIDTH + (NUM_REQS *`WORD_WIDTH)) - ) pipe_reg ( - .clk (clk), - .reset (reset), - .valid_in (core_rsp_valid_any), - .data_in ({core_rsp_valid_unqual, core_rsp_tag_unqual, core_rsp_data_unqual}), - .ready_in (core_rsp_ready_unqual), - .valid_out (core_rsp_valid), - .data_out ({core_rsp_tmask, core_rsp_tag, core_rsp_data}), - .ready_out (core_rsp_ready) - ); - - end else begin - - `UNUSED_VAR (per_bank_core_rsp_pmask) - - reg [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag_unqual; - reg [NUM_REQS-1:0][NUM_BANKS-1:0] bank_select_table; - - wire [NUM_REQS-1:0] core_rsp_ready_unqual; - - always @(*) begin - core_rsp_valid_unqual = 0; - core_rsp_tag_unqual = 'x; - core_rsp_data_unqual = 'x; - bank_select_table = 'x; - - for (integer i = NUM_BANKS-1; i >= 0; --i) begin - if (per_bank_core_rsp_valid[i]) begin - core_rsp_valid_unqual[per_bank_core_rsp_tid[i]] = 1; - core_rsp_tag_unqual[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_tag[i]; - core_rsp_data_unqual[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i]; - bank_select_table[per_bank_core_rsp_tid[i]] = (1 << i); - end - end - end - - always @(*) begin - for (integer i = 0; i < NUM_BANKS; i++) begin - core_rsp_bank_select[i] = core_rsp_ready_unqual[per_bank_core_rsp_tid[i]] - && bank_select_table[per_bank_core_rsp_tid[i]][i]; - end - end - - for (genvar i = 0; i < NUM_REQS; i++) begin - VX_skid_buffer #( - .DATAW (CORE_TAG_WIDTH + `WORD_WIDTH) - ) pipe_reg ( - .clk (clk), - .reset (reset), - .valid_in (core_rsp_valid_unqual[i]), - .data_in ({core_rsp_tag_unqual[i], core_rsp_data_unqual[i]}), - .ready_in (core_rsp_ready_unqual[i]), - .valid_out (core_rsp_valid[i]), - .data_out ({core_rsp_tag[i],core_rsp_data[i]}), - .ready_out (core_rsp_ready[i]) - ); - end - - assign core_rsp_tmask = core_rsp_valid; - - end - - for (genvar i = 0; i < NUM_BANKS; i++) begin - assign per_bank_core_rsp_ready[i] = core_rsp_bank_select[i]; - end - - end else begin - - `UNUSED_VAR (clk) - `UNUSED_VAR (reset) - `UNUSED_VAR (per_bank_core_rsp_pmask) - - if (NUM_REQS > 1) begin - - reg [`CORE_RSP_TAGS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag_unqual; - reg [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data_unqual; - - if (CORE_TAG_ID_BITS != 0) begin - - reg [NUM_REQS-1:0] core_rsp_tmask_unqual; - - always @(*) begin - core_rsp_tmask_unqual = 0; - core_rsp_tmask_unqual[per_bank_core_rsp_tid] = per_bank_core_rsp_valid; - - core_rsp_tag_unqual = per_bank_core_rsp_tag; - - core_rsp_data_unqual = 'x; - core_rsp_data_unqual[per_bank_core_rsp_tid] = per_bank_core_rsp_data; - end - - assign core_rsp_valid = per_bank_core_rsp_valid; - assign core_rsp_tmask = core_rsp_tmask_unqual; - assign per_bank_core_rsp_ready = core_rsp_ready; - - end else begin - - reg [`CORE_RSP_TAGS-1:0] core_rsp_valid_unqual; - - always @(*) begin - core_rsp_valid_unqual = 0; - core_rsp_valid_unqual[per_bank_core_rsp_tid] = per_bank_core_rsp_valid; - - core_rsp_tag_unqual = 'x; - core_rsp_tag_unqual[per_bank_core_rsp_tid] = per_bank_core_rsp_tag; - - core_rsp_data_unqual = 'x; - core_rsp_data_unqual[per_bank_core_rsp_tid] = per_bank_core_rsp_data; - end - - assign core_rsp_valid = core_rsp_valid_unqual; - assign core_rsp_tmask = core_rsp_valid_unqual; - assign per_bank_core_rsp_ready = core_rsp_ready[per_bank_core_rsp_tid]; - - end - - assign core_rsp_tag = core_rsp_tag_unqual; - assign core_rsp_data = core_rsp_data_unqual; - - end else begin - - `UNUSED_VAR(per_bank_core_rsp_tid) - assign core_rsp_valid = per_bank_core_rsp_valid; - assign core_rsp_tmask = per_bank_core_rsp_valid; - assign core_rsp_tag = per_bank_core_rsp_tag; - assign core_rsp_data = per_bank_core_rsp_data; - assign per_bank_core_rsp_ready = core_rsp_ready; - - end - end - -endmodule diff --git a/hw/rtl/cache/VX_data_access.sv b/hw/rtl/cache/VX_data_access.sv new file mode 100644 index 00000000..5b81140d --- /dev/null +++ b/hw/rtl/cache/VX_data_access.sv @@ -0,0 +1,136 @@ +`include "VX_cache_define.vh" + +module VX_data_access #( + parameter CACHE_ID = 0, + parameter BANK_ID = 0, + // Size of cache in bytes + parameter CACHE_SIZE = 1, + // Size of line inside a bank in bytes + parameter CACHE_LINE_SIZE = 1, + // Number of banks + parameter NUM_BANKS = 1, + // Number of ports per banks + parameter NUM_PORTS = 1, + // Size of a word in bytes + parameter WORD_SIZE = 1, + // Enable cache writeable + parameter WRITE_ENABLE = 1, + + parameter WORD_SELECT_BITS = `UP(`WORD_SELECT_BITS) +) ( + input wire clk, + input wire reset, + +`ifdef DBG_CACHE_REQ_INFO +`IGNORE_UNUSED_BEGIN + input wire[31:0] debug_pc, + input wire[`NW_BITS-1:0] debug_wid, +`IGNORE_UNUSED_END +`endif + + input wire stall, + + input wire read, + input wire fill, + input wire write, + input wire[`LINE_ADDR_WIDTH-1:0] addr, + input wire [NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] wsel, + input wire [NUM_PORTS-1:0] pmask, + input wire [NUM_PORTS-1:0][WORD_SIZE-1:0] byteen, + input wire [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] fill_data, + input wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] write_data, + output wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] read_data +); + `UNUSED_PARAM (CACHE_ID) + `UNUSED_PARAM (BANK_ID) + `UNUSED_PARAM (WORD_SIZE) + `UNUSED_VAR (reset) + `UNUSED_VAR (addr) + `UNUSED_VAR (read) + + localparam BYTEENW = WRITE_ENABLE ? CACHE_LINE_SIZE : 1; + + wire [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] rdata; + wire [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] wdata; + wire [BYTEENW-1:0] wren; + + wire [`LINE_SELECT_BITS-1:0] line_addr = addr[`LINE_SELECT_BITS-1:0]; + + if (WRITE_ENABLE) begin + if (`WORDS_PER_LINE > 1) begin + reg [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] wdata_r; + reg [`WORDS_PER_LINE-1:0][WORD_SIZE-1:0] wren_r; + if (NUM_PORTS > 1) begin + always @(*) begin + wdata_r = 'x; + wren_r = 0; + for (integer i = 0; i < NUM_PORTS; ++i) begin + if (pmask[i]) begin + wdata_r[wsel[i]] = write_data[i]; + wren_r[wsel[i]] = byteen[i]; + end + end + end + end else begin + `UNUSED_VAR (pmask) + always @(*) begin + wdata_r = {`WORDS_PER_LINE{write_data}}; + wren_r = 0; + wren_r[wsel] = byteen; + end + end + assign wdata = write ? wdata_r : fill_data; + assign wren = write ? wren_r : {BYTEENW{fill}}; + end else begin + `UNUSED_VAR (wsel) + `UNUSED_VAR (pmask) + assign wdata = write ? write_data : fill_data; + assign wren = write ? byteen : {BYTEENW{fill}}; + end + end else begin + `UNUSED_VAR (write) + `UNUSED_VAR (byteen) + `UNUSED_VAR (pmask) + `UNUSED_VAR (write_data) + assign wdata = fill_data; + assign wren = fill; + end + + VX_sp_ram #( + .DATAW (`CACHE_LINE_WIDTH), + .SIZE (`LINES_PER_BANK), + .BYTEENW (BYTEENW), + .NO_RWCHECK (1) + ) data_store ( + .clk (clk), + .addr (line_addr), + .wren (wren), + .wdata (wdata), + .rdata (rdata) + ); + + if (`WORDS_PER_LINE > 1) begin + for (genvar i = 0; i < NUM_PORTS; ++i) begin + assign read_data[i] = rdata[wsel[i]]; + end + end else begin + assign read_data = rdata; + end + + `UNUSED_VAR (stall) + +`ifdef DBG_PRINT_CACHE_DATA + always @(posedge clk) begin + if (fill && ~stall) begin + dpi_trace("%d: cache%0d:%0d data-fill: addr=%0h, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr, fill_data); + end + if (read && ~stall) begin + dpi_trace("%d: cache%0d:%0d data-read: addr=%0h, wid=%0d, PC=%0h, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, line_addr, read_data); + end + if (write && ~stall) begin + dpi_trace("%d: cache%0d:%0d data-write: addr=%0h, wid=%0d, PC=%0h, byteen=%b, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, byteen, line_addr, write_data); + end + end +`endif + +endmodule \ No newline at end of file diff --git a/hw/rtl/cache/VX_data_access.v b/hw/rtl/cache/VX_data_access.v deleted file mode 100644 index 338077fd..00000000 --- a/hw/rtl/cache/VX_data_access.v +++ /dev/null @@ -1,93 +0,0 @@ -`include "VX_cache_define.vh" - -module VX_data_access #( - parameter CACHE_ID = 0, - parameter BANK_ID = 0, - // Size of cache in bytes - parameter CACHE_SIZE = 1, - // Size of line inside a bank in bytes - parameter CACHE_LINE_SIZE = 1, - // Number of banks - parameter NUM_BANKS = 1, - // Size of a word in bytes - parameter WORD_SIZE = 1, - // Enable cache writeable - parameter WRITE_ENABLE = 1 -) ( - input wire clk, - input wire reset, - -`ifdef DBG_CACHE_REQ_INFO -`IGNORE_WARNINGS_BEGIN - input wire[31:0] debug_pc, - input wire[`NW_BITS-1:0] debug_wid, -`IGNORE_WARNINGS_END -`endif - -`IGNORE_WARNINGS_BEGIN - input wire[`LINE_ADDR_WIDTH-1:0] addr, -`IGNORE_WARNINGS_END - - // reading - input wire readen, - output wire [`CACHE_LINE_WIDTH-1:0] rdata, - - // writing - input wire writeen, - input wire is_fill, - input wire [CACHE_LINE_SIZE-1:0] byteen, - input wire [`CACHE_LINE_WIDTH-1:0] wdata -); - - `UNUSED_PARAM (CACHE_ID) - `UNUSED_PARAM (BANK_ID) - `UNUSED_PARAM (WORD_SIZE) - `UNUSED_VAR (reset) - `UNUSED_VAR (readen) - - localparam BYTEENW = WRITE_ENABLE ? CACHE_LINE_SIZE : 1; - - wire [`LINE_SELECT_BITS-1:0] line_addr; - wire [BYTEENW-1:0] byte_enable; - - assign line_addr = addr[`LINE_SELECT_BITS-1:0]; - - if (WRITE_ENABLE) begin - assign byte_enable = is_fill ? {BYTEENW{1'b1}} : byteen; - end else begin - `UNUSED_VAR (byteen) - `UNUSED_VAR (is_fill) - assign byte_enable = 1'b1; - end - - VX_sp_ram #( - .DATAW (CACHE_LINE_SIZE * 8), - .SIZE (`LINES_PER_BANK), - .BYTEENW (BYTEENW), - .RWCHECK (1) - ) data_store ( - .clk(clk), - .addr(line_addr), - .wren(writeen), - .byteen(byte_enable), - .rden(1'b1), - .din(wdata), - .dout(rdata) - ); - -`ifdef DBG_PRINT_CACHE_DATA - always @(posedge clk) begin - if (writeen) begin - if (is_fill) begin - $display("%t: cache%0d:%0d data-fill: addr=%0h, blk_addr=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr, wdata); - end else begin - $display("%t: cache%0d:%0d data-write: addr=%0h, wid=%0d, PC=%0h, byteen=%b, blk_addr=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, byte_enable, line_addr, wdata); - end - end - if (readen) begin - $display("%t: cache%0d:%0d data-read: addr=%0h, wid=%0d, PC=%0h, blk_addr=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, line_addr, rdata); - end - end -`endif - -endmodule \ No newline at end of file diff --git a/hw/rtl/cache/VX_flush_ctrl.v b/hw/rtl/cache/VX_flush_ctrl.sv similarity index 100% rename from hw/rtl/cache/VX_flush_ctrl.v rename to hw/rtl/cache/VX_flush_ctrl.sv diff --git a/hw/rtl/cache/VX_miss_resrv.sv b/hw/rtl/cache/VX_miss_resrv.sv new file mode 100644 index 00000000..152a6702 --- /dev/null +++ b/hw/rtl/cache/VX_miss_resrv.sv @@ -0,0 +1,240 @@ +`include "VX_cache_define.vh" + +module VX_miss_resrv #( + parameter CACHE_ID = 0, + parameter BANK_ID = 0, + + // Number of Word requests per cycle + parameter NUM_REQS = 1, + + // Size of line inside a bank in bytes + parameter CACHE_LINE_SIZE = 1, + // Number of banks + parameter NUM_BANKS = 1, + // Number of ports per banks + parameter NUM_PORTS = 1, + // Size of a word in bytes + parameter WORD_SIZE = 1, + // Miss Reserv Queue Knob + parameter MSHR_SIZE = 1, + // core request tag size + parameter CORE_TAG_WIDTH = 1, + + parameter MSHR_ADDR_WIDTH = $clog2(MSHR_SIZE) +) ( + input wire clk, + input wire reset, + +`ifdef DBG_CACHE_REQ_INFO +`IGNORE_UNUSED_BEGIN + input wire[31:0] deq_debug_pc, + input wire[`NW_BITS-1:0] deq_debug_wid, + input wire[31:0] lkp_debug_pc, + input wire[`NW_BITS-1:0] lkp_debug_wid, + input wire[31:0] rel_debug_pc, + input wire[`NW_BITS-1:0] rel_debug_wid, +`IGNORE_UNUSED_END +`endif + + // allocate + input wire allocate_valid, + input wire [`LINE_ADDR_WIDTH-1:0] allocate_addr, + input wire [`MSHR_DATA_WIDTH-1:0] allocate_data, + output wire [MSHR_ADDR_WIDTH-1:0] allocate_id, + output wire allocate_ready, + + // fill + input wire fill_valid, + input wire [MSHR_ADDR_WIDTH-1:0] fill_id, + output wire [`LINE_ADDR_WIDTH-1:0] fill_addr, + + // lookup + input wire lookup_valid, + input wire lookup_replay, + input wire [MSHR_ADDR_WIDTH-1:0] lookup_id, + input wire [`LINE_ADDR_WIDTH-1:0] lookup_addr, + output wire lookup_match, + + // dequeue + output wire dequeue_valid, + output wire [MSHR_ADDR_WIDTH-1:0] dequeue_id, + output wire [`LINE_ADDR_WIDTH-1:0] dequeue_addr, + output wire [`MSHR_DATA_WIDTH-1:0] dequeue_data, + input wire dequeue_ready, + + // release + input wire release_valid, + input wire [MSHR_ADDR_WIDTH-1:0] release_id +); + `UNUSED_PARAM (CACHE_ID) + `UNUSED_PARAM (BANK_ID) + + reg [MSHR_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] addr_table, addr_table_n; + reg [MSHR_SIZE-1:0] valid_table, valid_table_n; + reg [MSHR_SIZE-1:0] ready_table, ready_table_n; + + reg allocate_rdy_r, allocate_rdy_n; + reg [MSHR_ADDR_WIDTH-1:0] allocate_id_r, allocate_id_n; + + reg dequeue_val_r, dequeue_val_n, dequeue_val_x; + reg [MSHR_ADDR_WIDTH-1:0] dequeue_id_r, dequeue_id_n, dequeue_id_x; + + reg [MSHR_SIZE-1:0] valid_table_x; + reg [MSHR_SIZE-1:0] ready_table_x; + + wire [MSHR_SIZE-1:0] addr_matches; + + wire allocate_fire = allocate_valid && allocate_ready; + + wire dequeue_fire = dequeue_valid && dequeue_ready; + + for (genvar i = 0; i < MSHR_SIZE; ++i) begin + assign addr_matches[i] = (addr_table[i] == lookup_addr); + end + + always @(*) begin + valid_table_x = valid_table; + ready_table_x = ready_table; + if (dequeue_fire) begin + valid_table_x[dequeue_id] = 0; + end + if (lookup_replay) begin + ready_table_x |= addr_matches; + end + end + + VX_lzc #( + .N (MSHR_SIZE) + ) dequeue_sel ( + .in_i (valid_table_x & ready_table_x), + .cnt_o (dequeue_id_x), + .valid_o (dequeue_val_x) + ); + + VX_lzc #( + .N (MSHR_SIZE) + ) allocate_sel ( + .in_i (~valid_table_n), + .cnt_o (allocate_id_n), + .valid_o (allocate_rdy_n) + ); + + always @(*) begin + valid_table_n = valid_table_x; + ready_table_n = ready_table_x; + addr_table_n = addr_table; + dequeue_val_n = dequeue_val_r; + dequeue_id_n = dequeue_id_r; + + if (dequeue_fire) begin + dequeue_val_n = dequeue_val_x; + dequeue_id_n = dequeue_id_x; + end + + if (allocate_fire) begin + valid_table_n[allocate_id] = 1; + ready_table_n[allocate_id] = 0; + addr_table_n[allocate_id] = allocate_addr; + end + + if (fill_valid) begin + dequeue_val_n = 1; + dequeue_id_n = fill_id; + end + + if (release_valid) begin + valid_table_n[release_id] = 0; + end + end + + always @(posedge clk) begin + if (reset) begin + valid_table <= 0; + allocate_rdy_r <= 0; + dequeue_val_r <= 0; + end else begin + valid_table <= valid_table_n; + allocate_rdy_r <= allocate_rdy_n; + dequeue_val_r <= dequeue_val_n; + end + ready_table <= ready_table_n; + addr_table <= addr_table_n; + dequeue_id_r <= dequeue_id_n; + allocate_id_r <= allocate_id_n; + + `ASSERT(!allocate_fire || !valid_table[allocate_id_r], ("runtime error")); + `ASSERT(!release_valid || valid_table[release_id], ("runtime error")); + end + + `RUNTIME_ASSERT((!allocate_fire || ~valid_table[allocate_id]), ("%t: *** cache%0d:%0d in-use allocation: addr=%0h, id=%0d", $time, CACHE_ID, BANK_ID, + `LINE_TO_BYTE_ADDR(allocate_addr, BANK_ID), allocate_id)) + + `RUNTIME_ASSERT((!fill_valid || valid_table[fill_id]), ("%t: *** cache%0d:%0d invalid fill: addr=%0h, id=%0d", $time, CACHE_ID, BANK_ID, + `LINE_TO_BYTE_ADDR(addr_table[fill_id], BANK_ID), fill_id)) + + VX_dp_ram #( + .DATAW (`MSHR_DATA_WIDTH), + .SIZE (MSHR_SIZE), + .LUTRAM (1) + ) entries ( + .clk (clk), + .waddr (allocate_id_r), + .raddr (dequeue_id_r), + .wren (allocate_valid), + .wdata (allocate_data), + .rdata (dequeue_data) + ); + + assign fill_addr = addr_table[fill_id]; + + assign allocate_ready = allocate_rdy_r; + assign allocate_id = allocate_id_r; + + assign dequeue_valid = dequeue_val_r; + assign dequeue_id = dequeue_id_r; + assign dequeue_addr = addr_table[dequeue_id_r]; + + wire [MSHR_SIZE-1:0] lookup_entries; + for (genvar i = 0; i < MSHR_SIZE; ++i) begin + assign lookup_entries[i] = (i != lookup_id); + end + assign lookup_match = |(lookup_entries & valid_table & addr_matches); + + `UNUSED_VAR (lookup_valid) + +`ifdef DBG_PRINT_CACHE_MSHR + always @(posedge clk) begin + if (allocate_fire || fill_valid || dequeue_fire || lookup_replay || lookup_valid || release_valid) begin + if (allocate_fire) + dpi_trace("%d: cache%0d:%0d mshr-allocate: addr=%0h, id=%0d, wid=%0d, PC=%0h\n", $time, CACHE_ID, BANK_ID, + `LINE_TO_BYTE_ADDR(allocate_addr, BANK_ID), allocate_id, deq_debug_wid, deq_debug_pc); + if (fill_valid) + dpi_trace("%d: cache%0d:%0d mshr-fill: addr=%0h, id=%0d, addr=%0h\n", $time, CACHE_ID, BANK_ID, + `LINE_TO_BYTE_ADDR(addr_table[fill_id], BANK_ID), fill_id, `LINE_TO_BYTE_ADDR(fill_addr, BANK_ID)); + if (dequeue_fire) + dpi_trace("%d: cache%0d:%0d mshr-dequeue: addr=%0h, id=%0d, wid=%0d, PC=%0h\n", $time, CACHE_ID, BANK_ID, + `LINE_TO_BYTE_ADDR(dequeue_addr, BANK_ID), dequeue_id_r, deq_debug_wid, deq_debug_pc); + if (lookup_replay) + dpi_trace("%d: cache%0d:%0d mshr-replay: addr=%0h, id=%0d\n", $time, CACHE_ID, BANK_ID, + `LINE_TO_BYTE_ADDR(lookup_addr, BANK_ID), lookup_id); + if (lookup_valid) + dpi_trace("%d: cache%0d:%0d mshr-lookup: addr=%0h, id=%0d, match=%b, wid=%0d, PC=%0h\n", $time, CACHE_ID, BANK_ID, + `LINE_TO_BYTE_ADDR(lookup_addr, BANK_ID), lookup_id, lookup_match, lkp_debug_wid, lkp_debug_pc); + if (release_valid) + dpi_trace("%d: cache%0d:%0d mshr-release id=%0d, wid=%0d, PC=%0h\n", $time, CACHE_ID, BANK_ID, + release_id, rel_debug_wid, rel_debug_pc); + dpi_trace("%d: cache%0d:%0d mshr-table", $time, CACHE_ID, BANK_ID); + for (integer i = 0; i < MSHR_SIZE; ++i) begin + if (valid_table[i]) begin + dpi_trace(" "); + if (ready_table[i]) + dpi_trace("*"); + dpi_trace("%0d=%0h", i, `LINE_TO_BYTE_ADDR(addr_table[i], BANK_ID)); + end + end + dpi_trace("\n"); + end + end +`endif + +endmodule \ No newline at end of file diff --git a/hw/rtl/cache/VX_miss_resrv.v b/hw/rtl/cache/VX_miss_resrv.v deleted file mode 100644 index 99eda525..00000000 --- a/hw/rtl/cache/VX_miss_resrv.v +++ /dev/null @@ -1,233 +0,0 @@ -`include "VX_cache_define.vh" - -module VX_miss_resrv #( - parameter CACHE_ID = 0, - parameter BANK_ID = 0, - - // Number of Word requests per cycle - parameter NUM_REQS = 1, - - // Size of line inside a bank in bytes - parameter CACHE_LINE_SIZE = 1, - // Number of banks - parameter NUM_BANKS = 1, - // Number of ports per banks - parameter NUM_PORTS = 1, - // Size of a word in bytes - parameter WORD_SIZE = 1, - // Miss Reserv Queue Knob - parameter MSHR_SIZE = 1, - parameter ALM_FULL = (MSHR_SIZE-1), - // core request tag size - parameter CORE_TAG_WIDTH = 1 -) ( - input wire clk, - input wire reset, - -`ifdef DBG_CACHE_REQ_INFO -`IGNORE_WARNINGS_BEGIN - input wire[31:0] deq_debug_pc, - input wire[`NW_BITS-1:0] deq_debug_wid, - input wire[31:0] enq_debug_pc, - input wire[`NW_BITS-1:0] enq_debug_wid, -`IGNORE_WARNINGS_END -`endif - - // enqueue - input wire enqueue, - input wire [`LINE_ADDR_WIDTH-1:0] enqueue_addr, - input wire [`MSHR_DATA_WIDTH-1:0] enqueue_data, - input wire enqueue_is_mshr, - input wire enqueue_as_ready, - output wire enqueue_full, - output wire enqueue_almfull, - - // fill - input wire fill_start, - input wire [`LINE_ADDR_WIDTH-1:0] fill_addr, - - // lookup - input wire [`LINE_ADDR_WIDTH-1:0] lookup_addr, - output wire lookup_match, - input wire lookup_fill, - - // schedule - input wire schedule, - output wire schedule_valid, - output wire [`LINE_ADDR_WIDTH-1:0] schedule_addr, - output wire [`MSHR_DATA_WIDTH-1:0] schedule_data, - - // dequeue - input wire dequeue -); - `UNUSED_PARAM (CACHE_ID) - `UNUSED_PARAM (BANK_ID) - localparam ADDRW = $clog2(MSHR_SIZE); - - reg [MSHR_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] addr_table; - - reg [MSHR_SIZE-1:0] valid_table, valid_table_n; - reg [MSHR_SIZE-1:0] ready_table, ready_table_n; - reg [ADDRW-1:0] head_ptr, head_ptr_n; - reg [ADDRW-1:0] tail_ptr, tail_ptr_n; - reg [ADDRW-1:0] restore_ptr, restore_ptr_n; - reg [ADDRW-1:0] schedule_ptr, schedule_ptr_n; - reg [ADDRW-1:0] used_r; - reg alm_full_r, full_r; - reg valid_out_r; - - wire [MSHR_SIZE-1:0] valid_address_match; - for (genvar i = 0; i < MSHR_SIZE; i++) begin - assign valid_address_match[i] = valid_table[i] && (addr_table[i] == lookup_addr); - end - - wire push_new = enqueue && !enqueue_is_mshr; - - wire restore = enqueue && enqueue_is_mshr; - - always @(*) begin - valid_table_n = valid_table; - ready_table_n = ready_table; - head_ptr_n = head_ptr; - tail_ptr_n = tail_ptr; - schedule_ptr_n = schedule_ptr; - restore_ptr_n = restore_ptr; - - if (lookup_fill) begin - // unlock pending requests for scheduling - ready_table_n |= valid_address_match; - end - - if (schedule) begin - // schedule next entry - schedule_ptr_n = schedule_ptr + 1; - valid_table_n[schedule_ptr] = 0; - ready_table_n[schedule_ptr] = 0; - end - - if (fill_start && (fill_addr == addr_table[schedule_ptr])) begin - ready_table_n[schedule_ptr] = valid_table[schedule_ptr]; - end - - if (push_new) begin - // push new entry - valid_table_n[tail_ptr] = 1; - ready_table_n[tail_ptr] = enqueue_as_ready; - tail_ptr_n = tail_ptr + 1; - end else if (restore) begin - // restore schedule, returning missed mshr entry - valid_table_n[restore_ptr] = 1; - ready_table_n[restore_ptr] = enqueue_as_ready; - restore_ptr_n = restore_ptr + 1; - schedule_ptr_n = head_ptr; - end else if (dequeue) begin - // clear scheduled entry - head_ptr_n = head_ptr + 1; - restore_ptr_n = head_ptr_n; - end - end - - always @(posedge clk) begin - if (reset) begin - valid_table <= 0; - ready_table <= 0; - head_ptr <= 0; - tail_ptr <= 0; - schedule_ptr <= 0; - restore_ptr <= 0; - used_r <= 0; - alm_full_r <= 0; - full_r <= 0; - valid_out_r <= 0; - end else begin - if (schedule) begin - assert(schedule_valid); - assert(!fill_start); - assert(!restore); - end - - if (push_new) begin - assert(!full_r); - end else if (restore) begin - assert(!schedule); - end - - if (push_new) begin - if (!dequeue) begin - if (used_r == ADDRW'(ALM_FULL-1)) - alm_full_r <= 1; - if (used_r == ADDRW'(MSHR_SIZE-1)) - full_r <= 1; - end - end else if (dequeue) begin - if (used_r == ADDRW'(ALM_FULL)) - alm_full_r <= 0; - full_r <= 0; - end - - used_r <= used_r + ADDRW'($signed(2'(push_new) - 2'(dequeue))); - - valid_table <= valid_table_n; - ready_table <= ready_table_n; - head_ptr <= head_ptr_n; - tail_ptr <= tail_ptr_n; - schedule_ptr <= schedule_ptr_n; - restore_ptr <= restore_ptr_n; - valid_out_r <= ready_table_n[schedule_ptr_n]; - end - - if (push_new) begin - addr_table[tail_ptr] <= enqueue_addr; - end - end - - VX_dp_ram #( - .DATAW (`MSHR_DATA_WIDTH), - .SIZE (MSHR_SIZE), - .RWCHECK (1), - .FASTRAM (1) - ) entries ( - .clk (clk), - .waddr (tail_ptr), - .raddr (schedule_ptr), - .wren (push_new), - .byteen (1'b1), - .rden (1'b1), - .din (enqueue_data), - .dout (schedule_data) - ); - - assign lookup_match = (| valid_address_match); - assign schedule_valid = valid_out_r; - assign schedule_addr = addr_table[schedule_ptr]; - assign enqueue_almfull = alm_full_r; - assign enqueue_full = full_r; - -`ifdef DBG_PRINT_CACHE_MSHR - always @(posedge clk) begin - if (lookup_fill || schedule || enqueue || dequeue) begin - if (schedule) - $display("%t: cache%0d:%0d mshr-schedule: addr%0d=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, schedule_ptr, `LINE_TO_BYTE_ADDR(schedule_addr, BANK_ID), deq_debug_wid, deq_debug_pc); - if (enqueue) begin - if (enqueue_is_mshr) - $display("%t: cache%0d:%0d mshr-restore: addr%0d=%0h, ready=%b", $time, CACHE_ID, BANK_ID, restore_ptr, `LINE_TO_BYTE_ADDR(enqueue_addr, BANK_ID), enqueue_as_ready); - else - $display("%t: cache%0d:%0d mshr-enqueue: addr%0d=%0h, ready=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, tail_ptr, `LINE_TO_BYTE_ADDR(enqueue_addr, BANK_ID), enqueue_as_ready, enq_debug_wid, enq_debug_pc); - end - if (dequeue) - $display("%t: cache%0d:%0d mshr-dequeue addr%0d, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, head_ptr, enq_debug_wid, enq_debug_pc); - $write("%t: cache%0d:%0d mshr-table", $time, CACHE_ID, BANK_ID); - for (integer j = 0; j < MSHR_SIZE; j++) begin - if (valid_table[j]) begin - $write(" "); - if (schedule_ptr == $bits(schedule_ptr)'(j)) $write("*"); - if (~ready_table[j]) $write("!"); - $write("addr%0d=%0h", j, `LINE_TO_BYTE_ADDR(addr_table[j], BANK_ID)); - end - end - $write("\n"); - end - end -`endif - -endmodule \ No newline at end of file diff --git a/hw/rtl/cache/VX_nc_bypass.v b/hw/rtl/cache/VX_nc_bypass.sv similarity index 71% rename from hw/rtl/cache/VX_nc_bypass.v rename to hw/rtl/cache/VX_nc_bypass.sv index a1cf3156..21eb440a 100644 --- a/hw/rtl/cache/VX_nc_bypass.v +++ b/hw/rtl/cache/VX_nc_bypass.sv @@ -1,6 +1,7 @@ `include "VX_cache_define.vh" module VX_nc_bypass #( + parameter NUM_PORTS = 1, parameter NUM_REQS = 1, parameter NUM_RSP_TAGS = 0, parameter NC_TAG_BIT = 0, @@ -10,13 +11,14 @@ module VX_nc_bypass #( parameter CORE_TAG_IN_WIDTH = 1, parameter MEM_ADDR_WIDTH = 1, - parameter MEM_DATA_SIZE = 1, + parameter MEM_DATA_SIZE = 1, parameter MEM_TAG_IN_WIDTH = 1, parameter MEM_TAG_OUT_WIDTH = 1, - localparam CORE_DATA_WIDTH = CORE_DATA_SIZE * 8, - localparam MEM_DATA_WIDTH = MEM_DATA_SIZE * 8, - localparam CORE_TAG_OUT_WIDTH = CORE_TAG_IN_WIDTH - 1 + parameter CORE_DATA_WIDTH = CORE_DATA_SIZE * 8, + parameter MEM_DATA_WIDTH = MEM_DATA_SIZE * 8, + parameter CORE_TAG_OUT_WIDTH = CORE_TAG_IN_WIDTH - 1, + parameter MEM_SELECT_BITS = `UP(`CLOG2(MEM_DATA_SIZE / CORE_DATA_SIZE)) ) ( input wire clk, input wire reset, @@ -57,8 +59,10 @@ module VX_nc_bypass #( input wire mem_req_valid_in, input wire mem_req_rw_in, input wire [MEM_ADDR_WIDTH-1:0] mem_req_addr_in, - input wire [MEM_DATA_SIZE-1:0] mem_req_byteen_in, - input wire [MEM_DATA_WIDTH-1:0] mem_req_data_in, + input wire [NUM_PORTS-1:0] mem_req_pmask_in, + input wire [NUM_PORTS-1:0][CORE_DATA_SIZE-1:0] mem_req_byteen_in, + input wire [NUM_PORTS-1:0][MEM_SELECT_BITS-1:0] mem_req_wsel_in, + input wire [NUM_PORTS-1:0][CORE_DATA_WIDTH-1:0] mem_req_data_in, input wire [MEM_TAG_IN_WIDTH-1:0] mem_req_tag_in, output wire mem_req_ready_in, @@ -66,8 +70,10 @@ module VX_nc_bypass #( output wire mem_req_valid_out, output wire mem_req_rw_out, output wire [MEM_ADDR_WIDTH-1:0] mem_req_addr_out, - output wire [MEM_DATA_SIZE-1:0] mem_req_byteen_out, - output wire [MEM_DATA_WIDTH-1:0] mem_req_data_out, + output wire [NUM_PORTS-1:0] mem_req_pmask_out, + output wire [NUM_PORTS-1:0][CORE_DATA_SIZE-1:0] mem_req_byteen_out, + output wire [NUM_PORTS-1:0][MEM_SELECT_BITS-1:0] mem_req_wsel_out, + output wire [NUM_PORTS-1:0][CORE_DATA_WIDTH-1:0] mem_req_data_out, output wire [MEM_TAG_OUT_WIDTH-1:0] mem_req_tag_out, input wire mem_req_ready_out, @@ -99,9 +105,9 @@ module VX_nc_bypass #( // core request handling wire [NUM_REQS-1:0] core_req_valid_in_nc; - wire [NUM_REQS-1:0] core_req_nc_sel; wire [NUM_REQS-1:0] core_req_nc_tids; wire [`UP(CORE_REQ_TIDW)-1:0] core_req_nc_tid; + wire [NUM_REQS-1:0] core_req_nc_sel; wire core_req_nc_valid; for (genvar i = 0; i < NUM_REQS; ++i) begin @@ -142,7 +148,6 @@ module VX_nc_bypass #( (~mem_req_valid_in && mem_req_ready_out && core_req_nc_sel[i]) : core_req_ready_out[i]; end end else begin - `UNUSED_VAR (core_req_nc_sel) assign core_req_ready_in = core_req_valid_in_nc ? (~mem_req_valid_in && mem_req_ready_out) : core_req_ready_out; end @@ -151,7 +156,7 @@ module VX_nc_bypass #( assign mem_req_valid_out = mem_req_valid_in || core_req_nc_valid; assign mem_req_ready_in = mem_req_ready_out; - wire [(MEM_TAG_IN_WIDTH+1)-1:0] mem_req_tag_in_nc; + wire [(MEM_TAG_IN_WIDTH+1)-1:0] mem_req_tag_in_c; VX_bits_insert #( .N (MEM_TAG_IN_WIDTH), @@ -160,81 +165,69 @@ module VX_nc_bypass #( ) mem_req_tag_insert ( .data_in (mem_req_tag_in), .sel_in ('0), - .data_out (mem_req_tag_in_nc) + .data_out (mem_req_tag_in_c) ); + wire [CORE_TAG_IN_WIDTH-1:0] core_req_tag_in_sel; + wire [CORE_DATA_WIDTH-1:0] core_req_data_in_sel; + wire [CORE_DATA_SIZE-1:0] core_req_byteen_in_sel; + wire [CORE_ADDR_WIDTH-1:0] core_req_addr_in_sel; + wire core_req_rw_in_sel; + if (NUM_REQS > 1) begin - - wire [CORE_TAG_IN_WIDTH-1:0] core_req_tag_in_sel; - wire [CORE_DATA_WIDTH-1:0] core_req_data_in_sel; - wire [CORE_DATA_SIZE-1:0] core_req_byteen_in_sel; - wire [CORE_ADDR_WIDTH-1:0] core_req_addr_in_sel; - wire core_req_rw_in_sel; - wire [NUM_REQS-1:0][MUX_DATAW-1:0] core_req_nc_mux_in; for (genvar i = 0; i < NUM_REQS; ++i) begin assign core_req_nc_mux_in[i] = {core_req_tag_in[i], core_req_data_in[i], core_req_byteen_in[i], core_req_addr_in[i], core_req_rw_in[i]}; end - VX_onehot_mux #( - .DATAW (MUX_DATAW), - .N (NUM_REQS) - ) core_req_nc_mux ( - .data_in (core_req_nc_mux_in), - .sel_in (core_req_nc_sel), - .data_out ({core_req_tag_in_sel, core_req_data_in_sel, core_req_byteen_in_sel, core_req_addr_in_sel, core_req_rw_in_sel}) - ); - - assign mem_req_rw_out = mem_req_valid_in ? mem_req_rw_in : core_req_rw_in_sel; - assign mem_req_addr_out = mem_req_valid_in ? mem_req_addr_in : core_req_addr_in_sel[D +: MEM_ADDR_WIDTH]; - - for (genvar i = 0; i < P; ++i) begin - assign mem_req_data_out[i * CORE_DATA_WIDTH +: CORE_DATA_WIDTH] = mem_req_valid_in ? - mem_req_data_in[i * CORE_DATA_WIDTH +: CORE_DATA_WIDTH] : core_req_data_in_sel; - end - - if (D != 0) begin - wire [D-1:0] req_addr_idx = core_req_addr_in_sel[D-1:0]; - reg [MEM_DATA_SIZE-1:0] mem_req_byteen_in_r; - always @(*) begin - mem_req_byteen_in_r = 0; - mem_req_byteen_in_r[req_addr_idx * CORE_DATA_SIZE +: CORE_DATA_SIZE] = core_req_byteen_in_sel; - end - assign mem_req_byteen_out = mem_req_valid_in ? mem_req_byteen_in : mem_req_byteen_in_r; - assign mem_req_tag_out = mem_req_valid_in ? MEM_TAG_OUT_WIDTH'(mem_req_tag_in_nc) : MEM_TAG_OUT_WIDTH'({core_req_nc_tid, req_addr_idx, core_req_tag_in_sel}); - end else begin - assign mem_req_byteen_out = mem_req_valid_in ? mem_req_byteen_in : core_req_byteen_in_sel; - assign mem_req_tag_out = mem_req_valid_in ? MEM_TAG_OUT_WIDTH'(mem_req_tag_in_nc) : MEM_TAG_OUT_WIDTH'({core_req_nc_tid, core_req_tag_in_sel}); - end + assign {core_req_tag_in_sel, core_req_data_in_sel, core_req_byteen_in_sel, core_req_addr_in_sel, core_req_rw_in_sel} = core_req_nc_mux_in[core_req_nc_tid]; end else begin - `UNUSED_VAR (core_req_nc_tid) + assign core_req_tag_in_sel = core_req_tag_in; + assign core_req_data_in_sel = core_req_data_in; + assign core_req_byteen_in_sel = core_req_byteen_in; + assign core_req_addr_in_sel = core_req_addr_in; + assign core_req_rw_in_sel = core_req_rw_in; + end + + assign mem_req_rw_out = mem_req_valid_in ? mem_req_rw_in : core_req_rw_in_sel; + assign mem_req_addr_out = mem_req_valid_in ? mem_req_addr_in : core_req_addr_in_sel[D +: MEM_ADDR_WIDTH]; + + if (D != 0) begin + reg [NUM_PORTS-1:0][CORE_DATA_SIZE-1:0] mem_req_byteen_in_r; + reg [NUM_PORTS-1:0][MEM_SELECT_BITS-1:0] mem_req_wsel_in_r; + reg [NUM_PORTS-1:0][CORE_DATA_WIDTH-1:0] mem_req_data_in_r; + + wire [D-1:0] req_addr_idx = core_req_addr_in_sel[D-1:0]; - assign mem_req_rw_out = mem_req_valid_in ? mem_req_rw_in : core_req_rw_in; - assign mem_req_addr_out = mem_req_valid_in ? mem_req_addr_in : core_req_addr_in[0][D +: MEM_ADDR_WIDTH]; + always @(*) begin + mem_req_byteen_in_r = 0; + mem_req_byteen_in_r[0] = core_req_byteen_in_sel; - for (genvar i = 0; i < P; ++i) begin - assign mem_req_data_out[i * CORE_DATA_WIDTH +: CORE_DATA_WIDTH] = mem_req_valid_in ? - mem_req_data_in[i * CORE_DATA_WIDTH +: CORE_DATA_WIDTH] : core_req_data_in; + mem_req_wsel_in_r = 'x; + mem_req_wsel_in_r[0] = req_addr_idx; + + mem_req_data_in_r = 'x; + mem_req_data_in_r[0] = core_req_data_in_sel; end - if (D != 0) begin - wire [D-1:0] req_addr_idx = core_req_addr_in[0][D-1:0]; - reg [MEM_DATA_SIZE-1:0] mem_req_byteen_in_r; - always @(*) begin - mem_req_byteen_in_r = 0; - mem_req_byteen_in_r[req_addr_idx * CORE_DATA_SIZE +: CORE_DATA_SIZE] = core_req_byteen_in; - end - assign mem_req_byteen_out = mem_req_valid_in ? mem_req_byteen_in : mem_req_byteen_in_r; - assign mem_req_tag_out = mem_req_valid_in ? MEM_TAG_OUT_WIDTH'(mem_req_tag_in_nc) : MEM_TAG_OUT_WIDTH'({req_addr_idx, core_req_tag_in}); - end else begin - assign mem_req_byteen_out = mem_req_valid_in ? mem_req_byteen_in : core_req_byteen_in; - assign mem_req_tag_out = mem_req_valid_in ? MEM_TAG_OUT_WIDTH'(mem_req_tag_in_nc) : MEM_TAG_OUT_WIDTH'(core_req_tag_in); - end + assign mem_req_pmask_out = mem_req_valid_in ? mem_req_pmask_in : NUM_PORTS'(1'b1); + assign mem_req_byteen_out = mem_req_valid_in ? mem_req_byteen_in : mem_req_byteen_in_r; + assign mem_req_wsel_out = mem_req_valid_in ? mem_req_wsel_in : mem_req_wsel_in_r; + assign mem_req_data_out = mem_req_valid_in ? mem_req_data_in : mem_req_data_in_r; + assign mem_req_tag_out = mem_req_valid_in ? MEM_TAG_OUT_WIDTH'(mem_req_tag_in_c) : MEM_TAG_OUT_WIDTH'({core_req_nc_tid, req_addr_idx, core_req_tag_in_sel}); + end else begin + `UNUSED_VAR (mem_req_wsel_in) + `UNUSED_VAR (mem_req_pmask_in) + assign mem_req_pmask_out = 0; + assign mem_req_byteen_out = mem_req_valid_in ? mem_req_byteen_in : core_req_byteen_in_sel; + assign mem_req_data_out = mem_req_valid_in ? mem_req_data_in : core_req_data_in_sel; + assign mem_req_wsel_out = 0; + assign mem_req_tag_out = mem_req_valid_in ? MEM_TAG_OUT_WIDTH'(mem_req_tag_in_c) : MEM_TAG_OUT_WIDTH'({core_req_nc_tid, core_req_tag_in_sel}); end // core response handling - wire [NUM_RSP_TAGS-1:0][CORE_TAG_IN_WIDTH-1:0] core_rsp_tag_out_unqual; + wire [NUM_RSP_TAGS-1:0][CORE_TAG_IN_WIDTH-1:0] core_rsp_tag_out_c; wire is_mem_rsp_nc = mem_rsp_valid_in && mem_rsp_tag_in[NC_TAG_BIT]; @@ -246,7 +239,7 @@ module VX_nc_bypass #( ) core_rsp_tag_insert ( .data_in (core_rsp_tag_in[i]), .sel_in ('0), - .data_out (core_rsp_tag_out_unqual[i]) + .data_out (core_rsp_tag_out_c[i]) ); end @@ -272,14 +265,14 @@ module VX_nc_bypass #( for (genvar i = 0; i < NUM_REQS; ++i) begin assign core_rsp_data_out[i] = core_rsp_valid_in[i] ? core_rsp_data_in[i] : mem_rsp_data_in; end - end + end for (genvar i = 0; i < NUM_REQS; ++i) begin - assign core_rsp_tag_out[i] = core_rsp_valid_in[i] ? core_rsp_tag_out_unqual[i] : mem_rsp_tag_in[CORE_TAG_IN_WIDTH-1:0]; + assign core_rsp_tag_out[i] = core_rsp_valid_in[i] ? core_rsp_tag_out_c[i] : mem_rsp_tag_in[CORE_TAG_IN_WIDTH-1:0]; end end else begin assign core_rsp_valid_out = core_rsp_valid_in || is_mem_rsp_nc; - assign core_rsp_tag_out = core_rsp_valid_in ? core_rsp_tag_out_unqual : mem_rsp_tag_in[CORE_TAG_IN_WIDTH-1:0]; + assign core_rsp_tag_out = core_rsp_valid_in ? core_rsp_tag_out_c : mem_rsp_tag_in[CORE_TAG_IN_WIDTH-1:0]; assign core_rsp_ready_in = core_rsp_ready_out; if (NUM_REQS > 1) begin diff --git a/hw/rtl/cache/VX_shared_mem.v b/hw/rtl/cache/VX_shared_mem.sv similarity index 63% rename from hw/rtl/cache/VX_shared_mem.v rename to hw/rtl/cache/VX_shared_mem.sv index 71aaaf38..51c60a38 100644 --- a/hw/rtl/cache/VX_shared_mem.v +++ b/hw/rtl/cache/VX_shared_mem.sv @@ -24,14 +24,14 @@ module VX_shared_mem #( parameter CORE_TAG_WIDTH = (2 + CORE_TAG_ID_BITS), // bank offset from beginning of index range - parameter BANK_ADDR_OFFSET = `CLOG2(256) + parameter BANK_ADDR_OFFSET = `CLOG2(256) ) ( input wire clk, input wire reset, // PERF `ifdef PERF_ENABLE - VX_perf_cache_if perf_cache_if, + VX_perf_cache_if.master perf_cache_if, `endif // Core request @@ -64,7 +64,7 @@ module VX_shared_mem #( wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data_unqual; wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag_unqual; wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid_unqual; - wire per_bank_core_req_ready_unqual; + wire [NUM_BANKS-1:0] per_bank_core_req_ready_unqual; VX_core_req_bank_sel #( .CACHE_ID (CACHE_ID), @@ -74,8 +74,7 @@ module VX_shared_mem #( .WORD_SIZE (WORD_SIZE), .NUM_REQS (NUM_REQS), .CORE_TAG_WIDTH (CORE_TAG_WIDTH), - .BANK_ADDR_OFFSET(BANK_ADDR_OFFSET), - .SHARED_BANK_READY(1) + .BANK_ADDR_OFFSET(BANK_ADDR_OFFSET) ) core_req_bank_sel ( .clk (clk), .reset (reset), @@ -103,41 +102,34 @@ module VX_shared_mem #( wire [NUM_BANKS-1:0] per_bank_core_req_valid; wire [NUM_BANKS-1:0] per_bank_core_req_rw; - wire [NUM_BANKS-1:0][`LINE_SELECT_BITS-1:0] per_bank_core_req_addr; + wire [NUM_BANKS-1:0][`LINE_ADDR_WIDTH-1:0] per_bank_core_req_addr; wire [NUM_BANKS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen; wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data; wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag; wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid; - wire creq_in_ready; - wire creq_out_valid; - wire crsq_in_fire_last; - - wire [NUM_BANKS-1:0] per_bank_req_reads = per_bank_core_req_valid & ~per_bank_core_req_rw; - - wire per_bank_req_has_reads = (| per_bank_req_reads); - - wire creq_in_valid = (| core_req_valid); - - wire creq_out_ready = ~per_bank_req_has_reads // is write only - || crsq_in_fire_last; // is sending last read response - - assign per_bank_core_req_ready_unqual = creq_in_ready; + wire creq_out_valid, creq_out_ready; + wire creq_in_valid, creq_in_ready; wire creq_in_fire = creq_in_valid && creq_in_ready; + `UNUSED_VAR (creq_in_fire) wire creq_out_fire = creq_out_valid && creq_out_ready; + `UNUSED_VAR (creq_out_fire) - wire [NUM_BANKS-1:0][`LINE_SELECT_BITS-1:0] per_bank_core_req_addr_qual; - `UNUSED_VAR (per_bank_core_req_addr_unqual) - for (genvar i = 0; i < NUM_BANKS; i++) begin - assign per_bank_core_req_addr_qual[i] = per_bank_core_req_addr_unqual[i][`LINE_SELECT_BITS-1:0]; - end + assign creq_in_valid = (| core_req_valid); + assign per_bank_core_req_ready_unqual = {NUM_BANKS{creq_in_ready}}; + + wire [NUM_BANKS-1:0] core_req_read_mask, core_req_read_mask_unqual; + wire core_req_writeonly, core_req_writeonly_unqual; + + assign core_req_read_mask_unqual = per_bank_core_req_valid_unqual & ~per_bank_core_req_rw_unqual; + assign core_req_writeonly_unqual = ~(| core_req_read_mask_unqual); VX_elastic_buffer #( - .DATAW (NUM_BANKS * (1 + 1 + `LINE_SELECT_BITS + WORD_SIZE + `WORD_WIDTH + CORE_TAG_WIDTH + `REQS_BITS)), - .SIZE (CREQ_SIZE), - .OUTPUT_REG (1) // output should be registered for the data_store addr port + .DATAW (NUM_BANKS * (1 + 1 + `LINE_ADDR_WIDTH + WORD_SIZE + `WORD_WIDTH + CORE_TAG_WIDTH + `REQS_BITS) + NUM_BANKS + 1), + .SIZE (CREQ_SIZE), + .OUT_REG (1) // output should be registered for the data_store addr port ) core_req_queue ( .clk (clk), .reset (reset), @@ -145,44 +137,53 @@ module VX_shared_mem #( .valid_in (creq_in_valid), .data_in ({per_bank_core_req_valid_unqual, per_bank_core_req_rw_unqual, - per_bank_core_req_addr_qual, + per_bank_core_req_addr_unqual, per_bank_core_req_byteen_unqual, per_bank_core_req_data_unqual, per_bank_core_req_tag_unqual, - per_bank_core_req_tid_unqual}), + per_bank_core_req_tid_unqual, + core_req_read_mask_unqual, + core_req_writeonly_unqual}), .data_out ({per_bank_core_req_valid, per_bank_core_req_rw, per_bank_core_req_addr, per_bank_core_req_byteen, per_bank_core_req_data, per_bank_core_req_tag, - per_bank_core_req_tid}), + per_bank_core_req_tid, + core_req_read_mask, + core_req_writeonly}), .ready_out (creq_out_ready), .valid_out (creq_out_valid) ); - `UNUSED_VAR (creq_in_fire) + + wire crsq_in_valid, crsq_in_ready; + wire crsq_last_read; + + assign creq_out_ready = core_req_writeonly + || (crsq_in_ready && crsq_last_read); wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_rsp_data; for (genvar i = 0; i < NUM_BANKS; i++) begin - wire wren = per_bank_core_req_rw[i] - && per_bank_core_req_valid[i] - && creq_out_fire; + wire [WORD_SIZE-1:0] wren = per_bank_core_req_byteen[i] + & {WORD_SIZE{per_bank_core_req_valid[i] + && per_bank_core_req_rw[i]}}; + + wire [`LINE_SELECT_BITS-1:0] addr = per_bank_core_req_addr[i][`LINE_SELECT_BITS-1:0]; VX_sp_ram #( - .DATAW (`WORD_WIDTH), - .SIZE (`LINES_PER_BANK), - .BYTEENW (WORD_SIZE), - .RWCHECK (1) + .DATAW (`WORD_WIDTH), + .SIZE (`LINES_PER_BANK), + .BYTEENW (WORD_SIZE), + .NO_RWCHECK (1) ) data_store ( - .clk (clk), - .addr (per_bank_core_req_addr[i]), - .wren (wren), - .byteen (per_bank_core_req_byteen[i]), - .rden (1'b1), - .din (per_bank_core_req_data[i]), - .dout (per_bank_core_rsp_data[i]) + .clk (clk), + .addr (addr), + .wren (wren), + .wdata (per_bank_core_req_data[i]), + .rdata (per_bank_core_rsp_data[i]) ); end @@ -190,57 +191,54 @@ module VX_shared_mem #( // We first need to select the current tag to process, // then send all bank responses for that tag as a batch - wire crsq_in_valid, crsq_in_ready; - - reg [NUM_BANKS-1:0] bank_rsp_sel_prv, bank_rsp_sel_cur; - - wire [NUM_BANKS-1:0] bank_rsp_sel_n = bank_rsp_sel_prv | bank_rsp_sel_cur; + reg [NUM_REQS-1:0] core_rsp_valids_in; + reg [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data_in; + wire [CORE_TAG_WIDTH-1:0] core_rsp_tag_in; + reg [NUM_BANKS-1:0] bank_rsp_sel_r, bank_rsp_sel_n; wire crsq_in_fire = crsq_in_valid && crsq_in_ready; - assign crsq_in_fire_last = crsq_in_fire && (bank_rsp_sel_n == per_bank_req_reads); + assign crsq_last_read = (bank_rsp_sel_n == core_req_read_mask); always @(posedge clk) begin if (reset) begin - bank_rsp_sel_prv <= 0; + bank_rsp_sel_r <= 0; end else begin if (crsq_in_fire) begin - if (bank_rsp_sel_n == per_bank_req_reads) begin - bank_rsp_sel_prv <= 0; + if (crsq_last_read) begin + bank_rsp_sel_r <= 0; end else begin - bank_rsp_sel_prv <= bank_rsp_sel_n; + bank_rsp_sel_r <= bank_rsp_sel_n; end end end - end - - reg [NUM_REQS-1:0] core_rsp_valids_in; - reg [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data_in; - reg [CORE_TAG_WIDTH-1:0] core_rsp_tag_in; - - always @(*) begin + end + + VX_find_first #( + .N (NUM_BANKS), + .DATAW (CORE_TAG_WIDTH) + ) find_first ( + .valid_i (core_req_read_mask & ~bank_rsp_sel_r), + .data_i (per_bank_core_req_tag), + .data_o (core_rsp_tag_in), + `UNUSED_PIN (valid_o) + ); + + always @(*) begin core_rsp_valids_in = 0; core_rsp_data_in = 'x; - core_rsp_tag_in = 'x; - bank_rsp_sel_cur = 0; - - for (integer i = NUM_BANKS-1; i >= 0; --i) begin - if (per_bank_req_reads[i] && ~bank_rsp_sel_prv[i]) begin - core_rsp_tag_in = per_bank_core_req_tag[i]; - end - end - + bank_rsp_sel_n = bank_rsp_sel_r; for (integer i = 0; i < NUM_BANKS; i++) begin if (per_bank_core_req_valid[i] && (core_rsp_tag_in[CORE_TAG_ID_BITS-1:0] == per_bank_core_req_tag[i][CORE_TAG_ID_BITS-1:0])) begin core_rsp_valids_in[per_bank_core_req_tid[i]] = 1; core_rsp_data_in[per_bank_core_req_tid[i]] = per_bank_core_rsp_data[i]; - bank_rsp_sel_cur[i] = 1; + bank_rsp_sel_n[i] = 1; end end end - assign crsq_in_valid = creq_out_valid && per_bank_req_has_reads; + assign crsq_in_valid = creq_out_valid && ~core_req_writeonly; VX_elastic_buffer #( .DATAW (NUM_BANKS * (1 + `WORD_WIDTH) + CORE_TAG_WIDTH), @@ -257,10 +255,10 @@ module VX_shared_mem #( ); `ifdef DBG_CACHE_REQ_INFO -`IGNORE_WARNINGS_BEGIN +`IGNORE_UNUSED_BEGIN wire [NUM_BANKS-1:0][31:0] debug_pc_st0, debug_pc_st1; wire [NUM_BANKS-1:0][`NW_BITS-1:0] debug_wid_st0, debug_wid_st1; -`IGNORE_WARNINGS_END +`IGNORE_UNUSED_END for (genvar i = 0; i < NUM_BANKS; ++i) begin if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin @@ -276,17 +274,21 @@ module VX_shared_mem #( `ifdef DBG_PRINT_CACHE_BANK reg is_multi_tag_req; -`IGNORE_WARNINGS_BEGIN +`IGNORE_UNUSED_BEGIN reg [CORE_TAG_WIDTH-1:0] core_req_tag_sel; -`IGNORE_WARNINGS_END +`IGNORE_UNUSED_END - always @(*) begin - core_req_tag_sel ='x; - for (integer i = NUM_BANKS-1; i >= 0; --i) begin - if (per_bank_core_req_valid[i]) begin - core_req_tag_sel = per_bank_core_req_tag[i]; - end - end + VX_find_first #( + .N (NUM_BANKS), + .DATAW (CORE_TAG_WIDTH) + ) find_first_d ( + .valid_i (per_bank_core_req_valid), + .data_i (per_bank_core_req_tag), + .data_o (core_req_tag_sel), + `UNUSED_PIN (valid_o) + ); + + always @(*) begin is_multi_tag_req = 0; for (integer i = 0; i < NUM_BANKS; ++i) begin if (per_bank_core_req_valid[i] @@ -298,22 +300,20 @@ module VX_shared_mem #( always @(posedge clk) begin if (!crsq_in_ready) begin - $display("%t: *** cache%0d pipeline-stall", $time, CACHE_ID); + dpi_trace("%d: *** cache%0d pipeline-stall\n", $time, CACHE_ID); end if (is_multi_tag_req) begin - $display("%t: *** cache%0d multi-tag request!", $time, CACHE_ID); + dpi_trace("%d: *** cache%0d multi-tag request!\n", $time, CACHE_ID); end if (creq_in_fire) begin for (integer i = 0; i < NUM_BANKS; ++i) begin if (per_bank_core_req_valid_unqual[i]) begin if (per_bank_core_req_rw_unqual[i]) begin - $display("%t: cache%0d:%0d core-wr-req: addr=%0h, tag=%0h, byteen=%b, data=%0h, wid=%0d, PC=%0h", - $time, CACHE_ID, i, per_bank_core_req_addr_unqual[i], per_bank_core_req_tag_unqual[i], per_bank_core_req_byteen_unqual[i], per_bank_core_req_data_unqual[i], - debug_wid_st0[i], debug_pc_st0[i]); + dpi_trace("%d: cache%0d:%0d core-wr-req: addr=%0h, tag=%0h, byteen=%b, data=%0h, wid=%0d, PC=%0h\n", + $time, CACHE_ID, i, `LINE_TO_BYTE_ADDR(per_bank_core_req_addr_unqual[i], i), per_bank_core_req_tag_unqual[i], per_bank_core_req_byteen_unqual[i], per_bank_core_req_data_unqual[i], debug_wid_st0[i], debug_pc_st0[i]); end else begin - $display("%t: cache%0d:%0d core-rd-req: addr=%0h, tag=%0h, byteen=%b, wid=%0d, PC=%0h", - $time, CACHE_ID, i, per_bank_core_req_addr_unqual[i], per_bank_core_req_tag_unqual[i], per_bank_core_req_byteen_unqual[i], - debug_wid_st0[i], debug_pc_st0[i]); + dpi_trace("%d: cache%0d:%0d core-rd-req: addr=%0h, tag=%0h, byteen=%b, wid=%0d, PC=%0h\n", + $time, CACHE_ID, i, `LINE_TO_BYTE_ADDR(per_bank_core_req_addr_unqual[i], i), per_bank_core_req_tag_unqual[i], per_bank_core_req_byteen_unqual[i], debug_wid_st0[i], debug_pc_st0[i]); end end end @@ -322,13 +322,11 @@ module VX_shared_mem #( for (integer i = 0; i < NUM_BANKS; ++i) begin if (per_bank_core_req_valid[i]) begin if (per_bank_core_req_rw[i]) begin - $display("%t: cache%0d:%0d core-wr-rsp: addr=%0h, tag=%0h, byteen=%b, data=%0h, wid=%0d, PC=%0h", - $time, CACHE_ID, i, per_bank_core_req_addr[i], per_bank_core_req_tag[i], per_bank_core_req_byteen[i], per_bank_core_req_data[i], - debug_wid_st1[i], debug_pc_st1[i]); + dpi_trace("%d: cache%0d:%0d core-wr-rsp: addr=%0h, tag=%0h, byteen=%b, data=%0h, wid=%0d, PC=%0h\n", + $time, CACHE_ID, i, `LINE_TO_BYTE_ADDR(per_bank_core_req_addr[i], i), per_bank_core_req_tag[i], per_bank_core_req_byteen[i], per_bank_core_req_data[i], debug_wid_st1[i], debug_pc_st1[i]); end else begin - $display("%t: cache%0d:%0d core-rd-rsp: addr=%0h, tag=%0h, byteen=%b, data=%0h, wid=%0d, PC=%0h", - $time, CACHE_ID, i, per_bank_core_req_addr[i], per_bank_core_req_tag[i], per_bank_core_req_byteen[i], per_bank_core_rsp_data[i], - debug_wid_st1[i], debug_pc_st1[i]); + dpi_trace("%d: cache%0d:%0d core-rd-rsp: addr=%0h, tag=%0h, byteen=%b, data=%0h, wid=%0d, PC=%0h\n", + $time, CACHE_ID, i, `LINE_TO_BYTE_ADDR(per_bank_core_req_addr[i], i), per_bank_core_req_tag[i], per_bank_core_req_byteen[i], per_bank_core_rsp_data[i], debug_wid_st1[i], debug_pc_st1[i]); end end end @@ -338,16 +336,22 @@ module VX_shared_mem #( `ifdef PERF_ENABLE // per cycle: core_reads, core_writes - reg [($clog2(NUM_REQS+1)-1):0] perf_core_reads_per_cycle, perf_core_writes_per_cycle; - reg [($clog2(NUM_REQS+1)-1):0] perf_crsp_stall_per_cycle; + wire [$clog2(NUM_REQS+1)-1:0] perf_core_reads_per_cycle; + wire [$clog2(NUM_REQS+1)-1:0] perf_core_writes_per_cycle; + wire [$clog2(NUM_REQS+1)-1:0] perf_crsp_stall_per_cycle; - assign perf_core_reads_per_cycle = $countones(core_req_valid & core_req_ready & ~core_req_rw); - assign perf_core_writes_per_cycle = $countones(core_req_valid & core_req_ready & core_req_rw); + wire [NUM_REQS-1:0] perf_core_reads_per_mask = core_req_valid & core_req_ready & ~core_req_rw; + wire [NUM_REQS-1:0] perf_core_writes_per_mask = core_req_valid & core_req_ready & core_req_rw; + + `POP_COUNT(perf_core_reads_per_cycle, perf_core_reads_per_mask); + `POP_COUNT(perf_core_writes_per_cycle, perf_core_writes_per_mask); if (CORE_TAG_ID_BITS != 0) begin - assign perf_crsp_stall_per_cycle = $countones(core_rsp_tmask & {NUM_REQS{core_rsp_valid && ~core_rsp_ready}}); + wire [NUM_REQS-1:0] perf_crsp_stall_per_mask = core_rsp_tmask & {NUM_REQS{core_rsp_valid && ~core_rsp_ready}}; + `POP_COUNT(perf_crsp_stall_per_cycle, perf_crsp_stall_per_mask); end else begin - assign perf_crsp_stall_per_cycle = $countones(core_rsp_valid & ~core_rsp_ready); + wire [NUM_REQS-1:0] perf_crsp_stall_per_mask = core_rsp_valid & ~core_rsp_ready; + `POP_COUNT(perf_crsp_stall_per_cycle, perf_crsp_stall_per_mask); end reg [`PERF_CTR_BITS-1:0] perf_core_reads; diff --git a/hw/rtl/cache/VX_tag_access.sv b/hw/rtl/cache/VX_tag_access.sv new file mode 100644 index 00000000..e3433528 --- /dev/null +++ b/hw/rtl/cache/VX_tag_access.sv @@ -0,0 +1,82 @@ +`include "VX_cache_define.vh" + +module VX_tag_access #( + parameter CACHE_ID = 0, + parameter BANK_ID = 0, + // Size of cache in bytes + parameter CACHE_SIZE = 1, + // Size of line inside a bank in bytes + parameter CACHE_LINE_SIZE = 1, + // Number of banks + parameter NUM_BANKS = 1, + // Size of a word in bytes + parameter WORD_SIZE = 1, + // bank offset from beginning of index range + parameter BANK_ADDR_OFFSET = 0 +) ( + input wire clk, + input wire reset, + +`ifdef DBG_CACHE_REQ_INFO +`IGNORE_UNUSED_BEGIN + input wire[31:0] debug_pc, + input wire[`NW_BITS-1:0] debug_wid, +`IGNORE_UNUSED_END +`endif + + input wire stall, + + // read/fill + input wire lookup, + input wire[`LINE_ADDR_WIDTH-1:0] addr, + input wire fill, + input wire flush, + output wire tag_match +); + + `UNUSED_PARAM (CACHE_ID) + `UNUSED_PARAM (BANK_ID) + `UNUSED_VAR (reset) + `UNUSED_VAR (lookup) + + wire [`TAG_SELECT_BITS-1:0] read_tag; + wire read_valid; + + wire [`LINE_SELECT_BITS-1:0] line_addr = addr[`LINE_SELECT_BITS-1:0]; + wire [`TAG_SELECT_BITS-1:0] line_tag = `LINE_TAG_ADDR(addr); + + VX_sp_ram #( + .DATAW (`TAG_SELECT_BITS + 1), + .SIZE (`LINES_PER_BANK), + .NO_RWCHECK (1) + ) tag_store ( + .clk( clk), + .addr (line_addr), + .wren (fill || flush), + .wdata ({!flush, line_tag}), + .rdata ({read_valid, read_tag}) + ); + + assign tag_match = read_valid && (line_tag == read_tag); + + `UNUSED_VAR (stall) + +`ifdef DBG_PRINT_CACHE_TAG + always @(posedge clk) begin + if (fill && ~stall) begin + dpi_trace("%d: cache%0d:%0d tag-fill: addr=%0h, blk_addr=%0d, tag_id=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr, line_tag); + end + if (flush) begin + dpi_trace("%d: cache%0d:%0d tag-flush: addr=%0h, blk_addr=%0d\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr); + end + if (lookup && ~stall) begin + if (tag_match) begin + dpi_trace("%d: cache%0d:%0d tag-hit: addr=%0h, wid=%0d, PC=%0h, blk_addr=%0d, tag_id=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, line_addr, line_tag); + end else begin + dpi_trace("%d: cache%0d:%0d tag-miss: addr=%0h, wid=%0d, PC=%0h, blk_addr=%0d, tag_id=%0h, old_tag_id=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, line_addr, line_tag, read_tag); + end + end + end +`endif + +endmodule \ No newline at end of file diff --git a/hw/rtl/cache/VX_tag_access.v b/hw/rtl/cache/VX_tag_access.v deleted file mode 100644 index ef2c6347..00000000 --- a/hw/rtl/cache/VX_tag_access.v +++ /dev/null @@ -1,84 +0,0 @@ -`include "VX_cache_define.vh" - -module VX_tag_access #( - parameter CACHE_ID = 0, - parameter BANK_ID = 0, - // Size of cache in bytes - parameter CACHE_SIZE = 1, - // Size of line inside a bank in bytes - parameter CACHE_LINE_SIZE = 1, - // Number of banks - parameter NUM_BANKS = 1, - // Size of a word in bytes - parameter WORD_SIZE = 1, - // bank offset from beginning of index range - parameter BANK_ADDR_OFFSET = 0 -) ( - input wire clk, - input wire reset, - -`ifdef DBG_CACHE_REQ_INFO -`IGNORE_WARNINGS_BEGIN - input wire[31:0] debug_pc, - input wire[`NW_BITS-1:0] debug_wid, -`IGNORE_WARNINGS_END -`endif - - // read/fill - input wire lookup, - input wire[`LINE_ADDR_WIDTH-1:0] addr, - input wire fill, - input wire is_flush, - output wire tag_match -); - - `UNUSED_PARAM (CACHE_ID) - `UNUSED_PARAM (BANK_ID) - `UNUSED_VAR (reset) - `UNUSED_VAR (lookup) - - wire read_valid; - wire [`TAG_SELECT_BITS-1:0] read_tag; - - wire [`TAG_SELECT_BITS-1:0] line_tag = `LINE_TAG_ADDR(addr); - wire [`LINE_SELECT_BITS-1:0] line_addr = addr [`LINE_SELECT_BITS-1:0]; - - VX_sp_ram #( - .DATAW(`TAG_SELECT_BITS + 1), - .SIZE(`LINES_PER_BANK), - .INITZERO(1), - .RWCHECK(1) - ) tag_store ( - .clk(clk), - .addr(line_addr), - .wren(fill), - .byteen(1'b1), - .rden(1'b1), - .din({!is_flush, line_tag}), - .dout({read_valid, read_tag}) - ); - - assign tag_match = read_valid && (line_tag == read_tag); - -`ifdef DBG_PRINT_CACHE_TAG - always @(posedge clk) begin - if (fill) begin - if (is_flush) begin - $display("%t: cache%0d:%0d tag-flush: addr=%0h, blk_addr=%0d", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr); - end else begin - $display("%t: cache%0d:%0d tag-fill: addr=%0h, blk_addr=%0d, tag_id=%0h, old_tag_id=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr, line_tag, read_tag); - if (tag_match) begin - $display("%t: warning: redundant fill - addr=%0h", $time, `LINE_TO_BYTE_ADDR(addr, BANK_ID)); - end - end - end else if (lookup) begin - if (tag_match) begin - $display("%t: cache%0d:%0d tag-hit: addr=%0h, wid=%0d, PC=%0h, blk_addr=%0d, tag_id=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, line_addr, line_tag); - end else begin - $display("%t: cache%0d:%0d tag-miss: addr=%0h, wid=%0d, PC=%0h, blk_addr=%0d, tag_id=%0h, old_tag_id=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, line_addr, line_tag, read_tag); - end - end - end -`endif - -endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/VX_fp_class.sv b/hw/rtl/fp_cores/VX_fp_class.sv new file mode 100644 index 00000000..a98d51d5 --- /dev/null +++ b/hw/rtl/fp_cores/VX_fp_class.sv @@ -0,0 +1,28 @@ + +`include "VX_fpu_define.vh" + +module VX_fp_class # ( + parameter MAN_BITS = 23, + parameter EXP_BITS = 8 +) ( + input [EXP_BITS-1:0] exp_i, + input [MAN_BITS-1:0] man_i, + output fp_class_t clss_o +); + wire is_normal = (exp_i != '0) && (exp_i != '1); + wire is_zero = (exp_i == '0) && (man_i == '0); + wire is_subnormal = (exp_i == '0) && (man_i != '0); + wire is_inf = (exp_i == '1) && (man_i == '0); + wire is_nan = (exp_i == '1) && (man_i != '0); + wire is_signaling = is_nan && ~man_i[MAN_BITS-1]; + wire is_quiet = is_nan && ~is_signaling; + + assign clss_o.is_normal = is_normal; + assign clss_o.is_zero = is_zero; + assign clss_o.is_subnormal = is_subnormal; + assign clss_o.is_inf = is_inf; + assign clss_o.is_nan = is_nan; + assign clss_o.is_quiet = is_quiet; + assign clss_o.is_signaling = is_signaling; + +endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/VX_fp_cvt.v b/hw/rtl/fp_cores/VX_fp_cvt.sv similarity index 78% rename from hw/rtl/fp_cores/VX_fp_cvt.v rename to hw/rtl/fp_cores/VX_fp_cvt.sv index 1e823363..733713c1 100644 --- a/hw/rtl/fp_cores/VX_fp_cvt.v +++ b/hw/rtl/fp_cores/VX_fp_cvt.sv @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_fpu_define.vh" /// Modified port of cast module from fpnew Libray /// reference: https://github.com/pulp-platform/fpnew @@ -15,7 +15,7 @@ module VX_fp_cvt #( input wire [TAGW-1:0] tag_in, - input wire [`FRM_BITS-1:0] frm, + input wire [`INST_FRM_BITS-1:0] frm, input wire is_itof, input wire is_signed, @@ -59,13 +59,16 @@ module VX_fp_cvt #( // Input processing - fp_type_t [LANES-1:0] in_a_type; + fp_class_t [LANES-1:0] fp_clss; for (genvar i = 0; i < LANES; ++i) begin - VX_fp_type fp_type ( + VX_fp_class #( + .EXP_BITS (EXP_BITS), + .MAN_BITS (MAN_BITS) + ) fp_class ( .exp_i (dataa[i][30:23]), .man_i (dataa[i][22:0]), - .type_o (in_a_type[i]) + .clss_o (fp_clss[i]) ); end @@ -74,16 +77,18 @@ module VX_fp_cvt #( wire [LANES-1:0] input_sign; for (genvar i = 0; i < LANES; ++i) begin + `IGNORE_WARNINGS_BEGIN wire [INT_MAN_WIDTH-1:0] int_mantissa; wire [INT_MAN_WIDTH-1:0] fmt_mantissa; wire fmt_sign = dataa[i][31]; wire int_sign = dataa[i][31] & is_signed; assign int_mantissa = int_sign ? (-dataa[i]) : dataa[i]; - assign fmt_mantissa = INT_MAN_WIDTH'({in_a_type[i].is_normal, dataa[i][MAN_BITS-1:0]}); - - assign fmt_exponent[i] = {1'b0, dataa[i][MAN_BITS+EXP_BITS-1:MAN_BITS]}; + assign fmt_mantissa = INT_MAN_WIDTH'({fp_clss[i].is_normal, dataa[i][MAN_BITS-1:0]}); + assign fmt_exponent[i] = {1'b0, dataa[i][MAN_BITS +: EXP_BITS]} + + {1'b0, fp_clss[i].is_subnormal}; assign encoded_mant[i] = is_itof ? int_mantissa : fmt_mantissa; assign input_sign[i] = is_itof ? int_sign : fmt_sign; + `IGNORE_WARNINGS_END end // Pipeline stage0 @@ -93,7 +98,7 @@ module VX_fp_cvt #( wire is_itof_s0; wire unsigned_s0; wire [2:0] rnd_mode_s0; - fp_type_t [LANES-1:0] in_a_type_s0; + fp_class_t [LANES-1:0] fp_clss_s0; wire [LANES-1:0] input_sign_s0; wire [LANES-1:0][INT_EXP_WIDTH-1:0] fmt_exponent_s0; wire [LANES-1:0][INT_MAN_WIDTH-1:0] encoded_mant_s0; @@ -101,14 +106,14 @@ module VX_fp_cvt #( wire stall; VX_pipe_register #( - .DATAW (1 + TAGW + 1 + `FRM_BITS + 1 + LANES * ($bits(fp_type_t) + 1 + INT_EXP_WIDTH + INT_MAN_WIDTH)), + .DATAW (1 + TAGW + 1 + `INST_FRM_BITS + 1 + LANES * ($bits(fp_class_t) + 1 + INT_EXP_WIDTH + INT_MAN_WIDTH)), .RESETW (1) ) pipe_reg0 ( .clk (clk), .reset (reset), .enable (~stall), - .data_in ({valid_in, tag_in, is_itof, !is_signed, frm, in_a_type, input_sign, fmt_exponent, encoded_mant}), - .data_out ({valid_in_s0, tag_in_s0, is_itof_s0, unsigned_s0, rnd_mode_s0, in_a_type_s0, input_sign_s0, fmt_exponent_s0, encoded_mant_s0}) + .data_in ({valid_in, tag_in, is_itof, !is_signed, frm, fp_clss, input_sign, fmt_exponent, encoded_mant}), + .data_out ({valid_in_s0, tag_in_s0, is_itof_s0, unsigned_s0, rnd_mode_s0, fp_clss_s0, input_sign_s0, fmt_exponent_s0, encoded_mant_s0}) ); // Normalization @@ -119,8 +124,8 @@ module VX_fp_cvt #( for (genvar i = 0; i < LANES; ++i) begin wire mant_is_nonzero; VX_lzc #( - .WIDTH (INT_MAN_WIDTH), - .MODE (1) + .N (INT_MAN_WIDTH), + .MODE (1) ) lzc ( .in_i (encoded_mant_s0[i]), .cnt_o (renorm_shamt_s0[i]), @@ -134,20 +139,12 @@ module VX_fp_cvt #( for (genvar i = 0; i < LANES; ++i) begin `IGNORE_WARNINGS_BEGIN - // Input mantissa needs to be normalized - wire [INT_EXP_WIDTH-1:0] fp_input_exp; - wire [INT_EXP_WIDTH-1:0] int_input_exp; - - // Realign input mantissa, append zeroes if destination is wider + // Realign input mantissa, append zeroes if destination is wider assign input_mant_s0[i] = encoded_mant_s0[i] << renorm_shamt_s0[i]; // Unbias exponent and compensate for shift - assign fp_input_exp = fmt_exponent_s0[i] + - {1'b0, in_a_type_s0[i].is_subnormal} + - (FMT_SHIFT_COMPENSATION - EXP_BIAS) - - {1'b0, renorm_shamt_s0[i]}; - - assign int_input_exp = (INT_MAN_WIDTH-1) - {1'b0, renorm_shamt_s0[i]}; + wire [INT_EXP_WIDTH-1:0] fp_input_exp = fmt_exponent_s0[i] + (FMT_SHIFT_COMPENSATION - EXP_BIAS) - {1'b0, renorm_shamt_s0[i]}; + wire [INT_EXP_WIDTH-1:0] int_input_exp = (INT_MAN_WIDTH-1) - {1'b0, renorm_shamt_s0[i]}; assign input_exp_s0[i] = is_itof_s0 ? int_input_exp : fp_input_exp; `IGNORE_WARNINGS_END @@ -160,21 +157,21 @@ module VX_fp_cvt #( wire is_itof_s1; wire unsigned_s1; wire [2:0] rnd_mode_s1; - fp_type_t [LANES-1:0] in_a_type_s1; + fp_class_t [LANES-1:0] fp_clss_s1; wire [LANES-1:0] input_sign_s1; wire [LANES-1:0] mant_is_zero_s1; wire [LANES-1:0][INT_MAN_WIDTH-1:0] input_mant_s1; wire [LANES-1:0][INT_EXP_WIDTH-1:0] input_exp_s1; VX_pipe_register #( - .DATAW (1 + TAGW + 1 + `FRM_BITS + 1 + LANES * ($bits(fp_type_t) + 1 + 1 + INT_MAN_WIDTH + INT_EXP_WIDTH)), + .DATAW (1 + TAGW + 1 + `INST_FRM_BITS + 1 + LANES * ($bits(fp_class_t) + 1 + 1 + INT_MAN_WIDTH + INT_EXP_WIDTH)), .RESETW (1) ) pipe_reg1 ( .clk (clk), .reset (reset), .enable (~stall), - .data_in ({valid_in_s0, tag_in_s0, is_itof_s0, unsigned_s0, rnd_mode_s0, in_a_type_s0, input_sign_s0, mant_is_zero_s0, input_mant_s0, input_exp_s0}), - .data_out ({valid_in_s1, tag_in_s1, is_itof_s1, unsigned_s1, rnd_mode_s1, in_a_type_s1, input_sign_s1, mant_is_zero_s1, input_mant_s1, input_exp_s1}) + .data_in ({valid_in_s0, tag_in_s0, is_itof_s0, unsigned_s0, rnd_mode_s0, fp_clss_s0, input_sign_s0, mant_is_zero_s0, input_mant_s0, input_exp_s0}), + .data_out ({valid_in_s1, tag_in_s1, is_itof_s1, unsigned_s1, rnd_mode_s1, fp_clss_s1, input_sign_s1, mant_is_zero_s1, input_mant_s1, input_exp_s1}) ); // Perform adjustments to mantissa and exponent @@ -183,39 +180,35 @@ module VX_fp_cvt #( wire [LANES-1:0][INT_EXP_WIDTH-1:0] final_exp_s1; wire [LANES-1:0] of_before_round_s1; - for (genvar i = 0; i < LANES; ++i) begin - wire [INT_EXP_WIDTH-1:0] destination_exp; // re-biased exponent for destination + for (genvar i = 0; i < LANES; ++i) begin reg [2*INT_MAN_WIDTH:0] preshift_mant; // mantissa before final shift reg [SHAMT_BITS-1:0] denorm_shamt; // shift amount for denormalization reg [INT_EXP_WIDTH-1:0] final_exp; // after eventual adjustments reg of_before_round; - // Rebias the exponent - assign destination_exp = input_exp_s1[i] + EXP_BIAS; - always @(*) begin `IGNORE_WARNINGS_BEGIN // Default assignment - final_exp = destination_exp; // take exponent as is, only look at lower bits - preshift_mant = {input_mant_s1[i], 33'b0}; // Place mantissa to the left of the shifter + final_exp = input_exp_s1[i] + EXP_BIAS; // take exponent as is, only look at lower bits + preshift_mant = {input_mant_s1[i], 33'b0}; // Place mantissa to the left of the shifter denorm_shamt = 0; // right of mantissa of_before_round = 1'b0; // Handle INT casts if (is_itof_s1) begin - if ($signed(destination_exp) >= $signed(2**EXP_BITS-1)) begin + if ($signed(input_exp_s1[i]) >= $signed(2**EXP_BITS-1-EXP_BIAS)) begin // Overflow or infinities (for proper rounding) final_exp = (2**EXP_BITS-2); // largest normal value preshift_mant = ~0; // largest normal value and RS bits set of_before_round = 1'b1; - end else if ($signed(destination_exp) < $signed(-MAN_BITS)) begin + end else if ($signed(input_exp_s1[i]) < $signed(-MAN_BITS-EXP_BIAS)) begin // Limit the shift to retain sticky bits final_exp = 0; // denormal result - denorm_shamt = denorm_shamt + (2 + MAN_BITS); // to sticky - end else if ($signed(destination_exp) < $signed(1)) begin + denorm_shamt = (2 + MAN_BITS); // to sticky + end else if ($signed(input_exp_s1[i]) < $signed(1-EXP_BIAS)) begin // Denormalize underflowing values final_exp = 0; // denormal result - denorm_shamt = denorm_shamt + 1 - destination_exp; // adjust right shifting + denorm_shamt = (1-EXP_BIAS) - input_exp_s1[i]; // adjust right shifting end end else begin if ($signed(input_exp_s1[i]) >= $signed((MAX_INT_WIDTH-1) + unsigned_s1)) begin @@ -224,7 +217,7 @@ module VX_fp_cvt #( of_before_round = 1'b1; end else if ($signed(input_exp_s1[i]) < $signed(-1)) begin // underflow - denorm_shamt = MAX_INT_WIDTH + 1; // all bits go to the sticky + denorm_shamt = MAX_INT_WIDTH+1; // all bits go to the sticky end else begin // By default right shift mantissa to be an integer denorm_shamt = (MAX_INT_WIDTH-1) - input_exp_s1[i]; @@ -245,7 +238,7 @@ module VX_fp_cvt #( wire is_itof_s2; wire unsigned_s2; wire [2:0] rnd_mode_s2; - fp_type_t [LANES-1:0] in_a_type_s2; + fp_class_t [LANES-1:0] fp_clss_s2; wire [LANES-1:0] mant_is_zero_s2; wire [LANES-1:0] input_sign_s2; wire [LANES-1:0][2*INT_MAN_WIDTH:0] destination_mant_s2; @@ -253,14 +246,14 @@ module VX_fp_cvt #( wire [LANES-1:0] of_before_round_s2; VX_pipe_register #( - .DATAW (1 + TAGW + 1 + 1 + `FRM_BITS + LANES * ($bits(fp_type_t) + 1 + 1 + (2*INT_MAN_WIDTH+1) + INT_EXP_WIDTH + 1)), + .DATAW (1 + TAGW + 1 + 1 + `INST_FRM_BITS + LANES * ($bits(fp_class_t) + 1 + 1 + (2*INT_MAN_WIDTH+1) + INT_EXP_WIDTH + 1)), .RESETW (1) ) pipe_reg2 ( .clk (clk), .reset (reset), .enable (~stall), - .data_in ({valid_in_s1, tag_in_s1, is_itof_s1, unsigned_s1, rnd_mode_s1, in_a_type_s1, mant_is_zero_s1, input_sign_s1, destination_mant_s1, final_exp_s1, of_before_round_s1}), - .data_out ({valid_in_s2, tag_in_s2, is_itof_s2, unsigned_s2, rnd_mode_s2, in_a_type_s2, mant_is_zero_s2, input_sign_s2, destination_mant_s2, final_exp_s2, of_before_round_s2}) + .data_in ({valid_in_s1, tag_in_s1, is_itof_s1, unsigned_s1, rnd_mode_s1, fp_clss_s1, mant_is_zero_s1, input_sign_s1, destination_mant_s1, final_exp_s1, of_before_round_s1}), + .data_out ({valid_in_s2, tag_in_s2, is_itof_s2, unsigned_s2, rnd_mode_s2, fp_clss_s2, mant_is_zero_s2, input_sign_s2, destination_mant_s2, final_exp_s2, of_before_round_s2}) ); wire [LANES-1:0] rounded_sign; @@ -314,7 +307,7 @@ module VX_fp_cvt #( wire [TAGW-1:0] tag_in_s3; wire is_itof_s3; wire unsigned_s3; - fp_type_t [LANES-1:0] in_a_type_s3; + fp_class_t [LANES-1:0] fp_clss_s3; wire [LANES-1:0] mant_is_zero_s3; wire [LANES-1:0] input_sign_s3; wire [LANES-1:0] rounded_sign_s3; @@ -322,14 +315,14 @@ module VX_fp_cvt #( wire [LANES-1:0] of_before_round_s3; VX_pipe_register #( - .DATAW (1 + TAGW + 1 + 1 + LANES * ($bits(fp_type_t) + 1 + 1 + 32 + 1 + 1)), + .DATAW (1 + TAGW + 1 + 1 + LANES * ($bits(fp_class_t) + 1 + 1 + 32 + 1 + 1)), .RESETW (1) ) pipe_reg3 ( .clk (clk), .reset (reset), .enable (~stall), - .data_in ({valid_in_s2, tag_in_s2, is_itof_s2, unsigned_s2, in_a_type_s2, mant_is_zero_s2, input_sign_s2, rounded_abs, rounded_sign, of_before_round_s2}), - .data_out ({valid_in_s3, tag_in_s3, is_itof_s3, unsigned_s3, in_a_type_s3, mant_is_zero_s3, input_sign_s3, rounded_abs_s3, rounded_sign_s3, of_before_round_s3}) + .data_in ({valid_in_s2, tag_in_s2, is_itof_s2, unsigned_s2, fp_clss_s2, mant_is_zero_s2, input_sign_s2, rounded_abs, rounded_sign, of_before_round_s2}), + .data_out ({valid_in_s3, tag_in_s3, is_itof_s3, unsigned_s3, fp_clss_s3, mant_is_zero_s3, input_sign_s3, rounded_abs_s3, rounded_sign_s3, of_before_round_s3}) ); wire [LANES-1:0] of_after_round; @@ -362,14 +355,14 @@ module VX_fp_cvt #( for (genvar i = 0; i < LANES; ++i) begin // Detect special case from source format, I2F casts don't produce a special result - assign fp_result_is_special[i] = ~is_itof_s3 & (in_a_type_s3[i].is_zero | in_a_type_s3[i].is_nan); + assign fp_result_is_special[i] = ~is_itof_s3 & (fp_clss_s3[i].is_zero | fp_clss_s3[i].is_nan); // Signalling input NaNs raise invalid flag, otherwise no flags set - assign fp_special_status[i] = in_a_type_s3[i].is_signaling ? {1'b1, 4'h0} : 5'h0; // invalid operation + assign fp_special_status[i] = fp_clss_s3[i].is_signaling ? {1'b1, 4'h0} : 5'h0; // invalid operation // Assemble result according to destination format - assign fp_special_result[i] = in_a_type_s3[i].is_zero ? (32'(input_sign_s3) << 31) // signed zero - : {1'b0, QNAN_EXPONENT, QNAN_MANTISSA}; // qNaN + assign fp_special_result[i] = fp_clss_s3[i].is_zero ? (32'(input_sign_s3) << 31) // signed zero + : {1'b0, QNAN_EXPONENT, QNAN_MANTISSA}; // qNaN end // INT Special case handling @@ -381,7 +374,7 @@ module VX_fp_cvt #( for (genvar i = 0; i < LANES; ++i) begin // Assemble result according to destination format always @(*) begin - if (input_sign_s3[i] && !in_a_type_s3[i].is_nan) begin + if (input_sign_s3[i] && !fp_clss_s3[i].is_nan) begin int_special_result[i][30:0] = 0; // alone yields 2**(31)-1 int_special_result[i][31] = ~unsigned_s3; // for unsigned casts yields 2**31 end else begin @@ -391,8 +384,8 @@ module VX_fp_cvt #( end // Detect special case from source format (inf, nan, overflow, nan-boxing or negative unsigned) - assign int_result_is_special[i] = in_a_type_s3[i].is_nan - | in_a_type_s3[i].is_inf + assign int_result_is_special[i] = fp_clss_s3[i].is_nan + | fp_clss_s3[i].is_inf | of_before_round_s3[i] | (input_sign_s3[i] & unsigned_s3 & ~rounded_int_res_zero[i]); @@ -411,11 +404,11 @@ module VX_fp_cvt #( wire [31:0] fp_result, int_result; wire inexact = is_itof_s3 ? (| fp_round_sticky_bits[i]) // overflow is invalid in i2f; - : (| fp_round_sticky_bits[i]) | (~in_a_type_s3[i].is_inf & (of_before_round_s3[i] | of_after_round[i])); + : (| fp_round_sticky_bits[i]) | (~fp_clss_s3[i].is_inf & (of_before_round_s3[i] | of_after_round[i])); assign fp_regular_status.NV = is_itof_s3 & (of_before_round_s3[i] | of_after_round[i]); // overflow is invalid for I2F casts assign fp_regular_status.DZ = 1'b0; // no divisions - assign fp_regular_status.OF = ~is_itof_s3 & (~in_a_type_s3[i].is_inf & (of_before_round_s3[i] | of_after_round[i])); // inf casts no OF + assign fp_regular_status.OF = ~is_itof_s3 & (~fp_clss_s3[i].is_inf & (of_before_round_s3[i] | of_after_round[i])); // inf casts no OF assign fp_regular_status.UF = uf_after_round[i] & inexact; assign fp_regular_status.NX = inexact; @@ -435,7 +428,7 @@ module VX_fp_cvt #( assign stall = ~ready_out && valid_out; VX_pipe_register #( - .DATAW (1 + TAGW + (LANES * 32) + (LANES * `FFG_BITS)), + .DATAW (1 + TAGW + (LANES * 32) + (LANES * `FFLAGS_BITS)), .RESETW (1) ) pipe_reg4 ( .clk (clk), diff --git a/hw/rtl/fp_cores/VX_fp_div.v b/hw/rtl/fp_cores/VX_fp_div.sv similarity index 91% rename from hw/rtl/fp_cores/VX_fp_div.v rename to hw/rtl/fp_cores/VX_fp_div.sv index 8dd110d3..48e9d9b8 100644 --- a/hw/rtl/fp_cores/VX_fp_div.v +++ b/hw/rtl/fp_cores/VX_fp_div.sv @@ -1,8 +1,4 @@ -`include "VX_define.vh" - -`ifndef SYNTHESIS -`include "float_dpi.vh" -`endif +`include "VX_fpu_define.vh" module VX_fp_div #( parameter TAGW = 1, @@ -16,7 +12,7 @@ module VX_fp_div #( input wire [TAGW-1:0] tag_in, - input wire [`FRM_BITS-1:0] frm, + input wire [`INST_FRM_BITS-1:0] frm, input wire [LANES-1:0][31:0] dataa, input wire [LANES-1:0][31:0] datab, @@ -39,7 +35,7 @@ module VX_fp_div #( fflags_t f; always @(*) begin - dpi_fdiv (dataa[i], datab[i], frm, r, f); + dpi_fdiv (enable && valid_in, dataa[i], datab[i], frm, r, f); end `UNUSED_VAR (f) diff --git a/hw/rtl/fp_cores/VX_fp_fma.v b/hw/rtl/fp_cores/VX_fp_fma.sv similarity index 94% rename from hw/rtl/fp_cores/VX_fp_fma.v rename to hw/rtl/fp_cores/VX_fp_fma.sv index faf26e87..8f826b5f 100644 --- a/hw/rtl/fp_cores/VX_fp_fma.v +++ b/hw/rtl/fp_cores/VX_fp_fma.sv @@ -1,8 +1,4 @@ -`include "VX_define.vh" - -`ifndef SYNTHESIS -`include "float_dpi.vh" -`endif +`include "VX_fpu_define.vh" module VX_fp_fma #( parameter TAGW = 1, @@ -16,7 +12,7 @@ module VX_fp_fma #( input wire [TAGW-1:0] tag_in, - input wire [`FRM_BITS-1:0] frm, + input wire [`INST_FRM_BITS-1:0] frm, input wire do_madd, input wire do_sub, @@ -68,7 +64,7 @@ module VX_fp_fma #( fflags_t f; always @(*) begin - dpi_fmadd (a, b, c, frm, r, f); + dpi_fmadd (enable && valid_in, a, b, c, frm, r, f); end `UNUSED_VAR (f) diff --git a/hw/rtl/fp_cores/VX_fp_ncomp.v b/hw/rtl/fp_cores/VX_fp_ncomp.sv similarity index 65% rename from hw/rtl/fp_cores/VX_fp_ncomp.v rename to hw/rtl/fp_cores/VX_fp_ncomp.sv index b2dac840..17d42102 100644 --- a/hw/rtl/fp_cores/VX_fp_ncomp.v +++ b/hw/rtl/fp_cores/VX_fp_ncomp.sv @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_fpu_define.vh" /// Modified port of noncomp module from fpnew Libray /// reference: https://github.com/pulp-platform/fpnew @@ -15,8 +15,8 @@ module VX_fp_ncomp #( input wire [TAGW-1:0] tag_in, - input wire [`FPU_BITS-1:0] op_type, - input wire [`FRM_BITS-1:0] frm, + input wire [`INST_FPU_BITS-1:0] op_type, + input wire [`INST_FRM_BITS-1:0] frm, input wire [LANES-1:0][31:0] dataa, input wire [LANES-1:0][31:0] datab, @@ -30,6 +30,9 @@ module VX_fp_ncomp #( input wire ready_out, output wire valid_out ); + localparam EXP_BITS = 8; + localparam MAN_BITS = 23; + localparam NEG_INF = 32'h00000001, NEG_NORM = 32'h00000002, NEG_SUBNORM = 32'h00000004, @@ -38,86 +41,92 @@ module VX_fp_ncomp #( POS_SUBNORM = 32'h00000020, POS_NORM = 32'h00000040, POS_INF = 32'h00000080, - SIG_NAN = 32'h00000100, + //SIG_NAN = 32'h00000100, QUT_NAN = 32'h00000200; - wire [LANES-1:0] tmp_a_sign, tmp_b_sign; - wire [LANES-1:0][7:0] tmp_a_exponent, tmp_b_exponent; - wire [LANES-1:0][22:0] tmp_a_mantissa, tmp_b_mantissa; - fp_type_t [LANES-1:0] tmp_a_type, tmp_b_type; - wire [LANES-1:0] tmp_a_smaller, tmp_ab_equal; + wire [LANES-1:0] a_sign, b_sign; + wire [LANES-1:0][7:0] a_exponent, b_exponent; + wire [LANES-1:0][22:0] a_mantissa, b_mantissa; + fp_class_t [LANES-1:0] a_clss, b_clss; + wire [LANES-1:0] a_smaller, ab_equal; // Setup for (genvar i = 0; i < LANES; i++) begin - assign tmp_a_sign[i] = dataa[i][31]; - assign tmp_a_exponent[i] = dataa[i][30:23]; - assign tmp_a_mantissa[i] = dataa[i][22:0]; + assign a_sign[i] = dataa[i][31]; + assign a_exponent[i] = dataa[i][30:23]; + assign a_mantissa[i] = dataa[i][22:0]; - assign tmp_b_sign[i] = datab[i][31]; - assign tmp_b_exponent[i] = datab[i][30:23]; - assign tmp_b_mantissa[i] = datab[i][22:0]; + assign b_sign[i] = datab[i][31]; + assign b_exponent[i] = datab[i][30:23]; + assign b_mantissa[i] = datab[i][22:0]; - VX_fp_type fp_type_a ( - .exp_i (tmp_a_exponent[i]), - .man_i (tmp_a_mantissa[i]), - .type_o (tmp_a_type[i]) + VX_fp_class #( + .EXP_BITS (EXP_BITS), + .MAN_BITS (MAN_BITS) + ) fp_class_a ( + .exp_i (a_exponent[i]), + .man_i (a_mantissa[i]), + .clss_o (a_clss[i]) ); - VX_fp_type fp_type_b ( - .exp_i (tmp_b_exponent[i]), - .man_i (tmp_b_mantissa[i]), - .type_o (tmp_b_type[i]) + VX_fp_class #( + .EXP_BITS (EXP_BITS), + .MAN_BITS (MAN_BITS) + ) fp_class_b ( + .exp_i (b_exponent[i]), + .man_i (b_mantissa[i]), + .clss_o (b_clss[i]) ); - assign tmp_a_smaller[i] = $signed(dataa[i]) < $signed(datab[i]); - assign tmp_ab_equal[i] = (dataa[i] == datab[i]) | (tmp_a_type[i].is_zero & tmp_b_type[i].is_zero); + assign a_smaller[i] = $signed(dataa[i]) < $signed(datab[i]); + assign ab_equal[i] = (dataa[i] == datab[i]) | (a_clss[i].is_zero & b_clss[i].is_zero); end // Pipeline stage0 wire valid_in_s0; wire [TAGW-1:0] tag_in_s0; - wire [`FPU_BITS-1:0] op_type_s0; - wire [`FRM_BITS-1:0] frm_s0; + wire [`INST_FPU_BITS-1:0] op_type_s0; + wire [`INST_FRM_BITS-1:0] frm_s0; wire [LANES-1:0][31:0] dataa_s0, datab_s0; wire [LANES-1:0] a_sign_s0, b_sign_s0; wire [LANES-1:0][7:0] a_exponent_s0; wire [LANES-1:0][22:0] a_mantissa_s0; - fp_type_t [LANES-1:0] a_type_s0, b_type_s0; + fp_class_t [LANES-1:0] a_clss_s0, b_clss_s0; wire [LANES-1:0] a_smaller_s0, ab_equal_s0; wire stall; VX_pipe_register #( - .DATAW (1 + TAGW + `FPU_BITS + `FRM_BITS + LANES * (2 * 32 + 1 + 1 + 8 + 23 + 2 * $bits(fp_type_t) + 1 + 1)), + .DATAW (1 + TAGW + `INST_FPU_BITS + `INST_FRM_BITS + LANES * (2 * 32 + 1 + 1 + 8 + 23 + 2 * $bits(fp_class_t) + 1 + 1)), .RESETW (1), .DEPTH (0) ) pipe_reg0 ( .clk (clk), .reset (reset), .enable (!stall), - .data_in ({valid_in, tag_in, op_type, frm, dataa, datab, tmp_a_sign, tmp_b_sign, tmp_a_exponent, tmp_a_mantissa, tmp_a_type, tmp_b_type, tmp_a_smaller, tmp_ab_equal}), - .data_out ({valid_in_s0, tag_in_s0, op_type_s0, frm_s0, dataa_s0, datab_s0, a_sign_s0, b_sign_s0, a_exponent_s0, a_mantissa_s0, a_type_s0, b_type_s0, a_smaller_s0, ab_equal_s0}) + .data_in ({valid_in, tag_in, op_type, frm, dataa, datab, a_sign, b_sign, a_exponent, a_mantissa, a_clss, b_clss, a_smaller, ab_equal}), + .data_out ({valid_in_s0, tag_in_s0, op_type_s0, frm_s0, dataa_s0, datab_s0, a_sign_s0, b_sign_s0, a_exponent_s0, a_mantissa_s0, a_clss_s0, b_clss_s0, a_smaller_s0, ab_equal_s0}) ); // FCLASS reg [LANES-1:0][31:0] fclass_mask; // generate a 10-bit mask for integer reg for (genvar i = 0; i < LANES; i++) begin always @(*) begin - if (a_type_s0[i].is_normal) begin + if (a_clss_s0[i].is_normal) begin fclass_mask[i] = a_sign_s0[i] ? NEG_NORM : POS_NORM; end - else if (a_type_s0[i].is_inf) begin + else if (a_clss_s0[i].is_inf) begin fclass_mask[i] = a_sign_s0[i] ? NEG_INF : POS_INF; end - else if (a_type_s0[i].is_zero) begin + else if (a_clss_s0[i].is_zero) begin fclass_mask[i] = a_sign_s0[i] ? NEG_ZERO : POS_ZERO; end - else if (a_type_s0[i].is_subnormal) begin + else if (a_clss_s0[i].is_subnormal) begin fclass_mask[i] = a_sign_s0[i] ? NEG_SUBNORM : POS_SUBNORM; end - else if (a_type_s0[i].is_nan) begin - fclass_mask[i] = {22'h0, a_type_s0[i].is_quiet, a_type_s0[i].is_signaling, 8'h0}; + else if (a_clss_s0[i].is_nan) begin + fclass_mask[i] = {22'h0, a_clss_s0[i].is_quiet, a_clss_s0[i].is_signaling, 8'h0}; end else begin fclass_mask[i] = QUT_NAN; @@ -129,11 +138,11 @@ module VX_fp_ncomp #( reg [LANES-1:0][31:0] fminmax_res; // result of fmin/fmax for (genvar i = 0; i < LANES; i++) begin always @(*) begin - if (a_type_s0[i].is_nan && b_type_s0[i].is_nan) + if (a_clss_s0[i].is_nan && b_clss_s0[i].is_nan) fminmax_res[i] = {1'b0, 8'hff, 1'b1, 22'd0}; // canonical qNaN - else if (a_type_s0[i].is_nan) + else if (a_clss_s0[i].is_nan) fminmax_res[i] = datab_s0[i]; - else if (b_type_s0[i].is_nan) + else if (b_clss_s0[i].is_nan) fminmax_res[i] = dataa_s0[i]; else begin case (frm_s0) // use LSB to distinguish MIN and MAX @@ -160,33 +169,33 @@ module VX_fp_ncomp #( // Comparison reg [LANES-1:0][31:0] fcmp_res; // result of comparison - fflags_t [LANES-1:0] fcmp_fflags; // comparison fflags + fflags_t [LANES-1:0] fcmp_fflags; // comparison fflags for (genvar i = 0; i < LANES; i++) begin always @(*) begin case (frm_s0) - `FRM_RNE: begin // LE + `INST_FRM_RNE: begin // LE fcmp_fflags[i] = 5'h0; - if (a_type_s0[i].is_nan || b_type_s0[i].is_nan) begin + if (a_clss_s0[i].is_nan || b_clss_s0[i].is_nan) begin fcmp_res[i] = 32'h0; fcmp_fflags[i].NV = 1'b1; end else begin fcmp_res[i] = {31'h0, (a_smaller_s0[i] | ab_equal_s0[i])}; end end - `FRM_RTZ: begin // LS + `INST_FRM_RTZ: begin // LS fcmp_fflags[i] = 5'h0; - if (a_type_s0[i].is_nan || b_type_s0[i].is_nan) begin + if (a_clss_s0[i].is_nan || b_clss_s0[i].is_nan) begin fcmp_res[i] = 32'h0; fcmp_fflags[i].NV = 1'b1; end else begin fcmp_res[i] = {31'h0, (a_smaller_s0[i] & ~ab_equal_s0[i])}; end end - `FRM_RDN: begin // EQ + `INST_FRM_RDN: begin // EQ fcmp_fflags[i] = 5'h0; - if (a_type_s0[i].is_nan || b_type_s0[i].is_nan) begin + if (a_clss_s0[i].is_nan || b_clss_s0[i].is_nan) begin fcmp_res[i] = 32'h0; - fcmp_fflags[i].NV = a_type_s0[i].is_signaling | b_type_s0[i].is_signaling; + fcmp_fflags[i].NV = a_clss_s0[i].is_signaling | b_clss_s0[i].is_signaling; end else begin fcmp_res[i] = {31'h0, ab_equal_s0[i]}; end @@ -207,11 +216,11 @@ module VX_fp_ncomp #( for (genvar i = 0; i < LANES; i++) begin always @(*) begin case (op_type_s0) - `FPU_CLASS: begin + `INST_FPU_CLASS: begin tmp_result[i] = fclass_mask[i]; tmp_fflags[i] = 'x; end - `FPU_CMP: begin + `INST_FPU_CMP: begin tmp_result[i] = fcmp_res[i]; tmp_fflags[i] = fcmp_fflags[i]; end @@ -225,11 +234,11 @@ module VX_fp_ncomp #( 3,4: begin tmp_result[i] = fminmax_res[i]; tmp_fflags[i] = 0; - tmp_fflags[i].NV = a_type_s0[i].is_signaling | b_type_s0[i].is_signaling; + tmp_fflags[i].NV = a_clss_s0[i].is_signaling | b_clss_s0[i].is_signaling; end //5,6,7: MOVE default: begin - tmp_result[i] = dataa[i]; + tmp_result[i] = dataa_s0[i]; tmp_fflags[i] = 'x; end endcase @@ -238,15 +247,15 @@ module VX_fp_ncomp #( end end - wire has_fflags_s0 = ((op_type_s0 == `FPU_MISC) - && (frm_s0 == 3 // MIN - || frm_s0 == 4)) // MAX - || (op_type_s0 == `FPU_CMP); // CMP + wire has_fflags_s0 = ((op_type_s0 == `INST_FPU_MISC) + && (frm_s0 == 3 // MIN + || frm_s0 == 4)) // MAX + || (op_type_s0 == `INST_FPU_CMP); // CMP assign stall = ~ready_out && valid_out; VX_pipe_register #( - .DATAW (1 + TAGW + (LANES * 32) + 1 + (LANES * `FFG_BITS)), + .DATAW (1 + TAGW + (LANES * 32) + 1 + (LANES * `FFLAGS_BITS)), .RESETW (1) ) pipe_reg1 ( .clk (clk), diff --git a/hw/rtl/fp_cores/VX_fp_rounding.v b/hw/rtl/fp_cores/VX_fp_rounding.sv similarity index 83% rename from hw/rtl/fp_cores/VX_fp_rounding.v rename to hw/rtl/fp_cores/VX_fp_rounding.sv index 9e544e44..415dd29d 100644 --- a/hw/rtl/fp_cores/VX_fp_rounding.v +++ b/hw/rtl/fp_cores/VX_fp_rounding.sv @@ -1,5 +1,4 @@ - -`include "VX_define.vh" +`include "VX_fpu_define.vh" /// Modified port of rouding module from fpnew Libray /// reference: https://github.com/pulp-platform/fpnew @@ -34,7 +33,7 @@ module VX_fp_rounding #( always @(*) begin case (rnd_mode_i) - `FRM_RNE: // Decide accoring to round/sticky bits + `INST_FRM_RNE: // Decide accoring to round/sticky bits case (round_sticky_bits_i) 2'b00, 2'b01: round_up = 1'b0; // < ulp/2 away, round down @@ -42,10 +41,10 @@ module VX_fp_rounding #( 2'b11: round_up = 1'b1; // > ulp/2 away, round up default: round_up = 1'bx; endcase - `FRM_RTZ: round_up = 1'b0; // always round down - `FRM_RDN: round_up = (| round_sticky_bits_i) & sign_i; // to 0 if +, away if - - `FRM_RUP: round_up = (| round_sticky_bits_i) & ~sign_i; // to 0 if -, away if + - `FRM_RMM: round_up = round_sticky_bits_i[1]; // round down if < ulp/2 away, else up + `INST_FRM_RTZ: round_up = 1'b0; // always round down + `INST_FRM_RDN: round_up = (| round_sticky_bits_i) & sign_i; // to 0 if +, away if - + `INST_FRM_RUP: round_up = (| round_sticky_bits_i) & ~sign_i; // to 0 if -, away if + + `INST_FRM_RMM: round_up = round_sticky_bits_i[1]; // round down if < ulp/2 away, else up default: round_up = 1'bx; // propagate x endcase end @@ -58,7 +57,7 @@ module VX_fp_rounding #( // In case of effective subtraction (thus signs of addition operands must have differed) and a // true zero result, the result sign is '-' in case of RDN and '+' for other modes. - assign sign_o = (exact_zero_o && effective_subtraction_i) ? (rnd_mode_i == `FRM_RDN) + assign sign_o = (exact_zero_o && effective_subtraction_i) ? (rnd_mode_i == `INST_FRM_RDN) : sign_i; endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/VX_fp_sqrt.v b/hw/rtl/fp_cores/VX_fp_sqrt.sv similarity index 91% rename from hw/rtl/fp_cores/VX_fp_sqrt.v rename to hw/rtl/fp_cores/VX_fp_sqrt.sv index 1debc04d..441b8d95 100644 --- a/hw/rtl/fp_cores/VX_fp_sqrt.v +++ b/hw/rtl/fp_cores/VX_fp_sqrt.sv @@ -1,8 +1,4 @@ -`include "VX_define.vh" - -`ifndef SYNTHESIS -`include "float_dpi.vh" -`endif +`include "VX_fpu_define.vh" module VX_fp_sqrt #( parameter TAGW = 1, @@ -16,7 +12,7 @@ module VX_fp_sqrt #( input wire [TAGW-1:0] tag_in, - input wire [`FRM_BITS-1:0] frm, + input wire [`INST_FRM_BITS-1:0] frm, input wire [LANES-1:0][31:0] dataa, output wire [LANES-1:0][31:0] result, @@ -38,7 +34,7 @@ module VX_fp_sqrt #( fflags_t f; always @(*) begin - dpi_fsqrt (dataa[i], frm, r, f); + dpi_fsqrt (enable && valid_in, dataa[i], frm, r, f); end `UNUSED_VAR (f) diff --git a/hw/rtl/fp_cores/VX_fp_type.v b/hw/rtl/fp_cores/VX_fp_type.v deleted file mode 100644 index bdc41b86..00000000 --- a/hw/rtl/fp_cores/VX_fp_type.v +++ /dev/null @@ -1,27 +0,0 @@ - -`include "VX_define.vh" - -module VX_fp_type ( - // inputs - input [7:0] exp_i, - input [22:0] man_i, - // outputs - output fp_type_t type_o -); - wire is_normal = (exp_i != 8'd0) && (exp_i != 8'hff); - wire is_zero = (exp_i == 8'd0) && (man_i == 23'd0); - wire is_subnormal = (exp_i == 8'd0) && (man_i != 23'd0); - wire is_inf = (exp_i == 8'hff) && (man_i == 23'd0); - wire is_nan = (exp_i == 8'hff) && (man_i != 23'd0); - wire is_signaling = is_nan && (man_i[22] == 1'b0); - wire is_quiet = is_nan && !is_signaling; - - assign type_o.is_normal = is_normal; - assign type_o.is_zero = is_zero; - assign type_o.is_subnormal = is_subnormal; - assign type_o.is_inf = is_inf; - assign type_o.is_nan = is_nan; - assign type_o.is_quiet = is_quiet; - assign type_o.is_signaling = is_signaling; - -endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/VX_fpu_define.vh b/hw/rtl/fp_cores/VX_fpu_define.vh new file mode 100644 index 00000000..d764e8e4 --- /dev/null +++ b/hw/rtl/fp_cores/VX_fpu_define.vh @@ -0,0 +1,14 @@ +`ifndef VX_FPU_DEFINE +`define VX_FPU_DEFINE + +`include "VX_define.vh" + +`ifndef SYNTHESIS +`include "float_dpi.vh" +`endif + +`IGNORE_WARNINGS_BEGIN +import fpu_types::*; +`IGNORE_WARNINGS_END + +`endif \ No newline at end of file diff --git a/hw/rtl/fp_cores/VX_fpu_dpi.v b/hw/rtl/fp_cores/VX_fpu_dpi.sv similarity index 69% rename from hw/rtl/fp_cores/VX_fpu_dpi.v rename to hw/rtl/fp_cores/VX_fpu_dpi.sv index 10dab769..ae9f8306 100644 --- a/hw/rtl/fp_cores/VX_fpu_dpi.v +++ b/hw/rtl/fp_cores/VX_fpu_dpi.sv @@ -1,7 +1,4 @@ -`ifndef SYNTHESIS - -`include "VX_define.vh" -`include "float_dpi.vh" +`include "VX_fpu_define.vh" module VX_fpu_dpi #( parameter TAGW = 1 @@ -14,8 +11,8 @@ module VX_fpu_dpi #( input wire [TAGW-1:0] tag_in, - input wire [`FPU_BITS-1:0] op_type, - input wire [`MOD_BITS-1:0] frm, + input wire [`INST_FPU_BITS-1:0] op_type, + input wire [`INST_MOD_BITS-1:0] frm, input wire [`NUM_THREADS-1:0][31:0] dataa, input wire [`NUM_THREADS-1:0][31:0] datab, @@ -76,21 +73,21 @@ module VX_fpu_dpi #( is_fsgnjx = 0; case (op_type) - `FPU_ADD: begin core_select = FPU_FMA; is_fadd = 1; end - `FPU_SUB: begin core_select = FPU_FMA; is_fsub = 1; end - `FPU_MUL: begin core_select = FPU_FMA; is_fmul = 1; end - `FPU_MADD: begin core_select = FPU_FMA; is_fmadd = 1; end - `FPU_MSUB: begin core_select = FPU_FMA; is_fmsub = 1; end - `FPU_NMADD: begin core_select = FPU_FMA; is_fnmadd = 1; end - `FPU_NMSUB: begin core_select = FPU_FMA; is_fnmsub = 1; end - `FPU_DIV: begin core_select = FPU_DIV; end - `FPU_SQRT: begin core_select = FPU_SQRT; end - `FPU_CVTWS: begin core_select = FPU_CVT; is_ftoi = 1; end - `FPU_CVTWUS:begin core_select = FPU_CVT; is_ftou = 1; end - `FPU_CVTSW: begin core_select = FPU_CVT; is_itof = 1; end - `FPU_CVTSWU:begin core_select = FPU_CVT; is_utof = 1; end - `FPU_CLASS: begin core_select = FPU_NCP; is_fclss = 1; end - `FPU_CMP: begin core_select = FPU_NCP; + `INST_FPU_ADD: begin core_select = FPU_FMA; is_fadd = 1; end + `INST_FPU_SUB: begin core_select = FPU_FMA; is_fsub = 1; end + `INST_FPU_MUL: begin core_select = FPU_FMA; is_fmul = 1; end + `INST_FPU_MADD: begin core_select = FPU_FMA; is_fmadd = 1; end + `INST_FPU_MSUB: begin core_select = FPU_FMA; is_fmsub = 1; end + `INST_FPU_NMADD: begin core_select = FPU_FMA; is_fnmadd = 1; end + `INST_FPU_NMSUB: begin core_select = FPU_FMA; is_fnmsub = 1; end + `INST_FPU_DIV: begin core_select = FPU_DIV; end + `INST_FPU_SQRT: begin core_select = FPU_SQRT; end + `INST_FPU_CVTWS: begin core_select = FPU_CVT; is_ftoi = 1; end + `INST_FPU_CVTWUS:begin core_select = FPU_CVT; is_ftou = 1; end + `INST_FPU_CVTSW: begin core_select = FPU_CVT; is_itof = 1; end + `INST_FPU_CVTSWU:begin core_select = FPU_CVT; is_utof = 1; end + `INST_FPU_CLASS: begin core_select = FPU_NCP; is_fclss = 1; end + `INST_FPU_CMP: begin core_select = FPU_NCP; is_fle = (frm == 0); is_flt = (frm == 1); is_feq = (frm == 2); @@ -126,15 +123,20 @@ module VX_fpu_dpi #( fflags_t [`NUM_THREADS-1:0] fflags_fnmadd; fflags_t [`NUM_THREADS-1:0] fflags_fnmsub; + wire fma_valid = (valid_in && core_select == FPU_FMA); + wire fma_ready = per_core_ready_out[FPU_FMA] || ~per_core_valid_out[FPU_FMA]; + + wire fma_fire = fma_valid && fma_ready; + always @(*) begin for (integer i = 0; i < `NUM_THREADS; i++) begin - dpi_fadd (dataa[i], datab[i], frm, result_fadd[i], fflags_fadd[i]); - dpi_fsub (dataa[i], datab[i], frm, result_fsub[i], fflags_fsub[i]); - dpi_fmul (dataa[i], datab[i], frm, result_fmul[i], fflags_fmul[i]); - dpi_fmadd (dataa[i], datab[i], datac[i], frm, result_fmadd[i], fflags_fmadd[i]); - dpi_fmsub (dataa[i], datab[i], datac[i], frm, result_fmsub[i], fflags_fmsub[i]); - dpi_fnmadd (dataa[i], datab[i], datac[i], frm, result_fnmadd[i], fflags_fnmadd[i]); - dpi_fnmsub (dataa[i], datab[i], datac[i], frm, result_fnmsub[i], fflags_fnmsub[i]); + dpi_fadd (fma_fire, dataa[i], datab[i], frm, result_fadd[i], fflags_fadd[i]); + dpi_fsub (fma_fire, dataa[i], datab[i], frm, result_fsub[i], fflags_fsub[i]); + dpi_fmul (fma_fire, dataa[i], datab[i], frm, result_fmul[i], fflags_fmul[i]); + dpi_fmadd (fma_fire, dataa[i], datab[i], datac[i], frm, result_fmadd[i], fflags_fmadd[i]); + dpi_fmsub (fma_fire, dataa[i], datab[i], datac[i], frm, result_fmsub[i], fflags_fmsub[i]); + dpi_fnmadd (fma_fire, dataa[i], datab[i], datac[i], frm, result_fnmadd[i], fflags_fnmadd[i]); + dpi_fnmsub (fma_fire, dataa[i], datab[i], datac[i], frm, result_fnmsub[i], fflags_fnmsub[i]); end end @@ -154,10 +156,7 @@ module VX_fpu_dpi #( is_fmsub ? fflags_fmsub : is_fnmadd ? fflags_fnmadd : is_fnmsub ? fflags_fnmsub : - 0; - - wire enable = per_core_ready_out[FPU_FMA] || ~per_core_valid_out[FPU_FMA]; - wire valid = (valid_in && core_select == FPU_FMA); + 0; VX_shift_register #( .DATAW (1 + TAGW + `NUM_THREADS * (32 + $bits(fflags_t))), @@ -166,13 +165,13 @@ module VX_fpu_dpi #( ) shift_reg ( .clk (clk), .reset (reset), - .enable (enable), - .data_in ({valid, tag_in, result_fma, fflags_fma}), + .enable (fma_ready), + .data_in ({fma_valid, tag_in, result_fma, fflags_fma}), .data_out ({per_core_valid_out[FPU_FMA], per_core_tag_out[FPU_FMA], per_core_result[FPU_FMA], per_core_fflags[FPU_FMA]}) ); assign per_core_has_fflags[FPU_FMA] = 1; - assign per_core_ready_in[FPU_FMA] = enable; + assign per_core_ready_in[FPU_FMA] = fma_ready; end endgenerate @@ -182,16 +181,18 @@ module VX_fpu_dpi #( wire [`NUM_THREADS-1:0][31:0] result_fdiv; fflags_t [`NUM_THREADS-1:0] fflags_fdiv; + + wire fdiv_valid = (valid_in && core_select == FPU_DIV); + wire fdiv_ready = per_core_ready_out[FPU_DIV] || ~per_core_valid_out[FPU_DIV]; + + wire fdiv_fire = fdiv_valid && fdiv_ready; always @(*) begin for (integer i = 0; i < `NUM_THREADS; i++) begin - dpi_fdiv (dataa[i], datab[i], frm, result_fdiv[i], fflags_fdiv[i]); + dpi_fdiv (fdiv_fire, dataa[i], datab[i], frm, result_fdiv[i], fflags_fdiv[i]); end end - wire enable = per_core_ready_out[FPU_DIV] || ~per_core_valid_out[FPU_DIV]; - wire valid = (valid_in && core_select == FPU_DIV); - VX_shift_register #( .DATAW (1 + TAGW + `NUM_THREADS * (32 + $bits(fflags_t))), .DEPTH (`LATENCY_FDIV), @@ -199,13 +200,13 @@ module VX_fpu_dpi #( ) shift_reg ( .clk (clk), .reset (reset), - .enable (enable), - .data_in ({valid, tag_in, result_fdiv, fflags_fdiv}), + .enable (fdiv_ready), + .data_in ({fdiv_valid, tag_in, result_fdiv, fflags_fdiv}), .data_out ({per_core_valid_out[FPU_DIV], per_core_tag_out[FPU_DIV], per_core_result[FPU_DIV], per_core_fflags[FPU_DIV]}) ); assign per_core_has_fflags[FPU_DIV] = 1; - assign per_core_ready_in[FPU_DIV] = enable; + assign per_core_ready_in[FPU_DIV] = fdiv_ready; end endgenerate @@ -215,16 +216,18 @@ module VX_fpu_dpi #( wire [`NUM_THREADS-1:0][31:0] result_fsqrt; fflags_t [`NUM_THREADS-1:0] fflags_fsqrt; + + wire fsqrt_valid = (valid_in && core_select == FPU_SQRT); + wire fsqrt_ready = per_core_ready_out[FPU_SQRT] || ~per_core_valid_out[FPU_SQRT]; + + wire fsqrt_fire = fsqrt_valid && fsqrt_ready; always @(*) begin for (integer i = 0; i < `NUM_THREADS; i++) begin - dpi_fsqrt (dataa[i], frm, result_fsqrt[i], fflags_fsqrt[i]); + dpi_fsqrt (fsqrt_fire, dataa[i], frm, result_fsqrt[i], fflags_fsqrt[i]); end end - wire enable = per_core_ready_out[FPU_SQRT] || ~per_core_valid_out[FPU_SQRT]; - wire valid = (valid_in && core_select == FPU_SQRT); - VX_shift_register #( .DATAW (1 + TAGW + `NUM_THREADS * (32 + $bits(fflags_t))), .DEPTH (`LATENCY_FSQRT), @@ -232,13 +235,13 @@ module VX_fpu_dpi #( ) shift_reg ( .clk (clk), .reset (reset), - .enable (enable), - .data_in ({valid, tag_in, result_fsqrt, fflags_fsqrt}), + .enable (fsqrt_ready), + .data_in ({fsqrt_valid, tag_in, result_fsqrt, fflags_fsqrt}), .data_out ({per_core_valid_out[FPU_SQRT], per_core_tag_out[FPU_SQRT], per_core_result[FPU_SQRT], per_core_fflags[FPU_SQRT]}) ); assign per_core_has_fflags[FPU_SQRT] = 1; - assign per_core_ready_in[FPU_SQRT] = enable; + assign per_core_ready_in[FPU_SQRT] = fsqrt_ready; end endgenerate @@ -257,13 +260,18 @@ module VX_fpu_dpi #( fflags_t [`NUM_THREADS-1:0] fflags_utof; fflags_t [`NUM_THREADS-1:0] fflags_ftoi; fflags_t [`NUM_THREADS-1:0] fflags_ftou; - + + wire fcvt_valid = (valid_in && core_select == FPU_CVT); + wire fcvt_ready = per_core_ready_out[FPU_CVT] || ~per_core_valid_out[FPU_CVT]; + + wire fcvt_fire = fcvt_valid && fcvt_ready; + always @(*) begin for (integer i = 0; i < `NUM_THREADS; i++) begin - dpi_itof (dataa[i], frm, result_itof[i], fflags_itof[i]); - dpi_utof (dataa[i], frm, result_utof[i], fflags_utof[i]); - dpi_ftoi (dataa[i], frm, result_ftoi[i], fflags_ftoi[i]); - dpi_ftou (dataa[i], frm, result_ftou[i], fflags_ftou[i]); + dpi_itof (fcvt_fire, dataa[i], frm, result_itof[i], fflags_itof[i]); + dpi_utof (fcvt_fire, dataa[i], frm, result_utof[i], fflags_utof[i]); + dpi_ftoi (fcvt_fire, dataa[i], frm, result_ftoi[i], fflags_ftoi[i]); + dpi_ftou (fcvt_fire, dataa[i], frm, result_ftou[i], fflags_ftou[i]); end end @@ -279,9 +287,6 @@ module VX_fpu_dpi #( is_ftou ? fflags_ftou : 0; - wire enable = per_core_ready_out[FPU_CVT] || ~per_core_valid_out[FPU_CVT]; - wire valid = (valid_in && core_select == FPU_CVT); - VX_shift_register #( .DATAW (1 + TAGW + `NUM_THREADS * (32 + $bits(fflags_t))), .DEPTH (`LATENCY_FCVT), @@ -289,13 +294,13 @@ module VX_fpu_dpi #( ) shift_reg ( .clk (clk), .reset (reset), - .enable (enable), - .data_in ({valid, tag_in, result_fcvt, fflags_fcvt}), + .enable (fcvt_ready), + .data_in ({fcvt_valid, tag_in, result_fcvt, fflags_fcvt}), .data_out ({per_core_valid_out[FPU_CVT], per_core_tag_out[FPU_CVT], per_core_result[FPU_CVT], per_core_fflags[FPU_CVT]}) ); assign per_core_has_fflags[FPU_CVT] = 1; - assign per_core_ready_in[FPU_CVT] = enable; + assign per_core_ready_in[FPU_CVT] = fcvt_ready; end endgenerate @@ -321,18 +326,23 @@ module VX_fpu_dpi #( fflags_t [`NUM_THREADS-1:0] fflags_feq; fflags_t [`NUM_THREADS-1:0] fflags_fmin; fflags_t [`NUM_THREADS-1:0] fflags_fmax; - + + wire fncp_valid = (valid_in && core_select == FPU_NCP); + wire fncp_ready = per_core_ready_out[FPU_NCP] || ~per_core_valid_out[FPU_NCP]; + + wire fncp_fire = fncp_valid && fncp_ready; + always @(*) begin for (integer i = 0; i < `NUM_THREADS; i++) begin - dpi_fclss (dataa[i], result_fclss[i]); - dpi_flt (dataa[i], datab[i], result_flt[i], fflags_flt[i]); - dpi_fle (dataa[i], datab[i], result_fle[i], fflags_fle[i]); - dpi_feq (dataa[i], datab[i], result_feq[i], fflags_feq[i]); - dpi_fmin (dataa[i], datab[i], result_fmin[i], fflags_fmin[i]); - dpi_fmax (dataa[i], datab[i], result_fmax[i], fflags_fmax[i]); - dpi_fsgnj (dataa[i], datab[i], result_fsgnj[i]); - dpi_fsgnjn (dataa[i], datab[i], result_fsgnjn[i]); - dpi_fsgnjx (dataa[i], datab[i], result_fsgnjx[i]); + dpi_fclss (fncp_fire, dataa[i], result_fclss[i]); + dpi_flt (fncp_fire, dataa[i], datab[i], result_flt[i], fflags_flt[i]); + dpi_fle (fncp_fire, dataa[i], datab[i], result_fle[i], fflags_fle[i]); + dpi_feq (fncp_fire, dataa[i], datab[i], result_feq[i], fflags_feq[i]); + dpi_fmin (fncp_fire, dataa[i], datab[i], result_fmin[i], fflags_fmin[i]); + dpi_fmax (fncp_fire, dataa[i], datab[i], result_fmax[i], fflags_fmax[i]); + dpi_fsgnj (fncp_fire, dataa[i], datab[i], result_fsgnj[i]); + dpi_fsgnjn (fncp_fire, dataa[i], datab[i], result_fsgnjn[i]); + dpi_fsgnjx (fncp_fire, dataa[i], datab[i], result_fsgnjx[i]); result_fmv[i] = dataa[i]; end end @@ -357,9 +367,6 @@ module VX_fpu_dpi #( is_fmax ? fflags_fmax : 0; - wire enable = per_core_ready_out[FPU_NCP] || ~per_core_valid_out[FPU_NCP]; - wire valid = (valid_in && core_select == FPU_NCP); - VX_shift_register #( .DATAW (1 + TAGW + 1 + `NUM_THREADS * (32 + $bits(fflags_t))), .DEPTH (`LATENCY_FNCP), @@ -367,12 +374,12 @@ module VX_fpu_dpi #( ) shift_reg ( .clk (clk), .reset (reset), - .enable (enable), - .data_in ({valid, tag_in, has_fflags_fncp, result_fncp, fflags_fncp}), + .enable (fncp_ready), + .data_in ({fncp_valid, tag_in, has_fflags_fncp, result_fncp, fflags_fncp}), .data_out ({per_core_valid_out[FPU_NCP], per_core_tag_out[FPU_NCP], per_core_has_fflags[FPU_NCP], per_core_result[FPU_NCP], per_core_fflags[FPU_NCP]}) ); - assign per_core_ready_in[FPU_NCP] = enable; + assign per_core_ready_in[FPU_NCP] = fncp_ready; end endgenerate @@ -410,6 +417,4 @@ module VX_fpu_dpi #( assign ready_in = per_core_ready_in[core_select]; -endmodule - -`endif \ No newline at end of file +endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/VX_fpu_fpga.v b/hw/rtl/fp_cores/VX_fpu_fpga.sv similarity index 84% rename from hw/rtl/fp_cores/VX_fpu_fpga.v rename to hw/rtl/fp_cores/VX_fpu_fpga.sv index 791d1f4c..671f1656 100644 --- a/hw/rtl/fp_cores/VX_fpu_fpga.v +++ b/hw/rtl/fp_cores/VX_fpu_fpga.sv @@ -1,7 +1,7 @@ -`include "VX_define.vh" +`include "VX_fpu_define.vh" module VX_fpu_fpga #( - parameter TAGW = 1 + parameter TAGW = 4 ) ( input wire clk, input wire reset, @@ -11,8 +11,8 @@ module VX_fpu_fpga #( input wire [TAGW-1:0] tag_in, - input wire [`FPU_BITS-1:0] op_type, - input wire [`MOD_BITS-1:0] frm, + input wire [`INST_FPU_BITS-1:0] op_type, + input wire [`INST_MOD_BITS-1:0] frm, input wire [`NUM_THREADS-1:0][31:0] dataa, input wire [`NUM_THREADS-1:0][31:0] datab, @@ -54,19 +54,19 @@ module VX_fpu_fpga #( is_itof = 0; is_signed = 0; case (op_type) - `FPU_ADD: begin core_select = FPU_FMA; end - `FPU_SUB: begin core_select = FPU_FMA; do_sub = 1; end - `FPU_MUL: begin core_select = FPU_FMA; do_neg = 1; end - `FPU_MADD: begin core_select = FPU_FMA; do_madd = 1; end - `FPU_MSUB: begin core_select = FPU_FMA; do_madd = 1; do_sub = 1; end - `FPU_NMADD: begin core_select = FPU_FMA; do_madd = 1; do_neg = 1; end - `FPU_NMSUB: begin core_select = FPU_FMA; do_madd = 1; do_sub = 1; do_neg = 1; end - `FPU_DIV: begin core_select = FPU_DIV; end - `FPU_SQRT: begin core_select = FPU_SQRT; end - `FPU_CVTWS: begin core_select = FPU_CVT; is_signed = 1; end - `FPU_CVTWUS: begin core_select = FPU_CVT; end - `FPU_CVTSW: begin core_select = FPU_CVT; is_itof = 1; is_signed = 1; end - `FPU_CVTSWU: begin core_select = FPU_CVT; is_itof = 1; end + `INST_FPU_ADD: begin core_select = FPU_FMA; end + `INST_FPU_SUB: begin core_select = FPU_FMA; do_sub = 1; end + `INST_FPU_MUL: begin core_select = FPU_FMA; do_neg = 1; end + `INST_FPU_MADD: begin core_select = FPU_FMA; do_madd = 1; end + `INST_FPU_MSUB: begin core_select = FPU_FMA; do_madd = 1; do_sub = 1; end + `INST_FPU_NMADD: begin core_select = FPU_FMA; do_madd = 1; do_neg = 1; end + `INST_FPU_NMSUB: begin core_select = FPU_FMA; do_madd = 1; do_sub = 1; do_neg = 1; end + `INST_FPU_DIV: begin core_select = FPU_DIV; end + `INST_FPU_SQRT: begin core_select = FPU_SQRT; end + `INST_FPU_CVTWS: begin core_select = FPU_CVT; is_signed = 1; end + `INST_FPU_CVTWUS: begin core_select = FPU_CVT; end + `INST_FPU_CVTSW: begin core_select = FPU_CVT; is_itof = 1; is_signed = 1; end + `INST_FPU_CVTSWU: begin core_select = FPU_CVT; is_itof = 1; end default: begin core_select = FPU_NCP; end endcase end diff --git a/hw/rtl/fp_cores/VX_fpu_fpnew.v b/hw/rtl/fp_cores/VX_fpu_fpnew.sv similarity index 82% rename from hw/rtl/fp_cores/VX_fpu_fpnew.v rename to hw/rtl/fp_cores/VX_fpu_fpnew.sv index 450a8594..deaf62de 100644 --- a/hw/rtl/fp_cores/VX_fpu_fpnew.v +++ b/hw/rtl/fp_cores/VX_fpu_fpnew.sv @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_fpu_define.vh" `include "fpnew_pkg.sv" `include "defs_div_sqrt_mvp.sv" @@ -18,8 +18,8 @@ module VX_fpu_fpnew #( input wire [TAGW-1:0] tag_in, - input wire [`FPU_BITS-1:0] op_type, - input wire [`MOD_BITS-1:0] frm, + input wire [`INST_FPU_BITS-1:0] op_type, + input wire [`INST_MOD_BITS-1:0] frm, input wire [`NUM_THREADS-1:0][31:0] dataa, input wire [`NUM_THREADS-1:0][31:0] datab, @@ -80,7 +80,7 @@ module VX_fpu_fpnew #( fpnew_pkg::status_t [`NUM_THREADS-1:0] fpu_status; reg [FOP_BITS-1:0] fpu_op; - reg [`FRM_BITS-1:0] fpu_rnd; + reg [`INST_FRM_BITS-1:0] fpu_rnd; reg fpu_op_mod; reg fpu_has_fflags, fpu_has_fflags_out; @@ -94,38 +94,38 @@ module VX_fpu_fpnew #( fpu_operands[2] = datac; case (op_type) - `FPU_ADD: begin + `INST_FPU_ADD: begin fpu_op = fpnew_pkg::ADD; fpu_operands[1] = dataa; fpu_operands[2] = datab; end - `FPU_SUB: begin + `INST_FPU_SUB: begin fpu_op = fpnew_pkg::ADD; fpu_operands[1] = dataa; fpu_operands[2] = datab; fpu_op_mod = 1; end - `FPU_MUL: begin fpu_op = fpnew_pkg::MUL; end - `FPU_DIV: begin fpu_op = fpnew_pkg::DIV; end - `FPU_SQRT: begin fpu_op = fpnew_pkg::SQRT; end - `FPU_MADD: begin fpu_op = fpnew_pkg::FMADD; end - `FPU_MSUB: begin fpu_op = fpnew_pkg::FMADD; fpu_op_mod = 1; end - `FPU_NMADD: begin fpu_op = fpnew_pkg::FNMSUB; fpu_op_mod = 1; end - `FPU_NMSUB: begin fpu_op = fpnew_pkg::FNMSUB; end - `FPU_CVTWS: begin fpu_op = fpnew_pkg::F2I; end - `FPU_CVTWUS:begin fpu_op = fpnew_pkg::F2I; fpu_op_mod = 1; end - `FPU_CVTSW: begin fpu_op = fpnew_pkg::I2F; end - `FPU_CVTSWU:begin fpu_op = fpnew_pkg::I2F; fpu_op_mod = 1; end - `FPU_CLASS: begin fpu_op = fpnew_pkg::CLASSIFY; fpu_has_fflags = 0; end - `FPU_CMP: begin fpu_op = fpnew_pkg::CMP; end - `FPU_MISC: begin + `INST_FPU_MUL: begin fpu_op = fpnew_pkg::MUL; end + `INST_FPU_DIV: begin fpu_op = fpnew_pkg::DIV; end + `INST_FPU_SQRT: begin fpu_op = fpnew_pkg::SQRT; end + `INST_FPU_MADD: begin fpu_op = fpnew_pkg::FMADD; end + `INST_FPU_MSUB: begin fpu_op = fpnew_pkg::FMADD; fpu_op_mod = 1; end + `INST_FPU_NMADD: begin fpu_op = fpnew_pkg::FNMSUB; fpu_op_mod = 1; end + `INST_FPU_NMSUB: begin fpu_op = fpnew_pkg::FNMSUB; end + `INST_FPU_CVTWS: begin fpu_op = fpnew_pkg::F2I; end + `INST_FPU_CVTWUS:begin fpu_op = fpnew_pkg::F2I; fpu_op_mod = 1; end + `INST_FPU_CVTSW: begin fpu_op = fpnew_pkg::I2F; end + `INST_FPU_CVTSWU:begin fpu_op = fpnew_pkg::I2F; fpu_op_mod = 1; end + `INST_FPU_CLASS: begin fpu_op = fpnew_pkg::CLASSIFY; fpu_has_fflags = 0; end + `INST_FPU_CMP: begin fpu_op = fpnew_pkg::CMP; end + `INST_FPU_MISC: begin case (frm) - 0: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RNE; fpu_has_fflags = 0; end - 1: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RTZ; fpu_has_fflags = 0; end - 2: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RDN; fpu_has_fflags = 0; end - 3: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `FRM_RNE; end - 4: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `FRM_RTZ; end - default: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RUP; fpu_has_fflags = 0; end + 0: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `INST_FRM_RNE; fpu_has_fflags = 0; end + 1: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `INST_FRM_RTZ; fpu_has_fflags = 0; end + 2: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `INST_FRM_RDN; fpu_has_fflags = 0; end + 3: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `INST_FRM_RNE; end + 4: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `INST_FRM_RTZ; end + default: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `INST_FRM_RUP; fpu_has_fflags = 0; end endcase end default:; diff --git a/hw/rtl/fp_cores/VX_fpu_types.vh b/hw/rtl/fp_cores/VX_fpu_types.vh new file mode 100644 index 00000000..df8a955f --- /dev/null +++ b/hw/rtl/fp_cores/VX_fpu_types.vh @@ -0,0 +1,32 @@ +`ifndef VX_FPU_TYPES +`define VX_FPU_TYPES + +`include "VX_define.vh" + +package fpu_types; + +typedef struct packed { + logic is_normal; + logic is_zero; + logic is_subnormal; + logic is_inf; + logic is_nan; + logic is_quiet; + logic is_signaling; +} fp_class_t; + +`define FP_CLASS_BITS $bits(fpu_types::fp_class_t) + +typedef struct packed { + logic NV; // 4-Invalid + logic DZ; // 3-Divide by zero + logic OF; // 2-Overflow + logic UF; // 1-Underflow + logic NX; // 0-Inexact +} fflags_t; + +`define FFLAGS_BITS $bits(fpu_types::fflags_t) + +endpackage + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_alu_req_if.sv b/hw/rtl/interfaces/VX_alu_req_if.sv new file mode 100644 index 00000000..2c6ffd5e --- /dev/null +++ b/hw/rtl/interfaces/VX_alu_req_if.sv @@ -0,0 +1,65 @@ +`ifndef VX_ALU_REQ_IF +`define VX_ALU_REQ_IF + +`include "VX_define.vh" + +interface VX_alu_req_if (); + + wire valid; + wire [`NW_BITS-1:0] wid; + wire [`NUM_THREADS-1:0] tmask; + wire [31:0] PC; + wire [31:0] next_PC; + wire [`INST_ALU_BITS-1:0] op_type; + wire [`INST_MOD_BITS-1:0] op_mod; + wire use_PC; + wire use_imm; + wire [31:0] imm; + wire [`NT_BITS-1:0] tid; + wire [`NUM_THREADS-1:0][31:0] rs1_data; + wire [`NUM_THREADS-1:0][31:0] rs2_data; + wire [`NR_BITS-1:0] rd; + wire wb; + wire ready; + + modport master ( + output valid, + output wid, + output tmask, + output PC, + output next_PC, + output op_type, + output op_mod, + output use_PC, + output use_imm, + output imm, + output tid, + output rs1_data, + output rs2_data, + output rd, + output wb, + input ready + ); + + modport slave ( + input valid, + input wid, + input tmask, + input PC, + input next_PC, + input op_type, + input op_mod, + input use_PC, + input use_imm, + input imm, + input tid, + input rs1_data, + input rs2_data, + input rd, + input wb, + output ready + ); + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_alu_req_if.v b/hw/rtl/interfaces/VX_alu_req_if.v deleted file mode 100644 index 2df383fb..00000000 --- a/hw/rtl/interfaces/VX_alu_req_if.v +++ /dev/null @@ -1,27 +0,0 @@ -`ifndef VX_ALU_REQ_IF -`define VX_ALU_REQ_IF - -`include "VX_define.vh" - -interface VX_alu_req_if (); - - wire valid; - wire [`NW_BITS-1:0] wid; - wire [`NUM_THREADS-1:0] tmask; - wire [31:0] PC; - wire [31:0] next_PC; - wire [`ALU_BITS-1:0] op_type; - wire [`MOD_BITS-1:0] op_mod; - wire use_PC; - wire use_imm; - wire [31:0] imm; - wire [`NT_BITS-1:0] tid; - wire [`NUM_THREADS-1:0][31:0] rs1_data; - wire [`NUM_THREADS-1:0][31:0] rs2_data; - wire [`NR_BITS-1:0] rd; - wire wb; - wire ready; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_branch_ctl_if.v b/hw/rtl/interfaces/VX_branch_ctl_if.sv similarity index 53% rename from hw/rtl/interfaces/VX_branch_ctl_if.v rename to hw/rtl/interfaces/VX_branch_ctl_if.sv index 5e5e840a..f71c43fe 100644 --- a/hw/rtl/interfaces/VX_branch_ctl_if.v +++ b/hw/rtl/interfaces/VX_branch_ctl_if.sv @@ -10,6 +10,20 @@ interface VX_branch_ctl_if (); wire taken; wire [31:0] dest; + modport master ( + output valid, + output wid, + output taken, + output dest + ); + + modport slave ( + input valid, + input wid, + input taken, + input dest + ); + endinterface `endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_cmt_to_csr_if.sv b/hw/rtl/interfaces/VX_cmt_to_csr_if.sv new file mode 100644 index 00000000..800d428d --- /dev/null +++ b/hw/rtl/interfaces/VX_cmt_to_csr_if.sv @@ -0,0 +1,23 @@ +`ifndef VX_CMT_TO_CSR_IF +`define VX_CMT_TO_CSR_IF + +`include "VX_define.vh" + +interface VX_cmt_to_csr_if (); + + wire valid; + wire [$clog2(`NUM_THREADS+1)-1:0] commit_size; + + modport master ( + output valid, + output commit_size + ); + + modport slave ( + input valid, + input commit_size + ); + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_cmt_to_csr_if.v b/hw/rtl/interfaces/VX_cmt_to_csr_if.v deleted file mode 100644 index d8d11e6e..00000000 --- a/hw/rtl/interfaces/VX_cmt_to_csr_if.v +++ /dev/null @@ -1,15 +0,0 @@ -`ifndef VX_CMT_TO_CSR_IF -`define VX_CMT_TO_CSR_IF - -`include "VX_define.vh" - -interface VX_cmt_to_csr_if #( - parameter SIZE -)(); - - wire valid; - wire [SIZE-1:0] commit_size; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_commit_if.sv b/hw/rtl/interfaces/VX_commit_if.sv new file mode 100644 index 00000000..4b6844d6 --- /dev/null +++ b/hw/rtl/interfaces/VX_commit_if.sv @@ -0,0 +1,44 @@ +`ifndef VX_COMMIT_IF +`define VX_COMMIT_IF + +`include "VX_define.vh" + +interface VX_commit_if (); + + wire valid; + wire [`NW_BITS-1:0] wid; + wire [`NUM_THREADS-1:0] tmask; + wire [31:0] PC; + wire [`NUM_THREADS-1:0][31:0] data; + wire [`NR_BITS-1:0] rd; + wire wb; + wire eop; + wire ready; + + modport master ( + output valid, + output wid, + output tmask, + output PC, + output data, + output rd, + output wb, + output eop, + input ready + ); + + modport slave ( + input valid, + input wid, + input tmask, + input PC, + input data, + input rd, + input wb, + input eop, + output ready + ); + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_commit_if.v b/hw/rtl/interfaces/VX_commit_if.v deleted file mode 100644 index 05d0f11c..00000000 --- a/hw/rtl/interfaces/VX_commit_if.v +++ /dev/null @@ -1,20 +0,0 @@ -`ifndef VX_COMMIT_IF -`define VX_COMMIT_IF - -`include "VX_define.vh" - -interface VX_commit_if (); - - wire valid; - wire [`NW_BITS-1:0] wid; - wire [`NUM_THREADS-1:0] tmask; - wire [31:0] PC; - wire [`NUM_THREADS-1:0][31:0] data; - wire [`NR_BITS-1:0] rd; - wire wb; - wire eop; - wire ready; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_csr_req_if.sv b/hw/rtl/interfaces/VX_csr_req_if.sv new file mode 100644 index 00000000..23345d53 --- /dev/null +++ b/hw/rtl/interfaces/VX_csr_req_if.sv @@ -0,0 +1,53 @@ +`ifndef VX_CSR_REQ_IF +`define VX_CSR_REQ_IF + +`include "VX_define.vh" + +interface VX_csr_req_if (); + + wire valid; + wire [`NW_BITS-1:0] wid; + wire [`NUM_THREADS-1:0] tmask; + wire [31:0] PC; + wire [`INST_CSR_BITS-1:0] op_type; + wire [`CSR_ADDR_BITS-1:0] addr; + wire [31:0] rs1_data; + wire use_imm; + wire [`NRI_BITS-1:0] imm; + wire [`NR_BITS-1:0] rd; + wire wb; + wire ready; + + modport master ( + output valid, + output wid, + output tmask, + output PC, + output op_type, + output addr, + output rs1_data, + output use_imm, + output imm, + output rd, + output wb, + input ready + ); + + modport slave ( + input valid, + input wid, + input tmask, + input PC, + input op_type, + input addr, + input rs1_data, + input use_imm, + input imm, + input rd, + input wb, + output ready + ); + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_csr_req_if.v b/hw/rtl/interfaces/VX_csr_req_if.v deleted file mode 100644 index c02a67b4..00000000 --- a/hw/rtl/interfaces/VX_csr_req_if.v +++ /dev/null @@ -1,23 +0,0 @@ -`ifndef VX_CSR_REQ_IF -`define VX_CSR_REQ_IF - -`include "VX_define.vh" - -interface VX_csr_req_if (); - - wire valid; - wire [`NW_BITS-1:0] wid; - wire [`NUM_THREADS-1:0] tmask; - wire [31:0] PC; - wire [`CSR_BITS-1:0] op_type; - wire [`CSR_ADDR_BITS-1:0] addr; - wire [31:0] rs1_data; - wire use_imm; - wire [`NR_BITS-1:0] rs1; - wire [`NR_BITS-1:0] rd; - wire wb; - wire ready; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_dcache_req_if.v b/hw/rtl/interfaces/VX_dcache_req_if.sv similarity index 63% rename from hw/rtl/interfaces/VX_dcache_req_if.v rename to hw/rtl/interfaces/VX_dcache_req_if.sv index c922ea64..13f3b00b 100644 --- a/hw/rtl/interfaces/VX_dcache_req_if.v +++ b/hw/rtl/interfaces/VX_dcache_req_if.sv @@ -17,6 +17,26 @@ interface VX_dcache_req_if #( wire [NUM_REQS-1:0][TAG_WIDTH-1:0] tag; wire [NUM_REQS-1:0] ready; + modport master ( + output valid, + output rw, + output byteen, + output addr, + output data, + output tag, + input ready + ); + + modport slave ( + input valid, + input rw, + input byteen, + input addr, + input data, + input tag, + output ready + ); + endinterface `endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_dcache_rsp_if.v b/hw/rtl/interfaces/VX_dcache_rsp_if.sv similarity index 63% rename from hw/rtl/interfaces/VX_dcache_rsp_if.v rename to hw/rtl/interfaces/VX_dcache_rsp_if.sv index df72c1e3..0f424501 100644 --- a/hw/rtl/interfaces/VX_dcache_rsp_if.v +++ b/hw/rtl/interfaces/VX_dcache_rsp_if.sv @@ -15,6 +15,22 @@ interface VX_dcache_rsp_if #( wire [TAG_WIDTH-1:0] tag; wire ready; + modport master ( + output valid, + output tmask, + output data, + output tag, + input ready + ); + + modport slave ( + input valid, + input tmask, + input data, + input tag, + output ready + ); + endinterface `endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_decode_if.sv b/hw/rtl/interfaces/VX_decode_if.sv new file mode 100644 index 00000000..90c5d70e --- /dev/null +++ b/hw/rtl/interfaces/VX_decode_if.sv @@ -0,0 +1,65 @@ +`ifndef VX_DECODE_IF +`define VX_DECODE_IF + +`include "VX_define.vh" + +interface VX_decode_if (); + + wire valid; + wire [`NW_BITS-1:0] wid; + wire [`NUM_THREADS-1:0] tmask; + wire [31:0] PC; + wire [`EX_BITS-1:0] ex_type; + wire [`INST_OP_BITS-1:0] op_type; + wire [`INST_MOD_BITS-1:0] op_mod; + wire wb; + wire use_PC; + wire use_imm; + wire [31:0] imm; + wire [`NR_BITS-1:0] rd; + wire [`NR_BITS-1:0] rs1; + wire [`NR_BITS-1:0] rs2; + wire [`NR_BITS-1:0] rs3; + wire ready; + + modport master ( + output valid, + output wid, + output tmask, + output PC, + output ex_type, + output op_type, + output op_mod, + output wb, + output use_PC, + output use_imm, + output imm, + output rd, + output rs1, + output rs2, + output rs3, + input ready + ); + + modport slave ( + input valid, + input wid, + input tmask, + input PC, + input ex_type, + input op_type, + input op_mod, + input wb, + input use_PC, + input use_imm, + input imm, + input rd, + input rs1, + input rs2, + input rs3, + output ready + ); + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_decode_if.v b/hw/rtl/interfaces/VX_decode_if.v deleted file mode 100644 index c8465911..00000000 --- a/hw/rtl/interfaces/VX_decode_if.v +++ /dev/null @@ -1,28 +0,0 @@ -`ifndef VX_DECODE_IF -`define VX_DECODE_IF - -`include "VX_define.vh" - -interface VX_decode_if (); - - wire valid; - wire [`NW_BITS-1:0] wid; - wire [`NUM_THREADS-1:0] tmask; - wire [31:0] PC; - wire [`EX_BITS-1:0] ex_type; - wire [`OP_BITS-1:0] op_type; - wire [`MOD_BITS-1:0] op_mod; - wire wb; - wire [`NR_BITS-1:0] rd; - wire [`NR_BITS-1:0] rs1; - wire [`NR_BITS-1:0] rs2; - wire [`NR_BITS-1:0] rs3; - wire [31:0] imm; - wire use_PC; - wire use_imm; - wire [`NUM_REGS-1:0] used_regs; - wire ready; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_fetch_to_csr_if.sv b/hw/rtl/interfaces/VX_fetch_to_csr_if.sv new file mode 100644 index 00000000..1c2e3ddb --- /dev/null +++ b/hw/rtl/interfaces/VX_fetch_to_csr_if.sv @@ -0,0 +1,20 @@ +`ifndef VX_FETCH_TO_CSR_IF +`define VX_FETCH_TO_CSR_IF + +`include "VX_define.vh" + +interface VX_fetch_to_csr_if (); + + wire [`NUM_WARPS-1:0][`NUM_THREADS-1:0] thread_masks; + + modport master ( + output thread_masks + ); + + modport slave ( + input thread_masks + ); + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_fpu_req_if.sv b/hw/rtl/interfaces/VX_fpu_req_if.sv new file mode 100644 index 00000000..25867e42 --- /dev/null +++ b/hw/rtl/interfaces/VX_fpu_req_if.sv @@ -0,0 +1,53 @@ +`ifndef VX_FPU_REQ_IF +`define VX_FPU_REQ_IF + +`include "VX_define.vh" + +interface VX_fpu_req_if (); + + wire valid; + wire [`NW_BITS-1:0] wid; + wire [`NUM_THREADS-1:0] tmask; + wire [31:0] PC; + wire [`INST_FPU_BITS-1:0] op_type; + wire [`INST_MOD_BITS-1:0] op_mod; + wire [`NUM_THREADS-1:0][31:0] rs1_data; + wire [`NUM_THREADS-1:0][31:0] rs2_data; + wire [`NUM_THREADS-1:0][31:0] rs3_data; + wire [`NR_BITS-1:0] rd; + wire wb; + wire ready; + + modport master ( + output valid, + output wid, + output tmask, + output PC, + output op_type, + output op_mod, + output rs1_data, + output rs2_data, + output rs3_data, + output rd, + output wb, + input ready + ); + + modport slave ( + input valid, + input wid, + input tmask, + input PC, + input op_type, + input op_mod, + input rs1_data, + input rs2_data, + input rs3_data, + input rd, + input wb, + output ready + ); + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_fpu_req_if.v b/hw/rtl/interfaces/VX_fpu_req_if.v deleted file mode 100644 index a569e059..00000000 --- a/hw/rtl/interfaces/VX_fpu_req_if.v +++ /dev/null @@ -1,27 +0,0 @@ -`ifndef VX_FPU_REQ_IF -`define VX_FPU_REQ_IF - -`include "VX_define.vh" - -`ifndef EXTF_F_ENABLE - `IGNORE_WARNINGS_BEGIN -`endif - -interface VX_fpu_req_if (); - - wire valid; - wire [`NW_BITS-1:0] wid; - wire [`NUM_THREADS-1:0] tmask; - wire [31:0] PC; - wire [`FPU_BITS-1:0] op_type; - wire [`MOD_BITS-1:0] op_mod; - wire [`NUM_THREADS-1:0][31:0] rs1_data; - wire [`NUM_THREADS-1:0][31:0] rs2_data; - wire [`NUM_THREADS-1:0][31:0] rs3_data; - wire [`NR_BITS-1:0] rd; - wire wb; - wire ready; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_fpu_to_csr_if.sv b/hw/rtl/interfaces/VX_fpu_to_csr_if.sv new file mode 100644 index 00000000..62fe9628 --- /dev/null +++ b/hw/rtl/interfaces/VX_fpu_to_csr_if.sv @@ -0,0 +1,33 @@ +`ifndef VX_FPU_TO_CSR_IF +`define VX_FPU_TO_CSR_IF + +`include "VX_define.vh" + +interface VX_fpu_to_csr_if (); + + wire write_enable; + wire [`NW_BITS-1:0] write_wid; + fpu_types::fflags_t write_fflags; + + wire [`NW_BITS-1:0] read_wid; + wire [`INST_FRM_BITS-1:0] read_frm; + + modport master ( + output write_enable, + output write_wid, + output write_fflags, + output read_wid, + input read_frm + ); + + modport slave ( + input write_enable, + input write_wid, + input write_fflags, + input read_wid, + output read_frm + ); + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_fpu_to_csr_if.v b/hw/rtl/interfaces/VX_fpu_to_csr_if.v deleted file mode 100644 index cd101820..00000000 --- a/hw/rtl/interfaces/VX_fpu_to_csr_if.v +++ /dev/null @@ -1,17 +0,0 @@ -`ifndef VX_FPU_TO_CSR_IF -`define VX_FPU_TO_CSR_IF - -`include "VX_define.vh" - -interface VX_fpu_to_csr_if (); - - wire write_enable; - wire [`NW_BITS-1:0] write_wid; - fflags_t write_fflags; - - wire [`NW_BITS-1:0] read_wid; - wire [`FRM_BITS-1:0] read_frm; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_gpr_req_if.sv b/hw/rtl/interfaces/VX_gpr_req_if.sv new file mode 100644 index 00000000..d34448f4 --- /dev/null +++ b/hw/rtl/interfaces/VX_gpr_req_if.sv @@ -0,0 +1,29 @@ +`ifndef VX_GPR_REQ_IF +`define VX_GPR_REQ_IF + +`include "VX_define.vh" + +interface VX_gpr_req_if (); + + wire [`NW_BITS-1:0] wid; + wire [`NR_BITS-1:0] rs1; + wire [`NR_BITS-1:0] rs2; + wire [`NR_BITS-1:0] rs3; + + modport master ( + output wid, + output rs1, + output rs2, + output rs3 + ); + + modport slave ( + input wid, + input rs1, + input rs2, + input rs3 + ); + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_gpr_req_if.v b/hw/rtl/interfaces/VX_gpr_req_if.v deleted file mode 100644 index 0f818ed7..00000000 --- a/hw/rtl/interfaces/VX_gpr_req_if.v +++ /dev/null @@ -1,15 +0,0 @@ -`ifndef VX_GPR_REQ_IF -`define VX_GPR_REQ_IF - -`include "VX_define.vh" - -interface VX_gpr_req_if (); - - wire [`NW_BITS-1:0] wid; - wire [`NR_BITS-1:0] rs1; - wire [`NR_BITS-1:0] rs2; - wire [`NR_BITS-1:0] rs3; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_gpr_rsp_if.v b/hw/rtl/interfaces/VX_gpr_rsp_if.sv similarity index 56% rename from hw/rtl/interfaces/VX_gpr_rsp_if.v rename to hw/rtl/interfaces/VX_gpr_rsp_if.sv index b8e6f0df..c323555c 100644 --- a/hw/rtl/interfaces/VX_gpr_rsp_if.v +++ b/hw/rtl/interfaces/VX_gpr_rsp_if.sv @@ -9,6 +9,18 @@ interface VX_gpr_rsp_if (); wire [`NUM_THREADS-1:0][31:0] rs2_data; wire [`NUM_THREADS-1:0][31:0] rs3_data; + modport master ( + output rs1_data, + output rs2_data, + output rs3_data + ); + + modport slave ( + input rs1_data, + input rs2_data, + input rs3_data + ); + endinterface `endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_gpu_req_if.sv b/hw/rtl/interfaces/VX_gpu_req_if.sv new file mode 100644 index 00000000..e3511043 --- /dev/null +++ b/hw/rtl/interfaces/VX_gpu_req_if.sv @@ -0,0 +1,55 @@ +`ifndef VX_GPU_REQ_IF +`define VX_GPU_REQ_IF + +`include "VX_define.vh" + +interface VX_gpu_req_if(); + + wire valid; + + wire [`NW_BITS-1:0] wid; + wire [`NUM_THREADS-1:0] tmask; + wire [31:0] PC; + wire [31:0] next_PC; + wire [`INST_GPU_BITS-1:0] op_type; + wire [`NT_BITS-1:0] tid; + wire [`NUM_THREADS-1:0][31:0] rs1_data; + wire [31:0] rs2_data; + wire [`NR_BITS-1:0] rd; + wire wb; + + wire ready; + + modport master ( + output valid, + output wid, + output tmask, + output PC, + output next_PC, + output op_type, + output tid, + output rs1_data, + output rs2_data, + output rd, + output wb, + input ready + ); + + modport slave ( + input valid, + input wid, + input tmask, + input PC, + input next_PC, + input op_type, + input tid, + input rs1_data, + input rs2_data, + input rd, + input wb, + output ready + ); + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_gpu_req_if.v b/hw/rtl/interfaces/VX_gpu_req_if.v deleted file mode 100644 index 499358d2..00000000 --- a/hw/rtl/interfaces/VX_gpu_req_if.v +++ /dev/null @@ -1,26 +0,0 @@ -`ifndef VX_GPU_REQ_IF -`define VX_GPU_REQ_IF - -`include "VX_define.vh" - -interface VX_gpu_req_if(); - - wire valid; - - wire [`NW_BITS-1:0] wid; - wire [`NUM_THREADS-1:0] tmask; - wire [31:0] PC; - wire [31:0] next_PC; - wire [`GPU_BITS-1:0] op_type; - wire [`MOD_BITS-1:0] op_mod; - wire [`NUM_THREADS-1:0][31:0] rs1_data; - wire [`NUM_THREADS-1:0][31:0] rs2_data; - wire [`NUM_THREADS-1:0][31:0] rs3_data; - wire [`NR_BITS-1:0] rd; - wire wb; - - wire ready; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_ibuffer_if.sv b/hw/rtl/interfaces/VX_ibuffer_if.sv new file mode 100644 index 00000000..45569371 --- /dev/null +++ b/hw/rtl/interfaces/VX_ibuffer_if.sv @@ -0,0 +1,96 @@ +`ifndef VX_IBUFFER_IF +`define VX_IBUFFER_IF + +`include "VX_define.vh" + +interface VX_ibuffer_if (); + + wire valid; + wire [`NW_BITS-1:0] wid; + wire [`NUM_THREADS-1:0] tmask; + wire [31:0] PC; + wire [`EX_BITS-1:0] ex_type; + wire [`INST_OP_BITS-1:0] op_type; + wire [`INST_MOD_BITS-1:0] op_mod; + wire wb; + wire use_PC; + wire use_imm; + wire [31:0] imm; + wire [`NR_BITS-1:0] rd; + wire [`NR_BITS-1:0] rs1; + wire [`NR_BITS-1:0] rs2; + wire [`NR_BITS-1:0] rs3; + + wire [`NR_BITS-1:0] rd_n; + wire [`NR_BITS-1:0] rs1_n; + wire [`NR_BITS-1:0] rs2_n; + wire [`NR_BITS-1:0] rs3_n; + wire [`NW_BITS-1:0] wid_n; + + wire ready; + + modport master ( + output valid, + output wid, + output tmask, + output PC, + output ex_type, + output op_type, + output op_mod, + output wb, + output use_PC, + output use_imm, + output imm, + output rd, + output rs1, + output rs2, + output rs3, + output rd_n, + output rs1_n, + output rs2_n, + output rs3_n, + output wid_n, + input ready + ); + + modport slave ( + input valid, + input wid, + input tmask, + input PC, + input ex_type, + input op_type, + input op_mod, + input wb, + input use_PC, + input use_imm, + input imm, + input rd, + input rs1, + input rs2, + input rs3, + input rd_n, + input rs1_n, + input rs2_n, + input rs3_n, + input wid_n, + output ready + ); + + modport scoreboard ( + input valid, + input wid, + input PC, + input wb, + input rd, + input rd_n, + input rs1_n, + input rs2_n, + input rs3_n, + input wid_n, + output ready + ); + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_ibuffer_if.v b/hw/rtl/interfaces/VX_ibuffer_if.v deleted file mode 100644 index 30f93026..00000000 --- a/hw/rtl/interfaces/VX_ibuffer_if.v +++ /dev/null @@ -1,29 +0,0 @@ -`ifndef VX_IBUFFER_IF -`define VX_IBUFFER_IF - -`include "VX_define.vh" - -interface VX_ibuffer_if (); - - wire valid; - wire [`NW_BITS-1:0] wid; - wire [`NW_BITS-1:0] wid_n; - wire [`NUM_THREADS-1:0] tmask; - wire [31:0] PC; - wire [`EX_BITS-1:0] ex_type; - wire [`OP_BITS-1:0] op_type; - wire [`MOD_BITS-1:0] op_mod; - wire wb; - wire [`NR_BITS-1:0] rd; - wire [`NR_BITS-1:0] rs1; - wire [`NR_BITS-1:0] rs2; - wire [`NR_BITS-1:0] rs3; - wire [31:0] imm; - wire use_PC; - wire use_imm; - wire [`NUM_REGS-1:0] used_regs; - wire ready; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_icache_req_if.v b/hw/rtl/interfaces/VX_icache_req_if.sv similarity index 62% rename from hw/rtl/interfaces/VX_icache_req_if.v rename to hw/rtl/interfaces/VX_icache_req_if.sv index c60632f3..1decc6a5 100644 --- a/hw/rtl/interfaces/VX_icache_req_if.v +++ b/hw/rtl/interfaces/VX_icache_req_if.sv @@ -13,6 +13,20 @@ interface VX_icache_req_if #( wire [TAG_WIDTH-1:0] tag; wire ready; + modport master ( + output valid, + output addr, + output tag, + input ready + ); + + modport slave ( + input valid, + input addr, + input tag, + output ready + ); + endinterface `endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_icache_rsp_if.v b/hw/rtl/interfaces/VX_icache_rsp_if.sv similarity index 55% rename from hw/rtl/interfaces/VX_icache_rsp_if.v rename to hw/rtl/interfaces/VX_icache_rsp_if.sv index 9bab8b72..71cee32b 100644 --- a/hw/rtl/interfaces/VX_icache_rsp_if.v +++ b/hw/rtl/interfaces/VX_icache_rsp_if.sv @@ -11,7 +11,21 @@ interface VX_icache_rsp_if #( wire valid; wire [`WORD_WIDTH-1:0] data; wire [TAG_WIDTH-1:0] tag; - wire ready; + wire ready; + + modport master ( + output valid, + output data, + output tag, + input ready + ); + + modport slave ( + input valid, + input data, + input tag, + output ready + ); endinterface diff --git a/hw/rtl/interfaces/VX_ifetch_req_if.v b/hw/rtl/interfaces/VX_ifetch_req_if.sv similarity index 53% rename from hw/rtl/interfaces/VX_ifetch_req_if.v rename to hw/rtl/interfaces/VX_ifetch_req_if.sv index b99ed5da..3d75e736 100644 --- a/hw/rtl/interfaces/VX_ifetch_req_if.v +++ b/hw/rtl/interfaces/VX_ifetch_req_if.sv @@ -11,6 +11,22 @@ interface VX_ifetch_req_if (); wire [31:0] PC; wire ready; + modport master ( + output valid, + output tmask, + output wid, + output PC, + input ready + ); + + modport slave ( + input valid, + input tmask, + input wid, + input PC, + output ready + ); + endinterface `endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_ifetch_rsp_if.v b/hw/rtl/interfaces/VX_ifetch_rsp_if.sv similarity index 51% rename from hw/rtl/interfaces/VX_ifetch_rsp_if.v rename to hw/rtl/interfaces/VX_ifetch_rsp_if.sv index 78706577..a2f04fe4 100644 --- a/hw/rtl/interfaces/VX_ifetch_rsp_if.v +++ b/hw/rtl/interfaces/VX_ifetch_rsp_if.sv @@ -12,6 +12,24 @@ interface VX_ifetch_rsp_if (); wire [31:0] data; wire ready; + modport master ( + output valid, + output tmask, + output wid, + output PC, + output data, + input ready + ); + + modport slave ( + input valid, + input tmask, + input wid, + input PC, + input data, + output ready + ); + endinterface `endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_join_if.v b/hw/rtl/interfaces/VX_join_if.sv similarity index 54% rename from hw/rtl/interfaces/VX_join_if.v rename to hw/rtl/interfaces/VX_join_if.sv index 0ee163ab..d39ed9c0 100644 --- a/hw/rtl/interfaces/VX_join_if.v +++ b/hw/rtl/interfaces/VX_join_if.sv @@ -8,6 +8,16 @@ interface VX_join_if (); wire valid; wire [`NW_BITS-1:0] wid; + modport master ( + output valid, + output wid + ); + + modport slave ( + input valid, + input wid + ); + endinterface `endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_lsu_req_if.sv b/hw/rtl/interfaces/VX_lsu_req_if.sv new file mode 100644 index 00000000..36b4e778 --- /dev/null +++ b/hw/rtl/interfaces/VX_lsu_req_if.sv @@ -0,0 +1,53 @@ +`ifndef VX_LSU_REQ_IF +`define VX_LSU_REQ_IF + +`include "VX_define.vh" + +interface VX_lsu_req_if (); + + wire valid; + wire [`NW_BITS-1:0] wid; + wire [`NUM_THREADS-1:0] tmask; + wire [31:0] PC; + wire [`INST_LSU_BITS-1:0] op_type; + wire is_fence; + wire [`NUM_THREADS-1:0][31:0] store_data; + wire [`NUM_THREADS-1:0][31:0] base_addr; + wire [31:0] offset; + wire [`NR_BITS-1:0] rd; + wire wb; + wire ready; + + modport master ( + output valid, + output wid, + output tmask, + output PC, + output op_type, + output is_fence, + output store_data, + output base_addr, + output offset, + output rd, + output wb, + input ready + ); + + modport slave ( + input valid, + input wid, + input tmask, + input PC, + input op_type, + input is_fence, + input store_data, + input base_addr, + input offset, + input rd, + input wb, + output ready + ); + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_lsu_req_if.v b/hw/rtl/interfaces/VX_lsu_req_if.v deleted file mode 100644 index c9797b0f..00000000 --- a/hw/rtl/interfaces/VX_lsu_req_if.v +++ /dev/null @@ -1,23 +0,0 @@ -`ifndef VX_LSU_REQ_IF -`define VX_LSU_REQ_IF - -`include "VX_define.vh" - -interface VX_lsu_req_if (); - - wire valid; - wire [`NW_BITS-1:0] wid; - wire [`NUM_THREADS-1:0] tmask; - wire [31:0] PC; - wire [`LSU_BITS-1:0] op_type; - wire is_fence; - wire [`NUM_THREADS-1:0][31:0] store_data; - wire [`NUM_THREADS-1:0][31:0] base_addr; - wire [31:0] offset; - wire [`NR_BITS-1:0] rd; - wire wb; - wire ready; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_mem_req_if.v b/hw/rtl/interfaces/VX_mem_req_if.sv similarity index 59% rename from hw/rtl/interfaces/VX_mem_req_if.v rename to hw/rtl/interfaces/VX_mem_req_if.sv index a1a9040f..50bde8a2 100644 --- a/hw/rtl/interfaces/VX_mem_req_if.v +++ b/hw/rtl/interfaces/VX_mem_req_if.sv @@ -18,6 +18,26 @@ interface VX_mem_req_if #( wire [TAG_WIDTH-1:0] tag; wire ready; + modport master ( + output valid, + output rw, + output byteen, + output addr, + output data, + output tag, + input ready + ); + + modport slave ( + input valid, + input rw, + input byteen, + input addr, + input data, + input tag, + output ready + ); + endinterface `endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_mem_rsp_if.v b/hw/rtl/interfaces/VX_mem_rsp_if.sv similarity index 53% rename from hw/rtl/interfaces/VX_mem_rsp_if.v rename to hw/rtl/interfaces/VX_mem_rsp_if.sv index afc19989..3ee69d88 100644 --- a/hw/rtl/interfaces/VX_mem_rsp_if.v +++ b/hw/rtl/interfaces/VX_mem_rsp_if.sv @@ -11,7 +11,21 @@ interface VX_mem_rsp_if #( wire valid; wire [DATA_WIDTH-1:0] data; wire [TAG_WIDTH-1:0] tag; - wire ready; + wire ready; + + modport master ( + output valid, + output data, + output tag, + input ready + ); + + modport slave ( + input valid, + input data, + input tag, + output ready + ); endinterface diff --git a/hw/rtl/interfaces/VX_perf_cache_if.sv b/hw/rtl/interfaces/VX_perf_cache_if.sv new file mode 100644 index 00000000..d9efb2cc --- /dev/null +++ b/hw/rtl/interfaces/VX_perf_cache_if.sv @@ -0,0 +1,41 @@ +`ifndef VX_PERF_CACHE_IF +`define VX_PERF_CACHE_IF + +`include "VX_define.vh" + +interface VX_perf_cache_if (); + + wire [`PERF_CTR_BITS-1:0] reads; + wire [`PERF_CTR_BITS-1:0] writes; + wire [`PERF_CTR_BITS-1:0] read_misses; + wire [`PERF_CTR_BITS-1:0] write_misses; + wire [`PERF_CTR_BITS-1:0] bank_stalls; + wire [`PERF_CTR_BITS-1:0] mshr_stalls; + wire [`PERF_CTR_BITS-1:0] pipe_stalls; + wire [`PERF_CTR_BITS-1:0] crsp_stalls; + + modport master ( + output reads, + output writes, + output read_misses, + output write_misses, + output bank_stalls, + output mshr_stalls, + output pipe_stalls, + output crsp_stalls + ); + + modport slave ( + input reads, + input writes, + input read_misses, + input write_misses, + input bank_stalls, + input mshr_stalls, + input pipe_stalls, + input crsp_stalls + ); + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_perf_cache_if.v b/hw/rtl/interfaces/VX_perf_cache_if.v deleted file mode 100644 index 35004368..00000000 --- a/hw/rtl/interfaces/VX_perf_cache_if.v +++ /dev/null @@ -1,19 +0,0 @@ -`ifndef VX_PERF_CACHE_IF -`define VX_PERF_CACHE_IF - -`include "VX_define.vh" - -interface VX_perf_cache_if (); - - wire [`PERF_CTR_BITS-1:0] reads; - wire [`PERF_CTR_BITS-1:0] writes; - wire [`PERF_CTR_BITS-1:0] read_misses; - wire [`PERF_CTR_BITS-1:0] write_misses; - wire [`PERF_CTR_BITS-1:0] bank_stalls; - wire [`PERF_CTR_BITS-1:0] mshr_stalls; - wire [`PERF_CTR_BITS-1:0] pipe_stalls; - wire [`PERF_CTR_BITS-1:0] crsp_stalls; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_perf_memsys_if.sv b/hw/rtl/interfaces/VX_perf_memsys_if.sv new file mode 100644 index 00000000..f0e27ed6 --- /dev/null +++ b/hw/rtl/interfaces/VX_perf_memsys_if.sv @@ -0,0 +1,77 @@ +`ifndef VX_PERF_MEMSYS_IF +`define VX_PERF_MEMSYS_IF + +`include "VX_define.vh" + +interface VX_perf_memsys_if (); + + wire [`PERF_CTR_BITS-1:0] icache_reads; + wire [`PERF_CTR_BITS-1:0] icache_read_misses; + wire [`PERF_CTR_BITS-1:0] icache_pipe_stalls; + wire [`PERF_CTR_BITS-1:0] icache_crsp_stalls; + + wire [`PERF_CTR_BITS-1:0] dcache_reads; + wire [`PERF_CTR_BITS-1:0] dcache_writes; + wire [`PERF_CTR_BITS-1:0] dcache_read_misses; + wire [`PERF_CTR_BITS-1:0] dcache_write_misses; + wire [`PERF_CTR_BITS-1:0] dcache_bank_stalls; + wire [`PERF_CTR_BITS-1:0] dcache_mshr_stalls; + wire [`PERF_CTR_BITS-1:0] dcache_pipe_stalls; + wire [`PERF_CTR_BITS-1:0] dcache_crsp_stalls; + + wire [`PERF_CTR_BITS-1:0] smem_reads; + wire [`PERF_CTR_BITS-1:0] smem_writes; + wire [`PERF_CTR_BITS-1:0] smem_bank_stalls; + + wire [`PERF_CTR_BITS-1:0] mem_reads; + wire [`PERF_CTR_BITS-1:0] mem_writes; + wire [`PERF_CTR_BITS-1:0] mem_stalls; + wire [`PERF_CTR_BITS-1:0] mem_latency; + + modport master ( + output icache_reads, + output icache_read_misses, + output icache_pipe_stalls, + output icache_crsp_stalls, + output dcache_reads, + output dcache_writes, + output dcache_read_misses, + output dcache_write_misses, + output dcache_bank_stalls, + output dcache_mshr_stalls, + output dcache_pipe_stalls, + output dcache_crsp_stalls, + output smem_reads, + output smem_writes, + output smem_bank_stalls, + output mem_reads, + output mem_writes, + output mem_stalls, + output mem_latency + ); + + modport slave ( + input icache_reads, + input icache_read_misses, + input icache_pipe_stalls, + input icache_crsp_stalls, + input dcache_reads, + input dcache_writes, + input dcache_read_misses, + input dcache_write_misses, + input dcache_bank_stalls, + input dcache_mshr_stalls, + input dcache_pipe_stalls, + input dcache_crsp_stalls, + input smem_reads, + input smem_writes, + input smem_bank_stalls, + input mem_reads, + input mem_writes, + input mem_stalls, + input mem_latency + ); + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_perf_memsys_if.v b/hw/rtl/interfaces/VX_perf_memsys_if.v deleted file mode 100644 index a2ef4835..00000000 --- a/hw/rtl/interfaces/VX_perf_memsys_if.v +++ /dev/null @@ -1,33 +0,0 @@ -`ifndef VX_PERF_MEMSYS_IF -`define VX_PERF_MEMSYS_IF - -`include "VX_define.vh" - -interface VX_perf_memsys_if (); - - wire [`PERF_CTR_BITS-1:0] icache_reads; - wire [`PERF_CTR_BITS-1:0] icache_read_misses; - wire [`PERF_CTR_BITS-1:0] icache_pipe_stalls; - wire [`PERF_CTR_BITS-1:0] icache_crsp_stalls; - - wire [`PERF_CTR_BITS-1:0] dcache_reads; - wire [`PERF_CTR_BITS-1:0] dcache_writes; - wire [`PERF_CTR_BITS-1:0] dcache_read_misses; - wire [`PERF_CTR_BITS-1:0] dcache_write_misses; - wire [`PERF_CTR_BITS-1:0] dcache_bank_stalls; - wire [`PERF_CTR_BITS-1:0] dcache_mshr_stalls; - wire [`PERF_CTR_BITS-1:0] dcache_pipe_stalls; - wire [`PERF_CTR_BITS-1:0] dcache_crsp_stalls; - - wire [`PERF_CTR_BITS-1:0] smem_reads; - wire [`PERF_CTR_BITS-1:0] smem_writes; - wire [`PERF_CTR_BITS-1:0] smem_bank_stalls; - - wire [`PERF_CTR_BITS-1:0] mem_reads; - wire [`PERF_CTR_BITS-1:0] mem_writes; - wire [`PERF_CTR_BITS-1:0] mem_stalls; - wire [`PERF_CTR_BITS-1:0] mem_latency; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_perf_pipeline_if.sv b/hw/rtl/interfaces/VX_perf_pipeline_if.sv new file mode 100644 index 00000000..19cc15c3 --- /dev/null +++ b/hw/rtl/interfaces/VX_perf_pipeline_if.sv @@ -0,0 +1,44 @@ +`ifndef VX_PERF_PIPELINE_IF +`define VX_PERF_PIPELINE_IF + +`include "VX_define.vh" + +interface VX_perf_pipeline_if (); + + wire [`PERF_CTR_BITS-1:0] ibf_stalls; + wire [`PERF_CTR_BITS-1:0] scb_stalls; + wire [`PERF_CTR_BITS-1:0] lsu_stalls; + wire [`PERF_CTR_BITS-1:0] csr_stalls; + wire [`PERF_CTR_BITS-1:0] alu_stalls; +`ifdef EXT_F_ENABLE + wire [`PERF_CTR_BITS-1:0] fpu_stalls; +`endif + wire [`PERF_CTR_BITS-1:0] gpu_stalls; + + modport master ( + output ibf_stalls, + output scb_stalls, + output lsu_stalls, + output csr_stalls, + output alu_stalls, + `ifdef EXT_F_ENABLE + output fpu_stalls, + `endif + output gpu_stalls + ); + + modport slave ( + input ibf_stalls, + input scb_stalls, + input lsu_stalls, + input csr_stalls, + input alu_stalls, + `ifdef EXT_F_ENABLE + input fpu_stalls, + `endif + input gpu_stalls + ); + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_perf_pipeline_if.v b/hw/rtl/interfaces/VX_perf_pipeline_if.v deleted file mode 100644 index 12d76d9c..00000000 --- a/hw/rtl/interfaces/VX_perf_pipeline_if.v +++ /dev/null @@ -1,18 +0,0 @@ -`ifndef VX_PERF_PIPELINE_IF -`define VX_PERF_PIPELINE_IF - -`include "VX_define.vh" - -interface VX_perf_pipeline_if (); - wire [`PERF_CTR_BITS-1:0] ibf_stalls; - wire [`PERF_CTR_BITS-1:0] scb_stalls; - wire [`PERF_CTR_BITS-1:0] lsu_stalls; - wire [`PERF_CTR_BITS-1:0] csr_stalls; - wire [`PERF_CTR_BITS-1:0] alu_stalls; - wire [`PERF_CTR_BITS-1:0] gpu_stalls; -`ifdef EXT_F_ENABLE - wire [`PERF_CTR_BITS-1:0] fpu_stalls; -`endif -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_tex_csr_if.v b/hw/rtl/interfaces/VX_tex_csr_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_tex_csr_if.v rename to hw/rtl/interfaces/VX_tex_csr_if.sv diff --git a/hw/rtl/interfaces/VX_tex_req_if.v b/hw/rtl/interfaces/VX_tex_req_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_tex_req_if.v rename to hw/rtl/interfaces/VX_tex_req_if.sv diff --git a/hw/rtl/interfaces/VX_tex_rsp_if.v b/hw/rtl/interfaces/VX_tex_rsp_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_tex_rsp_if.v rename to hw/rtl/interfaces/VX_tex_rsp_if.sv diff --git a/hw/rtl/interfaces/VX_warp_ctl_if.sv b/hw/rtl/interfaces/VX_warp_ctl_if.sv new file mode 100644 index 00000000..d38d29b1 --- /dev/null +++ b/hw/rtl/interfaces/VX_warp_ctl_if.sv @@ -0,0 +1,35 @@ +`ifndef VX_WARP_CTL_IF +`define VX_WARP_CTL_IF + +`include "VX_define.vh" + +interface VX_warp_ctl_if (); + + wire valid; + wire [`NW_BITS-1:0] wid; + gpu_types::gpu_tmc_t tmc; + gpu_types::gpu_wspawn_t wspawn; + gpu_types::gpu_barrier_t barrier; + gpu_types::gpu_split_t split; + + modport master ( + output valid, + output wid, + output tmc, + output wspawn, + output barrier, + output split + ); + + modport slave ( + input valid, + input wid, + input tmc, + input wspawn, + input barrier, + input split + ); + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_warp_ctl_if.v b/hw/rtl/interfaces/VX_warp_ctl_if.v deleted file mode 100644 index 2a53c714..00000000 --- a/hw/rtl/interfaces/VX_warp_ctl_if.v +++ /dev/null @@ -1,17 +0,0 @@ -`ifndef VX_WARP_CTL_IF -`define VX_WARP_CTL_IF - -`include "VX_define.vh" - -interface VX_warp_ctl_if (); - - wire valid; - wire [`NW_BITS-1:0] wid; - gpu_tmc_t tmc; - gpu_wspawn_t wspawn; - gpu_barrier_t barrier; - gpu_split_t split; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_writeback_if.sv b/hw/rtl/interfaces/VX_writeback_if.sv new file mode 100644 index 00000000..b3e2060d --- /dev/null +++ b/hw/rtl/interfaces/VX_writeback_if.sv @@ -0,0 +1,50 @@ +`ifndef VX_WRITEBACK_IF +`define VX_WRITEBACK_IF + +`include "VX_define.vh" + +interface VX_writeback_if (); + + wire valid; + wire [`NUM_THREADS-1:0] tmask; + wire [`NW_BITS-1:0] wid; + wire [31:0] PC; + wire [`NR_BITS-1:0] rd; + wire [`NUM_THREADS-1:0][31:0] data; + wire eop; + wire ready; + + modport master ( + output valid, + output tmask, + output wid, + output PC, + output rd, + output data, + output eop, + input ready + ); + + modport slave ( + input valid, + input tmask, + input wid, + input PC, + input rd, + input data, + input eop, + output ready + ); + + modport scoreboard ( + input valid, + input wid, + input PC, + input rd, + input eop, + output ready + ); + +endinterface + +`endif diff --git a/hw/rtl/interfaces/VX_writeback_if.v b/hw/rtl/interfaces/VX_writeback_if.v deleted file mode 100644 index 6e2c9cc3..00000000 --- a/hw/rtl/interfaces/VX_writeback_if.v +++ /dev/null @@ -1,23 +0,0 @@ -`ifndef VX_WRITEBACK_IF -`define VX_WRITEBACK_IF - -`include "VX_define.vh" - -interface VX_writeback_if (); - - wire valid; - - wire [`NUM_THREADS-1:0] tmask; - wire [`NW_BITS-1:0] wid; -`IGNORE_WARNINGS_BEGIN - wire [31:0] PC; -`IGNORE_WARNINGS_END - wire [`NR_BITS-1:0] rd; - wire [`NUM_THREADS-1:0][31:0] data; - - wire eop; - wire ready; - -endinterface - -`endif diff --git a/hw/rtl/interfaces/VX_wstall_if.sv b/hw/rtl/interfaces/VX_wstall_if.sv new file mode 100644 index 00000000..cff00327 --- /dev/null +++ b/hw/rtl/interfaces/VX_wstall_if.sv @@ -0,0 +1,26 @@ +`ifndef VX_WSTALL_IF +`define VX_WSTALL_IF + +`include "VX_define.vh" + +interface VX_wstall_if(); + + wire valid; + wire [`NW_BITS-1:0] wid; + wire stalled; + + modport master ( + output valid, + output wid, + output stalled + ); + + modport slave ( + input valid, + input wid, + input stalled + ); + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_wstall_if.v b/hw/rtl/interfaces/VX_wstall_if.v deleted file mode 100644 index b50d0711..00000000 --- a/hw/rtl/interfaces/VX_wstall_if.v +++ /dev/null @@ -1,13 +0,0 @@ -`ifndef VX_WSTALL_IF -`define VX_WSTALL_IF - -`include "VX_define.vh" - -interface VX_wstall_if(); - - wire valid; - wire [`NW_BITS-1:0] wid; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/libs/VX_axi_adapter.sv b/hw/rtl/libs/VX_axi_adapter.sv new file mode 100644 index 00000000..2788c315 --- /dev/null +++ b/hw/rtl/libs/VX_axi_adapter.sv @@ -0,0 +1,154 @@ +`include "VX_define.vh" + +module VX_axi_adapter #( + parameter VX_DATA_WIDTH = 512, + parameter VX_ADDR_WIDTH = (32 - $clog2(VX_DATA_WIDTH/8)), + parameter VX_TAG_WIDTH = 8, + parameter AXI_DATA_WIDTH = VX_DATA_WIDTH, + parameter AXI_ADDR_WIDTH = 32, + parameter AXI_TID_WIDTH = VX_TAG_WIDTH, + + parameter VX_BYTEEN_WIDTH = (VX_DATA_WIDTH / 8), + parameter AXI_STROBE_WIDTH = (AXI_DATA_WIDTH / 8) +) ( + input wire clk, + input wire reset, + + // Vortex request + input wire mem_req_valid, + input wire mem_req_rw, + input wire [VX_BYTEEN_WIDTH-1:0] mem_req_byteen, + input wire [VX_ADDR_WIDTH-1:0] mem_req_addr, + input wire [VX_DATA_WIDTH-1:0] mem_req_data, + input wire [VX_TAG_WIDTH-1:0] mem_req_tag, + + // Vortex response + input wire mem_rsp_ready, + output wire mem_rsp_valid, + output wire [VX_DATA_WIDTH-1:0] mem_rsp_data, + output wire [VX_TAG_WIDTH-1:0] mem_rsp_tag, + output wire mem_req_ready, + + // AXI write request address channel + output wire [AXI_TID_WIDTH-1:0] m_axi_awid, + output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr, + output wire [7:0] m_axi_awlen, + output wire [2:0] m_axi_awsize, + output wire [1:0] m_axi_awburst, + output wire m_axi_awlock, + output wire [3:0] m_axi_awcache, + output wire [2:0] m_axi_awprot, + output wire [3:0] m_axi_awqos, + output wire m_axi_awvalid, + input wire m_axi_awready, + + // AXI write request data channel + output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata, + output wire [AXI_STROBE_WIDTH-1:0] m_axi_wstrb, + output wire m_axi_wlast, + output wire m_axi_wvalid, + input wire m_axi_wready, + + // AXI write response channel + input wire [AXI_TID_WIDTH-1:0] m_axi_bid, + input wire [1:0] m_axi_bresp, + input wire m_axi_bvalid, + output wire m_axi_bready, + + // AXI read address channel + output wire [AXI_TID_WIDTH-1:0] m_axi_arid, + output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr, + output wire [7:0] m_axi_arlen, + output wire [2:0] m_axi_arsize, + output wire [1:0] m_axi_arburst, + output wire m_axi_arlock, + output wire [3:0] m_axi_arcache, + output wire [2:0] m_axi_arprot, + output wire [3:0] m_axi_arqos, + output wire m_axi_arvalid, + input wire m_axi_arready, + + // AXI read response channel + input wire [AXI_TID_WIDTH-1:0] m_axi_rid, + input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata, + input wire [1:0] m_axi_rresp, + input wire m_axi_rlast, + input wire m_axi_rvalid, + output wire m_axi_rready +); + localparam AXSIZE = $clog2(VX_DATA_WIDTH/8); + + `STATIC_ASSERT((AXI_DATA_WIDTH == VX_DATA_WIDTH), ("invalid parameter")) + `STATIC_ASSERT((AXI_TID_WIDTH == VX_TAG_WIDTH), ("invalid parameter")) + + //`UNUSED_VAR () + + reg awvalid_ack; + reg wvalid_ack; + + wire mem_req_fire = mem_req_valid && mem_req_ready; + + always @(posedge clk) begin + if (reset) begin + awvalid_ack <= 0; + wvalid_ack <= 0; + end else begin + if (mem_req_fire) begin + awvalid_ack <= 0; + wvalid_ack <= 0; + end else begin + awvalid_ack <= m_axi_awvalid && m_axi_awready; + wvalid_ack <= m_axi_wvalid && m_axi_wready; + end + end + end + + wire axi_write_ready = (m_axi_awready || awvalid_ack) && (m_axi_wready || wvalid_ack); + + // AXI write request address channel + assign m_axi_awvalid = mem_req_valid && mem_req_rw && !awvalid_ack; + assign m_axi_awid = mem_req_tag; + assign m_axi_awaddr = AXI_ADDR_WIDTH'(mem_req_addr) << AXSIZE; + assign m_axi_awlen = 8'b00000000; + assign m_axi_awsize = 3'(AXSIZE); + assign m_axi_awburst = 2'b00; + assign m_axi_awlock = 1'b0; + assign m_axi_awcache = 4'b0; + assign m_axi_awprot = 3'b0; + assign m_axi_awqos = 4'b0; + + // AXI write request data channel + assign m_axi_wvalid = mem_req_valid && mem_req_rw && !wvalid_ack; + assign m_axi_wdata = mem_req_data; + assign m_axi_wstrb = mem_req_byteen; + assign m_axi_wlast = 1'b1; + + // AXI write response channel + `UNUSED_VAR (m_axi_bid); + `RUNTIME_ASSERT(~m_axi_bvalid || m_axi_bresp == 0, ("AXI response error")); + assign m_axi_bready = 1'b1; + + // AXI read request channel + assign m_axi_arvalid = mem_req_valid && !mem_req_rw; + assign m_axi_arid = mem_req_tag; + assign m_axi_araddr = AXI_ADDR_WIDTH'(mem_req_addr) << AXSIZE; + assign m_axi_arlen = 8'b00000000; + assign m_axi_arsize = 3'(AXSIZE); + assign m_axi_arburst = 2'b00; + assign m_axi_arlock = 1'b0; + assign m_axi_arcache = 4'b0; + assign m_axi_arprot = 3'b0; + assign m_axi_arqos = 4'b0; + + // AXI read response channel + assign mem_rsp_valid = m_axi_rvalid; + assign mem_rsp_tag = m_axi_rid; + assign mem_rsp_data = m_axi_rdata; + `RUNTIME_ASSERT(~m_axi_rvalid || m_axi_rresp == 0, ("AXI response error")); + `UNUSED_VAR (m_axi_rlast); + assign m_axi_rready = mem_rsp_ready; + + // Vortex request ack + assign mem_req_ready = mem_req_rw ? axi_write_ready : m_axi_arready; + +endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_bits_insert.v b/hw/rtl/libs/VX_bits_insert.sv similarity index 100% rename from hw/rtl/libs/VX_bits_insert.v rename to hw/rtl/libs/VX_bits_insert.sv diff --git a/hw/rtl/libs/VX_bits_remove.v b/hw/rtl/libs/VX_bits_remove.sv similarity index 100% rename from hw/rtl/libs/VX_bits_remove.v rename to hw/rtl/libs/VX_bits_remove.sv diff --git a/hw/rtl/libs/VX_bypass_buffer.v b/hw/rtl/libs/VX_bypass_buffer.sv similarity index 95% rename from hw/rtl/libs/VX_bypass_buffer.v rename to hw/rtl/libs/VX_bypass_buffer.sv index 84fcfd98..efb5517f 100644 --- a/hw/rtl/libs/VX_bypass_buffer.v +++ b/hw/rtl/libs/VX_bypass_buffer.sv @@ -31,7 +31,7 @@ module VX_bypass_buffer #( buffer_valid <= 0; end if (valid_in && ~ready_out) begin - assert(!buffer_valid); + `ASSERT(!buffer_valid, ("runtime error")); buffer_valid <= 1; end end diff --git a/hw/rtl/libs/VX_divider.v b/hw/rtl/libs/VX_divider.sv similarity index 98% rename from hw/rtl/libs/VX_divider.v rename to hw/rtl/libs/VX_divider.sv index 5cb38cfa..d30c7993 100644 --- a/hw/rtl/libs/VX_divider.v +++ b/hw/rtl/libs/VX_divider.sv @@ -1,5 +1,6 @@ `include "VX_platform.vh" +`TRACING_OFF module VX_divider #( parameter WIDTHN = 1, parameter WIDTHD = 1, @@ -91,4 +92,5 @@ module VX_divider #( `endif -endmodule \ No newline at end of file +endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_dp_ram.sv b/hw/rtl/libs/VX_dp_ram.sv new file mode 100644 index 00000000..7b39246f --- /dev/null +++ b/hw/rtl/libs/VX_dp_ram.sv @@ -0,0 +1,252 @@ +`include "VX_platform.vh" + +`TRACING_OFF +module VX_dp_ram #( + parameter DATAW = 1, + parameter SIZE = 1, + parameter BYTEENW = 1, + parameter OUT_REG = 0, + parameter NO_RWCHECK = 0, + parameter LUTRAM = 0, + parameter ADDRW = $clog2(SIZE), + parameter INIT_ENABLE = 0, + parameter INIT_FILE = "", + parameter [DATAW-1:0] INIT_VALUE = 0 +) ( + input wire clk, + input wire [BYTEENW-1:0] wren, + input wire [ADDRW-1:0] waddr, + input wire [DATAW-1:0] wdata, + input wire [ADDRW-1:0] raddr, + output wire [DATAW-1:0] rdata +); + + `STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter")) + +`define RAM_INITIALIZATION \ + if (INIT_ENABLE) begin \ + if (INIT_FILE != "") begin \ + initial $readmemh(INIT_FILE, ram); \ + end else begin \ + initial \ + for (integer i = 0; i < SIZE; ++i)\ + ram[i] = INIT_VALUE; \ + end \ + end + +`ifdef SYNTHESIS + if (LUTRAM) begin + if (OUT_REG) begin + reg [DATAW-1:0] rdata_r; + if (BYTEENW > 1) begin + `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + for (integer i = 0; i < BYTEENW; i++) begin + if (wren[i]) + ram[waddr][i] <= wdata[i * 8 +: 8]; + end + rdata_r <= ram[raddr]; + end + end else begin + `USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0]; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + if (wren) + ram[waddr] <= wdata; + rdata_r <= ram[raddr]; + end + end + assign rdata = rdata_r; + end else begin + if (BYTEENW > 1) begin + `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + for (integer i = 0; i < BYTEENW; i++) begin + if (wren[i]) + ram[waddr][i] <= wdata[i * 8 +: 8]; + end + end + assign rdata = ram[raddr]; + end else begin + `USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0]; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + if (wren) + ram[waddr] <= wdata; + end + assign rdata = ram[raddr]; + end + end + end else begin + if (OUT_REG) begin + reg [DATAW-1:0] rdata_r; + + if (BYTEENW > 1) begin + reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + for (integer i = 0; i < BYTEENW; i++) begin + if (wren[i]) + ram[waddr][i] <= wdata[i * 8 +: 8]; + end + rdata_r <= ram[raddr]; + end + end else begin + reg [DATAW-1:0] ram [SIZE-1:0]; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + if (wren) + ram[waddr] <= wdata; + rdata_r <= ram[raddr]; + end + end + assign rdata = rdata_r; + end else begin + if (NO_RWCHECK) begin + if (BYTEENW > 1) begin + `NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + for (integer i = 0; i < BYTEENW; i++) begin + if (wren[i]) + ram[waddr][i] <= wdata[i * 8 +: 8]; + end + end + assign rdata = ram[raddr]; + end else begin + `NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0]; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + if (wren) + ram[waddr] <= wdata; + end + assign rdata = ram[raddr]; + end + end else begin + if (BYTEENW > 1) begin + reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + for (integer i = 0; i < BYTEENW; i++) begin + if (wren[i]) + ram[waddr][i] <= wdata[i * 8 +: 8]; + end + end + assign rdata = ram[raddr]; + end else begin + reg [DATAW-1:0] ram [SIZE-1:0]; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + if (wren) + ram[waddr] <= wdata; + end + assign rdata = ram[raddr]; + end + end + end + end +`else + if (OUT_REG) begin + reg [DATAW-1:0] rdata_r; + if (BYTEENW > 1) begin + reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + for (integer i = 0; i < BYTEENW; i++) begin + if (wren[i]) + ram[waddr][i] <= wdata[i * 8 +: 8]; + end + rdata_r <= ram[raddr]; + end + end else begin + reg [DATAW-1:0] ram [SIZE-1:0]; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + if (wren) + ram[waddr] <= wdata; + rdata_r <= ram[raddr]; + end + end + assign rdata = rdata_r; + end else begin + if (BYTEENW > 1) begin + reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; + reg [DATAW-1:0] prev_data; + reg [ADDRW-1:0] prev_waddr; + reg prev_write; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + for (integer i = 0; i < BYTEENW; i++) begin + if (wren[i]) + ram[waddr][i] <= wdata[i * 8 +: 8]; + end + prev_write <= (| wren); + prev_data <= ram[waddr]; + prev_waddr <= waddr; + end + + if (LUTRAM || !NO_RWCHECK) begin + `UNUSED_VAR (prev_write) + `UNUSED_VAR (prev_data) + `UNUSED_VAR (prev_waddr) + assign rdata = ram[raddr]; + end else begin + assign rdata = (prev_write && (prev_waddr == raddr)) ? prev_data : ram[raddr]; + end + end else begin + reg [DATAW-1:0] ram [SIZE-1:0]; + reg [DATAW-1:0] prev_data; + reg [ADDRW-1:0] prev_waddr; + reg prev_write; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + if (wren) + ram[waddr] <= wdata; + prev_write <= wren; + prev_data <= ram[waddr]; + prev_waddr <= waddr; + end + if (LUTRAM || !NO_RWCHECK) begin + `UNUSED_VAR (prev_write) + `UNUSED_VAR (prev_data) + `UNUSED_VAR (prev_waddr) + assign rdata = ram[raddr]; + end else begin + assign rdata = (prev_write && (prev_waddr == raddr)) ? prev_data : ram[raddr]; + end + end + end +`endif + +endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_dp_ram.v b/hw/rtl/libs/VX_dp_ram.v deleted file mode 100644 index c1f3796b..00000000 --- a/hw/rtl/libs/VX_dp_ram.v +++ /dev/null @@ -1,199 +0,0 @@ -`include "VX_platform.vh" - -`TRACING_OFF -module VX_dp_ram #( - parameter DATAW = 1, - parameter SIZE = 1, - parameter BYTEENW = 1, - parameter OUTPUT_REG = 0, - parameter RWCHECK = 1, - parameter ADDRW = $clog2(SIZE), - parameter FASTRAM = 0, - parameter INITZERO = 0 -) ( - input wire clk, - input wire [ADDRW-1:0] waddr, - input wire [ADDRW-1:0] raddr, - input wire wren, - input wire [BYTEENW-1:0] byteen, - input wire rden, - input wire [DATAW-1:0] din, - output wire [DATAW-1:0] dout -); - - `STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter")) - - if (FASTRAM) begin - if (OUTPUT_REG) begin - reg [DATAW-1:0] dout_r; - - if (BYTEENW > 1) begin - `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; - - if (INITZERO) begin - initial mem = '{default: 0}; - end - - always @(posedge clk) begin - if (wren) begin - for (integer i = 0; i < BYTEENW; i++) begin - if (byteen[i]) - mem[waddr][i] <= din[i * 8 +: 8]; - end - end - if (rden) - dout_r <= mem[raddr]; - end - end else begin - `USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0]; - - if (INITZERO) begin - initial mem = '{default: 0}; - end - - always @(posedge clk) begin - if (wren && byteen) - mem[waddr] <= din; - if (rden) - dout_r <= mem[raddr]; - end - end - assign dout = dout_r; - end else begin - `UNUSED_VAR (rden) - - if (BYTEENW > 1) begin - `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; - - if (INITZERO) begin - initial mem = '{default: 0}; - end - - always @(posedge clk) begin - if (wren) begin - for (integer i = 0; i < BYTEENW; i++) begin - if (byteen[i]) - mem[waddr][i] <= din[i * 8 +: 8]; - end - end - end - assign dout = mem[raddr]; - end else begin - `USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0]; - - if (INITZERO) begin - initial mem = '{default: 0}; - end - - always @(posedge clk) begin - if (wren && byteen) - mem[waddr] <= din; - end - assign dout = mem[raddr]; - end - end - end else begin - if (OUTPUT_REG) begin - reg [DATAW-1:0] dout_r; - - if (BYTEENW > 1) begin - reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; - - if (INITZERO) begin - initial mem = '{default: 0}; - end - - always @(posedge clk) begin - if (wren) begin - for (integer i = 0; i < BYTEENW; i++) begin - if (byteen[i]) - mem[waddr][i] <= din[i * 8 +: 8]; - end - end - if (rden) - dout_r <= mem[raddr]; - end - end else begin - reg [DATAW-1:0] mem [SIZE-1:0]; - - if (INITZERO) begin - initial mem = '{default: 0}; - end - - always @(posedge clk) begin - if (wren && byteen) - mem[waddr] <= din; - if (rden) - dout_r <= mem[raddr]; - end - end - assign dout = dout_r; - end else begin - `UNUSED_VAR (rden) - - if (RWCHECK) begin - if (BYTEENW > 1) begin - reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; - - if (INITZERO) begin - initial mem = '{default: 0}; - end - - always @(posedge clk) begin - if (wren) begin - for (integer i = 0; i < BYTEENW; i++) begin - if (byteen[i]) - mem[waddr][i] <= din[i * 8 +: 8]; - end - end - end - assign dout = mem[raddr]; - end else begin - reg [DATAW-1:0] mem [SIZE-1:0]; - - if (INITZERO) begin - initial mem = '{default: 0}; - end - - always @(posedge clk) begin - if (wren && byteen) - mem[waddr] <= din; - end - assign dout = mem[raddr]; - end - end else begin - if (BYTEENW > 1) begin - `NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; - - if (INITZERO) begin - initial mem = '{default: 0}; - end - - always @(posedge clk) begin - if (wren) begin - for (integer i = 0; i < BYTEENW; i++) begin - if (byteen[i]) - mem[waddr][i] <= din[i * 8 +: 8]; - end - end - end - assign dout = mem[raddr]; - end else begin - `NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0]; - - if (INITZERO) begin - initial mem = '{default: 0}; - end - - always @(posedge clk) begin - if (wren && byteen) - mem[waddr] <= din; - end - assign dout = mem[raddr]; - end - end - end - end - -endmodule -`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_elastic_buffer.v b/hw/rtl/libs/VX_elastic_buffer.sv similarity index 82% rename from hw/rtl/libs/VX_elastic_buffer.v rename to hw/rtl/libs/VX_elastic_buffer.sv index 844b65a3..4eb5dc90 100644 --- a/hw/rtl/libs/VX_elastic_buffer.v +++ b/hw/rtl/libs/VX_elastic_buffer.sv @@ -1,10 +1,11 @@ `include "VX_platform.vh" +`TRACING_OFF module VX_elastic_buffer #( - parameter DATAW = 1, - parameter SIZE = 2, - parameter OUTPUT_REG = 0, - parameter FASTRAM = 0 + parameter DATAW = 1, + parameter SIZE = 2, + parameter OUT_REG = 0, + parameter LUTRAM = 0 ) ( input wire clk, input wire reset, @@ -31,8 +32,8 @@ module VX_elastic_buffer #( end else if (SIZE == 2) begin VX_skid_buffer #( - .DATAW (DATAW), - .OUTPUT_REG (OUTPUT_REG) + .DATAW (DATAW), + .OUT_REG (OUT_REG) ) queue ( .clk (clk), .reset (reset), @@ -52,10 +53,10 @@ module VX_elastic_buffer #( wire pop = valid_out && ready_out; VX_fifo_queue #( - .DATAW (DATAW), - .SIZE (SIZE), - .OUTPUT_REG (OUTPUT_REG), - .FASTRAM (FASTRAM) + .DATAW (DATAW), + .SIZE (SIZE), + .OUT_REG (OUT_REG), + .LUTRAM (LUTRAM) ) queue ( .clk (clk), .reset (reset), @@ -75,4 +76,5 @@ module VX_elastic_buffer #( end -endmodule \ No newline at end of file +endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_fair_arbiter.v b/hw/rtl/libs/VX_fair_arbiter.sv similarity index 73% rename from hw/rtl/libs/VX_fair_arbiter.v rename to hw/rtl/libs/VX_fair_arbiter.sv index 67e4b0dd..0e24efd5 100644 --- a/hw/rtl/libs/VX_fair_arbiter.v +++ b/hw/rtl/libs/VX_fair_arbiter.sv @@ -1,5 +1,6 @@ `include "VX_platform.vh" +`TRACING_OFF module VX_fair_arbiter #( parameter NUM_REQS = 1, parameter LOCK_ENABLE = 0, @@ -24,30 +25,31 @@ module VX_fair_arbiter #( end else begin - reg [NUM_REQS-1:0] remaining; + reg [NUM_REQS-1:0] buffer; reg use_buffer; - wire [NUM_REQS-1:0] requests_use = use_buffer ? remaining : requests; - wire [NUM_REQS-1:0] remaining_next = requests_use & ~grant_onehot; + wire [NUM_REQS-1:0] requests_qual = use_buffer ? buffer : requests; + wire [NUM_REQS-1:0] buffer_n = requests_qual & ~grant_onehot; always @(posedge clk) begin if (reset) begin - remaining <= 0; use_buffer <= 0; end else if (!LOCK_ENABLE || enable) begin - remaining <= remaining_next; - use_buffer <= (remaining_next != 0); + use_buffer <= (buffer_n != 0); + end + if (!LOCK_ENABLE || enable) begin + buffer <= buffer_n; end end VX_fixed_arbiter #( - .NUM_REQS(NUM_REQS), - .LOCK_ENABLE(LOCK_ENABLE) + .NUM_REQS (NUM_REQS), + .LOCK_ENABLE (LOCK_ENABLE) ) fixed_arbiter ( .clk (clk), .reset (reset), .enable (enable), - .requests (requests_use), + .requests (requests_qual), .grant_index (grant_index), .grant_onehot (grant_onehot), .grant_valid (grant_valid) @@ -55,3 +57,4 @@ module VX_fair_arbiter #( end endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_fifo_queue.v b/hw/rtl/libs/VX_fifo_queue.sv similarity index 79% rename from hw/rtl/libs/VX_fifo_queue.v rename to hw/rtl/libs/VX_fifo_queue.sv index 5ecdeb82..42f36885 100644 --- a/hw/rtl/libs/VX_fifo_queue.v +++ b/hw/rtl/libs/VX_fifo_queue.sv @@ -1,14 +1,15 @@ `include "VX_platform.vh" +`TRACING_OFF module VX_fifo_queue #( - parameter DATAW = 1, - parameter SIZE = 2, - parameter ALM_FULL = (SIZE - 1), - parameter ALM_EMPTY = 1, - parameter ADDRW = $clog2(SIZE), - parameter SIZEW = $clog2(SIZE+1), - parameter OUTPUT_REG = 0, - parameter FASTRAM = 1 + parameter DATAW = 1, + parameter SIZE = 2, + parameter ALM_FULL = (SIZE - 1), + parameter ALM_EMPTY = 1, + parameter ADDRW = $clog2(SIZE), + parameter SIZEW = $clog2(SIZE+1), + parameter OUT_REG = 0, + parameter LUTRAM = 1 ) ( input wire clk, input wire reset, @@ -34,8 +35,8 @@ module VX_fifo_queue #( head_r <= 0; size_r <= 0; end else begin - assert(!push || !full); - assert(!pop || !empty); + `ASSERT(!push || !full, ("runtime error")); + `ASSERT(!pop || !empty, ("runtime error")); if (push) begin if (!pop) begin size_r <= 1; @@ -70,8 +71,8 @@ module VX_fifo_queue #( alm_full_r <= 0; used_r <= 0; end else begin - assert(!push || !full); - assert(!pop || !empty); + `ASSERT(!push || !full, ("runtime error")); + `ASSERT(!pop || !empty, ("runtime error")); if (push) begin if (!pop) begin empty_r <= 0; @@ -95,16 +96,14 @@ module VX_fifo_queue #( used_r <= used_r + ADDRW'($signed(2'(push) - 2'(pop))); end else begin // (SIZE == 2); - `IGNORE_WARNINGS_BEGIN - used_r <= used_r ^ (push ^ pop); - `IGNORE_WARNINGS_END + used_r[0] <= used_r[0] ^ (push ^ pop); end end end if (SIZE == 2) begin - if (0 == OUTPUT_REG) begin + if (0 == OUT_REG) begin reg [DATAW-1:0] shift_reg [1:0]; @@ -139,7 +138,7 @@ module VX_fifo_queue #( end else begin - if (0 == OUTPUT_REG) begin + if (0 == OUT_REG) begin reg [ADDRW-1:0] rd_ptr_r; reg [ADDRW-1:0] wr_ptr_r; @@ -155,20 +154,17 @@ module VX_fifo_queue #( end VX_dp_ram #( - .DATAW (DATAW), - .SIZE (SIZE), - .OUTPUT_REG (0), - .RWCHECK (1), - .FASTRAM (FASTRAM) + .DATAW (DATAW), + .SIZE (SIZE), + .OUT_REG (0), + .LUTRAM (LUTRAM) ) dp_ram ( .clk(clk), - .waddr(wr_ptr_r), - .raddr(rd_ptr_r), - .wren(push), - .byteen(1'b1), - .rden(1'b1), - .din(data_in), - .dout(data_out) + .wren (push), + .waddr (wr_ptr_r), + .wdata (data_in), + .raddr (rd_ptr_r), + .rdata (data_out) ); end else begin @@ -200,20 +196,17 @@ module VX_fifo_queue #( end VX_dp_ram #( - .DATAW (DATAW), - .SIZE (SIZE), - .OUTPUT_REG (0), - .RWCHECK (1), - .FASTRAM (FASTRAM) + .DATAW (DATAW), + .SIZE (SIZE), + .OUT_REG (0), + .LUTRAM (LUTRAM) ) dp_ram ( - .clk(clk), - .waddr(wr_ptr_r), - .raddr(rd_ptr_n_r), - .wren(push), - .byteen(1'b1), - .rden(1'b1), - .din(data_in), - .dout(dout) + .clk (clk), + .wren (push), + .waddr (wr_ptr_r), + .wdata (data_in), + .raddr (rd_ptr_n_r), + .rdata (dout) ); always @(posedge clk) begin @@ -235,4 +228,5 @@ module VX_fifo_queue #( assign size = {full_r, used_r}; end -endmodule \ No newline at end of file +endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_find_first.sv b/hw/rtl/libs/VX_find_first.sv new file mode 100644 index 00000000..048a803c --- /dev/null +++ b/hw/rtl/libs/VX_find_first.sv @@ -0,0 +1,44 @@ +`include "VX_platform.vh" + +`TRACING_OFF +module VX_find_first #( + parameter N = 1, + parameter DATAW = 1, + parameter REVERSE = 0, + parameter LOGN = $clog2(N) +) ( + input wire [N-1:0][DATAW-1:0] data_i, + input wire [N-1:0] valid_i, + output wire [DATAW-1:0] data_o, + output wire valid_o +); + localparam TL = (1 << LOGN) - 1; + localparam TN = (1 << (LOGN+1)) - 1; + +`IGNORE_WARNINGS_BEGIN + wire [TN-1:0] s_n; + wire [TN-1:0][DATAW-1:0] d_n; +`IGNORE_WARNINGS_END + + for (genvar i = 0; i < N; ++i) begin + assign s_n[TL+i] = REVERSE ? valid_i[N-1-i] : valid_i[i]; + assign d_n[TL+i] = REVERSE ? data_i[N-1-i] : data_i[i]; + end + + for (genvar i = TL+N; i < TN; ++i) begin + assign s_n[i] = 0; + assign d_n[i] = 'x; + end + + for (genvar j = 0; j < LOGN; ++j) begin + for (genvar i = 0; i < (2**j); ++i) begin + assign s_n[2**j-1+i] = s_n[2**(j+1)-1+i*2] | s_n[2**(j+1)-1+i*2+1]; + assign d_n[2**j-1+i] = s_n[2**(j+1)-1+i*2] ? d_n[2**(j+1)-1+i*2] : d_n[2**(j+1)-1+i*2+1]; + end + end + + assign valid_o = s_n[0]; + assign data_o = d_n[0]; + +endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_fixed_arbiter.v b/hw/rtl/libs/VX_fixed_arbiter.sv similarity index 96% rename from hw/rtl/libs/VX_fixed_arbiter.v rename to hw/rtl/libs/VX_fixed_arbiter.sv index 6608b7f0..5fee1308 100644 --- a/hw/rtl/libs/VX_fixed_arbiter.v +++ b/hw/rtl/libs/VX_fixed_arbiter.sv @@ -1,5 +1,6 @@ `include "VX_platform.vh" +`TRACING_OFF module VX_fixed_arbiter #( parameter NUM_REQS = 1, parameter LOCK_ENABLE = 0, @@ -38,4 +39,5 @@ module VX_fixed_arbiter #( end -endmodule \ No newline at end of file +endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_index_buffer.v b/hw/rtl/libs/VX_index_buffer.sv similarity index 52% rename from hw/rtl/libs/VX_index_buffer.v rename to hw/rtl/libs/VX_index_buffer.sv index 62af4dbb..19efefcf 100644 --- a/hw/rtl/libs/VX_index_buffer.v +++ b/hw/rtl/libs/VX_index_buffer.sv @@ -1,10 +1,11 @@ `include "VX_platform.vh" +`TRACING_OFF module VX_index_buffer #( - parameter DATAW = 1, - parameter SIZE = 1, - parameter FASTRAM = 1, - parameter ADDRW = `LOG2UP(SIZE) + parameter DATAW = 1, + parameter SIZE = 1, + parameter LUTRAM = 1, + parameter ADDRW = `LOG2UP(SIZE) ) ( input wire clk, input wire reset, @@ -28,13 +29,12 @@ module VX_index_buffer #( wire free_valid; wire [ADDRW-1:0] free_index; - VX_priority_encoder #( + VX_lzc #( .N (SIZE) - ) free_slots_encoder ( - .data_in (free_slots_n), - .index (free_index), - `UNUSED_PIN (onehot), - .valid_out (free_valid) + ) free_slots_sel ( + .in_i (free_slots_n), + .cnt_o (free_index), + .valid_o (free_valid) ); always @(*) begin @@ -42,9 +42,8 @@ module VX_index_buffer #( if (release_slot) begin free_slots_n[release_addr] = 1; end - if (acquire_slot) begin - assert(1 == free_slots[write_addr]) else $error("%t: acquiring used slot at port %d", $time, write_addr); - free_slots_n[write_addr_r] = 0; + if (acquire_slot) begin + free_slots_n[write_addr_r] = 0; end end @@ -56,35 +55,34 @@ module VX_index_buffer #( full_r <= 1'b0; end else begin if (release_slot) begin - assert(0 == free_slots[release_addr]) else $error("%t: releasing invalid slot at port %d", $time, release_addr); + `ASSERT(0 == free_slots[release_addr], ("%t: releasing invalid slot at port %d", $time, release_addr)); end - if (acquire_slot || full_r) begin - write_addr_r <= free_index; + if (acquire_slot) begin + `ASSERT(1 == free_slots[write_addr], ("%t: acquiring used slot at port %d", $time, write_addr)); end - free_slots <= free_slots_n; - empty_r <= (& free_slots_n); - full_r <= ~free_valid; + write_addr_r <= free_index; + free_slots <= free_slots_n; + empty_r <= (& free_slots_n); + full_r <= ~free_valid; end end VX_dp_ram #( - .DATAW(DATAW), - .SIZE(SIZE), - .RWCHECK(1), - .FASTRAM(FASTRAM) + .DATAW (DATAW), + .SIZE (SIZE), + .LUTRAM (LUTRAM) ) data_table ( - .clk(clk), - .waddr(write_addr), - .raddr(read_addr), - .wren(acquire_slot), - .byteen(1'b1), - .rden(1'b1), - .din(write_data), - .dout(read_data) + .clk (clk), + .wren (acquire_slot), + .waddr (write_addr_r), + .wdata (write_data), + .raddr (read_addr), + .rdata (read_data) ); assign write_addr = write_addr_r; assign empty = empty_r; assign full = full_r; -endmodule \ No newline at end of file +endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_index_queue.v b/hw/rtl/libs/VX_index_queue.sv similarity index 94% rename from hw/rtl/libs/VX_index_queue.v rename to hw/rtl/libs/VX_index_queue.sv index 4bdb5f9d..66307d74 100644 --- a/hw/rtl/libs/VX_index_queue.v +++ b/hw/rtl/libs/VX_index_queue.sv @@ -1,5 +1,6 @@ `include "VX_platform.vh" +`TRACING_OFF module VX_index_queue #( parameter DATAW = 1, parameter SIZE = 1 @@ -31,10 +32,8 @@ module VX_index_queue #( assign enqueue = push; assign dequeue = !empty && !valid[rd_a]; // auto-remove when head is invalid - always @(*) begin - assert(!push || !full); - end - + `RUNTIME_ASSERT(!push || !full, ("invalid inputs")); + always @(posedge clk) begin if (reset) begin rd_ptr <= 0; @@ -61,4 +60,5 @@ module VX_index_queue #( assign write_addr = wr_a; assign read_data = entries[read_addr]; -endmodule \ No newline at end of file +endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_lzc.sv b/hw/rtl/libs/VX_lzc.sv new file mode 100644 index 00000000..cf89f586 --- /dev/null +++ b/hw/rtl/libs/VX_lzc.sv @@ -0,0 +1,31 @@ +`include "VX_platform.vh" + +`TRACING_OFF +module VX_lzc #( + parameter N = 2, + parameter MODE = 0, // 0 -> trailing zero, 1 -> leading zero + parameter LOGN = $clog2(N) +) ( + input wire [N-1:0] in_i, + output wire [LOGN-1:0] cnt_o, + output wire valid_o +); + wire [N-1:0][LOGN-1:0] indices; + + for (genvar i = 0; i < N; ++i) begin + assign indices[i] = MODE ? LOGN'(N-1-i) : LOGN'(i); + end + + VX_find_first #( + .N (N), + .DATAW (LOGN), + .REVERSE (MODE) + ) find_first ( + .data_i (indices), + .valid_i (in_i), + .data_o (cnt_o), + .valid_o (valid_o) + ); + +endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_lzc.v b/hw/rtl/libs/VX_lzc.v deleted file mode 100644 index 0ee0737a..00000000 --- a/hw/rtl/libs/VX_lzc.v +++ /dev/null @@ -1,86 +0,0 @@ -`include "VX_platform.vh" - -/// Modified port of lzc module from fpnew Libray -/// reference: https://github.com/pulp-platform/fpnew -/// A trailing zero counter / leading zero counter. -/// Set MODE to 0 for trailing zero counter => cnt_o is the number of trailing zeros (from the LSB) -/// Set MODE to 1 for leading zero counter => cnt_o is the number of leading zeros (from the MSB) -/// If the input does not contain a zero, `empty_o` is asserted. Additionally `cnt_o` contains -/// the maximum number of zeros - 1. For example: -/// in_i = 000_0000, empty_o = 1, cnt_o = 6 (mode = 0) -/// in_i = 000_0001, empty_o = 0, cnt_o = 0 (mode = 0) -/// in_i = 000_1000, empty_o = 0, cnt_o = 3 (mode = 0) -/// Furthermore, this unit contains a more efficient implementation for Verilator (simulation only). -/// This speeds up simulation significantly. - -module VX_lzc #( - /// The width of the input vector. - parameter int unsigned WIDTH = 2, - parameter bit MODE = 1'b0 // 0 -> trailing zero, 1 -> leading zero -) ( - input logic [WIDTH-1:0] in_i, - output logic [$clog2(WIDTH)-1:0] cnt_o, - output logic valid_o -); -`IGNORE_WARNINGS_BEGIN - - localparam int unsigned NUM_LEVELS = $clog2(WIDTH); - - // pragma translate_off - initial begin - assert(WIDTH > 0) else $fatal("input must be at least one bit wide"); - end - // pragma translate_on - - logic [WIDTH-1:0][NUM_LEVELS-1:0] index_lut; - logic [2**NUM_LEVELS-1:0] sel_nodes; - logic [2**NUM_LEVELS-1:0][NUM_LEVELS-1:0] index_nodes; - - logic [WIDTH-1:0] in_tmp; - - // reverse vector if required - always_comb begin : flip_vector - for (int unsigned i = 0; i < WIDTH; i++) begin - in_tmp[i] = (MODE) ? in_i[WIDTH-1-i] : in_i[i]; - end - end - - for (genvar j = 0; unsigned'(j) < WIDTH; j++) begin : g_index_lut - assign index_lut[j] = NUM_LEVELS'(unsigned'(j)); - end - - for (genvar level = 0; unsigned'(level) < NUM_LEVELS; level++) begin : g_levels - if (unsigned'(level) == NUM_LEVELS-1) begin : g_last_level - for (genvar k = 0; k < 2**level; k++) begin : g_level - // if two successive indices are still in the vector... - if (unsigned'(k) * 2 < WIDTH-1) begin - assign sel_nodes[2**level-1+k] = in_tmp[k*2] | in_tmp[k*2+1]; - assign index_nodes[2**level-1+k] = (in_tmp[k*2] == 1'b1) ? index_lut[k*2] : - index_lut[k*2+1]; - end - // if only the first index is still in the vector... - if (unsigned'(k) * 2 == WIDTH-1) begin - assign sel_nodes[2**level-1+k] = in_tmp[k*2]; - assign index_nodes[2**level-1+k] = index_lut[k*2]; - end - // if index is out of range - if (unsigned'(k) * 2 > WIDTH-1) begin - assign sel_nodes[2**level-1+k] = 1'b0; - assign index_nodes[2**level-1+k] = '0; - end - end - end else begin - for (genvar l = 0; l < 2**level; l++) begin : g_level - assign sel_nodes[2**level-1+l] = sel_nodes[2**(level+1)-1+l*2] | sel_nodes[2**(level+1)-1+l*2+1]; - assign index_nodes[2**level-1+l] = (sel_nodes[2**(level+1)-1+l*2] == 1'b1) ? index_nodes[2**(level+1)-1+l*2] : - index_nodes[2**(level+1)-1+l*2+1]; - end - end - end - - assign cnt_o = NUM_LEVELS > unsigned'(0) ? index_nodes[0] : $clog2(WIDTH)'(0); - assign valid_o = NUM_LEVELS > unsigned'(0) ? sel_nodes[0] : (|in_i); - -`IGNORE_WARNINGS_END - -endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_matrix_arbiter.v b/hw/rtl/libs/VX_matrix_arbiter.sv similarity index 98% rename from hw/rtl/libs/VX_matrix_arbiter.v rename to hw/rtl/libs/VX_matrix_arbiter.sv index 65c20d24..a6624ac5 100644 --- a/hw/rtl/libs/VX_matrix_arbiter.v +++ b/hw/rtl/libs/VX_matrix_arbiter.sv @@ -1,5 +1,6 @@ `include "VX_platform.vh" +`TRACING_OFF module VX_matrix_arbiter #( parameter NUM_REQS = 1, parameter LOCK_ENABLE = 0, @@ -83,4 +84,5 @@ module VX_matrix_arbiter #( end -endmodule \ No newline at end of file +endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_multiplier.v b/hw/rtl/libs/VX_multiplier.sv similarity index 83% rename from hw/rtl/libs/VX_multiplier.v rename to hw/rtl/libs/VX_multiplier.sv index 27c8c8e7..cbb52727 100644 --- a/hw/rtl/libs/VX_multiplier.v +++ b/hw/rtl/libs/VX_multiplier.sv @@ -1,5 +1,6 @@ `include "VX_platform.vh" +`TRACING_OFF module VX_multiplier #( parameter WIDTHA = 1, parameter WIDTHB = 1, @@ -48,18 +49,22 @@ module VX_multiplier #( assign result = result_unqual; end else begin reg [WIDTHP-1:0] result_pipe [LATENCY-1:0]; - - for (genvar i = 0; i < LATENCY; i++) begin + always @(posedge clk) begin + if (enable) begin + result_pipe[0] <= result_unqual; + end + end + for (genvar i = 1; i < LATENCY; i++) begin always @(posedge clk) begin if (enable) begin - result_pipe[i] <= (0 == i) ? result_unqual : result_pipe[i-1]; + result_pipe[i] <= result_pipe[i-1]; end end - end - + end assign result = result_pipe[LATENCY-1]; end `endif -endmodule \ No newline at end of file +endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_mux.v b/hw/rtl/libs/VX_mux.sv similarity index 92% rename from hw/rtl/libs/VX_mux.v rename to hw/rtl/libs/VX_mux.sv index 4ff920d3..3b5c3030 100644 --- a/hw/rtl/libs/VX_mux.v +++ b/hw/rtl/libs/VX_mux.sv @@ -1,5 +1,6 @@ `include "VX_platform.vh" +`TRACING_OFF module VX_mux #( parameter DATAW = 1, parameter N = 1, @@ -16,4 +17,5 @@ module VX_mux #( assign data_out = data_in; end -endmodule \ No newline at end of file +endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_onehot_encoder.v b/hw/rtl/libs/VX_onehot_encoder.sv similarity index 94% rename from hw/rtl/libs/VX_onehot_encoder.v rename to hw/rtl/libs/VX_onehot_encoder.sv index c8f686e1..8b85acb6 100644 --- a/hw/rtl/libs/VX_onehot_encoder.v +++ b/hw/rtl/libs/VX_onehot_encoder.sv @@ -1,8 +1,9 @@ `include "VX_platform.vh" // Fast encoder using parallel prefix computation -// Adapter from BaseJump STL: http://bjump.org/data_out.html +// Adapted from BaseJump STL: http://bjump.org/data_out.html +`TRACING_OFF module VX_onehot_encoder #( parameter N = 1, parameter REVERSE = 0, @@ -67,10 +68,7 @@ module VX_onehot_encoder #( for (genvar j = 0; j < LN; ++j) begin wire [N-1:0] mask; for (genvar i = 0; i < N; ++i) begin - `IGNORE_WARNINGS_BEGIN - wire [LN-1:0] i_w = i; - `IGNORE_WARNINGS_END - assign mask[i] = i_w[j]; + assign mask[i] = i[j]; end assign data_out[j] = |(mask & data_in); end @@ -105,4 +103,5 @@ module VX_onehot_encoder #( assign valid_out = (| data_in); end -endmodule \ No newline at end of file +endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_onehot_mux.v b/hw/rtl/libs/VX_onehot_mux.sv similarity index 98% rename from hw/rtl/libs/VX_onehot_mux.v rename to hw/rtl/libs/VX_onehot_mux.sv index a75c7c07..375ae105 100644 --- a/hw/rtl/libs/VX_onehot_mux.v +++ b/hw/rtl/libs/VX_onehot_mux.sv @@ -1,5 +1,6 @@ `include "VX_platform.vh" +`TRACING_OFF module VX_onehot_mux #( parameter DATAW = 1, parameter N = 1, @@ -52,4 +53,5 @@ module VX_onehot_mux #( assign data_out = data_in; end -endmodule \ No newline at end of file +endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_pending_size.v b/hw/rtl/libs/VX_pending_size.sv similarity index 74% rename from hw/rtl/libs/VX_pending_size.v rename to hw/rtl/libs/VX_pending_size.sv index e69ede09..2964fdd0 100644 --- a/hw/rtl/libs/VX_pending_size.v +++ b/hw/rtl/libs/VX_pending_size.sv @@ -1,13 +1,14 @@ `include "VX_platform.vh" +`TRACING_OFF module VX_pending_size #( parameter SIZE = 1, parameter SIZEW = $clog2(SIZE+1) ) ( input wire clk, input wire reset, - input wire push, - input wire pop, + input wire incr, + input wire decr, output wire empty, output wire full, output wire [SIZEW-1:0] size @@ -24,19 +25,19 @@ module VX_pending_size #( empty_r <= 1; full_r <= 0; end else begin - assert(!push || !full); - if (push) begin - if (!pop) begin + `ASSERT(!incr || !full, ("runtime error")); + if (incr) begin + if (!decr) begin empty_r <= 0; if (used_r == ADDRW'(SIZE-1)) full_r <= 1; end - end else if (pop) begin + end else if (decr) begin full_r <= 0; if (used_r == ADDRW'(1)) empty_r <= 1; end - used_r <= used_r + ADDRW'($signed(2'(push && !pop) - 2'(pop && !push))); + used_r <= used_r + ADDRW'($signed(2'(incr && !decr) - 2'(decr && !incr))); end end @@ -44,4 +45,5 @@ module VX_pending_size #( assign full = full_r; assign size = {full_r, used_r}; -endmodule \ No newline at end of file +endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_pipe_register.v b/hw/rtl/libs/VX_pipe_register.sv similarity index 98% rename from hw/rtl/libs/VX_pipe_register.v rename to hw/rtl/libs/VX_pipe_register.sv index 1e503ebd..f1d3dfe7 100644 --- a/hw/rtl/libs/VX_pipe_register.v +++ b/hw/rtl/libs/VX_pipe_register.sv @@ -1,5 +1,6 @@ `include "VX_platform.vh" +`TRACING_OFF module VX_pipe_register #( parameter DATAW = 1, parameter RESETW = DATAW, @@ -72,4 +73,5 @@ module VX_pipe_register #( ); end -endmodule \ No newline at end of file +endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_popcount.sv b/hw/rtl/libs/VX_popcount.sv new file mode 100644 index 00000000..3144f106 --- /dev/null +++ b/hw/rtl/libs/VX_popcount.sv @@ -0,0 +1,58 @@ +`include "VX_platform.vh" + +`TRACING_OFF +module VX_popcount #( + parameter MODEL = 1, + parameter N = 1, + parameter LOGN = $clog2(N), + parameter M = LOGN+1 +) ( + input wire [N-1:0] in_i, + output wire [M-1:0] cnt_o +); + if (N == 1) begin + + assign cnt_o = in_i; + + end else if (MODEL == 1) begin + `IGNORE_WARNINGS_BEGIN + localparam PN = 1 << $clog2(N); + localparam LOGPN = $clog2(PN); + + wire [M-1:0] tmp [0:PN-1] [0:PN-1]; + + for (genvar i = 0; i < N; ++i) begin + assign tmp[0][i] = in_i[i]; + end + + for (genvar i = N; i < PN; ++i) begin + assign tmp[0][i] = '0; + end + + for (genvar j = 0; j < LOGPN; ++j) begin + for (genvar i = 0; i < (1 << (LOGPN-j-1)); ++i) begin + assign tmp[j+1][i] = tmp[j][i*2] + tmp[j][i*2+1]; + end + end + + assign cnt_o = tmp[LOGPN][0]; + `IGNORE_WARNINGS_END + end else begin + + reg [M-1:0] cnt_r; + + always @(*) begin + cnt_r = '0; + for (integer i = 0; i < N; ++i) begin + `IGNORE_WARNINGS_BEGIN + cnt_r = cnt_r + in_i[i]; + `IGNORE_WARNINGS_END + end + end + + assign cnt_o = cnt_r; + + end + +endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_priority_encoder.sv b/hw/rtl/libs/VX_priority_encoder.sv new file mode 100644 index 00000000..ea5e27d7 --- /dev/null +++ b/hw/rtl/libs/VX_priority_encoder.sv @@ -0,0 +1,113 @@ +`include "VX_platform.vh" + +`TRACING_OFF +module VX_priority_encoder #( + parameter N = 1, + parameter REVERSE = 0, + parameter MODEL = 1, + parameter LN = `LOG2UP(N) +) ( + input wire [N-1:0] data_in, + output wire [N-1:0] onehot, + output wire [LN-1:0] index, + output wire valid_out +); + wire [N-1:0] reversed; + + if (REVERSE) begin + for (genvar i = 0; i < N; ++i) begin + assign reversed[N-i-1] = data_in[i]; + end + end else begin + assign reversed = data_in; + end + + if (N == 1) begin + + assign onehot = reversed; + assign index = 0; + assign valid_out = reversed; + + end else if (N == 2) begin + + assign onehot = {~reversed[0], reversed[0]}; + assign index = ~reversed[0]; + assign valid_out = (| reversed); + + end else if (MODEL == 1) begin + + wire [N-1:0] scan_lo; + + VX_scan #( + .N (N), + .OP (2) + ) scan ( + .data_in (reversed), + .data_out (scan_lo) + ); + + VX_lzc #( + .N (N) + ) lzc ( + .in_i (reversed), + .cnt_o (index), + `UNUSED_PIN (valid_o) + ); + + assign onehot = scan_lo & {(~scan_lo[N-2:0]), 1'b1}; + assign valid_out = scan_lo[N-1]; + + end else if (MODEL == 2) begin + + `IGNORE_WARNINGS_BEGIN + wire [N-1:0] higher_pri_regs; + `IGNORE_WARNINGS_END + assign higher_pri_regs[N-1:1] = higher_pri_regs[N-2:0] | reversed[N-2:0]; + assign higher_pri_regs[0] = 1'b0; + assign onehot[N-1:0] = reversed[N-1:0] & ~higher_pri_regs[N-1:0]; + + VX_lzc #( + .N (N) + ) lzc ( + .in_i (reversed), + .cnt_o (index), + .valid_o (valid_out) + ); + + end else if (MODEL == 3) begin + + assign onehot = reversed & ~(reversed-1); + + VX_lzc #( + .N (N) + ) lzc ( + .in_i (reversed), + .cnt_o (index), + .valid_o (valid_out) + ); + + end else begin + + reg [LN-1:0] index_r; + reg [N-1:0] onehot_r; + + always @(*) begin + index_r = 'x; + onehot_r = 'x; + for (integer i = N-1; i >= 0; --i) begin + if (reversed[i]) begin + index_r = LN'(i); + onehot_r = 0; + onehot_r[i] = 1'b1; + end + end + end + + assign index = index_r; + assign onehot = onehot_r; + assign valid_out = (| reversed); + + end + +endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_priority_encoder.v b/hw/rtl/libs/VX_priority_encoder.v deleted file mode 100644 index b2c6a4a9..00000000 --- a/hw/rtl/libs/VX_priority_encoder.v +++ /dev/null @@ -1,129 +0,0 @@ -`include "VX_platform.vh" - -module VX_priority_encoder #( - parameter N = 1, - parameter REVERSE = 0, - parameter MODEL = 1, - parameter LN = `LOG2UP(N) -) ( - input wire [N-1:0] data_in, - output wire [N-1:0] onehot, - output wire [LN-1:0] index, - output wire valid_out -); - - if (N == 1) begin - - assign onehot = data_in; - assign index = 0; - assign valid_out = data_in; - - end else if (N == 2) begin - - assign onehot = {~data_in[REVERSE], data_in[REVERSE]}; - assign index = ~data_in[REVERSE]; - assign valid_out = (| data_in); - - end else if (MODEL == 1) begin - - wire [N-1:0] scan_lo; - - VX_scan #( - .N (N), - .OP (2), - .REVERSE (REVERSE) - ) scan ( - .data_in (data_in), - .data_out (scan_lo) - ); - - if (REVERSE) begin - assign onehot = scan_lo & {1'b1, (~scan_lo[N-1:1])}; - assign valid_out = scan_lo[0]; - end else begin - assign onehot = scan_lo & {(~scan_lo[N-2:0]), 1'b1}; - assign valid_out = scan_lo[N-1]; - end - - VX_onehot_encoder #( - .N (N), - .REVERSE (REVERSE) - ) onehot_encoder ( - .data_in (onehot), - .data_out (index), - `UNUSED_PIN (valid_out) - ); - - end else if (MODEL == 2) begin - - `IGNORE_WARNINGS_BEGIN - wire [N-1:0] higher_pri_regs; - `IGNORE_WARNINGS_END - assign higher_pri_regs[N-1:1] = higher_pri_regs[N-2:0] | data_in[N-2:0]; - assign higher_pri_regs[0] = 1'b0; - assign onehot[N-1:0] = data_in[N-1:0] & ~higher_pri_regs[N-1:0]; - - VX_onehot_encoder #( - .N (N), - .REVERSE (REVERSE) - ) onehot_encoder ( - .data_in (onehot), - .data_out (index), - `UNUSED_PIN (valid_out) - ); - - assign valid_out = (| data_in); - - end else if (MODEL == 3) begin - - assign onehot = data_in & ~(data_in-1); - - VX_onehot_encoder #( - .N (N), - .REVERSE (REVERSE) - ) onehot_encoder ( - .data_in (onehot), - .data_out (index), - `UNUSED_PIN (valid_out) - ); - - assign valid_out = (| data_in); - - end else begin - - reg [LN-1:0] index_r; - reg [N-1:0] onehot_r; - - if (REVERSE) begin - always @(*) begin - index_r = 'x; - onehot_r = 'x; - for (integer i = 0; i < N; ++i) begin - if (data_in[i]) begin - index_r = LN'(i); - onehot_r = 0; - onehot_r[i] = 1'b1; - end - end - end - end else begin - always @(*) begin - index_r = 'x; - onehot_r = 'x; - for (integer i = N-1; i >= 0; --i) begin - if (data_in[i]) begin - index_r = LN'(i); - onehot_r = 0; - onehot_r[i] = 1'b1; - end - end - end - end - - assign index = index_r; - assign onehot = onehot_r; - assign valid_out = (| data_in); - - end - -endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_reset_relay.sv b/hw/rtl/libs/VX_reset_relay.sv new file mode 100644 index 00000000..94b24250 --- /dev/null +++ b/hw/rtl/libs/VX_reset_relay.sv @@ -0,0 +1,31 @@ +`include "VX_platform.vh" + +module VX_reset_relay #( + parameter N = 1, + parameter DEPTH = 1 +) ( + input wire clk, + input wire reset, + output wire [N-1:0] reset_o +); + + if (DEPTH > 1) begin + `PRESERVE_REG `DISABLE_BRAM reg [N-1:0] reset_r [DEPTH-1:0]; + always @(posedge clk) begin + for (integer i = DEPTH-1; i > 0; --i) + reset_r[i] <= reset_r[i-1]; + reset_r[0] <= {N{reset}}; + end + assign reset_o = reset_r[DEPTH-1]; + end else if (DEPTH == 1) begin + `PRESERVE_REG reg [N-1:0] reset_r; + always @(posedge clk) begin + reset_r <= {N{reset}}; + end + assign reset_o = reset_r; + end else begin + `UNUSED_VAR (clk) + assign reset_o = {N{reset}}; + end + +endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_reset_relay.v b/hw/rtl/libs/VX_reset_relay.v deleted file mode 100644 index 5f347cac..00000000 --- a/hw/rtl/libs/VX_reset_relay.v +++ /dev/null @@ -1,24 +0,0 @@ -`include "VX_platform.vh" - -module VX_reset_relay #( - parameter ASYNC = 0 -) ( - input wire clk, - input wire reset, - output wire reset_o -); - (* preserve *) reg reset_r; - - if (ASYNC) begin - always @(posedge clk or posedge reset) begin - reset_r <= reset; - end - end else begin - always @(posedge clk) begin - reset_r <= reset; - end - end - - assign reset_o = reset_r; - -endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_rr_arbiter.v b/hw/rtl/libs/VX_rr_arbiter.sv similarity index 99% rename from hw/rtl/libs/VX_rr_arbiter.v rename to hw/rtl/libs/VX_rr_arbiter.sv index 199bc1f0..d9b9ae12 100644 --- a/hw/rtl/libs/VX_rr_arbiter.v +++ b/hw/rtl/libs/VX_rr_arbiter.sv @@ -1,5 +1,6 @@ `include "VX_platform.vh" +`TRACING_OFF module VX_rr_arbiter #( parameter NUM_REQS = 1, parameter LOCK_ENABLE = 0, @@ -245,4 +246,5 @@ module VX_rr_arbiter #( assign grant_valid = (| requests); end -endmodule \ No newline at end of file +endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_scan.v b/hw/rtl/libs/VX_scan.sv similarity index 78% rename from hw/rtl/libs/VX_scan.v rename to hw/rtl/libs/VX_scan.sv index 866fb661..2ccec7e9 100644 --- a/hw/rtl/libs/VX_scan.v +++ b/hw/rtl/libs/VX_scan.sv @@ -3,6 +3,7 @@ // Fast Paralllel scan using Kogge-Stone style prefix tree with configurable operator // Adapted from BaseJump STL: http://bjump.org/index.html +`TRACING_OFF module VX_scan #( parameter N = 1, parameter OP = 0, // 0: XOR, 1: AND, 2: OR @@ -13,7 +14,9 @@ module VX_scan #( ); `IGNORE_WARNINGS_BEGIN - wire [$clog2(N):0][N-1:0] t; + localparam LOGN = $clog2(N); + + wire [LOGN:0][N-1:0] t; // reverses bits if (REVERSE) begin @@ -24,15 +27,15 @@ module VX_scan #( // optimize for the common case of small and-scans if ((N == 2) && (OP == 1)) begin - assign t[$clog2(N)] = {t[0][1], &t[0][1:0]}; + assign t[LOGN] = {t[0][1], &t[0][1:0]}; end else if ((N == 3) && (OP == 1)) begin - assign t[$clog2(N)] = {t[0][2], &t[0][2:1], &t[0][2:0]}; + assign t[LOGN] = {t[0][2], &t[0][2:1], &t[0][2:0]}; end else if ((N == 4) && (OP == 1)) begin - assign t[$clog2(N)] = {t[0][3], &t[0][3:2], &t[0][3:1], &t[0][3:0]}; + assign t[LOGN] = {t[0][3], &t[0][3:2], &t[0][3:1], &t[0][3:0]}; end else begin // general case wire [N-1:0] fill; - for (genvar i = 0; i < $clog2(N); i++) begin + for (genvar i = 0; i < LOGN; i++) begin wire [N-1:0] shifted = N'({fill, t[i]} >> (1<= waddr_end)) begin `ifdef DBG_PRINT_SCOPE - $display("%t: *** scope: recording stop - waddr=(%0d, %0d)", $time, waddr, waddr_end); + dpi_trace("%d: *** scope: recording stop - waddr=(%0d, %0d)\n", $time, waddr, waddr_end); `endif waddr <= waddr; // keep last address recording <= 0; @@ -232,12 +232,13 @@ module VX_scope #( `ifdef DBG_PRINT_SCOPE always @(posedge clk) begin if (bus_read) begin - $display("%t: scope-read: cmd=%0d, addr=%0d, value=%0h", $time, get_cmd, raddr, bus_out); + dpi_trace("%d: scope-read: cmd=%0d, addr=%0d, value=%0h\n", $time, get_cmd, raddr, bus_out); end if (bus_write) begin - $display("%t: scope-write: cmd=%0d, value=%0d", $time, cmd_type, cmd_data); + dpi_trace("%d: scope-write: cmd=%0d, value=%0d\n", $time, cmd_type, cmd_data); end end `endif -endmodule \ No newline at end of file +endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_serial_div.v b/hw/rtl/libs/VX_serial_div.sv similarity index 98% rename from hw/rtl/libs/VX_serial_div.v rename to hw/rtl/libs/VX_serial_div.sv index f1b27416..a87b7a5d 100644 --- a/hw/rtl/libs/VX_serial_div.v +++ b/hw/rtl/libs/VX_serial_div.sv @@ -1,5 +1,6 @@ `include "VX_platform.vh" +`TRACING_OFF module VX_serial_div #( parameter WIDTHN = 1, parameter WIDTHD = 1, @@ -97,4 +98,5 @@ module VX_serial_div #( assign tag_out = tag_r; assign valid_out = is_busy && done; -endmodule \ No newline at end of file +endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_shift_register.v b/hw/rtl/libs/VX_shift_register.sv similarity index 81% rename from hw/rtl/libs/VX_shift_register.v rename to hw/rtl/libs/VX_shift_register.sv index 5c07ea0e..e30f1f6c 100644 --- a/hw/rtl/libs/VX_shift_register.v +++ b/hw/rtl/libs/VX_shift_register.sv @@ -1,5 +1,6 @@ `include "VX_platform.vh" +`TRACING_OFF module VX_shift_register_nr #( parameter DATAW = 1, parameter DEPTH = 1, @@ -12,7 +13,7 @@ module VX_shift_register_nr #( input wire [DATAW-1:0] data_in, output wire [(NTAPS*DATAW)-1:0] data_out ); - `USE_FAST_BRAM reg [DATAW-1:0] entries [DEPTH-1:0]; + reg [DEPTH-1:0][DATAW-1:0] entries; always @(posedge clk) begin if (enable) begin @@ -21,7 +22,7 @@ module VX_shift_register_nr #( entries[0] <= data_in; end end - + for (genvar i = 0; i < NTAPS; ++i) begin assign data_out [i*DATAW+:DATAW] = entries [TAPS[i*DEPTHW+:DEPTHW]]; end @@ -41,30 +42,15 @@ module VX_shift_register_wr #( input wire [DATAW-1:0] data_in, output wire [(NTAPS*DATAW)-1:0] data_out ); - `USE_FAST_BRAM reg [DEPTH-1:0][DATAW-1:0] entries; + reg [DEPTH-1:0][DATAW-1:0] entries; - if (1 == DEPTH) begin - - always @(posedge clk) begin - if (reset) begin - entries <= (DEPTH * DATAW)'(0); - end else begin - if (enable) begin - entries <= data_in; - end - end - end - - end else begin - - always @(posedge clk) begin - if (reset) begin - entries <= (DEPTH * DATAW)'(0); - end else begin - if (enable) begin - entries <= {entries[DEPTH-2:0], data_in}; - end - end + always @(posedge clk) begin + if (reset) begin + entries <= '0; + end else if (enable) begin + for (integer i = DEPTH-1; i > 0; --i) + entries[i] <= entries[i-1]; + entries[0] <= data_in; end end @@ -151,4 +137,5 @@ module VX_shift_register #( end -endmodule \ No newline at end of file +endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_skid_buffer.v b/hw/rtl/libs/VX_skid_buffer.sv similarity index 89% rename from hw/rtl/libs/VX_skid_buffer.v rename to hw/rtl/libs/VX_skid_buffer.sv index 3da8f2a5..ba6c8b6c 100644 --- a/hw/rtl/libs/VX_skid_buffer.v +++ b/hw/rtl/libs/VX_skid_buffer.sv @@ -1,10 +1,11 @@ `include "VX_platform.vh" +`TRACING_OFF module VX_skid_buffer #( parameter DATAW = 1, parameter PASSTHRU = 0, parameter NOBACKPRESSURE = 0, - parameter OUTPUT_REG = 0 + parameter OUT_REG = 0 ) ( input wire clk, input wire reset, @@ -29,9 +30,7 @@ module VX_skid_buffer #( end else if (NOBACKPRESSURE) begin - always @(posedge clk) begin - assert(ready_out) else $error("ready_out should always be asserted"); - end + `RUNTIME_ASSERT(ready_out, ("ready_out should always be asserted")) wire stall = valid_out && ~ready_out; @@ -50,7 +49,7 @@ module VX_skid_buffer #( end else begin - if (OUTPUT_REG) begin + if (OUT_REG) begin reg [DATAW-1:0] data_out_r; reg [DATAW-1:0] buffer; @@ -67,8 +66,7 @@ module VX_skid_buffer #( end else begin if (ready_out) begin use_buffer <= 0; - end else if (push && valid_out_r) begin - assert(!use_buffer); + end else if (valid_in && valid_out_r) begin use_buffer <= 1; end if (pop) begin @@ -80,7 +78,7 @@ module VX_skid_buffer #( always @(posedge clk) begin if (push) begin buffer <= data_in; - end + end if (pop && !use_buffer) begin data_out_r <= data_in; end else if (ready_out) begin @@ -115,9 +113,7 @@ module VX_skid_buffer #( ready_in_r <= 1; valid_out_r <= rd_ptr_r; end - `IGNORE_WARNINGS_BEGIN rd_ptr_r <= rd_ptr_r ^ (push ^ pop); - `IGNORE_WARNINGS_END end end @@ -134,4 +130,5 @@ module VX_skid_buffer #( end end -endmodule \ No newline at end of file +endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_sp_ram.sv b/hw/rtl/libs/VX_sp_ram.sv new file mode 100644 index 00000000..2ed01d0d --- /dev/null +++ b/hw/rtl/libs/VX_sp_ram.sv @@ -0,0 +1,252 @@ +`include "VX_platform.vh" + +`TRACING_OFF +module VX_sp_ram #( + parameter DATAW = 1, + parameter SIZE = 1, + parameter BYTEENW = 1, + parameter OUT_REG = 0, + parameter NO_RWCHECK = 0, + parameter LUTRAM = 0, + parameter ADDRW = $clog2(SIZE), + parameter INIT_ENABLE = 0, + parameter INIT_FILE = "", + parameter [DATAW-1:0] INIT_VALUE = 0 +) ( + input wire clk, + input wire [ADDRW-1:0] addr, + input wire [BYTEENW-1:0] wren, + input wire [DATAW-1:0] wdata, + output wire [DATAW-1:0] rdata +); + + `STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter")) + +`define RAM_INITIALIZATION \ + if (INIT_ENABLE) begin \ + if (INIT_FILE != "") begin \ + initial $readmemh(INIT_FILE, ram); \ + end else begin \ + initial \ + for (integer i = 0; i < SIZE; ++i)\ + ram[i] = INIT_VALUE; \ + end \ + end + +`ifdef SYNTHESIS + if (LUTRAM) begin + if (OUT_REG) begin + reg [DATAW-1:0] rdata_r; + + if (BYTEENW > 1) begin + `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + for (integer i = 0; i < BYTEENW; i++) begin + if (wren[i]) + ram[addr][i] <= wdata[i * 8 +: 8]; + end + rdata_r <= ram[addr]; + end + end else begin + `USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0]; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + if (wren) + ram[addr] <= wdata; + rdata_r <= ram[addr]; + end + end + assign rdata = rdata_r; + end else begin + if (BYTEENW > 1) begin + `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + for (integer i = 0; i < BYTEENW; i++) begin + if (wren[i]) + ram[addr][i] <= wdata[i * 8 +: 8]; + end + end + assign rdata = ram[addr]; + end else begin + `USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0]; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + if (wren) + ram[addr] <= wdata; + end + assign rdata = ram[addr]; + end + end + end else begin + if (OUT_REG) begin + reg [DATAW-1:0] rdata_r; + + if (BYTEENW > 1) begin + reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + for (integer i = 0; i < BYTEENW; i++) begin + if (wren[i]) + ram[addr][i] <= wdata[i * 8 +: 8]; + end + rdata_r <= ram[addr]; + end + end else begin + reg [DATAW-1:0] ram [SIZE-1:0]; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + if (wren) + ram[addr] <= wdata; + rdata_r <= ram[addr]; + end + end + assign rdata = rdata_r; + end else begin + if (NO_RWCHECK) begin + if (BYTEENW > 1) begin + `NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + for (integer i = 0; i < BYTEENW; i++) begin + if (wren[i]) + ram[addr][i] <= wdata[i * 8 +: 8]; + end + end + assign rdata = ram[addr]; + end else begin + `NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0]; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + if (wren) + ram[addr] <= wdata; + end + assign rdata = ram[addr]; + end + end else begin + if (BYTEENW > 1) begin + reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + for (integer i = 0; i < BYTEENW; i++) begin + if (wren[i]) + ram[addr][i] <= wdata[i * 8 +: 8]; + end + end + assign rdata = ram[addr]; + end else begin + reg [DATAW-1:0] ram [SIZE-1:0]; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + if (wren) + ram[addr] <= wdata; + end + assign rdata = ram[addr]; + end + end + end + end +`else + if (OUT_REG) begin + reg [DATAW-1:0] rdata_r; + if (BYTEENW > 1) begin + reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + for (integer i = 0; i < BYTEENW; i++) begin + if (wren[i]) + ram[addr][i] <= wdata[i * 8 +: 8]; + end + rdata_r <= ram[addr]; + end + end else begin + reg [DATAW-1:0] ram [SIZE-1:0]; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + if (wren) + ram[addr] <= wdata; + rdata_r <= ram[addr]; + end + end + assign rdata = rdata_r; + end else begin + if (BYTEENW > 1) begin + reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; + reg [DATAW-1:0] prev_data; + reg [ADDRW-1:0] prev_addr; + reg prev_write; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + for (integer i = 0; i < BYTEENW; i++) begin + if (wren[i]) + ram[addr][i] <= wdata[i * 8 +: 8]; + end + prev_write <= (| wren); + prev_data <= ram[addr]; + prev_addr <= addr; + end + + if (LUTRAM || !NO_RWCHECK) begin + `UNUSED_VAR (prev_write) + `UNUSED_VAR (prev_data) + `UNUSED_VAR (prev_addr) + assign rdata = ram[addr]; + end else begin + assign rdata = (prev_write && (prev_addr == addr)) ? prev_data : ram[addr]; + end + end else begin + reg [DATAW-1:0] ram [SIZE-1:0]; + reg [DATAW-1:0] prev_data; + reg [ADDRW-1:0] prev_addr; + reg prev_write; + + `RAM_INITIALIZATION + + always @(posedge clk) begin + if (wren) + ram[addr] <= wdata; + prev_write <= wren; + prev_data <= ram[addr]; + prev_addr <= addr; + end + if (LUTRAM || !NO_RWCHECK) begin + `UNUSED_VAR (prev_write) + `UNUSED_VAR (prev_data) + `UNUSED_VAR (prev_addr) + assign rdata = ram[addr]; + end else begin + assign rdata = (prev_write && (prev_addr == addr)) ? prev_data : ram[addr]; + end + end + end +`endif + +endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_sp_ram.v b/hw/rtl/libs/VX_sp_ram.v deleted file mode 100644 index ab462b71..00000000 --- a/hw/rtl/libs/VX_sp_ram.v +++ /dev/null @@ -1,196 +0,0 @@ -`include "VX_platform.vh" - -`TRACING_OFF -module VX_sp_ram #( - parameter DATAW = 1, - parameter SIZE = 1, - parameter BYTEENW = 1, - parameter OUTPUT_REG = 0, - parameter RWCHECK = 1, - parameter ADDRW = $clog2(SIZE), - parameter FASTRAM = 0, - parameter INITZERO = 0 -) ( - input wire clk, - input wire [ADDRW-1:0] addr, - input wire wren, - input wire [BYTEENW-1:0] byteen, - input wire rden, - input wire [DATAW-1:0] din, - output wire [DATAW-1:0] dout -); - - `STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter")) - - if (FASTRAM) begin - if (OUTPUT_REG) begin - reg [DATAW-1:0] dout_r; - - if (BYTEENW > 1) begin - `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; - - if (INITZERO) begin - initial mem = '{default: 0}; - end - - always @(posedge clk) begin - if (wren) begin - for (integer i = 0; i < BYTEENW; i++) begin - if (byteen[i]) - mem[addr][i] <= din[i * 8 +: 8]; - end - end - if (rden) - dout_r <= mem[addr]; - end - end else begin - `USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0]; - - if (INITZERO) begin - initial mem = '{default: 0}; - end - - always @(posedge clk) begin - if (wren && byteen) - mem[addr] <= din; - if (rden) - dout_r <= mem[addr]; - end - end - assign dout = dout_r; - end else begin - `UNUSED_VAR (rden) - if (BYTEENW > 1) begin - `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; - - if (INITZERO) begin - initial mem = '{default: 0}; - end - - always @(posedge clk) begin - if (wren) begin - for (integer i = 0; i < BYTEENW; i++) begin - if (byteen[i]) - mem[addr][i] <= din[i * 8 +: 8]; - end - end - end - assign dout = mem[addr]; - end else begin - `USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0]; - - if (INITZERO) begin - initial mem = '{default: 0}; - end - - always @(posedge clk) begin - if (wren && byteen) - mem[addr] <= din; - end - assign dout = mem[addr]; - end - end - end else begin - if (OUTPUT_REG) begin - reg [DATAW-1:0] dout_r; - - if (BYTEENW > 1) begin - reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; - - if (INITZERO) begin - initial mem = '{default: 0}; - end - - always @(posedge clk) begin - if (wren) begin - for (integer i = 0; i < BYTEENW; i++) begin - if (byteen[i]) - mem[addr][i] <= din[i * 8 +: 8]; - end - end - if (rden) - dout_r <= mem[addr]; - end - end else begin - reg [DATAW-1:0] mem [SIZE-1:0]; - - if (INITZERO) begin - initial mem = '{default: 0}; - end - - always @(posedge clk) begin - if (wren && byteen) - mem[addr] <= din; - if (rden) - dout_r <= mem[addr]; - end - end - assign dout = dout_r; - end else begin - `UNUSED_VAR (rden) - if (RWCHECK) begin - if (BYTEENW > 1) begin - reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; - - if (INITZERO) begin - initial mem = '{default: 0}; - end - - always @(posedge clk) begin - if (wren) begin - for (integer i = 0; i < BYTEENW; i++) begin - if (byteen[i]) - mem[addr][i] <= din[i * 8 +: 8]; - end - end - end - assign dout = mem[addr]; - end else begin - reg [DATAW-1:0] mem [SIZE-1:0]; - - if (INITZERO) begin - initial mem = '{default: 0}; - end - - always @(posedge clk) begin - if (wren && byteen) - mem[addr] <= din; - end - assign dout = mem[addr]; - end - end else begin - if (BYTEENW > 1) begin - `NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; - - if (INITZERO) begin - initial mem = '{default: 0}; - end - - always @(posedge clk) begin - if (wren) begin - for (integer i = 0; i < BYTEENW; i++) begin - if (byteen[i]) - mem[addr][i] <= din[i * 8 +: 8]; - end - end - end - assign dout = mem[addr]; - end else begin - `NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0]; - - if (INITZERO) begin - initial mem = '{default: 0}; - end - - always @(posedge clk) begin - if (wren && byteen) - mem[addr] <= din; - end - assign dout = mem[addr]; - end - end - end - end - -endmodule -`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_stream_arbiter.v b/hw/rtl/libs/VX_stream_arbiter.sv similarity index 68% rename from hw/rtl/libs/VX_stream_arbiter.v rename to hw/rtl/libs/VX_stream_arbiter.sv index c01e17f0..c4466f39 100644 --- a/hw/rtl/libs/VX_stream_arbiter.v +++ b/hw/rtl/libs/VX_stream_arbiter.sv @@ -4,7 +4,7 @@ module VX_stream_arbiter #( parameter NUM_REQS = 1, parameter LANES = 1, parameter DATAW = 1, - parameter TYPE = "R", + parameter TYPE = "P", parameter LOCK_ENABLE = 1, parameter BUFFERED = 0 ) ( @@ -19,13 +19,13 @@ module VX_stream_arbiter #( output wire [LANES-1:0][DATAW-1:0] data_out, input wire [LANES-1:0] ready_out ); - - localparam LOG_NUM_REQS = $clog2(NUM_REQS); + localparam LOG_NUM_REQS = `CLOG2(NUM_REQS); if (NUM_REQS > 1) begin - wire sel_valid; - wire sel_ready; - wire [NUM_REQS-1:0] sel_1hot; + wire sel_valid; + wire sel_ready; + wire [LOG_NUM_REQS-1:0] sel_index; + wire [NUM_REQS-1:0] sel_onehot; wire [NUM_REQS-1:0] valid_in_any; wire [LANES-1:0] ready_in_sel; @@ -42,60 +42,60 @@ module VX_stream_arbiter #( assign sel_ready = ready_in_sel; end - if (TYPE == "X") begin + if (TYPE == "P") begin VX_fixed_arbiter #( - .NUM_REQS(NUM_REQS), - .LOCK_ENABLE(LOCK_ENABLE) - ) sel_arb ( - .clk (clk), - .reset (reset), - .requests (valid_in_any), - .enable (sel_ready), - .grant_valid (sel_valid), - .grant_onehot (sel_1hot), - `UNUSED_PIN (grant_index) - ); - end else if (TYPE == "R") begin - VX_rr_arbiter #( - .NUM_REQS(NUM_REQS), - .LOCK_ENABLE(LOCK_ENABLE) + .NUM_REQS (NUM_REQS), + .LOCK_ENABLE (LOCK_ENABLE) ) sel_arb ( .clk (clk), .reset (reset), .requests (valid_in_any), .enable (sel_ready), .grant_valid (sel_valid), - .grant_onehot (sel_1hot), - `UNUSED_PIN (grant_index) + .grant_index (sel_index), + .grant_onehot (sel_onehot) + ); + end else if (TYPE == "R") begin + VX_rr_arbiter #( + .NUM_REQS (NUM_REQS), + .LOCK_ENABLE (LOCK_ENABLE) + ) sel_arb ( + .clk (clk), + .reset (reset), + .requests (valid_in_any), + .enable (sel_ready), + .grant_valid (sel_valid), + .grant_index (sel_index), + .grant_onehot (sel_onehot) ); end else if (TYPE == "F") begin VX_fair_arbiter #( - .NUM_REQS(NUM_REQS), - .LOCK_ENABLE(LOCK_ENABLE) + .NUM_REQS (NUM_REQS), + .LOCK_ENABLE (LOCK_ENABLE) ) sel_arb ( .clk (clk), .reset (reset), .requests (valid_in_any), .enable (sel_ready), .grant_valid (sel_valid), - .grant_onehot (sel_1hot), - `UNUSED_PIN (grant_index) + .grant_index (sel_index), + .grant_onehot (sel_onehot) ); end else if (TYPE == "M") begin VX_matrix_arbiter #( - .NUM_REQS(NUM_REQS), - .LOCK_ENABLE(LOCK_ENABLE) + .NUM_REQS (NUM_REQS), + .LOCK_ENABLE (LOCK_ENABLE) ) sel_arb ( .clk (clk), .reset (reset), .requests (valid_in_any), .enable (sel_ready), .grant_valid (sel_valid), - .grant_onehot (sel_1hot), - `UNUSED_PIN (grant_index) + .grant_index (sel_index), + .grant_onehot (sel_onehot) ); end else begin - $error ("invalid parameter"); + `ERROR(("invalid parameter")); end wire [LANES-1:0] valid_in_sel; @@ -103,43 +103,25 @@ module VX_stream_arbiter #( if (LANES > 1) begin wire [NUM_REQS-1:0][(LANES * (1 + DATAW))-1:0] valid_data_in; - for (genvar i = 0; i < NUM_REQS; i++) begin assign valid_data_in[i] = {valid_in[i], data_in[i]}; end - - VX_onehot_mux #( - .DATAW (LANES * (1 + DATAW)), - .N (NUM_REQS) - ) data_in_mux ( - .data_in (valid_data_in), - .sel_in (sel_1hot), - .data_out ({valid_in_sel, data_in_sel}) - ); - + assign {valid_in_sel, data_in_sel} = valid_data_in[sel_index]; `UNUSED_VAR (sel_valid) end else begin - VX_onehot_mux #( - .DATAW (DATAW), - .N (NUM_REQS) - ) data_in_mux ( - .data_in (data_in), - .sel_in (sel_1hot), - .data_out (data_in_sel) - ); - + assign data_in_sel = data_in[sel_index]; assign valid_in_sel = sel_valid; end for (genvar i = 0; i < NUM_REQS; i++) begin - assign ready_in[i] = ready_in_sel & {LANES{sel_1hot[i]}}; + assign ready_in[i] = ready_in_sel & {LANES{sel_onehot[i]}}; end for (genvar i = 0; i < LANES; ++i) begin VX_skid_buffer #( - .DATAW (DATAW), - .PASSTHRU (0 == BUFFERED), - .OUTPUT_REG (2 == BUFFERED) + .DATAW (DATAW), + .PASSTHRU (0 == BUFFERED), + .OUT_REG (2 == BUFFERED) ) out_buffer ( .clk (clk), .reset (reset), diff --git a/hw/rtl/libs/VX_stream_demux.v b/hw/rtl/libs/VX_stream_demux.sv similarity index 90% rename from hw/rtl/libs/VX_stream_demux.v rename to hw/rtl/libs/VX_stream_demux.sv index e50d7a7c..282a2212 100644 --- a/hw/rtl/libs/VX_stream_demux.v +++ b/hw/rtl/libs/VX_stream_demux.sv @@ -5,7 +5,7 @@ module VX_stream_demux #( parameter LANES = 1, parameter DATAW = 1, parameter BUFFERED = 0, - localparam LOG_NUM_REQS = `LOG2UP(NUM_REQS) + parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS) ) ( input wire clk, input wire reset, @@ -37,9 +37,9 @@ module VX_stream_demux #( for (genvar i = 0; i < NUM_REQS; i++) begin VX_skid_buffer #( - .DATAW (DATAW), - .PASSTHRU (0 == BUFFERED), - .OUTPUT_REG (2 == BUFFERED) + .DATAW (DATAW), + .PASSTHRU (0 == BUFFERED), + .OUT_REG (2 == BUFFERED) ) out_buffer ( .clk (clk), .reset (reset), diff --git a/hw/scripts/scope.json b/hw/scripts/scope.json index 7c6901a3..50348b7f 100644 --- a/hw/scripts/scope.json +++ b/hw/scripts/scope.json @@ -1,9 +1,21 @@ { "version": 1, + "include_paths":[ + "../dpi", + "../rtl", + "../rtl/afu", + "../rtl/cache", + "../rtl/fp_cores", + "../rtl/interfaces", + "../rtl/libs" + ], "includes":[ - "../rtl/VX_config.vh", - "../rtl/VX_platform.vh", - "../rtl/VX_define.vh", + "../rtl/VX_config.vh", + "../rtl/VX_platform.vh", + "../rtl/VX_define.vh", + "../rtl/VX_gpu_types.vh", + "../rtl/fp_cores/VX_fpu_types.vh", + "../rtl/fp_cores/VX_fpu_define.vh", "../rtl/cache/VX_cache_define.vh" ], "modules": { @@ -60,8 +72,8 @@ "VX_gpu_unit": {}, "VX_mem_unit": { "submodules": { - "dcache": {"type":"VX_cache", "params":{"NUM_BANKS":"`DNUM_BANKS"}}, - "icache": {"type":"VX_cache", "params":{"NUM_BANKS":"`INUM_BANKS"}} + "dcache": {"type":"VX_cache", "params":{"NUM_BANKS":"`DCACHE_NUM_BANKS"}}, + "icache": {"type":"VX_cache", "params":{"NUM_BANKS":"1"}} } }, "VX_cache": { @@ -111,9 +123,9 @@ "!cci_pending_writes_full": 1, "?afu_mem_req_fire": 1, "afu_mem_req_addr": 26, - "afu_mem_req_tag": 29, + "afu_mem_req_tag": 27, "?afu_mem_rsp_fire": 1, - "afu_mem_rsp_tag": 29 + "afu_mem_rsp_tag": 27 }, "afu/vortex": { "!reset": 1, @@ -132,26 +144,26 @@ "?icache_req_fire": 1, "icache_req_wid":"`NW_BITS", "icache_req_addr": 32, - "icache_req_tag":"`ICORE_TAG_ID_BITS", + "icache_req_tag":"`ICACHE_CORE_TAG_ID_BITS", "?icache_rsp_fire": 1, "icache_rsp_data": 32, - "icache_rsp_tag":"`ICORE_TAG_ID_BITS" + "icache_rsp_tag":"`ICACHE_CORE_TAG_ID_BITS" }, "afu/vortex/cluster/core/pipeline/fetch/warp_sched": { - "?wsched_scheduled_warp": 1, + "?wsched_scheduled": 1, "wsched_active_warps": "`NUM_WARPS", - "wsched_schedule_table": "`NUM_WARPS", - "wsched_schedule_ready": "`NUM_WARPS", - "wsched_warp_to_schedule": "`NW_BITS", - "wsched_warp_pc": "32" + "wsched_stalled_warps": "`NUM_WARPS", + "wsched_schedule_tmask": "`NUM_THREADS", + "wsched_schedule_wid": "`NW_BITS", + "wsched_schedule_pc": "32" }, "afu/vortex/cluster/core/pipeline/execute/gpu_unit": { "?gpu_rsp_valid": 1, "gpu_rsp_wid": "`NW_BITS", - "gpu_rsp_tmc": "`GPU_TMC_BITS", - "gpu_rsp_wspawn": "`GPU_WSPAWN_BITS", - "gpu_rsp_split": "`GPU_SPLIT_BITS", - "gpu_rsp_barrier": "`GPU_BARRIER_BITS" + "gpu_rsp_tmc": 1, + "gpu_rsp_wspawn": 1, + "gpu_rsp_split": 1, + "gpu_rsp_barrier": 1 }, "afu/vortex/cluster/core/pipeline/execute/lsu_unit": { "?dcache_req_fire":"`NUM_THREADS", @@ -172,8 +184,8 @@ "issue_tmask":"`NUM_THREADS", "issue_pc": 32, "issue_ex_type":"`EX_BITS", - "issue_op_type":"`OP_BITS", - "issue_op_mod":"`MOD_BITS", + "issue_op_type":"`INST_OP_BITS", + "issue_op_mod":"`INST_MOD_BITS", "issue_wb": 1, "issue_rd":"`NR_BITS", "issue_rs1":"`NR_BITS", @@ -203,9 +215,7 @@ "is_fill_st0": 1, "is_mshr_st0": 1, "miss_st0": 1, - "force_miss_st0": 1, - "mshr_push": 1, - "?crsq_in_stall": 1, + "?crsq_stall": 1, "?mreq_alm_full": 1, "?mshr_alm_full": 1 } diff --git a/hw/scripts/scope.py b/hw/scripts/scope.py index a1b82870..679209a9 100755 --- a/hw/scripts/scope.py +++ b/hw/scripts/scope.py @@ -125,6 +125,11 @@ def parse_func_args(text): return (args, l) +def load_include_path(dir): + if not dir in include_dirs: + print("*** include path: " + dir) + include_dirs.append(dir) + def resolve_include_path(filename, parent_dir): if os.path.basename(filename) in exclude_files: return None @@ -137,7 +142,7 @@ def resolve_include_path(filename, parent_dir): filepath = os.path.join(dir, filename) if os.path.isfile(filepath): return os.path.abspath(filepath) - raise Exception("couldn't find include file: " + filename) + raise Exception("couldn't find include file: " + filename + " in " + parent_dir) def remove_comments(text): text = re.sub(re.compile("/\*.*?\*/",re.DOTALL ), "", text) # multiline @@ -273,6 +278,7 @@ def expand_text(text, params): return None def parse_include(filename, nesting): + print("*** parsing: " + filename + "...") if nesting > 99: raise Exception("include recursion!") #print("*** parsing '" + filename + "'...") @@ -356,15 +362,11 @@ def parse_includes(includes): for include in includes: parse_include(include, 0) + load_include_path(os.path.dirname(include)) # restore current directory os.chdir(old_dir) -def load_include_dirs(dirs): - for dir in dirs: - #print("*** include dir: " + dir) - include_dirs.append(dir) - def load_defines(defines): for define in defines: key_value = define.split('=', 2) @@ -396,6 +398,8 @@ def eval_node(text, params): try: __text = text.replace('$clog2', '__clog2') __text = translate_ternary(__text) + __text = __text.replace('||', 'or') + __text = __text.replace('&&', 'and') e = eval(__text, {'__clog2': clog2}) return e except (NameError, SyntaxError): @@ -801,7 +805,8 @@ def main(): global br_stack if args.I: - load_include_dirs(args.I) + for dir in args.I: + load_include_path(dir) if args.D: load_defines(args.D) @@ -810,6 +815,10 @@ def main(): exclude_files.append(os.path.basename(args.vl)) + if "include_paths" in config: + for path in config["include_paths"]: + load_include_path(path) + if "includes" in config: parse_includes(config["includes"]) diff --git a/hw/simulate/Makefile b/hw/simulate/Makefile deleted file mode 100644 index d1c55fd3..00000000 --- a/hw/simulate/Makefile +++ /dev/null @@ -1,101 +0,0 @@ -CFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors -#CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors - -CFLAGS += -Wno-maybe-uninitialized - -CFLAGS += -I../.. - -# control RTL debug print states -DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE -DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_ICACHE -DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_DCACHE -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_BANK -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSHR -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_TAG -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_DATA -DBG_PRINT_FLAGS += -DDBG_PRINT_MEM -DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE -DBG_PRINT_FLAGS += -DDBG_PRINT_AVS -DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE -DBG_PRINT_FLAGS += -DDBG_PRINT_TEX - -DBG_FLAGS += $(DBG_PRINT_FLAGS) -DBG_FLAGS += -DDBG_CACHE_REQ_INFO - -SINGLECORE = -DNUM_CLUSTERS=1 -DNUM_CORES=1 -DL2_ENABLE=0 - -#MULTICORE = -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1 -#MULTICORE = -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1 -MULTICORE = -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 - -SINGLECORE += $(CONFIGS) -MULTICORE += $(CONFIGS) - -TOP = Vortex - -RTL_DIR=../rtl -DPI_DIR=../dpi - -FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(DPI_DIR) -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src -I$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(RTL_DIR)/fp_cores/fpnew/src -TEX_INCLUDE = -I$(RTL_DIR)/tex_unit -RTL_INCLUDE = -I$(RTL_DIR)/ -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(RTL_DIR)/simulate $(FPU_INCLUDE) $(TEX_INCLUDE) - -SRCS = simulator.cpp main.cpp -SRCS += $(DPI_DIR)/util_dpi.cpp $(DPI_DIR)/float_dpi.cpp - -VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic -VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO -VL_FLAGS += --x-initial unique --x-assign unique -VL_FLAGS += verilator.vlt - -VL_FLAGS += --exe $(SRCS) $(RTL_INCLUDE) -VL_FLAGS += --cc Vortex.v --top-module $(TOP) - -# FPU backend -FPU_CORE ?= FPU_FPNEW -VL_FLAGS += -D$(FPU_CORE) - -DBG_FLAGS += -DVCD_OUTPUT - -THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') - -all: build-s - -gen-s: - verilator $(VL_FLAGS) -DNDEBUG $(SINGLECORE) -CFLAGS '$(CFLAGS) -DNDEBUG $(SINGLECORE)' - -gen-sd: - verilator $(VL_FLAGS) $(SINGLECORE) -CFLAGS '$(CFLAGS) $(DBG_FLAGS) $(SINGLECORE)' --trace --trace-structs $(DBG_FLAGS) - -gen-st: - verilator $(VL_FLAGS) -DNDEBUG $(SINGLECORE) -CFLAGS '$(CFLAGS) -DNDEBUG $(SINGLECORE)' --threads $(THREADS) - -gen-m: - verilator $(VL_FLAGS) -DNDEBUG $(MULTICORE) -CFLAGS '$(CFLAGS) -DNDEBUG $(MULTICORE)' - -gen-md: - verilator $(VL_FLAGS) $(MULTICORE) -CFLAGS '$(CFLAGS) $(DBG_FLAGS) $(MULTICORE)' --trace --trace-structs $(DBG_FLAGS) - -gen-mt: - verilator $(VL_FLAGS) -DNDEBUG $(MULTICORE) -CFLAGS '$(CFLAGS) -DNDEBUG $(MULTICORE)' --threads $(THREADS) - -build-s: gen-s - make -j -C obj_dir -f VVortex.mk - -build-sd: gen-sd - make -j -C obj_dir -f VVortex.mk - -build-st: gen-st - make -j -C obj_dir -f VVortex.mk - -build-m: gen-m - make -j -C obj_dir -f VVortex.mk - -build-md: gen-md - make -j -C obj_dir -f VVortex.mk - -build-mt: gen-mt - make -j -C obj_dir -f VVortex.mk - -clean: - rm -rf obj_dir \ No newline at end of file diff --git a/hw/simulate/ram.h b/hw/simulate/ram.h deleted file mode 100644 index 0ddd3e47..00000000 --- a/hw/simulate/ram.h +++ /dev/null @@ -1,64 +0,0 @@ -#pragma once - -#include -#include - -class RAM { -private: - - mutable uint8_t *mem_[(1 << 12)]; - - uint8_t *get(uint32_t address) const { - uint32_t block_addr = address >> 20; - uint32_t block_offset = address & 0x000FFFFF; - if (mem_[block_addr] == NULL) { - mem_[block_addr] = new uint8_t[(1 << 20)]; - } - return mem_[block_addr] + block_offset; - } - -public: - - RAM() { - for (uint32_t i = 0; i < (1 << 12); i++) { - mem_[i] = NULL; - } - } - - ~RAM() { - this->clear(); - } - - size_t size() const { - return (1ull << 32); - } - - void clear() { - for (uint32_t i = 0; i < (1 << 12); i++) { - if (mem_[i]) { - delete [] mem_[i]; - mem_[i] = NULL; - } - } - } - - void read(uint32_t address, uint32_t length, uint8_t *data) const { - for (unsigned i = 0; i < length; i++) { - data[i] = *this->get(address + i); - } - } - - void write(uint32_t address, uint32_t length, const uint8_t *data) { - for (unsigned i = 0; i < length; i++) { - *this->get(address + i) = data[i]; - } - } - - uint8_t& operator[](uint32_t address) { - return *get(address); - } - - const uint8_t& operator[](uint32_t address) const { - return *get(address); - } -}; \ No newline at end of file diff --git a/hw/simulate/simulator.cpp b/hw/simulate/simulator.cpp deleted file mode 100644 index 88cb8134..00000000 --- a/hw/simulate/simulator.cpp +++ /dev/null @@ -1,361 +0,0 @@ -#include "simulator.h" -#include -#include -#include - -#define ENABLE_MEM_STALLS - -#ifndef MEM_LATENCY -#define MEM_LATENCY 24 -#endif - -#ifndef MEM_RQ_SIZE -#define MEM_RQ_SIZE 16 -#endif - -#ifndef MEM_STALLS_MODULO -#define MEM_STALLS_MODULO 16 -#endif - -#ifndef VERILATOR_RESET_VALUE -#define VERILATOR_RESET_VALUE 2 -#endif - -#define VL_WDATA_GETW(lwp, i, n, w) \ - VL_SEL_IWII(0, n * w, 0, 0, lwp, i * w, w) - -uint64_t timestamp = 0; - -double sc_time_stamp() { - return timestamp; -} - -Simulator::Simulator() { - // force random values for unitialized signals - Verilated::randReset(VERILATOR_RESET_VALUE); - Verilated::randSeed(50); - - // Turn off assertion before reset - Verilated::assertOn(false); - - ram_ = nullptr; - vortex_ = new VVortex(); - -#ifdef VCD_OUTPUT - Verilated::traceEverOn(true); - trace_ = new VerilatedVcdC(); - vortex_->trace(trace_, 99); - trace_->open("trace.vcd"); -#endif - - // reset the device - this->reset(); -} - -Simulator::~Simulator() { - for (auto& buf : print_bufs_) { - auto str = buf.second.str(); - if (!str.empty()) { - std::cout << "#" << buf.first << ": " << str << std::endl; - } - } -#ifdef VCD_OUTPUT - trace_->close(); -#endif - delete vortex_; -} - -void Simulator::attach_ram(RAM* ram) { - ram_ = ram; - for (int b = 0; b < MEMORY_BANKS; ++b) { - mem_rsp_vec_[b].clear(); - } - last_mem_rsp_bank_ = 0; -} - -void Simulator::reset() { - print_bufs_.clear(); - for (int b = 0; b < MEMORY_BANKS; ++b) { - mem_rsp_vec_[b].clear(); - } - last_mem_rsp_bank_ = 0; - - mem_rsp_active_ = false; - - vortex_->mem_rsp_valid = 0; - vortex_->mem_req_ready = 0; - - vortex_->reset = 1; - - for (int i = 0; i < RESET_DELAY; ++i) { - vortex_->clk = 0; - this->eval(); - vortex_->clk = 1; - this->eval(); - } - - vortex_->reset = 0; - - // Turn on assertion after reset - Verilated::assertOn(true); -} - -void Simulator::step() { - - vortex_->clk = 0; - this->eval(); - - mem_rsp_ready_ = vortex_->mem_rsp_ready; - - vortex_->clk = 1; - this->eval(); - - this->eval_mem_bus(); - -#ifndef NDEBUG - fflush(stdout); -#endif -} - -void Simulator::eval() { - vortex_->eval(); -#ifdef VCD_OUTPUT - trace_->dump(timestamp); -#endif - ++timestamp; -} - -void Simulator::eval_mem_bus() { - if (ram_ == nullptr) { - vortex_->mem_req_ready = 0; - return; - } - - // update memory responses schedule - for (int b = 0; b < MEMORY_BANKS; ++b) { - for (auto& rsp : mem_rsp_vec_[b]) { - if (rsp.cycles_left > 0) - rsp.cycles_left -= 1; - } - } - - bool has_response = false; - - // schedule memory responses in FIFO order - for (int i = 0; i < MEMORY_BANKS; ++i) { - uint32_t b = (i + last_mem_rsp_bank_ + 1) % MEMORY_BANKS; - if (!mem_rsp_vec_[b].empty() - && (0 == mem_rsp_vec_[b].begin()->cycles_left)) { - has_response = true; - last_mem_rsp_bank_ = b; - break; - } - } - - // send memory response - if (mem_rsp_active_ - && vortex_->mem_rsp_valid && mem_rsp_ready_) { - mem_rsp_active_ = false; - } - if (!mem_rsp_active_) { - if (has_response) { - vortex_->mem_rsp_valid = 1; - std::list::iterator mem_rsp_it = mem_rsp_vec_[last_mem_rsp_bank_].begin(); - memcpy((uint8_t*)vortex_->mem_rsp_data, mem_rsp_it->block.data(), MEM_BLOCK_SIZE); - vortex_->mem_rsp_tag = mem_rsp_it->tag; - mem_rsp_vec_[last_mem_rsp_bank_].erase(mem_rsp_it); - mem_rsp_active_ = true; - } else { - vortex_->mem_rsp_valid = 0; - } - } - - // select the memory bank - uint32_t req_bank = (MEMORY_BANKS >= 2) ? (vortex_->mem_req_addr % MEMORY_BANKS) : 0; - - // handle memory stalls - bool mem_stalled = false; -#ifdef ENABLE_MEM_STALLS - if (0 == ((timestamp/2) % MEM_STALLS_MODULO)) { - mem_stalled = true; - } else - if (mem_rsp_vec_[req_bank].size() >= MEM_RQ_SIZE) { - mem_stalled = true; - } -#endif - - // process memory requests - if (!mem_stalled) { - if (vortex_->mem_req_valid) { - if (vortex_->mem_req_rw) { - uint64_t byteen = vortex_->mem_req_byteen; - unsigned base_addr = (vortex_->mem_req_addr * MEM_BLOCK_SIZE); - uint8_t* data = (uint8_t*)(vortex_->mem_req_data); - if (base_addr >= IO_COUT_ADDR - && base_addr <= (IO_COUT_ADDR + IO_COUT_SIZE - 1)) { - for (int i = 0; i < MEM_BLOCK_SIZE; i++) { - if ((byteen >> i) & 0x1) { - auto& ss_buf = print_bufs_[i]; - char c = data[i]; - ss_buf << c; - if (c == '\n') { - std::cout << std::dec << "#" << i << ": " << ss_buf.str() << std::flush; - ss_buf.str(""); - } - } - } - } else { - for (int i = 0; i < MEM_BLOCK_SIZE; i++) { - if ((byteen >> i) & 0x1) { - (*ram_)[base_addr + i] = data[i]; - } - } - } - } else { - mem_req_t mem_req; - mem_req.tag = vortex_->mem_req_tag; - mem_req.addr = vortex_->mem_req_addr; - ram_->read(vortex_->mem_req_addr * MEM_BLOCK_SIZE, MEM_BLOCK_SIZE, mem_req.block.data()); - mem_req.cycles_left = MEM_LATENCY; - for (auto& rsp : mem_rsp_vec_[req_bank]) { - if (mem_req.addr == rsp.addr) { - mem_req.cycles_left = rsp.cycles_left; - break; - } - } - mem_rsp_vec_[req_bank].emplace_back(mem_req); - } - } - } - - vortex_->mem_req_ready = !mem_stalled; -} - -void Simulator::wait(uint32_t cycles) { - for (int i = 0; i < cycles; ++i) { - this->step(); - } -} - -bool Simulator::is_busy() const { - return vortex_->busy; -} - -int Simulator::run() { - int exitcode = 0; - -#ifndef NDEBUG - std::cout << std::dec << timestamp << ": [sim] run()" << std::endl; -#endif - - // execute program - while (vortex_->busy) { - if (get_ebreak()) { - exitcode = get_last_wb_value(3); - break; - } - this->step(); - } - - // wait 5 cycles to flush the pipeline - this->wait(5); - - return exitcode; -} - -bool Simulator::get_ebreak() const { - return (int)vortex_->Vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->execute->ebreak; -} - -int Simulator::get_last_wb_value(int reg) const { - return (int)vortex_->Vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_wb_value[reg]; -} - -void Simulator::load_bin(const char* program_file) { - if (ram_ == nullptr) - return; - - std::ifstream ifs(program_file); - if (!ifs) { - std::cout << "error: " << program_file << " not found" << std::endl; - } - - ifs.seekg(0, ifs.end); - auto size = ifs.tellg(); - std::vector content(size); - ifs.seekg(0, ifs.beg); - ifs.read((char*)content.data(), size); - - ram_->write(STARTUP_ADDR, size, content.data()); -} - -void Simulator::load_ihex(const char* program_file) { - if (ram_ == nullptr) - return; - - auto hti = [&](char c)->uint32_t { - if (c >= 'A' && c <= 'F') - return c - 'A' + 10; - if (c >= 'a' && c <= 'f') - return c - 'a' + 10; - return c - '0'; - }; - - auto hToI = [&](const char *c, uint32_t size)->uint32_t { - uint32_t value = 0; - for (uint32_t i = 0; i < size; i++) { - value += hti(c[i]) << ((size - i - 1) * 4); - } - return value; - }; - - std::ifstream ifs(program_file); - if (!ifs) { - std::cout << "error: " << program_file << " not found" << std::endl; - } - - ifs.seekg(0, ifs.end); - uint32_t size = ifs.tellg(); - std::vector content(size); - ifs.seekg(0, ifs.beg); - ifs.read(content.data(), size); - - int offset = 0; - char *line = content.data(); - - while (true) { - if (line[0] == ':') { - uint32_t byteCount = hToI(line + 1, 2); - uint32_t nextAddr = hToI(line + 3, 4) + offset; - uint32_t key = hToI(line + 7, 2); - switch (key) { - case 0: - for (uint32_t i = 0; i < byteCount; i++) { - (*ram_)[nextAddr + i] = hToI(line + 9 + i * 2, 2); - } - break; - case 2: - offset = hToI(line + 9, 4) << 4; - break; - case 4: - offset = hToI(line + 9, 4) << 16; - break; - default: - break; - } - } - while (*line != '\n' && size != 0) { - ++line; - --size; - } - if (size <= 1) - break; - ++line; - --size; - } -} - -void Simulator::print_stats(std::ostream& out) { - out << std::left; - out << std::setw(24) << "# of total cycles:" << std::dec << timestamp/2 << std::endl; -} \ No newline at end of file diff --git a/hw/simulate/verilator.vlt b/hw/simulate/verilator.vlt deleted file mode 100644 index dd69f119..00000000 --- a/hw/simulate/verilator.vlt +++ /dev/null @@ -1,10 +0,0 @@ -`verilator_config - -lint_off -rule BLKANDNBLK -file "../rtl/fp_cores/fpnew/*" -lint_off -rule UNOPTFLAT -file "../rtl/fp_cores/fpnew/*" -lint_off -rule WIDTH -file "../rtl/fp_cores/fpnew/*" -lint_off -rule UNUSED -file "../rtl/fp_cores/fpnew/*" -lint_off -rule LITENDIAN -file "../rtl/fp_cores/fpnew/*" -lint_off -rule IMPORTSTAR -file "../rtl/fp_cores/fpnew/*" -lint_off -rule PINCONNECTEMPTY -file "../rtl/fp_cores/fpnew/*" -lint_off -file "../rtl/fp_cores/fpnew/*" \ No newline at end of file diff --git a/hw/syn/opae/Makefile b/hw/syn/opae/Makefile index f83e7044..58d82a5d 100644 --- a/hw/syn/opae/Makefile +++ b/hw/syn/opae/Makefile @@ -26,11 +26,11 @@ DBG_FLAGS += -DDBG_CACHE_REQ_INFO CONFIG1 := -DNUM_CLUSTERS=1 -DNUM_CORES=1 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS) CONFIG2 := -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS) -CONFIG4 := -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS) -CONFIG8 := -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS) -CONFIG16 := -DNUM_CLUSTERS=4 -DNUM_CORES=4 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS) -CONFIG32 := -DNUM_CLUSTERS=8 -DNUM_CORES=4 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS) -CONFIG64 := -DNUM_CLUSTERS=8 -DNUM_CORES=8 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS) +CONFIG4 := -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1 -DL3_ENABLE=0 -DICACHE_SIZE=8192 -DDCACHE_SIZE=8192 -DL2_CACHE_SIZE=131072 $(CONFIGS) +CONFIG8 := -DNUM_CLUSTERS=1 -DNUM_CORES=8 -DL2_ENABLE=1 -DL3_ENABLE=0 -DICACHE_SIZE=8192 -DDCACHE_SIZE=8192 -DL2_CACHE_SIZE=131072 $(CONFIGS) +CONFIG16 := -DNUM_CLUSTERS=4 -DNUM_CORES=4 -DL2_ENABLE=0 -DL3_ENABLE=1 -DICACHE_SIZE=8192 -DDCACHE_SIZE=8192 -DL3_CACHE_SIZE=262144 $(CONFIGS) +CONFIG32 := -DNUM_CLUSTERS=4 -DNUM_CORES=8 -DL2_ENABLE=0 -DL3_ENABLE=1 -DICACHE_SIZE=8192 -DDCACHE_SIZE=8192 -DL3_CACHE_SIZE=262144 $(CONFIGS) +CONFIG64 := -DNUM_CLUSTERS=8 -DNUM_CORES=8 -DL2_ENABLE=0 -DL3_ENABLE=1 -DICACHE_SIZE=8192 -DDCACHE_SIZE=8192 -DL3_CACHE_SIZE=524288 $(CONFIGS) FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY) TEX_INCLUDE = -I$(RTL_DIR)/tex_unit @@ -55,7 +55,11 @@ ifdef PERF CFLAGS += -DPERF_ENABLE endif -all: ase-1c +all: vortex_afu.h ase-1c + +# AFU info from JSON file, including AFU UUID +vortex_afu.h: vortex_afu.json + afu_json_mgr json-info --afu-json=$^ --c-hdr=$@ $(BUILD_DIR)_ase_1c/Makefile: afu_sim_setup -s setup.cfg $(BUILD_DIR)_ase_1c @@ -197,4 +201,4 @@ clean-fpga-32c: clean-fpga-64c: rm -rf $(BUILD_DIR)_fpga_64c sources.txt -clean: clean-ase-1c clean-ase-2c clean-ase-4c clean-fpga-1c clean-fpga-2c clean-fpga-4c clean-fpga-8c clean-fpga-16c clean-fpga-32c clean-fpga-64c \ No newline at end of file +clean: vortex_afu.h clean-ase-1c clean-ase-2c clean-ase-4c clean-fpga-1c clean-fpga-2c clean-fpga-4c clean-fpga-8c clean-fpga-16c clean-fpga-32c clean-fpga-64c \ No newline at end of file diff --git a/hw/syn/opae/README b/hw/syn/opae/README index ae8bca51..1c23b88f 100644 --- a/hw/syn/opae/README +++ b/hw/syn/opae/README @@ -63,13 +63,13 @@ qsub-sim make ase # tests -./run_ase.sh build_ase_arria10_1c ../../../driver/tests/basic/basic -n1 -t0 -./run_ase.sh build_ase_arria10_1c ../../../driver/tests/basic/basic -n1 -t1 -./run_ase.sh build_ase_arria10_1c ../../../driver/tests/basic/basic -n16 -./run_ase.sh build_ase_arria10_1c ../../../driver/tests/demo/demo -n16 -./run_ase.sh build_ase_arria10_1c ../../../driver/tests/dogfood/dogfood -n16 -./run_ase.sh build_ase_arria10_1c ../../../benchmarks/opencl/vecadd/vecadd -./run_ase.sh build_ase_arria10_1c ../../../benchmarks/opencl/sgemm/sgemm -n4 +./run_ase.sh build_arria10_ase_1c ../../../tests/regression/basic/basic -n1 -t0 +./run_ase.sh build_arria10_ase_1c ../../../tests/regression/basic/basic -n1 -t1 +./run_ase.sh build_arria10_ase_1c ../../../tests/regression/basic/basic -n16 +./run_ase.sh build_arria10_ase_1c ../../../tests/regression/demo/demo -n16 +./run_ase.sh build_arria10_ase_1c ../../../tests/regression/dogfood/dogfood -n16 +./run_ase.sh build_arria10_ase_1c ../../../tests/opencl/vecadd/vecadd +./run_ase.sh build_arria10_ase_1c ../../../tests/opencl/sgemm/sgemm -n4 # modify "vsim_run.tcl" to dump VCD trace vcd file trace.vcd @@ -82,7 +82,7 @@ tar -zcvf output_files_1c.tar.gz `find ./build_fpga_1c -type f \( -iname \*.rpt # compress log trace tar -zcvf run.log.tar.gz run.log tar -cvjf trace.vcd.tar.bz2 trace.vcd run.log -tar -cvjf trace.vcd.tar.bz2 build_ase_arria10_1c/work/run.log build_ase_arria10_1c/work/trace.vcd +tar -cvjf trace.vcd.tar.bz2 build_arria10_ase_1c/work/run.log build_arria10_ase_1c/work/trace.vcd # decompress log trace tar -zxvf vortex.vcd.tar.gz diff --git a/hw/syn/opae/fpga_prog.sh b/hw/syn/opae/fpga_prog.sh new file mode 100755 index 00000000..4fc9db22 --- /dev/null +++ b/hw/syn/opae/fpga_prog.sh @@ -0,0 +1,7 @@ +#!/bin/bash + +# FPGA programming +# first argument is the bitstream + +echo "fpgaconf --bus 0xaf $1" +fpgaconf --bus 0xaf $1 \ No newline at end of file diff --git a/hw/syn/opae/gen_sources.sh b/hw/syn/opae/gen_sources.sh index b330efc1..a320f53a 100755 --- a/hw/syn/opae/gen_sources.sh +++ b/hw/syn/opae/gen_sources.sh @@ -1,6 +1,6 @@ #!/bin/bash -exclude_list="VX_fpu_fpnew.v" +exclude_list="VX_fpu_fpnew.sv" macros=() includes=() diff --git a/hw/syn/opae/run_ase.sh b/hw/syn/opae/run_ase.sh index 9d7d6360..86b74121 100755 --- a/hw/syn/opae/run_ase.sh +++ b/hw/syn/opae/run_ase.sh @@ -35,5 +35,5 @@ done # run application pushd $PROGRAM_DIR echo " [DBG] running ./$PROGRAM $*" -ASE_LOG=0 LD_LIBRARY_PATH=$POCL_RT_PATH/lib:$VORTEX_DRV_PATH/opae/ase:$LD_LIBRARY_PATH ./$PROGRAM $* +ASE_LOG=0 LD_LIBRARY_PATH=$POCL_RT_PATH/lib:$VORTEX_DRV_PATH/asesim:$LD_LIBRARY_PATH ./$PROGRAM $* popd \ No newline at end of file diff --git a/hw/syn/opae/vortex_afu.qsf b/hw/syn/opae/vortex_afu.qsf index 0c7e4cbd..1628f9d8 100644 --- a/hw/syn/opae/vortex_afu.qsf +++ b/hw/syn/opae/vortex_afu.qsf @@ -23,12 +23,12 @@ set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_global_assignment -name USE_HIGH_SPEED_ADDER ON -set_global_assignment -name MUX_RESTRUCTURE ON -set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "FORCE ALL TILES WITH FAILING TIMING PATHS TO HIGH SPEED" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +#set_global_assignment -name USE_HIGH_SPEED_ADDER ON +#set_global_assignment -name MUX_RESTRUCTURE ON +#set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON +#set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "FORCE ALL TILES WITH FAILING TIMING PATHS TO HIGH SPEED" +#set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +#set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 diff --git a/hw/syn/quartus/.gitignore b/hw/syn/quartus/.gitignore index 7a0867fe..4b27eaab 100644 --- a/hw/syn/quartus/.gitignore +++ b/hw/syn/quartus/.gitignore @@ -7,6 +7,9 @@ /cache/* !/cache/Makefile +/fpu_core/* +!/fpu_core/Makefile + /vortex/* !/vortex/Makefile diff --git a/hw/syn/quartus/Makefile b/hw/syn/quartus/Makefile index d15644fe..662848e1 100644 --- a/hw/syn/quartus/Makefile +++ b/hw/syn/quartus/Makefile @@ -1,6 +1,11 @@ BUILD_DIR ?= build -.PHONY: unittest pipeline smem cache core vortex top1 top2 top4 top8 top16 top32 top64 +.PHONY: dogfood unittest pipeline smem cache fpu_core core vortex top1 top2 top4 top8 top16 top32 top64 + +dogfood: + mkdir -p dogfood/$(BUILD_DIR) + cp dogfood/Makefile dogfood/$(BUILD_DIR) + $(MAKE) -C dogfood/$(BUILD_DIR) clean && $(MAKE) -C dogfood/$(BUILD_DIR) > dogfood/$(BUILD_DIR)/build.log 2>&1 & unittest: mkdir -p unittest/$(BUILD_DIR) @@ -22,6 +27,11 @@ cache: cp cache/Makefile cache/$(BUILD_DIR) $(MAKE) -C cache/$(BUILD_DIR) clean && $(MAKE) -C cache/$(BUILD_DIR) > cache/$(BUILD_DIR)/build.log 2>&1 & +fpu_core: + mkdir -p fpu_core/$(BUILD_DIR) + cp fpu_core/Makefile fpu_core/$(BUILD_DIR) + $(MAKE) -C fpu_core/$(BUILD_DIR) clean && $(MAKE) -C fpu_core/$(BUILD_DIR) > fpu_core/$(BUILD_DIR)/build.log 2>&1 & + core: mkdir -p core/$(BUILD_DIR) cp core/Makefile core/$(BUILD_DIR) diff --git a/hw/syn/quartus/fpu_core/Makefile b/hw/syn/quartus/fpu_core/Makefile new file mode 100644 index 00000000..291d8124 --- /dev/null +++ b/hw/syn/quartus/fpu_core/Makefile @@ -0,0 +1,86 @@ +PROJECT = VX_fpu_fpga +TOP_LEVEL_ENTITY = VX_fpu_fpga +SRC_FILE = VX_fpu_fpga.v +RTL_DIR = ../../../../rtl + +FAMILY = "Arria 10" +DEVICE = 10AX115N3F40E2SG +FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10 + +#FAMILY = "Stratix 10" +#DEVICE = 1SX280HN2F43E2VG +#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10 + +FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src +RTL_INCLUDE = $(FPU_INCLUDE);$(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces +PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf + +# Part, Family +FAMILY = "Arria 10" +DEVICE = 10AX115N3F40E2SG + +# Executable Configuration +SYN_ARGS = --parallel --read_settings_files=on +FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on +ASM_ARGS = +STA_ARGS = --parallel --do_report_timing + +# Build targets +all: $(PROJECT).sta.rpt + +syn: $(PROJECT).syn.rpt + +fit: $(PROJECT).fit.rpt + +asm: $(PROJECT).asm.rpt + +sta: $(PROJECT).sta.rpt + +smart: smart.log + +# Target implementations +STAMP = echo done > + +$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) + quartus_syn $(PROJECT) $(SYN_ARGS) + $(STAMP) fit.chg + +$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt + quartus_fit $(PROJECT) $(FIT_ARGS) + $(STAMP) asm.chg + $(STAMP) sta.chg + +$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt + quartus_asm $(PROJECT) $(ASM_ARGS) + +$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt + quartus_sta $(PROJECT) $(STA_ARGS) + +smart.log: $(PROJECT_FILES) + quartus_sh --determine_smart_action $(PROJECT) > smart.log + +# Project initialization +$(PROJECT_FILES): + quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" +# -set "FPU_CVT2" + +syn.chg: + $(STAMP) syn.chg + +fit.chg: + $(STAMP) fit.chg + +sta.chg: + $(STAMP) sta.chg + +asm.chg: + $(STAMP) asm.chg + +timing: $(PROJECT_FILES) + quartus_sh -t ../../timing-html.tcl -project $(PROJECT) + +program: $(PROJECT).sof + quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof" + +clean: + rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/hw/syn/quartus/pipeline/Makefile b/hw/syn/quartus/pipeline/Makefile index 6de824b8..e4cad107 100644 --- a/hw/syn/quartus/pipeline/Makefile +++ b/hw/syn/quartus/pipeline/Makefile @@ -1,7 +1,7 @@ PROJECT = VX_pipeline TOP_LEVEL_ENTITY = VX_pipeline SRC_FILE = VX_pipeline.v -RTL_DIR = ../../../rtl +RTL_DIR = ../../../../rtl FAMILY = "Arria 10" DEVICE = 10AX115N3F40E2SG diff --git a/hw/syn/quartus/project.sdc b/hw/syn/quartus/project.sdc index c45de03e..797606f7 100644 --- a/hw/syn/quartus/project.sdc +++ b/hw/syn/quartus/project.sdc @@ -1,4 +1,4 @@ -create_clock -name {clk} -period "220 MHz" [get_ports {clk}] +create_clock -name {clk} -period "250 MHz" [get_ports {clk}] derive_pll_clocks -create_base_clocks derive_clock_uncertainty \ No newline at end of file diff --git a/hw/syn/quartus/top16/Makefile b/hw/syn/quartus/top16/Makefile index 055740b7..78f4df68 100644 --- a/hw/syn/quartus/top16/Makefile +++ b/hw/syn/quartus/top16/Makefile @@ -59,7 +59,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" -set "NUM_CLUSTERS=4" + quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" -set "NUM_CLUSTERS=4" -set "L2_ENABLE=0" -set "L3_ENABLE=1" -set "ICACHE_SIZE=8192" -set "DCACHE_SIZE=8192" -set "L3_CACHE_SIZE=262144" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/quartus/top32/Makefile b/hw/syn/quartus/top32/Makefile index a565fca2..cea702f5 100644 --- a/hw/syn/quartus/top32/Makefile +++ b/hw/syn/quartus/top32/Makefile @@ -3,13 +3,13 @@ TOP_LEVEL_ENTITY = vortex_afu SRC_FILE = vortex_afu.sv RTL_DIR = ../../../../rtl -#FAMILY = "Arria 10" -#DEVICE = 10AX115N3F40E2SG -#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10 +FAMILY = "Arria 10" +DEVICE = 10AX115N3F40E2SG +FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10 -FAMILY = "Stratix 10" -DEVICE = 1SX280HN2F43E2VG -FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10 +#FAMILY = "Stratix 10" +#DEVICE = 1SX280HN2F43E2VG +#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10 FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src TEX_INCLUDE = $(RTL_DIR)/tex_unit @@ -59,7 +59,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" -set "NUM_CLUSTERS=8" + quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=8" -set "NUM_CLUSTERS=4" -set "L2_ENABLE=0" -set "L3_ENABLE=1" -set "ICACHE_SIZE=8192" -set "DCACHE_SIZE=8192" -set "L3_CACHE_SIZE=262144" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/quartus/top4/Makefile b/hw/syn/quartus/top4/Makefile index 93699407..bfe734a7 100644 --- a/hw/syn/quartus/top4/Makefile +++ b/hw/syn/quartus/top4/Makefile @@ -59,8 +59,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" - + quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" -set "NUM_CLUSTERS=1" -set "L2_ENABLE=1" -set "L3_ENABLE=0" -set "ICACHE_SIZE=8192" -set "DCACHE_SIZE=8192" -set "L2_CACHE_SIZE=65536" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/quartus/top64/Makefile b/hw/syn/quartus/top64/Makefile index 17d7a2aa..604f794f 100644 --- a/hw/syn/quartus/top64/Makefile +++ b/hw/syn/quartus/top64/Makefile @@ -59,7 +59,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=8" -set "NUM_CLUSTERS=8" + quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=8" -set "NUM_CLUSTERS=8" -set "L2_ENABLE=0" -set "L3_ENABLE=1" -set "ICACHE_SIZE=8192" -set "DCACHE_SIZE=8192" -set "L3_CACHE_SIZE=524288" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/quartus/top8/Makefile b/hw/syn/quartus/top8/Makefile index d3287844..0614e0d5 100644 --- a/hw/syn/quartus/top8/Makefile +++ b/hw/syn/quartus/top8/Makefile @@ -59,7 +59,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" -set "NUM_CLUSTERS=2" + quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=8" -set "NUM_CLUSTERS=1" -set "L2_ENABLE=1" -set "L3_ENABLE=0" -set "ICACHE_SIZE=8192" -set "DCACHE_SIZE=8192" -set "L2_CACHE_SIZE=131072" syn.chg: $(STAMP) syn.chg diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/Makefile b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/Makefile similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/Makefile rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/Makefile diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/env_vsim b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/env_vsim similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/env_vsim rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/env_vsim diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.bitmap b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.bitmap similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.bitmap rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.bitmap diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.cpf b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.cpf similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.cpf rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.cpf diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.ctl b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.ctl similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.ctl rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.ctl diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.lef b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.lef similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.lef rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.lef diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.mdt b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.mdt similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.mdt rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.mdt diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.memlib b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.memlib similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.memlib rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.memlib diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.tv b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.tv similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.tv rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.tv diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_antenna.clf b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_antenna.clf similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_antenna.clf rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_antenna.clf diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.avm b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.avm similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.avm rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.avm diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.dat b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.dat similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.dat rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.dat diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.lib b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.lib similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.lib rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.lib diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.lib_sh5p1cm b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.lib_sh5p1cm similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.lib_sh5p1cm rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.lib_sh5p1cm diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.ps b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.ps similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.ps rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.ps diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_rtl.v b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_rtl.v similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_rtl.v rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_rtl.v diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ss_0p81v_0p81v_125c.avm b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ss_0p81v_0p81v_125c.avm similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ss_0p81v_0p81v_125c.avm rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ss_0p81v_0p81v_125c.avm diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ss_0p81v_0p81v_125c.dat b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ss_0p81v_0p81v_125c.dat similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ss_0p81v_0p81v_125c.dat rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ss_0p81v_0p81v_125c.dat diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ss_0p81v_0p81v_125c.lib b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ss_0p81v_0p81v_125c.lib similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ss_0p81v_0p81v_125c.lib rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ss_0p81v_0p81v_125c.lib diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ss_0p81v_0p81v_125c.ps b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ss_0p81v_0p81v_125c.ps similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ss_0p81v_0p81v_125c.ps rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ss_0p81v_0p81v_125c.ps diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_tt_0p81v_0p81v_0c.avm b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_tt_0p81v_0p81v_0c.avm similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_tt_0p81v_0p81v_0c.avm rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_tt_0p81v_0p81v_0c.avm diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_tt_0p81v_0p81v_0c.dat b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_tt_0p81v_0p81v_0c.dat similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_tt_0p81v_0p81v_0c.dat rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_tt_0p81v_0p81v_0c.dat diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_tt_0p81v_0p81v_0c.lib b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_tt_0p81v_0p81v_0c.lib similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_tt_0p81v_0p81v_0c.lib rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_tt_0p81v_0p81v_0c.lib diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_tt_0p81v_0p81v_0c.ps b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_tt_0p81v_0p81v_0c.ps similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_tt_0p81v_0p81v_0c.ps rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_tt_0p81v_0p81v_0c.ps diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/testbench.cpp b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/testbench.cpp similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/testbench.cpp rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/testbench.cpp diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf2_32x128_wm1_tb.v b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf2_32x128_wm1_tb.v similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf2_32x128_wm1_tb.v rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf2_32x128_wm1_tb.v diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf_tb.cr.mti b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf_tb.cr.mti similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf_tb.cr.mti rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf_tb.cr.mti diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf_tb.mpf b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf_tb.mpf similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf_tb.mpf rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf_tb.mpf diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/vsim/transcript b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/vsim/transcript similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/vsim/transcript rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/vsim/transcript diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/vsim/vsim.wlf b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/vsim/vsim.wlf similarity index 100% rename from hw/models/memory/cln28hpc/rf2_32x128_wm1/vsim/vsim.wlf rename to hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/vsim/vsim.wlf diff --git a/hw/models/memory/cln28hpc/rf2_32x128_wm1/vsim/work/@_opt/_lib.qdb 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diff --git a/hw/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x128_wm1_ff_0p99v_0p99v_125c.db b/hw/syn/synopsys/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x128_wm1_ff_0p99v_0p99v_125c.db similarity index 100% rename from hw/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x128_wm1_ff_0p99v_0p99v_125c.db rename to hw/syn/synopsys/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x128_wm1_ff_0p99v_0p99v_125c.db diff --git a/hw/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db b/hw/syn/synopsys/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db similarity index 100% rename from hw/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db rename to hw/syn/synopsys/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db diff --git a/hw/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x128_wm1_tt_0p90v_0p90v_25c.db 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a/hw/models/memory/cln28hpm/2d_hardmacro_db/rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db b/hw/syn/synopsys/models/memory/cln28hpm/2d_hardmacro_db/rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db similarity index 100% rename from hw/models/memory/cln28hpm/2d_hardmacro_db/rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db rename to hw/syn/synopsys/models/memory/cln28hpm/2d_hardmacro_db/rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db diff --git a/hw/models/memory/cln28hpm/2d_hardmacro_db/rf2_32x128_wm1_tt_0p90v_0p90v_25c.db b/hw/syn/synopsys/models/memory/cln28hpm/2d_hardmacro_db/rf2_32x128_wm1_tt_0p90v_0p90v_25c.db similarity index 100% rename from hw/models/memory/cln28hpm/2d_hardmacro_db/rf2_32x128_wm1_tt_0p90v_0p90v_25c.db rename to hw/syn/synopsys/models/memory/cln28hpm/2d_hardmacro_db/rf2_32x128_wm1_tt_0p90v_0p90v_25c.db diff --git a/hw/models/memory/cln28hpm/convertToDBAll.csh b/hw/syn/synopsys/models/memory/cln28hpm/convertToDBAll.csh similarity index 100% rename from hw/models/memory/cln28hpm/convertToDBAll.csh rename to hw/syn/synopsys/models/memory/cln28hpm/convertToDBAll.csh diff --git a/hw/models/memory/cln28hpm/convert_lib_to_db.tcl b/hw/syn/synopsys/models/memory/cln28hpm/convert_lib_to_db.tcl similarity index 100% rename from hw/models/memory/cln28hpm/convert_lib_to_db.tcl rename to hw/syn/synopsys/models/memory/cln28hpm/convert_lib_to_db.tcl diff --git a/hw/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.bitmap b/hw/syn/synopsys/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.bitmap similarity index 100% rename from hw/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.bitmap rename to hw/syn/synopsys/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.bitmap diff --git a/hw/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.cpf b/hw/syn/synopsys/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.cpf similarity index 100% rename from hw/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.cpf rename to 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a/hw/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1_ss_0p81v_0p81v_m40c.avm b/hw/syn/synopsys/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1_ss_0p81v_0p81v_m40c.avm similarity index 100% rename from hw/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1_ss_0p81v_0p81v_m40c.avm rename to hw/syn/synopsys/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1_ss_0p81v_0p81v_m40c.avm diff --git a/hw/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1_ss_0p81v_0p81v_m40c.dat b/hw/syn/synopsys/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1_ss_0p81v_0p81v_m40c.dat similarity index 100% rename from hw/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1_ss_0p81v_0p81v_m40c.dat rename to hw/syn/synopsys/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1_ss_0p81v_0p81v_m40c.dat diff --git a/hw/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1_ss_0p81v_0p81v_m40c.db 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a/hw/models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.ctl b/hw/syn/synopsys/models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.ctl similarity index 100% rename from hw/models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.ctl rename to hw/syn/synopsys/models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.ctl diff --git a/hw/models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.lef b/hw/syn/synopsys/models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.lef similarity index 100% rename from hw/models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.lef rename to hw/syn/synopsys/models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.lef diff --git a/hw/models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.mdt b/hw/syn/synopsys/models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.mdt similarity index 100% rename from hw/models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.mdt rename to hw/syn/synopsys/models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.mdt diff --git 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hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0.v diff --git a/hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_antenna.clf b/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_antenna.clf similarity index 100% rename from hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_antenna.clf rename to hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_antenna.clf diff --git a/hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ff_0p99v_0p99v_125c.avm b/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ff_0p99v_0p99v_125c.avm similarity index 100% rename from hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ff_0p99v_0p99v_125c.avm rename to hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ff_0p99v_0p99v_125c.avm diff --git a/hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ff_0p99v_0p99v_125c.dat b/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ff_0p99v_0p99v_125c.dat similarity index 100% rename from hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ff_0p99v_0p99v_125c.dat rename to hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ff_0p99v_0p99v_125c.dat diff --git a/hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ff_0p99v_0p99v_125c.lib b/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ff_0p99v_0p99v_125c.lib similarity index 100% rename from hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ff_0p99v_0p99v_125c.lib rename to hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ff_0p99v_0p99v_125c.lib diff --git a/hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ff_0p99v_0p99v_125c.ps b/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ff_0p99v_0p99v_125c.ps similarity index 100% rename from hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ff_0p99v_0p99v_125c.ps rename to hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ff_0p99v_0p99v_125c.ps diff --git a/hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_rtl.v b/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_rtl.v similarity index 100% rename from hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_rtl.v rename to hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_rtl.v diff --git a/hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ss_0p81v_0p81v_m40c.avm b/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ss_0p81v_0p81v_m40c.avm similarity index 100% rename from hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ss_0p81v_0p81v_m40c.avm rename to hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ss_0p81v_0p81v_m40c.avm diff --git a/hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ss_0p81v_0p81v_m40c.dat b/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ss_0p81v_0p81v_m40c.dat similarity index 100% rename from hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ss_0p81v_0p81v_m40c.dat rename to hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ss_0p81v_0p81v_m40c.dat diff --git a/hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ss_0p81v_0p81v_m40c.lib b/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ss_0p81v_0p81v_m40c.lib similarity index 100% rename from hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ss_0p81v_0p81v_m40c.lib rename to hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ss_0p81v_0p81v_m40c.lib diff --git a/hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ss_0p81v_0p81v_m40c.ps b/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ss_0p81v_0p81v_m40c.ps similarity index 100% rename from hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ss_0p81v_0p81v_m40c.ps rename to hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ss_0p81v_0p81v_m40c.ps diff --git a/hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_tt_0p90v_0p90v_25c.avm b/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_tt_0p90v_0p90v_25c.avm similarity index 100% rename from hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_tt_0p90v_0p90v_25c.avm rename to hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_tt_0p90v_0p90v_25c.avm diff --git a/hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_tt_0p90v_0p90v_25c.dat b/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_tt_0p90v_0p90v_25c.dat similarity index 100% rename from hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_tt_0p90v_0p90v_25c.dat rename to hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_tt_0p90v_0p90v_25c.dat diff --git a/hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_tt_0p90v_0p90v_25c.lib b/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_tt_0p90v_0p90v_25c.lib similarity index 100% rename from hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_tt_0p90v_0p90v_25c.lib rename to hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_tt_0p90v_0p90v_25c.lib diff --git a/hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_tt_0p90v_0p90v_25c.ps b/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_tt_0p90v_0p90v_25c.ps similarity index 100% rename from hw/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_tt_0p90v_0p90v_25c.ps rename to hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_tt_0p90v_0p90v_25c.ps diff --git a/hw/syn/yosys/Makefile b/hw/syn/yosys/Makefile new file mode 100644 index 00000000..6ac5f6a0 --- /dev/null +++ b/hw/syn/yosys/Makefile @@ -0,0 +1,20 @@ +PROJECT = Vortex +TOP_LEVEL_ENTITY = Vortex +SRC_FILE = Vortex.sv +RTL_DIR = ../../rtl + +DEFINES = -DNDEBUG -DSYNTHESIS -DEXT_F_DISABLE -DNUM_CORES=1 -DNUM_THREADS=2 -DNUM_WARPS=2 -DMEM_BLOCK_SIZE=64 + +RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache + +# Build targets +all: build + +output.v: + ./sv2v.sh $(DEFINES) $(RTL_INCLUDE) -ooutput.v + +build: output.v + ./synth.sh -t$(TOP_LEVEL_ENTITY) -soutput.v + +clean: + rm -rf output.v *.ys *.log diff --git a/hw/syn/yosys/diagram.ys b/hw/syn/yosys/diagram.ys deleted file mode 100644 index 7e1e5440..00000000 --- a/hw/syn/yosys/diagram.ys +++ /dev/null @@ -1,5 +0,0 @@ -# load design -read_verilog -sv -I../../rtl -I../../rtl/libs -I../../rtl/interfaces -I../../rtl/pipe_regs -I../../rtl/cache ../../rtl/Vortex.v - -# dump diagram -show diff --git a/hw/syn/yosys/sv2v.sh b/hw/syn/yosys/sv2v.sh new file mode 100755 index 00000000..cf5abaaf --- /dev/null +++ b/hw/syn/yosys/sv2v.sh @@ -0,0 +1,57 @@ +#!/bin/bash + +# this script uses sv2v and yosys tools to run. +# sv2v: https://github.com/zachjs/sv2v +# yosys: http://www.clifford.at/yosys/ + +# exit when any command fails +set -e + +source="" +includes=() +macro_args="" +output_file=out.v + +usage() { echo "$0 usage:" && grep " .)\ #" $0; exit 0; } +[ $# -eq 0 ] && usage +while getopts "o:I:D:h" arg; do + case $arg in + s) # source + source=${OPTARG} + ;; + o) # output-file + output_file=${OPTARG} + ;; + I) # include directory + includes+=(${OPTARG}) + ;; + D) # macro definition + macro_args="$macro_args -D${OPTARG}" + ;; + h | *) + usage + exit 0 + ;; + esac +done + +# process include paths +inc_args="" +for dir in "${includes[@]}" +do + inc_args="$inc_args -I$dir" +done + +# process source files +file_args=$source +for dir in "${includes[@]}" +do + for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f) + do + echo "file: $file" + file_args="$file_args $file" + done +done + +# system-verilog to verilog conversion +sv2v $macro_args $inc_args $file_args -v -w $output_file \ No newline at end of file diff --git a/hw/syn/yosys/synth.sh b/hw/syn/yosys/synth.sh index 544bbad0..07528757 100755 --- a/hw/syn/yosys/synth.sh +++ b/hw/syn/yosys/synth.sh @@ -1,32 +1,65 @@ #!/bin/bash -dir_list='../../rtl/libs ../../rtl/cache ../../rtl/interfaces ../../rtl' +# this script uses sv2v and yosys tools to run. +# sv2v: https://github.com/zachjs/sv2v +# yosys: http://www.clifford.at/yosys/ -inc_list="" -for dir in $dir_list; do - inc_list="$inc_list -I$dir" +# exit when any command fails +set -e + +source="" +top_level="" +dir_list=() +inc_args="" +macro_args="" + +usage() { echo "$0 usage:" && grep " .)\ #" $0; exit 0; } +[ $# -eq 0 ] && usage +while getopts "s:t:I:D:h" arg; do + case $arg in + s) # source + source=${OPTARG} + ;; + t) # top-level + top_level=${OPTARG} + ;; + I) # include directory + dir_list+=(${OPTARG}) + inc_args="$inc_args -I${OPTARG}" + ;; + D) # macro definition + macro_args="$macro_args -D${OPTARG}" + ;; + h | *) + usage + exit 0 + ;; + esac done -echo "inc_list=$inc_list" - -{ +{ # read design sources - for dir in $dir_list; do + for dir in "${dir_list[@]}" + do for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f) do - echo "read_verilog -sv $inc_list $file" + echo "read_verilog $macro_args $inc_args -sv $file" done done + if [ -n "$source" ]; then + echo "read_verilog $macro_args $inc_args -sv $source" + fi - echo "hierarchy -check -top Vortex" + # generic synthesis + echo "synth -top $top_level" - # insertation of global reset - echo "add -global_input reset 1" - echo "proc -global_arst reset" + # mapping to mycells.lib + echo "dfflibmap -liberty mycells.lib" + echo "abc -liberty mycells.lib" + echo "clean" - echo "synth -run coarse; opt -fine" - echo "tee -o brams.log memory_bram -rules scripts/brams.txt;;" - echo "write_verilog -noexpr -noattr synth.v" + # write synthesized design + echo "write_verilog synth.v" } > synth.ys -yosys -l synth.log synth.ys \ No newline at end of file +yosys -l yosys.log synth.ys \ No newline at end of file diff --git a/hw/syn/yosys/synth.ys b/hw/syn/yosys/synth.ys deleted file mode 100644 index f3ac0b0e..00000000 --- a/hw/syn/yosys/synth.ys +++ /dev/null @@ -1,99 +0,0 @@ -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_bypass_buffer.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_cam_buffer.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_countones.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_divide.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_elastic_buffer.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_fair_arbiter.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_fixed_arbiter.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_generic_queue.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_generic_register.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_index_queue.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_matrix_arbiter.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_multiplier.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_onehot_encooder.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_priority_encoder.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_rr_arbiter.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_scope.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_serial_div.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_shift_register.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_skid_buffer.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_bank.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_bank_core_req_arb.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_core_req_bank_sel.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_core_rsp_merge.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_dram_fill_arb.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_dram_req_arb.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_miss_resrv.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_snp_forwarder.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_snp_rsp_arb.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_tag_data_access.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_tag_data_store.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_alu_req_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_branch_ctl_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_core_req_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_core_rsp_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_dram_req_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_dram_rsp_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_snp_req_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_snp_rsp_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cmt_to_csr_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_csr_io_req_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_csr_io_rsp_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_csr_req_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_csr_to_issue_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_decode_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_exu_to_cmt_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_fpu_req_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_fpu_to_cmt_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_fpu_to_csr_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_gpr_req_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_gpr_rsp_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_gpu_req_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_ifetch_req_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_ifetch_rsp_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_join_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_lsu_req_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_mul_req_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_warp_ctl_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_writeback_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_wstall_if.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_alu_unit.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_cluster.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_commit.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_core.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_csr_arb.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_csr_data.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_csr_io_arb.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_csr_unit.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_dcache_arb.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_decode.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_execute.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_fetch.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_fpu_unit.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_gpr_bypass.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_gpr_fp_ctrl.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_gpr_ram.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_gpr_stage.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_gpu_unit.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_ibuffer.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_icache_stage.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_instr_demux.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_io_arb.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_ipdom_stack.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_issue.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_lsu_unit.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_mem_arb.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_mem_unit.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_mul_unit.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_pipeline.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_scoreboard.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_warp_sched.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_writeback.v -read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/Vortex.v -hierarchy -check -top Vortex -add -global_input reset 1 -proc -global_arst reset -synth -run coarse; opt -fine -tee -o brams.log memory_bram -rules scripts/brams.txt;; -write_verilog -noexpr -noattr synth.v diff --git a/hw/unit_tests/cache/Makefile b/hw/unit_tests/cache/Makefile index d430badc..b2211887 100644 --- a/hw/unit_tests/cache/Makefile +++ b/hw/unit_tests/cache/Makefile @@ -1,6 +1,4 @@ -TOP = VX_cache - -PARAMS += -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DCACHE_LINE_SIZE=16 -DNUM_BANKS=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 +PARAMS += -DCACHE_SIZE=4096 -DCACHE_WORD_SIZE=4 -DCACHE_LINE_SIZE=16 -DCACHE_NUM_BANKS=4 -DCACHE_CREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 # control RTL debug print states DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \ diff --git a/runtime/Makefile b/runtime/Makefile index fe486999..60c3b398 100644 --- a/runtime/Makefile +++ b/runtime/Makefile @@ -26,7 +26,7 @@ $(PROJECT).dump: $(PROJECT).a $(CC) $(CFLAGS) -c $< -o $@ $(PROJECT).a: $(OBJS) - $(AR) rc $(PROJECT).a $^ + $(AR) rcs $(PROJECT).a $^ .depend: $(SRCS) $(CC) $(CFLAGS) -MM $^ > .depend; diff --git a/runtime/include/vx_intrinsics.h b/runtime/include/vx_intrinsics.h index e624455d..d8b5d50c 100644 --- a/runtime/include/vx_intrinsics.h +++ b/runtime/include/vx_intrinsics.h @@ -118,8 +118,13 @@ extern "C" { }) // Set thread mask -inline void vx_tmc(unsigned num_threads) { - asm volatile (".insn s 0x6b, 0, x0, 0(%0)" :: "r"(num_threads)); +inline void vx_tmc(unsigned thread_mask) { + asm volatile (".insn s 0x6b, 0, x0, 0(%0)" :: "r"(thread_mask)); +} + +// Set thread predicate +inline void vx_pred(unsigned condition) { + asm volatile (".insn s 0x6b, 0, x1, 0(%0)" :: "r"(condition)); } typedef void (*vx_wspawn_pfn)(); @@ -186,6 +191,13 @@ inline int vx_core_id() { return result; } +// Return current threadk mask +inline int vx_thread_mask() { + int result; + asm volatile ("csrr %0, %1" : "=r"(result) : "i"(CSR_TMASK)); + return result; +} + // Return the number of threads in a warp inline int vx_num_threads() { int result; diff --git a/runtime/include/vx_print.h b/runtime/include/vx_print.h index c0ecd392..fde2cbe6 100644 --- a/runtime/include/vx_print.h +++ b/runtime/include/vx_print.h @@ -9,7 +9,10 @@ extern "C" { int vx_vprintf(const char* format, va_list va); int vx_printf(const char * format, ...); -int vx_putchar(int c); + +void vx_putchar(int c); +void vx_putint(int value, int base); +void vx_putfloat(float value, int precision); #ifdef __cplusplus } diff --git a/runtime/include/vx_spawn.h b/runtime/include/vx_spawn.h index 9d246e06..905f22a5 100644 --- a/runtime/include/vx_spawn.h +++ b/runtime/include/vx_spawn.h @@ -8,7 +8,7 @@ extern "C" { #endif -struct context_t { +typedef struct { uint32_t num_groups[3]; uint32_t global_offset[3]; uint32_t local_size[3]; @@ -16,11 +16,11 @@ struct context_t { uint32_t *printf_buffer_position; uint32_t printf_buffer_capacity; uint32_t work_dim; -}; +} context_t; typedef void (*vx_spawn_kernel_cb) ( const void * /* arg */, - const struct context_t * /* context */, + const context_t * /* context */, uint32_t /* group_x */, uint32_t /* group_y */, uint32_t /* group_z */ @@ -28,9 +28,9 @@ typedef void (*vx_spawn_kernel_cb) ( typedef void (*vx_spawn_tasks_cb)(int task_id, void *arg); -typedef void (*vx_serial_cb)(int task_id, void *arg); +typedef void (*vx_serial_cb)(void *arg); -void vx_spawn_kernel(struct context_t * ctx, vx_spawn_kernel_cb callback, void * arg); +void vx_spawn_kernel(context_t * ctx, vx_spawn_kernel_cb callback, void * arg); void vx_spawn_tasks(int num_tasks, vx_spawn_tasks_cb callback, void * arg); diff --git a/runtime/src/vx_print.c b/runtime/src/vx_print.c index e3e93190..b43cdd4a 100644 --- a/runtime/src/vx_print.c +++ b/runtime/src/vx_print.c @@ -4,28 +4,37 @@ #include #include #include +#include #ifdef __cplusplus extern "C" { #endif -struct printf_arg_t { +typedef struct { const char* format; - va_list va; + va_list* va; int ret; -}; +} printf_arg_t; -static void __printf_callback(int task_id, void* arg) { - struct printf_arg_t* p_arg = (struct printf_arg_t*)(arg); - p_arg->ret = vprintf(p_arg->format, p_arg->va); +typedef struct { + int value; + int base; +} putint_arg_t; + +typedef struct { + float value; + int precision; +} putfloat_arg_t; + +static void __printf_cb(printf_arg_t* arg) { + arg->ret = vprintf(arg->format, *arg->va); } int vx_vprintf(const char* format, va_list va) { - // need to execute 'vprintf' single-threaded due to potential thread-data dependency - struct printf_arg_t arg; + printf_arg_t arg; arg.format = format; - arg.va = va; - vx_serial(__printf_callback, &arg); + arg.va = &va; + vx_serial(__printf_cb, &arg); return arg.ret; } @@ -38,6 +47,45 @@ int vx_printf(const char * format, ...) { return ret; } +static void __putint_cb(const putint_arg_t* arg) { + char tmp[33]; + float value = arg->value; + int base = arg->base; + itoa(value, tmp, base); + for (int i = 0; i < 33; ++i) { + int c = tmp[i]; + if (!c) break; + vx_putchar(c); + } +} + +void vx_putint(int value, int base) { + putint_arg_t arg; + arg.value = value; + arg.base = base; + vx_serial(__putint_cb, &arg); +} + +static void __putfloat_cb(const putfloat_arg_t* arg) { + float value = arg->value; + int precision = arg->precision; + int ipart = (int)value; + vx_putint(ipart, 10); + if (precision != 0) { + vx_putchar('.'); + float frac = value - (float)ipart; + float fscaled = frac * pow(10, precision); + vx_putint((int)fscaled, 10); + } +} + +void vx_putfloat(float value, int precision) { + putfloat_arg_t arg; + arg.value = value; + arg.precision = precision; + vx_serial(__putfloat_cb, &arg); +} + #ifdef __cplusplus } #endif \ No newline at end of file diff --git a/runtime/src/vx_spawn.S b/runtime/src/vx_spawn.S index cf9caa48..d2388ce9 100644 --- a/runtime/src/vx_spawn.S +++ b/runtime/src/vx_spawn.S @@ -1,3 +1,5 @@ +#include + .type vx_serial, @function .global vx_serial vx_serial: @@ -8,23 +10,22 @@ vx_serial: sw s2, 8(sp) sw s1, 4(sp) sw s0, 0(sp) - mv s4, a0 # callback - mv s3, a1 # arg - csrr s2, 0xfc0 # NT - csrr s1, 0xcc0 # tid - li s0, 0 # index + mv s4, a0 # s4 <- callback + mv s3, a1 # s3 <- arg + csrr s2, CSR_NT # s2 <- NT + csrr s1, CSR_WTID # s1 <- tid + li s0, 0 # s0 <- index label_loop: sub t0, s0, s1 - snez t0, t0 - .insn s 0x6b, 2, x0, 0(t0) # split t0 + seqz t1, t0 # (index != tid) + .insn s 0x6b, 2, x0, 0(t1) # split t0 bnez t0, label_join - mv a0, s0 # a0 <- index - mv a1, s3 # a1 <- arg - jalr s4 # callback(index, arg) + mv a0, s3 # a0 <- arg + jalr s4 # callback(arg) label_join: .insn s 0x6b, 3, x0, 0(x0) # join - addi s0, s0, 1 - blt s0, s2, label_loop + addi s0, s0, 1 # index++ + blt s0, s2, label_loop # loop back lw ra, 20(sp) lw s4, 16(sp) lw s3, 12(sp) diff --git a/runtime/src/vx_spawn.c b/runtime/src/vx_spawn.c index 8ccd5f6b..eb8be09a 100644 --- a/runtime/src/vx_spawn.c +++ b/runtime/src/vx_spawn.c @@ -16,15 +16,17 @@ typedef struct { int offset; int N; int R; + int NW; } wspawn_tasks_args_t; typedef struct { - struct context_t * ctx; + context_t * ctx; vx_spawn_kernel_cb callback; void * arg; int offset; int N; int R; + int NW; char isXYpow2; char isXpow2; char log2XY; @@ -42,9 +44,7 @@ inline int fast_log2(int x) { return (*(int*)(&f)>>23) - 127; } -static void spawn_tasks_callback() { - vx_tmc(vx_num_threads()); - +static void __attribute__ ((noinline)) spawn_tasks_all_stub() { int core_id = vx_core_id(); int wid = vx_warp_id(); int tid = vx_thread_id(); @@ -60,12 +60,11 @@ static void spawn_tasks_callback() { (p_wspawn_args->callback)(task_id, p_wspawn_args->arg); } - vx_tmc(0 == wid); + // wait for all warps to complete + vx_barrier(0, p_wspawn_args->NW); } -void spawn_remaining_tasks_callback(int nthreads) { - vx_tmc(nthreads); - +static void __attribute__ ((noinline)) spawn_tasks_rem_stub() { int core_id = vx_core_id(); int tid = vx_thread_gid(); @@ -73,7 +72,28 @@ void spawn_remaining_tasks_callback(int nthreads) { int task_id = p_wspawn_args->offset + tid; (p_wspawn_args->callback)(task_id, p_wspawn_args->arg); +} +static void spawn_tasks_all_cb() { + // activate all threads + vx_tmc(-1); + + // call stub routine + spawn_tasks_all_stub(); + + // set warp0 to single-threaded and stop other warps + int wid = vx_warp_id(); + vx_tmc(0 == wid); +} + +static void spawn_tasks_rem_cb(int thread_mask) { + // activate threads + vx_tmc(thread_mask); + + // call stub routine + spawn_tasks_rem_stub(); + + // back to single-threaded vx_tmc(1); } @@ -112,28 +132,28 @@ void vx_spawn_tasks(int num_tasks, vx_spawn_tasks_cb callback , void * arg) { fW = 1; //-- - wspawn_tasks_args_t wspawn_args = { callback, arg, core_id * tasks_per_core, fW, rW }; + wspawn_tasks_args_t wspawn_args = { callback, arg, core_id * tasks_per_core, fW, rW, 0 }; g_wspawn_args[core_id] = &wspawn_args; //-- if (nW >= 1) { int nw = MIN(nW, NW); - vx_wspawn(nw, spawn_tasks_callback); - spawn_tasks_callback(); + wspawn_args.NW = nw; + vx_wspawn(nw, spawn_tasks_all_cb); + spawn_tasks_all_cb(); } //-- if (rT != 0) { wspawn_args.offset = tasks_per_core0 - rT; - spawn_remaining_tasks_callback(rT); + int tmask = (1 << rT) - 1; + spawn_tasks_rem_cb(tmask); } } /////////////////////////////////////////////////////////////////////////////// -static void spawn_kernel_callback() { - vx_tmc(vx_num_threads()); - +static void __attribute__ ((noinline)) spawn_kernel_all_stub() { int core_id = vx_core_id(); int wid = vx_warp_id(); int tid = vx_thread_id(); @@ -162,12 +182,11 @@ static void spawn_kernel_callback() { (p_wspawn_args->callback)(p_wspawn_args->arg, p_wspawn_args->ctx, gid0, gid1, gid2); } - vx_tmc(0 == wid); + // wait for all warps to complete + vx_barrier(0, p_wspawn_args->NW); } -static void spawn_kernel_remaining_callback(int nthreads) { - vx_tmc(nthreads); - +static void __attribute__ ((noinline)) spawn_kernel_rem_stub() { int core_id = vx_core_id(); int tid = vx_thread_gid(); @@ -189,11 +208,32 @@ static void spawn_kernel_remaining_callback(int nthreads) { int gid2 = p_wspawn_args->ctx->global_offset[2] + k; (p_wspawn_args->callback)(p_wspawn_args->arg, p_wspawn_args->ctx, gid0, gid1, gid2); +} +static void spawn_kernel_all_cb() { + // activate all threads + vx_tmc(-1); + + // call stub routine + spawn_kernel_all_stub(); + + // set warp0 to single-threaded and stop other warps + int wid = vx_warp_id(); + vx_tmc(0 == wid); +} + +static void spawn_kernel_rem_cb(int thread_mask) { + // activate threads + vx_tmc(thread_mask); + + // call stub routine + spawn_kernel_rem_stub(); + + // back to single-threaded vx_tmc(1); } -void vx_spawn_kernel(struct context_t * ctx, vx_spawn_kernel_cb callback, void * arg) { +void vx_spawn_kernel(context_t * ctx, vx_spawn_kernel_cb callback, void * arg) { // total number of WGs int X = ctx->num_groups[0]; int Y = ctx->num_groups[1]; @@ -242,21 +282,23 @@ void vx_spawn_kernel(struct context_t * ctx, vx_spawn_kernel_cb callback, void * //-- wspawn_kernel_args_t wspawn_args = { - ctx, callback, arg, core_id * wgs_per_core, fW, rW, isXYpow2, isXpow2, log2XY, log2X + ctx, callback, arg, core_id * wgs_per_core, fW, rW, 0, isXYpow2, isXpow2, log2XY, log2X }; g_wspawn_args[core_id] = &wspawn_args; //-- if (nW >= 1) { int nw = MIN(nW, NW); - vx_wspawn(nw, spawn_kernel_callback); - spawn_kernel_callback(); + wspawn_args.NW = nw; + vx_wspawn(nw, spawn_kernel_all_cb); + spawn_kernel_all_cb(); } //-- if (rT != 0) { wspawn_args.offset = wgs_per_core0 - rT; - spawn_kernel_remaining_callback(rT); + int tmask = (1 << rT) - 1; + spawn_kernel_rem_cb(tmask); } } diff --git a/runtime/src/vx_start.S b/runtime/src/vx_start.S index e830d752..0d2a0078 100644 --- a/runtime/src/vx_start.S +++ b/runtime/src/vx_start.S @@ -59,7 +59,7 @@ label_exit_next: .global vx_set_sp vx_set_sp: # activate all threads - csrr a0, CSR_NT # get num threads + li a0, -1 .insn s 0x6b, 0, x0, 0(a0) # tmc a0 # set global pointer register diff --git a/sim/Makefile b/sim/Makefile new file mode 100644 index 00000000..eca60c0b --- /dev/null +++ b/sim/Makefile @@ -0,0 +1,11 @@ +all: + $(MAKE) -C common + $(MAKE) -C simX + $(MAKE) -C rtlsim + $(MAKE) -C vlsim + +clean: + $(MAKE) -C common clean + $(MAKE) -C simX clean + $(MAKE) -C rtlsim clean + $(MAKE) -C vlsim clean \ No newline at end of file diff --git a/sim/common/Makefile b/sim/common/Makefile new file mode 100644 index 00000000..b17dc25b --- /dev/null +++ b/sim/common/Makefile @@ -0,0 +1,5 @@ +all: + SPECIALIZE_TYPE=RISCV SOFTFLOAT_OPTS="-fPIC -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 -DSOFTFLOAT_FAST_DIV64TO32" $(MAKE) -C softfloat/build/Linux-x86_64-GCC + +clean: + $(MAKE) -C softfloat/build/Linux-x86_64-GCC clean \ No newline at end of file diff --git a/simX/mem.cpp b/sim/common/mem.cpp similarity index 52% rename from simX/mem.cpp rename to sim/common/mem.cpp index cb33bb1f..6c4b94de 100644 --- a/simX/mem.cpp +++ b/sim/common/mem.cpp @@ -1,21 +1,13 @@ -#include -#include -#include -#include -#include -#include -#include -#include - -#include "debug.h" -#include "types.h" -#include "util.h" #include "mem.h" -#include "core.h" +#include +#include +#include +#include +#include "util.h" using namespace vortex; -RamMemDevice::RamMemDevice(const char *filename, Size wordSize) +RamMemDevice::RamMemDevice(const char *filename, uint32_t wordSize) : wordSize_(wordSize) { std::ifstream input(filename); @@ -32,12 +24,12 @@ RamMemDevice::RamMemDevice(const char *filename, Size wordSize) contents_.push_back(0x00); } -RamMemDevice::RamMemDevice(Size size, Size wordSize) +RamMemDevice::RamMemDevice(uint64_t size, uint32_t wordSize) : contents_(size) , wordSize_(wordSize) {} -void RamMemDevice::read(Addr addr, void *data, Size size) { +void RamMemDevice::read(void *data, uint64_t addr, uint64_t size) { auto addr_end = addr + size; if ((addr & (wordSize_-1)) || (addr_end & (wordSize_-1)) @@ -46,13 +38,13 @@ void RamMemDevice::read(Addr addr, void *data, Size size) { throw BadAddress(); } - const Byte *s = contents_.data() + addr; - for (Byte *d = (Byte*)data, *de = d + size; d != de;) { + const uint8_t *s = contents_.data() + addr; + for (uint8_t *d = (uint8_t*)data, *de = d + size; d != de;) { *d++ = *s++; } } -void RamMemDevice::write(Addr addr, const void *data, Size size) { +void RamMemDevice::write(const void *data, uint64_t addr, uint64_t size) { auto addr_end = addr + size; if ((addr & (wordSize_-1)) || (addr_end & (wordSize_-1)) @@ -61,23 +53,23 @@ void RamMemDevice::write(Addr addr, const void *data, Size size) { throw BadAddress(); } - const Byte *s = (const Byte*)data; - for (Byte *d = contents_.data() + addr, *de = d + size; d != de;) { + const uint8_t *s = (const uint8_t*)data; + for (uint8_t *d = contents_.data() + addr, *de = d + size; d != de;) { *d++ = *s++; } } /////////////////////////////////////////////////////////////////////////////// -void RomMemDevice::write(Addr /*addr*/, const void* /*data*/, Size /*size*/) { +void RomMemDevice::write(const void* /*data*/, uint64_t /*addr*/, uint64_t /*size*/) { std::cout << "attempt to write to ROM.\n"; std::abort(); } /////////////////////////////////////////////////////////////////////////////// -bool MemoryUnit::ADecoder::lookup(Addr a, Size wordSize, mem_accessor_t* ma) { - Addr e = a + (wordSize - 1); +bool MemoryUnit::ADecoder::lookup(uint64_t a, uint32_t wordSize, mem_accessor_t* ma) { + uint64_t e = a + (wordSize - 1); assert(e >= a); for (auto iter = entries_.rbegin(), iterE = entries_.rend(); iter != iterE; ++iter) { if (a >= iter->start && e <= iter->end) { @@ -89,89 +81,87 @@ bool MemoryUnit::ADecoder::lookup(Addr a, Size wordSize, mem_accessor_t* ma) { return false; } -void MemoryUnit::ADecoder::map(Addr a, Addr e, MemDevice &m) { +void MemoryUnit::ADecoder::map(uint64_t a, uint64_t e, MemDevice &m) { assert(e >= a); entry_t entry{&m, a, e}; entries_.emplace_back(entry); } -void MemoryUnit::ADecoder::read(Addr addr, void *data, Size size) { +void MemoryUnit::ADecoder::read(void *data, uint64_t addr, uint64_t size) { mem_accessor_t ma; if (!this->lookup(addr, size, &ma)) { std::cout << "lookup of 0x" << std::hex << addr << " failed.\n"; throw BadAddress(); } - ma.md->read(ma.addr, data, size); + ma.md->read(data, ma.addr, size); } -void MemoryUnit::ADecoder::write(Addr addr, const void *data, Size size) { +void MemoryUnit::ADecoder::write(const void *data, uint64_t addr, uint64_t size) { mem_accessor_t ma; if (!this->lookup(addr, size, &ma)) { std::cout << "lookup of 0x" << std::hex << addr << " failed.\n"; throw BadAddress(); } - ma.md->write(ma.addr, data, size); + ma.md->write(data, ma.addr, size); } /////////////////////////////////////////////////////////////////////////////// -MemoryUnit::MemoryUnit(Size pageSize, Size addrBytes, bool disableVm) +MemoryUnit::MemoryUnit(uint64_t pageSize, uint64_t addrBytes, bool disableVm) : pageSize_(pageSize) , addrBytes_(addrBytes) - , disableVm_(disableVm) { + , disableVM_(disableVm) { if (!disableVm) { tlb_[0] = TLBEntry(0, 077); } } -void MemoryUnit::attach(MemDevice &m, Addr start, Addr end) { +void MemoryUnit::attach(MemDevice &m, uint64_t start, uint64_t end) { decoder_.map(start, end, m); } -MemoryUnit::TLBEntry MemoryUnit::tlbLookup(Addr vAddr, Word flagMask) { +MemoryUnit::TLBEntry MemoryUnit::tlbLookup(uint64_t vAddr, uint32_t flagMask) { auto iter = tlb_.find(vAddr / pageSize_); if (iter != tlb_.end()) { if (iter->second.flags & flagMask) return iter->second; else { - D(3, "*** Page fault on addr 0x" << std::hex << vAddr << "(bad flags)"); throw PageFault(vAddr, false); } } else { - D(3, "*** Page fault on addr 0x" << std::hex << vAddr << "(not in TLB)"); throw PageFault(vAddr, true); } } -void MemoryUnit::read(Addr addr, void *data, Size size, bool sup) { - Addr pAddr; - if (disableVm_) { +void MemoryUnit::read(void *data, uint64_t addr, uint64_t size, bool sup) { + uint64_t pAddr; + if (disableVM_) { pAddr = addr; } else { - Word flagMask = sup ? 8 : 1; + uint32_t flagMask = sup ? 8 : 1; TLBEntry t = this->tlbLookup(addr, flagMask); pAddr = t.pfn * pageSize_ + addr % pageSize_; } - return decoder_.read(pAddr, data, size); + return decoder_.read(data, pAddr, size); } -void MemoryUnit::write(Addr addr, const void *data, Size size, bool sup) { - Addr pAddr; - if (disableVm_) { +void MemoryUnit::write(const void *data, uint64_t addr, uint64_t size, bool sup) { + uint64_t pAddr; + if (disableVM_) { pAddr = addr; } else { - Word flagMask = sup ? 16 : 2; + uint32_t flagMask = sup ? 16 : 2; TLBEntry t = tlbLookup(addr, flagMask); pAddr = t.pfn * pageSize_ + addr % pageSize_; } - decoder_.write(pAddr, data, size); + decoder_.write(data, pAddr, size); } -void MemoryUnit::tlbAdd(Addr virt, Addr phys, Word flags) { +void MemoryUnit::tlbAdd(uint64_t virt, uint64_t phys, uint32_t flags) { tlb_[virt / pageSize_] = TLBEntry(phys / pageSize_, flags); } -void MemoryUnit::tlbRm(Addr va) { +void MemoryUnit::tlbRm(uint64_t va) { if (tlb_.find(va / pageSize_) != tlb_.end()) tlb_.erase(tlb_.find(va / pageSize_)); } @@ -182,8 +172,7 @@ RAM::RAM(uint32_t num_pages, uint32_t page_size) : page_bits_(log2ceil(page_size)) { assert(ispow2(page_size)); mem_.resize(num_pages, NULL); - uint64_t sizel = uint64_t(mem_.size()) << page_bits_; - size_ = (sizel <= 0xFFFFFFFF) ? sizel : 0xffffffff; + size_ = uint64_t(mem_.size()) << page_bits_; } RAM::~RAM() { @@ -197,16 +186,16 @@ void RAM::clear() { } } -Size RAM::size() const { +uint64_t RAM::size() const { return size_; } -uint8_t *RAM::get(uint32_t address) { +uint8_t *RAM::get(uint32_t address) const { uint32_t page_size = 1 << page_bits_; uint32_t page_index = address >> page_bits_; uint32_t byte_offset = address & ((1 << page_bits_) - 1); - uint8_t* &page = mem_.at(page_index); + auto &page = mem_.at(page_index); if (page == NULL) { uint8_t *ptr = new uint8_t[page_size]; // set uninitialized data to "baadf00d" @@ -218,88 +207,99 @@ uint8_t *RAM::get(uint32_t address) { return page + byte_offset; } -void RAM::read(Addr addr, void *data, Size size) { - Byte* d = (Byte*)data; - for (unsigned i = 0; i < size; i++) { +void RAM::read(void *data, uint64_t addr, uint64_t size) { + uint8_t* d = (uint8_t*)data; + for (uint64_t i = 0; i < size; i++) { d[i] = *this->get(addr + i); } } -void RAM::write(Addr addr, const void *data, Size size) { - const Byte* s = (const Byte*)data; - for (unsigned i = 0; i < size; i++) { +void RAM::write(const void *data, uint64_t addr, uint64_t size) { + const uint8_t* s = (const uint8_t*)data; + for (uint64_t i = 0; i < size; i++) { *this->get(addr + i) = s[i]; } } -static uint32_t hti_old(char c) { - if (c >= 'A' && c <= 'F') - return c - 'A' + 10; - if (c >= 'a' && c <= 'f') - return c - 'a' + 10; - return c - '0'; -} - -static uint32_t hToI_old(char *c, uint32_t size) { - uint32_t value = 0; - for (uint32_t i = 0; i < size; i++) { - value += hti_old(c[i]) << ((size - i - 1) * 4); +void RAM::loadBinImage(const char* filename, uint64_t destination) { + std::ifstream ifs(filename); + if (!ifs) { + std::cout << "error: " << filename << " not found" << std::endl; } - return value; -} -void RAM::loadHexImage(std::string path) { + ifs.seekg(0, ifs.end); + size_t size = ifs.tellg(); + std::vector content(size); + ifs.seekg(0, ifs.beg); + ifs.read((char*)content.data(), size); + this->clear(); - FILE *fp = fopen(&path[0], "r"); - if (fp == 0) { - std::cout << path << " not found" << std::endl; + this->write(content.data(), destination, size); +} + +void RAM::loadHexImage(const char* filename) { + auto hti = [&](char c)->uint32_t { + if (c >= 'A' && c <= 'F') + return c - 'A' + 10; + if (c >= 'a' && c <= 'f') + return c - 'a' + 10; + return c - '0'; + }; + + auto hToI = [&](const char *c, uint32_t size)->uint32_t { + uint32_t value = 0; + for (uint32_t i = 0; i < size; i++) { + value += hti(c[i]) << ((size - i - 1) * 4); + } + return value; + }; + + std::ifstream ifs(filename); + if (!ifs) { + std::cout << "error: " << filename << " not found" << std::endl; } - fseek(fp, 0, SEEK_END); - uint32_t size = ftell(fp); - fseek(fp, 0, SEEK_SET); - char *content = new char[size]; - int x = fread(content, 1, size, fp); - if (!x) { - std::cout << "COULD NOT READ FILE\n"; - std::abort(); - } + ifs.seekg(0, ifs.end); + size_t size = ifs.tellg(); + std::vector content(size); + ifs.seekg(0, ifs.beg); + ifs.read(content.data(), size); int offset = 0; - char *line = content; - - while (1) { + char *line = content.data(); + + this->clear(); + + while (true) { if (line[0] == ':') { - uint32_t byteCount = hToI_old(line + 1, 2); - uint32_t nextAddr = hToI_old(line + 3, 4) + offset; - uint32_t key = hToI_old(line + 7, 2); + uint32_t byteCount = hToI(line + 1, 2); + uint32_t nextAddr = hToI(line + 3, 4) + offset; + uint32_t key = hToI(line + 7, 2); switch (key) { case 0: for (uint32_t i = 0; i < byteCount; i++) { - unsigned add = nextAddr + i; - *this->get(add) = hToI_old(line + 9 + i * 2, 2); + uint32_t addr = nextAddr + i; + uint32_t value = hToI(line + 9 + i * 2, 2); + *this->get(addr) = value; } break; case 2: - offset = hToI_old(line + 9, 4) << 4; + offset = hToI(line + 9, 4) << 4; break; case 4: - offset = hToI_old(line + 9, 4) << 16; + offset = hToI(line + 9, 4) << 16; break; default: break; } } while (*line != '\n' && size != 0) { - line++; - size--; + ++line; + --size; } if (size <= 1) break; - line++; - size--; + ++line; + --size; } - - if (content) - delete[] content; } \ No newline at end of file diff --git a/sim/common/mem.h b/sim/common/mem.h new file mode 100644 index 00000000..8929b4d9 --- /dev/null +++ b/sim/common/mem.h @@ -0,0 +1,163 @@ +#pragma once + +#include +#include + +namespace vortex { +struct BadAddress {}; + +class MemDevice { +public: + virtual ~MemDevice() {} + virtual uint64_t size() const = 0; + virtual void read(void *data, uint64_t addr, uint64_t size) = 0; + virtual void write(const void *data, uint64_t addr, uint64_t size) = 0; +}; + +/////////////////////////////////////////////////////////////////////////////// + +class RamMemDevice : public MemDevice { +public: + RamMemDevice(uint64_t size, uint32_t wordSize); + RamMemDevice(const char *filename, uint32_t wordSize); + ~RamMemDevice() {} + + void read(void *data, uint64_t addr, uint64_t size) override; + void write(const void *data, uint64_t addr, uint64_t size) override; + + virtual uint64_t size() const { + return contents_.size(); + }; + +protected: + std::vector contents_; + uint32_t wordSize_; +}; + +/////////////////////////////////////////////////////////////////////////////// + +class RomMemDevice : public RamMemDevice { +public: + RomMemDevice(const char *filename, uint32_t wordSize) + : RamMemDevice(filename, wordSize) + {} + + RomMemDevice(uint64_t size, uint32_t wordSize) + : RamMemDevice(size, wordSize) + {} + + ~RomMemDevice(); + + void write(const void *data, uint64_t addr, uint64_t size) override; +}; + +/////////////////////////////////////////////////////////////////////////////// + +class MemoryUnit { +public: + + struct PageFault { + PageFault(uint64_t a, bool nf) + : faultAddr(a) + , notFound(nf) + {} + uint64_t faultAddr; + bool notFound; + }; + + MemoryUnit(uint64_t pageSize, uint64_t addrBytes, bool disableVm = false); + + void attach(MemDevice &m, uint64_t start, uint64_t end); + + void read(void *data, uint64_t addr, uint64_t size, bool sup); + void write(const void *data, uint64_t addr, uint64_t size, bool sup); + + void tlbAdd(uint64_t virt, uint64_t phys, uint32_t flags); + void tlbRm(uint64_t va); + void tlbFlush() { + tlb_.clear(); + } +private: + + class ADecoder { + public: + ADecoder() {} + + void read(void *data, uint64_t addr, uint64_t size); + void write(const void *data, uint64_t addr, uint64_t size); + + void map(uint64_t start, uint64_t end, MemDevice &md); + + private: + + struct mem_accessor_t { + MemDevice* md; + uint64_t addr; + }; + + struct entry_t { + MemDevice *md; + uint64_t start; + uint64_t end; + }; + + bool lookup(uint64_t a, uint32_t wordSize, mem_accessor_t*); + + std::vector entries_; + }; + + struct TLBEntry { + TLBEntry() {} + TLBEntry(uint32_t pfn, uint32_t flags) + : pfn(pfn) + , flags(flags) + {} + uint32_t pfn; + uint32_t flags; + }; + + TLBEntry tlbLookup(uint64_t vAddr, uint32_t flagMask); + + std::unordered_map tlb_; + uint64_t pageSize_; + uint64_t addrBytes_; + ADecoder decoder_; + bool disableVM_; +}; + +/////////////////////////////////////////////////////////////////////////////// + +class RAM : public MemDevice { +public: + + RAM(uint32_t num_pages, uint32_t page_size); + + ~RAM(); + + void clear(); + + uint64_t size() const override; + void read(void *data, uint64_t addr, uint64_t size) override; + void write(const void *data, uint64_t addr, uint64_t size) override; + + void loadBinImage(const char* filename, uint64_t destination); + void loadHexImage(const char* filename); + + uint8_t& operator[](uint64_t address) { + return *this->get(address); + } + + const uint8_t& operator[](uint64_t address) const { + return *this->get(address); + } + +private: + + uint8_t *get(uint32_t address) const; + + mutable std::vector mem_; + uint32_t page_bits_; + uint64_t size_; +}; + +} // namespace vortex \ No newline at end of file diff --git a/sim/common/rvfloats.cpp b/sim/common/rvfloats.cpp new file mode 100644 index 00000000..c23cb8da --- /dev/null +++ b/sim/common/rvfloats.cpp @@ -0,0 +1,227 @@ +#include "rvfloats.h" +#include + +extern "C" { +#include +#include +#include +} + +#define F32_SIGN 0x80000000 + +inline float32_t to_float32_t(uint32_t x) { return float32_t{x}; } + +inline uint32_t from_float32_t(float32_t x) { return uint32_t(x.v); } + +inline uint32_t get_fflags() { + uint32_t fflags = softfloat_exceptionFlags; + if (fflags) { + softfloat_exceptionFlags = 0; + } + return fflags; +} + +#ifdef __cplusplus +extern "C" { +#endif + +uint32_t rv_fadd(uint32_t a, uint32_t b, uint32_t frm, uint32_t* fflags) { + softfloat_roundingMode = frm; + auto r = f32_add(to_float32_t(a), to_float32_t(b)); + if (fflags) { *fflags = get_fflags(); } + return from_float32_t(r); +} + +uint32_t rv_fsub(uint32_t a, uint32_t b, uint32_t frm, uint32_t* fflags) { + softfloat_roundingMode = frm; + auto r = f32_sub(to_float32_t(a), to_float32_t(b)); + if (fflags) { *fflags = get_fflags(); } + return from_float32_t(r); +} + +uint32_t rv_fmul(uint32_t a, uint32_t b, uint32_t frm, uint32_t* fflags) { + softfloat_roundingMode = frm; + auto r = f32_mul(to_float32_t(a), to_float32_t(b)); + if (fflags) { *fflags = get_fflags(); } + return from_float32_t(r); +} + +uint32_t rv_fmadd(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags) { + softfloat_roundingMode = frm; + auto r = f32_mulAdd(to_float32_t(a), to_float32_t(b), to_float32_t(c)); + if (fflags) { *fflags = get_fflags(); } + return from_float32_t(r); +} + +uint32_t rv_fmsub(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags) { + softfloat_roundingMode = frm; + int c_neg = c ^ F32_SIGN; + auto r = f32_mulAdd(to_float32_t(a), to_float32_t(b), to_float32_t(c_neg)); + if (fflags) { *fflags = get_fflags(); } + return from_float32_t(r); +} + +uint32_t rv_fnmadd(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags) { + softfloat_roundingMode = frm; + int a_neg = a ^ F32_SIGN; + int c_neg = c ^ F32_SIGN; + auto r = f32_mulAdd(to_float32_t(a_neg), to_float32_t(b), to_float32_t(c_neg)); + if (fflags) { *fflags = get_fflags(); } + return from_float32_t(r); +} + +uint32_t rv_fnmsub(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags) { + softfloat_roundingMode = frm; + int a_neg = a ^ F32_SIGN; + auto r = f32_mulAdd(to_float32_t(a_neg), to_float32_t(b), to_float32_t(c)); + if (fflags) { *fflags = get_fflags(); } + return from_float32_t(r); +} + +uint32_t rv_fdiv(uint32_t a, uint32_t b, uint32_t frm, uint32_t* fflags) { + softfloat_roundingMode = frm; + auto r = f32_div(to_float32_t(a), to_float32_t(b)); + if (fflags) { *fflags = get_fflags(); } + return from_float32_t(r); +} + +uint32_t rv_fsqrt(uint32_t a, uint32_t frm, uint32_t* fflags) { + softfloat_roundingMode = frm; + auto r = f32_sqrt(to_float32_t(a)); + if (fflags) { *fflags = get_fflags(); } + return from_float32_t(r); +} + +uint32_t rv_ftoi(uint32_t a, uint32_t frm, uint32_t* fflags) { + softfloat_roundingMode = frm; + auto r = f32_to_i32(to_float32_t(a), frm, true); + if (fflags) { *fflags = get_fflags(); } + return r; +} + +uint32_t rv_ftou(uint32_t a, uint32_t frm, uint32_t* fflags) { + softfloat_roundingMode = frm; + auto r = f32_to_ui32(to_float32_t(a), frm, true); + if (fflags) { *fflags = get_fflags(); } + return r; +} + +uint32_t rv_itof(uint32_t a, uint32_t frm, uint32_t* fflags) { + softfloat_roundingMode = frm; + auto r = i32_to_f32(a); + if (fflags) { *fflags = get_fflags(); } + return from_float32_t(r); +} + +uint32_t rv_utof(uint32_t a, uint32_t frm, uint32_t* fflags) { + softfloat_roundingMode = frm; + auto r = ui32_to_f32(a); + if (fflags) { *fflags = get_fflags(); } + return from_float32_t(r); +} + +uint32_t rv_flt(uint32_t a, uint32_t b, uint32_t* fflags) { + auto r = f32_lt(to_float32_t(a), to_float32_t(b)); + if (fflags) { *fflags = get_fflags(); } + return r; +} + +uint32_t rv_fle(uint32_t a, uint32_t b, uint32_t* fflags) { + auto r = f32_le(to_float32_t(a), to_float32_t(b)); + if (fflags) { *fflags = get_fflags(); } + return r; +} + +uint32_t rv_feq(uint32_t a, uint32_t b, uint32_t* fflags) { + auto r = f32_eq(to_float32_t(a), to_float32_t(b)); + if (fflags) { *fflags = get_fflags(); } + return r; +} + +uint32_t rv_fmin(uint32_t a, uint32_t b, uint32_t* fflags) { + int r; + if (isNaNF32UI(a) && isNaNF32UI(b)) { + r = defaultNaNF32UI; + } else { + auto fa = to_float32_t(a); + auto fb = to_float32_t(b); + if ((f32_lt_quiet(fa, fb) || (f32_eq(fa, fb) && (a & F32_SIGN))) + || isNaNF32UI(b)) { + r = a; + } else { + r = b; + } + } + if (fflags) { *fflags = get_fflags(); } + return r; +} + +uint32_t rv_fmax(uint32_t a, uint32_t b, uint32_t* fflags) { + int r; + if (isNaNF32UI(a) && isNaNF32UI(b)) { + r = defaultNaNF32UI; + } else { + auto fa = to_float32_t(a); + auto fb = to_float32_t(b); + if ((f32_lt_quiet(fb, fa) || (f32_eq(fb, fa) && (b & F32_SIGN))) + || isNaNF32UI(b)) { + r = a; + } else { + r = b; + } + } + if (fflags) { *fflags = get_fflags(); } + return r; +} + +uint32_t rv_fclss(uint32_t a) { + auto infOrNaN = (0xff == expF32UI(a)); + auto subnormOrZero = (0 == expF32UI(a)); + bool sign = signF32UI(a); + bool fracZero = (0 == fracF32UI(a)); + bool isNaN = isNaNF32UI(a); + bool isSNaN = softfloat_isSigNaNF32UI(a); + + int r = + ( sign && infOrNaN && fracZero ) << 0 | + ( sign && !infOrNaN && !subnormOrZero ) << 1 | + ( sign && subnormOrZero && !fracZero ) << 2 | + ( sign && subnormOrZero && fracZero ) << 3 | + ( !sign && infOrNaN && fracZero ) << 7 | + ( !sign && !infOrNaN && !subnormOrZero ) << 6 | + ( !sign && subnormOrZero && !fracZero ) << 5 | + ( !sign && subnormOrZero && fracZero ) << 4 | + ( isNaN && isSNaN ) << 8 | + ( isNaN && !isSNaN ) << 9; + + return r; +} + +uint32_t rv_fsgnj(uint32_t a, uint32_t b) { + + int sign = b & F32_SIGN; + int r = sign | (a & ~F32_SIGN); + + return r; +} + +uint32_t rv_fsgnjn(uint32_t a, uint32_t b) { + + int sign = ~b & F32_SIGN; + int r = sign | (a & ~F32_SIGN); + + return r; +} + +uint32_t rv_fsgnjx(uint32_t a, uint32_t b) { + + int sign1 = a & F32_SIGN; + int sign2 = b & F32_SIGN; + int r = (sign1 ^ sign2) | (a & ~F32_SIGN); + + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/sim/common/rvfloats.h b/sim/common/rvfloats.h new file mode 100644 index 00000000..392e5b63 --- /dev/null +++ b/sim/common/rvfloats.h @@ -0,0 +1,41 @@ +#ifndef RVFLOATS_H +#define RVFLOATS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +uint32_t rv_fadd(uint32_t a, uint32_t b, uint32_t frm, uint32_t* fflags); +uint32_t rv_fsub(uint32_t a, uint32_t b, uint32_t frm, uint32_t* fflags); +uint32_t rv_fmul(uint32_t a, uint32_t b, uint32_t frm, uint32_t* fflags); +uint32_t rv_fmadd(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags); +uint32_t rv_fmsub(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags); +uint32_t rv_fnmadd(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags); +uint32_t rv_fnmsub(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags); + +uint32_t rv_fdiv(uint32_t a, uint32_t b, uint32_t frm, uint32_t* fflags); +uint32_t rv_fsqrt(uint32_t a, uint32_t frm, uint32_t* fflags); + +uint32_t rv_ftoi(uint32_t a, uint32_t frm, uint32_t* fflags); +uint32_t rv_ftou(uint32_t a, uint32_t frm, uint32_t* fflags); +uint32_t rv_itof(uint32_t a, uint32_t frm, uint32_t* fflags); +uint32_t rv_utof(uint32_t a, uint32_t frm, uint32_t* fflags); + +uint32_t rv_fclss(uint32_t a); +uint32_t rv_fsgnj(uint32_t a, uint32_t b); +uint32_t rv_fsgnjn(uint32_t a, uint32_t b); +uint32_t rv_fsgnjx(uint32_t a, uint32_t b); + +uint32_t rv_flt(uint32_t a, uint32_t b, uint32_t* fflags); +uint32_t rv_fle(uint32_t a, uint32_t b, uint32_t* fflags); +uint32_t rv_feq(uint32_t a, uint32_t b, uint32_t* fflags); +uint32_t rv_fmin(uint32_t a, uint32_t b, uint32_t* fflags); +uint32_t rv_fmax(uint32_t a, uint32_t b, uint32_t* fflags); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/sim/common/softfloat b/sim/common/softfloat new file mode 160000 index 00000000..b64af41c --- /dev/null +++ b/sim/common/softfloat @@ -0,0 +1 @@ +Subproject commit b64af41c3276f97f0e181920400ee056b9c88037 diff --git a/sim/common/util.cpp b/sim/common/util.cpp new file mode 100644 index 00000000..eb125499 --- /dev/null +++ b/sim/common/util.cpp @@ -0,0 +1,10 @@ +#include "util.h" +#include + +// return file extension +const char* fileExtension(const char* filepath) { + const char *ext = strrchr(filepath, '.'); + if (ext == NULL || ext == filepath) + return ""; + return ext + 1; +} \ No newline at end of file diff --git a/sim/common/util.h b/sim/common/util.h new file mode 100644 index 00000000..dbaeb5fa --- /dev/null +++ b/sim/common/util.h @@ -0,0 +1,32 @@ +#pragma once + +#include +#include + +template +void unused(Args&&...) {} + +#define __unused(...) unused(__VA_ARGS__) + +constexpr bool ispow2(uint64_t value) { + return value && !(value & (value - 1)); +} + +constexpr unsigned log2ceil(uint32_t value) { + return 32 - __builtin_clz(value - 1); +} + +inline uint64_t align_size(uint64_t size, uint64_t alignment) { + assert(0 == (alignment & (alignment - 1))); + return (size + alignment - 1) & ~(alignment - 1); +} + +// Apply integer sign extension +inline uint32_t signExt(uint32_t w, uint32_t bit, uint32_t mask) { + if (w >> (bit - 1)) + w |= ~mask; + return w; +} + +// return file extension +const char* fileExtension(const char* filepath); \ No newline at end of file diff --git a/hw/simulate/.gitignore b/sim/rtlsim/.gitignore similarity index 100% rename from hw/simulate/.gitignore rename to sim/rtlsim/.gitignore diff --git a/sim/rtlsim/Makefile b/sim/rtlsim/Makefile new file mode 100644 index 00000000..6059e711 --- /dev/null +++ b/sim/rtlsim/Makefile @@ -0,0 +1,92 @@ +RTL_DIR=../../hw/rtl +DPI_DIR=../../hw/dpi + +CXXFLAGS += -std=c++11 -Wall -Wextra -Wfatal-errors +CXXFLAGS += -fPIC -Wno-maybe-uninitialized +CXXFLAGS += -I../../../hw -I../../common +CXXFLAGS += -I../../common/softfloat/source/include + +LDFLAGS += ../../common/softfloat/build/Linux-x86_64-GCC/softfloat.a + +# control RTL debug print states +DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE +DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_ICACHE +DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_DCACHE +DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_BANK +DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSHR +DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_TAG +DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_DATA +DBG_PRINT_FLAGS += -DDBG_PRINT_MEM +DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE +DBG_PRINT_FLAGS += -DDBG_PRINT_AVS +DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE + +DBG_FLAGS += $(DBG_PRINT_FLAGS) +DBG_FLAGS += -DDBG_CACHE_REQ_INFO +DBG_FLAGS += -DVCD_OUTPUT + +FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src -I$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(RTL_DIR)/fp_cores/fpnew/src +RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(RTL_DIR)/simulate $(FPU_INCLUDE) + +SRCS = ../common/util.cpp ../common/mem.cpp ../common/rvfloats.cpp +SRCS += $(DPI_DIR)/util_dpi.cpp $(DPI_DIR)/float_dpi.cpp +SRCS += main.cpp simulator.cpp + +ifdef AXI_BUS + TOP = Vortex_axi + CXXFLAGS += -DAXI_BUS +else + TOP = Vortex +endif + +VL_FLAGS = --exe --cc $(TOP) --top-module $(TOP) +VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic +VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO +VL_FLAGS += --x-initial unique --x-assign unique +VL_FLAGS += verilator.vlt +VL_FLAGS += $(RTL_INCLUDE) + +VL_FLAGS += $(CONFIGS) +CXXFLAGS += $(CONFIGS) + +# Debugigng +ifdef DEBUG + VL_FLAGS += -DVCD_OUTPUT --trace --trace-structs $(DBG_FLAGS) + CXXFLAGS += -g -O0 -DVCD_OUTPUT $(DBG_FLAGS) +else + VL_FLAGS += -DNDEBUG + CXXFLAGS += -O2 -DNDEBUG +endif + +# Enable perf counters +ifdef PERF + VL_FLAGS += -DPERF_ENABLE + CXXFLAGS += -DPERF_ENABLE +endif + +# ALU backend +VL_FLAGS += -DIMUL_DPI +VL_FLAGS += -DIDIV_DPI + +# FPU backend +FPU_CORE ?= FPU_DPI +VL_FLAGS += -D$(FPU_CORE) + +THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') + +PROJECT = rtlsim + +all: $(PROJECT) + +$(PROJECT): $(SRCS) + verilator --build $(VL_FLAGS) $(SRCS) -CFLAGS '$(CXXFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT) + +static: $(SRCS) + verilator --build $(VL_FLAGS) $(SRCS) -CFLAGS '$(CXXFLAGS)' -LDFLAGS '$(LDFLAGS)' + $(AR) rcs lib$(PROJECT).a obj_dir/*.o ../common/softfloat/build/Linux-x86_64-GCC/*.o + +clean-static: + rm -rf lib$(PROJECT).a obj_dir + +clean: clean-static + rm -rf $(PROJECT) diff --git a/hw/simulate/main.cpp b/sim/rtlsim/main.cpp similarity index 72% rename from hw/simulate/main.cpp rename to sim/rtlsim/main.cpp index bf332a19..0f0575f5 100644 --- a/hw/simulate/main.cpp +++ b/sim/rtlsim/main.cpp @@ -1,7 +1,13 @@ -#include "simulator.h" #include #include #include +#include +#include +#include +#include +#include "simulator.h" + +using namespace vortex; static void show_usage() { std::cout << "Usage: [-r] [-h: help] programs.." << std::endl; @@ -43,10 +49,20 @@ int main(int argc, char **argv) { for (auto program : programs) { std::cout << "Running " << program << "..." << std::endl; - RAM ram; - Simulator simulator; + vortex::RAM ram((1<<12), (1<<20)); + vortex::Simulator simulator; simulator.attach_ram(&ram); - simulator.load_ihex(program); + + std::string program_ext(fileExtension(program)); + if (program_ext == "bin") { + ram.loadBinImage(program, STARTUP_ADDR); + } else if (program_ext == "hex") { + ram.loadHexImage(program); + } else { + std::cout << "*** error: only *.bin or *.hex images supported." << std::endl; + return -1; + } + exitcode = simulator.run(); if (riscv_test) { diff --git a/sim/rtlsim/simulator.cpp b/sim/rtlsim/simulator.cpp new file mode 100644 index 00000000..8d3f9acf --- /dev/null +++ b/sim/rtlsim/simulator.cpp @@ -0,0 +1,579 @@ +#include "simulator.h" + +#include + +#ifdef AXI_BUS +#include "VVortex_axi.h" +#include "VVortex_axi__Syms.h" +#else +#include "VVortex.h" +#include "VVortex__Syms.h" +#endif + +#ifdef VCD_OUTPUT +#include +#endif + +#include +#include +#include +#include + +#define ENABLE_MEM_STALLS + +#ifndef TRACE_START_TIME +#define TRACE_START_TIME 0ull +#endif + +#ifndef TRACE_STOP_TIME +#define TRACE_STOP_TIME -1ull +#endif + +#ifndef MEM_LATENCY +#define MEM_LATENCY 24 +#endif + +#ifndef MEM_RQ_SIZE +#define MEM_RQ_SIZE 16 +#endif + +#ifndef MEM_STALLS_MODULO +#define MEM_STALLS_MODULO 16 +#endif + +#ifndef VERILATOR_RESET_VALUE +#define VERILATOR_RESET_VALUE 2 +#endif + +#define VL_WDATA_GETW(lwp, i, n, w) \ + VL_SEL_IWII(0, n * w, 0, 0, lwp, i * w, w) + +using namespace vortex; + +static uint64_t timestamp = 0; + +double sc_time_stamp() { + return timestamp; +} + +/////////////////////////////////////////////////////////////////////////////// + +static bool trace_enabled = false; +static uint64_t trace_start_time = TRACE_START_TIME; +static uint64_t trace_stop_time = TRACE_STOP_TIME; + +bool sim_trace_enabled() { + if (timestamp >= trace_start_time + && timestamp < trace_stop_time) + return true; + return trace_enabled; +} + +void sim_trace_enable(bool enable) { + trace_enabled = enable; +} + +/////////////////////////////////////////////////////////////////////////////// + +namespace vortex { +class VL_OBJ { +public: +#ifdef AXI_BUS + VVortex_axi *device; +#else + VVortex *device; +#endif +#ifdef VCD_OUTPUT + VerilatedVcdC *trace; +#endif + + VL_OBJ() { + // force random values for unitialized signals + Verilated::randReset(VERILATOR_RESET_VALUE); + Verilated::randSeed(50); + + // Turn off assertion before reset + Verilated::assertOn(false); + + #ifdef AXI_BUS + this->device = new VVortex_axi(); + #else + this->device = new VVortex(); + #endif + + #ifdef VCD_OUTPUT + Verilated::traceEverOn(true); + this->trace = new VerilatedVcdC(); + this->device->trace(this->trace, 99); + this->trace->open("trace.vcd"); + #endif + } + + ~VL_OBJ() { + #ifdef VCD_OUTPUT + this->trace->close(); + delete this->trace; + #endif + delete this->device; + } +}; +} + +/////////////////////////////////////////////////////////////////////////////// + +Simulator::Simulator() { + vl_obj_ = new VL_OBJ(); + ram_ = nullptr; + // reset the device + this->reset(); +} + +Simulator::~Simulator() { + for (auto& buf : print_bufs_) { + auto str = buf.second.str(); + if (!str.empty()) { + std::cout << "#" << buf.first << ": " << str << std::endl; + } + } + delete vl_obj_; +} + +void Simulator::attach_ram(RAM* ram) { + ram_ = ram; + for (int b = 0; b < MEMORY_BANKS; ++b) { + mem_rsp_vec_[b].clear(); + } + last_mem_rsp_bank_ = 0; +} + +void Simulator::reset() { + print_bufs_.clear(); + + for (int b = 0; b < MEMORY_BANKS; ++b) { + mem_rsp_vec_[b].clear(); + } + last_mem_rsp_bank_ = 0; + mem_rd_rsp_active_ = false; + mem_wr_rsp_active_ = false; + +#ifdef AXI_BUS + this->reset_axi_bus(); +#else + this->reset_mem_bus(); +#endif + + vl_obj_->device->reset = 1; + + for (int i = 0; i < RESET_DELAY; ++i) { + vl_obj_->device->clk = 0; + this->eval(); + vl_obj_->device->clk = 1; + this->eval(); + } + + vl_obj_->device->reset = 0; + + // Turn on assertion after reset + Verilated::assertOn(true); +} + +void Simulator::step() { + + vl_obj_->device->clk = 0; + this->eval(); + +#ifdef AXI_BUS + this->eval_axi_bus(0); +#else + this->eval_mem_bus(0); +#endif + + vl_obj_->device->clk = 1; + this->eval(); + +#ifdef AXI_BUS + this->eval_axi_bus(1); +#else + this->eval_mem_bus(1); +#endif + +#ifndef NDEBUG + fflush(stdout); +#endif +} + +void Simulator::eval() { + vl_obj_->device->eval(); +#ifdef VCD_OUTPUT + if (sim_trace_enabled()) { + vl_obj_->trace->dump(timestamp); + } +#endif + ++timestamp; +} + +#ifdef AXI_BUS + +void Simulator::reset_axi_bus() { + vl_obj_->device->m_axi_wready = 0; + vl_obj_->device->m_axi_awready = 0; + vl_obj_->device->m_axi_arready = 0; + vl_obj_->device->m_axi_rvalid = 0; + vl_obj_->device->m_axi_bvalid = 0; +} + +void Simulator::eval_axi_bus(bool clk) { + if (!clk) { + mem_rd_rsp_ready_ = vl_obj_->device->m_axi_rready; + mem_wr_rsp_ready_ = vl_obj_->device->m_axi_bready; + return; + } + + if (ram_ == nullptr) { + vl_obj_->device->m_axi_wready = 0; + vl_obj_->device->m_axi_awready = 0; + vl_obj_->device->m_axi_arready = 0; + return; + } + + // update memory responses schedule + for (int b = 0; b < MEMORY_BANKS; ++b) { + for (auto& rsp : mem_rsp_vec_[b]) { + if (rsp.cycles_left > 0) + rsp.cycles_left -= 1; + } + } + + bool has_rd_response = false; + bool has_wr_response = false; + + // schedule memory responses that are ready + for (int i = 0; i < MEMORY_BANKS; ++i) { + uint32_t b = (i + last_mem_rsp_bank_ + 1) % MEMORY_BANKS; + if (!mem_rsp_vec_[b].empty()) { + auto mem_rsp_it = mem_rsp_vec_[b].begin(); + if (mem_rsp_it->cycles_left <= 0) { + has_rd_response = !mem_rsp_it->write; + has_wr_response = mem_rsp_it->write; + last_mem_rsp_bank_ = b; + break; + } + } + } + + // send memory read response + if (mem_rd_rsp_active_ + && vl_obj_->device->m_axi_rvalid && mem_rd_rsp_ready_) { + mem_rd_rsp_active_ = false; + } + if (!mem_rd_rsp_active_) { + if (has_rd_response) { + auto mem_rsp_it = mem_rsp_vec_[last_mem_rsp_bank_].begin(); + /* + printf("%0ld: [sim] MEM Rd Rsp: bank=%d, addr=%0lx, data=", timestamp, last_mem_rsp_bank_, mem_rsp_it->addr); + for (int i = 0; i < MEM_BLOCK_SIZE; i++) { + printf("%02x", mem_rsp_it->block[(MEM_BLOCK_SIZE-1)-i]); + } + printf("\n"); + */ + vl_obj_->device->m_axi_rvalid = 1; + vl_obj_->device->m_axi_rid = mem_rsp_it->tag; + vl_obj_->device->m_axi_rresp = 0; + vl_obj_->device->m_axi_rlast = 1; + memcpy((uint8_t*)vl_obj_->device->m_axi_rdata, mem_rsp_it->block.data(), MEM_BLOCK_SIZE); + mem_rsp_vec_[last_mem_rsp_bank_].erase(mem_rsp_it); + mem_rd_rsp_active_ = true; + } else { + vl_obj_->device->m_axi_rvalid = 0; + } + } + + // send memory write response + if (mem_wr_rsp_active_ + && vl_obj_->device->m_axi_bvalid && mem_wr_rsp_ready_) { + mem_wr_rsp_active_ = false; + } + if (!mem_wr_rsp_active_) { + if (has_wr_response) { + auto mem_rsp_it = mem_rsp_vec_[last_mem_rsp_bank_].begin(); + /* + printf("%0ld: [sim] MEM Wr Rsp: bank=%d, addr=%0lx\n", timestamp, last_mem_rsp_bank_, mem_rsp_it->addr); + */ + vl_obj_->device->m_axi_bvalid = 1; + vl_obj_->device->m_axi_bid = mem_rsp_it->tag; + vl_obj_->device->m_axi_bresp = 0; + mem_rsp_vec_[last_mem_rsp_bank_].erase(mem_rsp_it); + mem_wr_rsp_active_ = true; + } else { + vl_obj_->device->m_axi_bvalid = 0; + } + } + + // select the memory bank + uint32_t req_addr = vl_obj_->device->m_axi_wvalid ? vl_obj_->device->m_axi_awaddr : vl_obj_->device->m_axi_araddr; + uint32_t req_bank = (MEMORY_BANKS >= 2) ? ((req_addr / MEM_BLOCK_SIZE) % MEMORY_BANKS) : 0; + + // handle memory stalls + bool mem_stalled = false; +#ifdef ENABLE_MEM_STALLS + if (0 == ((timestamp/2) % MEM_STALLS_MODULO)) { + mem_stalled = true; + } else + if (mem_rsp_vec_[req_bank].size() >= MEM_RQ_SIZE) { + mem_stalled = true; + } +#endif + + // process memory requests + if (!mem_stalled) { + if (vl_obj_->device->m_axi_wvalid || vl_obj_->device->m_axi_arvalid) { + if (vl_obj_->device->m_axi_wvalid) { + uint64_t byteen = vl_obj_->device->m_axi_wstrb; + unsigned base_addr = vl_obj_->device->m_axi_awaddr; + uint8_t* data = (uint8_t*)(vl_obj_->device->m_axi_wdata); + + // detect stdout write + if (base_addr >= IO_COUT_ADDR + && base_addr <= (IO_COUT_ADDR + IO_COUT_SIZE - 1)) { + for (int i = 0; i < MEM_BLOCK_SIZE; i++) { + if ((byteen >> i) & 0x1) { + auto& ss_buf = print_bufs_[i]; + char c = data[i]; + ss_buf << c; + if (c == '\n') { + std::cout << std::dec << "#" << i << ": " << ss_buf.str() << std::flush; + ss_buf.str(""); + } + } + } + } else { + /* + printf("%0ld: [sim] MEM Wr: addr=%0x, byteen=%0lx, data=", timestamp, base_addr, byteen); + for (int i = 0; i < MEM_BLOCK_SIZE; i++) { + printf("%02x", data[(MEM_BLOCK_SIZE-1)-i]); + } + printf("\n"); + */ + for (int i = 0; i < MEM_BLOCK_SIZE; i++) { + if ((byteen >> i) & 0x1) { + (*ram_)[base_addr + i] = data[i]; + } + } + mem_req_t mem_req; + mem_req.tag = vl_obj_->device->m_axi_arid; + mem_req.addr = vl_obj_->device->m_axi_araddr; + mem_req.cycles_left = 0; + mem_req.write = 1; + mem_rsp_vec_[req_bank].emplace_back(mem_req); + } + } else { + mem_req_t mem_req; + mem_req.tag = vl_obj_->device->m_axi_arid; + mem_req.addr = vl_obj_->device->m_axi_araddr; + ram_->read(mem_req.block.data(), vl_obj_->device->m_axi_araddr, MEM_BLOCK_SIZE); + mem_req.cycles_left = MEM_LATENCY; + mem_req.write = 0; + for (auto& rsp : mem_rsp_vec_[req_bank]) { + if (mem_req.addr == rsp.addr) { + // duplicate requests receive the same cycle delay + mem_req.cycles_left = rsp.cycles_left; + break; + } + } + mem_rsp_vec_[req_bank].emplace_back(mem_req); + } + } + } + + vl_obj_->device->m_axi_wready = !mem_stalled; + vl_obj_->device->m_axi_awready = !mem_stalled; + vl_obj_->device->m_axi_arready = !mem_stalled; +} + +#else + +void Simulator::reset_mem_bus() { + vl_obj_->device->mem_req_ready = 0; + vl_obj_->device->mem_rsp_valid = 0; +} + +void Simulator::eval_mem_bus(bool clk) { + if (!clk) { + mem_rd_rsp_ready_ = vl_obj_->device->mem_rsp_ready; + return; + } + + if (ram_ == nullptr) { + vl_obj_->device->mem_req_ready = 0; + return; + } + + // update memory responses schedule + for (int b = 0; b < MEMORY_BANKS; ++b) { + for (auto& rsp : mem_rsp_vec_[b]) { + if (rsp.cycles_left > 0) + rsp.cycles_left -= 1; + } + } + + bool has_response = false; + + // schedule memory responses that are ready + for (int i = 0; i < MEMORY_BANKS; ++i) { + uint32_t b = (i + last_mem_rsp_bank_ + 1) % MEMORY_BANKS; + if (!mem_rsp_vec_[b].empty() + && (mem_rsp_vec_[b].begin()->cycles_left) <= 0) { + has_response = true; + last_mem_rsp_bank_ = b; + break; + } + } + + // send memory response + if (mem_rd_rsp_active_ + && vl_obj_->device->mem_rsp_valid && mem_rd_rsp_ready_) { + mem_rd_rsp_active_ = false; + } + if (!mem_rd_rsp_active_) { + if (has_response) { + vl_obj_->device->mem_rsp_valid = 1; + auto mem_rsp_it = mem_rsp_vec_[last_mem_rsp_bank_].begin(); + /* + printf("%0ld: [sim] MEM Rd: bank=%d, addr=%0lx, data=", timestamp, last_mem_rsp_bank_, mem_rsp_it->addr); + for (int i = 0; i < MEM_BLOCK_SIZE; i++) { + printf("%02x", mem_rsp_it->block[(MEM_BLOCK_SIZE-1)-i]); + } + printf("\n"); + */ + memcpy((uint8_t*)vl_obj_->device->mem_rsp_data, mem_rsp_it->block.data(), MEM_BLOCK_SIZE); + vl_obj_->device->mem_rsp_tag = mem_rsp_it->tag; + mem_rsp_vec_[last_mem_rsp_bank_].erase(mem_rsp_it); + mem_rd_rsp_active_ = true; + } else { + vl_obj_->device->mem_rsp_valid = 0; + } + } + + // select the memory bank + uint32_t req_bank = (MEMORY_BANKS >= 2) ? (vl_obj_->device->mem_req_addr % MEMORY_BANKS) : 0; + + // handle memory stalls + bool mem_stalled = false; +#ifdef ENABLE_MEM_STALLS + if (0 == ((timestamp/2) % MEM_STALLS_MODULO)) { + mem_stalled = true; + } else + if (mem_rsp_vec_[req_bank].size() >= MEM_RQ_SIZE) { + mem_stalled = true; + } +#endif + + // process memory requests + if (!mem_stalled) { + if (vl_obj_->device->mem_req_valid) { + if (vl_obj_->device->mem_req_rw) { + uint64_t byteen = vl_obj_->device->mem_req_byteen; + unsigned base_addr = (vl_obj_->device->mem_req_addr * MEM_BLOCK_SIZE); + uint8_t* data = (uint8_t*)(vl_obj_->device->mem_req_data); + if (base_addr >= IO_COUT_ADDR + && base_addr <= (IO_COUT_ADDR + IO_COUT_SIZE - 1)) { + for (int i = 0; i < MEM_BLOCK_SIZE; i++) { + if ((byteen >> i) & 0x1) { + auto& ss_buf = print_bufs_[i]; + char c = data[i]; + ss_buf << c; + if (c == '\n') { + std::cout << std::dec << "#" << i << ": " << ss_buf.str() << std::flush; + ss_buf.str(""); + } + } + } + } else { + /* + printf("%0ld: [sim] MEM Wr: addr=%0x, byteen=%0lx, data=", timestamp, base_addr, byteen); + for (int i = 0; i < MEM_BLOCK_SIZE; i++) { + printf("%02x", data[(MEM_BLOCK_SIZE-1)-i]); + } + printf("\n"); + */ + for (int i = 0; i < MEM_BLOCK_SIZE; i++) { + if ((byteen >> i) & 0x1) { + (*ram_)[base_addr + i] = data[i]; + } + } + } + } else { + mem_req_t mem_req; + mem_req.tag = vl_obj_->device->mem_req_tag; + mem_req.addr = (vl_obj_->device->mem_req_addr * MEM_BLOCK_SIZE); + ram_->read(mem_req.block.data(), vl_obj_->device->mem_req_addr * MEM_BLOCK_SIZE, MEM_BLOCK_SIZE); + mem_req.cycles_left = MEM_LATENCY; + for (auto& rsp : mem_rsp_vec_[req_bank]) { + if (mem_req.addr == rsp.addr) { + // duplicate requests receive the same cycle delay + mem_req.cycles_left = rsp.cycles_left; + break; + } + } + mem_rsp_vec_[req_bank].emplace_back(mem_req); + } + } + } + + vl_obj_->device->mem_req_ready = !mem_stalled; +} + +#endif + +void Simulator::wait(uint32_t cycles) { + for (int i = 0; i < cycles; ++i) { + this->step(); + } +} + +bool Simulator::is_busy() const { + return vl_obj_->device->busy; +} + +int Simulator::run() { + int exitcode = 0; + +#ifndef NDEBUG + std::cout << std::dec << timestamp << ": [sim] run()" << std::endl; +#endif + + // execute program + while (vl_obj_->device->busy) { + if (get_ebreak()) { + exitcode = get_last_wb_value(3); + break; + } + this->step(); + } + + // wait 5 cycles to flush the pipeline + this->wait(5); + + return exitcode; +} + +bool Simulator::get_ebreak() const { +#ifdef AXI_BUS + return (int)vl_obj_->device->Vortex_axi->vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->execute->ebreak; +#else + return (int)vl_obj_->device->Vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->execute->ebreak; +#endif +} + +int Simulator::get_last_wb_value(int reg) const { +#ifdef AXI_BUS + return (int)vl_obj_->device->Vortex_axi->vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_wb_value[reg]; +#else + return (int)vl_obj_->device->Vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_wb_value[reg]; +#endif +} + +void Simulator::print_stats(std::ostream& out) { + out << std::left; + out << std::setw(24) << "# of total cycles:" << std::dec << timestamp/2 << std::endl; +} \ No newline at end of file diff --git a/hw/simulate/simulator.h b/sim/rtlsim/simulator.h similarity index 69% rename from hw/simulate/simulator.h rename to sim/rtlsim/simulator.h index e9fe9389..3b36c520 100644 --- a/hw/simulate/simulator.h +++ b/sim/rtlsim/simulator.h @@ -1,16 +1,6 @@ #pragma once -#include "VVortex.h" -#include "VVortex__Syms.h" -#include "verilated.h" - -#ifdef VCD_OUTPUT -#include -#endif - #include -#include "ram.h" - #include #include #include @@ -25,6 +15,11 @@ #endif #endif +namespace vortex { + +class VL_OBJ; +class RAM; + class Simulator { public: @@ -33,9 +28,6 @@ public: void attach_ram(RAM* ram); - void load_bin(const char* program_file); - void load_ihex(const char* program_file); - bool is_busy() const; void reset(); @@ -48,18 +40,25 @@ public: private: - typedef struct { + typedef struct { int cycles_left; std::array block; - uint32_t addr; + uint64_t addr; uint64_t tag; + bool write; } mem_req_t; std::unordered_map print_bufs_; void eval(); - - void eval_mem_bus(); + +#ifdef AXI_BUS + void reset_axi_bus(); + void eval_axi_bus(bool clk); +#else + void reset_mem_bus(); + void eval_mem_bus(bool clk); +#endif int get_last_wb_value(int reg) const; @@ -68,13 +67,15 @@ private: std::list mem_rsp_vec_ [MEMORY_BANKS]; uint32_t last_mem_rsp_bank_; - bool mem_rsp_active_; + bool mem_rd_rsp_active_; + bool mem_rd_rsp_ready_; - bool mem_rsp_ready_; + bool mem_wr_rsp_active_; + bool mem_wr_rsp_ready_; RAM *ram_; - VVortex *vortex_; -#ifdef VCD_OUTPUT - VerilatedVcdC *trace_; -#endif -}; \ No newline at end of file + + VL_OBJ* vl_obj_; +}; + +} \ No newline at end of file diff --git a/driver/rtlsim/verilator.vlt b/sim/rtlsim/verilator.vlt similarity index 90% rename from driver/rtlsim/verilator.vlt rename to sim/rtlsim/verilator.vlt index 792578ea..986af455 100644 --- a/driver/rtlsim/verilator.vlt +++ b/sim/rtlsim/verilator.vlt @@ -7,4 +7,4 @@ lint_off -rule UNUSED -file "../../hw/rtl/fp_cores/fpnew/*" lint_off -rule LITENDIAN -file "../../hw/rtl/fp_cores/fpnew/*" lint_off -rule IMPORTSTAR -file "../../hw/rtl/fp_cores/fpnew/*" lint_off -rule PINCONNECTEMPTY -file "../../hw/rtl/fp_cores/fpnew/*" -lint_off -file "../rtl/fp_cores/fpnew/*" \ No newline at end of file +lint_off -file "../../hw/rtl/fp_cores/fpnew/*" \ No newline at end of file diff --git a/sim/simX/Makefile b/sim/simX/Makefile new file mode 100644 index 00000000..29b53fc3 --- /dev/null +++ b/sim/simX/Makefile @@ -0,0 +1,50 @@ +RTL_DIR = ../hw/rtl + +CXXFLAGS += -std=c++11 -Wall -Wextra -Wfatal-errors +CXXFLAGS += -fPIC -Wno-maybe-uninitialized +CXXFLAGS += -I. -I../common -I../../hw +CXXFLAGS += -I../common/softfloat/source/include +CXXFLAGS += $(CONFIGS) + +LDFLAGS += ../common/softfloat/build/Linux-x86_64-GCC/softfloat.a + +TOP = vx_cache_sim + +SRCS = ../common/util.cpp ../common/mem.cpp ../common/rvfloats.cpp +SRCS += args.cpp pipeline.cpp warp.cpp core.cpp decode.cpp execute.cpp main.cpp + +OBJS := $(patsubst %.cpp, obj_dir/%.o, $(notdir $(SRCS))) +VPATH := $(sort $(dir $(SRCS))) + +#$(info OBJS is $(OBJS)) +#$(info VPATH is $(VPATH)) + +# Debugigng +ifdef DEBUG + CXXFLAGS += -g -O0 -DDEBUG_LEVEL=$(DEBUG) +else + CXXFLAGS += -O2 -DNDEBUG +endif + +PROJECT = simX + +all: $(PROJECT) + +$(PROJECT): $(SRCS) + $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ + +obj_dir/%.o: %.cpp + mkdir -p obj_dir + $(CXX) $(CXXFLAGS) -c $< -o $@ + +static: $(OBJS) + $(AR) rcs lib$(PROJECT).a $(OBJS) ../common/softfloat/build/Linux-x86_64-GCC/*.o + +.depend: $(SRCS) + $(CXX) $(CXXFLAGS) -MM $^ > .depend; + +clean-static: + rm -rf lib$(PROJECT).a obj_dir .depend + +clean: clean-static + rm -rf $(PROJECT) \ No newline at end of file diff --git a/simX/archdef.h b/sim/simX/archdef.h similarity index 100% rename from simX/archdef.h rename to sim/simX/archdef.h diff --git a/simX/args.cpp b/sim/simX/args.cpp similarity index 100% rename from simX/args.cpp rename to sim/simX/args.cpp diff --git a/simX/args.h b/sim/simX/args.h similarity index 98% rename from simX/args.h rename to sim/simX/args.h index 7fbf236c..aeaba4e5 100644 --- a/simX/args.h +++ b/sim/simX/args.h @@ -4,7 +4,7 @@ #include #include #include -#include "util.h" +#include namespace vortex { diff --git a/simX/core.cpp b/sim/simX/core.cpp similarity index 96% rename from simX/core.cpp rename to sim/simX/core.cpp index 705b8768..c68ac854 100644 --- a/simX/core.cpp +++ b/sim/simX/core.cpp @@ -2,8 +2,8 @@ #include #include #include +#include #include "types.h" -#include "util.h" #include "archdef.h" #include "mem.h" #include "decode.h" @@ -267,6 +267,9 @@ Word Core::get_csr(Addr addr, int tid, int wid) { } else if (addr == CSR_GCID) { // Processor coreID return id_; + } else if (addr == CSR_TMASK) { + // Processor coreID + return warps_.at(wid)->getTmask(); } else if (addr == CSR_NT) { // Number of threads per warp return arch_.num_threads(); @@ -320,7 +323,7 @@ void Core::barrier(int bar_id, int count, int warp_id) { Word Core::icache_fetch(Addr addr) { Word data; - mem_.read(addr, &data, sizeof(Word), 0); + mem_.read(&data, addr, sizeof(Word), 0); return data; } @@ -330,11 +333,11 @@ Word Core::dcache_read(Addr addr, Size size) { #ifdef SM_ENABLE if ((addr >= (SMEM_BASE_ADDR - SMEM_SIZE)) && ((addr + 3) < SMEM_BASE_ADDR)) { - shared_mem_.read(addr & (SMEM_SIZE-1), &data, size); + shared_mem_.read(&data, addr & (SMEM_SIZE-1), size); return data; } #endif - mem_.read(addr, &data, size, 0); + mem_.read(&data, addr, size, 0); return data; } @@ -343,7 +346,7 @@ void Core::dcache_write(Addr addr, Word data, Size size) { #ifdef SM_ENABLE if ((addr >= (SMEM_BASE_ADDR - SMEM_SIZE)) && ((addr + 3) < SMEM_BASE_ADDR)) { - shared_mem_.write(addr & (SMEM_SIZE-1), &data, size); + shared_mem_.write(&data, addr & (SMEM_SIZE-1), size); return; } #endif @@ -352,7 +355,7 @@ void Core::dcache_write(Addr addr, Word data, Size size) { this->writeToStdOut(addr, data); return; } - mem_.write(addr, &data, size, 0); + mem_.write(&data, addr, size, 0); } bool Core::running() const { diff --git a/simX/core.h b/sim/simX/core.h similarity index 100% rename from simX/core.h rename to sim/simX/core.h diff --git a/simX/debug.h b/sim/simX/debug.h similarity index 100% rename from simX/debug.h rename to sim/simX/debug.h diff --git a/simX/decode.cpp b/sim/simX/decode.cpp similarity index 97% rename from simX/decode.cpp rename to sim/simX/decode.cpp index ad111846..01570aab 100644 --- a/simX/decode.cpp +++ b/sim/simX/decode.cpp @@ -5,9 +5,9 @@ #include #include #include +#include #include "debug.h" #include "types.h" -#include "util.h" #include "decode.h" #include "archdef.h" #include "instr.h" @@ -280,7 +280,7 @@ Decoder::Decoder(const ArchDef &arch) { v_imm_mask_ = 0x7ff; } -std::shared_ptr Decoder::decode(Word code) { +std::shared_ptr Decoder::decode(Word code, Word PC) { auto instr = std::make_shared(); Opcode op = (Opcode)((code >> shift_opcode_) & opcode_mask_); instr->setOpcode(op); @@ -289,12 +289,18 @@ std::shared_ptr Decoder::decode(Word code) { Word func6 = (code >> shift_func6_) & func6_mask_; Word func7 = (code >> shift_func7_) & func7_mask_; - int rd = (code >> shift_rd_) & reg_mask_; + int rd = (code >> shift_rd_) & reg_mask_; int rs1 = (code >> shift_rs1_) & reg_mask_; int rs2 = (code >> shift_rs2_) & reg_mask_; int rs3 = (code >> shift_rs3_) & reg_mask_; - auto iType = sc_instTable.at(op).iType; + auto op_it = sc_instTable.find(op); + if (op_it == sc_instTable.end()) { + std::cout << std::hex << "invalid opcode: 0x" << op << ", instruction=0x" << code << ", PC=" << PC << std::endl; + std::abort(); + } + + auto iType = op_it->second.iType; if (op == Opcode::FL || op == Opcode::FS) { if (func3 != 0x2) { iType = InstType::V_TYPE; diff --git a/simX/decode.h b/sim/simX/decode.h similarity index 94% rename from simX/decode.h rename to sim/simX/decode.h index 6335a494..f8f3909c 100644 --- a/simX/decode.h +++ b/sim/simX/decode.h @@ -13,7 +13,7 @@ class Decoder { public: Decoder(const ArchDef &); - std::shared_ptr decode(Word code); + std::shared_ptr decode(Word code, Word PC); private: diff --git a/simX/execute.cpp b/sim/simX/execute.cpp similarity index 79% rename from simX/execute.cpp rename to sim/simX/execute.cpp index 3feae285..01271e59 100644 --- a/simX/execute.cpp +++ b/sim/simX/execute.cpp @@ -6,9 +6,9 @@ #include #include #include -#include #include -#include "util.h" +#include +#include #include "warp.h" #include "instr.h" #include "core.h" @@ -38,30 +38,14 @@ static bool HasDivergentThreads(const ThreadMask &thread_mask, return false; } -static void update_fcrs(Core* core, int tid, int wid, bool outOfRange = false) { - if (fetestexcept(FE_INEXACT)) { - core->set_csr(CSR_FCSR, core->get_csr(CSR_FCSR, tid, wid) | 0x1, tid, wid); // set NX bit - core->set_csr(CSR_FFLAGS, core->get_csr(CSR_FFLAGS, tid, wid) | 0x1, tid, wid); // set NX bit - } - - if (fetestexcept(FE_UNDERFLOW)) { - core->set_csr(CSR_FCSR, core->get_csr(CSR_FCSR, tid, wid) | 0x2, tid, wid); // set UF bit - core->set_csr(CSR_FFLAGS, core->get_csr(CSR_FFLAGS, tid, wid) | 0x2, tid, wid); // set UF bit - } +inline uint32_t get_fpu_rm(uint32_t func3, Core* core, uint32_t tid, uint32_t wid) { + return (func3 == 0x7) ? core->get_csr(CSR_FRM, tid, wid) : func3; +} - if (fetestexcept(FE_OVERFLOW)) { - core->set_csr(CSR_FCSR, core->get_csr(CSR_FCSR, tid, wid) | 0x4, tid, wid); // set OF bit - core->set_csr(CSR_FFLAGS, core->get_csr(CSR_FFLAGS, tid, wid) | 0x4, tid, wid); // set OF bit - } - - if (fetestexcept(FE_DIVBYZERO)) { - core->set_csr(CSR_FCSR, core->get_csr(CSR_FCSR, tid, wid) | 0x8, tid, wid); // set DZ bit - core->set_csr(CSR_FFLAGS, core->get_csr(CSR_FFLAGS, tid, wid) | 0x8, tid, wid); // set DZ bit - } - - if (fetestexcept(FE_INVALID) || outOfRange) { - core->set_csr(CSR_FCSR, core->get_csr(CSR_FCSR, tid, wid) | 0x10, tid, wid); // set NV bit - core->set_csr(CSR_FFLAGS, core->get_csr(CSR_FFLAGS, tid, wid) | 0x10, tid, wid); // set NV bit +inline void update_fcrs(uint32_t fflags, Core* core, uint32_t tid, uint32_t wid) { + if (fflags) { + core->set_csr(CSR_FCSR, core->get_csr(CSR_FCSR, tid, wid) | fflags, tid, wid); + core->set_csr(CSR_FFLAGS, core->get_csr(CSR_FFLAGS, tid, wid) | fflags, tid, wid); } } @@ -114,15 +98,19 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) { } DPN(2, std::endl); } + + bool rd_write = false; switch (opcode) { case NOP: break; case LUI_INST: rddata = (immsrc << 12) & 0xfffff000; + rd_write = true; break; case AUIPC_INST: rddata = ((immsrc << 12) & 0xfffff000) + PC_; + rd_write = true; break; case R_INST: { if (func7 & 0x1) { @@ -245,6 +233,7 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) { std::abort(); } } + rd_write = true; } break; case I_INST: switch (func3) { @@ -290,6 +279,7 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) { default: std::abort(); } + rd_write = true; break; case B_INST: switch (func3) { @@ -338,12 +328,14 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) { nextPC = PC_ + immsrc; pipeline->stall_warp = true; runOnce = true; + rd_write = true; break; case JALR_INST: rddata = nextPC; nextPC = rsdata[0] + immsrc; pipeline->stall_warp = true; runOnce = true; + rd_write = true; break; case L_INST: { Word memAddr = ((rsdata[0] + immsrc) & 0xFFFFFFFC); // word aligned @@ -374,6 +366,7 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) { default: std::abort(); } + rd_write = true; } break; case S_INST: { Word memAddr = rsdata[0] + immsrc; @@ -409,31 +402,37 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) { // CSRRW rddata = csr_value; core_->set_csr(csr_addr, rsdata[0], t, id_); + rd_write = true; break; case 2: // CSRRS rddata = csr_value; core_->set_csr(csr_addr, csr_value | rsdata[0], t, id_); + rd_write = true; break; case 3: // CSRRC rddata = csr_value; core_->set_csr(csr_addr, csr_value & ~rsdata[0], t, id_); + rd_write = true; break; case 5: // CSRRWI rddata = csr_value; core_->set_csr(csr_addr, rsrc0, t, id_); + rd_write = true; break; case 6: // CSRRSI rddata = csr_value; core_->set_csr(csr_addr, csr_value | rsrc0, t, id_); + rd_write = true; break; case 7: // CSRRCI rddata = csr_value; core_->set_csr(csr_addr, csr_value & ~rsrc0, t, id_); + rd_write = true; break; default: break; @@ -475,6 +474,7 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) { } break; } + rd_write = true; break; case (FS | VS): if (func3 == 0x2) { @@ -498,328 +498,142 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) { } } break; - case FCI: // floating point computational instruction + case FCI: { + uint32_t frm = get_fpu_rm(func3, core_, t, id_); + uint32_t fflags = 0; switch (func7) { - case 0x00: //FADD - case 0x04: //FSUB - case 0x08: //FMUL - case 0x0c: //FDIV - case 0x2c: //FSQRT - { - if (fpBinIsNan(rsdata[0]) || fpBinIsNan(rsdata[1])) { - // if one of op is NaN, one of them is not quiet NaN, them set FCSR - if ((fpBinIsNan(rsdata[0])==2) | (fpBinIsNan(rsdata[1])==2)) { - core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x10, t, id_); // set NV bit - core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x10, t, id_); // set NV bit - } - if (fpBinIsNan(rsdata[0]) && fpBinIsNan(rsdata[1])) - rddata = 0x7fc00000; // canonical(quiet) NaN - else if (fpBinIsNan(rsdata[0])) - rddata = rsdata[1]; - else - rddata = rsdata[0]; - } else { - float fpsrc_0 = intregToFloat(rsdata[0]); - float fpsrc_1 = intregToFloat(rsdata[1]); - float fpDest; - - feclearexcept(FE_ALL_EXCEPT); - - if (func7 == 0x00) // FADD - fpDest = fpsrc_0 + fpsrc_1; - else if (func7==0x04) // FSUB - fpDest = fpsrc_0 - fpsrc_1; - else if (func7==0x08) // FMUL - fpDest = fpsrc_0 * fpsrc_1; - else if (func7==0x0c) // FDIV - fpDest = fpsrc_0 / fpsrc_1; - else if (func7==0x2c) // FSQRT - fpDest = sqrt(fpsrc_0); - else { - std::abort(); - } - - // update fcsrs - update_fcrs(core_, t, id_); - - D(3, "fpDest: " << fpDest); - if (fpBinIsNan(floatToBin(fpDest)) == 0) { - rddata = floatToBin(fpDest); - } else { - // According to risc-v spec p.64 section 11.3 - // If the result is NaN, it is the canonical NaN - rddata = 0x7fc00000; - } - } - } break; - - // FSGNJ.S, FSGNJN.S, FSGNJX.S - case 0x10: { - bool fsign1 = (rsdata[0] >> 31); - uint32_t fdata1 = rsdata[0] & 0x7FFFFFFF; - bool fsign2 = (rsdata[1] >> 31); - switch (func3) { - case 0: // FSGNJ.S - rddata = (fsign2 << 31) | fdata1; - break; - case 1: // FSGNJN.S - rddata = (!fsign2 << 31) | fdata1; - break; - case 2: { // FSGNJX.S - rddata = ((fsign1 ^ fsign2) << 31) | fdata1; - } break; - } - } break; - - // FMIN.S, FMAX.S - case 0x14: { - if (fpBinIsNan(rsdata[0]) || fpBinIsNan(rsdata[1])) { // if one of src is NaN - // one of them is not quiet NaN, them set FCSR - if ((fpBinIsNan(rsdata[0])==2) | (fpBinIsNan(rsdata[1])==2)) { - core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x10, t, id_); // set NV bit - core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x10, t, id_); // set NV bit - } - if (fpBinIsNan(rsdata[0]) && fpBinIsNan(rsdata[1])) - rddata = 0x7fc00000; // canonical(quiet) NaN - else if (fpBinIsNan(rsdata[0])) - rddata = rsdata[1]; - else - rddata = rsdata[0]; - } else { - uint8_t sr0IsZero = fpBinIsZero(rsdata[0]); - uint8_t sr1IsZero = fpBinIsZero(rsdata[1]); - - if (sr0IsZero && sr1IsZero && (sr0IsZero != sr1IsZero)) { - // both are zero and not equal - // handle corner case that compare +0 and -0 - if (func3) { - // FMAX.S - rddata = (sr1IsZero==2) ? rsdata[1] : rsdata[0]; - } else { - // FMIM.S - rddata = (sr1IsZero==2) ? rsdata[0] : rsdata[1]; - } - } else { - float rs1 = intregToFloat(rsdata[0]); - float rs2 = intregToFloat(rsdata[1]); - if (func3) { - // FMAX.S - float fmax = std::max(rs1, rs2); - rddata = floatToBin(fmax); - } else { - // FMIN.S - float fmin = std::min(rs1, rs2); - rddata = floatToBin(fmin); - } - } - } - } break; - - // FCVT.W.S FCVT.WU.S - case 0x60: { - float fpSrc = intregToFloat(rsdata[0]); - Word result; - bool outOfRange = false; - if (rsrc1 == 0) { - // FCVT.W.S - // Convert floating point to 32-bit signed integer - if (fpSrc > pow(2.0, 31) - 1 || fpBinIsNan(rsdata[0]) || fpBinIsInf(rsdata[0]) == 2) { - feclearexcept(FE_ALL_EXCEPT); - outOfRange = true; - // result = 2^31 - 1 - result = 0x7FFFFFFF; - } else if (fpSrc < -1*pow(2.0, 31) || fpBinIsInf(rsdata[0]) == 1) { - feclearexcept(FE_ALL_EXCEPT); - outOfRange = true; - // result = -1*2^31 - result = 0x80000000; - } else { - feclearexcept(FE_ALL_EXCEPT); - result = (int32_t) fpSrc; - } - } else { - // FCVT.WU.S - // Convert floating point to 32-bit unsigned integer - if (fpSrc > pow(2.0, 32) - 1 || fpBinIsNan(rsdata[0]) || fpBinIsInf(rsdata[0]) == 2) { - feclearexcept(FE_ALL_EXCEPT); - outOfRange = true; - // result = 2^32 - 1 - result = 0xFFFFFFFF; - } else if (fpSrc <= -1.0 || fpBinIsInf(rsdata[0]) == 1) { - feclearexcept(FE_ALL_EXCEPT); - outOfRange = true; - // result = 0 - result = 0x00000000; - } else { - feclearexcept(FE_ALL_EXCEPT); - result = (uint32_t) fpSrc; - } - } - - // update fcsrs - update_fcrs(core_, t, id_, outOfRange); - - rddata = result; - } break; - - // FMV.X.W FCLASS.S - case 0x70: { - // FCLASS.S - if (func3) { - // Examine the value in fpReg rs1 and write to integer rd - // a 10-bit mask to indicate the class of the fp number - rddata = 0; // clear all bits - - bool fsign = rsdata[0] & 0x80000000; - uint32_t expo = (rsdata[0]>>23) & 0x000000FF; - uint32_t fraction = rsdata[0] & 0x007FFFFF; - - if ((expo==0) && (fraction==0)) { - rddata = fsign ? (1<<3) : (1<<4); // +/- 0 - } else if ((expo==0) && (fraction!=0)) { - rddata = fsign ? (1<<2) : (1<<5); // +/- subnormal - } else if ((expo==0xFF) && (fraction==0)) { - rddata = fsign ? (1<<0) : (1<<7); // +/- infinity - } else if ((expo==0xFF) && (fraction!=0)) { - if (!fsign && (fraction == 0x00400000)) { - rddata = (1<<9); // quiet NaN - } else { - rddata = (1<<8); // signaling NaN - } - } else { - rddata = fsign ? (1<<1) : (1<<6); // +/- normal - } - } else { - // FMV.X.W - // Move bit values from floating-point register rs1 to integer register rd - // Since we are using integer register to represent floating point register, - // just simply assign here. - rddata = rsdata[0]; - } - } break; - - // FEQ.S FLT.S FLE.S - // rdest is integer register - case 0x50: { - // TODO: FLT.S and FLE.S perform IEEE 754-2009, signaling comparisons, set - // TODO: the invalid operation exception flag if either input is NaN - if (fpBinIsNan(rsdata[0]) || fpBinIsNan(rsdata[1])) { - // FLE.S or FLT.S - if (func3 == 0 || func3 == 1) { - // If either input is NaN, set NV bit - core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x10, t, id_); // set NV bit - core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x10, t, id_); // set NV bit - } else { // FEQ.S - // Only set NV bit if it is signaling NaN - if (fpBinIsNan(rsdata[0]) == 2 || fpBinIsNan(rsdata[1]) == 2) { - // If either input is NaN, set NV bit - core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x10, t, id_); // set NV bit - core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x10, t, id_); // set NV bit - } - } - // The result is 0 if either operand is NaN - rddata = 0; - } else { - switch(func3) { - case 0: { - // FLE.S - rddata = (intregToFloat(rsdata[0]) <= intregToFloat(rsdata[1])); - } break; - case 1: { - // FLT.S - rddata = (intregToFloat(rsdata[0]) < intregToFloat(rsdata[1])); - } break; - case 2: { - // FEQ.S - rddata = (intregToFloat(rsdata[0]) == intregToFloat(rsdata[1])); - } break; - default: - std::abort(); - } - } - } break; - - case 0x68: - // Cast integer to floating point - if (rsrc1) { - // FCVT.S.WU: convert 32-bit unsigned integer to floating point - float data = rsdata[0]; - rddata = floatToBin(data); - } else { - // FCVT.S.W: convert 32-bit signed integer to floating point - // rsdata[0] is actually a unsigned number - float data = (WordI)rsdata[0]; - rddata = floatToBin(data); - } + case 0x00: //FADD + rddata = rv_fadd(rsdata[0], rsdata[1], frm, &fflags); break; - - case 0x78: { - // FMV.W.X - // Move bit values from integer register rs1 to floating register rd - // Since we are using integer register to represent floating point register, - // just simply assign here. - rddata = rsdata[0]; + case 0x04: //FSUB + rddata = rv_fsub(rsdata[0], rsdata[1], frm, &fflags); + break; + case 0x08: //FMUL + rddata = rv_fmul(rsdata[0], rsdata[1], frm, &fflags); + break; + case 0x0c: //FDIV + rddata = rv_fdiv(rsdata[0], rsdata[1], frm, &fflags); + break; + case 0x2c: //FSQRT + rddata = rv_fsqrt(rsdata[0], frm, &fflags); + break; + case 0x10: + switch (func3) { + case 0: // FSGNJ.S + rddata = rv_fsgnj(rsdata[0], rsdata[1]); + break; + case 1: // FSGNJN.S + rddata = rv_fsgnjn(rsdata[0], rsdata[1]); + break; + case 2: // FSGNJX.S + rddata = rv_fsgnjx(rsdata[0], rsdata[1]); + break; } break; + case 0x14: + if (func3) { + // FMAX.S + rddata = rv_fmax(rsdata[0], rsdata[1], &fflags); + } else { + // FMIN.S + rddata = rv_fmin(rsdata[0], rsdata[1], &fflags); + } + break; + case 0x60: + if (rsrc1 == 0) { + // FCVT.W.S + rddata = rv_ftoi(rsdata[0], frm, &fflags); + } else { + // FCVT.WU.S + rddata = rv_ftou(rsdata[0], frm, &fflags); + } + break; + case 0x70: + if (func3) { + // FCLASS.S + rddata = rv_fclss(rsdata[0]); + } else { + // FMV.X.W + rddata = rsdata[0]; + } + break; + case 0x50: + switch(func3) { + case 0: + // FLE.S + rddata = rv_fle(rsdata[0], rsdata[1], &fflags); + break; + case 1: + // FLT.S + rddata = rv_flt(rsdata[0], rsdata[1], &fflags); + break; + case 2: + // FEQ.S + rddata = rv_feq(rsdata[0], rsdata[1], &fflags); + break; + } break; + case 0x68: + if (rsrc1) { + // FCVT.S.WU: + rddata = rv_utof(rsdata[0], frm, &fflags); + } else { + // FCVT.S.W: + rddata = rv_itof(rsdata[0], frm, &fflags); + } + break; + case 0x78: + // FMV.W.X + rddata = rsdata[0]; + break; } - break; - + update_fcrs(fflags, core_, t, id_); + rd_write = true; + } break; case FMADD: case FMSUB: case FMNMADD: case FMNMSUB: { - // multiplicands are infinity and zero, them set FCSR - if (fpBinIsZero(rsdata[0]) || fpBinIsZero(rsdata[1]) || fpBinIsInf(rsdata[0]) || fpBinIsInf(rsdata[1])) { - core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x10, t, id_); // set NV bit - core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x10, t, id_); // set NV bit - } - if (fpBinIsNan(rsdata[0]) || fpBinIsNan(rsdata[1]) || fpBinIsNan(rsdata[2])) { - // if one of op is NaN, if addend is not quiet NaN, them set FCSR - if ((fpBinIsNan(rsdata[0])==2) | (fpBinIsNan(rsdata[1])==2) | (fpBinIsNan(rsdata[1])==2)) { - core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x10, t, id_); // set NV bit - core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x10, t, id_); // set NV bit - } - rddata = 0x7fc00000; // canonical(quiet) NaN - } else { - float rs1 = intregToFloat(rsdata[0]); - float rs2 = intregToFloat(rsdata[1]); - float rs3 = intregToFloat(rsdata[2]); - float fpDest(0.0); - feclearexcept(FE_ALL_EXCEPT); - switch (opcode) { - case FMADD: - // rd = (rs1*rs2)+rs3 - fpDest = (rs1 * rs2) + rs3; break; - case FMSUB: - // rd = (rs1*rs2)-rs3 - fpDest = (rs1 * rs2) - rs3; break; - case FMNMADD: - // rd = -(rs1*rs2)+rs3 - fpDest = -1*(rs1 * rs2) - rs3; break; - case FMNMSUB: - // rd = -(rs1*rs2)-rs3 - fpDest = -1*(rs1 * rs2) + rs3; break; - default: - std::abort(); - break; - } - - // update fcsrs - update_fcrs(core_, t, id_); - - rddata = floatToBin(fpDest); - } - } - break; + int frm = get_fpu_rm(func3, core_, t, id_); + Word fflags = 0; + switch (opcode) { + case FMADD: + rddata = rv_fmadd(rsdata[0], rsdata[1], rsdata[2], frm, &fflags); + break; + case FMSUB: + rddata = rv_fmsub(rsdata[0], rsdata[1], rsdata[2], frm, &fflags); + break; + case FMNMADD: + rddata = rv_fnmadd(rsdata[0], rsdata[1], rsdata[2], frm, &fflags); + break; + case FMNMSUB: + rddata = rv_fnmsub(rsdata[0], rsdata[1], rsdata[2], frm, &fflags); + break; + default: + break; + } + update_fcrs(fflags, core_, t, id_); + rd_write = true; + } break; case GPGPU: switch (func3) { case 0: { - // TMC - int active_threads = std::min(rsdata[0], num_threads); - tmask_.reset(); - for (int i = 0; i < active_threads; ++i) { - tmask_[i] = true; + // TMC + if (rsrc1) { + // predicate mode + ThreadMask pred; + for (int i = 0; i < num_threads; ++i) { + pred[i] = tmask_[i] ? (iRegFile_[i][rsrc0] != 0) : 0; + } + if (pred.any()) { + tmask_ &= pred; + } + } else { + tmask_.reset(); + for (int i = 0; i < num_threads; ++i) { + tmask_[i] = rsdata[0] & (1 << i); + } } + D(3, "*** TMC " << tmask_); active_ = tmask_.any(); pipeline->stall_warp = true; runOnce = true; @@ -858,7 +672,7 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) { for (int i = 0; i < num_threads; ++i) DPN(3, e.tmask[num_threads-i-1]); DPN(3, ", PC=0x" << std::hex << e.PC << "\n"); } else { - D(3, "*** Unanimous pred: r" << rsrc0 << ", val: " << rsdata[0]); + D(3, "*** Unanimous pred"); DomStackEntry e(tmask_); e.unanimous = true; domStack_.push(e); @@ -1754,20 +1568,22 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) { std::abort(); } - int rdt = instr.getRDType(); - switch (rdt) { - case 1: - if (rdest) { - D(2, "[" << std::dec << t << "] Dest Regs: r" << rdest << "=0x" << std::hex << std::hex << rddata); - iregs[rdest] = rddata; + if (rd_write) { + int rdt = instr.getRDType(); + switch (rdt) { + case 1: + if (rdest) { + D(2, "[" << std::dec << t << "] Dest Regs: r" << rdest << "=0x" << std::hex << std::hex << rddata); + iregs[rdest] = rddata; + } + break; + case 2: + D(2, "[" << std::dec << t << "] Dest Regs: fr" << rdest << "=0x" << std::hex << std::hex << rddata); + fregs[rdest] = rddata; + break; + default: + break; } - break; - case 2: - D(2, "[" << std::dec << t << "] Dest Regs: fr" << rdest << "=0x" << std::hex << std::hex << rddata); - fregs[rdest] = rddata; - break; - default: - break; } } diff --git a/simX/instr.h b/sim/simX/instr.h similarity index 100% rename from simX/instr.h rename to sim/simX/instr.h diff --git a/simX/main.cpp b/sim/simX/main.cpp similarity index 86% rename from simX/main.cpp rename to sim/simX/main.cpp index 21660d91..9af8ff02 100644 --- a/simX/main.cpp +++ b/sim/simX/main.cpp @@ -53,10 +53,19 @@ int main(int argc, char **argv) { Decoder decoder(arch); MemoryUnit mu(0, arch.wsize(), true); - RAM old_ram((1<<12), (1<<20)); - old_ram.loadHexImage(imgFileName.c_str()); + RAM ram((1<<12), (1<<20)); - mu.attach(old_ram, 0, 0xFFFFFFFF); + std::string program_ext(fileExtension(imgFileName.c_str())); + if (program_ext == "bin") { + ram.loadBinImage(imgFileName.c_str(), STARTUP_ADDR); + } else if (program_ext == "hex") { + ram.loadHexImage(imgFileName.c_str()); + } else { + std::cout << "*** error: only *.bin or *.hex images supported." << std::endl; + return -1; + } + + mu.attach(ram, 0, 0xFFFFFFFF); struct stat hello; fstat(0, &hello); diff --git a/simX/pipeline.cpp b/sim/simX/pipeline.cpp similarity index 100% rename from simX/pipeline.cpp rename to sim/simX/pipeline.cpp diff --git a/simX/pipeline.h b/sim/simX/pipeline.h similarity index 93% rename from simX/pipeline.h rename to sim/simX/pipeline.h index 42cb2af1..f8899a63 100644 --- a/simX/pipeline.h +++ b/sim/simX/pipeline.h @@ -2,8 +2,9 @@ #pragma once #include +#include +#include "types.h" #include "debug.h" -#include "util.h" namespace vortex { diff --git a/simX/types.h b/sim/simX/types.h similarity index 74% rename from simX/types.h rename to sim/simX/types.h index 256118b2..ca732040 100644 --- a/simX/types.h +++ b/sim/simX/types.h @@ -19,13 +19,4 @@ typedef std::bitset<32> ThreadMask; typedef std::bitset<32> WarpMask; -enum MemFlags { - RD_USR = 1, - WR_USR = 2, - EX_USR = 4, - RD_SUP = 8, - WR_SUP = 16, - EX_SUP = 32 -}; - } \ No newline at end of file diff --git a/simX/warp.cpp b/sim/simX/warp.cpp similarity index 96% rename from simX/warp.cpp rename to sim/simX/warp.cpp index 05df1837..a505fe5c 100644 --- a/simX/warp.cpp +++ b/sim/simX/warp.cpp @@ -3,8 +3,8 @@ #include #include #include +#include -#include "util.h" #include "instr.h" #include "core.h" @@ -36,7 +36,7 @@ void Warp::step(Pipeline *pipeline) { /* Fetch and decode. */ Word fetched = core_->icache_fetch(PC_); - auto instr = core_->decoder().decode(fetched); + auto instr = core_->decoder().decode(fetched, PC_); // Update pipeline pipeline->valid = true; diff --git a/simX/warp.h b/sim/simX/warp.h similarity index 94% rename from simX/warp.h rename to sim/simX/warp.h index da91f78d..7473d858 100644 --- a/simX/warp.h +++ b/sim/simX/warp.h @@ -37,6 +37,7 @@ struct vtype { int vsew; int vlmul; }; + class Warp { public: Warp(Core *core, Word id); @@ -74,6 +75,12 @@ public: active_ = tmask_.any(); } + Word getTmask() const { + if (active_) + return tmask_.to_ulong(); + return 0; + } + Word getIRegValue(int reg) const { return iRegFile_[0][reg]; } diff --git a/driver/opae/vlsim/.gitignore b/sim/vlsim/.gitignore similarity index 100% rename from driver/opae/vlsim/.gitignore rename to sim/vlsim/.gitignore diff --git a/sim/vlsim/Makefile b/sim/vlsim/Makefile new file mode 100644 index 00000000..7de01df9 --- /dev/null +++ b/sim/vlsim/Makefile @@ -0,0 +1,103 @@ +RTL_DIR = ../../hw/rtl +DPI_DIR = ../../hw/dpi +SCRIPT_DIR=../../hw/scripts + +CXXFLAGS += -std=c++11 -Wall -Wextra -Wfatal-errors +CXXFLAGS += -fPIC -Wno-maybe-uninitialized +CXXFLAGS += -I.. -I../../../hw -I../../common +CXXFLAGS += -I../../common/softfloat/source/include + +LDFLAGS += -shared ../../common/softfloat/build/Linux-x86_64-GCC/softfloat.a + +# control RTL debug print states +DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE +DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_ICACHE +DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_DCACHE +DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_BANK +DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSHR +DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_TAG +DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_DATA +DBG_PRINT_FLAGS += -DDBG_PRINT_MEM +DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE +DBG_PRINT_FLAGS += -DDBG_PRINT_AVS +DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE + +DBG_FLAGS += $(DBG_PRINT_FLAGS) +DBG_FLAGS += -DDBG_CACHE_REQ_INFO + +SRCS = ../common/util.cpp ../common/mem.cpp ../common/rvfloats.cpp +SRCS += $(DPI_DIR)/util_dpi.cpp $(DPI_DIR)/float_dpi.cpp +SRCS += fpga.cpp opae_sim.cpp + +FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src -I$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(RTL_DIR)/fp_cores/fpnew/src +RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache $(FPU_INCLUDE) +RTL_INCLUDE += -I$(RTL_DIR)/afu -I$(RTL_DIR)/afu/ccip + +TOP = vortex_afu_shim + +VL_FLAGS = --exe --cc $(TOP) --top-module $(TOP) +VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic +VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO +VL_FLAGS += --x-initial unique --x-assign unique +VL_FLAGS += verilator.vlt +VL_FLAGS += $(RTL_INCLUDE) + +VL_FLAGS += $(CONFIGS) +CXXFLAGS += $(CONFIGS) + +# Enable Verilator multithreaded simulation +#THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') +#VL_FLAGS += --threads $(THREADS) + +# Debugigng +ifdef DEBUG + VL_FLAGS += -DVCD_OUTPUT --trace --trace-structs $(DBG_FLAGS) + CXXFLAGS += -g -O0 -DVCD_OUTPUT $(DBG_FLAGS) +else + VL_FLAGS += -DNDEBUG + CXXFLAGS += -O2 -DNDEBUG +endif + +# Enable scope analyzer +ifdef SCOPE + VL_FLAGS += -DSCOPE + CXXFLAGS += -DSCOPE +endif + +# Enable perf counters +ifdef PERF + VL_FLAGS += -DPERF_ENABLE + CXXFLAGS += -DPERF_ENABLE +endif + +# use our OPAE shim +VL_FLAGS += -DNOPAE +CXXFLAGS += -DNOPAE + +# ALU backend +VL_FLAGS += -DIMUL_DPI +VL_FLAGS += -DIDIV_DPI + +# FPU backend +FPU_CORE ?= FPU_DPI +VL_FLAGS += -D$(FPU_CORE) + +PROJECT = libopae-c-vlsim + +all: shared + +vortex_afu.h : $(RTL_DIR)/afu/vortex_afu.vh + $(SCRIPT_DIR)/gen_config.py -i $(RTL_DIR)/afu/vortex_afu.vh -o vortex_afu.h + +shared: $(SRCS) vortex_afu.h + verilator --build $(VL_FLAGS) $(SRCS) -CFLAGS '$(CXXFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT).so + +static: $(SRCS) vortex_afu.h + verilator --build $(VL_FLAGS) $(SRCS) -CFLAGS '$(CXXFLAGS)' -LDFLAGS '$(LDFLAGS)' + $(AR) rcs $(PROJECT).a obj_dir/*.o ../common/softfloat/build/Linux-x86_64-GCC/*.o + +clean-static: + rm -rf $(PROJECT).a obj_dir vortex_afu.h + +clean: clean-static + rm -rf $(PROJECT).so diff --git a/driver/opae/vlsim/fpga.cpp b/sim/vlsim/fpga.cpp similarity index 98% rename from driver/opae/vlsim/fpga.cpp rename to sim/vlsim/fpga.cpp index 3c5ae726..1c861513 100644 --- a/driver/opae/vlsim/fpga.cpp +++ b/sim/vlsim/fpga.cpp @@ -9,6 +9,8 @@ #include "opae_sim.h" #include +using namespace vortex; + extern fpga_result fpgaOpen(fpga_token token, fpga_handle *handle, int flags) { if (NULL == handle || flags != 0) return FPGA_INVALID_PARAM; diff --git a/driver/opae/vlsim/fpga.h b/sim/vlsim/fpga.h similarity index 100% rename from driver/opae/vlsim/fpga.h rename to sim/vlsim/fpga.h diff --git a/driver/opae/vlsim/opae_sim.cpp b/sim/vlsim/opae_sim.cpp similarity index 55% rename from driver/opae/vlsim/opae_sim.cpp rename to sim/vlsim/opae_sim.cpp index a5a6454e..ced1e233 100644 --- a/driver/opae/vlsim/opae_sim.cpp +++ b/sim/vlsim/opae_sim.cpp @@ -1,7 +1,17 @@ #include "opae_sim.h" + +#include +#include "Vvortex_afu_shim.h" +#include "Vvortex_afu_shim__Syms.h" + +#ifdef VCD_OUTPUT +#include +#endif + #include #include #include +#include #define CCI_LATENCY 8 #define CCI_RAND_MOD 8 @@ -10,6 +20,14 @@ #define ENABLE_MEM_STALLS +#ifndef TRACE_START_TIME +#define TRACE_START_TIME 0ull +#endif + +#ifndef TRACE_STOP_TIME +#define TRACE_STOP_TIME -1ull +#endif + #ifndef MEM_LATENCY #define MEM_LATENCY 24 #endif @@ -26,7 +44,9 @@ #define VERILATOR_RESET_VALUE 2 #endif -uint64_t timestamp = 0; +using namespace vortex; + +static uint64_t timestamp = 0; double sc_time_stamp() { return timestamp; @@ -49,25 +69,74 @@ static void __aligned_free(void *ptr) { /////////////////////////////////////////////////////////////////////////////// +static bool trace_enabled = false; +static uint64_t trace_start_time = TRACE_START_TIME; +static uint64_t trace_stop_time = TRACE_STOP_TIME; + +bool sim_trace_enabled() { + if (timestamp >= trace_start_time + && timestamp < trace_stop_time) + return true; + return trace_enabled; +} + +void sim_trace_enable(bool enable) { + trace_enabled = enable; +} + +/////////////////////////////////////////////////////////////////////////////// + +namespace vortex { +class VL_OBJ { +public: +#ifdef AXI_BUS + VVortex_axi *device; +#else + Vvortex_afu_shim *device; +#endif +#ifdef VCD_OUTPUT + VerilatedVcdC *trace; +#endif + + VL_OBJ() { + // force random values for unitialized signals + Verilated::randReset(VERILATOR_RESET_VALUE); + Verilated::randSeed(50); + + // Turn off assertion before reset + Verilated::assertOn(false); + + #ifdef AXI_BUS + this->device = new Vvortex_afu_shim(); + #else + this->device = new Vvortex_afu_shim(); + #endif + + #ifdef VCD_OUTPUT + Verilated::traceEverOn(true); + this->trace = new VerilatedVcdC(); + this->device->trace(this->trace, 99); + this->trace->open("trace.vcd"); + #endif + } + + ~VL_OBJ() { + #ifdef VCD_OUTPUT + this->trace->close(); + delete this->trace; + #endif + delete this->device; + } +}; +} + +/////////////////////////////////////////////////////////////////////////////// + opae_sim::opae_sim() : stop_(false) - , host_buffer_ids_(0) -{ - // force random values for unitialized signals - Verilated::randReset(VERILATOR_RESET_VALUE); - Verilated::randSeed(50); - - // Turn off assertion before reset - Verilated::assertOn(false); - - vortex_afu_ = new Vvortex_afu_shim(); - -#ifdef VCD_OUTPUT - Verilated::traceEverOn(true); - trace_ = new VerilatedVcdC(); - vortex_afu_->trace(trace_, 99); - trace_->open("trace.vcd"); -#endif + , host_buffer_ids_(0) { + vl_obj_ = new VL_OBJ(); + ram_ = new RAM((1<<12), (1<<20)); // reset the device this->reset(); @@ -85,14 +154,12 @@ opae_sim::~opae_sim() { stop_ = true; if (future_.valid()) { future_.wait(); - } -#ifdef VCD_OUTPUT - trace_->close(); -#endif + } for (auto& buffer : host_buffers_) { __aligned_free(buffer.second.data); } - delete vortex_afu_; + delete vl_obj_; + delete ram_; } int opae_sim::prepare_buffer(uint64_t len, void **buf_addr, uint64_t *wsid, int flags) { @@ -125,26 +192,26 @@ void opae_sim::get_io_address(uint64_t wsid, uint64_t *ioaddr) { void opae_sim::read_mmio64(uint32_t mmio_num, uint64_t offset, uint64_t *value) { std::lock_guard guard(mutex_); - vortex_afu_->vcp2af_sRxPort_c0_mmioRdValid = 1; - vortex_afu_->vcp2af_sRxPort_c0_ReqMmioHdr_address = offset / 4; - vortex_afu_->vcp2af_sRxPort_c0_ReqMmioHdr_length = 1; - vortex_afu_->vcp2af_sRxPort_c0_ReqMmioHdr_tid = 0; + vl_obj_->device->vcp2af_sRxPort_c0_mmioRdValid = 1; + vl_obj_->device->vcp2af_sRxPort_c0_ReqMmioHdr_address = offset / 4; + vl_obj_->device->vcp2af_sRxPort_c0_ReqMmioHdr_length = 1; + vl_obj_->device->vcp2af_sRxPort_c0_ReqMmioHdr_tid = 0; this->step(); - vortex_afu_->vcp2af_sRxPort_c0_mmioRdValid = 0; - assert(vortex_afu_->af2cp_sTxPort_c2_mmioRdValid); - *value = vortex_afu_->af2cp_sTxPort_c2_data; + vl_obj_->device->vcp2af_sRxPort_c0_mmioRdValid = 0; + assert(vl_obj_->device->af2cp_sTxPort_c2_mmioRdValid); + *value = vl_obj_->device->af2cp_sTxPort_c2_data; } void opae_sim::write_mmio64(uint32_t mmio_num, uint64_t offset, uint64_t value) { std::lock_guard guard(mutex_); - vortex_afu_->vcp2af_sRxPort_c0_mmioWrValid = 1; - vortex_afu_->vcp2af_sRxPort_c0_ReqMmioHdr_address = offset / 4; - vortex_afu_->vcp2af_sRxPort_c0_ReqMmioHdr_length = 1; - vortex_afu_->vcp2af_sRxPort_c0_ReqMmioHdr_tid = 0; - memcpy(vortex_afu_->vcp2af_sRxPort_c0_data, &value, 8); + vl_obj_->device->vcp2af_sRxPort_c0_mmioWrValid = 1; + vl_obj_->device->vcp2af_sRxPort_c0_ReqMmioHdr_address = offset / 4; + vl_obj_->device->vcp2af_sRxPort_c0_ReqMmioHdr_length = 1; + vl_obj_->device->vcp2af_sRxPort_c0_ReqMmioHdr_tid = 0; + memcpy(vl_obj_->device->vcp2af_sRxPort_c0_data, &value, 8); this->step(); - vortex_afu_->vcp2af_sRxPort_c0_mmioWrValid = 0; + vl_obj_->device->vcp2af_sRxPort_c0_mmioWrValid = 0; } /////////////////////////////////////////////////////////////////////////////// @@ -152,29 +219,29 @@ void opae_sim::write_mmio64(uint32_t mmio_num, uint64_t offset, uint64_t value) void opae_sim::reset() { cci_reads_.clear(); cci_writes_.clear(); - vortex_afu_->vcp2af_sRxPort_c0_mmioRdValid = 0; - vortex_afu_->vcp2af_sRxPort_c0_mmioWrValid = 0; - vortex_afu_->vcp2af_sRxPort_c0_rspValid = 0; - vortex_afu_->vcp2af_sRxPort_c1_rspValid = 0; - vortex_afu_->vcp2af_sRxPort_c0_TxAlmFull = 0; - vortex_afu_->vcp2af_sRxPort_c1_TxAlmFull = 0; + vl_obj_->device->vcp2af_sRxPort_c0_mmioRdValid = 0; + vl_obj_->device->vcp2af_sRxPort_c0_mmioWrValid = 0; + vl_obj_->device->vcp2af_sRxPort_c0_rspValid = 0; + vl_obj_->device->vcp2af_sRxPort_c1_rspValid = 0; + vl_obj_->device->vcp2af_sRxPort_c0_TxAlmFull = 0; + vl_obj_->device->vcp2af_sRxPort_c1_TxAlmFull = 0; for (int b = 0; b < MEMORY_BANKS; ++b) { mem_reads_[b].clear(); - vortex_afu_->avs_readdatavalid[b] = 0; - vortex_afu_->avs_waitrequest[b] = 0; + vl_obj_->device->avs_readdatavalid[b] = 0; + vl_obj_->device->avs_waitrequest[b] = 0; } - vortex_afu_->reset = 1; + vl_obj_->device->reset = 1; for (int i = 0; i < RESET_DELAY; ++i) { - vortex_afu_->clk = 0; + vl_obj_->device->clk = 0; this->eval(); - vortex_afu_->clk = 1; + vl_obj_->device->clk = 1; this->eval(); } - vortex_afu_->reset = 0; + vl_obj_->device->reset = 0; // Turn on assertion after reset Verilated::assertOn(true); @@ -185,9 +252,9 @@ void opae_sim::step() { this->sTxPort_bus(); this->avs_bus(); - vortex_afu_->clk = 0; + vl_obj_->device->clk = 0; this->eval(); - vortex_afu_->clk = 1; + vl_obj_->device->clk = 1; this->eval(); #ifndef NDEBUG @@ -196,17 +263,19 @@ void opae_sim::step() { } void opae_sim::eval() { - vortex_afu_->eval(); + vl_obj_->device->eval(); #ifdef VCD_OUTPUT - trace_->dump(timestamp); + if (sim_trace_enabled()) { + vl_obj_->trace->dump(timestamp); + } #endif ++timestamp; } void opae_sim::sRxPort_bus() { // check mmio request - bool mmio_req_enabled = vortex_afu_->vcp2af_sRxPort_c0_mmioRdValid - || vortex_afu_->vcp2af_sRxPort_c0_mmioWrValid; + bool mmio_req_enabled = vl_obj_->device->vcp2af_sRxPort_c0_mmioRdValid + || vl_obj_->device->vcp2af_sRxPort_c0_mmioWrValid; // schedule CCI read responses std::list::iterator cci_rd_it(cci_reads_.end()); @@ -229,22 +298,22 @@ void opae_sim::sRxPort_bus() { } // send CCI write response - vortex_afu_->vcp2af_sRxPort_c1_rspValid = 0; + vl_obj_->device->vcp2af_sRxPort_c1_rspValid = 0; if (cci_wr_it != cci_writes_.end()) { - vortex_afu_->vcp2af_sRxPort_c1_rspValid = 1; - vortex_afu_->vcp2af_sRxPort_c1_hdr_resp_type = 0; - vortex_afu_->vcp2af_sRxPort_c1_hdr_mdata = cci_wr_it->mdata; + vl_obj_->device->vcp2af_sRxPort_c1_rspValid = 1; + vl_obj_->device->vcp2af_sRxPort_c1_hdr_resp_type = 0; + vl_obj_->device->vcp2af_sRxPort_c1_hdr_mdata = cci_wr_it->mdata; cci_writes_.erase(cci_wr_it); } // send CCI read response (ensure mmio disabled) - vortex_afu_->vcp2af_sRxPort_c0_rspValid = 0; + vl_obj_->device->vcp2af_sRxPort_c0_rspValid = 0; if (!mmio_req_enabled && (cci_rd_it != cci_reads_.end())) { - vortex_afu_->vcp2af_sRxPort_c0_rspValid = 1; - vortex_afu_->vcp2af_sRxPort_c0_hdr_resp_type = 0; - memcpy(vortex_afu_->vcp2af_sRxPort_c0_data, cci_rd_it->data.data(), CACHE_BLOCK_SIZE); - vortex_afu_->vcp2af_sRxPort_c0_hdr_mdata = cci_rd_it->mdata; + vl_obj_->device->vcp2af_sRxPort_c0_rspValid = 1; + vl_obj_->device->vcp2af_sRxPort_c0_hdr_resp_type = 0; + memcpy(vl_obj_->device->vcp2af_sRxPort_c0_data, cci_rd_it->data.data(), CACHE_BLOCK_SIZE); + vl_obj_->device->vcp2af_sRxPort_c0_hdr_mdata = cci_rd_it->mdata; /*printf("%0ld: [sim] CCI Rd Rsp: addr=%ld, mdata=%d, data=", timestamp, cci_rd_it->addr, cci_rd_it->mdata); for (int i = 0; i < CACHE_BLOCK_SIZE; ++i) printf("%02x", cci_rd_it->data[CACHE_BLOCK_SIZE-1-i]); @@ -255,32 +324,32 @@ void opae_sim::sRxPort_bus() { void opae_sim::sTxPort_bus() { // process read requests - if (vortex_afu_->af2cp_sTxPort_c0_valid) { - assert(!vortex_afu_->vcp2af_sRxPort_c0_TxAlmFull); + if (vl_obj_->device->af2cp_sTxPort_c0_valid) { + assert(!vl_obj_->device->vcp2af_sRxPort_c0_TxAlmFull); cci_rd_req_t cci_req; cci_req.cycles_left = CCI_LATENCY + (timestamp % CCI_RAND_MOD); - cci_req.addr = vortex_afu_->af2cp_sTxPort_c0_hdr_address; - cci_req.mdata = vortex_afu_->af2cp_sTxPort_c0_hdr_mdata; - auto host_ptr = (uint64_t*)(vortex_afu_->af2cp_sTxPort_c0_hdr_address * CACHE_BLOCK_SIZE); + cci_req.addr = vl_obj_->device->af2cp_sTxPort_c0_hdr_address; + cci_req.mdata = vl_obj_->device->af2cp_sTxPort_c0_hdr_mdata; + auto host_ptr = (uint64_t*)(vl_obj_->device->af2cp_sTxPort_c0_hdr_address * CACHE_BLOCK_SIZE); memcpy(cci_req.data.data(), host_ptr, CACHE_BLOCK_SIZE); - //printf("%0ld: [sim] CCI Rd Req: addr=%ld, mdata=%d\n", timestamp, vortex_afu_->af2cp_sTxPort_c0_hdr_address, cci_req.mdata); + //printf("%0ld: [sim] CCI Rd Req: addr=%ld, mdata=%d\n", timestamp, vl_obj_->device->af2cp_sTxPort_c0_hdr_address, cci_req.mdata); cci_reads_.emplace_back(cci_req); } // process write requests - if (vortex_afu_->af2cp_sTxPort_c1_valid) { - assert(!vortex_afu_->vcp2af_sRxPort_c1_TxAlmFull); + if (vl_obj_->device->af2cp_sTxPort_c1_valid) { + assert(!vl_obj_->device->vcp2af_sRxPort_c1_TxAlmFull); cci_wr_req_t cci_req; cci_req.cycles_left = CCI_LATENCY + (timestamp % CCI_RAND_MOD); - cci_req.mdata = vortex_afu_->af2cp_sTxPort_c1_hdr_mdata; - auto host_ptr = (uint64_t*)(vortex_afu_->af2cp_sTxPort_c1_hdr_address * CACHE_BLOCK_SIZE); - memcpy(host_ptr, vortex_afu_->af2cp_sTxPort_c1_data, CACHE_BLOCK_SIZE); + cci_req.mdata = vl_obj_->device->af2cp_sTxPort_c1_hdr_mdata; + auto host_ptr = (uint64_t*)(vl_obj_->device->af2cp_sTxPort_c1_hdr_address * CACHE_BLOCK_SIZE); + memcpy(host_ptr, vl_obj_->device->af2cp_sTxPort_c1_data, CACHE_BLOCK_SIZE); cci_writes_.emplace_back(cci_req); } // check queues overflow - vortex_afu_->vcp2af_sRxPort_c0_TxAlmFull = (cci_reads_.size() >= (CCI_RQ_SIZE-1)); - vortex_afu_->vcp2af_sRxPort_c1_TxAlmFull = (cci_writes_.size() >= (CCI_WQ_SIZE-1)); + vl_obj_->device->vcp2af_sRxPort_c0_TxAlmFull = (cci_reads_.size() >= (CCI_RQ_SIZE-1)); + vl_obj_->device->vcp2af_sRxPort_c1_TxAlmFull = (cci_writes_.size() >= (CCI_WQ_SIZE-1)); } void opae_sim::avs_bus() { @@ -299,10 +368,10 @@ void opae_sim::avs_bus() { } // send memory response - vortex_afu_->avs_readdatavalid[b] = 0; + vl_obj_->device->avs_readdatavalid[b] = 0; if (mem_rd_it != mem_reads_[b].end()) { - vortex_afu_->avs_readdatavalid[b] = 1; - memcpy(vortex_afu_->avs_readdata[b], mem_rd_it->data.data(), MEM_BLOCK_SIZE); + vl_obj_->device->avs_readdatavalid[b] = 1; + memcpy(vl_obj_->device->avs_readdata[b], mem_rd_it->data.data(), MEM_BLOCK_SIZE); uint32_t addr = mem_rd_it->addr; mem_reads_[b].erase(mem_rd_it); /*printf("%0ld: [sim] MEM Rd Rsp: bank=%d, addr=%x, pending={", timestamp, b, addr * MEM_BLOCK_SIZE); @@ -328,29 +397,30 @@ void opae_sim::avs_bus() { // process memory requests if (!mem_stalled) { - assert(!vortex_afu_->avs_read[b] || !vortex_afu_->avs_write[b]); - if (vortex_afu_->avs_write[b]) { - uint64_t byteen = vortex_afu_->avs_byteenable[b]; - unsigned base_addr = vortex_afu_->avs_address[b] * MEM_BLOCK_SIZE; - uint8_t* data = (uint8_t*)(vortex_afu_->avs_writedata[b]); + assert(!vl_obj_->device->avs_read[b] || !vl_obj_->device->avs_write[b]); + if (vl_obj_->device->avs_write[b]) { + uint64_t byteen = vl_obj_->device->avs_byteenable[b]; + unsigned base_addr = vl_obj_->device->avs_address[b] * MEM_BLOCK_SIZE; + uint8_t* data = (uint8_t*)(vl_obj_->device->avs_writedata[b]); for (int i = 0; i < MEM_BLOCK_SIZE; i++) { if ((byteen >> i) & 0x1) { - ram_[base_addr + i] = data[i]; + (*ram_)[base_addr + i] = data[i]; } } /*printf("%0ld: [sim] MEM Wr Req: bank=%d, addr=%x, data=", timestamp, b, base_addr); for (int i = 0; i < MEM_BLOCK_SIZE; i++) { - printf("%0x", data[(MEM_BLOCK_SIZE-1)-i]); + printf("%02x", data[(MEM_BLOCK_SIZE-1)-i]); } printf("\n");*/ } - if (vortex_afu_->avs_read[b]) { + if (vl_obj_->device->avs_read[b]) { mem_rd_req_t mem_req; - mem_req.addr = vortex_afu_->avs_address[b]; - ram_.read(vortex_afu_->avs_address[b] * MEM_BLOCK_SIZE, MEM_BLOCK_SIZE, mem_req.data.data()); + mem_req.addr = vl_obj_->device->avs_address[b]; + ram_->read(mem_req.data.data(), vl_obj_->device->avs_address[b] * MEM_BLOCK_SIZE, MEM_BLOCK_SIZE); mem_req.cycles_left = MEM_LATENCY; for (auto& rsp : mem_reads_[b]) { if (mem_req.addr == rsp.addr) { + // duplicate requests receive the same cycle delay mem_req.cycles_left = rsp.cycles_left; break; } @@ -367,6 +437,6 @@ void opae_sim::avs_bus() { } } - vortex_afu_->avs_waitrequest[b] = mem_stalled; + vl_obj_->device->avs_waitrequest[b] = mem_stalled; } } \ No newline at end of file diff --git a/driver/opae/vlsim/opae_sim.h b/sim/vlsim/opae_sim.h similarity index 84% rename from driver/opae/vlsim/opae_sim.h rename to sim/vlsim/opae_sim.h index 46b165dd..aa19532f 100644 --- a/driver/opae/vlsim/opae_sim.h +++ b/sim/vlsim/opae_sim.h @@ -1,17 +1,7 @@ #pragma once -#include "verilated.h" -//#include "verilated_stub.h" -#include "Vvortex_afu_shim.h" -#include "Vvortex_afu_shim__Syms.h" - -#ifdef VCD_OUTPUT -#include -#endif - #include -#include "vortex_afu.h" -#include "ram.h" +#include #include #include @@ -31,6 +21,11 @@ #define CACHE_BLOCK_SIZE 64 +namespace vortex { + +class VL_OBJ; +class RAM; + class opae_sim { public: @@ -97,9 +92,9 @@ private: std::mutex mutex_; - RAM ram_; - Vvortex_afu_shim *vortex_afu_; -#ifdef VCD_OUTPUT - VerilatedVcdC *trace_; -#endif -}; \ No newline at end of file + RAM *ram_; + + VL_OBJ* vl_obj_; +}; + +} \ No newline at end of file diff --git a/driver/opae/vlsim/verilator.vlt b/sim/vlsim/verilator.vlt similarity index 100% rename from driver/opae/vlsim/verilator.vlt rename to sim/vlsim/verilator.vlt diff --git a/driver/opae/vlsim/vortex_afu_shim.sv b/sim/vlsim/vortex_afu_shim.sv similarity index 100% rename from driver/opae/vlsim/vortex_afu_shim.sv rename to sim/vlsim/vortex_afu_shim.sv diff --git a/simX/Makefile b/simX/Makefile deleted file mode 100644 index 8b0e2ef3..00000000 --- a/simX/Makefile +++ /dev/null @@ -1,32 +0,0 @@ -#CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors -CXXFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors - -CXXFLAGS += -Wno-maybe-uninitialized -CXXFLAGS += -I. -I../hw -CXXFLAGS += -DDUMP_PERF_STATS - -TOP = vx_cache_sim - -RTL_DIR = ../hw/rtl - -PROJECT = simX - -SRCS = util.cpp args.cpp mem.cpp pipeline.cpp warp.cpp core.cpp decode.cpp execute.cpp main.cpp - -# Debugigng -ifdef DEBUG - CXXFLAGS += -DDEBUG_LEVEL=3 -else - CXXFLAGS += -DNDEBUG -endif - -all: $(PROJECT) - -$(PROJECT): $(SRCS) - $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ - -.depend: $(SRCS) - $(CXX) $(CXXFLAGS) -MM $^ > .depend; - -clean: - rm -rf $(PROJECT) *.o .depend diff --git a/simX/mem.h b/simX/mem.h deleted file mode 100644 index d7426b41..00000000 --- a/simX/mem.h +++ /dev/null @@ -1,157 +0,0 @@ -#pragma once - -#include -#include -#include -#include -#include "types.h" - -namespace vortex { -struct BadAddress {}; - -class MemDevice { -public: - virtual ~MemDevice() {} - virtual Size size() const = 0; - virtual void read(Addr addr, void *data, Size size) = 0; - virtual void write(Addr addr, const void *data, Size size) = 0; -}; - -/////////////////////////////////////////////////////////////////////////////// - -class RamMemDevice : public MemDevice { -public: - RamMemDevice(Size size, Size wordSize); - RamMemDevice(const char *filename, Size wordSize); - ~RamMemDevice() {} - - void read(Addr addr, void *data, Size size) override; - void write(Addr addr, const void *data, Size size) override; - - virtual Size size() const { - return contents_.size(); - }; - -protected: - std::vector contents_; - Size wordSize_; -}; - -/////////////////////////////////////////////////////////////////////////////// - -class RomMemDevice : public RamMemDevice { -public: - RomMemDevice(const char *filename, Size wordSize) - : RamMemDevice(filename, wordSize) - {} - - RomMemDevice(Size size, Size wordSize) - : RamMemDevice(size, wordSize) - {} - - ~RomMemDevice(); - - void write(Addr addr, const void *data, Size size) override; -}; - -/////////////////////////////////////////////////////////////////////////////// - -class MemoryUnit { -public: - - struct PageFault { - PageFault(Addr a, bool nf) - : faultAddr(a) - , notFound(nf) - {} - Addr faultAddr; - bool notFound; - }; - - MemoryUnit(Size pageSize, Size addrBytes, bool disableVm = false); - - void attach(MemDevice &m, Addr start, Addr end); - - void read(Addr addr, void *data, Size size, bool sup); - void write(Addr addr, const void *data, Size size, bool sup); - - void tlbAdd(Addr virt, Addr phys, Word flags); - void tlbRm(Addr va); - void tlbFlush() { - tlb_.clear(); - } -private: - - class ADecoder { - public: - ADecoder() {} - - void read(Addr addr, void *data, Size size); - void write(Addr addr, const void *data, Size size); - - void map(Addr start, Addr end, MemDevice &md); - - private: - - struct mem_accessor_t { - MemDevice* md; - Addr addr; - }; - - struct entry_t { - MemDevice *md; - Addr start; - Addr end; - }; - - bool lookup(Addr a, Size wordSize, mem_accessor_t*); - - std::vector entries_; - }; - - struct TLBEntry { - TLBEntry() {} - TLBEntry(Word pfn, Word flags) - : pfn(pfn) - , flags(flags) - {} - Word pfn; - Word flags; - }; - - TLBEntry tlbLookup(Addr vAddr, Word flagMask); - - std::unordered_map tlb_; - Size pageSize_; - Size addrBytes_; - ADecoder decoder_; - bool disableVm_; -}; - -/////////////////////////////////////////////////////////////////////////////// - -class RAM : public MemDevice { -public: - - RAM(uint32_t num_pages, uint32_t page_size); - - ~RAM(); - - void clear(); - - Size size() const override; - void read(Addr addr, void *data, Size size) override; - void write(Addr addr, const void *data, Size size) override; - - void loadHexImage(std::string path); - -private: - - uint8_t *get(uint32_t address); - - std::vector mem_; - uint32_t page_bits_; - uint32_t size_; -}; - -} // namespace vortex \ No newline at end of file diff --git a/simX/util.cpp b/simX/util.cpp deleted file mode 100644 index 95628917..00000000 --- a/simX/util.cpp +++ /dev/null @@ -1,180 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include "types.h" -#include "util.h" - -using namespace vortex; - -Word vortex::signExt(Word w, Size bit, Word mask) { - if (w >> (bit - 1)) - w |= ~mask; - return w; -} - -void vortex::wordToBytes(Byte *b, Word w, Size wordSize) { - while (wordSize--) { - *(b++) = w & 0xff; - w >>= 8; - } -} - -Word vortex::bytesToWord(const Byte *b, Size wordSize) { - Word w = 0; - b += wordSize-1; - while (wordSize--) { - w <<= 8; - w |= *(b--); - } - return w; -} - -Word vortex::flagsToWord(bool r, bool w, bool x) { - Word word = 0; - if (r) word |= RD_USR; - if (w) word |= WR_USR; - if (x) word |= EX_USR; - return word; -} - -void vortex::wordToFlags(bool &r, bool &w, bool &x, Word f) { - r = f & RD_USR; - w = f & WR_USR; - x = f & EX_USR; -} - -Byte vortex::readByte(const std::vector &b, Size &n) { - if (b.size() <= n) - throw std::out_of_range("out of range"); - return b[n++]; -} - -Word vortex::readWord(const std::vector &b, Size &n, Size wordSize) { - if (b.size() - n < wordSize) - throw std::out_of_range("out of range"); - Word w(0); - n += wordSize; - // std::cout << "wordSize: " << wordSize << "\n"; - for (Size i = 0; i < wordSize; i++) { - w <<= 8; - // cout << "index: " << n - i - 1 << "\n"; - w |= b[n - i - 1]; - } - // cout << "b[0]" << std::hex << w << "\n"; - return w; -} - -void vortex::writeByte(std::vector &p, Size &n, Byte b) { - if (p.size() <= n) p.resize(n+1); - p[n++] = b; -} - -void vortex::writeWord(std::vector &p, Size &n, Size wordSize, Word w) { - if (p.size() < (n+wordSize)) p.resize(n+wordSize); - while (wordSize--) { - p[n++] = w & 0xff; - w >>= 8; - } -} - -// Convert 32-bit integer register file to IEEE-754 floating point number. -float vortex::intregToFloat(uint32_t input) { - // 31th bit - bool sign = input & 0x80000000; - // Exponent: 23th ~ 30th bits -> 8 bits in total - int32_t exp = ((input & 0x7F800000)>>23); - // printf("exp = %u\n", exp); - // 0th ~ 22th bits -> 23 bits fraction - uint32_t frac = input & 0x007FFFFF; - // Frac_value= 1 + sum{i = 1}{23}{b_{23-i}*2^{-i}} - double frac_value; - if (exp == 0) { // subnormal - if (frac == 0) { - // zero - if (sign) - return -0.0; - else - return 0.0; - } - frac_value = 0.0; - } else - frac_value = 1.0; - - for (int i = 0; i < 23; i++) { - int bi = frac & 0x1; - frac_value += static_cast(bi * pow(2.0, i-23)); - frac = (frac >> 1); - } - - return (float)((static_cast(pow(-1.0, sign))) * (static_cast(pow(2.0, exp - 127.0)))* frac_value); -} - -// Convert a floating point number to IEEE-754 32-bit representation, -// so that it could be stored in a 32-bit integer register file -// Reference: https://www.wikihow.com/Convert-a-Number-from-Decimal-to-IEEE-754-Floating-Point-Representation - // https://www.technical-recipes.com/2012/converting-between-binary-and-decimal-representations-of-ieee-754-floating-point-numbers-in-c/ -uint32_t vortex::floatToBin(float in_value) { - union { - float input; // assumes sizeof(float) == sizeof(int) - int output; - } data; - - data.input = in_value; - - std::bitset bits(data.output); - std::string mystring = bits.to_string, std::allocator >(); - // Convert binary to uint32_t - Word result = stoul(mystring, nullptr, 2); - return result; -} - -// https://en.wikipedia.org/wiki/Single-precision_floating-point_format -// check floating-point number in binary format is NaN -uint8_t vortex::fpBinIsNan(uint32_t din) { - bool fsign = din & 0x80000000; - uint32_t expo = (din>>23) & 0x000000FF; - uint32_t fraction = din & 0x007FFFFF; - uint32_t bit_22 = din & 0x00400000; - - if ((expo==0xFF) && (fraction!=0)) { - // if (!fsign && (fraction == 0x00400000)) - if (!fsign && (bit_22)) - return 1; // quiet NaN, return 1 - else - return 2; // signaling NaN, return 2 - } - return 0; -} - -// check floating-point number in binary format is zero -uint8_t vortex::fpBinIsZero(uint32_t din) { - bool fsign = din & 0x80000000; - uint32_t expo = (din>>23) & 0x000000FF; - uint32_t fraction = din & 0x007FFFFF; - - if ((expo==0) && (fraction==0)) { - if (fsign) - return 1; // negative 0 - else - return 2; // positive 0 - } - return 0; // not zero -} - -// check floating-point number in binary format is infinity -uint8_t vortex::fpBinIsInf(uint32_t din) { - bool fsign = din & 0x80000000; - uint32_t expo = (din>>23) & 0x000000FF; - uint32_t fraction = din & 0x007FFFFF; - - if ((expo==0xFF) && (fraction==0)) { - if (fsign) - return 1; // negative infinity - else - return 2; // positive infinity - } - return 0; // not infinity -} \ No newline at end of file diff --git a/simX/util.h b/simX/util.h deleted file mode 100644 index b50db756..00000000 --- a/simX/util.h +++ /dev/null @@ -1,48 +0,0 @@ -#pragma once - -#include -#include "types.h" - -namespace vortex { - -template -void unused(Args&&...) {} - -#define __unused(...) unused(__VA_ARGS__) - -constexpr bool ispow2(uint32_t value) { - return value && !(value & (value - 1)); -} - -constexpr unsigned log2ceil(uint32_t value) { - return 32 - __builtin_clz(value - 1); -} - -Word signExt(Word w, Size bit, Word mask); - -Word bytesToWord(const Byte *b, Size wordSize); -void wordToBytes(Byte *b, Word w, Size wordSize); -Word flagsToWord(bool r, bool w, bool x); -void wordToFlags(bool &r, bool &w, bool &x, Word f); - -Byte readByte(const std::vector &b, Size &n); -Word readWord(const std::vector &b, Size &n, Size wordSize); -void writeByte(std::vector &p, Size &n, Byte b); -void writeWord(std::vector &p, Size &n, Size wordSize, Word w); - -// Convert 32-bit integer register file to IEEE-754 floating point number. -float intregToFloat(uint32_t input); - -// Convert a floating point number to IEEE-754 32-bit representation -uint32_t floatToBin(float in_value); - -// check floating-point number in binary format is NaN -uint8_t fpBinIsNan(uint32_t din); - -// check floating-point number in binary format is zero -uint8_t fpBinIsZero(uint32_t din); - -// check floating-point number in binary format is infinity -uint8_t fpBinIsInf(uint32_t din); - -} \ No newline at end of file diff --git a/tests/opencl/Makefile b/tests/opencl/Makefile index 30c5b154..c882b6a6 100644 --- a/tests/opencl/Makefile +++ b/tests/opencl/Makefile @@ -5,7 +5,7 @@ all: $(MAKE) -C sfilter $(MAKE) -C nearn $(MAKE) -C guassian - $(MAKE) -C printf + $(MAKE) -C oclprintf $(MAKE) -C psort run-simx: @@ -15,8 +15,8 @@ run-simx: $(MAKE) -C sfilter run-simx $(MAKE) -C nearn run-simx $(MAKE) -C guassian run-simx - $(MAKE) -C printf run-simx - #$(MAKE) -C psort run-simx + $(MAKE) -C oclprintf run-simx + $(MAKE) -C psort run-simx run-rtlsim: $(MAKE) -C vecadd run-rtlsim @@ -25,8 +25,8 @@ run-rtlsim: $(MAKE) -C sfilter run-rtlsim $(MAKE) -C nearn run-rtlsim $(MAKE) -C guassian run-rtlsim - $(MAKE) -C printf run-rtlsim - #$(MAKE) -C psort run-rtlsim + $(MAKE) -C oclprintf run-rtlsim + $(MAKE) -C psort run-rtlsim run-vlsim: $(MAKE) -C vecadd run-vlsim @@ -35,8 +35,8 @@ run-vlsim: $(MAKE) -C sfilter run-vlsim $(MAKE) -C nearn run-vlsim $(MAKE) -C guassian run-vlsim - $(MAKE) -C printf run-vlsim - #$(MAKE) -C psort run-vlsim + $(MAKE) -C oclprintf run-vlsim + $(MAKE) -C psort run-vlsim clean: $(MAKE) -C vecadd clean @@ -45,7 +45,7 @@ clean: $(MAKE) -C sfilter clean $(MAKE) -C nearn clean $(MAKE) -C guassian clean - $(MAKE) -C printf clean + $(MAKE) -C oclprintf clean $(MAKE) -C psort clean clean-all: @@ -55,5 +55,5 @@ clean-all: $(MAKE) -C sfilter clean-all $(MAKE) -C nearn clean-all $(MAKE) -C guassian clean-all - $(MAKE) -C printf clean-all + $(MAKE) -C oclprintf clean-all $(MAKE) -C psort clean-all \ No newline at end of file diff --git a/tests/opencl/bfs/Makefile b/tests/opencl/bfs/Makefile index cf71bf13..13b88729 100644 --- a/tests/opencl/bfs/Makefile +++ b/tests/opencl/bfs/Makefile @@ -7,8 +7,8 @@ POCL_RT_PATH ?= /opt/pocl/runtime VORTEX_DRV_PATH ?= $(realpath ../../../driver) VORTEX_RT_PATH ?= $(realpath ../../../runtime) -K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -float-abi=hard -code-model=small" -K_CFLAGS += "-v -O3 -Wstack-usage=1024 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" +K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -mattr=+vortex -float-abi=hard -code-model=small" +K_CFLAGS += "-v -O3 -Wstack-usage=1024 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -Xclang -target-feature -Xclang +vortex -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" K_LDFLAGS += "-Wl,-Bstatic,-T$(VORTEX_RT_PATH)/linker/vx_link.ld -Wl,--gc-sections $(VORTEX_RT_PATH)/libvortexrt.a -lm" CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -pedantic -Wfatal-errors @@ -31,13 +31,13 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ run-fpga: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) run-asesim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) run-vlsim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) run-simx: $(PROJECT) kernel.pocl LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) diff --git a/tests/opencl/convolution/Makefile b/tests/opencl/convolution/Makefile index 0a1e9d0c..e76b5968 100644 --- a/tests/opencl/convolution/Makefile +++ b/tests/opencl/convolution/Makefile @@ -7,8 +7,8 @@ POCL_RT_PATH ?= /opt/pocl/runtime VORTEX_DRV_PATH ?= $(realpath ../../../driver) VORTEX_RT_PATH ?= $(realpath ../../../runtime) -K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -float-abi=hard -code-model=small" -K_CFLAGS += "-v -O3 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" +K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -mattr=+vortex -float-abi=hard -code-model=small" +K_CFLAGS += "-v -O3 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -Xclang -target-feature -Xclang +vortex -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" K_LDFLAGS += "-Wl,-Bstatic,-T$(VORTEX_RT_PATH)/linker/vx_link.ld -Wl,--gc-sections $(VORTEX_RT_PATH)/libvortexrt.a -lm" CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -pedantic -Wfatal-errors @@ -31,13 +31,13 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ run-fpga: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) run-asesim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) run-vlsim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) run-simx: $(PROJECT) kernel.pocl LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) diff --git a/tests/opencl/guassian/Fan1.dump b/tests/opencl/guassian/Fan1.dump index 0b8484fc..a7eb60cc 100644 --- a/tests/opencl/guassian/Fan1.dump +++ b/tests/opencl/guassian/Fan1.dump @@ -1,39 +1,39 @@ -/tmp/pocl_vortex_kernel-8b-5f-88-fa-7a.elf: file format ELF32-riscv +/tmp/pocl_vortex_kernel-b3-29-58-52-fd.elf: file format ELF32-riscv Disassembly of section .init: 80000000 _start: 80000000: 97 05 00 00 auipc a1, 0 -80000004: 93 85 85 31 addi a1, a1, 792 +80000004: 93 85 05 35 addi a1, a1, 848 80000008: 73 25 10 fc csrr a0, 4033 -8000000c: 6b 10 b5 00 -80000010: ef 00 80 30 jal 776 +8000000c: 6b 10 b5 00 vx_wspawn a0, a1 +80000010: ef 00 00 34 jal 832 80000014: 13 05 10 00 addi a0, zero, 1 -80000018: 6b 00 05 00 +80000018: 6b 00 05 00 vx_tmc a0 8000001c: 17 15 00 00 auipc a0, 1 80000020: 13 05 85 41 addi a0, a0, 1048 80000024: 17 16 00 00 auipc a2, 1 80000028: 13 06 06 49 addi a2, a2, 1168 8000002c: 33 06 a6 40 sub a2, a2, a0 80000030: 93 05 00 00 mv a1, zero -80000034: ef 00 90 1e jal 2536 -80000038: 17 15 00 00 auipc a0, 1 -8000003c: 13 05 c5 8e addi a0, a0, -1812 -80000040: ef 00 d0 09 jal 2204 -80000044: ef 00 d0 13 jal 2364 +80000034: ef 00 50 26 jal 2660 +80000038: 17 05 00 00 auipc a0, 0 +8000003c: 13 05 85 3e addi a0, a0, 1000 +80000040: ef 00 10 21 jal 2576 +80000044: ef 00 00 34 jal 832 80000048: ef 00 00 02 jal 32 -8000004c: 6f 00 50 0a j 2212 +8000004c: 6f 00 90 21 j 2584 Disassembly of section .text: 80000050 register_fini: 80000050: 93 07 00 00 mv a5, zero 80000054: 63 88 07 00 beqz a5, 16 -80000058: 37 15 00 80 lui a0, 524289 -8000005c: 13 05 45 92 addi a0, a0, -1756 -80000060: 6f 00 d0 07 j 2172 +80000058: 37 05 00 80 lui a0, 524288 +8000005c: 13 05 05 42 addi a0, a0, 1056 +80000060: 6f 00 10 1f j 2544 80000064: 67 80 00 00 ret 80000068 main: @@ -44,7 +44,7 @@ Disassembly of section .text: 80000078: 37 05 ff 7f lui a0, 524272 8000007c: 13 06 45 03 addi a2, a0, 52 80000080: 37 05 ff 7f lui a0, 524272 -80000084: ef 00 80 41 jal 1048 +80000084: ef 00 40 60 jal 1540 80000088: 13 05 00 00 mv a0, zero 8000008c: 83 20 c1 00 lw ra, 12(sp) 80000090: 13 01 01 01 addi sp, sp, 16 @@ -108,755 +108,792 @@ Disassembly of section .text: 80000170: 67 80 00 00 ret 80000174 _pocl_kernel_Fan1_workgroup: -80000174: 13 08 00 00 mv a6, zero -80000178: 83 26 05 00 lw a3, 0(a0) -8000017c: 03 27 45 00 lw a4, 4(a0) -80000180: 83 27 c5 00 lw a5, 12(a0) -80000184: 03 25 05 01 lw a0, 16(a0) -80000188: 83 a3 06 00 lw t2, 0(a3) -8000018c: 83 2e 07 00 lw t4, 0(a4) -80000190: 83 a6 07 00 lw a3, 0(a5) -80000194: 03 25 05 00 lw a0, 0(a0) -80000198: 83 af 85 01 lw t6, 24(a1) -8000019c: 83 a2 c5 01 lw t0, 28(a1) -800001a0: 83 a8 05 02 lw a7, 32(a1) -800001a4: 03 ae c5 00 lw t3, 12(a1) -800001a8: 33 87 cf 02 mul a4, t6, a2 -800001ac: 93 15 25 00 slli a1, a0, 2 -800001b0: 33 83 be 00 add t1, t4, a1 -800001b4: 33 06 d5 02 mul a2, a0, a3 -800001b8: 13 16 26 00 slli a2, a2, 2 -800001bc: 33 0f c3 00 add t5, t1, a2 -800001c0: 13 46 f5 ff not a2, a0 -800001c4: 33 86 c6 00 add a2, a3, a2 -800001c8: 33 05 ae 00 add a0, t3, a0 -800001cc: 33 05 e5 00 add a0, a0, a4 -800001d0: 13 05 15 00 addi a0, a0, 1 -800001d4: 33 85 a6 02 mul a0, a3, a0 -800001d8: 13 15 25 00 slli a0, a0, 2 -800001dc: 33 03 b5 00 add t1, a0, a1 -800001e0: 93 96 26 00 slli a3, a3, 2 -800001e4: 33 05 ee 00 add a0, t3, a4 -800001e8: 6f 00 c0 00 j 12 -800001ec: 13 08 18 00 addi a6, a6, 1 -800001f0: 63 78 18 05 bgeu a6, a7, 80 -800001f4: 13 0e 00 00 mv t3, zero -800001f8: 6f 00 c0 00 j 12 -800001fc: 13 0e 1e 00 addi t3, t3, 1 -80000200: e3 76 5e fe bgeu t3, t0, -20 -80000204: 13 07 00 00 mv a4, zero -80000208: 93 05 03 00 mv a1, t1 -8000020c: 6f 00 00 01 j 16 -80000210: 13 07 17 00 addi a4, a4, 1 -80000214: b3 85 d5 00 add a1, a1, a3 -80000218: e3 72 f7 ff bgeu a4, t6, -28 -8000021c: b3 07 e5 00 add a5, a0, a4 -80000220: e3 d8 c7 fe bge a5, a2, -16 -80000224: b3 87 be 00 add a5, t4, a1 -80000228: 07 a0 07 00 flw ft0, 0(a5) -8000022c: 87 20 0f 00 flw ft1, 0(t5) -80000230: 53 70 10 18 fdiv.s ft0, ft0, ft1 -80000234: b3 87 b3 00 add a5, t2, a1 -80000238: 27 a0 07 00 fsw ft0, 0(a5) -8000023c: 6f f0 5f fd j -44 -80000240: 67 80 00 00 ret +80000174: 13 01 01 ff addi sp, sp, -16 +80000178: 23 26 81 00 sw s0, 12(sp) +8000017c: 23 24 91 00 sw s1, 8(sp) +80000180: 13 08 00 00 mv a6, zero +80000184: 83 26 05 00 lw a3, 0(a0) +80000188: 03 27 45 00 lw a4, 4(a0) +8000018c: 83 27 c5 00 lw a5, 12(a0) +80000190: 03 25 05 01 lw a0, 16(a0) +80000194: 83 a3 06 00 lw t2, 0(a3) +80000198: 03 2f 07 00 lw t5, 0(a4) +8000019c: 83 a6 07 00 lw a3, 0(a5) +800001a0: 03 25 05 00 lw a0, 0(a0) +800001a4: 83 a7 85 01 lw a5, 24(a1) +800001a8: 83 a2 c5 01 lw t0, 28(a1) +800001ac: 83 a8 05 02 lw a7, 32(a1) +800001b0: 03 ae c5 00 lw t3, 12(a1) +800001b4: 33 87 c7 02 mul a4, a5, a2 +800001b8: 93 15 25 00 slli a1, a0, 2 +800001bc: 33 03 bf 00 add t1, t5, a1 +800001c0: 33 06 d5 02 mul a2, a0, a3 +800001c4: 13 16 26 00 slli a2, a2, 2 +800001c8: b3 0f c3 00 add t6, t1, a2 +800001cc: 13 46 f5 ff not a2, a0 +800001d0: 33 86 c6 00 add a2, a3, a2 +800001d4: 33 05 ae 00 add a0, t3, a0 +800001d8: 33 05 e5 00 add a0, a0, a4 +800001dc: 13 05 15 00 addi a0, a0, 1 +800001e0: 33 85 a6 02 mul a0, a3, a0 +800001e4: 13 15 25 00 slli a0, a0, 2 +800001e8: 33 03 b5 00 add t1, a0, a1 +800001ec: 93 96 26 00 slli a3, a3, 2 +800001f0: 33 05 ee 00 add a0, t3, a4 +800001f4: 6f 00 c0 00 j 12 +800001f8: 13 08 18 00 addi a6, a6, 1 +800001fc: 63 72 18 07 bgeu a6, a7, 100 +80000200: 13 0e 00 00 mv t3, zero +80000204: 6f 00 00 01 j 16 +80000208: 6b 80 0e 00 vx_tmc t4 +8000020c: 13 0e 1e 00 addi t3, t3, 1 +80000210: e3 74 5e fe bgeu t3, t0, -24 +80000214: 13 07 00 00 mv a4, zero +80000218: f3 2e 40 cc csrr t4, tmask +8000021c: 93 05 03 00 mv a1, t1 +80000220: 6f 00 40 01 j 20 +80000224: 6b 30 00 00 vx_join +80000228: 13 07 17 00 addi a4, a4, 1 +8000022c: b3 85 d5 00 add a1, a1, a3 +80000230: e3 7c f7 fc bgeu a4, a5, -40 +80000234: 33 04 e5 00 add s0, a0, a4 +80000238: b3 24 c4 00 slt s1, s0, a2 +8000023c: 6b a0 04 00 vx_split s1 +80000240: e3 52 c4 fe bge s0, a2, -28 +80000244: 33 04 bf 00 add s0, t5, a1 +80000248: 07 20 04 00 flw ft0, 0(s0) +8000024c: 87 a0 0f 00 flw ft1, 0(t6) +80000250: 53 70 10 18 fdiv.s ft0, ft0, ft1 +80000254: 33 84 b3 00 add s0, t2, a1 +80000258: 27 20 04 00 fsw ft0, 0(s0) +8000025c: 6f f0 9f fc j -56 +80000260: 83 24 81 00 lw s1, 8(sp) +80000264: 03 24 c1 00 lw s0, 12(sp) +80000268: 13 01 01 01 addi sp, sp, 16 +8000026c: 67 80 00 00 ret -80000244 _pocl_kernel_Fan1_workgroup_fast: -80000244: 13 08 00 00 mv a6, zero -80000248: 83 26 c5 00 lw a3, 12(a0) -8000024c: 03 27 05 01 lw a4, 16(a0) -80000250: 83 23 05 00 lw t2, 0(a0) -80000254: 83 2e 45 00 lw t4, 4(a0) -80000258: 03 a5 06 00 lw a0, 0(a3) -8000025c: 83 26 07 00 lw a3, 0(a4) -80000260: 83 af 85 01 lw t6, 24(a1) -80000264: 83 a2 c5 01 lw t0, 28(a1) -80000268: 83 a8 05 02 lw a7, 32(a1) -8000026c: 03 ae c5 00 lw t3, 12(a1) -80000270: 33 87 cf 02 mul a4, t6, a2 -80000274: 93 95 26 00 slli a1, a3, 2 -80000278: 33 83 be 00 add t1, t4, a1 -8000027c: 33 86 a6 02 mul a2, a3, a0 -80000280: 13 16 26 00 slli a2, a2, 2 -80000284: 33 0f c3 00 add t5, t1, a2 -80000288: 13 c6 f6 ff not a2, a3 -8000028c: 33 06 c5 00 add a2, a0, a2 -80000290: b3 06 de 00 add a3, t3, a3 -80000294: b3 86 e6 00 add a3, a3, a4 -80000298: 93 86 16 00 addi a3, a3, 1 -8000029c: b3 06 d5 02 mul a3, a0, a3 -800002a0: 93 96 26 00 slli a3, a3, 2 -800002a4: 33 83 b6 00 add t1, a3, a1 -800002a8: 93 16 25 00 slli a3, a0, 2 -800002ac: 33 07 ee 00 add a4, t3, a4 -800002b0: 6f 00 c0 00 j 12 -800002b4: 13 08 18 00 addi a6, a6, 1 -800002b8: 63 78 18 05 bgeu a6, a7, 80 -800002bc: 13 0e 00 00 mv t3, zero -800002c0: 6f 00 c0 00 j 12 -800002c4: 13 0e 1e 00 addi t3, t3, 1 -800002c8: e3 76 5e fe bgeu t3, t0, -20 -800002cc: 13 05 00 00 mv a0, zero -800002d0: 93 05 03 00 mv a1, t1 -800002d4: 6f 00 00 01 j 16 -800002d8: 13 05 15 00 addi a0, a0, 1 -800002dc: b3 85 d5 00 add a1, a1, a3 -800002e0: e3 72 f5 ff bgeu a0, t6, -28 -800002e4: b3 07 a7 00 add a5, a4, a0 -800002e8: e3 d8 c7 fe bge a5, a2, -16 -800002ec: b3 87 be 00 add a5, t4, a1 -800002f0: 07 a0 07 00 flw ft0, 0(a5) -800002f4: 87 20 0f 00 flw ft1, 0(t5) -800002f8: 53 70 10 18 fdiv.s ft0, ft0, ft1 -800002fc: b3 87 b3 00 add a5, t2, a1 -80000300: 27 a0 07 00 fsw ft0, 0(a5) -80000304: 6f f0 5f fd j -44 -80000308: 67 80 00 00 ret +80000270 _pocl_kernel_Fan1_workgroup_fast: +80000270: 13 08 00 00 mv a6, zero +80000274: 83 26 c5 00 lw a3, 12(a0) +80000278: 03 27 05 01 lw a4, 16(a0) +8000027c: 83 23 05 00 lw t2, 0(a0) +80000280: 83 2e 45 00 lw t4, 4(a0) +80000284: 03 a5 06 00 lw a0, 0(a3) +80000288: 83 26 07 00 lw a3, 0(a4) +8000028c: 83 af 85 01 lw t6, 24(a1) +80000290: 83 a2 c5 01 lw t0, 28(a1) +80000294: 83 a8 05 02 lw a7, 32(a1) +80000298: 03 ae c5 00 lw t3, 12(a1) +8000029c: 33 87 cf 02 mul a4, t6, a2 +800002a0: 93 95 26 00 slli a1, a3, 2 +800002a4: 33 83 be 00 add t1, t4, a1 +800002a8: 33 86 a6 02 mul a2, a3, a0 +800002ac: 13 16 26 00 slli a2, a2, 2 +800002b0: 33 0f c3 00 add t5, t1, a2 +800002b4: 13 c6 f6 ff not a2, a3 +800002b8: 33 06 c5 00 add a2, a0, a2 +800002bc: b3 06 de 00 add a3, t3, a3 +800002c0: b3 86 e6 00 add a3, a3, a4 +800002c4: 93 86 16 00 addi a3, a3, 1 +800002c8: b3 06 d5 02 mul a3, a0, a3 +800002cc: 93 96 26 00 slli a3, a3, 2 +800002d0: 33 83 b6 00 add t1, a3, a1 +800002d4: 93 16 25 00 slli a3, a0, 2 +800002d8: 33 07 ee 00 add a4, t3, a4 +800002dc: 6f 00 c0 00 j 12 +800002e0: 13 08 18 00 addi a6, a6, 1 +800002e4: 63 78 18 05 bgeu a6, a7, 80 +800002e8: 13 0e 00 00 mv t3, zero +800002ec: 6f 00 c0 00 j 12 +800002f0: 13 0e 1e 00 addi t3, t3, 1 +800002f4: e3 76 5e fe bgeu t3, t0, -20 +800002f8: 13 05 00 00 mv a0, zero +800002fc: 93 05 03 00 mv a1, t1 +80000300: 6f 00 00 01 j 16 +80000304: 13 05 15 00 addi a0, a0, 1 +80000308: b3 85 d5 00 add a1, a1, a3 +8000030c: e3 72 f5 ff bgeu a0, t6, -28 +80000310: b3 07 a7 00 add a5, a4, a0 +80000314: e3 d8 c7 fe bge a5, a2, -16 +80000318: b3 87 be 00 add a5, t4, a1 +8000031c: 07 a0 07 00 flw ft0, 0(a5) +80000320: 87 20 0f 00 flw ft1, 0(t5) +80000324: 53 70 10 18 fdiv.s ft0, ft0, ft1 +80000328: b3 87 b3 00 add a5, t2, a1 +8000032c: 27 a0 07 00 fsw ft0, 0(a5) +80000330: 6f f0 5f fd j -44 +80000334: 67 80 00 00 ret -8000030c _exit: -8000030c: ef 00 c0 3b jal 956 -80000310: 13 05 00 00 mv a0, zero -80000314: 6b 00 05 00 +80000338 _exit: +80000338: 63 06 05 00 beqz a0, 12 +8000033c: 93 01 05 00 mv gp, a0 +80000340: 73 00 00 00 ecall -80000318 vx_set_sp: -80000318: 73 25 00 fc csrr a0, 4032 -8000031c: 6b 00 05 00 -80000320: 97 11 00 00 auipc gp, 1 -80000324: 93 81 81 4e addi gp, gp, 1256 -80000328: 17 01 00 7f auipc sp, 520192 -8000032c: 13 01 81 cd addi sp, sp, -808 -80000330: 93 05 00 40 addi a1, zero, 1024 -80000334: 73 26 10 cc csrr a2, 3265 -80000338: b3 85 c5 02 mul a1, a1, a2 -8000033c: 33 01 b1 40 sub sp, sp, a1 -80000340: f3 26 30 cc csrr a3, 3267 -80000344: 63 86 06 00 beqz a3, 12 +80000344 label_exit_next: +80000344: ef 00 80 4f jal 1272 80000348: 13 05 00 00 mv a0, zero -8000034c: 6b 00 05 00 +8000034c: 6b 00 05 00 vx_tmc a0 -80000350 RETURN: -80000350: 67 80 00 00 ret +80000350 vx_set_sp: +80000350: 13 05 f0 ff addi a0, zero, -1 +80000354: 6b 00 05 00 vx_tmc a0 +80000358: 97 11 00 00 auipc gp, 1 +8000035c: 93 81 01 4b addi gp, gp, 1200 +80000360: 37 01 00 ff lui sp, 1044480 +80000364: 73 26 10 cc csrr a2, 3265 +80000368: 93 15 a6 00 slli a1, a2, 10 +8000036c: 33 01 b1 40 sub sp, sp, a1 +80000370: f3 26 30 cc csrr a3, 3267 +80000374: 63 86 06 00 beqz a3, 12 +80000378: 13 05 00 00 mv a0, zero +8000037c: 6b 00 05 00 vx_tmc a0 -80000354 spawn_kernel_callback: -80000354: 13 01 01 fe addi sp, sp, -32 -80000358: 23 2e 11 00 sw ra, 28(sp) -8000035c: 23 2c 81 00 sw s0, 24(sp) -80000360: 23 2a 91 00 sw s1, 20(sp) -80000364: 23 28 21 01 sw s2, 16(sp) -80000368: 23 26 31 01 sw s3, 12(sp) -8000036c: 23 24 41 01 sw s4, 8(sp) -80000370: 23 22 51 01 sw s5, 4(sp) -80000374: f3 27 00 fc csrr a5, 4032 -80000378: 6b 80 07 00 -8000037c: f3 26 50 cc csrr a3, 3269 -80000380: 73 29 30 cc csrr s2, 3267 -80000384: 73 27 00 cc csrr a4, 3264 -80000388: 73 26 00 fc csrr a2, 4032 -8000038c: b7 17 00 80 lui a5, 524289 -80000390: 93 96 26 00 slli a3, a3, 2 -80000394: 93 87 47 43 addi a5, a5, 1076 -80000398: b3 87 d7 00 add a5, a5, a3 -8000039c: 03 a4 07 00 lw s0, 0(a5) -800003a0: 83 24 44 01 lw s1, 20(s0) -800003a4: 83 26 04 01 lw a3, 16(s0) -800003a8: b3 2a 99 00 slt s5, s2, s1 -800003ac: 93 87 04 00 mv a5, s1 -800003b0: b3 8a da 00 add s5, s5, a3 -800003b4: b3 84 26 03 mul s1, a3, s2 -800003b8: 63 54 f9 00 bge s2, a5, 8 -800003bc: 93 07 09 00 mv a5, s2 -800003c0: b3 84 f4 00 add s1, s1, a5 -800003c4: 83 25 04 00 lw a1, 0(s0) -800003c8: 83 26 c4 00 lw a3, 12(s0) -800003cc: 83 a9 05 00 lw s3, 0(a1) -800003d0: 03 aa 45 00 lw s4, 4(a1) -800003d4: b3 84 c4 02 mul s1, s1, a2 -800003d8: b3 87 ea 02 mul a5, s5, a4 -800003dc: b3 84 d4 00 add s1, s1, a3 -800003e0: b3 84 f4 00 add s1, s1, a5 -800003e4: b3 8a 9a 00 add s5, s5, s1 -800003e8: 33 8a 49 03 mul s4, s3, s4 -800003ec: 63 c0 54 07 blt s1, s5, 96 -800003f0: 6f 00 00 08 j 128 -800003f4: 03 47 a4 01 lbu a4, 26(s0) -800003f8: 83 46 94 01 lbu a3, 25(s0) -800003fc: 33 d7 e4 40 sra a4, s1, a4 -80000400: b3 07 47 03 mul a5, a4, s4 -80000404: b3 87 f4 40 sub a5, s1, a5 -80000408: 63 80 06 06 beqz a3, 96 -8000040c: 83 46 b4 01 lbu a3, 27(s0) -80000410: b3 d6 d7 40 sra a3, a5, a3 -80000414: b3 88 36 03 mul a7, a3, s3 -80000418: 03 ae 45 01 lw t3, 20(a1) -8000041c: 03 a3 05 01 lw t1, 16(a1) -80000420: 03 a6 c5 00 lw a2, 12(a1) -80000424: 03 28 44 00 lw a6, 4(s0) -80000428: 03 25 84 00 lw a0, 8(s0) -8000042c: 93 84 14 00 addi s1, s1, 1 -80000430: 33 07 c7 01 add a4, a4, t3 -80000434: b3 86 66 00 add a3, a3, t1 -80000438: b3 87 17 41 sub a5, a5, a7 -8000043c: 33 86 c7 00 add a2, a5, a2 -80000440: e7 00 08 00 jalr a6 -80000444: 63 86 9a 02 beq s5, s1, 44 -80000448: 83 25 04 00 lw a1, 0(s0) -8000044c: 83 47 84 01 lbu a5, 24(s0) -80000450: e3 92 07 fa bnez a5, -92 -80000454: 33 c7 44 03 div a4, s1, s4 -80000458: 83 46 94 01 lbu a3, 25(s0) -8000045c: b3 07 47 03 mul a5, a4, s4 -80000460: b3 87 f4 40 sub a5, s1, a5 -80000464: e3 94 06 fa bnez a3, -88 -80000468: b3 c6 37 03 div a3, a5, s3 -8000046c: 6f f0 9f fa j -88 -80000470: 13 39 19 00 seqz s2, s2 -80000474: 6b 00 09 00 -80000478: 83 20 c1 01 lw ra, 28(sp) -8000047c: 03 24 81 01 lw s0, 24(sp) -80000480: 83 24 41 01 lw s1, 20(sp) -80000484: 03 29 01 01 lw s2, 16(sp) -80000488: 83 29 c1 00 lw s3, 12(sp) -8000048c: 03 2a 81 00 lw s4, 8(sp) -80000490: 83 2a 41 00 lw s5, 4(sp) -80000494: 13 01 01 02 addi sp, sp, 32 -80000498: 67 80 00 00 ret +80000380 RETURN: +80000380: 67 80 00 00 ret -8000049c vx_spawn_kernel: -8000049c: 13 01 01 fc addi sp, sp, -64 -800004a0: 23 2e 11 02 sw ra, 60(sp) -800004a4: 23 2c 81 02 sw s0, 56(sp) -800004a8: 23 2a 91 02 sw s1, 52(sp) -800004ac: 23 28 21 03 sw s2, 48(sp) -800004b0: 23 26 31 03 sw s3, 44(sp) -800004b4: f3 28 20 fc csrr a7, 4034 -800004b8: 73 23 10 fc csrr t1, 4033 -800004bc: 73 24 00 fc csrr s0, 4032 -800004c0: f3 27 50 cc csrr a5, 3269 -800004c4: 13 07 f0 01 addi a4, zero, 31 -800004c8: 63 46 f7 0e blt a4, a5, 236 -800004cc: 03 2e 05 00 lw t3, 0(a0) -800004d0: 83 26 45 00 lw a3, 4(a0) -800004d4: 03 28 85 00 lw a6, 8(a0) -800004d8: b3 0e 83 02 mul t4, t1, s0 -800004dc: 13 07 10 00 addi a4, zero, 1 -800004e0: b3 06 de 02 mul a3, t3, a3 -800004e4: 33 88 06 03 mul a6, a3, a6 -800004e8: 63 d4 0e 01 bge t4, a6, 8 -800004ec: 33 47 d8 03 div a4, a6, t4 -800004f0: 63 c0 e8 0e blt a7, a4, 224 -800004f4: 63 d0 e7 0c bge a5, a4, 192 -800004f8: 93 88 f8 ff addi a7, a7, -1 -800004fc: b3 4e e8 02 div t4, a6, a4 -80000500: 93 84 0e 00 mv s1, t4 -80000504: 63 96 f8 00 bne a7, a5, 12 -80000508: 33 67 e8 02 rem a4, a6, a4 -8000050c: b3 04 d7 01 add s1, a4, t4 -80000510: 33 c9 84 02 div s2, s1, s0 -80000514: b3 e4 84 02 rem s1, s1, s0 -80000518: 63 42 69 0c blt s2, t1, 196 -8000051c: 93 02 10 00 addi t0, zero, 1 -80000520: 33 48 69 02 div a6, s2, t1 -80000524: 63 06 08 00 beqz a6, 12 -80000528: 93 02 08 00 mv t0, a6 -8000052c: 33 68 69 02 rem a6, s2, t1 -80000530: d3 f7 06 d0 fcvt.s.w fa5, a3 -80000534: 93 8f f6 ff addi t6, a3, -1 -80000538: 13 0f fe ff addi t5, t3, -1 -8000053c: b7 19 00 80 lui s3, 524289 -80000540: b3 f6 df 00 and a3, t6, a3 -80000544: 93 89 49 43 addi s3, s3, 1076 -80000548: 93 b6 16 00 seqz a3, a3 -8000054c: 23 22 a1 00 sw a0, 4(sp) -80000550: 23 24 b1 00 sw a1, 8(sp) -80000554: 23 26 c1 00 sw a2, 12(sp) -80000558: 23 2a 51 00 sw t0, 20(sp) -8000055c: 23 2c 01 01 sw a6, 24(sp) -80000560: 23 0e d1 00 sb a3, 28(sp) -80000564: 33 87 fe 02 mul a4, t4, a5 -80000568: d3 8e 07 e0 fmv.x.w t4, fa5 -8000056c: d3 77 0e d0 fcvt.s.w fa5, t3 -80000570: 93 97 27 00 slli a5, a5, 2 -80000574: 33 7e cf 01 and t3, t5, t3 -80000578: d3 88 07 e0 fmv.x.w a7, fa5 -8000057c: 93 de 7e 41 srai t4, t4, 23 -80000580: 13 3e 1e 00 seqz t3, t3 -80000584: 93 d8 78 41 srai a7, a7, 23 -80000588: 93 8e 1e f8 addi t4, t4, -127 -8000058c: 93 88 18 f8 addi a7, a7, -127 -80000590: b3 87 f9 00 add a5, s3, a5 -80000594: 23 28 e1 00 sw a4, 16(sp) -80000598: 13 07 41 00 addi a4, sp, 4 -8000059c: a3 0e c1 01 sb t3, 29(sp) -800005a0: 23 0f d1 01 sb t4, 30(sp) -800005a4: a3 0f 11 01 sb a7, 31(sp) -800005a8: 23 a0 e7 00 sw a4, 0(a5) -800005ac: 63 4e 20 03 bgtz s2, 60 -800005b0: 63 9c 04 04 bnez s1, 88 -800005b4: 83 20 c1 03 lw ra, 60(sp) -800005b8: 03 24 81 03 lw s0, 56(sp) -800005bc: 83 24 41 03 lw s1, 52(sp) -800005c0: 03 29 01 03 lw s2, 48(sp) -800005c4: 83 29 c1 02 lw s3, 44(sp) -800005c8: 13 01 01 04 addi sp, sp, 64 -800005cc: 67 80 00 00 ret -800005d0: 13 87 08 00 mv a4, a7 -800005d4: e3 c2 e7 f2 blt a5, a4, -220 -800005d8: 6f f0 df fd j -36 -800005dc: 13 08 00 00 mv a6, zero -800005e0: 93 02 10 00 addi t0, zero, 1 -800005e4: 6f f0 df f4 j -180 -800005e8: 13 07 09 00 mv a4, s2 -800005ec: 63 54 23 01 bge t1, s2, 8 -800005f0: 13 07 03 00 mv a4, t1 -800005f4: b7 07 00 80 lui a5, 524288 -800005f8: 93 87 47 35 addi a5, a5, 852 -800005fc: 6b 10 f7 00 -80000600: ef f0 5f d5 jal -684 -80000604: e3 88 04 fa beqz s1, -80 -80000608: 33 04 89 02 mul s0, s2, s0 -8000060c: 23 28 81 00 sw s0, 16(sp) -80000610: 6b 80 04 00 -80000614: 73 27 50 cc csrr a4, 3269 -80000618: f3 27 20 cc csrr a5, 3266 -8000061c: 13 17 27 00 slli a4, a4, 2 -80000620: b3 89 e9 00 add s3, s3, a4 -80000624: 03 a5 09 00 lw a0, 0(s3) -80000628: 83 25 05 00 lw a1, 0(a0) -8000062c: 83 26 c5 00 lw a3, 12(a0) -80000630: 03 47 85 01 lbu a4, 24(a0) -80000634: 03 a8 05 00 lw a6, 0(a1) -80000638: 03 a6 45 00 lw a2, 4(a1) -8000063c: b3 87 d7 00 add a5, a5, a3 -80000640: 33 06 c8 02 mul a2, a6, a2 -80000644: 63 0e 07 06 beqz a4, 124 -80000648: 03 47 a5 01 lbu a4, 26(a0) -8000064c: 33 d7 e7 40 sra a4, a5, a4 -80000650: 83 46 95 01 lbu a3, 25(a0) -80000654: 33 06 e6 02 mul a2, a2, a4 -80000658: b3 87 c7 40 sub a5, a5, a2 -8000065c: 63 8e 06 04 beqz a3, 92 -80000660: 83 48 b5 01 lbu a7, 27(a0) -80000664: b3 d8 17 41 sra a7, a5, a7 -80000668: 33 08 18 03 mul a6, a6, a7 -8000066c: 03 ae 45 01 lw t3, 20(a1) -80000670: 83 a6 05 01 lw a3, 16(a1) -80000674: 03 a6 c5 00 lw a2, 12(a1) -80000678: 03 23 45 00 lw t1, 4(a0) -8000067c: 03 25 85 00 lw a0, 8(a0) -80000680: 33 07 c7 01 add a4, a4, t3 -80000684: b3 86 d8 00 add a3, a7, a3 -80000688: b3 87 07 41 sub a5, a5, a6 -8000068c: 33 86 c7 00 add a2, a5, a2 -80000690: e7 00 03 00 jalr t1 -80000694: 93 07 10 00 addi a5, zero, 1 -80000698: 6b 80 07 00 -8000069c: 83 20 c1 03 lw ra, 60(sp) -800006a0: 03 24 81 03 lw s0, 56(sp) -800006a4: 83 24 41 03 lw s1, 52(sp) -800006a8: 03 29 01 03 lw s2, 48(sp) -800006ac: 83 29 c1 02 lw s3, 44(sp) -800006b0: 13 01 01 04 addi sp, sp, 64 -800006b4: 67 80 00 00 ret -800006b8: b3 c8 07 03 div a7, a5, a6 -800006bc: 6f f0 df fa j -84 -800006c0: 33 c7 c7 02 div a4, a5, a2 -800006c4: 6f f0 df f8 j -116 +80000384 __libc_init_array: +80000384: 13 01 01 ff addi sp, sp, -16 +80000388: 23 24 81 00 sw s0, 8(sp) +8000038c: 23 20 21 01 sw s2, 0(sp) +80000390: 37 14 00 80 lui s0, 524289 +80000394: 37 19 00 80 lui s2, 524289 +80000398: 93 07 04 00 mv a5, s0 +8000039c: 13 09 09 00 mv s2, s2 +800003a0: 33 09 f9 40 sub s2, s2, a5 +800003a4: 23 26 11 00 sw ra, 12(sp) +800003a8: 23 22 91 00 sw s1, 4(sp) +800003ac: 13 59 29 40 srai s2, s2, 2 +800003b0: 63 00 09 02 beqz s2, 32 +800003b4: 13 04 04 00 mv s0, s0 +800003b8: 93 04 00 00 mv s1, zero +800003bc: 83 27 04 00 lw a5, 0(s0) +800003c0: 93 84 14 00 addi s1, s1, 1 +800003c4: 13 04 44 00 addi s0, s0, 4 +800003c8: e7 80 07 00 jalr a5 +800003cc: e3 18 99 fe bne s2, s1, -16 +800003d0: 37 14 00 80 lui s0, 524289 +800003d4: 37 19 00 80 lui s2, 524289 +800003d8: 93 07 04 00 mv a5, s0 +800003dc: 13 09 49 00 addi s2, s2, 4 +800003e0: 33 09 f9 40 sub s2, s2, a5 +800003e4: 13 59 29 40 srai s2, s2, 2 +800003e8: 63 00 09 02 beqz s2, 32 +800003ec: 13 04 04 00 mv s0, s0 +800003f0: 93 04 00 00 mv s1, zero +800003f4: 83 27 04 00 lw a5, 0(s0) +800003f8: 93 84 14 00 addi s1, s1, 1 +800003fc: 13 04 44 00 addi s0, s0, 4 +80000400: e7 80 07 00 jalr a5 +80000404: e3 18 99 fe bne s2, s1, -16 +80000408: 83 20 c1 00 lw ra, 12(sp) +8000040c: 03 24 81 00 lw s0, 8(sp) +80000410: 83 24 41 00 lw s1, 4(sp) +80000414: 03 29 01 00 lw s2, 0(sp) +80000418: 13 01 01 01 addi sp, sp, 16 +8000041c: 67 80 00 00 ret -800006c8 vx_perf_dump: -800006c8: f3 27 50 cc csrr a5, 3269 -800006cc: 37 07 ff 00 lui a4, 4080 -800006d0: b3 87 e7 00 add a5, a5, a4 -800006d4: 93 97 87 00 slli a5, a5, 8 -800006d8: 73 27 00 b0 csrr a4, mcycle -800006dc: 23 a0 e7 00 sw a4, 0(a5) -800006e0: 73 27 10 b0 csrr a4, 2817 -800006e4: 23 a2 e7 00 sw a4, 4(a5) -800006e8: 73 27 20 b0 csrr a4, minstret -800006ec: 23 a4 e7 00 sw a4, 8(a5) -800006f0: 73 27 30 b0 csrr a4, mhpmcounter3 -800006f4: 23 a6 e7 00 sw a4, 12(a5) -800006f8: 73 27 40 b0 csrr a4, mhpmcounter4 -800006fc: 23 a8 e7 00 sw a4, 16(a5) -80000700: 73 27 50 b0 csrr a4, mhpmcounter5 -80000704: 23 aa e7 00 sw a4, 20(a5) -80000708: 73 27 60 b0 csrr a4, mhpmcounter6 -8000070c: 23 ac e7 00 sw a4, 24(a5) -80000710: 73 27 70 b0 csrr a4, mhpmcounter7 -80000714: 23 ae e7 00 sw a4, 28(a5) -80000718: 73 27 80 b0 csrr a4, mhpmcounter8 -8000071c: 23 a0 e7 02 sw a4, 32(a5) -80000720: 73 27 90 b0 csrr a4, mhpmcounter9 -80000724: 23 a2 e7 02 sw a4, 36(a5) -80000728: 73 27 a0 b0 csrr a4, mhpmcounter10 -8000072c: 23 a4 e7 02 sw a4, 40(a5) -80000730: 73 27 b0 b0 csrr a4, mhpmcounter11 -80000734: 23 a6 e7 02 sw a4, 44(a5) -80000738: 73 27 c0 b0 csrr a4, mhpmcounter12 -8000073c: 23 a8 e7 02 sw a4, 48(a5) -80000740: 73 27 d0 b0 csrr a4, mhpmcounter13 -80000744: 23 aa e7 02 sw a4, 52(a5) -80000748: 73 27 e0 b0 csrr a4, mhpmcounter14 -8000074c: 23 ac e7 02 sw a4, 56(a5) -80000750: 73 27 f0 b0 csrr a4, mhpmcounter15 -80000754: 23 ae e7 02 sw a4, 60(a5) -80000758: 73 27 00 b1 csrr a4, mhpmcounter16 -8000075c: 23 a0 e7 04 sw a4, 64(a5) -80000760: 73 27 10 b1 csrr a4, mhpmcounter17 -80000764: 23 a2 e7 04 sw a4, 68(a5) -80000768: 73 27 20 b1 csrr a4, mhpmcounter18 -8000076c: 23 a4 e7 04 sw a4, 72(a5) -80000770: 73 27 30 b1 csrr a4, mhpmcounter19 -80000774: 23 a6 e7 04 sw a4, 76(a5) -80000778: 73 27 40 b1 csrr a4, mhpmcounter20 -8000077c: 23 a8 e7 04 sw a4, 80(a5) -80000780: 73 27 50 b1 csrr a4, mhpmcounter21 -80000784: 23 aa e7 04 sw a4, 84(a5) -80000788: 73 27 60 b1 csrr a4, mhpmcounter22 -8000078c: 23 ac e7 04 sw a4, 88(a5) -80000790: 73 27 70 b1 csrr a4, mhpmcounter23 -80000794: 23 ae e7 04 sw a4, 92(a5) -80000798: 73 27 80 b1 csrr a4, mhpmcounter24 -8000079c: 23 a0 e7 06 sw a4, 96(a5) -800007a0: 73 27 90 b1 csrr a4, mhpmcounter25 -800007a4: 23 a2 e7 06 sw a4, 100(a5) -800007a8: 73 27 a0 b1 csrr a4, mhpmcounter26 -800007ac: 23 a4 e7 06 sw a4, 104(a5) -800007b0: 73 27 b0 b1 csrr a4, mhpmcounter27 -800007b4: 23 a6 e7 06 sw a4, 108(a5) -800007b8: 73 27 c0 b1 csrr a4, mhpmcounter28 -800007bc: 23 a8 e7 06 sw a4, 112(a5) -800007c0: 73 27 d0 b1 csrr a4, mhpmcounter29 -800007c4: 23 aa e7 06 sw a4, 116(a5) -800007c8: 73 27 e0 b1 csrr a4, mhpmcounter30 -800007cc: 23 ac e7 06 sw a4, 120(a5) -800007d0: 73 27 f0 b1 csrr a4, mhpmcounter31 -800007d4: 23 ae e7 06 sw a4, 124(a5) -800007d8: 73 27 00 b8 csrr a4, mcycleh -800007dc: 23 a0 e7 08 sw a4, 128(a5) -800007e0: 73 27 10 b8 csrr a4, 2945 -800007e4: 23 a2 e7 08 sw a4, 132(a5) -800007e8: 73 27 20 b8 csrr a4, minstreth -800007ec: 23 a4 e7 08 sw a4, 136(a5) -800007f0: 73 27 30 b8 csrr a4, mhpmcounter3h -800007f4: 23 a6 e7 08 sw a4, 140(a5) -800007f8: 73 27 40 b8 csrr a4, mhpmcounter4h -800007fc: 23 a8 e7 08 sw a4, 144(a5) -80000800: 73 27 50 b8 csrr a4, mhpmcounter5h -80000804: 23 aa e7 08 sw a4, 148(a5) -80000808: 73 27 60 b8 csrr a4, mhpmcounter6h -8000080c: 23 ac e7 08 sw a4, 152(a5) -80000810: 73 27 70 b8 csrr a4, mhpmcounter7h -80000814: 23 ae e7 08 sw a4, 156(a5) -80000818: 73 27 80 b8 csrr a4, mhpmcounter8h -8000081c: 23 a0 e7 0a sw a4, 160(a5) -80000820: 73 27 90 b8 csrr a4, mhpmcounter9h -80000824: 23 a2 e7 0a sw a4, 164(a5) -80000828: 73 27 a0 b8 csrr a4, mhpmcounter10h -8000082c: 23 a4 e7 0a sw a4, 168(a5) -80000830: 73 27 b0 b8 csrr a4, mhpmcounter11h -80000834: 23 a6 e7 0a sw a4, 172(a5) -80000838: 73 27 c0 b8 csrr a4, mhpmcounter12h -8000083c: 23 a8 e7 0a sw a4, 176(a5) -80000840: 73 27 d0 b8 csrr a4, mhpmcounter13h -80000844: 23 aa e7 0a sw a4, 180(a5) -80000848: 73 27 e0 b8 csrr a4, mhpmcounter14h -8000084c: 23 ac e7 0a sw a4, 184(a5) -80000850: 73 27 f0 b8 csrr a4, mhpmcounter15h -80000854: 23 ae e7 0a sw a4, 188(a5) -80000858: 73 27 00 b9 csrr a4, mhpmcounter16h -8000085c: 23 a0 e7 0c sw a4, 192(a5) -80000860: 73 27 10 b9 csrr a4, mhpmcounter17h -80000864: 23 a2 e7 0c sw a4, 196(a5) -80000868: 73 27 20 b9 csrr a4, mhpmcounter18h -8000086c: 23 a4 e7 0c sw a4, 200(a5) -80000870: 73 27 30 b9 csrr a4, mhpmcounter19h -80000874: 23 a6 e7 0c sw a4, 204(a5) -80000878: 73 27 40 b9 csrr a4, mhpmcounter20h -8000087c: 23 a8 e7 0c sw a4, 208(a5) -80000880: 73 27 50 b9 csrr a4, mhpmcounter21h -80000884: 23 aa e7 0c sw a4, 212(a5) -80000888: 73 27 60 b9 csrr a4, mhpmcounter22h -8000088c: 23 ac e7 0c sw a4, 216(a5) -80000890: 73 27 70 b9 csrr a4, mhpmcounter23h -80000894: 23 ae e7 0c sw a4, 220(a5) -80000898: 73 27 80 b9 csrr a4, mhpmcounter24h -8000089c: 23 a0 e7 0e sw a4, 224(a5) -800008a0: 73 27 90 b9 csrr a4, mhpmcounter25h -800008a4: 23 a2 e7 0e sw a4, 228(a5) -800008a8: 73 27 a0 b9 csrr a4, mhpmcounter26h -800008ac: 23 a4 e7 0e sw a4, 232(a5) -800008b0: 73 27 b0 b9 csrr a4, mhpmcounter27h -800008b4: 23 a6 e7 0e sw a4, 236(a5) -800008b8: 73 27 c0 b9 csrr a4, mhpmcounter28h -800008bc: 23 a8 e7 0e sw a4, 240(a5) -800008c0: 73 27 d0 b9 csrr a4, mhpmcounter29h -800008c4: 23 aa e7 0e sw a4, 244(a5) -800008c8: 73 27 e0 b9 csrr a4, mhpmcounter30h -800008cc: 23 ac e7 0e sw a4, 248(a5) -800008d0: 73 27 f0 b9 csrr a4, mhpmcounter31h -800008d4: 23 ae e7 0e sw a4, 252(a5) -800008d8: 67 80 00 00 ret +80000420 __libc_fini_array: +80000420: 13 01 01 ff addi sp, sp, -16 +80000424: 23 24 81 00 sw s0, 8(sp) +80000428: b7 17 00 80 lui a5, 524289 +8000042c: 37 14 00 80 lui s0, 524289 +80000430: 13 04 44 00 addi s0, s0, 4 +80000434: 93 87 47 00 addi a5, a5, 4 +80000438: b3 87 87 40 sub a5, a5, s0 +8000043c: 23 22 91 00 sw s1, 4(sp) +80000440: 23 26 11 00 sw ra, 12(sp) +80000444: 93 d4 27 40 srai s1, a5, 2 +80000448: 63 80 04 02 beqz s1, 32 +8000044c: 93 87 c7 ff addi a5, a5, -4 +80000450: 33 84 87 00 add s0, a5, s0 +80000454: 83 27 04 00 lw a5, 0(s0) +80000458: 93 84 f4 ff addi s1, s1, -1 +8000045c: 13 04 c4 ff addi s0, s0, -4 +80000460: e7 80 07 00 jalr a5 +80000464: e3 98 04 fe bnez s1, -16 +80000468: 83 20 c1 00 lw ra, 12(sp) +8000046c: 03 24 81 00 lw s0, 8(sp) +80000470: 83 24 41 00 lw s1, 4(sp) +80000474: 13 01 01 01 addi sp, sp, 16 +80000478: 67 80 00 00 ret -800008dc atexit: -800008dc: 93 05 05 00 mv a1, a0 -800008e0: 93 06 00 00 mv a3, zero -800008e4: 13 06 00 00 mv a2, zero -800008e8: 13 05 00 00 mv a0, zero -800008ec: 6f 00 c0 20 j 524 +8000047c spawn_kernel_all_stub: +8000047c: 13 01 01 fe addi sp, sp, -32 +80000480: 23 2e 11 00 sw ra, 28(sp) +80000484: 23 2c 81 00 sw s0, 24(sp) +80000488: 23 2a 91 00 sw s1, 20(sp) +8000048c: 23 28 21 01 sw s2, 16(sp) +80000490: 23 26 31 01 sw s3, 12(sp) +80000494: 23 24 41 01 sw s4, 8(sp) +80000498: 73 26 50 cc csrr a2, 3269 +8000049c: 73 27 30 cc csrr a4, 3267 +800004a0: f3 26 00 cc csrr a3, 3264 +800004a4: 73 25 00 fc csrr a0, 4032 +800004a8: b7 17 00 80 lui a5, 524289 +800004ac: 13 16 26 00 slli a2, a2, 2 +800004b0: 93 87 47 43 addi a5, a5, 1076 +800004b4: b3 87 c7 00 add a5, a5, a2 +800004b8: 03 a4 07 00 lw s0, 0(a5) +800004bc: 83 24 44 01 lw s1, 20(s0) +800004c0: 03 26 04 01 lw a2, 16(s0) +800004c4: 33 2a 97 00 slt s4, a4, s1 +800004c8: 93 87 04 00 mv a5, s1 +800004cc: 33 0a ca 00 add s4, s4, a2 +800004d0: b3 04 e6 02 mul s1, a2, a4 +800004d4: 63 54 f7 00 bge a4, a5, 8 +800004d8: 93 07 07 00 mv a5, a4 +800004dc: b3 84 f4 00 add s1, s1, a5 +800004e0: 83 25 04 00 lw a1, 0(s0) +800004e4: 03 27 c4 00 lw a4, 12(s0) +800004e8: 03 a9 05 00 lw s2, 0(a1) +800004ec: 83 a9 45 00 lw s3, 4(a1) +800004f0: b3 84 a4 02 mul s1, s1, a0 +800004f4: b3 07 da 02 mul a5, s4, a3 +800004f8: b3 84 e4 00 add s1, s1, a4 +800004fc: b3 84 f4 00 add s1, s1, a5 +80000500: 33 0a 9a 00 add s4, s4, s1 +80000504: b3 09 39 03 mul s3, s2, s3 +80000508: 63 c0 44 07 blt s1, s4, 96 +8000050c: 6f 00 00 08 j 128 +80000510: 03 47 e4 01 lbu a4, 30(s0) +80000514: 83 46 d4 01 lbu a3, 29(s0) +80000518: 33 d7 e4 40 sra a4, s1, a4 +8000051c: b3 07 37 03 mul a5, a4, s3 +80000520: b3 87 f4 40 sub a5, s1, a5 +80000524: 63 80 06 06 beqz a3, 96 +80000528: 83 46 f4 01 lbu a3, 31(s0) +8000052c: b3 d6 d7 40 sra a3, a5, a3 +80000530: b3 88 26 03 mul a7, a3, s2 +80000534: 03 ae 45 01 lw t3, 20(a1) +80000538: 03 a3 05 01 lw t1, 16(a1) +8000053c: 03 a6 c5 00 lw a2, 12(a1) +80000540: 03 28 44 00 lw a6, 4(s0) +80000544: 03 25 84 00 lw a0, 8(s0) +80000548: 93 84 14 00 addi s1, s1, 1 +8000054c: 33 07 c7 01 add a4, a4, t3 +80000550: b3 86 66 00 add a3, a3, t1 +80000554: b3 87 17 41 sub a5, a5, a7 +80000558: 33 86 c7 00 add a2, a5, a2 +8000055c: e7 00 08 00 jalr a6 +80000560: 63 06 9a 02 beq s4, s1, 44 +80000564: 83 25 04 00 lw a1, 0(s0) +80000568: 83 47 c4 01 lbu a5, 28(s0) +8000056c: e3 92 07 fa bnez a5, -92 +80000570: 33 c7 34 03 div a4, s1, s3 +80000574: 83 46 d4 01 lbu a3, 29(s0) +80000578: b3 07 37 03 mul a5, a4, s3 +8000057c: b3 87 f4 40 sub a5, s1, a5 +80000580: e3 94 06 fa bnez a3, -88 +80000584: b3 c6 27 03 div a3, a5, s2 +80000588: 6f f0 9f fa j -88 +8000058c: 03 27 84 01 lw a4, 24(s0) +80000590: 93 07 00 00 mv a5, zero +80000594: 6b c0 e7 00 vx_bar a5, a4 +80000598: 83 20 c1 01 lw ra, 28(sp) +8000059c: 03 24 81 01 lw s0, 24(sp) +800005a0: 83 24 41 01 lw s1, 20(sp) +800005a4: 03 29 01 01 lw s2, 16(sp) +800005a8: 83 29 c1 00 lw s3, 12(sp) +800005ac: 03 2a 81 00 lw s4, 8(sp) +800005b0: 13 01 01 02 addi sp, sp, 32 +800005b4: 67 80 00 00 ret -800008f0 exit: -800008f0: 13 01 01 ff addi sp, sp, -16 -800008f4: 93 05 00 00 mv a1, zero -800008f8: 23 24 81 00 sw s0, 8(sp) -800008fc: 23 26 11 00 sw ra, 12(sp) -80000900: 13 04 05 00 mv s0, a0 -80000904: ef 00 00 29 jal 656 -80000908: b7 17 00 80 lui a5, 524289 -8000090c: 03 a5 07 43 lw a0, 1072(a5) -80000910: 83 27 c5 03 lw a5, 60(a0) -80000914: 63 84 07 00 beqz a5, 8 -80000918: e7 80 07 00 jalr a5 -8000091c: 13 05 04 00 mv a0, s0 -80000920: ef f0 df 9e jal -1556 +800005b8 spawn_kernel_rem_stub: +800005b8: f3 26 50 cc csrr a3, 3269 +800005bc: f3 27 20 cc csrr a5, 3266 +800005c0: 37 17 00 80 lui a4, 524289 +800005c4: 93 96 26 00 slli a3, a3, 2 +800005c8: 13 07 47 43 addi a4, a4, 1076 +800005cc: 33 07 d7 00 add a4, a4, a3 +800005d0: 03 25 07 00 lw a0, 0(a4) +800005d4: 83 25 05 00 lw a1, 0(a0) +800005d8: 83 26 c5 00 lw a3, 12(a0) +800005dc: 03 47 c5 01 lbu a4, 28(a0) +800005e0: 83 a8 05 00 lw a7, 0(a1) +800005e4: 03 a6 45 00 lw a2, 4(a1) +800005e8: b3 87 d7 00 add a5, a5, a3 +800005ec: 33 86 c8 02 mul a2, a7, a2 +800005f0: 63 08 07 04 beqz a4, 80 +800005f4: 03 47 e5 01 lbu a4, 30(a0) +800005f8: 83 46 d5 01 lbu a3, 29(a0) +800005fc: 33 d7 e7 40 sra a4, a5, a4 +80000600: 33 06 c7 02 mul a2, a4, a2 +80000604: b3 87 c7 40 sub a5, a5, a2 +80000608: 63 86 06 04 beqz a3, 76 +8000060c: 83 46 f5 01 lbu a3, 31(a0) +80000610: 33 d8 d7 40 sra a6, a5, a3 +80000614: 83 a6 05 01 lw a3, 16(a1) +80000618: 03 ae 45 01 lw t3, 20(a1) +8000061c: 03 a6 c5 00 lw a2, 12(a1) +80000620: b3 06 d8 00 add a3, a6, a3 +80000624: 33 08 18 03 mul a6, a6, a7 +80000628: 03 23 45 00 lw t1, 4(a0) +8000062c: 03 25 85 00 lw a0, 8(a0) +80000630: 33 07 c7 01 add a4, a4, t3 +80000634: b3 87 07 41 sub a5, a5, a6 +80000638: 33 86 c7 00 add a2, a5, a2 +8000063c: 67 00 03 00 jr t1 +80000640: 33 c7 c7 02 div a4, a5, a2 +80000644: 83 46 d5 01 lbu a3, 29(a0) +80000648: 33 06 c7 02 mul a2, a4, a2 +8000064c: b3 87 c7 40 sub a5, a5, a2 +80000650: e3 9e 06 fa bnez a3, -68 +80000654: 33 c8 17 03 div a6, a5, a7 +80000658: 6f f0 df fb j -68 -80000924 __libc_fini_array: -80000924: 13 01 01 ff addi sp, sp, -16 -80000928: 23 24 81 00 sw s0, 8(sp) -8000092c: b7 17 00 80 lui a5, 524289 -80000930: 37 14 00 80 lui s0, 524289 -80000934: 13 04 44 00 addi s0, s0, 4 -80000938: 93 87 47 00 addi a5, a5, 4 -8000093c: b3 87 87 40 sub a5, a5, s0 -80000940: 23 22 91 00 sw s1, 4(sp) -80000944: 23 26 11 00 sw ra, 12(sp) -80000948: 93 d4 27 40 srai s1, a5, 2 -8000094c: 63 80 04 02 beqz s1, 32 -80000950: 93 87 c7 ff addi a5, a5, -4 -80000954: 33 84 87 00 add s0, a5, s0 -80000958: 83 27 04 00 lw a5, 0(s0) -8000095c: 93 84 f4 ff addi s1, s1, -1 -80000960: 13 04 c4 ff addi s0, s0, -4 -80000964: e7 80 07 00 jalr a5 -80000968: e3 98 04 fe bnez s1, -16 -8000096c: 83 20 c1 00 lw ra, 12(sp) -80000970: 03 24 81 00 lw s0, 8(sp) -80000974: 83 24 41 00 lw s1, 4(sp) -80000978: 13 01 01 01 addi sp, sp, 16 -8000097c: 67 80 00 00 ret +8000065c spawn_kernel_all_cb: +8000065c: 13 01 01 ff addi sp, sp, -16 +80000660: 23 26 11 00 sw ra, 12(sp) +80000664: 93 07 f0 ff addi a5, zero, -1 +80000668: 6b 80 07 00 vx_tmc a5 +8000066c: ef f0 1f e1 jal -496 +80000670: f3 27 30 cc csrr a5, 3267 +80000674: 93 b7 17 00 seqz a5, a5 +80000678: 6b 80 07 00 vx_tmc a5 +8000067c: 83 20 c1 00 lw ra, 12(sp) +80000680: 13 01 01 01 addi sp, sp, 16 +80000684: 67 80 00 00 ret -80000980 __libc_init_array: -80000980: 13 01 01 ff addi sp, sp, -16 -80000984: 23 24 81 00 sw s0, 8(sp) -80000988: 23 20 21 01 sw s2, 0(sp) -8000098c: 37 14 00 80 lui s0, 524289 -80000990: 37 19 00 80 lui s2, 524289 -80000994: 93 07 04 00 mv a5, s0 -80000998: 13 09 09 00 mv s2, s2 -8000099c: 33 09 f9 40 sub s2, s2, a5 -800009a0: 23 26 11 00 sw ra, 12(sp) -800009a4: 23 22 91 00 sw s1, 4(sp) -800009a8: 13 59 29 40 srai s2, s2, 2 -800009ac: 63 00 09 02 beqz s2, 32 -800009b0: 13 04 04 00 mv s0, s0 -800009b4: 93 04 00 00 mv s1, zero -800009b8: 83 27 04 00 lw a5, 0(s0) -800009bc: 93 84 14 00 addi s1, s1, 1 -800009c0: 13 04 44 00 addi s0, s0, 4 -800009c4: e7 80 07 00 jalr a5 -800009c8: e3 18 99 fe bne s2, s1, -16 -800009cc: 37 14 00 80 lui s0, 524289 -800009d0: 37 19 00 80 lui s2, 524289 -800009d4: 93 07 04 00 mv a5, s0 -800009d8: 13 09 49 00 addi s2, s2, 4 -800009dc: 33 09 f9 40 sub s2, s2, a5 -800009e0: 13 59 29 40 srai s2, s2, 2 -800009e4: 63 00 09 02 beqz s2, 32 -800009e8: 13 04 04 00 mv s0, s0 -800009ec: 93 04 00 00 mv s1, zero -800009f0: 83 27 04 00 lw a5, 0(s0) -800009f4: 93 84 14 00 addi s1, s1, 1 -800009f8: 13 04 44 00 addi s0, s0, 4 -800009fc: e7 80 07 00 jalr a5 -80000a00: e3 18 99 fe bne s2, s1, -16 -80000a04: 83 20 c1 00 lw ra, 12(sp) -80000a08: 03 24 81 00 lw s0, 8(sp) -80000a0c: 83 24 41 00 lw s1, 4(sp) -80000a10: 03 29 01 00 lw s2, 0(sp) -80000a14: 13 01 01 01 addi sp, sp, 16 -80000a18: 67 80 00 00 ret +80000688 vx_spawn_kernel: +80000688: 13 01 01 fd addi sp, sp, -48 +8000068c: 23 26 11 02 sw ra, 44(sp) +80000690: 23 24 81 02 sw s0, 40(sp) +80000694: 23 22 91 02 sw s1, 36(sp) +80000698: 23 20 21 03 sw s2, 32(sp) +8000069c: f3 28 20 fc csrr a7, 4034 +800006a0: 73 23 10 fc csrr t1, 4033 +800006a4: f3 24 00 fc csrr s1, 4032 +800006a8: f3 27 50 cc csrr a5, 3269 +800006ac: 13 07 f0 01 addi a4, zero, 31 +800006b0: 63 46 f7 0e blt a4, a5, 236 +800006b4: 03 2e 05 00 lw t3, 0(a0) +800006b8: 83 26 45 00 lw a3, 4(a0) +800006bc: 03 28 85 00 lw a6, 8(a0) +800006c0: b3 0e 93 02 mul t4, t1, s1 +800006c4: 13 07 10 00 addi a4, zero, 1 +800006c8: b3 06 de 02 mul a3, t3, a3 +800006cc: 33 88 06 03 mul a6, a3, a6 +800006d0: 63 d4 0e 01 bge t4, a6, 8 +800006d4: 33 47 d8 03 div a4, a6, t4 +800006d8: 63 ce e8 0c blt a7, a4, 220 +800006dc: 63 d0 e7 0c bge a5, a4, 192 +800006e0: 93 88 f8 ff addi a7, a7, -1 +800006e4: b3 4e e8 02 div t4, a6, a4 +800006e8: 13 84 0e 00 mv s0, t4 +800006ec: 63 96 f8 00 bne a7, a5, 12 +800006f0: 33 67 e8 02 rem a4, a6, a4 +800006f4: 33 04 d7 01 add s0, a4, t4 +800006f8: 33 49 94 02 div s2, s0, s1 +800006fc: 33 64 94 02 rem s0, s0, s1 +80000700: 63 40 69 0c blt s2, t1, 192 +80000704: 93 0f 10 00 addi t6, zero, 1 +80000708: 33 4f 69 02 div t5, s2, t1 +8000070c: 63 06 0f 00 beqz t5, 12 +80000710: 93 0f 0f 00 mv t6, t5 +80000714: 33 6f 69 02 rem t5, s2, t1 +80000718: d3 f7 06 d0 fcvt.s.w fa5, a3 +8000071c: 13 07 fe ff addi a4, t3, -1 +80000720: 93 82 f6 ff addi t0, a3, -1 +80000724: d3 88 07 e0 fmv.x.w a7, fa5 +80000728: d3 77 0e d0 fcvt.s.w fa5, t3 +8000072c: 33 7e c7 01 and t3, a4, t3 +80000730: 37 17 00 80 lui a4, 524289 +80000734: 53 88 07 e0 fmv.x.w a6, fa5 +80000738: b3 f6 d2 00 and a3, t0, a3 +8000073c: 93 d8 78 41 srai a7, a7, 23 +80000740: 13 58 78 41 srai a6, a6, 23 +80000744: 13 07 47 43 addi a4, a4, 1076 +80000748: 93 b6 16 00 seqz a3, a3 +8000074c: 13 3e 1e 00 seqz t3, t3 +80000750: 93 88 18 f8 addi a7, a7, -127 +80000754: 13 08 18 f8 addi a6, a6, -127 +80000758: 23 20 a1 00 sw a0, 0(sp) +8000075c: 23 22 b1 00 sw a1, 4(sp) +80000760: 23 24 c1 00 sw a2, 8(sp) +80000764: 23 28 f1 01 sw t6, 16(sp) +80000768: 23 2a e1 01 sw t5, 20(sp) +8000076c: 23 2c 01 00 sw zero, 24(sp) +80000770: 23 0e d1 00 sb a3, 28(sp) +80000774: a3 0e c1 01 sb t3, 29(sp) +80000778: 23 0f 11 01 sb a7, 30(sp) +8000077c: a3 0f 01 01 sb a6, 31(sp) +80000780: b3 8e fe 02 mul t4, t4, a5 +80000784: 93 97 27 00 slli a5, a5, 2 +80000788: b3 07 f7 00 add a5, a4, a5 +8000078c: 23 a0 27 00 sw sp, 0(a5) +80000790: 23 26 d1 01 sw t4, 12(sp) +80000794: 63 4c 20 03 bgtz s2, 56 +80000798: 63 16 04 06 bnez s0, 108 +8000079c: 83 20 c1 02 lw ra, 44(sp) +800007a0: 03 24 81 02 lw s0, 40(sp) +800007a4: 83 24 41 02 lw s1, 36(sp) +800007a8: 03 29 01 02 lw s2, 32(sp) +800007ac: 13 01 01 03 addi sp, sp, 48 +800007b0: 67 80 00 00 ret +800007b4: 13 87 08 00 mv a4, a7 +800007b8: e3 c4 e7 f2 blt a5, a4, -216 +800007bc: 6f f0 1f fe j -32 +800007c0: 13 0f 00 00 mv t5, zero +800007c4: 93 0f 10 00 addi t6, zero, 1 +800007c8: 6f f0 1f f5 j -176 +800007cc: 13 07 09 00 mv a4, s2 +800007d0: 63 54 23 01 bge t1, s2, 8 +800007d4: 13 07 03 00 mv a4, t1 +800007d8: b7 07 00 80 lui a5, 524288 +800007dc: 23 2c e1 00 sw a4, 24(sp) +800007e0: 93 87 c7 65 addi a5, a5, 1628 +800007e4: 6b 10 f7 00 vx_wspawn a4, a5 +800007e8: 93 07 f0 ff addi a5, zero, -1 +800007ec: 6b 80 07 00 vx_tmc a5 +800007f0: ef f0 df c8 jal -884 +800007f4: f3 27 30 cc csrr a5, 3267 +800007f8: 93 b7 17 00 seqz a5, a5 +800007fc: 6b 80 07 00 vx_tmc a5 +80000800: e3 0e 04 f8 beqz s0, -100 +80000804: b3 04 99 02 mul s1, s2, s1 +80000808: 13 09 10 00 addi s2, zero, 1 +8000080c: 33 14 89 00 sll s0, s2, s0 +80000810: 13 04 f4 ff addi s0, s0, -1 +80000814: 23 26 91 00 sw s1, 12(sp) +80000818: 6b 00 04 00 vx_tmc s0 +8000081c: ef f0 df d9 jal -612 +80000820: 6b 00 09 00 vx_tmc s2 +80000824: 83 20 c1 02 lw ra, 44(sp) +80000828: 03 24 81 02 lw s0, 40(sp) +8000082c: 83 24 41 02 lw s1, 36(sp) +80000830: 03 29 01 02 lw s2, 32(sp) +80000834: 13 01 01 03 addi sp, sp, 48 +80000838: 67 80 00 00 ret -80000a1c memset: -80000a1c: 13 03 f0 00 addi t1, zero, 15 -80000a20: 13 07 05 00 mv a4, a0 -80000a24: 63 7e c3 02 bgeu t1, a2, 60 -80000a28: 93 77 f7 00 andi a5, a4, 15 -80000a2c: 63 90 07 0a bnez a5, 160 -80000a30: 63 92 05 08 bnez a1, 132 -80000a34: 93 76 06 ff andi a3, a2, -16 -80000a38: 13 76 f6 00 andi a2, a2, 15 -80000a3c: b3 86 e6 00 add a3, a3, a4 -80000a40: 23 20 b7 00 sw a1, 0(a4) -80000a44: 23 22 b7 00 sw a1, 4(a4) -80000a48: 23 24 b7 00 sw a1, 8(a4) -80000a4c: 23 26 b7 00 sw a1, 12(a4) -80000a50: 13 07 07 01 addi a4, a4, 16 -80000a54: e3 66 d7 fe bltu a4, a3, -20 -80000a58: 63 14 06 00 bnez a2, 8 -80000a5c: 67 80 00 00 ret -80000a60: b3 06 c3 40 sub a3, t1, a2 -80000a64: 93 96 26 00 slli a3, a3, 2 -80000a68: 97 02 00 00 auipc t0, 0 -80000a6c: b3 86 56 00 add a3, a3, t0 -80000a70: 67 80 c6 00 jr 12(a3) -80000a74: 23 07 b7 00 sb a1, 14(a4) -80000a78: a3 06 b7 00 sb a1, 13(a4) -80000a7c: 23 06 b7 00 sb a1, 12(a4) -80000a80: a3 05 b7 00 sb a1, 11(a4) -80000a84: 23 05 b7 00 sb a1, 10(a4) -80000a88: a3 04 b7 00 sb a1, 9(a4) -80000a8c: 23 04 b7 00 sb a1, 8(a4) -80000a90: a3 03 b7 00 sb a1, 7(a4) -80000a94: 23 03 b7 00 sb a1, 6(a4) -80000a98: a3 02 b7 00 sb a1, 5(a4) -80000a9c: 23 02 b7 00 sb a1, 4(a4) -80000aa0: a3 01 b7 00 sb a1, 3(a4) -80000aa4: 23 01 b7 00 sb a1, 2(a4) -80000aa8: a3 00 b7 00 sb a1, 1(a4) -80000aac: 23 00 b7 00 sb a1, 0(a4) -80000ab0: 67 80 00 00 ret -80000ab4: 93 f5 f5 0f andi a1, a1, 255 -80000ab8: 93 96 85 00 slli a3, a1, 8 -80000abc: b3 e5 d5 00 or a1, a1, a3 -80000ac0: 93 96 05 01 slli a3, a1, 16 -80000ac4: b3 e5 d5 00 or a1, a1, a3 -80000ac8: 6f f0 df f6 j -148 -80000acc: 93 96 27 00 slli a3, a5, 2 -80000ad0: 97 02 00 00 auipc t0, 0 -80000ad4: b3 86 56 00 add a3, a3, t0 -80000ad8: 93 82 00 00 mv t0, ra -80000adc: e7 80 06 fa jalr -96(a3) -80000ae0: 93 80 02 00 mv ra, t0 -80000ae4: 93 87 07 ff addi a5, a5, -16 -80000ae8: 33 07 f7 40 sub a4, a4, a5 -80000aec: 33 06 f6 00 add a2, a2, a5 -80000af0: e3 78 c3 f6 bgeu t1, a2, -144 -80000af4: 6f f0 df f3 j -196 +8000083c vx_perf_dump: +8000083c: f3 27 50 cc csrr a5, 3269 +80000840: 37 07 ff 00 lui a4, 4080 +80000844: b3 87 e7 00 add a5, a5, a4 +80000848: 93 97 87 00 slli a5, a5, 8 +8000084c: 73 27 00 b0 csrr a4, mcycle +80000850: 23 a0 e7 00 sw a4, 0(a5) +80000854: 73 27 10 b0 csrr a4, 2817 +80000858: 23 a2 e7 00 sw a4, 4(a5) +8000085c: 73 27 20 b0 csrr a4, minstret +80000860: 23 a4 e7 00 sw a4, 8(a5) +80000864: 73 27 30 b0 csrr a4, mhpmcounter3 +80000868: 23 a6 e7 00 sw a4, 12(a5) +8000086c: 73 27 40 b0 csrr a4, mhpmcounter4 +80000870: 23 a8 e7 00 sw a4, 16(a5) +80000874: 73 27 50 b0 csrr a4, mhpmcounter5 +80000878: 23 aa e7 00 sw a4, 20(a5) +8000087c: 73 27 60 b0 csrr a4, mhpmcounter6 +80000880: 23 ac e7 00 sw a4, 24(a5) +80000884: 73 27 70 b0 csrr a4, mhpmcounter7 +80000888: 23 ae e7 00 sw a4, 28(a5) +8000088c: 73 27 80 b0 csrr a4, mhpmcounter8 +80000890: 23 a0 e7 02 sw a4, 32(a5) +80000894: 73 27 90 b0 csrr a4, mhpmcounter9 +80000898: 23 a2 e7 02 sw a4, 36(a5) +8000089c: 73 27 a0 b0 csrr a4, mhpmcounter10 +800008a0: 23 a4 e7 02 sw a4, 40(a5) +800008a4: 73 27 b0 b0 csrr a4, mhpmcounter11 +800008a8: 23 a6 e7 02 sw a4, 44(a5) +800008ac: 73 27 c0 b0 csrr a4, mhpmcounter12 +800008b0: 23 a8 e7 02 sw a4, 48(a5) +800008b4: 73 27 d0 b0 csrr a4, mhpmcounter13 +800008b8: 23 aa e7 02 sw a4, 52(a5) +800008bc: 73 27 e0 b0 csrr a4, mhpmcounter14 +800008c0: 23 ac e7 02 sw a4, 56(a5) +800008c4: 73 27 f0 b0 csrr a4, mhpmcounter15 +800008c8: 23 ae e7 02 sw a4, 60(a5) +800008cc: 73 27 00 b1 csrr a4, mhpmcounter16 +800008d0: 23 a0 e7 04 sw a4, 64(a5) +800008d4: 73 27 10 b1 csrr a4, mhpmcounter17 +800008d8: 23 a2 e7 04 sw a4, 68(a5) +800008dc: 73 27 20 b1 csrr a4, mhpmcounter18 +800008e0: 23 a4 e7 04 sw a4, 72(a5) +800008e4: 73 27 30 b1 csrr a4, mhpmcounter19 +800008e8: 23 a6 e7 04 sw a4, 76(a5) +800008ec: 73 27 40 b1 csrr a4, mhpmcounter20 +800008f0: 23 a8 e7 04 sw a4, 80(a5) +800008f4: 73 27 50 b1 csrr a4, mhpmcounter21 +800008f8: 23 aa e7 04 sw a4, 84(a5) +800008fc: 73 27 60 b1 csrr a4, mhpmcounter22 +80000900: 23 ac e7 04 sw a4, 88(a5) +80000904: 73 27 70 b1 csrr a4, mhpmcounter23 +80000908: 23 ae e7 04 sw a4, 92(a5) +8000090c: 73 27 80 b1 csrr a4, mhpmcounter24 +80000910: 23 a0 e7 06 sw a4, 96(a5) +80000914: 73 27 90 b1 csrr a4, mhpmcounter25 +80000918: 23 a2 e7 06 sw a4, 100(a5) +8000091c: 73 27 a0 b1 csrr a4, mhpmcounter26 +80000920: 23 a4 e7 06 sw a4, 104(a5) +80000924: 73 27 b0 b1 csrr a4, mhpmcounter27 +80000928: 23 a6 e7 06 sw a4, 108(a5) +8000092c: 73 27 c0 b1 csrr a4, mhpmcounter28 +80000930: 23 a8 e7 06 sw a4, 112(a5) +80000934: 73 27 d0 b1 csrr a4, mhpmcounter29 +80000938: 23 aa e7 06 sw a4, 116(a5) +8000093c: 73 27 e0 b1 csrr a4, mhpmcounter30 +80000940: 23 ac e7 06 sw a4, 120(a5) +80000944: 73 27 f0 b1 csrr a4, mhpmcounter31 +80000948: 23 ae e7 06 sw a4, 124(a5) +8000094c: 73 27 00 b8 csrr a4, mcycleh +80000950: 23 a0 e7 08 sw a4, 128(a5) +80000954: 73 27 10 b8 csrr a4, 2945 +80000958: 23 a2 e7 08 sw a4, 132(a5) +8000095c: 73 27 20 b8 csrr a4, minstreth +80000960: 23 a4 e7 08 sw a4, 136(a5) +80000964: 73 27 30 b8 csrr a4, mhpmcounter3h +80000968: 23 a6 e7 08 sw a4, 140(a5) +8000096c: 73 27 40 b8 csrr a4, mhpmcounter4h +80000970: 23 a8 e7 08 sw a4, 144(a5) +80000974: 73 27 50 b8 csrr a4, mhpmcounter5h +80000978: 23 aa e7 08 sw a4, 148(a5) +8000097c: 73 27 60 b8 csrr a4, mhpmcounter6h +80000980: 23 ac e7 08 sw a4, 152(a5) +80000984: 73 27 70 b8 csrr a4, mhpmcounter7h +80000988: 23 ae e7 08 sw a4, 156(a5) +8000098c: 73 27 80 b8 csrr a4, mhpmcounter8h +80000990: 23 a0 e7 0a sw a4, 160(a5) +80000994: 73 27 90 b8 csrr a4, mhpmcounter9h +80000998: 23 a2 e7 0a sw a4, 164(a5) +8000099c: 73 27 a0 b8 csrr a4, mhpmcounter10h +800009a0: 23 a4 e7 0a sw a4, 168(a5) +800009a4: 73 27 b0 b8 csrr a4, mhpmcounter11h +800009a8: 23 a6 e7 0a sw a4, 172(a5) +800009ac: 73 27 c0 b8 csrr a4, mhpmcounter12h +800009b0: 23 a8 e7 0a sw a4, 176(a5) +800009b4: 73 27 d0 b8 csrr a4, mhpmcounter13h +800009b8: 23 aa e7 0a sw a4, 180(a5) +800009bc: 73 27 e0 b8 csrr a4, mhpmcounter14h +800009c0: 23 ac e7 0a sw a4, 184(a5) +800009c4: 73 27 f0 b8 csrr a4, mhpmcounter15h +800009c8: 23 ae e7 0a sw a4, 188(a5) +800009cc: 73 27 00 b9 csrr a4, mhpmcounter16h +800009d0: 23 a0 e7 0c sw a4, 192(a5) +800009d4: 73 27 10 b9 csrr a4, mhpmcounter17h +800009d8: 23 a2 e7 0c sw a4, 196(a5) +800009dc: 73 27 20 b9 csrr a4, mhpmcounter18h +800009e0: 23 a4 e7 0c sw a4, 200(a5) +800009e4: 73 27 30 b9 csrr a4, mhpmcounter19h +800009e8: 23 a6 e7 0c sw a4, 204(a5) +800009ec: 73 27 40 b9 csrr a4, mhpmcounter20h +800009f0: 23 a8 e7 0c sw a4, 208(a5) +800009f4: 73 27 50 b9 csrr a4, mhpmcounter21h +800009f8: 23 aa e7 0c sw a4, 212(a5) +800009fc: 73 27 60 b9 csrr a4, mhpmcounter22h +80000a00: 23 ac e7 0c sw a4, 216(a5) +80000a04: 73 27 70 b9 csrr a4, mhpmcounter23h +80000a08: 23 ae e7 0c sw a4, 220(a5) +80000a0c: 73 27 80 b9 csrr a4, mhpmcounter24h +80000a10: 23 a0 e7 0e sw a4, 224(a5) +80000a14: 73 27 90 b9 csrr a4, mhpmcounter25h +80000a18: 23 a2 e7 0e sw a4, 228(a5) +80000a1c: 73 27 a0 b9 csrr a4, mhpmcounter26h +80000a20: 23 a4 e7 0e sw a4, 232(a5) +80000a24: 73 27 b0 b9 csrr a4, mhpmcounter27h +80000a28: 23 a6 e7 0e sw a4, 236(a5) +80000a2c: 73 27 c0 b9 csrr a4, mhpmcounter28h +80000a30: 23 a8 e7 0e sw a4, 240(a5) +80000a34: 73 27 d0 b9 csrr a4, mhpmcounter29h +80000a38: 23 aa e7 0e sw a4, 244(a5) +80000a3c: 73 27 e0 b9 csrr a4, mhpmcounter30h +80000a40: 23 ac e7 0e sw a4, 248(a5) +80000a44: 73 27 f0 b9 csrr a4, mhpmcounter31h +80000a48: 23 ae e7 0e sw a4, 252(a5) +80000a4c: 67 80 00 00 ret -80000af8 __register_exitproc: -80000af8: b7 17 00 80 lui a5, 524289 -80000afc: 03 a7 07 43 lw a4, 1072(a5) -80000b00: 83 27 87 14 lw a5, 328(a4) -80000b04: 63 8c 07 04 beqz a5, 88 -80000b08: 03 a7 47 00 lw a4, 4(a5) -80000b0c: 13 08 f0 01 addi a6, zero, 31 -80000b10: 63 4e e8 06 blt a6, a4, 124 -80000b14: 13 18 27 00 slli a6, a4, 2 -80000b18: 63 06 05 02 beqz a0, 44 -80000b1c: 33 83 07 01 add t1, a5, a6 -80000b20: 23 24 c3 08 sw a2, 136(t1) -80000b24: 83 a8 87 18 lw a7, 392(a5) -80000b28: 13 06 10 00 addi a2, zero, 1 -80000b2c: 33 16 e6 00 sll a2, a2, a4 -80000b30: b3 e8 c8 00 or a7, a7, a2 -80000b34: 23 a4 17 19 sw a7, 392(a5) -80000b38: 23 24 d3 10 sw a3, 264(t1) -80000b3c: 93 06 20 00 addi a3, zero, 2 -80000b40: 63 04 d5 02 beq a0, a3, 40 -80000b44: 13 07 17 00 addi a4, a4, 1 -80000b48: 23 a2 e7 00 sw a4, 4(a5) -80000b4c: b3 87 07 01 add a5, a5, a6 -80000b50: 23 a4 b7 00 sw a1, 8(a5) -80000b54: 13 05 00 00 mv a0, zero -80000b58: 67 80 00 00 ret -80000b5c: 93 07 c7 14 addi a5, a4, 332 -80000b60: 23 24 f7 14 sw a5, 328(a4) -80000b64: 6f f0 5f fa j -92 -80000b68: 83 a6 c7 18 lw a3, 396(a5) -80000b6c: 13 07 17 00 addi a4, a4, 1 -80000b70: 23 a2 e7 00 sw a4, 4(a5) -80000b74: 33 e6 c6 00 or a2, a3, a2 -80000b78: 23 a6 c7 18 sw a2, 396(a5) -80000b7c: b3 87 07 01 add a5, a5, a6 -80000b80: 23 a4 b7 00 sw a1, 8(a5) -80000b84: 13 05 00 00 mv a0, zero -80000b88: 67 80 00 00 ret -80000b8c: 13 05 f0 ff addi a0, zero, -1 -80000b90: 67 80 00 00 ret +80000a50 atexit: +80000a50: 93 05 05 00 mv a1, a0 +80000a54: 93 06 00 00 mv a3, zero +80000a58: 13 06 00 00 mv a2, zero +80000a5c: 13 05 00 00 mv a0, zero +80000a60: 6f 00 40 11 j 276 -80000b94 __call_exitprocs: -80000b94: 13 01 01 fd addi sp, sp, -48 -80000b98: b7 17 00 80 lui a5, 524289 -80000b9c: 23 2c 41 01 sw s4, 24(sp) -80000ba0: 03 aa 07 43 lw s4, 1072(a5) -80000ba4: 23 20 21 03 sw s2, 32(sp) -80000ba8: 23 26 11 02 sw ra, 44(sp) -80000bac: 03 29 8a 14 lw s2, 328(s4) -80000bb0: 23 24 81 02 sw s0, 40(sp) -80000bb4: 23 22 91 02 sw s1, 36(sp) -80000bb8: 23 2e 31 01 sw s3, 28(sp) -80000bbc: 23 2a 51 01 sw s5, 20(sp) -80000bc0: 23 28 61 01 sw s6, 16(sp) -80000bc4: 23 26 71 01 sw s7, 12(sp) -80000bc8: 23 24 81 01 sw s8, 8(sp) -80000bcc: 63 00 09 04 beqz s2, 64 -80000bd0: 13 0b 05 00 mv s6, a0 -80000bd4: 93 8b 05 00 mv s7, a1 -80000bd8: 93 0a 10 00 addi s5, zero, 1 -80000bdc: 93 09 f0 ff addi s3, zero, -1 -80000be0: 83 24 49 00 lw s1, 4(s2) -80000be4: 13 84 f4 ff addi s0, s1, -1 -80000be8: 63 42 04 02 bltz s0, 36 -80000bec: 93 94 24 00 slli s1, s1, 2 -80000bf0: b3 04 99 00 add s1, s2, s1 -80000bf4: 63 84 0b 04 beqz s7, 72 -80000bf8: 83 a7 44 10 lw a5, 260(s1) -80000bfc: 63 80 77 05 beq a5, s7, 64 -80000c00: 13 04 f4 ff addi s0, s0, -1 -80000c04: 93 84 c4 ff addi s1, s1, -4 -80000c08: e3 16 34 ff bne s0, s3, -20 -80000c0c: 83 20 c1 02 lw ra, 44(sp) -80000c10: 03 24 81 02 lw s0, 40(sp) -80000c14: 83 24 41 02 lw s1, 36(sp) -80000c18: 03 29 01 02 lw s2, 32(sp) -80000c1c: 83 29 c1 01 lw s3, 28(sp) -80000c20: 03 2a 81 01 lw s4, 24(sp) -80000c24: 83 2a 41 01 lw s5, 20(sp) -80000c28: 03 2b 01 01 lw s6, 16(sp) -80000c2c: 83 2b c1 00 lw s7, 12(sp) -80000c30: 03 2c 81 00 lw s8, 8(sp) -80000c34: 13 01 01 03 addi sp, sp, 48 -80000c38: 67 80 00 00 ret -80000c3c: 83 27 49 00 lw a5, 4(s2) -80000c40: 83 a6 44 00 lw a3, 4(s1) -80000c44: 93 87 f7 ff addi a5, a5, -1 -80000c48: 63 8e 87 04 beq a5, s0, 92 -80000c4c: 23 a2 04 00 sw zero, 4(s1) -80000c50: e3 88 06 fa beqz a3, -80 -80000c54: 83 27 89 18 lw a5, 392(s2) -80000c58: 33 97 8a 00 sll a4, s5, s0 -80000c5c: 03 2c 49 00 lw s8, 4(s2) -80000c60: b3 77 f7 00 and a5, a4, a5 -80000c64: 63 92 07 02 bnez a5, 36 -80000c68: e7 80 06 00 jalr a3 -80000c6c: 03 27 49 00 lw a4, 4(s2) -80000c70: 83 27 8a 14 lw a5, 328(s4) -80000c74: 63 14 87 01 bne a4, s8, 8 -80000c78: e3 04 f9 f8 beq s2, a5, -120 -80000c7c: e3 88 07 f8 beqz a5, -112 -80000c80: 13 89 07 00 mv s2, a5 -80000c84: 6f f0 df f5 j -164 -80000c88: 83 27 c9 18 lw a5, 396(s2) -80000c8c: 83 a5 44 08 lw a1, 132(s1) -80000c90: 33 77 f7 00 and a4, a4, a5 -80000c94: 63 1c 07 00 bnez a4, 24 -80000c98: 13 05 0b 00 mv a0, s6 -80000c9c: e7 80 06 00 jalr a3 -80000ca0: 6f f0 df fc j -52 -80000ca4: 23 22 89 00 sw s0, 4(s2) -80000ca8: 6f f0 9f fa j -88 -80000cac: 13 85 05 00 mv a0, a1 -80000cb0: e7 80 06 00 jalr a3 -80000cb4: 6f f0 9f fb j -72 +80000a64 exit: +80000a64: 13 01 01 ff addi sp, sp, -16 +80000a68: 93 05 00 00 mv a1, zero +80000a6c: 23 24 81 00 sw s0, 8(sp) +80000a70: 23 26 11 00 sw ra, 12(sp) +80000a74: 13 04 05 00 mv s0, a0 +80000a78: ef 00 80 19 jal 408 +80000a7c: b7 17 00 80 lui a5, 524289 +80000a80: 03 a5 07 43 lw a0, 1072(a5) +80000a84: 83 27 c5 03 lw a5, 60(a0) +80000a88: 63 84 07 00 beqz a5, 8 +80000a8c: e7 80 07 00 jalr a5 +80000a90: 13 05 04 00 mv a0, s0 +80000a94: ef f0 5f 8a jal -1884 + +80000a98 memset: +80000a98: 13 03 f0 00 addi t1, zero, 15 +80000a9c: 13 07 05 00 mv a4, a0 +80000aa0: 63 7e c3 02 bgeu t1, a2, 60 +80000aa4: 93 77 f7 00 andi a5, a4, 15 +80000aa8: 63 90 07 0a bnez a5, 160 +80000aac: 63 92 05 08 bnez a1, 132 +80000ab0: 93 76 06 ff andi a3, a2, -16 +80000ab4: 13 76 f6 00 andi a2, a2, 15 +80000ab8: b3 86 e6 00 add a3, a3, a4 +80000abc: 23 20 b7 00 sw a1, 0(a4) +80000ac0: 23 22 b7 00 sw a1, 4(a4) +80000ac4: 23 24 b7 00 sw a1, 8(a4) +80000ac8: 23 26 b7 00 sw a1, 12(a4) +80000acc: 13 07 07 01 addi a4, a4, 16 +80000ad0: e3 66 d7 fe bltu a4, a3, -20 +80000ad4: 63 14 06 00 bnez a2, 8 +80000ad8: 67 80 00 00 ret +80000adc: b3 06 c3 40 sub a3, t1, a2 +80000ae0: 93 96 26 00 slli a3, a3, 2 +80000ae4: 97 02 00 00 auipc t0, 0 +80000ae8: b3 86 56 00 add a3, a3, t0 +80000aec: 67 80 c6 00 jr 12(a3) +80000af0: 23 07 b7 00 sb a1, 14(a4) +80000af4: a3 06 b7 00 sb a1, 13(a4) +80000af8: 23 06 b7 00 sb a1, 12(a4) +80000afc: a3 05 b7 00 sb a1, 11(a4) +80000b00: 23 05 b7 00 sb a1, 10(a4) +80000b04: a3 04 b7 00 sb a1, 9(a4) +80000b08: 23 04 b7 00 sb a1, 8(a4) +80000b0c: a3 03 b7 00 sb a1, 7(a4) +80000b10: 23 03 b7 00 sb a1, 6(a4) +80000b14: a3 02 b7 00 sb a1, 5(a4) +80000b18: 23 02 b7 00 sb a1, 4(a4) +80000b1c: a3 01 b7 00 sb a1, 3(a4) +80000b20: 23 01 b7 00 sb a1, 2(a4) +80000b24: a3 00 b7 00 sb a1, 1(a4) +80000b28: 23 00 b7 00 sb a1, 0(a4) +80000b2c: 67 80 00 00 ret +80000b30: 93 f5 f5 0f andi a1, a1, 255 +80000b34: 93 96 85 00 slli a3, a1, 8 +80000b38: b3 e5 d5 00 or a1, a1, a3 +80000b3c: 93 96 05 01 slli a3, a1, 16 +80000b40: b3 e5 d5 00 or a1, a1, a3 +80000b44: 6f f0 df f6 j -148 +80000b48: 93 96 27 00 slli a3, a5, 2 +80000b4c: 97 02 00 00 auipc t0, 0 +80000b50: b3 86 56 00 add a3, a3, t0 +80000b54: 93 82 00 00 mv t0, ra +80000b58: e7 80 06 fa jalr -96(a3) +80000b5c: 93 80 02 00 mv ra, t0 +80000b60: 93 87 07 ff addi a5, a5, -16 +80000b64: 33 07 f7 40 sub a4, a4, a5 +80000b68: 33 06 f6 00 add a2, a2, a5 +80000b6c: e3 78 c3 f6 bgeu t1, a2, -144 +80000b70: 6f f0 df f3 j -196 + +80000b74 __register_exitproc: +80000b74: b7 17 00 80 lui a5, 524289 +80000b78: 03 a7 07 43 lw a4, 1072(a5) +80000b7c: 83 27 87 14 lw a5, 328(a4) +80000b80: 63 8c 07 04 beqz a5, 88 +80000b84: 03 a7 47 00 lw a4, 4(a5) +80000b88: 13 08 f0 01 addi a6, zero, 31 +80000b8c: 63 4e e8 06 blt a6, a4, 124 +80000b90: 13 18 27 00 slli a6, a4, 2 +80000b94: 63 06 05 02 beqz a0, 44 +80000b98: 33 83 07 01 add t1, a5, a6 +80000b9c: 23 24 c3 08 sw a2, 136(t1) +80000ba0: 83 a8 87 18 lw a7, 392(a5) +80000ba4: 13 06 10 00 addi a2, zero, 1 +80000ba8: 33 16 e6 00 sll a2, a2, a4 +80000bac: b3 e8 c8 00 or a7, a7, a2 +80000bb0: 23 a4 17 19 sw a7, 392(a5) +80000bb4: 23 24 d3 10 sw a3, 264(t1) +80000bb8: 93 06 20 00 addi a3, zero, 2 +80000bbc: 63 04 d5 02 beq a0, a3, 40 +80000bc0: 13 07 17 00 addi a4, a4, 1 +80000bc4: 23 a2 e7 00 sw a4, 4(a5) +80000bc8: b3 87 07 01 add a5, a5, a6 +80000bcc: 23 a4 b7 00 sw a1, 8(a5) +80000bd0: 13 05 00 00 mv a0, zero +80000bd4: 67 80 00 00 ret +80000bd8: 93 07 c7 14 addi a5, a4, 332 +80000bdc: 23 24 f7 14 sw a5, 328(a4) +80000be0: 6f f0 5f fa j -92 +80000be4: 83 a6 c7 18 lw a3, 396(a5) +80000be8: 13 07 17 00 addi a4, a4, 1 +80000bec: 23 a2 e7 00 sw a4, 4(a5) +80000bf0: 33 e6 c6 00 or a2, a3, a2 +80000bf4: 23 a6 c7 18 sw a2, 396(a5) +80000bf8: b3 87 07 01 add a5, a5, a6 +80000bfc: 23 a4 b7 00 sw a1, 8(a5) +80000c00: 13 05 00 00 mv a0, zero +80000c04: 67 80 00 00 ret +80000c08: 13 05 f0 ff addi a0, zero, -1 +80000c0c: 67 80 00 00 ret + +80000c10 __call_exitprocs: +80000c10: 13 01 01 fd addi sp, sp, -48 +80000c14: b7 17 00 80 lui a5, 524289 +80000c18: 23 2c 41 01 sw s4, 24(sp) +80000c1c: 03 aa 07 43 lw s4, 1072(a5) +80000c20: 23 20 21 03 sw s2, 32(sp) +80000c24: 23 26 11 02 sw ra, 44(sp) +80000c28: 03 29 8a 14 lw s2, 328(s4) +80000c2c: 23 24 81 02 sw s0, 40(sp) +80000c30: 23 22 91 02 sw s1, 36(sp) +80000c34: 23 2e 31 01 sw s3, 28(sp) +80000c38: 23 2a 51 01 sw s5, 20(sp) +80000c3c: 23 28 61 01 sw s6, 16(sp) +80000c40: 23 26 71 01 sw s7, 12(sp) +80000c44: 23 24 81 01 sw s8, 8(sp) +80000c48: 63 00 09 04 beqz s2, 64 +80000c4c: 13 0b 05 00 mv s6, a0 +80000c50: 93 8b 05 00 mv s7, a1 +80000c54: 93 0a 10 00 addi s5, zero, 1 +80000c58: 93 09 f0 ff addi s3, zero, -1 +80000c5c: 83 24 49 00 lw s1, 4(s2) +80000c60: 13 84 f4 ff addi s0, s1, -1 +80000c64: 63 42 04 02 bltz s0, 36 +80000c68: 93 94 24 00 slli s1, s1, 2 +80000c6c: b3 04 99 00 add s1, s2, s1 +80000c70: 63 84 0b 04 beqz s7, 72 +80000c74: 83 a7 44 10 lw a5, 260(s1) +80000c78: 63 80 77 05 beq a5, s7, 64 +80000c7c: 13 04 f4 ff addi s0, s0, -1 +80000c80: 93 84 c4 ff addi s1, s1, -4 +80000c84: e3 16 34 ff bne s0, s3, -20 +80000c88: 83 20 c1 02 lw ra, 44(sp) +80000c8c: 03 24 81 02 lw s0, 40(sp) +80000c90: 83 24 41 02 lw s1, 36(sp) +80000c94: 03 29 01 02 lw s2, 32(sp) +80000c98: 83 29 c1 01 lw s3, 28(sp) +80000c9c: 03 2a 81 01 lw s4, 24(sp) +80000ca0: 83 2a 41 01 lw s5, 20(sp) +80000ca4: 03 2b 01 01 lw s6, 16(sp) +80000ca8: 83 2b c1 00 lw s7, 12(sp) +80000cac: 03 2c 81 00 lw s8, 8(sp) +80000cb0: 13 01 01 03 addi sp, sp, 48 +80000cb4: 67 80 00 00 ret +80000cb8: 83 27 49 00 lw a5, 4(s2) +80000cbc: 83 a6 44 00 lw a3, 4(s1) +80000cc0: 93 87 f7 ff addi a5, a5, -1 +80000cc4: 63 8e 87 04 beq a5, s0, 92 +80000cc8: 23 a2 04 00 sw zero, 4(s1) +80000ccc: e3 88 06 fa beqz a3, -80 +80000cd0: 83 27 89 18 lw a5, 392(s2) +80000cd4: 33 97 8a 00 sll a4, s5, s0 +80000cd8: 03 2c 49 00 lw s8, 4(s2) +80000cdc: b3 77 f7 00 and a5, a4, a5 +80000ce0: 63 92 07 02 bnez a5, 36 +80000ce4: e7 80 06 00 jalr a3 +80000ce8: 03 27 49 00 lw a4, 4(s2) +80000cec: 83 27 8a 14 lw a5, 328(s4) +80000cf0: 63 14 87 01 bne a4, s8, 8 +80000cf4: e3 04 f9 f8 beq s2, a5, -120 +80000cf8: e3 88 07 f8 beqz a5, -112 +80000cfc: 13 89 07 00 mv s2, a5 +80000d00: 6f f0 df f5 j -164 +80000d04: 83 27 c9 18 lw a5, 396(s2) +80000d08: 83 a5 44 08 lw a1, 132(s1) +80000d0c: 33 77 f7 00 and a4, a4, a5 +80000d10: 63 1c 07 00 bnez a4, 24 +80000d14: 13 05 0b 00 mv a0, s6 +80000d18: e7 80 06 00 jalr a3 +80000d1c: 6f f0 df fc j -52 +80000d20: 23 22 89 00 sw s0, 4(s2) +80000d24: 6f f0 9f fa j -88 +80000d28: 13 85 05 00 mv a0, a1 +80000d2c: e7 80 06 00 jalr a3 +80000d30: 6f f0 9f fb j -72 Disassembly of section .init_array: @@ -928,25 +965,25 @@ Disassembly of section .comment: 36: 6a 65 38: 63 74 2e 67 bgeu t3, s2, 1640 3c: 69 74 - 3e: 20 65 - 40: 66 33 - 42: 32 63 - 44: 36 31 - 46: 31 61 - 48: 61 32 - 4a: 31 34 - 4c: 64 65 - 4e: 61 38 - 50: 35 35 - 52: 33 36 34 65 - 56: 66 64 - 58: 37 62 61 34 lui tp, 214550 - 5c: 35 31 - 5e: 65 63 - 60: 35 65 - 62: 63 33 66 37 - 66: 34 29 - 68: 00 47 + 3e: 20 32 + 40: 61 32 + 42: 33 65 66 61 + 46: 63 33 35 32 + 4a: 66 39 + 4c: 31 39 + 4e: 65 62 + 50: 64 31 + 52: 65 63 + 54: 31 62 + 56: 65 34 + 58: 35 31 + 5a: 34 36 + 5c: 64 36 + 5e: 61 39 + 60: 66 61 + 62: 32 31 + 64: 62 35 + 66: 33 29 00 47 6a: 43 43 3a 20 fmadd.s ft6, fs4, ft3, ft4, rmm 6e: 28 47 70: 4e 55 @@ -1030,342 +1067,360 @@ Disassembly of section .symtab: 9e: f1 ff a0: 0e 00 a2: 00 00 - a4: 50 03 + a4: 44 03 a6: 00 80 a8: 00 00 aa: 00 00 ac: 00 00 ae: 02 00 - b0: 15 00 - ... + b0: 1e 00 + b2: 00 00 + b4: 80 03 + b6: 00 80 + b8: 00 00 ba: 00 00 - bc: 04 00 - be: f1 ff + bc: 00 00 + be: 02 00 c0: 25 00 - c2: 00 00 - c4: 50 00 - c6: 00 80 - c8: 18 00 - ca: 00 00 - cc: 02 00 - ce: 02 00 - d0: 33 00 00 00 add zero, zero, zero ... - dc: 04 00 - de: f1 ff - e0: 57 00 00 00 + ca: 00 00 + cc: 04 00 + ce: f1 ff + d0: 35 00 + d2: 00 00 + d4: 50 00 + d6: 00 80 + d8: 18 00 + da: 00 00 + dc: 02 00 + de: 02 00 + e0: 43 00 00 00 fmadd.s ft0, ft0, ft0, ft0, rne ... ec: 04 00 ee: f1 ff - f0: 63 00 00 00 beqz zero, 0 + f0: 67 00 00 00 jr zero ... fc: 04 00 fe: f1 ff - 100: 6e 00 - 102: 00 00 - 104: 54 03 - 106: 00 80 - 108: 48 01 - 10a: 00 00 - 10c: 02 00 - 10e: 02 00 - 110: 84 00 + 100: 73 00 00 00 ecall + ... + 10c: 04 00 + 10e: f1 ff + 110: 81 00 ... 11a: 00 00 11c: 04 00 11e: f1 ff - 120: 9e 00 - ... + 120: 8c 00 + 122: 00 00 + 124: 7c 04 + 126: 00 80 + 128: 3c 01 12a: 00 00 - 12c: 04 00 - 12e: f1 ff - 130: a0 00 - ... + 12c: 02 00 + 12e: 02 00 + 130: a2 00 + 132: 00 00 + 134: b8 05 + 136: 00 80 + 138: a4 00 13a: 00 00 - 13c: 04 00 - 13e: f1 ff - 140: 8e 00 - ... + 13c: 02 00 + 13e: 02 00 + 140: b8 00 + 142: 00 00 + 144: 5c 06 + 146: 00 80 + 148: 2c 00 14a: 00 00 - 14c: 04 00 - 14e: f1 ff - 150: 95 00 + 14c: 02 00 + 14e: 02 00 + 150: cc 00 ... 15a: 00 00 15c: 04 00 15e: f1 ff - 160: 9c 00 + 160: d8 00 ... 16a: 00 00 16c: 04 00 16e: f1 ff - 170: a7 00 00 00 + 170: da 00 ... + 17a: 00 00 17c: 04 00 17e: f1 ff - 180: b0 00 - 182: 00 00 - 184: 08 10 - 186: 00 80 - 188: 28 04 - 18a: 00 00 - 18c: 01 00 - 18e: 04 00 + 180: d6 00 ... + 18a: 00 00 + 18c: 04 00 + 18e: f1 ff + 190: e1 00 + ... + 19a: 00 00 19c: 04 00 19e: f1 ff - 1a0: bc 00 + 1a0: ea 00 1a2: 00 00 - 1a4: 04 10 + 1a4: 08 10 1a6: 00 80 - 1a8: 00 00 + 1a8: 28 04 1aa: 00 00 - 1ac: 00 00 - 1ae: 03 00 cd 00 lb zero, 12(s10) - 1b2: 00 00 - 1b4: 04 10 - 1b6: 00 80 - 1b8: 00 00 - 1ba: 00 00 - 1bc: 00 00 - 1be: 03 00 e0 00 lb zero, 14(zero) + 1ac: 01 00 + 1ae: 04 00 + ... + 1bc: 04 00 + 1be: f1 ff + 1c0: f6 00 1c2: 00 00 1c4: 04 10 1c6: 00 80 1c8: 00 00 1ca: 00 00 1cc: 00 00 - 1ce: 03 00 f1 00 lb zero, 15(sp) + 1ce: 03 00 07 01 lb zero, 16(a4) 1d2: 00 00 - 1d4: 00 10 + 1d4: 04 10 1d6: 00 80 1d8: 00 00 1da: 00 00 1dc: 00 00 - 1de: 03 00 05 01 lb zero, 16(a0) + 1de: 03 00 1a 01 lb zero, 17(s4) 1e2: 00 00 - 1e4: 00 10 + 1e4: 04 10 1e6: 00 80 1e8: 00 00 1ea: 00 00 1ec: 00 00 - 1ee: 03 00 18 01 lb zero, 17(a6) + 1ee: 03 00 2b 01 lb zero, 18(s6) 1f2: 00 00 1f4: 00 10 1f6: 00 80 1f8: 00 00 1fa: 00 00 1fc: 00 00 - 1fe: 03 00 2e 01 lb zero, 18(t3) - ... + 1fe: 03 00 3f 01 lb zero, 19(t5) + 202: 00 00 + 204: 00 10 + 206: 00 80 + 208: 00 00 20a: 00 00 - 20c: 10 00 - 20e: f1 ff - 210: 3c 01 + 20c: 00 00 + 20e: 03 00 52 01 lb zero, 21(tp) 212: 00 00 - 214: 00 04 - 216: 00 00 + 214: 00 10 + 216: 00 80 218: 00 00 21a: 00 00 - 21c: 10 00 - 21e: f1 ff - 220: 49 01 - 222: 00 00 - 224: 34 14 - 226: 00 80 - 228: 80 00 + 21c: 00 00 + 21e: 03 00 68 01 lb zero, 22(a6) + ... 22a: 00 00 - 22c: 11 00 - 22e: 06 00 - 230: 57 01 00 00 - 234: 30 14 - 236: 00 80 + 22c: 10 00 + 22e: f1 ff + 230: 76 01 + 232: 00 00 + 234: 00 04 + 236: 00 00 238: 00 00 23a: 00 00 23c: 10 00 - 23e: 05 00 - 240: 67 01 00 00 jalr sp, zero - 244: 74 01 + 23e: f1 ff + 240: 83 01 00 00 lb gp, 0(zero) + 244: 34 14 246: 00 80 - 248: d0 00 + 248: 80 00 24a: 00 00 - 24c: 12 00 - 24e: 02 00 - 250: 83 01 00 00 lb gp, 0(zero) - 254: 08 18 + 24c: 11 00 + 24e: 06 00 + 250: 91 01 + 252: 00 00 + 254: 30 14 256: 00 80 258: 00 00 25a: 00 00 25c: 10 00 - 25e: f1 ff - 260: 94 01 + 25e: 05 00 + 260: a1 01 262: 00 00 - 264: 30 14 + 264: 74 01 266: 00 80 - 268: 04 00 + 268: fc 00 26a: 00 00 - 26c: 11 00 - 26e: 05 00 - 270: a7 01 00 00 - 274: 80 09 + 26c: 12 00 + 26e: 02 00 + 270: bd 01 + 272: 00 00 + 274: 08 18 276: 00 80 - 278: 9c 00 + 278: 00 00 27a: 00 00 - 27c: 12 00 - 27e: 02 00 - 280: b9 01 + 27c: 10 00 + 27e: f1 ff + 280: ce 01 282: 00 00 - 284: 24 09 + 284: 30 14 286: 00 80 - 288: 5c 00 + 288: 04 00 28a: 00 00 - 28c: 12 00 - 28e: 02 00 - 290: cb 01 00 00 fnmsub.s ft3, ft0, ft0, ft0, rne - 294: 00 00 - 296: 00 ff - 298: 00 00 + 28c: 11 00 + 28e: 05 00 + 290: e1 01 + 292: 00 00 + 294: 84 03 + 296: 00 80 + 298: 9c 00 29a: 00 00 - 29c: 10 00 - 29e: f1 ff - 2a0: d7 01 00 00 - 2a4: 98 00 + 29c: 12 00 + 29e: 02 00 + 2a0: f3 01 00 00 + 2a4: 20 04 2a6: 00 80 - 2a8: dc 00 + 2a8: 5c 00 2aa: 00 00 2ac: 12 00 2ae: 02 00 - 2b0: e9 01 + 2b0: 05 02 2b2: 00 00 - 2b4: 18 03 + 2b4: 98 00 2b6: 00 80 - 2b8: 00 00 + 2b8: dc 00 2ba: 00 00 2bc: 12 00 2be: 02 00 - 2c0: f3 01 00 00 - 2c4: 94 0b + 2c0: 17 02 00 00 auipc tp, 0 + 2c4: 50 03 2c6: 00 80 - 2c8: 24 01 + 2c8: 00 00 2ca: 00 00 2cc: 12 00 2ce: 02 00 - 2d0: 29 02 + 2d0: 21 02 2d2: 00 00 - 2d4: 00 00 + 2d4: 10 0c 2d6: 00 80 - 2d8: 50 00 + 2d8: 24 01 2da: 00 00 2dc: 12 00 - 2de: 01 00 - 2e0: 04 02 - 2e2: 00 00 - 2e4: f8 0a + 2de: 02 00 + 2e0: 57 02 00 00 + 2e4: 00 00 2e6: 00 80 - 2e8: 9c 00 + 2e8: 50 00 2ea: 00 00 2ec: 12 00 - 2ee: 02 00 - 2f0: 18 02 + 2ee: 01 00 + 2f0: 32 02 2f2: 00 00 - 2f4: b4 14 + 2f4: 74 0b 2f6: 00 80 - 2f8: 00 00 + 2f8: 9c 00 2fa: 00 00 - 2fc: 10 00 - 2fe: 06 00 - 300: 24 02 + 2fc: 12 00 + 2fe: 02 00 + 300: 46 02 302: 00 00 - 304: 34 14 + 304: b4 14 306: 00 80 308: 00 00 30a: 00 00 30c: 10 00 30e: 06 00 - 310: 30 02 + 310: 52 02 312: 00 00 - 314: 1c 0a + 314: 34 14 316: 00 80 - 318: dc 00 + 318: 00 00 31a: 00 00 - 31c: 12 00 - 31e: 02 00 - 320: 37 02 00 00 lui tp, 0 - 324: 68 00 + 31c: 10 00 + 31e: 06 00 + 320: 5e 02 + 322: 00 00 + 324: 98 0a 326: 00 80 - 328: 30 00 + 328: dc 00 32a: 00 00 32c: 12 00 32e: 02 00 - 330: 3c 02 + 330: 65 02 332: 00 00 - 334: dc 08 + 334: 68 00 336: 00 80 - 338: 14 00 + 338: 30 00 33a: 00 00 33c: 12 00 33e: 02 00 - 340: 43 02 00 00 fmadd.s ft4, ft0, ft0, ft0, rne - 344: 08 10 + 340: 6a 02 + 342: 00 00 + 344: 50 0a 346: 00 80 - 348: 00 00 + 348: 14 00 34a: 00 00 - 34c: 10 00 - 34e: 04 00 - 350: 52 02 + 34c: 12 00 + 34e: 02 00 + 350: 71 02 352: 00 00 - 354: 44 02 + 354: 08 10 356: 00 80 - 358: c8 00 + 358: 00 00 35a: 00 00 - 35c: 12 00 - 35e: 02 00 - 360: 73 02 00 00 - 364: 34 14 + 35c: 10 00 + 35e: 04 00 + 360: 80 02 + 362: 00 00 + 364: 70 02 366: 00 80 - 368: 00 00 + 368: c8 00 36a: 00 00 - 36c: 10 00 - 36e: 05 00 - 370: c8 00 + 36c: 12 00 + 36e: 02 00 + 370: a1 02 372: 00 00 - 374: b4 14 + 374: 34 14 376: 00 80 378: 00 00 37a: 00 00 37c: 10 00 - 37e: 06 00 - 380: 88 02 + 37e: 05 00 + 380: 02 01 382: 00 00 - 384: f0 08 + 384: b4 14 386: 00 80 - 388: 34 00 + 388: 00 00 38a: 00 00 - 38c: 12 00 - 38e: 02 00 - 390: 7a 02 + 38c: 10 00 + 38e: 06 00 + 390: b6 02 392: 00 00 - 394: c8 06 + 394: 64 0a 396: 00 80 - 398: 14 02 + 398: 34 00 39a: 00 00 39c: 12 00 39e: 02 00 - 3a0: 87 02 00 00 - 3a4: 0c 03 + 3a0: a8 02 + 3a2: 00 00 + 3a4: 3c 08 3a6: 00 80 - 3a8: 00 00 + 3a8: 14 02 3aa: 00 00 3ac: 12 00 3ae: 02 00 - 3b0: 8d 02 + 3b0: b5 02 3b2: 00 00 - 3b4: 9c 04 + 3b4: 38 03 3b6: 00 80 - 3b8: 2c 02 + 3b8: 00 00 3ba: 00 00 3bc: 12 00 3be: 02 00 + 3c0: bb 02 00 00 + 3c4: 88 06 + 3c6: 00 80 + 3c8: b4 01 + 3ca: 00 00 + 3cc: 12 00 + 3ce: 02 00 Disassembly of section .strtab: @@ -1375,258 +1430,274 @@ Disassembly of section .strtab: 4: 73 74 61 72 csrrci s0, 1830, 2 8: 74 2e a: 53 2e 6f 00 fadd.s ft8, ft10, ft6, rdn - e: 52 45 - 10: 54 55 - 12: 52 4e - 14: 00 5f - 16: 5f 63 61 6c - 1a: 6c 5f - 1c: 61 74 - 1e: 65 78 - 20: 69 74 - 22: 2e 63 - 24: 00 72 - 26: 65 67 - 28: 69 73 - 2a: 74 65 - 2c: 72 5f - 2e: 66 69 - 30: 6e 69 - 32: 00 70 - 34: 6f 63 6c 5f jal t1, 812534 - 38: 76 6f - 3a: 72 74 - 3c: 65 78 - 3e: 5f 6b 65 72 - 42: 6e 65 - 44: 6c 2d - 46: 35 36 - 48: 2d 32 - 4a: 61 2d - 4c: 30 35 - 4e: 2d 63 - 50: 62 2d - 52: 36 37 - 54: 2e 63 - 56: 00 70 - 58: 61 72 - 5a: 61 6c - 5c: 6c 65 - 5e: 6c 5f - 60: 62 63 - 62: 00 76 - 64: 78 5f - 66: 73 70 61 77 csrci 1910, 2 - 6a: 6e 2e - 6c: 63 00 73 70 beq t1, t2, 1792 - 70: 61 77 - 72: 6e 5f - 74: 6b 65 72 6e - 78: 65 6c - 7a: 5f 63 61 6c - 7e: 6c 62 - 80: 61 63 - 82: 6b 00 76 78 - 86: 5f 70 65 72 - 8a: 66 2e - 8c: 63 00 66 69 beq a2, s6, 1664 - 90: 6e 69 - 92: 2e 63 - 94: 00 69 - 96: 6e 69 - 98: 74 2e - 9a: 63 00 5f 5f beq t5, s5, 1504 - 9e: 61 74 - a0: 65 78 - a2: 69 74 - a4: 2e 63 - a6: 00 69 - a8: 6d 70 - aa: 75 72 - ac: 65 2e - ae: 63 00 69 6d beq s2, s6, 1728 - b2: 70 75 - b4: 72 65 - b6: 5f 64 61 74 - ba: 61 00 - bc: 5f 5f 66 69 - c0: 6e 69 - c2: 5f 61 72 72 - c6: 61 79 - c8: 5f 65 6e 64 - cc: 00 5f - ce: 5f 66 69 6e - d2: 69 5f - d4: 61 72 - d6: 72 61 - d8: 79 5f - da: 73 74 61 72 csrrci s0, 1830, 2 - de: 74 00 - e0: 5f 5f 69 6e - e4: 69 74 - e6: 5f 61 72 72 - ea: 61 79 - ec: 5f 65 6e 64 - f0: 00 5f - f2: 5f 70 72 65 - f6: 69 6e - f8: 69 74 - fa: 5f 61 72 72 - fe: 61 79 - 100: 5f 65 6e 64 - 104: 00 5f - 106: 5f 69 6e 69 - 10a: 74 5f - 10c: 61 72 - 10e: 72 61 - 110: 79 5f - 112: 73 74 61 72 csrrci s0, 1830, 2 - 116: 74 00 - 118: 5f 5f 70 72 - 11c: 65 69 - 11e: 6e 69 - 120: 74 5f - 122: 61 72 - 124: 72 61 - 126: 79 5f - 128: 73 74 61 72 csrrci s0, 1830, 2 - 12c: 74 00 - 12e: 5f 5f 73 74 - 132: 61 63 - 134: 6b 5f 75 73 - 138: 61 67 - 13a: 65 00 - 13c: 5f 5f 73 74 - 140: 61 63 - 142: 6b 5f 73 69 - 146: 7a 65 - 148: 00 67 - 14a: 5f 77 73 70 - 14e: 61 77 - 150: 6e 5f - 152: 61 72 - 154: 67 73 00 5f - 158: 5f 53 44 41 - 15c: 54 41 - 15e: 5f 42 45 47 - 162: 49 4e - 164: 5f 5f 00 5f - 168: 70 6f - 16a: 63 6c 5f 6b bltu t5, s5, 1720 - 16e: 65 72 - 170: 6e 65 - 172: 6c 5f - 174: 46 61 - 176: 6e 31 - 178: 5f 77 6f 72 - 17c: 6b 67 72 6f - 180: 75 70 - 182: 00 5f - 184: 5f 67 6c 6f - 188: 62 61 - 18a: 6c 5f - 18c: 70 6f - 18e: 69 6e - 190: 74 65 - 192: 72 00 - 194: 5f 67 6c 6f - 198: 62 61 - 19a: 6c 5f - 19c: 69 6d - 19e: 70 75 - 1a0: 72 65 - 1a2: 5f 70 74 72 - 1a6: 00 5f - 1a8: 5f 6c 69 62 - 1ac: 63 5f 69 6e bge s2, t1, 1790 - 1b0: 69 74 - 1b2: 5f 61 72 72 - 1b6: 61 79 - 1b8: 00 5f - 1ba: 5f 6c 69 62 - 1be: 63 5f 66 69 bge a2, s6, 1694 - 1c2: 6e 69 - 1c4: 5f 61 72 72 - 1c8: 61 79 - 1ca: 00 5f - 1cc: 5f 73 74 61 - 1d0: 63 6b 5f 74 bltu t5, t0, 1878 - 1d4: 6f 70 00 5f j 30192 - 1d8: 70 6f - 1da: 63 6c 5f 6b bltu t5, s5, 1720 - 1de: 65 72 - 1e0: 6e 65 - 1e2: 6c 5f - 1e4: 46 61 - 1e6: 6e 31 - 1e8: 00 76 - 1ea: 78 5f - 1ec: 73 65 74 5f csrrsi a0, 1527, 8 - 1f0: 73 70 00 5f csrci 1520, 0 - 1f4: 5f 63 61 6c - 1f8: 6c 5f - 1fa: 65 78 - 1fc: 69 74 - 1fe: 70 72 - 200: 6f 63 73 00 jal t1, 223238 - 204: 5f 5f 72 65 - 208: 67 69 73 74 + e: 6c 61 + 10: 62 65 + 12: 6c 5f + 14: 65 78 + 16: 69 74 + 18: 5f 6e 65 78 + 1c: 74 00 + 1e: 52 45 + 20: 54 55 + 22: 52 4e + 24: 00 5f + 26: 5f 63 61 6c + 2a: 6c 5f + 2c: 61 74 + 2e: 65 78 + 30: 69 74 + 32: 2e 63 + 34: 00 72 + 36: 65 67 + 38: 69 73 + 3a: 74 65 + 3c: 72 5f + 3e: 66 69 + 40: 6e 69 + 42: 00 70 + 44: 6f 63 6c 5f jal t1, 812534 + 48: 76 6f + 4a: 72 74 + 4c: 65 78 + 4e: 5f 6b 65 72 + 52: 6e 65 + 54: 6c 2d + 56: 33 33 2d 39 + 5a: 35 2d + 5c: 31 33 + 5e: 2d 39 + 60: 61 2d + 62: 35 38 + 64: 2e 63 + 66: 00 70 + 68: 61 72 + 6a: 61 6c + 6c: 6c 65 + 6e: 6c 5f + 70: 62 63 + 72: 00 76 + 74: 78 5f + 76: 73 79 73 63 csrrci s2, 1591, 6 + 7a: 61 6c + 7c: 6c 73 + 7e: 2e 63 + 80: 00 76 + 82: 78 5f + 84: 73 70 61 77 csrci 1910, 2 + 88: 6e 2e + 8a: 63 00 73 70 beq t1, t2, 1792 + 8e: 61 77 + 90: 6e 5f + 92: 6b 65 72 6e + 96: 65 6c + 98: 5f 61 6c 6c + 9c: 5f 73 74 75 + a0: 62 00 + a2: 73 70 61 77 csrci 1910, 2 + a6: 6e 5f + a8: 6b 65 72 6e + ac: 65 6c + ae: 5f 72 65 6d + b2: 5f 73 74 75 + b6: 62 00 + b8: 73 70 61 77 csrci 1910, 2 + bc: 6e 5f + be: 6b 65 72 6e + c2: 65 6c + c4: 5f 61 6c 6c + c8: 5f 63 62 00 + cc: 76 78 + ce: 5f 70 65 72 + d2: 66 2e + d4: 63 00 5f 5f beq t5, s5, 1504 + d8: 61 74 + da: 65 78 + dc: 69 74 + de: 2e 63 + e0: 00 69 + e2: 6d 70 + e4: 75 72 + e6: 65 2e + e8: 63 00 69 6d beq s2, s6, 1728 + ec: 70 75 + ee: 72 65 + f0: 5f 64 61 74 + f4: 61 00 + f6: 5f 5f 66 69 + fa: 6e 69 + fc: 5f 61 72 72 + 100: 61 79 + 102: 5f 65 6e 64 + 106: 00 5f + 108: 5f 66 69 6e + 10c: 69 5f + 10e: 61 72 + 110: 72 61 + 112: 79 5f + 114: 73 74 61 72 csrrci s0, 1830, 2 + 118: 74 00 + 11a: 5f 5f 69 6e + 11e: 69 74 + 120: 5f 61 72 72 + 124: 61 79 + 126: 5f 65 6e 64 + 12a: 00 5f + 12c: 5f 70 72 65 + 130: 69 6e + 132: 69 74 + 134: 5f 61 72 72 + 138: 61 79 + 13a: 5f 65 6e 64 + 13e: 00 5f + 140: 5f 69 6e 69 + 144: 74 5f + 146: 61 72 + 148: 72 61 + 14a: 79 5f + 14c: 73 74 61 72 csrrci s0, 1830, 2 + 150: 74 00 + 152: 5f 5f 70 72 + 156: 65 69 + 158: 6e 69 + 15a: 74 5f + 15c: 61 72 + 15e: 72 61 + 160: 79 5f + 162: 73 74 61 72 csrrci s0, 1830, 2 + 166: 74 00 + 168: 5f 5f 73 74 + 16c: 61 63 + 16e: 6b 5f 75 73 + 172: 61 67 + 174: 65 00 + 176: 5f 5f 73 74 + 17a: 61 63 + 17c: 6b 5f 73 69 + 180: 7a 65 + 182: 00 67 + 184: 5f 77 73 70 + 188: 61 77 + 18a: 6e 5f + 18c: 61 72 + 18e: 67 73 00 5f + 192: 5f 53 44 41 + 196: 54 41 + 198: 5f 42 45 47 + 19c: 49 4e + 19e: 5f 5f 00 5f + 1a2: 70 6f + 1a4: 63 6c 5f 6b bltu t5, s5, 1720 + 1a8: 65 72 + 1aa: 6e 65 + 1ac: 6c 5f + 1ae: 46 61 + 1b0: 6e 31 + 1b2: 5f 77 6f 72 + 1b6: 6b 67 72 6f + 1ba: 75 70 + 1bc: 00 5f + 1be: 5f 67 6c 6f + 1c2: 62 61 + 1c4: 6c 5f + 1c6: 70 6f + 1c8: 69 6e + 1ca: 74 65 + 1cc: 72 00 + 1ce: 5f 67 6c 6f + 1d2: 62 61 + 1d4: 6c 5f + 1d6: 69 6d + 1d8: 70 75 + 1da: 72 65 + 1dc: 5f 70 74 72 + 1e0: 00 5f + 1e2: 5f 6c 69 62 + 1e6: 63 5f 69 6e bge s2, t1, 1790 + 1ea: 69 74 + 1ec: 5f 61 72 72 + 1f0: 61 79 + 1f2: 00 5f + 1f4: 5f 6c 69 62 + 1f8: 63 5f 66 69 bge a2, s6, 1694 + 1fc: 6e 69 + 1fe: 5f 61 72 72 + 202: 61 79 + 204: 00 5f + 206: 70 6f + 208: 63 6c 5f 6b bltu t5, s5, 1720 20c: 65 72 - 20e: 5f 65 78 69 - 212: 74 70 - 214: 72 6f - 216: 63 00 5f 5f beq t5, s5, 1504 - 21a: 42 53 - 21c: 53 5f 45 4e - 220: 44 5f - 222: 5f 00 5f 5f - 226: 62 73 - 228: 73 5f 73 74 csrrwi t5, 1863, 6 - 22c: 61 72 - 22e: 74 00 - 230: 6d 65 - 232: 6d 73 - 234: 65 74 - 236: 00 6d - 238: 61 69 - 23a: 6e 00 - 23c: 61 74 - 23e: 65 78 - 240: 69 74 - 242: 00 5f - 244: 5f 44 41 54 - 248: 41 5f - 24a: 42 45 - 24c: 47 49 4e 5f - 250: 5f 00 5f 70 - 254: 6f 63 6c 5f jal t1, 812534 - 258: 6b 65 72 6e - 25c: 65 6c - 25e: 5f 46 61 6e - 262: 31 5f - 264: 77 6f 72 6b - 268: 67 72 6f 75 - 26c: 70 5f - 26e: 66 61 - 270: 73 74 00 5f csrrci s0, 1520, 0 - 274: 65 64 - 276: 61 74 - 278: 61 00 - 27a: 76 78 - 27c: 5f 70 65 72 - 280: 66 5f - 282: 64 75 - 284: 6d 70 - 286: 00 5f - 288: 65 78 - 28a: 69 74 - 28c: 00 76 - 28e: 78 5f - 290: 73 70 61 77 csrci 1910, 2 - 294: 6e 5f - 296: 6b 65 72 6e - 29a: 65 6c - 29c: 00 + 20e: 6e 65 + 210: 6c 5f + 212: 46 61 + 214: 6e 31 + 216: 00 76 + 218: 78 5f + 21a: 73 65 74 5f csrrsi a0, 1527, 8 + 21e: 73 70 00 5f csrci 1520, 0 + 222: 5f 63 61 6c + 226: 6c 5f + 228: 65 78 + 22a: 69 74 + 22c: 70 72 + 22e: 6f 63 73 00 jal t1, 223238 + 232: 5f 5f 72 65 + 236: 67 69 73 74 + 23a: 65 72 + 23c: 5f 65 78 69 + 240: 74 70 + 242: 72 6f + 244: 63 00 5f 5f beq t5, s5, 1504 + 248: 42 53 + 24a: 53 5f 45 4e + 24e: 44 5f + 250: 5f 00 5f 5f + 254: 62 73 + 256: 73 5f 73 74 csrrwi t5, 1863, 6 + 25a: 61 72 + 25c: 74 00 + 25e: 6d 65 + 260: 6d 73 + 262: 65 74 + 264: 00 6d + 266: 61 69 + 268: 6e 00 + 26a: 61 74 + 26c: 65 78 + 26e: 69 74 + 270: 00 5f + 272: 5f 44 41 54 + 276: 41 5f + 278: 42 45 + 27a: 47 49 4e 5f + 27e: 5f 00 5f 70 + 282: 6f 63 6c 5f jal t1, 812534 + 286: 6b 65 72 6e + 28a: 65 6c + 28c: 5f 46 61 6e + 290: 31 5f + 292: 77 6f 72 6b + 296: 67 72 6f 75 + 29a: 70 5f + 29c: 66 61 + 29e: 73 74 00 5f csrrci s0, 1520, 0 + 2a2: 65 64 + 2a4: 61 74 + 2a6: 61 00 + 2a8: 76 78 + 2aa: 5f 70 65 72 + 2ae: 66 5f + 2b0: 64 75 + 2b2: 6d 70 + 2b4: 00 5f + 2b6: 65 78 + 2b8: 69 74 + 2ba: 00 76 + 2bc: 78 5f + 2be: 73 70 61 77 csrci 1910, 2 + 2c2: 6e 5f + 2c4: 6b 65 72 6e + 2c8: 65 6c + 2ca: 00 Disassembly of section .shstrtab: diff --git a/tests/opencl/guassian/Fan2.dump b/tests/opencl/guassian/Fan2.dump index cf530fe8..5ce592b8 100644 --- a/tests/opencl/guassian/Fan2.dump +++ b/tests/opencl/guassian/Fan2.dump @@ -1,39 +1,39 @@ -/tmp/pocl_vortex_kernel-54-45-d2-99-6d.elf: file format ELF32-riscv +/tmp/pocl_vortex_kernel-46-fc-40-76-2a.elf: file format ELF32-riscv Disassembly of section .init: 80000000 _start: 80000000: 97 05 00 00 auipc a1, 0 -80000004: 93 85 45 67 addi a1, a1, 1652 +80000004: 93 85 85 6d addi a1, a1, 1752 80000008: 73 25 10 fc csrr a0, 4033 -8000000c: 6b 10 b5 00 -80000010: ef 00 40 66 jal 1636 +8000000c: 6b 10 b5 00 vx_wspawn a0, a1 +80000010: ef 00 80 6c jal 1736 80000014: 13 05 10 00 addi a0, zero, 1 -80000018: 6b 00 05 00 +80000018: 6b 00 05 00 vx_tmc a0 8000001c: 17 25 00 00 auipc a0, 2 -80000020: 13 05 85 42 addi a0, a0, 1064 +80000020: 13 05 05 4d addi a0, a0, 1232 80000024: 17 26 00 00 auipc a2, 2 -80000028: 13 06 06 4a addi a2, a2, 1184 +80000028: 13 06 86 54 addi a2, a2, 1352 8000002c: 33 06 a6 40 sub a2, a2, a0 80000030: 93 05 00 00 mv a1, zero -80000034: ef 00 50 54 jal 3396 -80000038: 17 15 00 00 auipc a0, 1 -8000003c: 13 05 85 c4 addi a0, a0, -952 -80000040: ef 00 90 3f jal 3064 -80000044: ef 00 90 49 jal 3224 +80000034: ef 00 d0 5e jal 3564 +80000038: 17 05 00 00 auipc a0, 0 +8000003c: 13 05 05 77 addi a0, a0, 1904 +80000040: ef 00 90 59 jal 3480 +80000044: ef 00 80 6c jal 1736 80000048: ef 00 00 02 jal 32 -8000004c: 6f 00 10 40 j 3072 +8000004c: 6f 00 10 5a j 3488 Disassembly of section .text: 80000050 register_fini: 80000050: 93 07 00 00 mv a5, zero 80000054: 63 88 07 00 beqz a5, 16 -80000058: 37 15 00 80 lui a0, 524289 -8000005c: 13 05 05 c8 addi a0, a0, -896 -80000060: 6f 00 90 3d j 3032 +80000058: 37 05 00 80 lui a0, 524288 +8000005c: 13 05 85 7a addi a0, a0, 1960 +80000060: 6f 00 90 57 j 3448 80000064: 67 80 00 00 ret 80000068 main: @@ -44,7 +44,7 @@ Disassembly of section .text: 80000078: 37 05 ff 7f lui a0, 524272 8000007c: 13 06 45 03 addi a2, a0, 52 80000080: 37 05 ff 7f lui a0, 524272 -80000084: ef 00 40 77 jal 1908 +80000084: ef 00 d0 18 jal 2444 80000088: 13 05 00 00 mv a0, zero 8000008c: 83 20 c1 00 lw ra, 12(sp) 80000090: 13 01 01 01 addi sp, sp, 16 @@ -176,943 +176,991 @@ Disassembly of section .text: 80000280: 67 80 00 00 ret 80000284 _pocl_kernel_Fan2_workgroup: -80000284: 13 01 01 fd addi sp, sp, -48 -80000288: 23 26 81 02 sw s0, 44(sp) -8000028c: 23 24 91 02 sw s1, 40(sp) -80000290: 23 22 21 03 sw s2, 36(sp) -80000294: 23 20 31 03 sw s3, 32(sp) -80000298: 23 2e 41 01 sw s4, 28(sp) -8000029c: 23 2c 51 01 sw s5, 24(sp) -800002a0: 23 2a 61 01 sw s6, 20(sp) -800002a4: 23 28 71 01 sw s7, 16(sp) -800002a8: 23 26 81 01 sw s8, 12(sp) -800002ac: 23 24 91 01 sw s9, 8(sp) -800002b0: 03 27 05 00 lw a4, 0(a0) -800002b4: 13 08 00 00 mv a6, zero -800002b8: 03 29 07 00 lw s2, 0(a4) -800002bc: 03 27 45 00 lw a4, 4(a0) -800002c0: 83 24 85 00 lw s1, 8(a0) -800002c4: 03 24 c5 00 lw s0, 12(a0) -800002c8: 03 25 05 01 lw a0, 16(a0) -800002cc: 83 28 07 00 lw a7, 0(a4) -800002d0: 83 a9 04 00 lw s3, 0(s1) -800002d4: 03 24 04 00 lw s0, 0(s0) -800002d8: 03 23 05 00 lw t1, 0(a0) -800002dc: 83 ac 85 01 lw s9, 24(a1) -800002e0: 03 ae c5 01 lw t3, 28(a1) -800002e4: 83 a2 05 02 lw t0, 32(a1) -800002e8: 03 a5 05 01 lw a0, 16(a1) -800002ec: 83 ae c5 00 lw t4, 12(a1) -800002f0: b3 85 cc 02 mul a1, s9, a2 -800002f4: b3 06 de 02 mul a3, t3, a3 -800002f8: 33 0f d5 00 add t5, a0, a3 -800002fc: 13 46 f3 ff not a2, t1 -80000300: 33 06 c4 00 add a2, s0, a2 -80000304: b3 0f 64 40 sub t6, s0, t1 -80000308: b3 03 83 02 mul t2, t1, s0 -8000030c: 93 14 23 00 slli s1, t1, 2 -80000310: 33 8a 99 00 add s4, s3, s1 -80000314: 33 05 65 00 add a0, a0, t1 -80000318: 33 05 d5 00 add a0, a0, a3 -8000031c: b3 86 6e 00 add a3, t4, t1 -80000320: b3 86 b6 00 add a3, a3, a1 -80000324: 93 86 16 00 addi a3, a3, 1 -80000328: b3 04 d4 02 mul s1, s0, a3 -8000032c: 33 05 95 00 add a0, a0, s1 -80000330: 93 17 25 00 slli a5, a0, 2 -80000334: 33 85 be 00 add a0, t4, a1 -80000338: b3 8e f8 00 add t4, a7, a5 -8000033c: 93 15 24 00 slli a1, s0, 2 -80000340: 33 04 93 00 add s0, t1, s1 -80000344: 13 14 24 00 slli s0, s0, 2 -80000348: b3 0a 89 00 add s5, s2, s0 -8000034c: 93 96 26 00 slli a3, a3, 2 -80000350: b3 89 d9 00 add s3, s3, a3 -80000354: 33 09 f9 00 add s2, s2, a5 -80000358: 6f 00 c0 00 j 12 -8000035c: 13 08 18 00 addi a6, a6, 1 -80000360: 63 76 58 0e bgeu a6, t0, 236 -80000364: 13 0b 00 00 mv s6, zero -80000368: 93 0b 09 00 mv s7, s2 -8000036c: 93 87 0e 00 mv a5, t4 -80000370: 6f 00 40 01 j 20 -80000374: 13 0b 1b 00 addi s6, s6, 1 -80000378: 93 87 47 00 addi a5, a5, 4 -8000037c: 93 8b 4b 00 addi s7, s7, 4 -80000380: e3 7e cb fd bgeu s6, t3, -36 -80000384: b3 06 6f 01 add a3, t5, s6 -80000388: e3 d6 f6 ff bge a3, t6, -20 -8000038c: 33 84 66 00 add s0, a3, t1 -80000390: 33 04 74 00 add s0, s0, t2 -80000394: 13 14 24 00 slli s0, s0, 2 -80000398: 33 8c 88 00 add s8, a7, s0 -8000039c: 63 84 06 04 beqz a3, 72 -800003a0: 93 06 00 00 mv a3, zero -800003a4: 13 04 00 00 mv s0, zero -800003a8: 6f 00 00 01 j 16 -800003ac: 13 04 14 00 addi s0, s0, 1 -800003b0: b3 86 b6 00 add a3, a3, a1 -800003b4: e3 70 94 fd bgeu s0, s9, -64 -800003b8: 33 07 85 00 add a4, a0, s0 -800003bc: e3 58 c7 fe bge a4, a2, -16 -800003c0: 33 87 da 00 add a4, s5, a3 -800003c4: 07 20 07 00 flw ft0, 0(a4) -800003c8: 87 20 0c 00 flw ft1, 0(s8) -800003cc: 33 87 d7 00 add a4, a5, a3 -800003d0: 07 21 07 00 flw ft2, 0(a4) -800003d4: 53 70 10 10 fmul.s ft0, ft0, ft1 -800003d8: 53 70 01 08 fsub.s ft0, ft2, ft0 -800003dc: 27 20 07 00 fsw ft0, 0(a4) -800003e0: 6f f0 df fc j -52 -800003e4: 93 04 00 00 mv s1, zero -800003e8: 13 04 00 00 mv s0, zero -800003ec: 93 86 09 00 mv a3, s3 -800003f0: 6f 00 40 01 j 20 -800003f4: 13 04 14 00 addi s0, s0, 1 -800003f8: 93 86 46 00 addi a3, a3, 4 -800003fc: b3 84 b4 00 add s1, s1, a1 -80000400: e3 7a 94 f7 bgeu s0, s9, -140 -80000404: 33 07 85 00 add a4, a0, s0 -80000408: e3 56 c7 fe bge a4, a2, -20 -8000040c: 33 87 9a 00 add a4, s5, s1 -80000410: 07 20 07 00 flw ft0, 0(a4) -80000414: 87 20 0c 00 flw ft1, 0(s8) -80000418: 33 87 97 00 add a4, a5, s1 -8000041c: 07 21 07 00 flw ft2, 0(a4) -80000420: 53 70 10 10 fmul.s ft0, ft0, ft1 -80000424: 53 70 01 08 fsub.s ft0, ft2, ft0 -80000428: 27 20 07 00 fsw ft0, 0(a4) -8000042c: 33 87 9b 00 add a4, s7, s1 -80000430: 07 20 07 00 flw ft0, 0(a4) -80000434: 87 20 0a 00 flw ft1, 0(s4) -80000438: 07 a1 06 00 flw ft2, 0(a3) -8000043c: 53 70 10 10 fmul.s ft0, ft0, ft1 -80000440: 53 70 01 08 fsub.s ft0, ft2, ft0 -80000444: 27 a0 06 00 fsw ft0, 0(a3) -80000448: 6f f0 df fa j -84 -8000044c: 83 2c 81 00 lw s9, 8(sp) -80000450: 03 2c c1 00 lw s8, 12(sp) -80000454: 83 2b 01 01 lw s7, 16(sp) -80000458: 03 2b 41 01 lw s6, 20(sp) -8000045c: 83 2a 81 01 lw s5, 24(sp) -80000460: 03 2a c1 01 lw s4, 28(sp) -80000464: 83 29 01 02 lw s3, 32(sp) -80000468: 03 29 41 02 lw s2, 36(sp) -8000046c: 83 24 81 02 lw s1, 40(sp) -80000470: 03 24 c1 02 lw s0, 44(sp) -80000474: 13 01 01 03 addi sp, sp, 48 -80000478: 67 80 00 00 ret +80000284: 13 01 01 fc addi sp, sp, -64 +80000288: 23 2e 11 02 sw ra, 60(sp) +8000028c: 23 2c 81 02 sw s0, 56(sp) +80000290: 23 2a 91 02 sw s1, 52(sp) +80000294: 23 28 21 03 sw s2, 48(sp) +80000298: 23 26 31 03 sw s3, 44(sp) +8000029c: 23 24 41 03 sw s4, 40(sp) +800002a0: 23 22 51 03 sw s5, 36(sp) +800002a4: 23 20 61 03 sw s6, 32(sp) +800002a8: 23 2e 71 01 sw s7, 28(sp) +800002ac: 23 2c 81 01 sw s8, 24(sp) +800002b0: 23 2a 91 01 sw s9, 20(sp) +800002b4: 23 28 a1 01 sw s10, 16(sp) +800002b8: 23 26 b1 01 sw s11, 12(sp) +800002bc: 03 27 05 00 lw a4, 0(a0) +800002c0: 13 08 00 00 mv a6, zero +800002c4: 03 29 07 00 lw s2, 0(a4) +800002c8: 03 27 45 00 lw a4, 4(a0) +800002cc: 83 24 85 00 lw s1, 8(a0) +800002d0: 03 24 c5 00 lw s0, 12(a0) +800002d4: 03 25 05 01 lw a0, 16(a0) +800002d8: 83 28 07 00 lw a7, 0(a4) +800002dc: 83 a9 04 00 lw s3, 0(s1) +800002e0: 03 24 04 00 lw s0, 0(s0) +800002e4: 03 23 05 00 lw t1, 0(a0) +800002e8: 83 ad 85 01 lw s11, 24(a1) +800002ec: 03 ae c5 01 lw t3, 28(a1) +800002f0: 83 a2 05 02 lw t0, 32(a1) +800002f4: 03 a5 05 01 lw a0, 16(a1) +800002f8: 83 ae c5 00 lw t4, 12(a1) +800002fc: b3 85 cd 02 mul a1, s11, a2 +80000300: b3 06 de 02 mul a3, t3, a3 +80000304: 33 0f d5 00 add t5, a0, a3 +80000308: 13 46 f3 ff not a2, t1 +8000030c: 33 06 c4 00 add a2, s0, a2 +80000310: b3 0f 64 40 sub t6, s0, t1 +80000314: b3 03 83 02 mul t2, t1, s0 +80000318: 93 14 23 00 slli s1, t1, 2 +8000031c: b3 8a 99 00 add s5, s3, s1 +80000320: 33 05 65 00 add a0, a0, t1 +80000324: 33 05 d5 00 add a0, a0, a3 +80000328: b3 86 6e 00 add a3, t4, t1 +8000032c: b3 86 b6 00 add a3, a3, a1 +80000330: 93 86 16 00 addi a3, a3, 1 +80000334: b3 04 d4 02 mul s1, s0, a3 +80000338: 33 05 95 00 add a0, a0, s1 +8000033c: 93 17 25 00 slli a5, a0, 2 +80000340: b3 80 be 00 add ra, t4, a1 +80000344: b3 8e f8 00 add t4, a7, a5 +80000348: 93 15 24 00 slli a1, s0, 2 +8000034c: 33 04 93 00 add s0, t1, s1 +80000350: 13 14 24 00 slli s0, s0, 2 +80000354: 33 0b 89 00 add s6, s2, s0 +80000358: 93 96 26 00 slli a3, a3, 2 +8000035c: 33 8a d9 00 add s4, s3, a3 +80000360: 33 09 f9 00 add s2, s2, a5 +80000364: 6f 00 00 01 j 16 +80000368: 6b 80 09 00 vx_tmc s3 +8000036c: 13 08 18 00 addi a6, a6, 1 +80000370: 63 74 58 12 bgeu a6, t0, 296 +80000374: 93 0b 00 00 mv s7, zero +80000378: f3 29 40 cc csrr s3, tmask +8000037c: 93 0c 09 00 mv s9, s2 +80000380: 93 87 0e 00 mv a5, t4 +80000384: 6f 00 c0 01 j 28 +80000388: 6b 80 06 00 vx_tmc a3 +8000038c: 6b 30 00 00 vx_join +80000390: 93 8b 1b 00 addi s7, s7, 1 +80000394: 93 87 47 00 addi a5, a5, 4 +80000398: 93 8c 4c 00 addi s9, s9, 4 +8000039c: e3 f6 cb fd bgeu s7, t3, -52 +800003a0: b3 06 7f 01 add a3, t5, s7 +800003a4: 33 a4 f6 01 slt s0, a3, t6 +800003a8: 6b 20 04 00 vx_split s0 +800003ac: e3 d0 f6 ff bge a3, t6, -32 +800003b0: 33 84 66 00 add s0, a3, t1 +800003b4: 33 04 74 00 add s0, s0, t2 +800003b8: 13 14 24 00 slli s0, s0, 2 +800003bc: 33 8d 88 00 add s10, a7, s0 +800003c0: 63 8c 06 04 beqz a3, 88 +800003c4: 13 04 00 00 mv s0, zero +800003c8: 93 04 00 00 mv s1, zero +800003cc: f3 26 40 cc csrr a3, tmask +800003d0: 6f 00 40 01 j 20 +800003d4: 6b 30 00 00 vx_join +800003d8: 93 84 14 00 addi s1, s1, 1 +800003dc: 33 04 b4 00 add s0, s0, a1 +800003e0: e3 f4 b4 fb bgeu s1, s11, -88 +800003e4: 33 85 90 00 add a0, ra, s1 +800003e8: 33 27 c5 00 slt a4, a0, a2 +800003ec: 6b 20 07 00 vx_split a4 +800003f0: e3 52 c5 fe bge a0, a2, -28 +800003f4: 33 05 8b 00 add a0, s6, s0 +800003f8: 07 20 05 00 flw ft0, 0(a0) +800003fc: 87 20 0d 00 flw ft1, 0(s10) +80000400: 33 85 87 00 add a0, a5, s0 +80000404: 07 21 05 00 flw ft2, 0(a0) +80000408: 53 70 10 10 fmul.s ft0, ft0, ft1 +8000040c: 53 70 01 08 fsub.s ft0, ft2, ft0 +80000410: 27 20 05 00 fsw ft0, 0(a0) +80000414: 6f f0 1f fc j -64 +80000418: 93 04 00 00 mv s1, zero +8000041c: 13 04 00 00 mv s0, zero +80000420: 73 2c 40 cc csrr s8, tmask +80000424: 93 06 0a 00 mv a3, s4 +80000428: 6f 00 80 01 j 24 +8000042c: 6b 30 00 00 vx_join +80000430: 13 04 14 00 addi s0, s0, 1 +80000434: 93 86 46 00 addi a3, a3, 4 +80000438: b3 84 b4 00 add s1, s1, a1 +8000043c: 63 7a b4 05 bgeu s0, s11, 84 +80000440: 33 87 80 00 add a4, ra, s0 +80000444: 33 25 c7 00 slt a0, a4, a2 +80000448: 6b 20 05 00 vx_split a0 +8000044c: e3 50 c7 fe bge a4, a2, -32 +80000450: 33 05 9b 00 add a0, s6, s1 +80000454: 07 20 05 00 flw ft0, 0(a0) +80000458: 87 20 0d 00 flw ft1, 0(s10) +8000045c: 33 85 97 00 add a0, a5, s1 +80000460: 07 21 05 00 flw ft2, 0(a0) +80000464: 53 70 10 10 fmul.s ft0, ft0, ft1 +80000468: 53 70 01 08 fsub.s ft0, ft2, ft0 +8000046c: 27 20 05 00 fsw ft0, 0(a0) +80000470: 33 85 9c 00 add a0, s9, s1 +80000474: 07 20 05 00 flw ft0, 0(a0) +80000478: 87 a0 0a 00 flw ft1, 0(s5) +8000047c: 07 a1 06 00 flw ft2, 0(a3) +80000480: 53 70 10 10 fmul.s ft0, ft0, ft1 +80000484: 53 70 01 08 fsub.s ft0, ft2, ft0 +80000488: 27 a0 06 00 fsw ft0, 0(a3) +8000048c: 6f f0 1f fa j -96 +80000490: 6b 00 0c 00 vx_tmc s8 +80000494: 6f f0 9f ef j -264 +80000498: 83 2d c1 00 lw s11, 12(sp) +8000049c: 03 2d 01 01 lw s10, 16(sp) +800004a0: 83 2c 41 01 lw s9, 20(sp) +800004a4: 03 2c 81 01 lw s8, 24(sp) +800004a8: 83 2b c1 01 lw s7, 28(sp) +800004ac: 03 2b 01 02 lw s6, 32(sp) +800004b0: 83 2a 41 02 lw s5, 36(sp) +800004b4: 03 2a 81 02 lw s4, 40(sp) +800004b8: 83 29 c1 02 lw s3, 44(sp) +800004bc: 03 29 01 03 lw s2, 48(sp) +800004c0: 83 24 41 03 lw s1, 52(sp) +800004c4: 03 24 81 03 lw s0, 56(sp) +800004c8: 83 20 c1 03 lw ra, 60(sp) +800004cc: 13 01 01 04 addi sp, sp, 64 +800004d0: 67 80 00 00 ret -8000047c _pocl_kernel_Fan2_workgroup_fast: -8000047c: 13 01 01 fd addi sp, sp, -48 -80000480: 23 26 81 02 sw s0, 44(sp) -80000484: 23 24 91 02 sw s1, 40(sp) -80000488: 23 22 21 03 sw s2, 36(sp) -8000048c: 23 20 31 03 sw s3, 32(sp) -80000490: 23 2e 41 01 sw s4, 28(sp) -80000494: 23 2c 51 01 sw s5, 24(sp) -80000498: 23 2a 61 01 sw s6, 20(sp) -8000049c: 23 28 71 01 sw s7, 16(sp) -800004a0: 23 26 81 01 sw s8, 12(sp) -800004a4: 23 24 91 01 sw s9, 8(sp) -800004a8: 13 08 00 00 mv a6, zero -800004ac: 03 29 05 00 lw s2, 0(a0) -800004b0: 03 27 c5 00 lw a4, 12(a0) -800004b4: 83 27 05 01 lw a5, 16(a0) -800004b8: 83 28 45 00 lw a7, 4(a0) -800004bc: 83 29 85 00 lw s3, 8(a0) -800004c0: 83 24 07 00 lw s1, 0(a4) -800004c4: 03 a3 07 00 lw t1, 0(a5) -800004c8: 83 ac 85 01 lw s9, 24(a1) -800004cc: 03 ae c5 01 lw t3, 28(a1) -800004d0: 83 a2 05 02 lw t0, 32(a1) -800004d4: 83 a7 05 01 lw a5, 16(a1) -800004d8: 83 ae c5 00 lw t4, 12(a1) -800004dc: b3 85 cc 02 mul a1, s9, a2 -800004e0: b3 06 de 02 mul a3, t3, a3 -800004e4: 33 8f d7 00 add t5, a5, a3 -800004e8: 13 46 f3 ff not a2, t1 -800004ec: 33 86 c4 00 add a2, s1, a2 -800004f0: b3 8f 64 40 sub t6, s1, t1 -800004f4: b3 03 93 02 mul t2, t1, s1 -800004f8: 13 15 23 00 slli a0, t1, 2 -800004fc: 33 8a a9 00 add s4, s3, a0 -80000500: 33 85 67 00 add a0, a5, t1 -80000504: b3 07 d5 00 add a5, a0, a3 -80000508: b3 86 6e 00 add a3, t4, t1 -8000050c: b3 86 b6 00 add a3, a3, a1 -80000510: 93 86 16 00 addi a3, a3, 1 -80000514: 33 85 d4 02 mul a0, s1, a3 -80000518: b3 87 a7 00 add a5, a5, a0 -8000051c: 13 94 27 00 slli s0, a5, 2 -80000520: b3 87 be 00 add a5, t4, a1 -80000524: b3 8e 88 00 add t4, a7, s0 -80000528: 93 95 24 00 slli a1, s1, 2 -8000052c: 33 05 a3 00 add a0, t1, a0 -80000530: 13 15 25 00 slli a0, a0, 2 -80000534: b3 0a a9 00 add s5, s2, a0 -80000538: 13 95 26 00 slli a0, a3, 2 -8000053c: b3 89 a9 00 add s3, s3, a0 -80000540: 33 09 89 00 add s2, s2, s0 -80000544: 6f 00 c0 00 j 12 -80000548: 13 08 18 00 addi a6, a6, 1 -8000054c: 63 76 58 0e bgeu a6, t0, 236 -80000550: 13 0b 00 00 mv s6, zero -80000554: 93 0b 09 00 mv s7, s2 -80000558: 13 85 0e 00 mv a0, t4 -8000055c: 6f 00 40 01 j 20 -80000560: 13 0b 1b 00 addi s6, s6, 1 -80000564: 13 05 45 00 addi a0, a0, 4 -80000568: 93 8b 4b 00 addi s7, s7, 4 -8000056c: e3 7e cb fd bgeu s6, t3, -36 -80000570: b3 06 6f 01 add a3, t5, s6 -80000574: e3 d6 f6 ff bge a3, t6, -20 -80000578: 33 84 66 00 add s0, a3, t1 -8000057c: 33 04 74 00 add s0, s0, t2 -80000580: 13 14 24 00 slli s0, s0, 2 -80000584: 33 8c 88 00 add s8, a7, s0 -80000588: 63 84 06 04 beqz a3, 72 -8000058c: 93 06 00 00 mv a3, zero -80000590: 13 04 00 00 mv s0, zero -80000594: 6f 00 00 01 j 16 -80000598: 13 04 14 00 addi s0, s0, 1 -8000059c: b3 86 b6 00 add a3, a3, a1 -800005a0: e3 70 94 fd bgeu s0, s9, -64 -800005a4: 33 87 87 00 add a4, a5, s0 -800005a8: e3 58 c7 fe bge a4, a2, -16 -800005ac: 33 87 da 00 add a4, s5, a3 -800005b0: 07 20 07 00 flw ft0, 0(a4) -800005b4: 87 20 0c 00 flw ft1, 0(s8) -800005b8: 33 07 d5 00 add a4, a0, a3 -800005bc: 07 21 07 00 flw ft2, 0(a4) -800005c0: 53 70 10 10 fmul.s ft0, ft0, ft1 -800005c4: 53 70 01 08 fsub.s ft0, ft2, ft0 -800005c8: 27 20 07 00 fsw ft0, 0(a4) -800005cc: 6f f0 df fc j -52 -800005d0: 93 04 00 00 mv s1, zero -800005d4: 13 04 00 00 mv s0, zero -800005d8: 93 86 09 00 mv a3, s3 -800005dc: 6f 00 40 01 j 20 -800005e0: 13 04 14 00 addi s0, s0, 1 -800005e4: 93 86 46 00 addi a3, a3, 4 -800005e8: b3 84 b4 00 add s1, s1, a1 -800005ec: e3 7a 94 f7 bgeu s0, s9, -140 -800005f0: 33 87 87 00 add a4, a5, s0 -800005f4: e3 56 c7 fe bge a4, a2, -20 -800005f8: 33 87 9a 00 add a4, s5, s1 -800005fc: 07 20 07 00 flw ft0, 0(a4) -80000600: 87 20 0c 00 flw ft1, 0(s8) -80000604: 33 07 95 00 add a4, a0, s1 -80000608: 07 21 07 00 flw ft2, 0(a4) -8000060c: 53 70 10 10 fmul.s ft0, ft0, ft1 -80000610: 53 70 01 08 fsub.s ft0, ft2, ft0 -80000614: 27 20 07 00 fsw ft0, 0(a4) -80000618: 33 87 9b 00 add a4, s7, s1 -8000061c: 07 20 07 00 flw ft0, 0(a4) -80000620: 87 20 0a 00 flw ft1, 0(s4) -80000624: 07 a1 06 00 flw ft2, 0(a3) -80000628: 53 70 10 10 fmul.s ft0, ft0, ft1 -8000062c: 53 70 01 08 fsub.s ft0, ft2, ft0 -80000630: 27 a0 06 00 fsw ft0, 0(a3) -80000634: 6f f0 df fa j -84 -80000638: 83 2c 81 00 lw s9, 8(sp) -8000063c: 03 2c c1 00 lw s8, 12(sp) -80000640: 83 2b 01 01 lw s7, 16(sp) -80000644: 03 2b 41 01 lw s6, 20(sp) -80000648: 83 2a 81 01 lw s5, 24(sp) -8000064c: 03 2a c1 01 lw s4, 28(sp) -80000650: 83 29 01 02 lw s3, 32(sp) -80000654: 03 29 41 02 lw s2, 36(sp) -80000658: 83 24 81 02 lw s1, 40(sp) -8000065c: 03 24 c1 02 lw s0, 44(sp) -80000660: 13 01 01 03 addi sp, sp, 48 -80000664: 67 80 00 00 ret +800004d4 _pocl_kernel_Fan2_workgroup_fast: +800004d4: 13 01 01 fd addi sp, sp, -48 +800004d8: 23 26 81 02 sw s0, 44(sp) +800004dc: 23 24 91 02 sw s1, 40(sp) +800004e0: 23 22 21 03 sw s2, 36(sp) +800004e4: 23 20 31 03 sw s3, 32(sp) +800004e8: 23 2e 41 01 sw s4, 28(sp) +800004ec: 23 2c 51 01 sw s5, 24(sp) +800004f0: 23 2a 61 01 sw s6, 20(sp) +800004f4: 23 28 71 01 sw s7, 16(sp) +800004f8: 23 26 81 01 sw s8, 12(sp) +800004fc: 23 24 91 01 sw s9, 8(sp) +80000500: 13 08 00 00 mv a6, zero +80000504: 03 29 05 00 lw s2, 0(a0) +80000508: 03 27 c5 00 lw a4, 12(a0) +8000050c: 83 27 05 01 lw a5, 16(a0) +80000510: 83 28 45 00 lw a7, 4(a0) +80000514: 83 29 85 00 lw s3, 8(a0) +80000518: 83 24 07 00 lw s1, 0(a4) +8000051c: 03 a3 07 00 lw t1, 0(a5) +80000520: 83 ac 85 01 lw s9, 24(a1) +80000524: 03 ae c5 01 lw t3, 28(a1) +80000528: 83 a2 05 02 lw t0, 32(a1) +8000052c: 83 a7 05 01 lw a5, 16(a1) +80000530: 83 ae c5 00 lw t4, 12(a1) +80000534: b3 85 cc 02 mul a1, s9, a2 +80000538: b3 06 de 02 mul a3, t3, a3 +8000053c: 33 8f d7 00 add t5, a5, a3 +80000540: 13 46 f3 ff not a2, t1 +80000544: 33 86 c4 00 add a2, s1, a2 +80000548: b3 8f 64 40 sub t6, s1, t1 +8000054c: b3 03 93 02 mul t2, t1, s1 +80000550: 13 15 23 00 slli a0, t1, 2 +80000554: 33 8a a9 00 add s4, s3, a0 +80000558: 33 85 67 00 add a0, a5, t1 +8000055c: b3 07 d5 00 add a5, a0, a3 +80000560: b3 86 6e 00 add a3, t4, t1 +80000564: b3 86 b6 00 add a3, a3, a1 +80000568: 93 86 16 00 addi a3, a3, 1 +8000056c: 33 85 d4 02 mul a0, s1, a3 +80000570: b3 87 a7 00 add a5, a5, a0 +80000574: 13 94 27 00 slli s0, a5, 2 +80000578: b3 87 be 00 add a5, t4, a1 +8000057c: b3 8e 88 00 add t4, a7, s0 +80000580: 93 95 24 00 slli a1, s1, 2 +80000584: 33 05 a3 00 add a0, t1, a0 +80000588: 13 15 25 00 slli a0, a0, 2 +8000058c: b3 0a a9 00 add s5, s2, a0 +80000590: 13 95 26 00 slli a0, a3, 2 +80000594: b3 89 a9 00 add s3, s3, a0 +80000598: 33 09 89 00 add s2, s2, s0 +8000059c: 6f 00 c0 00 j 12 +800005a0: 13 08 18 00 addi a6, a6, 1 +800005a4: 63 76 58 0e bgeu a6, t0, 236 +800005a8: 13 0b 00 00 mv s6, zero +800005ac: 93 0b 09 00 mv s7, s2 +800005b0: 13 85 0e 00 mv a0, t4 +800005b4: 6f 00 40 01 j 20 +800005b8: 13 0b 1b 00 addi s6, s6, 1 +800005bc: 13 05 45 00 addi a0, a0, 4 +800005c0: 93 8b 4b 00 addi s7, s7, 4 +800005c4: e3 7e cb fd bgeu s6, t3, -36 +800005c8: b3 06 6f 01 add a3, t5, s6 +800005cc: e3 d6 f6 ff bge a3, t6, -20 +800005d0: 33 84 66 00 add s0, a3, t1 +800005d4: 33 04 74 00 add s0, s0, t2 +800005d8: 13 14 24 00 slli s0, s0, 2 +800005dc: 33 8c 88 00 add s8, a7, s0 +800005e0: 63 84 06 04 beqz a3, 72 +800005e4: 93 06 00 00 mv a3, zero +800005e8: 13 04 00 00 mv s0, zero +800005ec: 6f 00 00 01 j 16 +800005f0: 13 04 14 00 addi s0, s0, 1 +800005f4: b3 86 b6 00 add a3, a3, a1 +800005f8: e3 70 94 fd bgeu s0, s9, -64 +800005fc: 33 87 87 00 add a4, a5, s0 +80000600: e3 58 c7 fe bge a4, a2, -16 +80000604: 33 87 da 00 add a4, s5, a3 +80000608: 07 20 07 00 flw ft0, 0(a4) +8000060c: 87 20 0c 00 flw ft1, 0(s8) +80000610: 33 07 d5 00 add a4, a0, a3 +80000614: 07 21 07 00 flw ft2, 0(a4) +80000618: 53 70 10 10 fmul.s ft0, ft0, ft1 +8000061c: 53 70 01 08 fsub.s ft0, ft2, ft0 +80000620: 27 20 07 00 fsw ft0, 0(a4) +80000624: 6f f0 df fc j -52 +80000628: 93 04 00 00 mv s1, zero +8000062c: 13 04 00 00 mv s0, zero +80000630: 93 86 09 00 mv a3, s3 +80000634: 6f 00 40 01 j 20 +80000638: 13 04 14 00 addi s0, s0, 1 +8000063c: 93 86 46 00 addi a3, a3, 4 +80000640: b3 84 b4 00 add s1, s1, a1 +80000644: e3 7a 94 f7 bgeu s0, s9, -140 +80000648: 33 87 87 00 add a4, a5, s0 +8000064c: e3 56 c7 fe bge a4, a2, -20 +80000650: 33 87 9a 00 add a4, s5, s1 +80000654: 07 20 07 00 flw ft0, 0(a4) +80000658: 87 20 0c 00 flw ft1, 0(s8) +8000065c: 33 07 95 00 add a4, a0, s1 +80000660: 07 21 07 00 flw ft2, 0(a4) +80000664: 53 70 10 10 fmul.s ft0, ft0, ft1 +80000668: 53 70 01 08 fsub.s ft0, ft2, ft0 +8000066c: 27 20 07 00 fsw ft0, 0(a4) +80000670: 33 87 9b 00 add a4, s7, s1 +80000674: 07 20 07 00 flw ft0, 0(a4) +80000678: 87 20 0a 00 flw ft1, 0(s4) +8000067c: 07 a1 06 00 flw ft2, 0(a3) +80000680: 53 70 10 10 fmul.s ft0, ft0, ft1 +80000684: 53 70 01 08 fsub.s ft0, ft2, ft0 +80000688: 27 a0 06 00 fsw ft0, 0(a3) +8000068c: 6f f0 df fa j -84 +80000690: 83 2c 81 00 lw s9, 8(sp) +80000694: 03 2c c1 00 lw s8, 12(sp) +80000698: 83 2b 01 01 lw s7, 16(sp) +8000069c: 03 2b 41 01 lw s6, 20(sp) +800006a0: 83 2a 81 01 lw s5, 24(sp) +800006a4: 03 2a c1 01 lw s4, 28(sp) +800006a8: 83 29 01 02 lw s3, 32(sp) +800006ac: 03 29 41 02 lw s2, 36(sp) +800006b0: 83 24 81 02 lw s1, 40(sp) +800006b4: 03 24 c1 02 lw s0, 44(sp) +800006b8: 13 01 01 03 addi sp, sp, 48 +800006bc: 67 80 00 00 ret -80000668 _exit: -80000668: ef 00 c0 3b jal 956 -8000066c: 13 05 00 00 mv a0, zero -80000670: 6b 00 05 00 +800006c0 _exit: +800006c0: 63 06 05 00 beqz a0, 12 +800006c4: 93 01 05 00 mv gp, a0 +800006c8: 73 00 00 00 ecall -80000674 vx_set_sp: -80000674: 73 25 00 fc csrr a0, 4032 -80000678: 6b 00 05 00 -8000067c: 97 21 00 00 auipc gp, 2 -80000680: 93 81 c1 19 addi gp, gp, 412 -80000684: 17 01 00 7f auipc sp, 520192 -80000688: 13 01 c1 97 addi sp, sp, -1668 -8000068c: 93 05 00 40 addi a1, zero, 1024 -80000690: 73 26 10 cc csrr a2, 3265 -80000694: b3 85 c5 02 mul a1, a1, a2 -80000698: 33 01 b1 40 sub sp, sp, a1 -8000069c: f3 26 30 cc csrr a3, 3267 -800006a0: 63 86 06 00 beqz a3, 12 -800006a4: 13 05 00 00 mv a0, zero -800006a8: 6b 00 05 00 +800006cc label_exit_next: +800006cc: ef 00 80 4f jal 1272 +800006d0: 13 05 00 00 mv a0, zero +800006d4: 6b 00 05 00 vx_tmc a0 -800006ac RETURN: -800006ac: 67 80 00 00 ret +800006d8 vx_set_sp: +800006d8: 13 05 f0 ff addi a0, zero, -1 +800006dc: 6b 00 05 00 vx_tmc a0 +800006e0: 97 21 00 00 auipc gp, 2 +800006e4: 93 81 01 1e addi gp, gp, 480 +800006e8: 37 01 00 ff lui sp, 1044480 +800006ec: 73 26 10 cc csrr a2, 3265 +800006f0: 93 15 a6 00 slli a1, a2, 10 +800006f4: 33 01 b1 40 sub sp, sp, a1 +800006f8: f3 26 30 cc csrr a3, 3267 +800006fc: 63 86 06 00 beqz a3, 12 +80000700: 13 05 00 00 mv a0, zero +80000704: 6b 00 05 00 vx_tmc a0 -800006b0 spawn_kernel_callback: -800006b0: 13 01 01 fe addi sp, sp, -32 -800006b4: 23 2e 11 00 sw ra, 28(sp) -800006b8: 23 2c 81 00 sw s0, 24(sp) -800006bc: 23 2a 91 00 sw s1, 20(sp) -800006c0: 23 28 21 01 sw s2, 16(sp) -800006c4: 23 26 31 01 sw s3, 12(sp) -800006c8: 23 24 41 01 sw s4, 8(sp) -800006cc: 23 22 51 01 sw s5, 4(sp) -800006d0: f3 27 00 fc csrr a5, 4032 -800006d4: 6b 80 07 00 -800006d8: f3 26 50 cc csrr a3, 3269 -800006dc: 73 29 30 cc csrr s2, 3267 -800006e0: 73 27 00 cc csrr a4, 3264 -800006e4: 73 26 00 fc csrr a2, 4032 -800006e8: b7 27 00 80 lui a5, 524290 -800006ec: 93 96 26 00 slli a3, a3, 2 -800006f0: 93 87 47 44 addi a5, a5, 1092 -800006f4: b3 87 d7 00 add a5, a5, a3 -800006f8: 03 a4 07 00 lw s0, 0(a5) -800006fc: 83 24 44 01 lw s1, 20(s0) -80000700: 83 26 04 01 lw a3, 16(s0) -80000704: b3 2a 99 00 slt s5, s2, s1 -80000708: 93 87 04 00 mv a5, s1 -8000070c: b3 8a da 00 add s5, s5, a3 -80000710: b3 84 26 03 mul s1, a3, s2 -80000714: 63 54 f9 00 bge s2, a5, 8 -80000718: 93 07 09 00 mv a5, s2 -8000071c: b3 84 f4 00 add s1, s1, a5 -80000720: 83 25 04 00 lw a1, 0(s0) -80000724: 83 26 c4 00 lw a3, 12(s0) -80000728: 83 a9 05 00 lw s3, 0(a1) -8000072c: 03 aa 45 00 lw s4, 4(a1) -80000730: b3 84 c4 02 mul s1, s1, a2 -80000734: b3 87 ea 02 mul a5, s5, a4 -80000738: b3 84 d4 00 add s1, s1, a3 -8000073c: b3 84 f4 00 add s1, s1, a5 -80000740: b3 8a 9a 00 add s5, s5, s1 -80000744: 33 8a 49 03 mul s4, s3, s4 -80000748: 63 c0 54 07 blt s1, s5, 96 -8000074c: 6f 00 00 08 j 128 -80000750: 03 47 a4 01 lbu a4, 26(s0) -80000754: 83 46 94 01 lbu a3, 25(s0) -80000758: 33 d7 e4 40 sra a4, s1, a4 -8000075c: b3 07 47 03 mul a5, a4, s4 -80000760: b3 87 f4 40 sub a5, s1, a5 -80000764: 63 80 06 06 beqz a3, 96 -80000768: 83 46 b4 01 lbu a3, 27(s0) -8000076c: b3 d6 d7 40 sra a3, a5, a3 -80000770: b3 88 36 03 mul a7, a3, s3 -80000774: 03 ae 45 01 lw t3, 20(a1) -80000778: 03 a3 05 01 lw t1, 16(a1) -8000077c: 03 a6 c5 00 lw a2, 12(a1) -80000780: 03 28 44 00 lw a6, 4(s0) -80000784: 03 25 84 00 lw a0, 8(s0) -80000788: 93 84 14 00 addi s1, s1, 1 -8000078c: 33 07 c7 01 add a4, a4, t3 -80000790: b3 86 66 00 add a3, a3, t1 -80000794: b3 87 17 41 sub a5, a5, a7 -80000798: 33 86 c7 00 add a2, a5, a2 -8000079c: e7 00 08 00 jalr a6 -800007a0: 63 86 9a 02 beq s5, s1, 44 -800007a4: 83 25 04 00 lw a1, 0(s0) -800007a8: 83 47 84 01 lbu a5, 24(s0) -800007ac: e3 92 07 fa bnez a5, -92 -800007b0: 33 c7 44 03 div a4, s1, s4 -800007b4: 83 46 94 01 lbu a3, 25(s0) -800007b8: b3 07 47 03 mul a5, a4, s4 -800007bc: b3 87 f4 40 sub a5, s1, a5 -800007c0: e3 94 06 fa bnez a3, -88 -800007c4: b3 c6 37 03 div a3, a5, s3 -800007c8: 6f f0 9f fa j -88 -800007cc: 13 39 19 00 seqz s2, s2 -800007d0: 6b 00 09 00 -800007d4: 83 20 c1 01 lw ra, 28(sp) -800007d8: 03 24 81 01 lw s0, 24(sp) -800007dc: 83 24 41 01 lw s1, 20(sp) -800007e0: 03 29 01 01 lw s2, 16(sp) -800007e4: 83 29 c1 00 lw s3, 12(sp) -800007e8: 03 2a 81 00 lw s4, 8(sp) -800007ec: 83 2a 41 00 lw s5, 4(sp) -800007f0: 13 01 01 02 addi sp, sp, 32 -800007f4: 67 80 00 00 ret +80000708 RETURN: +80000708: 67 80 00 00 ret -800007f8 vx_spawn_kernel: -800007f8: 13 01 01 fc addi sp, sp, -64 -800007fc: 23 2e 11 02 sw ra, 60(sp) -80000800: 23 2c 81 02 sw s0, 56(sp) -80000804: 23 2a 91 02 sw s1, 52(sp) -80000808: 23 28 21 03 sw s2, 48(sp) -8000080c: 23 26 31 03 sw s3, 44(sp) -80000810: f3 28 20 fc csrr a7, 4034 -80000814: 73 23 10 fc csrr t1, 4033 -80000818: 73 24 00 fc csrr s0, 4032 -8000081c: f3 27 50 cc csrr a5, 3269 -80000820: 13 07 f0 01 addi a4, zero, 31 -80000824: 63 46 f7 0e blt a4, a5, 236 -80000828: 03 2e 05 00 lw t3, 0(a0) -8000082c: 83 26 45 00 lw a3, 4(a0) -80000830: 03 28 85 00 lw a6, 8(a0) -80000834: b3 0e 83 02 mul t4, t1, s0 -80000838: 13 07 10 00 addi a4, zero, 1 -8000083c: b3 06 de 02 mul a3, t3, a3 -80000840: 33 88 06 03 mul a6, a3, a6 -80000844: 63 d4 0e 01 bge t4, a6, 8 -80000848: 33 47 d8 03 div a4, a6, t4 -8000084c: 63 c0 e8 0e blt a7, a4, 224 -80000850: 63 d0 e7 0c bge a5, a4, 192 -80000854: 93 88 f8 ff addi a7, a7, -1 -80000858: b3 4e e8 02 div t4, a6, a4 -8000085c: 93 84 0e 00 mv s1, t4 -80000860: 63 96 f8 00 bne a7, a5, 12 -80000864: 33 67 e8 02 rem a4, a6, a4 -80000868: b3 04 d7 01 add s1, a4, t4 -8000086c: 33 c9 84 02 div s2, s1, s0 -80000870: b3 e4 84 02 rem s1, s1, s0 -80000874: 63 42 69 0c blt s2, t1, 196 -80000878: 93 02 10 00 addi t0, zero, 1 -8000087c: 33 48 69 02 div a6, s2, t1 -80000880: 63 06 08 00 beqz a6, 12 -80000884: 93 02 08 00 mv t0, a6 -80000888: 33 68 69 02 rem a6, s2, t1 -8000088c: d3 f7 06 d0 fcvt.s.w fa5, a3 -80000890: 93 8f f6 ff addi t6, a3, -1 -80000894: 13 0f fe ff addi t5, t3, -1 -80000898: b7 29 00 80 lui s3, 524290 -8000089c: b3 f6 df 00 and a3, t6, a3 -800008a0: 93 89 49 44 addi s3, s3, 1092 -800008a4: 93 b6 16 00 seqz a3, a3 -800008a8: 23 22 a1 00 sw a0, 4(sp) -800008ac: 23 24 b1 00 sw a1, 8(sp) -800008b0: 23 26 c1 00 sw a2, 12(sp) -800008b4: 23 2a 51 00 sw t0, 20(sp) -800008b8: 23 2c 01 01 sw a6, 24(sp) -800008bc: 23 0e d1 00 sb a3, 28(sp) -800008c0: 33 87 fe 02 mul a4, t4, a5 -800008c4: d3 8e 07 e0 fmv.x.w t4, fa5 -800008c8: d3 77 0e d0 fcvt.s.w fa5, t3 -800008cc: 93 97 27 00 slli a5, a5, 2 -800008d0: 33 7e cf 01 and t3, t5, t3 -800008d4: d3 88 07 e0 fmv.x.w a7, fa5 -800008d8: 93 de 7e 41 srai t4, t4, 23 -800008dc: 13 3e 1e 00 seqz t3, t3 -800008e0: 93 d8 78 41 srai a7, a7, 23 -800008e4: 93 8e 1e f8 addi t4, t4, -127 -800008e8: 93 88 18 f8 addi a7, a7, -127 -800008ec: b3 87 f9 00 add a5, s3, a5 -800008f0: 23 28 e1 00 sw a4, 16(sp) -800008f4: 13 07 41 00 addi a4, sp, 4 -800008f8: a3 0e c1 01 sb t3, 29(sp) -800008fc: 23 0f d1 01 sb t4, 30(sp) -80000900: a3 0f 11 01 sb a7, 31(sp) -80000904: 23 a0 e7 00 sw a4, 0(a5) -80000908: 63 4e 20 03 bgtz s2, 60 -8000090c: 63 9c 04 04 bnez s1, 88 -80000910: 83 20 c1 03 lw ra, 60(sp) -80000914: 03 24 81 03 lw s0, 56(sp) -80000918: 83 24 41 03 lw s1, 52(sp) -8000091c: 03 29 01 03 lw s2, 48(sp) -80000920: 83 29 c1 02 lw s3, 44(sp) -80000924: 13 01 01 04 addi sp, sp, 64 -80000928: 67 80 00 00 ret -8000092c: 13 87 08 00 mv a4, a7 -80000930: e3 c2 e7 f2 blt a5, a4, -220 -80000934: 6f f0 df fd j -36 -80000938: 13 08 00 00 mv a6, zero -8000093c: 93 02 10 00 addi t0, zero, 1 -80000940: 6f f0 df f4 j -180 -80000944: 13 07 09 00 mv a4, s2 -80000948: 63 54 23 01 bge t1, s2, 8 -8000094c: 13 07 03 00 mv a4, t1 -80000950: b7 07 00 80 lui a5, 524288 -80000954: 93 87 07 6b addi a5, a5, 1712 -80000958: 6b 10 f7 00 -8000095c: ef f0 5f d5 jal -684 -80000960: e3 88 04 fa beqz s1, -80 -80000964: 33 04 89 02 mul s0, s2, s0 -80000968: 23 28 81 00 sw s0, 16(sp) -8000096c: 6b 80 04 00 -80000970: 73 27 50 cc csrr a4, 3269 -80000974: f3 27 20 cc csrr a5, 3266 -80000978: 13 17 27 00 slli a4, a4, 2 -8000097c: b3 89 e9 00 add s3, s3, a4 -80000980: 03 a5 09 00 lw a0, 0(s3) -80000984: 83 25 05 00 lw a1, 0(a0) -80000988: 83 26 c5 00 lw a3, 12(a0) -8000098c: 03 47 85 01 lbu a4, 24(a0) -80000990: 03 a8 05 00 lw a6, 0(a1) -80000994: 03 a6 45 00 lw a2, 4(a1) -80000998: b3 87 d7 00 add a5, a5, a3 -8000099c: 33 06 c8 02 mul a2, a6, a2 -800009a0: 63 0e 07 06 beqz a4, 124 -800009a4: 03 47 a5 01 lbu a4, 26(a0) -800009a8: 33 d7 e7 40 sra a4, a5, a4 -800009ac: 83 46 95 01 lbu a3, 25(a0) -800009b0: 33 06 e6 02 mul a2, a2, a4 -800009b4: b3 87 c7 40 sub a5, a5, a2 -800009b8: 63 8e 06 04 beqz a3, 92 -800009bc: 83 48 b5 01 lbu a7, 27(a0) -800009c0: b3 d8 17 41 sra a7, a5, a7 -800009c4: 33 08 18 03 mul a6, a6, a7 -800009c8: 03 ae 45 01 lw t3, 20(a1) -800009cc: 83 a6 05 01 lw a3, 16(a1) -800009d0: 03 a6 c5 00 lw a2, 12(a1) -800009d4: 03 23 45 00 lw t1, 4(a0) -800009d8: 03 25 85 00 lw a0, 8(a0) -800009dc: 33 07 c7 01 add a4, a4, t3 -800009e0: b3 86 d8 00 add a3, a7, a3 -800009e4: b3 87 07 41 sub a5, a5, a6 -800009e8: 33 86 c7 00 add a2, a5, a2 -800009ec: e7 00 03 00 jalr t1 -800009f0: 93 07 10 00 addi a5, zero, 1 -800009f4: 6b 80 07 00 -800009f8: 83 20 c1 03 lw ra, 60(sp) -800009fc: 03 24 81 03 lw s0, 56(sp) -80000a00: 83 24 41 03 lw s1, 52(sp) -80000a04: 03 29 01 03 lw s2, 48(sp) -80000a08: 83 29 c1 02 lw s3, 44(sp) -80000a0c: 13 01 01 04 addi sp, sp, 64 -80000a10: 67 80 00 00 ret -80000a14: b3 c8 07 03 div a7, a5, a6 -80000a18: 6f f0 df fa j -84 -80000a1c: 33 c7 c7 02 div a4, a5, a2 -80000a20: 6f f0 df f8 j -116 +8000070c __libc_init_array: +8000070c: 13 01 01 ff addi sp, sp, -16 +80000710: 23 24 81 00 sw s0, 8(sp) +80000714: 23 20 21 01 sw s2, 0(sp) +80000718: 37 24 00 80 lui s0, 524290 +8000071c: 37 29 00 80 lui s2, 524290 +80000720: 93 07 c4 0b addi a5, s0, 188 +80000724: 13 09 c9 0b addi s2, s2, 188 +80000728: 33 09 f9 40 sub s2, s2, a5 +8000072c: 23 26 11 00 sw ra, 12(sp) +80000730: 23 22 91 00 sw s1, 4(sp) +80000734: 13 59 29 40 srai s2, s2, 2 +80000738: 63 00 09 02 beqz s2, 32 +8000073c: 13 04 c4 0b addi s0, s0, 188 +80000740: 93 04 00 00 mv s1, zero +80000744: 83 27 04 00 lw a5, 0(s0) +80000748: 93 84 14 00 addi s1, s1, 1 +8000074c: 13 04 44 00 addi s0, s0, 4 +80000750: e7 80 07 00 jalr a5 +80000754: e3 18 99 fe bne s2, s1, -16 +80000758: 37 24 00 80 lui s0, 524290 +8000075c: 37 29 00 80 lui s2, 524290 +80000760: 93 07 c4 0b addi a5, s0, 188 +80000764: 13 09 09 0c addi s2, s2, 192 +80000768: 33 09 f9 40 sub s2, s2, a5 +8000076c: 13 59 29 40 srai s2, s2, 2 +80000770: 63 00 09 02 beqz s2, 32 +80000774: 13 04 c4 0b addi s0, s0, 188 +80000778: 93 04 00 00 mv s1, zero +8000077c: 83 27 04 00 lw a5, 0(s0) +80000780: 93 84 14 00 addi s1, s1, 1 +80000784: 13 04 44 00 addi s0, s0, 4 +80000788: e7 80 07 00 jalr a5 +8000078c: e3 18 99 fe bne s2, s1, -16 +80000790: 83 20 c1 00 lw ra, 12(sp) +80000794: 03 24 81 00 lw s0, 8(sp) +80000798: 83 24 41 00 lw s1, 4(sp) +8000079c: 03 29 01 00 lw s2, 0(sp) +800007a0: 13 01 01 01 addi sp, sp, 16 +800007a4: 67 80 00 00 ret -80000a24 vx_perf_dump: -80000a24: f3 27 50 cc csrr a5, 3269 -80000a28: 37 07 ff 00 lui a4, 4080 -80000a2c: b3 87 e7 00 add a5, a5, a4 -80000a30: 93 97 87 00 slli a5, a5, 8 -80000a34: 73 27 00 b0 csrr a4, mcycle -80000a38: 23 a0 e7 00 sw a4, 0(a5) -80000a3c: 73 27 10 b0 csrr a4, 2817 -80000a40: 23 a2 e7 00 sw a4, 4(a5) -80000a44: 73 27 20 b0 csrr a4, minstret -80000a48: 23 a4 e7 00 sw a4, 8(a5) -80000a4c: 73 27 30 b0 csrr a4, mhpmcounter3 -80000a50: 23 a6 e7 00 sw a4, 12(a5) -80000a54: 73 27 40 b0 csrr a4, mhpmcounter4 -80000a58: 23 a8 e7 00 sw a4, 16(a5) -80000a5c: 73 27 50 b0 csrr a4, mhpmcounter5 -80000a60: 23 aa e7 00 sw a4, 20(a5) -80000a64: 73 27 60 b0 csrr a4, mhpmcounter6 -80000a68: 23 ac e7 00 sw a4, 24(a5) -80000a6c: 73 27 70 b0 csrr a4, mhpmcounter7 -80000a70: 23 ae e7 00 sw a4, 28(a5) -80000a74: 73 27 80 b0 csrr a4, mhpmcounter8 -80000a78: 23 a0 e7 02 sw a4, 32(a5) -80000a7c: 73 27 90 b0 csrr a4, mhpmcounter9 -80000a80: 23 a2 e7 02 sw a4, 36(a5) -80000a84: 73 27 a0 b0 csrr a4, mhpmcounter10 -80000a88: 23 a4 e7 02 sw a4, 40(a5) -80000a8c: 73 27 b0 b0 csrr a4, mhpmcounter11 -80000a90: 23 a6 e7 02 sw a4, 44(a5) -80000a94: 73 27 c0 b0 csrr a4, mhpmcounter12 -80000a98: 23 a8 e7 02 sw a4, 48(a5) -80000a9c: 73 27 d0 b0 csrr a4, mhpmcounter13 -80000aa0: 23 aa e7 02 sw a4, 52(a5) -80000aa4: 73 27 e0 b0 csrr a4, mhpmcounter14 -80000aa8: 23 ac e7 02 sw a4, 56(a5) -80000aac: 73 27 f0 b0 csrr a4, mhpmcounter15 -80000ab0: 23 ae e7 02 sw a4, 60(a5) -80000ab4: 73 27 00 b1 csrr a4, mhpmcounter16 -80000ab8: 23 a0 e7 04 sw a4, 64(a5) -80000abc: 73 27 10 b1 csrr a4, mhpmcounter17 -80000ac0: 23 a2 e7 04 sw a4, 68(a5) -80000ac4: 73 27 20 b1 csrr a4, mhpmcounter18 -80000ac8: 23 a4 e7 04 sw a4, 72(a5) -80000acc: 73 27 30 b1 csrr a4, mhpmcounter19 -80000ad0: 23 a6 e7 04 sw a4, 76(a5) -80000ad4: 73 27 40 b1 csrr a4, mhpmcounter20 -80000ad8: 23 a8 e7 04 sw a4, 80(a5) -80000adc: 73 27 50 b1 csrr a4, mhpmcounter21 -80000ae0: 23 aa e7 04 sw a4, 84(a5) -80000ae4: 73 27 60 b1 csrr a4, mhpmcounter22 -80000ae8: 23 ac e7 04 sw a4, 88(a5) -80000aec: 73 27 70 b1 csrr a4, mhpmcounter23 -80000af0: 23 ae e7 04 sw a4, 92(a5) -80000af4: 73 27 80 b1 csrr a4, mhpmcounter24 -80000af8: 23 a0 e7 06 sw a4, 96(a5) -80000afc: 73 27 90 b1 csrr a4, mhpmcounter25 -80000b00: 23 a2 e7 06 sw a4, 100(a5) -80000b04: 73 27 a0 b1 csrr a4, mhpmcounter26 -80000b08: 23 a4 e7 06 sw a4, 104(a5) -80000b0c: 73 27 b0 b1 csrr a4, mhpmcounter27 -80000b10: 23 a6 e7 06 sw a4, 108(a5) -80000b14: 73 27 c0 b1 csrr a4, mhpmcounter28 -80000b18: 23 a8 e7 06 sw a4, 112(a5) -80000b1c: 73 27 d0 b1 csrr a4, mhpmcounter29 -80000b20: 23 aa e7 06 sw a4, 116(a5) -80000b24: 73 27 e0 b1 csrr a4, mhpmcounter30 -80000b28: 23 ac e7 06 sw a4, 120(a5) -80000b2c: 73 27 f0 b1 csrr a4, mhpmcounter31 -80000b30: 23 ae e7 06 sw a4, 124(a5) -80000b34: 73 27 00 b8 csrr a4, mcycleh -80000b38: 23 a0 e7 08 sw a4, 128(a5) -80000b3c: 73 27 10 b8 csrr a4, 2945 -80000b40: 23 a2 e7 08 sw a4, 132(a5) -80000b44: 73 27 20 b8 csrr a4, minstreth -80000b48: 23 a4 e7 08 sw a4, 136(a5) -80000b4c: 73 27 30 b8 csrr a4, mhpmcounter3h -80000b50: 23 a6 e7 08 sw a4, 140(a5) -80000b54: 73 27 40 b8 csrr a4, mhpmcounter4h -80000b58: 23 a8 e7 08 sw a4, 144(a5) -80000b5c: 73 27 50 b8 csrr a4, mhpmcounter5h -80000b60: 23 aa e7 08 sw a4, 148(a5) -80000b64: 73 27 60 b8 csrr a4, mhpmcounter6h -80000b68: 23 ac e7 08 sw a4, 152(a5) -80000b6c: 73 27 70 b8 csrr a4, mhpmcounter7h -80000b70: 23 ae e7 08 sw a4, 156(a5) -80000b74: 73 27 80 b8 csrr a4, mhpmcounter8h -80000b78: 23 a0 e7 0a sw a4, 160(a5) -80000b7c: 73 27 90 b8 csrr a4, mhpmcounter9h -80000b80: 23 a2 e7 0a sw a4, 164(a5) -80000b84: 73 27 a0 b8 csrr a4, mhpmcounter10h -80000b88: 23 a4 e7 0a sw a4, 168(a5) -80000b8c: 73 27 b0 b8 csrr a4, mhpmcounter11h -80000b90: 23 a6 e7 0a sw a4, 172(a5) -80000b94: 73 27 c0 b8 csrr a4, mhpmcounter12h -80000b98: 23 a8 e7 0a sw a4, 176(a5) -80000b9c: 73 27 d0 b8 csrr a4, mhpmcounter13h -80000ba0: 23 aa e7 0a sw a4, 180(a5) -80000ba4: 73 27 e0 b8 csrr a4, mhpmcounter14h -80000ba8: 23 ac e7 0a sw a4, 184(a5) -80000bac: 73 27 f0 b8 csrr a4, mhpmcounter15h -80000bb0: 23 ae e7 0a sw a4, 188(a5) -80000bb4: 73 27 00 b9 csrr a4, mhpmcounter16h -80000bb8: 23 a0 e7 0c sw a4, 192(a5) -80000bbc: 73 27 10 b9 csrr a4, mhpmcounter17h -80000bc0: 23 a2 e7 0c sw a4, 196(a5) -80000bc4: 73 27 20 b9 csrr a4, mhpmcounter18h -80000bc8: 23 a4 e7 0c sw a4, 200(a5) -80000bcc: 73 27 30 b9 csrr a4, mhpmcounter19h -80000bd0: 23 a6 e7 0c sw a4, 204(a5) -80000bd4: 73 27 40 b9 csrr a4, mhpmcounter20h -80000bd8: 23 a8 e7 0c sw a4, 208(a5) -80000bdc: 73 27 50 b9 csrr a4, mhpmcounter21h -80000be0: 23 aa e7 0c sw a4, 212(a5) -80000be4: 73 27 60 b9 csrr a4, mhpmcounter22h -80000be8: 23 ac e7 0c sw a4, 216(a5) -80000bec: 73 27 70 b9 csrr a4, mhpmcounter23h -80000bf0: 23 ae e7 0c sw a4, 220(a5) -80000bf4: 73 27 80 b9 csrr a4, mhpmcounter24h -80000bf8: 23 a0 e7 0e sw a4, 224(a5) -80000bfc: 73 27 90 b9 csrr a4, mhpmcounter25h -80000c00: 23 a2 e7 0e sw a4, 228(a5) -80000c04: 73 27 a0 b9 csrr a4, mhpmcounter26h -80000c08: 23 a4 e7 0e sw a4, 232(a5) -80000c0c: 73 27 b0 b9 csrr a4, mhpmcounter27h -80000c10: 23 a6 e7 0e sw a4, 236(a5) -80000c14: 73 27 c0 b9 csrr a4, mhpmcounter28h -80000c18: 23 a8 e7 0e sw a4, 240(a5) -80000c1c: 73 27 d0 b9 csrr a4, mhpmcounter29h -80000c20: 23 aa e7 0e sw a4, 244(a5) -80000c24: 73 27 e0 b9 csrr a4, mhpmcounter30h -80000c28: 23 ac e7 0e sw a4, 248(a5) -80000c2c: 73 27 f0 b9 csrr a4, mhpmcounter31h -80000c30: 23 ae e7 0e sw a4, 252(a5) -80000c34: 67 80 00 00 ret +800007a8 __libc_fini_array: +800007a8: 13 01 01 ff addi sp, sp, -16 +800007ac: 23 24 81 00 sw s0, 8(sp) +800007b0: b7 27 00 80 lui a5, 524290 +800007b4: 37 24 00 80 lui s0, 524290 +800007b8: 13 04 04 0c addi s0, s0, 192 +800007bc: 93 87 07 0c addi a5, a5, 192 +800007c0: b3 87 87 40 sub a5, a5, s0 +800007c4: 23 22 91 00 sw s1, 4(sp) +800007c8: 23 26 11 00 sw ra, 12(sp) +800007cc: 93 d4 27 40 srai s1, a5, 2 +800007d0: 63 80 04 02 beqz s1, 32 +800007d4: 93 87 c7 ff addi a5, a5, -4 +800007d8: 33 84 87 00 add s0, a5, s0 +800007dc: 83 27 04 00 lw a5, 0(s0) +800007e0: 93 84 f4 ff addi s1, s1, -1 +800007e4: 13 04 c4 ff addi s0, s0, -4 +800007e8: e7 80 07 00 jalr a5 +800007ec: e3 98 04 fe bnez s1, -16 +800007f0: 83 20 c1 00 lw ra, 12(sp) +800007f4: 03 24 81 00 lw s0, 8(sp) +800007f8: 83 24 41 00 lw s1, 4(sp) +800007fc: 13 01 01 01 addi sp, sp, 16 +80000800: 67 80 00 00 ret -80000c38 atexit: -80000c38: 93 05 05 00 mv a1, a0 -80000c3c: 93 06 00 00 mv a3, zero -80000c40: 13 06 00 00 mv a2, zero -80000c44: 13 05 00 00 mv a0, zero -80000c48: 6f 00 c0 20 j 524 +80000804 spawn_kernel_all_stub: +80000804: 13 01 01 fe addi sp, sp, -32 +80000808: 23 2e 11 00 sw ra, 28(sp) +8000080c: 23 2c 81 00 sw s0, 24(sp) +80000810: 23 2a 91 00 sw s1, 20(sp) +80000814: 23 28 21 01 sw s2, 16(sp) +80000818: 23 26 31 01 sw s3, 12(sp) +8000081c: 23 24 41 01 sw s4, 8(sp) +80000820: 73 26 50 cc csrr a2, 3269 +80000824: 73 27 30 cc csrr a4, 3267 +80000828: f3 26 00 cc csrr a3, 3264 +8000082c: 73 25 00 fc csrr a0, 4032 +80000830: b7 27 00 80 lui a5, 524290 +80000834: 13 16 26 00 slli a2, a2, 2 +80000838: 93 87 c7 4e addi a5, a5, 1260 +8000083c: b3 87 c7 00 add a5, a5, a2 +80000840: 03 a4 07 00 lw s0, 0(a5) +80000844: 83 24 44 01 lw s1, 20(s0) +80000848: 03 26 04 01 lw a2, 16(s0) +8000084c: 33 2a 97 00 slt s4, a4, s1 +80000850: 93 87 04 00 mv a5, s1 +80000854: 33 0a ca 00 add s4, s4, a2 +80000858: b3 04 e6 02 mul s1, a2, a4 +8000085c: 63 54 f7 00 bge a4, a5, 8 +80000860: 93 07 07 00 mv a5, a4 +80000864: b3 84 f4 00 add s1, s1, a5 +80000868: 83 25 04 00 lw a1, 0(s0) +8000086c: 03 27 c4 00 lw a4, 12(s0) +80000870: 03 a9 05 00 lw s2, 0(a1) +80000874: 83 a9 45 00 lw s3, 4(a1) +80000878: b3 84 a4 02 mul s1, s1, a0 +8000087c: b3 07 da 02 mul a5, s4, a3 +80000880: b3 84 e4 00 add s1, s1, a4 +80000884: b3 84 f4 00 add s1, s1, a5 +80000888: 33 0a 9a 00 add s4, s4, s1 +8000088c: b3 09 39 03 mul s3, s2, s3 +80000890: 63 c0 44 07 blt s1, s4, 96 +80000894: 6f 00 00 08 j 128 +80000898: 03 47 e4 01 lbu a4, 30(s0) +8000089c: 83 46 d4 01 lbu a3, 29(s0) +800008a0: 33 d7 e4 40 sra a4, s1, a4 +800008a4: b3 07 37 03 mul a5, a4, s3 +800008a8: b3 87 f4 40 sub a5, s1, a5 +800008ac: 63 80 06 06 beqz a3, 96 +800008b0: 83 46 f4 01 lbu a3, 31(s0) +800008b4: b3 d6 d7 40 sra a3, a5, a3 +800008b8: b3 88 26 03 mul a7, a3, s2 +800008bc: 03 ae 45 01 lw t3, 20(a1) +800008c0: 03 a3 05 01 lw t1, 16(a1) +800008c4: 03 a6 c5 00 lw a2, 12(a1) +800008c8: 03 28 44 00 lw a6, 4(s0) +800008cc: 03 25 84 00 lw a0, 8(s0) +800008d0: 93 84 14 00 addi s1, s1, 1 +800008d4: 33 07 c7 01 add a4, a4, t3 +800008d8: b3 86 66 00 add a3, a3, t1 +800008dc: b3 87 17 41 sub a5, a5, a7 +800008e0: 33 86 c7 00 add a2, a5, a2 +800008e4: e7 00 08 00 jalr a6 +800008e8: 63 06 9a 02 beq s4, s1, 44 +800008ec: 83 25 04 00 lw a1, 0(s0) +800008f0: 83 47 c4 01 lbu a5, 28(s0) +800008f4: e3 92 07 fa bnez a5, -92 +800008f8: 33 c7 34 03 div a4, s1, s3 +800008fc: 83 46 d4 01 lbu a3, 29(s0) +80000900: b3 07 37 03 mul a5, a4, s3 +80000904: b3 87 f4 40 sub a5, s1, a5 +80000908: e3 94 06 fa bnez a3, -88 +8000090c: b3 c6 27 03 div a3, a5, s2 +80000910: 6f f0 9f fa j -88 +80000914: 03 27 84 01 lw a4, 24(s0) +80000918: 93 07 00 00 mv a5, zero +8000091c: 6b c0 e7 00 vx_bar a5, a4 +80000920: 83 20 c1 01 lw ra, 28(sp) +80000924: 03 24 81 01 lw s0, 24(sp) +80000928: 83 24 41 01 lw s1, 20(sp) +8000092c: 03 29 01 01 lw s2, 16(sp) +80000930: 83 29 c1 00 lw s3, 12(sp) +80000934: 03 2a 81 00 lw s4, 8(sp) +80000938: 13 01 01 02 addi sp, sp, 32 +8000093c: 67 80 00 00 ret -80000c4c exit: -80000c4c: 13 01 01 ff addi sp, sp, -16 -80000c50: 93 05 00 00 mv a1, zero -80000c54: 23 24 81 00 sw s0, 8(sp) -80000c58: 23 26 11 00 sw ra, 12(sp) -80000c5c: 13 04 05 00 mv s0, a0 -80000c60: ef 00 00 29 jal 656 -80000c64: b7 27 00 80 lui a5, 524290 -80000c68: 03 a5 07 44 lw a0, 1088(a5) -80000c6c: 83 27 c5 03 lw a5, 60(a0) -80000c70: 63 84 07 00 beqz a5, 8 -80000c74: e7 80 07 00 jalr a5 -80000c78: 13 05 04 00 mv a0, s0 -80000c7c: ef f0 df 9e jal -1556 +80000940 spawn_kernel_rem_stub: +80000940: f3 26 50 cc csrr a3, 3269 +80000944: f3 27 20 cc csrr a5, 3266 +80000948: 37 27 00 80 lui a4, 524290 +8000094c: 93 96 26 00 slli a3, a3, 2 +80000950: 13 07 c7 4e addi a4, a4, 1260 +80000954: 33 07 d7 00 add a4, a4, a3 +80000958: 03 25 07 00 lw a0, 0(a4) +8000095c: 83 25 05 00 lw a1, 0(a0) +80000960: 83 26 c5 00 lw a3, 12(a0) +80000964: 03 47 c5 01 lbu a4, 28(a0) +80000968: 83 a8 05 00 lw a7, 0(a1) +8000096c: 03 a6 45 00 lw a2, 4(a1) +80000970: b3 87 d7 00 add a5, a5, a3 +80000974: 33 86 c8 02 mul a2, a7, a2 +80000978: 63 08 07 04 beqz a4, 80 +8000097c: 03 47 e5 01 lbu a4, 30(a0) +80000980: 83 46 d5 01 lbu a3, 29(a0) +80000984: 33 d7 e7 40 sra a4, a5, a4 +80000988: 33 06 c7 02 mul a2, a4, a2 +8000098c: b3 87 c7 40 sub a5, a5, a2 +80000990: 63 86 06 04 beqz a3, 76 +80000994: 83 46 f5 01 lbu a3, 31(a0) +80000998: 33 d8 d7 40 sra a6, a5, a3 +8000099c: 83 a6 05 01 lw a3, 16(a1) +800009a0: 03 ae 45 01 lw t3, 20(a1) +800009a4: 03 a6 c5 00 lw a2, 12(a1) +800009a8: b3 06 d8 00 add a3, a6, a3 +800009ac: 33 08 18 03 mul a6, a6, a7 +800009b0: 03 23 45 00 lw t1, 4(a0) +800009b4: 03 25 85 00 lw a0, 8(a0) +800009b8: 33 07 c7 01 add a4, a4, t3 +800009bc: b3 87 07 41 sub a5, a5, a6 +800009c0: 33 86 c7 00 add a2, a5, a2 +800009c4: 67 00 03 00 jr t1 +800009c8: 33 c7 c7 02 div a4, a5, a2 +800009cc: 83 46 d5 01 lbu a3, 29(a0) +800009d0: 33 06 c7 02 mul a2, a4, a2 +800009d4: b3 87 c7 40 sub a5, a5, a2 +800009d8: e3 9e 06 fa bnez a3, -68 +800009dc: 33 c8 17 03 div a6, a5, a7 +800009e0: 6f f0 df fb j -68 -80000c80 __libc_fini_array: -80000c80: 13 01 01 ff addi sp, sp, -16 -80000c84: 23 24 81 00 sw s0, 8(sp) -80000c88: b7 27 00 80 lui a5, 524290 -80000c8c: 37 24 00 80 lui s0, 524290 -80000c90: 13 04 84 01 addi s0, s0, 24 -80000c94: 93 87 87 01 addi a5, a5, 24 -80000c98: b3 87 87 40 sub a5, a5, s0 -80000c9c: 23 22 91 00 sw s1, 4(sp) -80000ca0: 23 26 11 00 sw ra, 12(sp) -80000ca4: 93 d4 27 40 srai s1, a5, 2 -80000ca8: 63 80 04 02 beqz s1, 32 -80000cac: 93 87 c7 ff addi a5, a5, -4 -80000cb0: 33 84 87 00 add s0, a5, s0 -80000cb4: 83 27 04 00 lw a5, 0(s0) -80000cb8: 93 84 f4 ff addi s1, s1, -1 -80000cbc: 13 04 c4 ff addi s0, s0, -4 -80000cc0: e7 80 07 00 jalr a5 -80000cc4: e3 98 04 fe bnez s1, -16 -80000cc8: 83 20 c1 00 lw ra, 12(sp) -80000ccc: 03 24 81 00 lw s0, 8(sp) -80000cd0: 83 24 41 00 lw s1, 4(sp) -80000cd4: 13 01 01 01 addi sp, sp, 16 -80000cd8: 67 80 00 00 ret +800009e4 spawn_kernel_all_cb: +800009e4: 13 01 01 ff addi sp, sp, -16 +800009e8: 23 26 11 00 sw ra, 12(sp) +800009ec: 93 07 f0 ff addi a5, zero, -1 +800009f0: 6b 80 07 00 vx_tmc a5 +800009f4: ef f0 1f e1 jal -496 +800009f8: f3 27 30 cc csrr a5, 3267 +800009fc: 93 b7 17 00 seqz a5, a5 +80000a00: 6b 80 07 00 vx_tmc a5 +80000a04: 83 20 c1 00 lw ra, 12(sp) +80000a08: 13 01 01 01 addi sp, sp, 16 +80000a0c: 67 80 00 00 ret -80000cdc __libc_init_array: -80000cdc: 13 01 01 ff addi sp, sp, -16 -80000ce0: 23 24 81 00 sw s0, 8(sp) -80000ce4: 23 20 21 01 sw s2, 0(sp) -80000ce8: 37 24 00 80 lui s0, 524290 -80000cec: 37 29 00 80 lui s2, 524290 -80000cf0: 93 07 44 01 addi a5, s0, 20 -80000cf4: 13 09 49 01 addi s2, s2, 20 -80000cf8: 33 09 f9 40 sub s2, s2, a5 -80000cfc: 23 26 11 00 sw ra, 12(sp) -80000d00: 23 22 91 00 sw s1, 4(sp) -80000d04: 13 59 29 40 srai s2, s2, 2 -80000d08: 63 00 09 02 beqz s2, 32 -80000d0c: 13 04 44 01 addi s0, s0, 20 -80000d10: 93 04 00 00 mv s1, zero -80000d14: 83 27 04 00 lw a5, 0(s0) -80000d18: 93 84 14 00 addi s1, s1, 1 -80000d1c: 13 04 44 00 addi s0, s0, 4 -80000d20: e7 80 07 00 jalr a5 -80000d24: e3 18 99 fe bne s2, s1, -16 -80000d28: 37 24 00 80 lui s0, 524290 -80000d2c: 37 29 00 80 lui s2, 524290 -80000d30: 93 07 44 01 addi a5, s0, 20 -80000d34: 13 09 89 01 addi s2, s2, 24 -80000d38: 33 09 f9 40 sub s2, s2, a5 -80000d3c: 13 59 29 40 srai s2, s2, 2 -80000d40: 63 00 09 02 beqz s2, 32 -80000d44: 13 04 44 01 addi s0, s0, 20 -80000d48: 93 04 00 00 mv s1, zero -80000d4c: 83 27 04 00 lw a5, 0(s0) -80000d50: 93 84 14 00 addi s1, s1, 1 -80000d54: 13 04 44 00 addi s0, s0, 4 -80000d58: e7 80 07 00 jalr a5 -80000d5c: e3 18 99 fe bne s2, s1, -16 -80000d60: 83 20 c1 00 lw ra, 12(sp) -80000d64: 03 24 81 00 lw s0, 8(sp) -80000d68: 83 24 41 00 lw s1, 4(sp) -80000d6c: 03 29 01 00 lw s2, 0(sp) -80000d70: 13 01 01 01 addi sp, sp, 16 -80000d74: 67 80 00 00 ret +80000a10 vx_spawn_kernel: +80000a10: 13 01 01 fd addi sp, sp, -48 +80000a14: 23 26 11 02 sw ra, 44(sp) +80000a18: 23 24 81 02 sw s0, 40(sp) +80000a1c: 23 22 91 02 sw s1, 36(sp) +80000a20: 23 20 21 03 sw s2, 32(sp) +80000a24: f3 28 20 fc csrr a7, 4034 +80000a28: 73 23 10 fc csrr t1, 4033 +80000a2c: f3 24 00 fc csrr s1, 4032 +80000a30: f3 27 50 cc csrr a5, 3269 +80000a34: 13 07 f0 01 addi a4, zero, 31 +80000a38: 63 46 f7 0e blt a4, a5, 236 +80000a3c: 03 2e 05 00 lw t3, 0(a0) +80000a40: 83 26 45 00 lw a3, 4(a0) +80000a44: 03 28 85 00 lw a6, 8(a0) +80000a48: b3 0e 93 02 mul t4, t1, s1 +80000a4c: 13 07 10 00 addi a4, zero, 1 +80000a50: b3 06 de 02 mul a3, t3, a3 +80000a54: 33 88 06 03 mul a6, a3, a6 +80000a58: 63 d4 0e 01 bge t4, a6, 8 +80000a5c: 33 47 d8 03 div a4, a6, t4 +80000a60: 63 ce e8 0c blt a7, a4, 220 +80000a64: 63 d0 e7 0c bge a5, a4, 192 +80000a68: 93 88 f8 ff addi a7, a7, -1 +80000a6c: b3 4e e8 02 div t4, a6, a4 +80000a70: 13 84 0e 00 mv s0, t4 +80000a74: 63 96 f8 00 bne a7, a5, 12 +80000a78: 33 67 e8 02 rem a4, a6, a4 +80000a7c: 33 04 d7 01 add s0, a4, t4 +80000a80: 33 49 94 02 div s2, s0, s1 +80000a84: 33 64 94 02 rem s0, s0, s1 +80000a88: 63 40 69 0c blt s2, t1, 192 +80000a8c: 93 0f 10 00 addi t6, zero, 1 +80000a90: 33 4f 69 02 div t5, s2, t1 +80000a94: 63 06 0f 00 beqz t5, 12 +80000a98: 93 0f 0f 00 mv t6, t5 +80000a9c: 33 6f 69 02 rem t5, s2, t1 +80000aa0: d3 f7 06 d0 fcvt.s.w fa5, a3 +80000aa4: 13 07 fe ff addi a4, t3, -1 +80000aa8: 93 82 f6 ff addi t0, a3, -1 +80000aac: d3 88 07 e0 fmv.x.w a7, fa5 +80000ab0: d3 77 0e d0 fcvt.s.w fa5, t3 +80000ab4: 33 7e c7 01 and t3, a4, t3 +80000ab8: 37 27 00 80 lui a4, 524290 +80000abc: 53 88 07 e0 fmv.x.w a6, fa5 +80000ac0: b3 f6 d2 00 and a3, t0, a3 +80000ac4: 93 d8 78 41 srai a7, a7, 23 +80000ac8: 13 58 78 41 srai a6, a6, 23 +80000acc: 13 07 c7 4e addi a4, a4, 1260 +80000ad0: 93 b6 16 00 seqz a3, a3 +80000ad4: 13 3e 1e 00 seqz t3, t3 +80000ad8: 93 88 18 f8 addi a7, a7, -127 +80000adc: 13 08 18 f8 addi a6, a6, -127 +80000ae0: 23 20 a1 00 sw a0, 0(sp) +80000ae4: 23 22 b1 00 sw a1, 4(sp) +80000ae8: 23 24 c1 00 sw a2, 8(sp) +80000aec: 23 28 f1 01 sw t6, 16(sp) +80000af0: 23 2a e1 01 sw t5, 20(sp) +80000af4: 23 2c 01 00 sw zero, 24(sp) +80000af8: 23 0e d1 00 sb a3, 28(sp) +80000afc: a3 0e c1 01 sb t3, 29(sp) +80000b00: 23 0f 11 01 sb a7, 30(sp) +80000b04: a3 0f 01 01 sb a6, 31(sp) +80000b08: b3 8e fe 02 mul t4, t4, a5 +80000b0c: 93 97 27 00 slli a5, a5, 2 +80000b10: b3 07 f7 00 add a5, a4, a5 +80000b14: 23 a0 27 00 sw sp, 0(a5) +80000b18: 23 26 d1 01 sw t4, 12(sp) +80000b1c: 63 4c 20 03 bgtz s2, 56 +80000b20: 63 16 04 06 bnez s0, 108 +80000b24: 83 20 c1 02 lw ra, 44(sp) +80000b28: 03 24 81 02 lw s0, 40(sp) +80000b2c: 83 24 41 02 lw s1, 36(sp) +80000b30: 03 29 01 02 lw s2, 32(sp) +80000b34: 13 01 01 03 addi sp, sp, 48 +80000b38: 67 80 00 00 ret +80000b3c: 13 87 08 00 mv a4, a7 +80000b40: e3 c4 e7 f2 blt a5, a4, -216 +80000b44: 6f f0 1f fe j -32 +80000b48: 13 0f 00 00 mv t5, zero +80000b4c: 93 0f 10 00 addi t6, zero, 1 +80000b50: 6f f0 1f f5 j -176 +80000b54: 13 07 09 00 mv a4, s2 +80000b58: 63 54 23 01 bge t1, s2, 8 +80000b5c: 13 07 03 00 mv a4, t1 +80000b60: b7 17 00 80 lui a5, 524289 +80000b64: 23 2c e1 00 sw a4, 24(sp) +80000b68: 93 87 47 9e addi a5, a5, -1564 +80000b6c: 6b 10 f7 00 vx_wspawn a4, a5 +80000b70: 93 07 f0 ff addi a5, zero, -1 +80000b74: 6b 80 07 00 vx_tmc a5 +80000b78: ef f0 df c8 jal -884 +80000b7c: f3 27 30 cc csrr a5, 3267 +80000b80: 93 b7 17 00 seqz a5, a5 +80000b84: 6b 80 07 00 vx_tmc a5 +80000b88: e3 0e 04 f8 beqz s0, -100 +80000b8c: b3 04 99 02 mul s1, s2, s1 +80000b90: 13 09 10 00 addi s2, zero, 1 +80000b94: 33 14 89 00 sll s0, s2, s0 +80000b98: 13 04 f4 ff addi s0, s0, -1 +80000b9c: 23 26 91 00 sw s1, 12(sp) +80000ba0: 6b 00 04 00 vx_tmc s0 +80000ba4: ef f0 df d9 jal -612 +80000ba8: 6b 00 09 00 vx_tmc s2 +80000bac: 83 20 c1 02 lw ra, 44(sp) +80000bb0: 03 24 81 02 lw s0, 40(sp) +80000bb4: 83 24 41 02 lw s1, 36(sp) +80000bb8: 03 29 01 02 lw s2, 32(sp) +80000bbc: 13 01 01 03 addi sp, sp, 48 +80000bc0: 67 80 00 00 ret -80000d78 memset: -80000d78: 13 03 f0 00 addi t1, zero, 15 -80000d7c: 13 07 05 00 mv a4, a0 -80000d80: 63 7e c3 02 bgeu t1, a2, 60 -80000d84: 93 77 f7 00 andi a5, a4, 15 -80000d88: 63 90 07 0a bnez a5, 160 -80000d8c: 63 92 05 08 bnez a1, 132 -80000d90: 93 76 06 ff andi a3, a2, -16 -80000d94: 13 76 f6 00 andi a2, a2, 15 -80000d98: b3 86 e6 00 add a3, a3, a4 -80000d9c: 23 20 b7 00 sw a1, 0(a4) -80000da0: 23 22 b7 00 sw a1, 4(a4) -80000da4: 23 24 b7 00 sw a1, 8(a4) -80000da8: 23 26 b7 00 sw a1, 12(a4) -80000dac: 13 07 07 01 addi a4, a4, 16 -80000db0: e3 66 d7 fe bltu a4, a3, -20 -80000db4: 63 14 06 00 bnez a2, 8 -80000db8: 67 80 00 00 ret -80000dbc: b3 06 c3 40 sub a3, t1, a2 -80000dc0: 93 96 26 00 slli a3, a3, 2 -80000dc4: 97 02 00 00 auipc t0, 0 -80000dc8: b3 86 56 00 add a3, a3, t0 -80000dcc: 67 80 c6 00 jr 12(a3) -80000dd0: 23 07 b7 00 sb a1, 14(a4) -80000dd4: a3 06 b7 00 sb a1, 13(a4) -80000dd8: 23 06 b7 00 sb a1, 12(a4) -80000ddc: a3 05 b7 00 sb a1, 11(a4) -80000de0: 23 05 b7 00 sb a1, 10(a4) -80000de4: a3 04 b7 00 sb a1, 9(a4) -80000de8: 23 04 b7 00 sb a1, 8(a4) -80000dec: a3 03 b7 00 sb a1, 7(a4) -80000df0: 23 03 b7 00 sb a1, 6(a4) -80000df4: a3 02 b7 00 sb a1, 5(a4) -80000df8: 23 02 b7 00 sb a1, 4(a4) -80000dfc: a3 01 b7 00 sb a1, 3(a4) -80000e00: 23 01 b7 00 sb a1, 2(a4) -80000e04: a3 00 b7 00 sb a1, 1(a4) -80000e08: 23 00 b7 00 sb a1, 0(a4) -80000e0c: 67 80 00 00 ret -80000e10: 93 f5 f5 0f andi a1, a1, 255 -80000e14: 93 96 85 00 slli a3, a1, 8 -80000e18: b3 e5 d5 00 or a1, a1, a3 -80000e1c: 93 96 05 01 slli a3, a1, 16 -80000e20: b3 e5 d5 00 or a1, a1, a3 -80000e24: 6f f0 df f6 j -148 -80000e28: 93 96 27 00 slli a3, a5, 2 -80000e2c: 97 02 00 00 auipc t0, 0 -80000e30: b3 86 56 00 add a3, a3, t0 -80000e34: 93 82 00 00 mv t0, ra -80000e38: e7 80 06 fa jalr -96(a3) -80000e3c: 93 80 02 00 mv ra, t0 -80000e40: 93 87 07 ff addi a5, a5, -16 -80000e44: 33 07 f7 40 sub a4, a4, a5 -80000e48: 33 06 f6 00 add a2, a2, a5 -80000e4c: e3 78 c3 f6 bgeu t1, a2, -144 -80000e50: 6f f0 df f3 j -196 +80000bc4 vx_perf_dump: +80000bc4: f3 27 50 cc csrr a5, 3269 +80000bc8: 37 07 ff 00 lui a4, 4080 +80000bcc: b3 87 e7 00 add a5, a5, a4 +80000bd0: 93 97 87 00 slli a5, a5, 8 +80000bd4: 73 27 00 b0 csrr a4, mcycle +80000bd8: 23 a0 e7 00 sw a4, 0(a5) +80000bdc: 73 27 10 b0 csrr a4, 2817 +80000be0: 23 a2 e7 00 sw a4, 4(a5) +80000be4: 73 27 20 b0 csrr a4, minstret +80000be8: 23 a4 e7 00 sw a4, 8(a5) +80000bec: 73 27 30 b0 csrr a4, mhpmcounter3 +80000bf0: 23 a6 e7 00 sw a4, 12(a5) +80000bf4: 73 27 40 b0 csrr a4, mhpmcounter4 +80000bf8: 23 a8 e7 00 sw a4, 16(a5) +80000bfc: 73 27 50 b0 csrr a4, mhpmcounter5 +80000c00: 23 aa e7 00 sw a4, 20(a5) +80000c04: 73 27 60 b0 csrr a4, mhpmcounter6 +80000c08: 23 ac e7 00 sw a4, 24(a5) +80000c0c: 73 27 70 b0 csrr a4, mhpmcounter7 +80000c10: 23 ae e7 00 sw a4, 28(a5) +80000c14: 73 27 80 b0 csrr a4, mhpmcounter8 +80000c18: 23 a0 e7 02 sw a4, 32(a5) +80000c1c: 73 27 90 b0 csrr a4, mhpmcounter9 +80000c20: 23 a2 e7 02 sw a4, 36(a5) +80000c24: 73 27 a0 b0 csrr a4, mhpmcounter10 +80000c28: 23 a4 e7 02 sw a4, 40(a5) +80000c2c: 73 27 b0 b0 csrr a4, mhpmcounter11 +80000c30: 23 a6 e7 02 sw a4, 44(a5) +80000c34: 73 27 c0 b0 csrr a4, mhpmcounter12 +80000c38: 23 a8 e7 02 sw a4, 48(a5) +80000c3c: 73 27 d0 b0 csrr a4, mhpmcounter13 +80000c40: 23 aa e7 02 sw a4, 52(a5) +80000c44: 73 27 e0 b0 csrr a4, mhpmcounter14 +80000c48: 23 ac e7 02 sw a4, 56(a5) +80000c4c: 73 27 f0 b0 csrr a4, mhpmcounter15 +80000c50: 23 ae e7 02 sw a4, 60(a5) +80000c54: 73 27 00 b1 csrr a4, mhpmcounter16 +80000c58: 23 a0 e7 04 sw a4, 64(a5) +80000c5c: 73 27 10 b1 csrr a4, mhpmcounter17 +80000c60: 23 a2 e7 04 sw a4, 68(a5) +80000c64: 73 27 20 b1 csrr a4, mhpmcounter18 +80000c68: 23 a4 e7 04 sw a4, 72(a5) +80000c6c: 73 27 30 b1 csrr a4, mhpmcounter19 +80000c70: 23 a6 e7 04 sw a4, 76(a5) +80000c74: 73 27 40 b1 csrr a4, mhpmcounter20 +80000c78: 23 a8 e7 04 sw a4, 80(a5) +80000c7c: 73 27 50 b1 csrr a4, mhpmcounter21 +80000c80: 23 aa e7 04 sw a4, 84(a5) +80000c84: 73 27 60 b1 csrr a4, mhpmcounter22 +80000c88: 23 ac e7 04 sw a4, 88(a5) +80000c8c: 73 27 70 b1 csrr a4, mhpmcounter23 +80000c90: 23 ae e7 04 sw a4, 92(a5) +80000c94: 73 27 80 b1 csrr a4, mhpmcounter24 +80000c98: 23 a0 e7 06 sw a4, 96(a5) +80000c9c: 73 27 90 b1 csrr a4, mhpmcounter25 +80000ca0: 23 a2 e7 06 sw a4, 100(a5) +80000ca4: 73 27 a0 b1 csrr a4, mhpmcounter26 +80000ca8: 23 a4 e7 06 sw a4, 104(a5) +80000cac: 73 27 b0 b1 csrr a4, mhpmcounter27 +80000cb0: 23 a6 e7 06 sw a4, 108(a5) +80000cb4: 73 27 c0 b1 csrr a4, mhpmcounter28 +80000cb8: 23 a8 e7 06 sw a4, 112(a5) +80000cbc: 73 27 d0 b1 csrr a4, mhpmcounter29 +80000cc0: 23 aa e7 06 sw a4, 116(a5) +80000cc4: 73 27 e0 b1 csrr a4, mhpmcounter30 +80000cc8: 23 ac e7 06 sw a4, 120(a5) +80000ccc: 73 27 f0 b1 csrr a4, mhpmcounter31 +80000cd0: 23 ae e7 06 sw a4, 124(a5) +80000cd4: 73 27 00 b8 csrr a4, mcycleh +80000cd8: 23 a0 e7 08 sw a4, 128(a5) +80000cdc: 73 27 10 b8 csrr a4, 2945 +80000ce0: 23 a2 e7 08 sw a4, 132(a5) +80000ce4: 73 27 20 b8 csrr a4, minstreth +80000ce8: 23 a4 e7 08 sw a4, 136(a5) +80000cec: 73 27 30 b8 csrr a4, mhpmcounter3h +80000cf0: 23 a6 e7 08 sw a4, 140(a5) +80000cf4: 73 27 40 b8 csrr a4, mhpmcounter4h +80000cf8: 23 a8 e7 08 sw a4, 144(a5) +80000cfc: 73 27 50 b8 csrr a4, mhpmcounter5h +80000d00: 23 aa e7 08 sw a4, 148(a5) +80000d04: 73 27 60 b8 csrr a4, mhpmcounter6h +80000d08: 23 ac e7 08 sw a4, 152(a5) +80000d0c: 73 27 70 b8 csrr a4, mhpmcounter7h +80000d10: 23 ae e7 08 sw a4, 156(a5) +80000d14: 73 27 80 b8 csrr a4, mhpmcounter8h +80000d18: 23 a0 e7 0a sw a4, 160(a5) +80000d1c: 73 27 90 b8 csrr a4, mhpmcounter9h +80000d20: 23 a2 e7 0a sw a4, 164(a5) +80000d24: 73 27 a0 b8 csrr a4, mhpmcounter10h +80000d28: 23 a4 e7 0a sw a4, 168(a5) +80000d2c: 73 27 b0 b8 csrr a4, mhpmcounter11h +80000d30: 23 a6 e7 0a sw a4, 172(a5) +80000d34: 73 27 c0 b8 csrr a4, mhpmcounter12h +80000d38: 23 a8 e7 0a sw a4, 176(a5) +80000d3c: 73 27 d0 b8 csrr a4, mhpmcounter13h +80000d40: 23 aa e7 0a sw a4, 180(a5) +80000d44: 73 27 e0 b8 csrr a4, mhpmcounter14h +80000d48: 23 ac e7 0a sw a4, 184(a5) +80000d4c: 73 27 f0 b8 csrr a4, mhpmcounter15h +80000d50: 23 ae e7 0a sw a4, 188(a5) +80000d54: 73 27 00 b9 csrr a4, mhpmcounter16h +80000d58: 23 a0 e7 0c sw a4, 192(a5) +80000d5c: 73 27 10 b9 csrr a4, mhpmcounter17h +80000d60: 23 a2 e7 0c sw a4, 196(a5) +80000d64: 73 27 20 b9 csrr a4, mhpmcounter18h +80000d68: 23 a4 e7 0c sw a4, 200(a5) +80000d6c: 73 27 30 b9 csrr a4, mhpmcounter19h +80000d70: 23 a6 e7 0c sw a4, 204(a5) +80000d74: 73 27 40 b9 csrr a4, mhpmcounter20h +80000d78: 23 a8 e7 0c sw a4, 208(a5) +80000d7c: 73 27 50 b9 csrr a4, mhpmcounter21h +80000d80: 23 aa e7 0c sw a4, 212(a5) +80000d84: 73 27 60 b9 csrr a4, mhpmcounter22h +80000d88: 23 ac e7 0c sw a4, 216(a5) +80000d8c: 73 27 70 b9 csrr a4, mhpmcounter23h +80000d90: 23 ae e7 0c sw a4, 220(a5) +80000d94: 73 27 80 b9 csrr a4, mhpmcounter24h +80000d98: 23 a0 e7 0e sw a4, 224(a5) +80000d9c: 73 27 90 b9 csrr a4, mhpmcounter25h +80000da0: 23 a2 e7 0e sw a4, 228(a5) +80000da4: 73 27 a0 b9 csrr a4, mhpmcounter26h +80000da8: 23 a4 e7 0e sw a4, 232(a5) +80000dac: 73 27 b0 b9 csrr a4, mhpmcounter27h +80000db0: 23 a6 e7 0e sw a4, 236(a5) +80000db4: 73 27 c0 b9 csrr a4, mhpmcounter28h +80000db8: 23 a8 e7 0e sw a4, 240(a5) +80000dbc: 73 27 d0 b9 csrr a4, mhpmcounter29h +80000dc0: 23 aa e7 0e sw a4, 244(a5) +80000dc4: 73 27 e0 b9 csrr a4, mhpmcounter30h +80000dc8: 23 ac e7 0e sw a4, 248(a5) +80000dcc: 73 27 f0 b9 csrr a4, mhpmcounter31h +80000dd0: 23 ae e7 0e sw a4, 252(a5) +80000dd4: 67 80 00 00 ret -80000e54 __register_exitproc: -80000e54: b7 27 00 80 lui a5, 524290 -80000e58: 03 a7 07 44 lw a4, 1088(a5) -80000e5c: 83 27 87 14 lw a5, 328(a4) -80000e60: 63 8c 07 04 beqz a5, 88 -80000e64: 03 a7 47 00 lw a4, 4(a5) -80000e68: 13 08 f0 01 addi a6, zero, 31 -80000e6c: 63 4e e8 06 blt a6, a4, 124 -80000e70: 13 18 27 00 slli a6, a4, 2 -80000e74: 63 06 05 02 beqz a0, 44 -80000e78: 33 83 07 01 add t1, a5, a6 -80000e7c: 23 24 c3 08 sw a2, 136(t1) -80000e80: 83 a8 87 18 lw a7, 392(a5) -80000e84: 13 06 10 00 addi a2, zero, 1 -80000e88: 33 16 e6 00 sll a2, a2, a4 -80000e8c: b3 e8 c8 00 or a7, a7, a2 -80000e90: 23 a4 17 19 sw a7, 392(a5) -80000e94: 23 24 d3 10 sw a3, 264(t1) -80000e98: 93 06 20 00 addi a3, zero, 2 -80000e9c: 63 04 d5 02 beq a0, a3, 40 -80000ea0: 13 07 17 00 addi a4, a4, 1 -80000ea4: 23 a2 e7 00 sw a4, 4(a5) -80000ea8: b3 87 07 01 add a5, a5, a6 -80000eac: 23 a4 b7 00 sw a1, 8(a5) -80000eb0: 13 05 00 00 mv a0, zero +80000dd8 atexit: +80000dd8: 93 05 05 00 mv a1, a0 +80000ddc: 93 06 00 00 mv a3, zero +80000de0: 13 06 00 00 mv a2, zero +80000de4: 13 05 00 00 mv a0, zero +80000de8: 6f 00 40 11 j 276 + +80000dec exit: +80000dec: 13 01 01 ff addi sp, sp, -16 +80000df0: 93 05 00 00 mv a1, zero +80000df4: 23 24 81 00 sw s0, 8(sp) +80000df8: 23 26 11 00 sw ra, 12(sp) +80000dfc: 13 04 05 00 mv s0, a0 +80000e00: ef 00 80 19 jal 408 +80000e04: b7 27 00 80 lui a5, 524290 +80000e08: 03 a5 87 4e lw a0, 1256(a5) +80000e0c: 83 27 c5 03 lw a5, 60(a0) +80000e10: 63 84 07 00 beqz a5, 8 +80000e14: e7 80 07 00 jalr a5 +80000e18: 13 05 04 00 mv a0, s0 +80000e1c: ef f0 5f 8a jal -1884 + +80000e20 memset: +80000e20: 13 03 f0 00 addi t1, zero, 15 +80000e24: 13 07 05 00 mv a4, a0 +80000e28: 63 7e c3 02 bgeu t1, a2, 60 +80000e2c: 93 77 f7 00 andi a5, a4, 15 +80000e30: 63 90 07 0a bnez a5, 160 +80000e34: 63 92 05 08 bnez a1, 132 +80000e38: 93 76 06 ff andi a3, a2, -16 +80000e3c: 13 76 f6 00 andi a2, a2, 15 +80000e40: b3 86 e6 00 add a3, a3, a4 +80000e44: 23 20 b7 00 sw a1, 0(a4) +80000e48: 23 22 b7 00 sw a1, 4(a4) +80000e4c: 23 24 b7 00 sw a1, 8(a4) +80000e50: 23 26 b7 00 sw a1, 12(a4) +80000e54: 13 07 07 01 addi a4, a4, 16 +80000e58: e3 66 d7 fe bltu a4, a3, -20 +80000e5c: 63 14 06 00 bnez a2, 8 +80000e60: 67 80 00 00 ret +80000e64: b3 06 c3 40 sub a3, t1, a2 +80000e68: 93 96 26 00 slli a3, a3, 2 +80000e6c: 97 02 00 00 auipc t0, 0 +80000e70: b3 86 56 00 add a3, a3, t0 +80000e74: 67 80 c6 00 jr 12(a3) +80000e78: 23 07 b7 00 sb a1, 14(a4) +80000e7c: a3 06 b7 00 sb a1, 13(a4) +80000e80: 23 06 b7 00 sb a1, 12(a4) +80000e84: a3 05 b7 00 sb a1, 11(a4) +80000e88: 23 05 b7 00 sb a1, 10(a4) +80000e8c: a3 04 b7 00 sb a1, 9(a4) +80000e90: 23 04 b7 00 sb a1, 8(a4) +80000e94: a3 03 b7 00 sb a1, 7(a4) +80000e98: 23 03 b7 00 sb a1, 6(a4) +80000e9c: a3 02 b7 00 sb a1, 5(a4) +80000ea0: 23 02 b7 00 sb a1, 4(a4) +80000ea4: a3 01 b7 00 sb a1, 3(a4) +80000ea8: 23 01 b7 00 sb a1, 2(a4) +80000eac: a3 00 b7 00 sb a1, 1(a4) +80000eb0: 23 00 b7 00 sb a1, 0(a4) 80000eb4: 67 80 00 00 ret -80000eb8: 93 07 c7 14 addi a5, a4, 332 -80000ebc: 23 24 f7 14 sw a5, 328(a4) -80000ec0: 6f f0 5f fa j -92 -80000ec4: 83 a6 c7 18 lw a3, 396(a5) -80000ec8: 13 07 17 00 addi a4, a4, 1 -80000ecc: 23 a2 e7 00 sw a4, 4(a5) -80000ed0: 33 e6 c6 00 or a2, a3, a2 -80000ed4: 23 a6 c7 18 sw a2, 396(a5) -80000ed8: b3 87 07 01 add a5, a5, a6 -80000edc: 23 a4 b7 00 sw a1, 8(a5) -80000ee0: 13 05 00 00 mv a0, zero -80000ee4: 67 80 00 00 ret -80000ee8: 13 05 f0 ff addi a0, zero, -1 -80000eec: 67 80 00 00 ret +80000eb8: 93 f5 f5 0f andi a1, a1, 255 +80000ebc: 93 96 85 00 slli a3, a1, 8 +80000ec0: b3 e5 d5 00 or a1, a1, a3 +80000ec4: 93 96 05 01 slli a3, a1, 16 +80000ec8: b3 e5 d5 00 or a1, a1, a3 +80000ecc: 6f f0 df f6 j -148 +80000ed0: 93 96 27 00 slli a3, a5, 2 +80000ed4: 97 02 00 00 auipc t0, 0 +80000ed8: b3 86 56 00 add a3, a3, t0 +80000edc: 93 82 00 00 mv t0, ra +80000ee0: e7 80 06 fa jalr -96(a3) +80000ee4: 93 80 02 00 mv ra, t0 +80000ee8: 93 87 07 ff addi a5, a5, -16 +80000eec: 33 07 f7 40 sub a4, a4, a5 +80000ef0: 33 06 f6 00 add a2, a2, a5 +80000ef4: e3 78 c3 f6 bgeu t1, a2, -144 +80000ef8: 6f f0 df f3 j -196 -80000ef0 __call_exitprocs: -80000ef0: 13 01 01 fd addi sp, sp, -48 -80000ef4: b7 27 00 80 lui a5, 524290 -80000ef8: 23 2c 41 01 sw s4, 24(sp) -80000efc: 03 aa 07 44 lw s4, 1088(a5) -80000f00: 23 20 21 03 sw s2, 32(sp) -80000f04: 23 26 11 02 sw ra, 44(sp) -80000f08: 03 29 8a 14 lw s2, 328(s4) -80000f0c: 23 24 81 02 sw s0, 40(sp) -80000f10: 23 22 91 02 sw s1, 36(sp) -80000f14: 23 2e 31 01 sw s3, 28(sp) -80000f18: 23 2a 51 01 sw s5, 20(sp) -80000f1c: 23 28 61 01 sw s6, 16(sp) -80000f20: 23 26 71 01 sw s7, 12(sp) -80000f24: 23 24 81 01 sw s8, 8(sp) -80000f28: 63 00 09 04 beqz s2, 64 -80000f2c: 13 0b 05 00 mv s6, a0 -80000f30: 93 8b 05 00 mv s7, a1 -80000f34: 93 0a 10 00 addi s5, zero, 1 -80000f38: 93 09 f0 ff addi s3, zero, -1 -80000f3c: 83 24 49 00 lw s1, 4(s2) -80000f40: 13 84 f4 ff addi s0, s1, -1 -80000f44: 63 42 04 02 bltz s0, 36 -80000f48: 93 94 24 00 slli s1, s1, 2 -80000f4c: b3 04 99 00 add s1, s2, s1 -80000f50: 63 84 0b 04 beqz s7, 72 -80000f54: 83 a7 44 10 lw a5, 260(s1) -80000f58: 63 80 77 05 beq a5, s7, 64 -80000f5c: 13 04 f4 ff addi s0, s0, -1 -80000f60: 93 84 c4 ff addi s1, s1, -4 -80000f64: e3 16 34 ff bne s0, s3, -20 -80000f68: 83 20 c1 02 lw ra, 44(sp) -80000f6c: 03 24 81 02 lw s0, 40(sp) -80000f70: 83 24 41 02 lw s1, 36(sp) -80000f74: 03 29 01 02 lw s2, 32(sp) -80000f78: 83 29 c1 01 lw s3, 28(sp) -80000f7c: 03 2a 81 01 lw s4, 24(sp) -80000f80: 83 2a 41 01 lw s5, 20(sp) -80000f84: 03 2b 01 01 lw s6, 16(sp) -80000f88: 83 2b c1 00 lw s7, 12(sp) -80000f8c: 03 2c 81 00 lw s8, 8(sp) -80000f90: 13 01 01 03 addi sp, sp, 48 +80000efc __register_exitproc: +80000efc: b7 27 00 80 lui a5, 524290 +80000f00: 03 a7 87 4e lw a4, 1256(a5) +80000f04: 83 27 87 14 lw a5, 328(a4) +80000f08: 63 8c 07 04 beqz a5, 88 +80000f0c: 03 a7 47 00 lw a4, 4(a5) +80000f10: 13 08 f0 01 addi a6, zero, 31 +80000f14: 63 4e e8 06 blt a6, a4, 124 +80000f18: 13 18 27 00 slli a6, a4, 2 +80000f1c: 63 06 05 02 beqz a0, 44 +80000f20: 33 83 07 01 add t1, a5, a6 +80000f24: 23 24 c3 08 sw a2, 136(t1) +80000f28: 83 a8 87 18 lw a7, 392(a5) +80000f2c: 13 06 10 00 addi a2, zero, 1 +80000f30: 33 16 e6 00 sll a2, a2, a4 +80000f34: b3 e8 c8 00 or a7, a7, a2 +80000f38: 23 a4 17 19 sw a7, 392(a5) +80000f3c: 23 24 d3 10 sw a3, 264(t1) +80000f40: 93 06 20 00 addi a3, zero, 2 +80000f44: 63 04 d5 02 beq a0, a3, 40 +80000f48: 13 07 17 00 addi a4, a4, 1 +80000f4c: 23 a2 e7 00 sw a4, 4(a5) +80000f50: b3 87 07 01 add a5, a5, a6 +80000f54: 23 a4 b7 00 sw a1, 8(a5) +80000f58: 13 05 00 00 mv a0, zero +80000f5c: 67 80 00 00 ret +80000f60: 93 07 c7 14 addi a5, a4, 332 +80000f64: 23 24 f7 14 sw a5, 328(a4) +80000f68: 6f f0 5f fa j -92 +80000f6c: 83 a6 c7 18 lw a3, 396(a5) +80000f70: 13 07 17 00 addi a4, a4, 1 +80000f74: 23 a2 e7 00 sw a4, 4(a5) +80000f78: 33 e6 c6 00 or a2, a3, a2 +80000f7c: 23 a6 c7 18 sw a2, 396(a5) +80000f80: b3 87 07 01 add a5, a5, a6 +80000f84: 23 a4 b7 00 sw a1, 8(a5) +80000f88: 13 05 00 00 mv a0, zero +80000f8c: 67 80 00 00 ret +80000f90: 13 05 f0 ff addi a0, zero, -1 80000f94: 67 80 00 00 ret -80000f98: 83 27 49 00 lw a5, 4(s2) -80000f9c: 83 a6 44 00 lw a3, 4(s1) -80000fa0: 93 87 f7 ff addi a5, a5, -1 -80000fa4: 63 8e 87 04 beq a5, s0, 92 -80000fa8: 23 a2 04 00 sw zero, 4(s1) -80000fac: e3 88 06 fa beqz a3, -80 -80000fb0: 83 27 89 18 lw a5, 392(s2) -80000fb4: 33 97 8a 00 sll a4, s5, s0 -80000fb8: 03 2c 49 00 lw s8, 4(s2) -80000fbc: b3 77 f7 00 and a5, a4, a5 -80000fc0: 63 92 07 02 bnez a5, 36 -80000fc4: e7 80 06 00 jalr a3 -80000fc8: 03 27 49 00 lw a4, 4(s2) -80000fcc: 83 27 8a 14 lw a5, 328(s4) -80000fd0: 63 14 87 01 bne a4, s8, 8 -80000fd4: e3 04 f9 f8 beq s2, a5, -120 -80000fd8: e3 88 07 f8 beqz a5, -112 -80000fdc: 13 89 07 00 mv s2, a5 -80000fe0: 6f f0 df f5 j -164 -80000fe4: 83 27 c9 18 lw a5, 396(s2) -80000fe8: 83 a5 44 08 lw a1, 132(s1) -80000fec: 33 77 f7 00 and a4, a4, a5 -80000ff0: 63 1c 07 00 bnez a4, 24 -80000ff4: 13 05 0b 00 mv a0, s6 -80000ff8: e7 80 06 00 jalr a3 -80000ffc: 6f f0 df fc j -52 -80001000: 23 22 89 00 sw s0, 4(s2) -80001004: 6f f0 9f fa j -88 -80001008: 13 85 05 00 mv a0, a1 -8000100c: e7 80 06 00 jalr a3 -80001010: 6f f0 9f fb j -72 + +80000f98 __call_exitprocs: +80000f98: 13 01 01 fd addi sp, sp, -48 +80000f9c: b7 27 00 80 lui a5, 524290 +80000fa0: 23 2c 41 01 sw s4, 24(sp) +80000fa4: 03 aa 87 4e lw s4, 1256(a5) +80000fa8: 23 20 21 03 sw s2, 32(sp) +80000fac: 23 26 11 02 sw ra, 44(sp) +80000fb0: 03 29 8a 14 lw s2, 328(s4) +80000fb4: 23 24 81 02 sw s0, 40(sp) +80000fb8: 23 22 91 02 sw s1, 36(sp) +80000fbc: 23 2e 31 01 sw s3, 28(sp) +80000fc0: 23 2a 51 01 sw s5, 20(sp) +80000fc4: 23 28 61 01 sw s6, 16(sp) +80000fc8: 23 26 71 01 sw s7, 12(sp) +80000fcc: 23 24 81 01 sw s8, 8(sp) +80000fd0: 63 00 09 04 beqz s2, 64 +80000fd4: 13 0b 05 00 mv s6, a0 +80000fd8: 93 8b 05 00 mv s7, a1 +80000fdc: 93 0a 10 00 addi s5, zero, 1 +80000fe0: 93 09 f0 ff addi s3, zero, -1 +80000fe4: 83 24 49 00 lw s1, 4(s2) +80000fe8: 13 84 f4 ff addi s0, s1, -1 +80000fec: 63 42 04 02 bltz s0, 36 +80000ff0: 93 94 24 00 slli s1, s1, 2 +80000ff4: b3 04 99 00 add s1, s2, s1 +80000ff8: 63 84 0b 04 beqz s7, 72 +80000ffc: 83 a7 44 10 lw a5, 260(s1) +80001000: 63 80 77 05 beq a5, s7, 64 +80001004: 13 04 f4 ff addi s0, s0, -1 +80001008: 93 84 c4 ff addi s1, s1, -4 +8000100c: e3 16 34 ff bne s0, s3, -20 +80001010: 83 20 c1 02 lw ra, 44(sp) +80001014: 03 24 81 02 lw s0, 40(sp) +80001018: 83 24 41 02 lw s1, 36(sp) +8000101c: 03 29 01 02 lw s2, 32(sp) +80001020: 83 29 c1 01 lw s3, 28(sp) +80001024: 03 2a 81 01 lw s4, 24(sp) +80001028: 83 2a 41 01 lw s5, 20(sp) +8000102c: 03 2b 01 01 lw s6, 16(sp) +80001030: 83 2b c1 00 lw s7, 12(sp) +80001034: 03 2c 81 00 lw s8, 8(sp) +80001038: 13 01 01 03 addi sp, sp, 48 +8000103c: 67 80 00 00 ret +80001040: 83 27 49 00 lw a5, 4(s2) +80001044: 83 a6 44 00 lw a3, 4(s1) +80001048: 93 87 f7 ff addi a5, a5, -1 +8000104c: 63 8e 87 04 beq a5, s0, 92 +80001050: 23 a2 04 00 sw zero, 4(s1) +80001054: e3 88 06 fa beqz a3, -80 +80001058: 83 27 89 18 lw a5, 392(s2) +8000105c: 33 97 8a 00 sll a4, s5, s0 +80001060: 03 2c 49 00 lw s8, 4(s2) +80001064: b3 77 f7 00 and a5, a4, a5 +80001068: 63 92 07 02 bnez a5, 36 +8000106c: e7 80 06 00 jalr a3 +80001070: 03 27 49 00 lw a4, 4(s2) +80001074: 83 27 8a 14 lw a5, 328(s4) +80001078: 63 14 87 01 bne a4, s8, 8 +8000107c: e3 04 f9 f8 beq s2, a5, -120 +80001080: e3 88 07 f8 beqz a5, -112 +80001084: 13 89 07 00 mv s2, a5 +80001088: 6f f0 df f5 j -164 +8000108c: 83 27 c9 18 lw a5, 396(s2) +80001090: 83 a5 44 08 lw a1, 132(s1) +80001094: 33 77 f7 00 and a4, a4, a5 +80001098: 63 1c 07 00 bnez a4, 24 +8000109c: 13 05 0b 00 mv a0, s6 +800010a0: e7 80 06 00 jalr a3 +800010a4: 6f f0 df fc j -52 +800010a8: 23 22 89 00 sw s0, 4(s2) +800010ac: 6f f0 9f fa j -88 +800010b0: 13 85 05 00 mv a0, a1 +800010b4: e7 80 06 00 jalr a3 +800010b8: 6f f0 9f fb j -72 Disassembly of section .init_array: -80002014 __preinit_array_start: -80002014: 50 00 -80002016: 00 80 +800020bc __preinit_array_start: +800020bc: 50 00 +800020be: 00 80 Disassembly of section .data: -80002018 impure_data: -80002018: 00 00 -8000201a: 00 00 -8000201c: 04 23 -8000201e: 00 80 -80002020: 6c 23 -80002022: 00 80 -80002024: d4 23 -80002026: 00 80 - ... -800020c0: 01 00 +800020c0 impure_data: +800020c0: 00 00 800020c2: 00 00 -800020c4: 00 00 -800020c6: 00 00 -800020c8: 0e 33 -800020ca: cd ab -800020cc: 34 12 -800020ce: 6d e6 -800020d0: ec de -800020d2: 05 00 -800020d4: 0b 00 00 00 +800020c4: ac 23 +800020c6: 00 80 +800020c8: 14 24 +800020ca: 00 80 +800020cc: 7c 24 +800020ce: 00 80 + ... +80002168: 01 00 +8000216a: 00 00 +8000216c: 00 00 +8000216e: 00 00 +80002170: 0e 33 +80002172: cd ab +80002174: 34 12 +80002176: 6d e6 +80002178: ec de +8000217a: 05 00 +8000217c: 0b 00 00 00 ... Disassembly of section .sdata: -80002440 _global_impure_ptr: -80002440: 18 20 -80002442: 00 80 +800024e8 _global_impure_ptr: +800024e8: c0 20 +800024ea: 00 80 Disassembly of section .bss: -80002444 g_wspawn_args: +800024ec g_wspawn_args: ... Disassembly of section .comment: @@ -1143,25 +1191,25 @@ Disassembly of section .comment: 36: 6a 65 38: 63 74 2e 67 bgeu t3, s2, 1640 3c: 69 74 - 3e: 20 65 - 40: 66 33 - 42: 32 63 - 44: 36 31 - 46: 31 61 - 48: 61 32 - 4a: 31 34 - 4c: 64 65 - 4e: 61 38 - 50: 35 35 - 52: 33 36 34 65 - 56: 66 64 - 58: 37 62 61 34 lui tp, 214550 - 5c: 35 31 - 5e: 65 63 - 60: 35 65 - 62: 63 33 66 37 - 66: 34 29 - 68: 00 47 + 3e: 20 32 + 40: 61 32 + 42: 33 65 66 61 + 46: 63 33 35 32 + 4a: 66 39 + 4c: 31 39 + 4e: 65 62 + 50: 64 31 + 52: 65 63 + 54: 31 62 + 56: 65 34 + 58: 35 31 + 5a: 34 36 + 5c: 64 36 + 5e: 61 39 + 60: 66 61 + 62: 32 31 + 64: 62 35 + 66: 33 29 00 47 6a: 43 43 3a 20 fmadd.s ft6, fs4, ft3, ft4, rmm 6e: 28 47 70: 4e 55 @@ -1208,28 +1256,28 @@ Disassembly of section .symtab: 2c: 03 00 02 00 lb zero, 0(tp) 30: 00 00 32: 00 00 - 34: 14 20 + 34: bc 20 36: 00 80 38: 00 00 3a: 00 00 3c: 03 00 03 00 lb zero, 0(t1) 40: 00 00 42: 00 00 - 44: 18 20 + 44: c0 20 46: 00 80 48: 00 00 4a: 00 00 4c: 03 00 04 00 lb zero, 0(s0) 50: 00 00 52: 00 00 - 54: 40 24 + 54: e8 24 56: 00 80 58: 00 00 5a: 00 00 5c: 03 00 05 00 lb zero, 0(a0) 60: 00 00 62: 00 00 - 64: 44 24 + 64: ec 24 66: 00 80 68: 00 00 6a: 00 00 @@ -1245,347 +1293,361 @@ Disassembly of section .symtab: 9e: f1 ff a0: 0e 00 a2: 00 00 - a4: ac 06 + a4: cc 06 a6: 00 80 a8: 00 00 aa: 00 00 ac: 00 00 ae: 02 00 - b0: 15 00 - ... + b0: 1e 00 + b2: 00 00 + b4: 08 07 + b6: 00 80 + b8: 00 00 ba: 00 00 - bc: 04 00 - be: f1 ff + bc: 00 00 + be: 02 00 c0: 25 00 - c2: 00 00 - c4: 50 00 - c6: 00 80 - c8: 18 00 - ca: 00 00 - cc: 02 00 - ce: 02 00 - d0: 33 00 00 00 add zero, zero, zero ... - dc: 04 00 - de: f1 ff - e0: 57 00 00 00 + ca: 00 00 + cc: 04 00 + ce: f1 ff + d0: 35 00 + d2: 00 00 + d4: 50 00 + d6: 00 80 + d8: 18 00 + da: 00 00 + dc: 02 00 + de: 02 00 + e0: 43 00 00 00 fmadd.s ft0, ft0, ft0, ft0, rne ... ec: 04 00 ee: f1 ff - f0: 63 00 00 00 beqz zero, 0 + f0: 67 00 00 00 jr zero ... fc: 04 00 fe: f1 ff - 100: 6e 00 - 102: 00 00 - 104: b0 06 - 106: 00 80 - 108: 48 01 - 10a: 00 00 - 10c: 02 00 - 10e: 02 00 - 110: 84 00 + 100: 73 00 00 00 ecall + ... + 10c: 04 00 + 10e: f1 ff + 110: 81 00 ... 11a: 00 00 11c: 04 00 11e: f1 ff - 120: 9e 00 - ... + 120: 8c 00 + 122: 00 00 + 124: 04 08 + 126: 00 80 + 128: 3c 01 12a: 00 00 - 12c: 04 00 - 12e: f1 ff - 130: a0 00 - ... + 12c: 02 00 + 12e: 02 00 + 130: a2 00 + 132: 00 00 + 134: 40 09 + 136: 00 80 + 138: a4 00 13a: 00 00 - 13c: 04 00 - 13e: f1 ff - 140: 8e 00 - ... + 13c: 02 00 + 13e: 02 00 + 140: b8 00 + 142: 00 00 + 144: e4 09 + 146: 00 80 + 148: 2c 00 14a: 00 00 - 14c: 04 00 - 14e: f1 ff - 150: 95 00 + 14c: 02 00 + 14e: 02 00 + 150: cc 00 ... 15a: 00 00 15c: 04 00 15e: f1 ff - 160: 9c 00 + 160: d8 00 ... 16a: 00 00 16c: 04 00 16e: f1 ff - 170: a7 00 00 00 + 170: da 00 ... + 17a: 00 00 17c: 04 00 17e: f1 ff - 180: b0 00 - 182: 00 00 - 184: 18 20 - 186: 00 80 - 188: 28 04 - 18a: 00 00 - 18c: 01 00 - 18e: 04 00 + 180: d6 00 ... + 18a: 00 00 + 18c: 04 00 + 18e: f1 ff + 190: e1 00 + ... + 19a: 00 00 19c: 04 00 19e: f1 ff - 1a0: bc 00 + 1a0: ea 00 1a2: 00 00 - 1a4: 18 20 + 1a4: c0 20 1a6: 00 80 - 1a8: 00 00 + 1a8: 28 04 1aa: 00 00 - 1ac: 00 00 + 1ac: 01 00 1ae: 04 00 - 1b0: cd 00 - 1b2: 00 00 - 1b4: 18 20 - 1b6: 00 80 - 1b8: 00 00 - 1ba: 00 00 - 1bc: 00 00 - 1be: 04 00 - 1c0: e0 00 + ... + 1bc: 04 00 + 1be: f1 ff + 1c0: f6 00 1c2: 00 00 - 1c4: 18 20 + 1c4: c0 20 1c6: 00 80 1c8: 00 00 1ca: 00 00 1cc: 00 00 - 1ce: 03 00 f1 00 lb zero, 15(sp) - 1d2: 00 00 - 1d4: 14 20 + 1ce: 04 00 + 1d0: 07 01 00 00 + 1d4: c0 20 1d6: 00 80 1d8: 00 00 1da: 00 00 1dc: 00 00 - 1de: 03 00 05 01 lb zero, 16(a0) + 1de: 04 00 + 1e0: 1a 01 1e2: 00 00 - 1e4: 14 20 + 1e4: c0 20 1e6: 00 80 1e8: 00 00 1ea: 00 00 1ec: 00 00 - 1ee: 03 00 18 01 lb zero, 17(a6) + 1ee: 03 00 2b 01 lb zero, 18(s6) 1f2: 00 00 - 1f4: 14 20 + 1f4: bc 20 1f6: 00 80 1f8: 00 00 1fa: 00 00 1fc: 00 00 - 1fe: 03 00 2e 01 lb zero, 18(t3) - ... + 1fe: 03 00 3f 01 lb zero, 19(t5) + 202: 00 00 + 204: bc 20 + 206: 00 80 + 208: 00 00 20a: 00 00 - 20c: 10 00 - 20e: f1 ff - 210: 3c 01 + 20c: 00 00 + 20e: 03 00 52 01 lb zero, 21(tp) 212: 00 00 - 214: 00 04 - 216: 00 00 + 214: bc 20 + 216: 00 80 218: 00 00 21a: 00 00 - 21c: 10 00 - 21e: f1 ff - 220: 49 01 - 222: 00 00 - 224: 44 24 - 226: 00 80 - 228: 80 00 + 21c: 00 00 + 21e: 03 00 68 01 lb zero, 22(a6) + ... 22a: 00 00 - 22c: 11 00 - 22e: 06 00 - 230: 57 01 00 00 - 234: 40 24 - 236: 00 80 + 22c: 10 00 + 22e: f1 ff + 230: 76 01 + 232: 00 00 + 234: 00 04 + 236: 00 00 238: 00 00 23a: 00 00 23c: 10 00 - 23e: 05 00 - 240: 67 01 00 00 jalr sp, zero - 244: 18 28 + 23e: f1 ff + 240: 83 01 00 00 lb gp, 0(zero) + 244: ec 24 246: 00 80 - 248: 00 00 + 248: 80 00 24a: 00 00 - 24c: 10 00 - 24e: f1 ff - 250: 78 01 + 24c: 11 00 + 24e: 06 00 + 250: 91 01 252: 00 00 - 254: 7c 04 + 254: e8 24 256: 00 80 - 258: ec 01 + 258: 00 00 25a: 00 00 - 25c: 12 00 - 25e: 02 00 - 260: 99 01 + 25c: 10 00 + 25e: 05 00 + 260: a1 01 262: 00 00 - 264: 40 24 + 264: c0 28 266: 00 80 - 268: 04 00 + 268: 00 00 26a: 00 00 - 26c: 11 00 - 26e: 05 00 - 270: ac 01 + 26c: 10 00 + 26e: f1 ff + 270: b2 01 272: 00 00 - 274: dc 0c + 274: d4 04 276: 00 80 - 278: 9c 00 + 278: ec 01 27a: 00 00 27c: 12 00 27e: 02 00 - 280: be 01 - 282: 00 00 - 284: 80 0c + 280: d3 01 00 00 fadd.s ft3, ft0, ft0, rne + 284: e8 24 286: 00 80 - 288: 5c 00 + 288: 04 00 28a: 00 00 - 28c: 12 00 - 28e: 02 00 - 290: d0 01 + 28c: 11 00 + 28e: 05 00 + 290: e6 01 292: 00 00 - 294: 00 00 - 296: 00 ff - 298: 00 00 + 294: 0c 07 + 296: 00 80 + 298: 9c 00 29a: 00 00 - 29c: 10 00 - 29e: f1 ff - 2a0: dc 01 + 29c: 12 00 + 29e: 02 00 + 2a0: f8 01 2a2: 00 00 - 2a4: 74 06 + 2a4: a8 07 2a6: 00 80 - 2a8: 00 00 + 2a8: 5c 00 2aa: 00 00 2ac: 12 00 2ae: 02 00 - 2b0: e6 01 + 2b0: 0a 02 2b2: 00 00 - 2b4: 84 02 + 2b4: d8 06 2b6: 00 80 - 2b8: f8 01 + 2b8: 00 00 2ba: 00 00 2bc: 12 00 2be: 02 00 - 2c0: 02 02 + 2c0: 14 02 2c2: 00 00 - 2c4: f0 0e + 2c4: 84 02 2c6: 00 80 - 2c8: 24 01 + 2c8: 50 02 2ca: 00 00 2cc: 12 00 2ce: 02 00 - 2d0: 38 02 + 2d0: 30 02 2d2: 00 00 - 2d4: 00 00 + 2d4: 98 0f 2d6: 00 80 - 2d8: 50 00 + 2d8: 24 01 2da: 00 00 2dc: 12 00 - 2de: 01 00 - 2e0: 13 02 00 00 mv tp, zero - 2e4: 54 0e + 2de: 02 00 + 2e0: 66 02 + 2e2: 00 00 + 2e4: 00 00 2e6: 00 80 - 2e8: 9c 00 + 2e8: 50 00 2ea: 00 00 2ec: 12 00 - 2ee: 02 00 - 2f0: 27 02 00 00 - 2f4: c4 24 + 2ee: 01 00 + 2f0: 41 02 + 2f2: 00 00 + 2f4: fc 0e 2f6: 00 80 - 2f8: 00 00 + 2f8: 9c 00 2fa: 00 00 - 2fc: 10 00 - 2fe: 06 00 - 300: 33 02 00 00 add tp, zero, zero - 304: 44 24 + 2fc: 12 00 + 2fe: 02 00 + 300: 55 02 + 302: 00 00 + 304: 6c 25 306: 00 80 308: 00 00 30a: 00 00 30c: 10 00 30e: 06 00 - 310: 3f 02 00 00 - 314: 78 0d + 310: 61 02 + 312: 00 00 + 314: ec 24 316: 00 80 - 318: dc 00 + 318: 00 00 31a: 00 00 - 31c: 12 00 - 31e: 02 00 - 320: 46 02 + 31c: 10 00 + 31e: 06 00 + 320: 6d 02 322: 00 00 - 324: 68 00 + 324: 20 0e 326: 00 80 - 328: 30 00 + 328: dc 00 32a: 00 00 32c: 12 00 32e: 02 00 - 330: 4b 02 00 00 fnmsub.s ft4, ft0, ft0, ft0, rne - 334: 38 0c + 330: 74 02 + 332: 00 00 + 334: 68 00 336: 00 80 - 338: 14 00 + 338: 30 00 33a: 00 00 33c: 12 00 33e: 02 00 - 340: 52 02 + 340: 79 02 342: 00 00 - 344: 18 20 + 344: d8 0d 346: 00 80 - 348: 00 00 + 348: 14 00 34a: 00 00 - 34c: 10 00 - 34e: 04 00 - 350: 61 02 + 34c: 12 00 + 34e: 02 00 + 350: 80 02 352: 00 00 - 354: 44 24 + 354: c0 20 356: 00 80 358: 00 00 35a: 00 00 35c: 10 00 - 35e: 05 00 - 360: c8 00 - 362: 00 00 - 364: c4 24 + 35e: 04 00 + 360: 8f 02 00 00 + 364: ec 24 366: 00 80 368: 00 00 36a: 00 00 36c: 10 00 - 36e: 06 00 - 370: 76 02 + 36e: 05 00 + 370: 02 01 372: 00 00 - 374: 4c 0c + 374: 6c 25 376: 00 80 - 378: 34 00 + 378: 00 00 37a: 00 00 - 37c: 12 00 - 37e: 02 00 - 380: 68 02 + 37c: 10 00 + 37e: 06 00 + 380: a4 02 382: 00 00 - 384: 24 0a + 384: ec 0d 386: 00 80 - 388: 14 02 + 388: 34 00 38a: 00 00 38c: 12 00 38e: 02 00 - 390: 75 02 + 390: 96 02 392: 00 00 - 394: 68 06 + 394: c4 0b 396: 00 80 - 398: 00 00 + 398: 14 02 39a: 00 00 39c: 12 00 39e: 02 00 - 3a0: 7b 02 00 00 - 3a4: 98 00 + 3a0: a3 02 00 00 sb zero, 5(zero) + 3a4: c0 06 3a6: 00 80 - 3a8: ec 01 + 3a8: 00 00 3aa: 00 00 3ac: 12 00 3ae: 02 00 - 3b0: 8d 02 + 3b0: a9 02 3b2: 00 00 - 3b4: f8 07 + 3b4: 98 00 3b6: 00 80 - 3b8: 2c 02 + 3b8: ec 01 3ba: 00 00 3bc: 12 00 3be: 02 00 + 3c0: bb 02 00 00 + 3c4: 10 0a + 3c6: 00 80 + 3c8: b4 01 + 3ca: 00 00 + 3cc: 12 00 + 3ce: 02 00 Disassembly of section .strtab: @@ -1595,255 +1657,271 @@ Disassembly of section .strtab: 4: 73 74 61 72 csrrci s0, 1830, 2 8: 74 2e a: 53 2e 6f 00 fadd.s ft8, ft10, ft6, rdn - e: 52 45 - 10: 54 55 - 12: 52 4e - 14: 00 5f - 16: 5f 63 61 6c - 1a: 6c 5f - 1c: 61 74 - 1e: 65 78 - 20: 69 74 - 22: 2e 63 - 24: 00 72 - 26: 65 67 - 28: 69 73 - 2a: 74 65 - 2c: 72 5f - 2e: 66 69 - 30: 6e 69 - 32: 00 70 - 34: 6f 63 6c 5f jal t1, 812534 - 38: 76 6f - 3a: 72 74 - 3c: 65 78 - 3e: 5f 6b 65 72 - 42: 6e 65 - 44: 6c 2d - 46: 36 64 - 48: 2d 34 - 4a: 62 2d - 4c: 63 63 2d 33 bltu s10, s2, 806 - 50: 62 2d - 52: 37 62 2e 63 lui tp, 406246 - 56: 00 70 - 58: 61 72 - 5a: 61 6c - 5c: 6c 65 - 5e: 6c 5f - 60: 62 63 - 62: 00 76 - 64: 78 5f - 66: 73 70 61 77 csrci 1910, 2 - 6a: 6e 2e - 6c: 63 00 73 70 beq t1, t2, 1792 - 70: 61 77 - 72: 6e 5f - 74: 6b 65 72 6e - 78: 65 6c - 7a: 5f 63 61 6c - 7e: 6c 62 - 80: 61 63 - 82: 6b 00 76 78 - 86: 5f 70 65 72 - 8a: 66 2e - 8c: 63 00 66 69 beq a2, s6, 1664 - 90: 6e 69 - 92: 2e 63 - 94: 00 69 - 96: 6e 69 - 98: 74 2e - 9a: 63 00 5f 5f beq t5, s5, 1504 - 9e: 61 74 - a0: 65 78 - a2: 69 74 - a4: 2e 63 - a6: 00 69 - a8: 6d 70 - aa: 75 72 - ac: 65 2e - ae: 63 00 69 6d beq s2, s6, 1728 - b2: 70 75 - b4: 72 65 - b6: 5f 64 61 74 - ba: 61 00 - bc: 5f 5f 66 69 - c0: 6e 69 - c2: 5f 61 72 72 - c6: 61 79 - c8: 5f 65 6e 64 - cc: 00 5f - ce: 5f 66 69 6e - d2: 69 5f - d4: 61 72 - d6: 72 61 - d8: 79 5f - da: 73 74 61 72 csrrci s0, 1830, 2 - de: 74 00 - e0: 5f 5f 69 6e - e4: 69 74 - e6: 5f 61 72 72 - ea: 61 79 - ec: 5f 65 6e 64 - f0: 00 5f - f2: 5f 70 72 65 - f6: 69 6e - f8: 69 74 - fa: 5f 61 72 72 - fe: 61 79 - 100: 5f 65 6e 64 - 104: 00 5f - 106: 5f 69 6e 69 - 10a: 74 5f - 10c: 61 72 - 10e: 72 61 - 110: 79 5f - 112: 73 74 61 72 csrrci s0, 1830, 2 - 116: 74 00 - 118: 5f 5f 70 72 - 11c: 65 69 - 11e: 6e 69 - 120: 74 5f - 122: 61 72 - 124: 72 61 - 126: 79 5f - 128: 73 74 61 72 csrrci s0, 1830, 2 - 12c: 74 00 - 12e: 5f 5f 73 74 - 132: 61 63 - 134: 6b 5f 75 73 - 138: 61 67 - 13a: 65 00 - 13c: 5f 5f 73 74 - 140: 61 63 - 142: 6b 5f 73 69 - 146: 7a 65 - 148: 00 67 - 14a: 5f 77 73 70 - 14e: 61 77 - 150: 6e 5f - 152: 61 72 - 154: 67 73 00 5f - 158: 5f 53 44 41 - 15c: 54 41 - 15e: 5f 42 45 47 - 162: 49 4e - 164: 5f 5f 00 5f - 168: 5f 67 6c 6f - 16c: 62 61 - 16e: 6c 5f - 170: 70 6f - 172: 69 6e - 174: 74 65 - 176: 72 00 - 178: 5f 70 6f 63 - 17c: 6c 5f - 17e: 6b 65 72 6e - 182: 65 6c - 184: 5f 46 61 6e - 188: 32 5f - 18a: 77 6f 72 6b - 18e: 67 72 6f 75 - 192: 70 5f - 194: 66 61 - 196: 73 74 00 5f csrrci s0, 1520, 0 - 19a: 67 6c 6f 62 - 19e: 61 6c - 1a0: 5f 69 6d 70 - 1a4: 75 72 - 1a6: 65 5f - 1a8: 70 74 - 1aa: 72 00 - 1ac: 5f 5f 6c 69 - 1b0: 62 63 - 1b2: 5f 69 6e 69 - 1b6: 74 5f - 1b8: 61 72 - 1ba: 72 61 - 1bc: 79 00 - 1be: 5f 5f 6c 69 - 1c2: 62 63 - 1c4: 5f 66 69 6e - 1c8: 69 5f - 1ca: 61 72 - 1cc: 72 61 - 1ce: 79 00 - 1d0: 5f 5f 73 74 - 1d4: 61 63 - 1d6: 6b 5f 74 6f - 1da: 70 00 - 1dc: 76 78 - 1de: 5f 73 65 74 - 1e2: 5f 73 70 00 - 1e6: 5f 70 6f 63 - 1ea: 6c 5f - 1ec: 6b 65 72 6e - 1f0: 65 6c - 1f2: 5f 46 61 6e - 1f6: 32 5f - 1f8: 77 6f 72 6b - 1fc: 67 72 6f 75 - 200: 70 00 - 202: 5f 5f 63 61 - 206: 6c 6c - 208: 5f 65 78 69 - 20c: 74 70 - 20e: 72 6f - 210: 63 73 00 5f bgeu zero, a6, 1510 - 214: 5f 72 65 67 - 218: 69 73 - 21a: 74 65 - 21c: 72 5f - 21e: 65 78 - 220: 69 74 - 222: 70 72 - 224: 6f 63 00 5f jal t1, 26096 - 228: 5f 42 53 53 - 22c: 5f 45 4e 44 - 230: 5f 5f 00 5f - 234: 5f 62 73 73 - 238: 5f 73 74 61 - 23c: 72 74 - 23e: 00 6d - 240: 65 6d - 242: 73 65 74 00 csrrsi a0, 7, 8 - 246: 6d 61 - 248: 69 6e - 24a: 00 61 - 24c: 74 65 - 24e: 78 69 - 250: 74 00 - 252: 5f 5f 44 41 - 256: 54 41 - 258: 5f 42 45 47 - 25c: 49 4e + e: 6c 61 + 10: 62 65 + 12: 6c 5f + 14: 65 78 + 16: 69 74 + 18: 5f 6e 65 78 + 1c: 74 00 + 1e: 52 45 + 20: 54 55 + 22: 52 4e + 24: 00 5f + 26: 5f 63 61 6c + 2a: 6c 5f + 2c: 61 74 + 2e: 65 78 + 30: 69 74 + 32: 2e 63 + 34: 00 72 + 36: 65 67 + 38: 69 73 + 3a: 74 65 + 3c: 72 5f + 3e: 66 69 + 40: 6e 69 + 42: 00 70 + 44: 6f 63 6c 5f jal t1, 812534 + 48: 76 6f + 4a: 72 74 + 4c: 65 78 + 4e: 5f 6b 65 72 + 52: 6e 65 + 54: 6c 2d + 56: 63 39 2d 61 + 5a: 65 2d + 5c: 32 66 + 5e: 2d 36 + 60: 37 2d 32 35 lui s10, 217890 + 64: 2e 63 + 66: 00 70 + 68: 61 72 + 6a: 61 6c + 6c: 6c 65 + 6e: 6c 5f + 70: 62 63 + 72: 00 76 + 74: 78 5f + 76: 73 79 73 63 csrrci s2, 1591, 6 + 7a: 61 6c + 7c: 6c 73 + 7e: 2e 63 + 80: 00 76 + 82: 78 5f + 84: 73 70 61 77 csrci 1910, 2 + 88: 6e 2e + 8a: 63 00 73 70 beq t1, t2, 1792 + 8e: 61 77 + 90: 6e 5f + 92: 6b 65 72 6e + 96: 65 6c + 98: 5f 61 6c 6c + 9c: 5f 73 74 75 + a0: 62 00 + a2: 73 70 61 77 csrci 1910, 2 + a6: 6e 5f + a8: 6b 65 72 6e + ac: 65 6c + ae: 5f 72 65 6d + b2: 5f 73 74 75 + b6: 62 00 + b8: 73 70 61 77 csrci 1910, 2 + bc: 6e 5f + be: 6b 65 72 6e + c2: 65 6c + c4: 5f 61 6c 6c + c8: 5f 63 62 00 + cc: 76 78 + ce: 5f 70 65 72 + d2: 66 2e + d4: 63 00 5f 5f beq t5, s5, 1504 + d8: 61 74 + da: 65 78 + dc: 69 74 + de: 2e 63 + e0: 00 69 + e2: 6d 70 + e4: 75 72 + e6: 65 2e + e8: 63 00 69 6d beq s2, s6, 1728 + ec: 70 75 + ee: 72 65 + f0: 5f 64 61 74 + f4: 61 00 + f6: 5f 5f 66 69 + fa: 6e 69 + fc: 5f 61 72 72 + 100: 61 79 + 102: 5f 65 6e 64 + 106: 00 5f + 108: 5f 66 69 6e + 10c: 69 5f + 10e: 61 72 + 110: 72 61 + 112: 79 5f + 114: 73 74 61 72 csrrci s0, 1830, 2 + 118: 74 00 + 11a: 5f 5f 69 6e + 11e: 69 74 + 120: 5f 61 72 72 + 124: 61 79 + 126: 5f 65 6e 64 + 12a: 00 5f + 12c: 5f 70 72 65 + 130: 69 6e + 132: 69 74 + 134: 5f 61 72 72 + 138: 61 79 + 13a: 5f 65 6e 64 + 13e: 00 5f + 140: 5f 69 6e 69 + 144: 74 5f + 146: 61 72 + 148: 72 61 + 14a: 79 5f + 14c: 73 74 61 72 csrrci s0, 1830, 2 + 150: 74 00 + 152: 5f 5f 70 72 + 156: 65 69 + 158: 6e 69 + 15a: 74 5f + 15c: 61 72 + 15e: 72 61 + 160: 79 5f + 162: 73 74 61 72 csrrci s0, 1830, 2 + 166: 74 00 + 168: 5f 5f 73 74 + 16c: 61 63 + 16e: 6b 5f 75 73 + 172: 61 67 + 174: 65 00 + 176: 5f 5f 73 74 + 17a: 61 63 + 17c: 6b 5f 73 69 + 180: 7a 65 + 182: 00 67 + 184: 5f 77 73 70 + 188: 61 77 + 18a: 6e 5f + 18c: 61 72 + 18e: 67 73 00 5f + 192: 5f 53 44 41 + 196: 54 41 + 198: 5f 42 45 47 + 19c: 49 4e + 19e: 5f 5f 00 5f + 1a2: 5f 67 6c 6f + 1a6: 62 61 + 1a8: 6c 5f + 1aa: 70 6f + 1ac: 69 6e + 1ae: 74 65 + 1b0: 72 00 + 1b2: 5f 70 6f 63 + 1b6: 6c 5f + 1b8: 6b 65 72 6e + 1bc: 65 6c + 1be: 5f 46 61 6e + 1c2: 32 5f + 1c4: 77 6f 72 6b + 1c8: 67 72 6f 75 + 1cc: 70 5f + 1ce: 66 61 + 1d0: 73 74 00 5f csrrci s0, 1520, 0 + 1d4: 67 6c 6f 62 + 1d8: 61 6c + 1da: 5f 69 6d 70 + 1de: 75 72 + 1e0: 65 5f + 1e2: 70 74 + 1e4: 72 00 + 1e6: 5f 5f 6c 69 + 1ea: 62 63 + 1ec: 5f 69 6e 69 + 1f0: 74 5f + 1f2: 61 72 + 1f4: 72 61 + 1f6: 79 00 + 1f8: 5f 5f 6c 69 + 1fc: 62 63 + 1fe: 5f 66 69 6e + 202: 69 5f + 204: 61 72 + 206: 72 61 + 208: 79 00 + 20a: 76 78 + 20c: 5f 73 65 74 + 210: 5f 73 70 00 + 214: 5f 70 6f 63 + 218: 6c 5f + 21a: 6b 65 72 6e + 21e: 65 6c + 220: 5f 46 61 6e + 224: 32 5f + 226: 77 6f 72 6b + 22a: 67 72 6f 75 + 22e: 70 00 + 230: 5f 5f 63 61 + 234: 6c 6c + 236: 5f 65 78 69 + 23a: 74 70 + 23c: 72 6f + 23e: 63 73 00 5f bgeu zero, a6, 1510 + 242: 5f 72 65 67 + 246: 69 73 + 248: 74 65 + 24a: 72 5f + 24c: 65 78 + 24e: 69 74 + 250: 70 72 + 252: 6f 63 00 5f jal t1, 26096 + 256: 5f 42 53 53 + 25a: 5f 45 4e 44 25e: 5f 5f 00 5f - 262: 65 64 - 264: 61 74 - 266: 61 00 - 268: 76 78 - 26a: 5f 70 65 72 - 26e: 66 5f - 270: 64 75 - 272: 6d 70 - 274: 00 5f - 276: 65 78 - 278: 69 74 - 27a: 00 5f - 27c: 70 6f - 27e: 63 6c 5f 6b bltu t5, s5, 1720 - 282: 65 72 - 284: 6e 65 - 286: 6c 5f - 288: 46 61 - 28a: 6e 32 - 28c: 00 76 - 28e: 78 5f - 290: 73 70 61 77 csrci 1910, 2 - 294: 6e 5f - 296: 6b 65 72 6e - 29a: 65 6c - 29c: 00 + 262: 5f 62 73 73 + 266: 5f 73 74 61 + 26a: 72 74 + 26c: 00 6d + 26e: 65 6d + 270: 73 65 74 00 csrrsi a0, 7, 8 + 274: 6d 61 + 276: 69 6e + 278: 00 61 + 27a: 74 65 + 27c: 78 69 + 27e: 74 00 + 280: 5f 5f 44 41 + 284: 54 41 + 286: 5f 42 45 47 + 28a: 49 4e + 28c: 5f 5f 00 5f + 290: 65 64 + 292: 61 74 + 294: 61 00 + 296: 76 78 + 298: 5f 70 65 72 + 29c: 66 5f + 29e: 64 75 + 2a0: 6d 70 + 2a2: 00 5f + 2a4: 65 78 + 2a6: 69 74 + 2a8: 00 5f + 2aa: 70 6f + 2ac: 63 6c 5f 6b bltu t5, s5, 1720 + 2b0: 65 72 + 2b2: 6e 65 + 2b4: 6c 5f + 2b6: 46 61 + 2b8: 6e 32 + 2ba: 00 76 + 2bc: 78 5f + 2be: 73 70 61 77 csrci 1910, 2 + 2c2: 6e 5f + 2c4: 6b 65 72 6e + 2c8: 65 6c + 2ca: 00 Disassembly of section .shstrtab: diff --git a/tests/opencl/guassian/Makefile b/tests/opencl/guassian/Makefile index dd98e5dd..01be4ae5 100644 --- a/tests/opencl/guassian/Makefile +++ b/tests/opencl/guassian/Makefile @@ -7,8 +7,8 @@ POCL_RT_PATH ?= /opt/pocl/runtime VORTEX_DRV_PATH ?= $(realpath ../../../driver) VORTEX_RT_PATH ?= $(realpath ../../../runtime) -K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -float-abi=hard -code-model=small" -K_CFLAGS += "-v -O3 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" +K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -mattr=+vortex -float-abi=hard -code-model=small" +K_CFLAGS += "-v -O3 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -Xclang -target-feature -Xclang +vortex -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" K_LDFLAGS += "-Wl,-Bstatic,-T$(VORTEX_RT_PATH)/linker/vx_link.ld -Wl,--gc-sections $(VORTEX_RT_PATH)/libvortexrt.a -lm" CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors @@ -34,13 +34,13 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ run-fpga: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) run-asesim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) run-vlsim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) run-simx: $(PROJECT) kernel.pocl LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) diff --git a/tests/opencl/guassian/kernel.pocl b/tests/opencl/guassian/kernel.pocl index 2b6f5843..faa860a0 100644 Binary files a/tests/opencl/guassian/kernel.pocl and b/tests/opencl/guassian/kernel.pocl differ diff --git a/tests/opencl/kmeans/Makefile b/tests/opencl/kmeans/Makefile index fee9950b..8251d75a 100644 --- a/tests/opencl/kmeans/Makefile +++ b/tests/opencl/kmeans/Makefile @@ -7,8 +7,8 @@ POCL_RT_PATH ?= /opt/pocl/runtime VORTEX_DRV_PATH ?= $(realpath ../../../driver) VORTEX_RT_PATH ?= $(realpath ../../../runtime) -K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -float-abi=hard -code-model=small" -K_CFLAGS += "-v -O3 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" +K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -mattr=+vortex -float-abi=hard -code-model=small" +K_CFLAGS += "-v -O3 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -Xclang -target-feature -Xclang +vortex -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" K_LDFLAGS += "-Wl,-Bstatic,-T$(VORTEX_RT_PATH)/linker/vx_link.ld -Wl,--gc-sections $(VORTEX_RT_PATH)/libvortexrt.a -lm" CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -pedantic -Wfatal-errors @@ -31,13 +31,13 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ run-fpga: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) run-asesim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) run-vlsim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) run-simx: $(PROJECT) kernel.pocl LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) diff --git a/tests/opencl/nearn/Makefile b/tests/opencl/nearn/Makefile index 84045f59..52d20b38 100644 --- a/tests/opencl/nearn/Makefile +++ b/tests/opencl/nearn/Makefile @@ -9,8 +9,8 @@ OPTS ?= filelist.txt VORTEX_DRV_PATH ?= $(realpath ../../../driver) VORTEX_RT_PATH ?= $(realpath ../../../runtime) -K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -float-abi=hard -code-model=small" -K_CFLAGS += "-v -O3 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" +K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -mattr=+vortex -float-abi=hard -code-model=small" +K_CFLAGS += "-v -O3 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -Xclang -target-feature -Xclang +vortex -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" K_LDFLAGS += "-Wl,-Bstatic,-T$(VORTEX_RT_PATH)/linker/vx_link.ld -Wl,--gc-sections $(VORTEX_RT_PATH)/libvortexrt.a -lm" CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors @@ -36,13 +36,13 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ run-fpga: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-simx: $(PROJECT) kernel.pocl LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/opencl/nearn/NearestNeighbor.dump b/tests/opencl/nearn/NearestNeighbor.dump index 6f6a9b57..57cd207a 100644 --- a/tests/opencl/nearn/NearestNeighbor.dump +++ b/tests/opencl/nearn/NearestNeighbor.dump @@ -1,39 +1,39 @@ -/tmp/pocl_vortex_kernel-f1-04-b2-42-7e.elf: file format ELF32-riscv +/tmp/pocl_vortex_kernel-9a-fe-0b-0c-9e.elf: file format ELF32-riscv Disassembly of section .init: 80000000 _start: 80000000: 97 05 00 00 auipc a1, 0 -80000004: 93 85 c5 49 addi a1, a1, 1180 +80000004: 93 85 45 4c addi a1, a1, 1220 80000008: 73 25 10 fc csrr a0, 4033 -8000000c: 6b 10 b5 00 -80000010: ef 00 c0 48 jal 1164 +8000000c: 6b 10 b5 00 vx_wspawn a0, a1 +80000010: ef 00 40 4b jal 1204 80000014: 13 05 10 00 addi a0, zero, 1 -80000018: 6b 00 05 00 -8000001c: 17 15 00 00 auipc a0, 1 -80000020: 13 05 c5 41 addi a0, a0, 1052 -80000024: 17 16 00 00 auipc a2, 1 -80000028: 13 06 86 49 addi a2, a2, 1176 +80000018: 6b 00 05 00 vx_tmc a0 +8000001c: 17 25 00 00 auipc a0, 2 +80000020: 13 05 c5 44 addi a0, a0, 1100 +80000024: 17 26 00 00 auipc a2, 2 +80000028: 13 06 86 4c addi a2, a2, 1224 8000002c: 33 06 a6 40 sub a2, a2, a0 80000030: 93 05 00 00 mv a1, zero -80000034: ef 00 90 4f jal 3320 -80000038: 17 15 00 00 auipc a0, 1 -8000003c: 13 05 c5 bf addi a0, a0, -1028 -80000040: ef 00 10 3a jal 2976 -80000044: ef 00 d0 44 jal 3148 +80000034: ef 00 50 56 jal 3428 +80000038: 17 05 00 00 auipc a0, 0 +8000003c: 13 05 c5 55 addi a0, a0, 1372 +80000040: ef 00 50 50 jal 3332 +80000044: ef 00 40 4b jal 1204 80000048: ef 00 00 02 jal 32 -8000004c: 6f 00 50 3b j 2996 +8000004c: 6f 00 90 51 j 3352 Disassembly of section .text: 80000050 register_fini: 80000050: 93 07 00 00 mv a5, zero 80000054: 63 88 07 00 beqz a5, 16 -80000058: 37 15 00 80 lui a0, 524289 -8000005c: 13 05 45 c3 addi a0, a0, -972 -80000060: 6f 00 10 38 j 2944 +80000058: 37 05 00 80 lui a0, 524288 +8000005c: 13 05 45 59 addi a0, a0, 1428 +80000060: 6f 00 50 4e j 3300 80000064: 67 80 00 00 ret 80000068 main: @@ -44,7 +44,7 @@ Disassembly of section .text: 80000078: 37 05 ff 7f lui a0, 524272 8000007c: 13 06 45 03 addi a2, a0, 52 80000080: 37 05 ff 7f lui a0, 524272 -80000084: ef 00 c0 59 jal 1436 +80000084: ef 00 80 77 jal 1912 80000088: 13 05 00 00 mv a0, zero 8000008c: 83 20 c1 00 lw ra, 12(sp) 80000090: 13 01 01 01 addi sp, sp, 16 @@ -59,7 +59,7 @@ Disassembly of section .text: 800000ac: 83 20 c1 00 lw ra, 12(sp) 800000b0: 13 01 01 01 addi sp, sp, 16 800000b4: 17 13 00 00 auipc t1, 1 -800000b8: 67 00 c3 9a jr -1620(t1) +800000b8: 67 00 03 b1 jr -1264(t1) 800000bc _pocl_kernel_NearestNeighbor: 800000bc: 13 01 01 fc addi sp, sp, -64 @@ -169,948 +169,981 @@ Disassembly of section .text: 80000254: 83 24 c5 00 lw s1, 12(a0) 80000258: 03 25 05 01 lw a0, 16(a0) 8000025c: 03 27 07 00 lw a4, 0(a4) -80000260: 83 aa 07 00 lw s5, 0(a5) +80000260: 83 ad 07 00 lw s11, 0(a5) 80000264: 07 a4 04 00 flw fs0, 0(s1) 80000268: 87 24 05 00 flw fs1, 0(a0) -8000026c: 83 ac 85 01 lw s9, 24(a1) +8000026c: 83 aa 85 01 lw s5, 24(a1) 80000270: 03 a5 c5 00 lw a0, 12(a1) 80000274: 83 a9 c5 01 lw s3, 28(a1) -80000278: 03 aa 05 02 lw s4, 32(a1) -8000027c: b3 85 cc 02 mul a1, s9, a2 -80000280: 33 0d b5 00 add s10, a0, a1 -80000284: 13 15 3d 00 slli a0, s10, 3 -80000288: 33 85 a6 00 add a0, a3, a0 -8000028c: 93 15 2d 00 slli a1, s10, 2 -80000290: 33 0b b7 00 add s6, a4, a1 -80000294: 93 0b 45 00 addi s7, a0, 4 -80000298: 6f 00 c0 00 j 12 -8000029c: 13 09 19 00 addi s2, s2, 1 -800002a0: 63 74 49 07 bgeu s2, s4, 104 -800002a4: 13 0c 00 00 mv s8, zero -800002a8: 6f 00 c0 00 j 12 -800002ac: 13 0c 1c 00 addi s8, s8, 1 -800002b0: e3 76 3c ff bgeu s8, s3, -20 -800002b4: 13 04 00 00 mv s0, zero -800002b8: 93 0d 0b 00 mv s11, s6 -800002bc: 93 84 0b 00 mv s1, s7 -800002c0: 6f 00 40 01 j 20 -800002c4: 13 04 14 00 addi s0, s0, 1 -800002c8: 93 84 84 00 addi s1, s1, 8 -800002cc: 93 8d 4d 00 addi s11, s11, 4 -800002d0: e3 7e 94 fd bgeu s0, s9, -36 -800002d4: 33 05 8d 00 add a0, s10, s0 -800002d8: e3 56 55 ff bge a0, s5, -20 -800002dc: 07 a0 c4 ff flw ft0, -4(s1) -800002e0: 87 a0 04 00 flw ft1, 0(s1) -800002e4: 53 70 04 08 fsub.s ft0, fs0, ft0 -800002e8: d3 f0 14 08 fsub.s ft1, fs1, ft1 -800002ec: d3 f0 10 10 fmul.s ft1, ft1, ft1 -800002f0: 53 70 00 10 fmul.s ft0, ft0, ft0 -800002f4: 53 75 10 00 fadd.s fa0, ft0, ft1 -800002f8: 97 00 00 00 auipc ra, 0 -800002fc: e7 80 00 da jalr -608(ra) -80000300: 27 a0 ad 00 fsw fa0, 0(s11) -80000304: 6f f0 1f fc j -64 -80000308: 87 24 41 00 flw fs1, 4(sp) -8000030c: 07 24 81 00 flw fs0, 8(sp) -80000310: 83 2d c1 00 lw s11, 12(sp) -80000314: 03 2d 01 01 lw s10, 16(sp) -80000318: 83 2c 41 01 lw s9, 20(sp) -8000031c: 03 2c 81 01 lw s8, 24(sp) -80000320: 83 2b c1 01 lw s7, 28(sp) -80000324: 03 2b 01 02 lw s6, 32(sp) -80000328: 83 2a 41 02 lw s5, 36(sp) -8000032c: 03 2a 81 02 lw s4, 40(sp) -80000330: 83 29 c1 02 lw s3, 44(sp) -80000334: 03 29 01 03 lw s2, 48(sp) -80000338: 83 24 41 03 lw s1, 52(sp) -8000033c: 03 24 81 03 lw s0, 56(sp) -80000340: 83 20 c1 03 lw ra, 60(sp) -80000344: 13 01 01 04 addi sp, sp, 64 -80000348: 67 80 00 00 ret +80000278: 83 a5 05 02 lw a1, 32(a1) +8000027c: 23 20 b1 00 sw a1, 0(sp) +80000280: b3 85 ca 02 mul a1, s5, a2 +80000284: 33 0d b5 00 add s10, a0, a1 +80000288: 13 15 3d 00 slli a0, s10, 3 +8000028c: 33 85 a6 00 add a0, a3, a0 +80000290: 93 15 2d 00 slli a1, s10, 2 +80000294: 33 0b b7 00 add s6, a4, a1 +80000298: 13 0a 45 00 addi s4, a0, 4 +8000029c: 6f 00 00 01 j 16 +800002a0: 13 09 19 00 addi s2, s2, 1 +800002a4: 03 25 01 00 lw a0, 0(sp) +800002a8: 63 7e a9 06 bgeu s2, a0, 124 +800002ac: 13 0c 00 00 mv s8, zero +800002b0: 6f 00 00 01 j 16 +800002b4: 6b 80 0c 00 vx_tmc s9 +800002b8: 13 0c 1c 00 addi s8, s8, 1 +800002bc: e3 72 3c ff bgeu s8, s3, -28 +800002c0: 13 04 00 00 mv s0, zero +800002c4: f3 2c 40 cc csrr s9, tmask +800002c8: 93 04 0b 00 mv s1, s6 +800002cc: 93 0b 0a 00 mv s7, s4 +800002d0: 6f 00 80 01 j 24 +800002d4: 6b 30 00 00 vx_join +800002d8: 13 04 14 00 addi s0, s0, 1 +800002dc: 93 8b 8b 00 addi s7, s7, 8 +800002e0: 93 84 44 00 addi s1, s1, 4 +800002e4: e3 78 54 fd bgeu s0, s5, -48 +800002e8: 33 05 8d 00 add a0, s10, s0 +800002ec: b3 25 b5 01 slt a1, a0, s11 +800002f0: 6b a0 05 00 vx_split a1 +800002f4: e3 50 b5 ff bge a0, s11, -32 +800002f8: 07 a0 cb ff flw ft0, -4(s7) +800002fc: 87 a0 0b 00 flw ft1, 0(s7) +80000300: 53 70 04 08 fsub.s ft0, fs0, ft0 +80000304: d3 f0 14 08 fsub.s ft1, fs1, ft1 +80000308: d3 f0 10 10 fmul.s ft1, ft1, ft1 +8000030c: 53 70 00 10 fmul.s ft0, ft0, ft0 +80000310: 53 75 10 00 fadd.s fa0, ft0, ft1 +80000314: 97 00 00 00 auipc ra, 0 +80000318: e7 80 40 d8 jalr -636(ra) +8000031c: 27 a0 a4 00 fsw fa0, 0(s1) +80000320: 6f f0 5f fb j -76 +80000324: 87 24 41 00 flw fs1, 4(sp) +80000328: 07 24 81 00 flw fs0, 8(sp) +8000032c: 83 2d c1 00 lw s11, 12(sp) +80000330: 03 2d 01 01 lw s10, 16(sp) +80000334: 83 2c 41 01 lw s9, 20(sp) +80000338: 03 2c 81 01 lw s8, 24(sp) +8000033c: 83 2b c1 01 lw s7, 28(sp) +80000340: 03 2b 01 02 lw s6, 32(sp) +80000344: 83 2a 41 02 lw s5, 36(sp) +80000348: 03 2a 81 02 lw s4, 40(sp) +8000034c: 83 29 c1 02 lw s3, 44(sp) +80000350: 03 29 01 03 lw s2, 48(sp) +80000354: 83 24 41 03 lw s1, 52(sp) +80000358: 03 24 81 03 lw s0, 56(sp) +8000035c: 83 20 c1 03 lw ra, 60(sp) +80000360: 13 01 01 04 addi sp, sp, 64 +80000364: 67 80 00 00 ret -8000034c _pocl_kernel_NearestNeighbor_workgroup_fast: -8000034c: 13 01 01 fc addi sp, sp, -64 -80000350: 23 2e 11 02 sw ra, 60(sp) -80000354: 23 2c 81 02 sw s0, 56(sp) -80000358: 23 2a 91 02 sw s1, 52(sp) -8000035c: 23 28 21 03 sw s2, 48(sp) -80000360: 23 26 31 03 sw s3, 44(sp) -80000364: 23 24 41 03 sw s4, 40(sp) -80000368: 23 22 51 03 sw s5, 36(sp) -8000036c: 23 20 61 03 sw s6, 32(sp) -80000370: 23 2e 71 01 sw s7, 28(sp) -80000374: 23 2c 81 01 sw s8, 24(sp) -80000378: 23 2a 91 01 sw s9, 20(sp) -8000037c: 23 28 a1 01 sw s10, 16(sp) -80000380: 23 26 b1 01 sw s11, 12(sp) -80000384: 27 24 81 00 fsw fs0, 8(sp) -80000388: 27 22 91 00 fsw fs1, 4(sp) -8000038c: 13 09 00 00 mv s2, zero -80000390: 83 26 05 00 lw a3, 0(a0) -80000394: 03 27 85 00 lw a4, 8(a0) -80000398: 83 27 c5 00 lw a5, 12(a0) -8000039c: 83 24 05 01 lw s1, 16(a0) -800003a0: 03 25 45 00 lw a0, 4(a0) -800003a4: 83 2a 07 00 lw s5, 0(a4) -800003a8: 07 a4 07 00 flw fs0, 0(a5) -800003ac: 87 a4 04 00 flw fs1, 0(s1) -800003b0: 83 ac 85 01 lw s9, 24(a1) -800003b4: 03 a7 c5 00 lw a4, 12(a1) -800003b8: 83 a9 c5 01 lw s3, 28(a1) -800003bc: 03 aa 05 02 lw s4, 32(a1) -800003c0: b3 85 cc 02 mul a1, s9, a2 -800003c4: 33 0d b7 00 add s10, a4, a1 -800003c8: 93 15 3d 00 slli a1, s10, 3 -800003cc: b3 85 b6 00 add a1, a3, a1 -800003d0: 13 16 2d 00 slli a2, s10, 2 -800003d4: 33 0b c5 00 add s6, a0, a2 -800003d8: 93 8b 45 00 addi s7, a1, 4 -800003dc: 6f 00 c0 00 j 12 -800003e0: 13 09 19 00 addi s2, s2, 1 -800003e4: 63 74 49 07 bgeu s2, s4, 104 -800003e8: 13 0c 00 00 mv s8, zero -800003ec: 6f 00 c0 00 j 12 -800003f0: 13 0c 1c 00 addi s8, s8, 1 -800003f4: e3 76 3c ff bgeu s8, s3, -20 -800003f8: 13 04 00 00 mv s0, zero -800003fc: 93 0d 0b 00 mv s11, s6 -80000400: 93 84 0b 00 mv s1, s7 -80000404: 6f 00 40 01 j 20 -80000408: 13 04 14 00 addi s0, s0, 1 -8000040c: 93 84 84 00 addi s1, s1, 8 -80000410: 93 8d 4d 00 addi s11, s11, 4 -80000414: e3 7e 94 fd bgeu s0, s9, -36 -80000418: 33 05 8d 00 add a0, s10, s0 -8000041c: e3 56 55 ff bge a0, s5, -20 -80000420: 07 a0 c4 ff flw ft0, -4(s1) -80000424: 87 a0 04 00 flw ft1, 0(s1) -80000428: 53 70 04 08 fsub.s ft0, fs0, ft0 -8000042c: d3 f0 14 08 fsub.s ft1, fs1, ft1 -80000430: d3 f0 10 10 fmul.s ft1, ft1, ft1 -80000434: 53 70 00 10 fmul.s ft0, ft0, ft0 -80000438: 53 75 10 00 fadd.s fa0, ft0, ft1 -8000043c: 97 00 00 00 auipc ra, 0 -80000440: e7 80 c0 c5 jalr -932(ra) -80000444: 27 a0 ad 00 fsw fa0, 0(s11) -80000448: 6f f0 1f fc j -64 -8000044c: 87 24 41 00 flw fs1, 4(sp) -80000450: 07 24 81 00 flw fs0, 8(sp) -80000454: 83 2d c1 00 lw s11, 12(sp) -80000458: 03 2d 01 01 lw s10, 16(sp) -8000045c: 83 2c 41 01 lw s9, 20(sp) -80000460: 03 2c 81 01 lw s8, 24(sp) -80000464: 83 2b c1 01 lw s7, 28(sp) -80000468: 03 2b 01 02 lw s6, 32(sp) -8000046c: 83 2a 41 02 lw s5, 36(sp) -80000470: 03 2a 81 02 lw s4, 40(sp) -80000474: 83 29 c1 02 lw s3, 44(sp) -80000478: 03 29 01 03 lw s2, 48(sp) -8000047c: 83 24 41 03 lw s1, 52(sp) -80000480: 03 24 81 03 lw s0, 56(sp) -80000484: 83 20 c1 03 lw ra, 60(sp) -80000488: 13 01 01 04 addi sp, sp, 64 -8000048c: 67 80 00 00 ret +80000368 _pocl_kernel_NearestNeighbor_workgroup_fast: +80000368: 13 01 01 fc addi sp, sp, -64 +8000036c: 23 2e 11 02 sw ra, 60(sp) +80000370: 23 2c 81 02 sw s0, 56(sp) +80000374: 23 2a 91 02 sw s1, 52(sp) +80000378: 23 28 21 03 sw s2, 48(sp) +8000037c: 23 26 31 03 sw s3, 44(sp) +80000380: 23 24 41 03 sw s4, 40(sp) +80000384: 23 22 51 03 sw s5, 36(sp) +80000388: 23 20 61 03 sw s6, 32(sp) +8000038c: 23 2e 71 01 sw s7, 28(sp) +80000390: 23 2c 81 01 sw s8, 24(sp) +80000394: 23 2a 91 01 sw s9, 20(sp) +80000398: 23 28 a1 01 sw s10, 16(sp) +8000039c: 23 26 b1 01 sw s11, 12(sp) +800003a0: 27 24 81 00 fsw fs0, 8(sp) +800003a4: 27 22 91 00 fsw fs1, 4(sp) +800003a8: 13 09 00 00 mv s2, zero +800003ac: 83 26 05 00 lw a3, 0(a0) +800003b0: 03 27 85 00 lw a4, 8(a0) +800003b4: 83 27 c5 00 lw a5, 12(a0) +800003b8: 83 24 05 01 lw s1, 16(a0) +800003bc: 03 25 45 00 lw a0, 4(a0) +800003c0: 83 2a 07 00 lw s5, 0(a4) +800003c4: 07 a4 07 00 flw fs0, 0(a5) +800003c8: 87 a4 04 00 flw fs1, 0(s1) +800003cc: 83 ac 85 01 lw s9, 24(a1) +800003d0: 03 a7 c5 00 lw a4, 12(a1) +800003d4: 83 a9 c5 01 lw s3, 28(a1) +800003d8: 03 aa 05 02 lw s4, 32(a1) +800003dc: b3 85 cc 02 mul a1, s9, a2 +800003e0: 33 0d b7 00 add s10, a4, a1 +800003e4: 93 15 3d 00 slli a1, s10, 3 +800003e8: b3 85 b6 00 add a1, a3, a1 +800003ec: 13 16 2d 00 slli a2, s10, 2 +800003f0: 33 0b c5 00 add s6, a0, a2 +800003f4: 93 8b 45 00 addi s7, a1, 4 +800003f8: 6f 00 c0 00 j 12 +800003fc: 13 09 19 00 addi s2, s2, 1 +80000400: 63 74 49 07 bgeu s2, s4, 104 +80000404: 13 0c 00 00 mv s8, zero +80000408: 6f 00 c0 00 j 12 +8000040c: 13 0c 1c 00 addi s8, s8, 1 +80000410: e3 76 3c ff bgeu s8, s3, -20 +80000414: 13 04 00 00 mv s0, zero +80000418: 93 0d 0b 00 mv s11, s6 +8000041c: 93 84 0b 00 mv s1, s7 +80000420: 6f 00 40 01 j 20 +80000424: 13 04 14 00 addi s0, s0, 1 +80000428: 93 84 84 00 addi s1, s1, 8 +8000042c: 93 8d 4d 00 addi s11, s11, 4 +80000430: e3 7e 94 fd bgeu s0, s9, -36 +80000434: 33 05 8d 00 add a0, s10, s0 +80000438: e3 56 55 ff bge a0, s5, -20 +8000043c: 07 a0 c4 ff flw ft0, -4(s1) +80000440: 87 a0 04 00 flw ft1, 0(s1) +80000444: 53 70 04 08 fsub.s ft0, fs0, ft0 +80000448: d3 f0 14 08 fsub.s ft1, fs1, ft1 +8000044c: d3 f0 10 10 fmul.s ft1, ft1, ft1 +80000450: 53 70 00 10 fmul.s ft0, ft0, ft0 +80000454: 53 75 10 00 fadd.s fa0, ft0, ft1 +80000458: 97 00 00 00 auipc ra, 0 +8000045c: e7 80 00 c4 jalr -960(ra) +80000460: 27 a0 ad 00 fsw fa0, 0(s11) +80000464: 6f f0 1f fc j -64 +80000468: 87 24 41 00 flw fs1, 4(sp) +8000046c: 07 24 81 00 flw fs0, 8(sp) +80000470: 83 2d c1 00 lw s11, 12(sp) +80000474: 03 2d 01 01 lw s10, 16(sp) +80000478: 83 2c 41 01 lw s9, 20(sp) +8000047c: 03 2c 81 01 lw s8, 24(sp) +80000480: 83 2b c1 01 lw s7, 28(sp) +80000484: 03 2b 01 02 lw s6, 32(sp) +80000488: 83 2a 41 02 lw s5, 36(sp) +8000048c: 03 2a 81 02 lw s4, 40(sp) +80000490: 83 29 c1 02 lw s3, 44(sp) +80000494: 03 29 01 03 lw s2, 48(sp) +80000498: 83 24 41 03 lw s1, 52(sp) +8000049c: 03 24 81 03 lw s0, 56(sp) +800004a0: 83 20 c1 03 lw ra, 60(sp) +800004a4: 13 01 01 04 addi sp, sp, 64 +800004a8: 67 80 00 00 ret -80000490 _exit: -80000490: ef 00 c0 3b jal 956 -80000494: 13 05 00 00 mv a0, zero -80000498: 6b 00 05 00 +800004ac _exit: +800004ac: 63 06 05 00 beqz a0, 12 +800004b0: 93 01 05 00 mv gp, a0 +800004b4: 73 00 00 00 ecall -8000049c vx_set_sp: -8000049c: 73 25 00 fc csrr a0, 4032 -800004a0: 6b 00 05 00 -800004a4: 97 11 00 00 auipc gp, 1 -800004a8: 93 81 41 36 addi gp, gp, 868 -800004ac: 17 01 00 7f auipc sp, 520192 -800004b0: 13 01 41 b5 addi sp, sp, -1196 -800004b4: 93 05 00 40 addi a1, zero, 1024 -800004b8: 73 26 10 cc csrr a2, 3265 -800004bc: b3 85 c5 02 mul a1, a1, a2 -800004c0: 33 01 b1 40 sub sp, sp, a1 -800004c4: f3 26 30 cc csrr a3, 3267 -800004c8: 63 86 06 00 beqz a3, 12 -800004cc: 13 05 00 00 mv a0, zero -800004d0: 6b 00 05 00 +800004b8 label_exit_next: +800004b8: ef 00 80 4f jal 1272 +800004bc: 13 05 00 00 mv a0, zero +800004c0: 6b 00 05 00 vx_tmc a0 -800004d4 RETURN: -800004d4: 67 80 00 00 ret +800004c4 vx_set_sp: +800004c4: 13 05 f0 ff addi a0, zero, -1 +800004c8: 6b 00 05 00 vx_tmc a0 +800004cc: 97 21 00 00 auipc gp, 2 +800004d0: 93 81 c1 36 addi gp, gp, 876 +800004d4: 37 01 00 ff lui sp, 1044480 +800004d8: 73 26 10 cc csrr a2, 3265 +800004dc: 93 15 a6 00 slli a1, a2, 10 +800004e0: 33 01 b1 40 sub sp, sp, a1 +800004e4: f3 26 30 cc csrr a3, 3267 +800004e8: 63 86 06 00 beqz a3, 12 +800004ec: 13 05 00 00 mv a0, zero +800004f0: 6b 00 05 00 vx_tmc a0 -800004d8 spawn_kernel_callback: -800004d8: 13 01 01 fe addi sp, sp, -32 -800004dc: 23 2e 11 00 sw ra, 28(sp) -800004e0: 23 2c 81 00 sw s0, 24(sp) -800004e4: 23 2a 91 00 sw s1, 20(sp) -800004e8: 23 28 21 01 sw s2, 16(sp) -800004ec: 23 26 31 01 sw s3, 12(sp) -800004f0: 23 24 41 01 sw s4, 8(sp) -800004f4: 23 22 51 01 sw s5, 4(sp) -800004f8: f3 27 00 fc csrr a5, 4032 -800004fc: 6b 80 07 00 -80000500: f3 26 50 cc csrr a3, 3269 -80000504: 73 29 30 cc csrr s2, 3267 -80000508: 73 27 00 cc csrr a4, 3264 -8000050c: 73 26 00 fc csrr a2, 4032 -80000510: b7 17 00 80 lui a5, 524289 -80000514: 93 96 26 00 slli a3, a3, 2 -80000518: 93 87 c7 43 addi a5, a5, 1084 -8000051c: b3 87 d7 00 add a5, a5, a3 -80000520: 03 a4 07 00 lw s0, 0(a5) -80000524: 83 24 44 01 lw s1, 20(s0) -80000528: 83 26 04 01 lw a3, 16(s0) -8000052c: b3 2a 99 00 slt s5, s2, s1 -80000530: 93 87 04 00 mv a5, s1 -80000534: b3 8a da 00 add s5, s5, a3 -80000538: b3 84 26 03 mul s1, a3, s2 -8000053c: 63 54 f9 00 bge s2, a5, 8 -80000540: 93 07 09 00 mv a5, s2 -80000544: b3 84 f4 00 add s1, s1, a5 -80000548: 83 25 04 00 lw a1, 0(s0) -8000054c: 83 26 c4 00 lw a3, 12(s0) -80000550: 83 a9 05 00 lw s3, 0(a1) -80000554: 03 aa 45 00 lw s4, 4(a1) -80000558: b3 84 c4 02 mul s1, s1, a2 -8000055c: b3 87 ea 02 mul a5, s5, a4 -80000560: b3 84 d4 00 add s1, s1, a3 -80000564: b3 84 f4 00 add s1, s1, a5 -80000568: b3 8a 9a 00 add s5, s5, s1 -8000056c: 33 8a 49 03 mul s4, s3, s4 -80000570: 63 c0 54 07 blt s1, s5, 96 -80000574: 6f 00 00 08 j 128 -80000578: 03 47 a4 01 lbu a4, 26(s0) -8000057c: 83 46 94 01 lbu a3, 25(s0) -80000580: 33 d7 e4 40 sra a4, s1, a4 -80000584: b3 07 47 03 mul a5, a4, s4 -80000588: b3 87 f4 40 sub a5, s1, a5 -8000058c: 63 80 06 06 beqz a3, 96 -80000590: 83 46 b4 01 lbu a3, 27(s0) -80000594: b3 d6 d7 40 sra a3, a5, a3 -80000598: b3 88 36 03 mul a7, a3, s3 -8000059c: 03 ae 45 01 lw t3, 20(a1) -800005a0: 03 a3 05 01 lw t1, 16(a1) -800005a4: 03 a6 c5 00 lw a2, 12(a1) -800005a8: 03 28 44 00 lw a6, 4(s0) -800005ac: 03 25 84 00 lw a0, 8(s0) -800005b0: 93 84 14 00 addi s1, s1, 1 -800005b4: 33 07 c7 01 add a4, a4, t3 -800005b8: b3 86 66 00 add a3, a3, t1 -800005bc: b3 87 17 41 sub a5, a5, a7 -800005c0: 33 86 c7 00 add a2, a5, a2 -800005c4: e7 00 08 00 jalr a6 -800005c8: 63 86 9a 02 beq s5, s1, 44 -800005cc: 83 25 04 00 lw a1, 0(s0) -800005d0: 83 47 84 01 lbu a5, 24(s0) -800005d4: e3 92 07 fa bnez a5, -92 -800005d8: 33 c7 44 03 div a4, s1, s4 -800005dc: 83 46 94 01 lbu a3, 25(s0) -800005e0: b3 07 47 03 mul a5, a4, s4 -800005e4: b3 87 f4 40 sub a5, s1, a5 -800005e8: e3 94 06 fa bnez a3, -88 -800005ec: b3 c6 37 03 div a3, a5, s3 -800005f0: 6f f0 9f fa j -88 -800005f4: 13 39 19 00 seqz s2, s2 -800005f8: 6b 00 09 00 -800005fc: 83 20 c1 01 lw ra, 28(sp) -80000600: 03 24 81 01 lw s0, 24(sp) -80000604: 83 24 41 01 lw s1, 20(sp) -80000608: 03 29 01 01 lw s2, 16(sp) -8000060c: 83 29 c1 00 lw s3, 12(sp) -80000610: 03 2a 81 00 lw s4, 8(sp) -80000614: 83 2a 41 00 lw s5, 4(sp) -80000618: 13 01 01 02 addi sp, sp, 32 -8000061c: 67 80 00 00 ret +800004f4 RETURN: +800004f4: 67 80 00 00 ret -80000620 vx_spawn_kernel: -80000620: 13 01 01 fc addi sp, sp, -64 -80000624: 23 2e 11 02 sw ra, 60(sp) -80000628: 23 2c 81 02 sw s0, 56(sp) -8000062c: 23 2a 91 02 sw s1, 52(sp) -80000630: 23 28 21 03 sw s2, 48(sp) -80000634: 23 26 31 03 sw s3, 44(sp) -80000638: f3 28 20 fc csrr a7, 4034 -8000063c: 73 23 10 fc csrr t1, 4033 -80000640: 73 24 00 fc csrr s0, 4032 -80000644: f3 27 50 cc csrr a5, 3269 -80000648: 13 07 f0 01 addi a4, zero, 31 -8000064c: 63 46 f7 0e blt a4, a5, 236 -80000650: 03 2e 05 00 lw t3, 0(a0) -80000654: 83 26 45 00 lw a3, 4(a0) -80000658: 03 28 85 00 lw a6, 8(a0) -8000065c: b3 0e 83 02 mul t4, t1, s0 -80000660: 13 07 10 00 addi a4, zero, 1 -80000664: b3 06 de 02 mul a3, t3, a3 -80000668: 33 88 06 03 mul a6, a3, a6 -8000066c: 63 d4 0e 01 bge t4, a6, 8 -80000670: 33 47 d8 03 div a4, a6, t4 -80000674: 63 c0 e8 0e blt a7, a4, 224 -80000678: 63 d0 e7 0c bge a5, a4, 192 -8000067c: 93 88 f8 ff addi a7, a7, -1 -80000680: b3 4e e8 02 div t4, a6, a4 -80000684: 93 84 0e 00 mv s1, t4 -80000688: 63 96 f8 00 bne a7, a5, 12 -8000068c: 33 67 e8 02 rem a4, a6, a4 -80000690: b3 04 d7 01 add s1, a4, t4 -80000694: 33 c9 84 02 div s2, s1, s0 -80000698: b3 e4 84 02 rem s1, s1, s0 -8000069c: 63 42 69 0c blt s2, t1, 196 -800006a0: 93 02 10 00 addi t0, zero, 1 -800006a4: 33 48 69 02 div a6, s2, t1 -800006a8: 63 06 08 00 beqz a6, 12 -800006ac: 93 02 08 00 mv t0, a6 -800006b0: 33 68 69 02 rem a6, s2, t1 -800006b4: d3 f7 06 d0 fcvt.s.w fa5, a3 -800006b8: 93 8f f6 ff addi t6, a3, -1 -800006bc: 13 0f fe ff addi t5, t3, -1 -800006c0: b7 19 00 80 lui s3, 524289 -800006c4: b3 f6 df 00 and a3, t6, a3 -800006c8: 93 89 c9 43 addi s3, s3, 1084 -800006cc: 93 b6 16 00 seqz a3, a3 -800006d0: 23 22 a1 00 sw a0, 4(sp) -800006d4: 23 24 b1 00 sw a1, 8(sp) -800006d8: 23 26 c1 00 sw a2, 12(sp) -800006dc: 23 2a 51 00 sw t0, 20(sp) -800006e0: 23 2c 01 01 sw a6, 24(sp) -800006e4: 23 0e d1 00 sb a3, 28(sp) -800006e8: 33 87 fe 02 mul a4, t4, a5 -800006ec: d3 8e 07 e0 fmv.x.w t4, fa5 -800006f0: d3 77 0e d0 fcvt.s.w fa5, t3 -800006f4: 93 97 27 00 slli a5, a5, 2 -800006f8: 33 7e cf 01 and t3, t5, t3 -800006fc: d3 88 07 e0 fmv.x.w a7, fa5 -80000700: 93 de 7e 41 srai t4, t4, 23 -80000704: 13 3e 1e 00 seqz t3, t3 -80000708: 93 d8 78 41 srai a7, a7, 23 -8000070c: 93 8e 1e f8 addi t4, t4, -127 -80000710: 93 88 18 f8 addi a7, a7, -127 -80000714: b3 87 f9 00 add a5, s3, a5 -80000718: 23 28 e1 00 sw a4, 16(sp) -8000071c: 13 07 41 00 addi a4, sp, 4 -80000720: a3 0e c1 01 sb t3, 29(sp) -80000724: 23 0f d1 01 sb t4, 30(sp) -80000728: a3 0f 11 01 sb a7, 31(sp) -8000072c: 23 a0 e7 00 sw a4, 0(a5) -80000730: 63 4e 20 03 bgtz s2, 60 -80000734: 63 9c 04 04 bnez s1, 88 -80000738: 83 20 c1 03 lw ra, 60(sp) -8000073c: 03 24 81 03 lw s0, 56(sp) -80000740: 83 24 41 03 lw s1, 52(sp) -80000744: 03 29 01 03 lw s2, 48(sp) -80000748: 83 29 c1 02 lw s3, 44(sp) -8000074c: 13 01 01 04 addi sp, sp, 64 -80000750: 67 80 00 00 ret -80000754: 13 87 08 00 mv a4, a7 -80000758: e3 c2 e7 f2 blt a5, a4, -220 -8000075c: 6f f0 df fd j -36 -80000760: 13 08 00 00 mv a6, zero -80000764: 93 02 10 00 addi t0, zero, 1 -80000768: 6f f0 df f4 j -180 -8000076c: 13 07 09 00 mv a4, s2 -80000770: 63 54 23 01 bge t1, s2, 8 -80000774: 13 07 03 00 mv a4, t1 -80000778: b7 07 00 80 lui a5, 524288 -8000077c: 93 87 87 4d addi a5, a5, 1240 -80000780: 6b 10 f7 00 -80000784: ef f0 5f d5 jal -684 -80000788: e3 88 04 fa beqz s1, -80 -8000078c: 33 04 89 02 mul s0, s2, s0 -80000790: 23 28 81 00 sw s0, 16(sp) -80000794: 6b 80 04 00 -80000798: 73 27 50 cc csrr a4, 3269 -8000079c: f3 27 20 cc csrr a5, 3266 -800007a0: 13 17 27 00 slli a4, a4, 2 -800007a4: b3 89 e9 00 add s3, s3, a4 -800007a8: 03 a5 09 00 lw a0, 0(s3) -800007ac: 83 25 05 00 lw a1, 0(a0) -800007b0: 83 26 c5 00 lw a3, 12(a0) -800007b4: 03 47 85 01 lbu a4, 24(a0) -800007b8: 03 a8 05 00 lw a6, 0(a1) -800007bc: 03 a6 45 00 lw a2, 4(a1) -800007c0: b3 87 d7 00 add a5, a5, a3 -800007c4: 33 06 c8 02 mul a2, a6, a2 -800007c8: 63 0e 07 06 beqz a4, 124 -800007cc: 03 47 a5 01 lbu a4, 26(a0) -800007d0: 33 d7 e7 40 sra a4, a5, a4 -800007d4: 83 46 95 01 lbu a3, 25(a0) -800007d8: 33 06 e6 02 mul a2, a2, a4 -800007dc: b3 87 c7 40 sub a5, a5, a2 -800007e0: 63 8e 06 04 beqz a3, 92 -800007e4: 83 48 b5 01 lbu a7, 27(a0) -800007e8: b3 d8 17 41 sra a7, a5, a7 -800007ec: 33 08 18 03 mul a6, a6, a7 -800007f0: 03 ae 45 01 lw t3, 20(a1) -800007f4: 83 a6 05 01 lw a3, 16(a1) -800007f8: 03 a6 c5 00 lw a2, 12(a1) -800007fc: 03 23 45 00 lw t1, 4(a0) -80000800: 03 25 85 00 lw a0, 8(a0) -80000804: 33 07 c7 01 add a4, a4, t3 -80000808: b3 86 d8 00 add a3, a7, a3 -8000080c: b3 87 07 41 sub a5, a5, a6 -80000810: 33 86 c7 00 add a2, a5, a2 -80000814: e7 00 03 00 jalr t1 -80000818: 93 07 10 00 addi a5, zero, 1 -8000081c: 6b 80 07 00 -80000820: 83 20 c1 03 lw ra, 60(sp) -80000824: 03 24 81 03 lw s0, 56(sp) -80000828: 83 24 41 03 lw s1, 52(sp) -8000082c: 03 29 01 03 lw s2, 48(sp) -80000830: 83 29 c1 02 lw s3, 44(sp) -80000834: 13 01 01 04 addi sp, sp, 64 -80000838: 67 80 00 00 ret -8000083c: b3 c8 07 03 div a7, a5, a6 -80000840: 6f f0 df fa j -84 -80000844: 33 c7 c7 02 div a4, a5, a2 -80000848: 6f f0 df f8 j -116 +800004f8 __libc_init_array: +800004f8: 13 01 01 ff addi sp, sp, -16 +800004fc: 23 24 81 00 sw s0, 8(sp) +80000500: 23 20 21 01 sw s2, 0(sp) +80000504: 37 24 00 80 lui s0, 524290 +80000508: 37 29 00 80 lui s2, 524290 +8000050c: 93 07 44 03 addi a5, s0, 52 +80000510: 13 09 49 03 addi s2, s2, 52 +80000514: 33 09 f9 40 sub s2, s2, a5 +80000518: 23 26 11 00 sw ra, 12(sp) +8000051c: 23 22 91 00 sw s1, 4(sp) +80000520: 13 59 29 40 srai s2, s2, 2 +80000524: 63 00 09 02 beqz s2, 32 +80000528: 13 04 44 03 addi s0, s0, 52 +8000052c: 93 04 00 00 mv s1, zero +80000530: 83 27 04 00 lw a5, 0(s0) +80000534: 93 84 14 00 addi s1, s1, 1 +80000538: 13 04 44 00 addi s0, s0, 4 +8000053c: e7 80 07 00 jalr a5 +80000540: e3 18 99 fe bne s2, s1, -16 +80000544: 37 24 00 80 lui s0, 524290 +80000548: 37 29 00 80 lui s2, 524290 +8000054c: 93 07 44 03 addi a5, s0, 52 +80000550: 13 09 89 03 addi s2, s2, 56 +80000554: 33 09 f9 40 sub s2, s2, a5 +80000558: 13 59 29 40 srai s2, s2, 2 +8000055c: 63 00 09 02 beqz s2, 32 +80000560: 13 04 44 03 addi s0, s0, 52 +80000564: 93 04 00 00 mv s1, zero +80000568: 83 27 04 00 lw a5, 0(s0) +8000056c: 93 84 14 00 addi s1, s1, 1 +80000570: 13 04 44 00 addi s0, s0, 4 +80000574: e7 80 07 00 jalr a5 +80000578: e3 18 99 fe bne s2, s1, -16 +8000057c: 83 20 c1 00 lw ra, 12(sp) +80000580: 03 24 81 00 lw s0, 8(sp) +80000584: 83 24 41 00 lw s1, 4(sp) +80000588: 03 29 01 00 lw s2, 0(sp) +8000058c: 13 01 01 01 addi sp, sp, 16 +80000590: 67 80 00 00 ret -8000084c vx_perf_dump: -8000084c: f3 27 50 cc csrr a5, 3269 -80000850: 37 07 ff 00 lui a4, 4080 -80000854: b3 87 e7 00 add a5, a5, a4 -80000858: 93 97 87 00 slli a5, a5, 8 -8000085c: 73 27 00 b0 csrr a4, mcycle -80000860: 23 a0 e7 00 sw a4, 0(a5) -80000864: 73 27 10 b0 csrr a4, 2817 -80000868: 23 a2 e7 00 sw a4, 4(a5) -8000086c: 73 27 20 b0 csrr a4, minstret -80000870: 23 a4 e7 00 sw a4, 8(a5) -80000874: 73 27 30 b0 csrr a4, mhpmcounter3 -80000878: 23 a6 e7 00 sw a4, 12(a5) -8000087c: 73 27 40 b0 csrr a4, mhpmcounter4 -80000880: 23 a8 e7 00 sw a4, 16(a5) -80000884: 73 27 50 b0 csrr a4, mhpmcounter5 -80000888: 23 aa e7 00 sw a4, 20(a5) -8000088c: 73 27 60 b0 csrr a4, mhpmcounter6 -80000890: 23 ac e7 00 sw a4, 24(a5) -80000894: 73 27 70 b0 csrr a4, mhpmcounter7 -80000898: 23 ae e7 00 sw a4, 28(a5) -8000089c: 73 27 80 b0 csrr a4, mhpmcounter8 -800008a0: 23 a0 e7 02 sw a4, 32(a5) -800008a4: 73 27 90 b0 csrr a4, mhpmcounter9 -800008a8: 23 a2 e7 02 sw a4, 36(a5) -800008ac: 73 27 a0 b0 csrr a4, mhpmcounter10 -800008b0: 23 a4 e7 02 sw a4, 40(a5) -800008b4: 73 27 b0 b0 csrr a4, mhpmcounter11 -800008b8: 23 a6 e7 02 sw a4, 44(a5) -800008bc: 73 27 c0 b0 csrr a4, mhpmcounter12 -800008c0: 23 a8 e7 02 sw a4, 48(a5) -800008c4: 73 27 d0 b0 csrr a4, mhpmcounter13 -800008c8: 23 aa e7 02 sw a4, 52(a5) -800008cc: 73 27 e0 b0 csrr a4, mhpmcounter14 -800008d0: 23 ac e7 02 sw a4, 56(a5) -800008d4: 73 27 f0 b0 csrr a4, mhpmcounter15 -800008d8: 23 ae e7 02 sw a4, 60(a5) -800008dc: 73 27 00 b1 csrr a4, mhpmcounter16 -800008e0: 23 a0 e7 04 sw a4, 64(a5) -800008e4: 73 27 10 b1 csrr a4, mhpmcounter17 -800008e8: 23 a2 e7 04 sw a4, 68(a5) -800008ec: 73 27 20 b1 csrr a4, mhpmcounter18 -800008f0: 23 a4 e7 04 sw a4, 72(a5) -800008f4: 73 27 30 b1 csrr a4, mhpmcounter19 -800008f8: 23 a6 e7 04 sw a4, 76(a5) -800008fc: 73 27 40 b1 csrr a4, mhpmcounter20 -80000900: 23 a8 e7 04 sw a4, 80(a5) -80000904: 73 27 50 b1 csrr a4, mhpmcounter21 -80000908: 23 aa e7 04 sw a4, 84(a5) -8000090c: 73 27 60 b1 csrr a4, mhpmcounter22 -80000910: 23 ac e7 04 sw a4, 88(a5) -80000914: 73 27 70 b1 csrr a4, mhpmcounter23 -80000918: 23 ae e7 04 sw a4, 92(a5) -8000091c: 73 27 80 b1 csrr a4, mhpmcounter24 -80000920: 23 a0 e7 06 sw a4, 96(a5) -80000924: 73 27 90 b1 csrr a4, mhpmcounter25 -80000928: 23 a2 e7 06 sw a4, 100(a5) -8000092c: 73 27 a0 b1 csrr a4, mhpmcounter26 -80000930: 23 a4 e7 06 sw a4, 104(a5) -80000934: 73 27 b0 b1 csrr a4, mhpmcounter27 -80000938: 23 a6 e7 06 sw a4, 108(a5) -8000093c: 73 27 c0 b1 csrr a4, mhpmcounter28 -80000940: 23 a8 e7 06 sw a4, 112(a5) -80000944: 73 27 d0 b1 csrr a4, mhpmcounter29 -80000948: 23 aa e7 06 sw a4, 116(a5) -8000094c: 73 27 e0 b1 csrr a4, mhpmcounter30 -80000950: 23 ac e7 06 sw a4, 120(a5) -80000954: 73 27 f0 b1 csrr a4, mhpmcounter31 -80000958: 23 ae e7 06 sw a4, 124(a5) -8000095c: 73 27 00 b8 csrr a4, mcycleh -80000960: 23 a0 e7 08 sw a4, 128(a5) -80000964: 73 27 10 b8 csrr a4, 2945 -80000968: 23 a2 e7 08 sw a4, 132(a5) -8000096c: 73 27 20 b8 csrr a4, minstreth -80000970: 23 a4 e7 08 sw a4, 136(a5) -80000974: 73 27 30 b8 csrr a4, mhpmcounter3h -80000978: 23 a6 e7 08 sw a4, 140(a5) -8000097c: 73 27 40 b8 csrr a4, mhpmcounter4h -80000980: 23 a8 e7 08 sw a4, 144(a5) -80000984: 73 27 50 b8 csrr a4, mhpmcounter5h -80000988: 23 aa e7 08 sw a4, 148(a5) -8000098c: 73 27 60 b8 csrr a4, mhpmcounter6h -80000990: 23 ac e7 08 sw a4, 152(a5) -80000994: 73 27 70 b8 csrr a4, mhpmcounter7h -80000998: 23 ae e7 08 sw a4, 156(a5) -8000099c: 73 27 80 b8 csrr a4, mhpmcounter8h -800009a0: 23 a0 e7 0a sw a4, 160(a5) -800009a4: 73 27 90 b8 csrr a4, mhpmcounter9h -800009a8: 23 a2 e7 0a sw a4, 164(a5) -800009ac: 73 27 a0 b8 csrr a4, mhpmcounter10h -800009b0: 23 a4 e7 0a sw a4, 168(a5) -800009b4: 73 27 b0 b8 csrr a4, mhpmcounter11h -800009b8: 23 a6 e7 0a sw a4, 172(a5) -800009bc: 73 27 c0 b8 csrr a4, mhpmcounter12h -800009c0: 23 a8 e7 0a sw a4, 176(a5) -800009c4: 73 27 d0 b8 csrr a4, mhpmcounter13h -800009c8: 23 aa e7 0a sw a4, 180(a5) -800009cc: 73 27 e0 b8 csrr a4, mhpmcounter14h -800009d0: 23 ac e7 0a sw a4, 184(a5) -800009d4: 73 27 f0 b8 csrr a4, mhpmcounter15h -800009d8: 23 ae e7 0a sw a4, 188(a5) -800009dc: 73 27 00 b9 csrr a4, mhpmcounter16h -800009e0: 23 a0 e7 0c sw a4, 192(a5) -800009e4: 73 27 10 b9 csrr a4, mhpmcounter17h -800009e8: 23 a2 e7 0c sw a4, 196(a5) -800009ec: 73 27 20 b9 csrr a4, mhpmcounter18h -800009f0: 23 a4 e7 0c sw a4, 200(a5) -800009f4: 73 27 30 b9 csrr a4, mhpmcounter19h -800009f8: 23 a6 e7 0c sw a4, 204(a5) -800009fc: 73 27 40 b9 csrr a4, mhpmcounter20h -80000a00: 23 a8 e7 0c sw a4, 208(a5) -80000a04: 73 27 50 b9 csrr a4, mhpmcounter21h -80000a08: 23 aa e7 0c sw a4, 212(a5) -80000a0c: 73 27 60 b9 csrr a4, mhpmcounter22h -80000a10: 23 ac e7 0c sw a4, 216(a5) -80000a14: 73 27 70 b9 csrr a4, mhpmcounter23h -80000a18: 23 ae e7 0c sw a4, 220(a5) -80000a1c: 73 27 80 b9 csrr a4, mhpmcounter24h -80000a20: 23 a0 e7 0e sw a4, 224(a5) -80000a24: 73 27 90 b9 csrr a4, mhpmcounter25h -80000a28: 23 a2 e7 0e sw a4, 228(a5) -80000a2c: 73 27 a0 b9 csrr a4, mhpmcounter26h -80000a30: 23 a4 e7 0e sw a4, 232(a5) -80000a34: 73 27 b0 b9 csrr a4, mhpmcounter27h -80000a38: 23 a6 e7 0e sw a4, 236(a5) -80000a3c: 73 27 c0 b9 csrr a4, mhpmcounter28h -80000a40: 23 a8 e7 0e sw a4, 240(a5) -80000a44: 73 27 d0 b9 csrr a4, mhpmcounter29h -80000a48: 23 aa e7 0e sw a4, 244(a5) -80000a4c: 73 27 e0 b9 csrr a4, mhpmcounter30h -80000a50: 23 ac e7 0e sw a4, 248(a5) -80000a54: 73 27 f0 b9 csrr a4, mhpmcounter31h -80000a58: 23 ae e7 0e sw a4, 252(a5) -80000a5c: 67 80 00 00 ret +80000594 __libc_fini_array: +80000594: 13 01 01 ff addi sp, sp, -16 +80000598: 23 24 81 00 sw s0, 8(sp) +8000059c: b7 27 00 80 lui a5, 524290 +800005a0: 37 24 00 80 lui s0, 524290 +800005a4: 13 04 84 03 addi s0, s0, 56 +800005a8: 93 87 87 03 addi a5, a5, 56 +800005ac: b3 87 87 40 sub a5, a5, s0 +800005b0: 23 22 91 00 sw s1, 4(sp) +800005b4: 23 26 11 00 sw ra, 12(sp) +800005b8: 93 d4 27 40 srai s1, a5, 2 +800005bc: 63 80 04 02 beqz s1, 32 +800005c0: 93 87 c7 ff addi a5, a5, -4 +800005c4: 33 84 87 00 add s0, a5, s0 +800005c8: 83 27 04 00 lw a5, 0(s0) +800005cc: 93 84 f4 ff addi s1, s1, -1 +800005d0: 13 04 c4 ff addi s0, s0, -4 +800005d4: e7 80 07 00 jalr a5 +800005d8: e3 98 04 fe bnez s1, -16 +800005dc: 83 20 c1 00 lw ra, 12(sp) +800005e0: 03 24 81 00 lw s0, 8(sp) +800005e4: 83 24 41 00 lw s1, 4(sp) +800005e8: 13 01 01 01 addi sp, sp, 16 +800005ec: 67 80 00 00 ret -80000a60 sqrtf: -80000a60: 13 01 01 fe addi sp, sp, -32 -80000a64: 27 26 81 00 fsw fs0, 12(sp) -80000a68: 23 2e 11 00 sw ra, 28(sp) -80000a6c: 53 04 a5 20 fmv.s fs0, fa0 -80000a70: 27 24 91 00 fsw fs1, 8(sp) -80000a74: ef 00 00 06 jal 96 -80000a78: b7 17 00 80 lui a5, 524289 -80000a7c: 03 a7 87 43 lw a4, 1080(a5) -80000a80: 93 07 f0 ff addi a5, zero, -1 -80000a84: 63 0c f7 00 beq a4, a5, 24 -80000a88: d3 27 84 a0 feq.s a5, fs0, fs0 -80000a8c: 63 88 07 00 beqz a5, 16 -80000a90: d3 04 00 f0 fmv.w.x fs1, zero -80000a94: d3 17 94 a0 flt.s a5, fs0, fs1 -80000a98: 63 9c 07 00 bnez a5, 24 -80000a9c: 83 20 c1 01 lw ra, 28(sp) -80000aa0: 07 24 c1 00 flw fs0, 12(sp) -80000aa4: 87 24 81 00 flw fs1, 8(sp) -80000aa8: 13 01 01 02 addi sp, sp, 32 -80000aac: 67 80 00 00 ret -80000ab0: ef 00 40 14 jal 324 -80000ab4: 83 20 c1 01 lw ra, 28(sp) -80000ab8: 93 07 10 02 addi a5, zero, 33 -80000abc: 23 20 f5 00 sw a5, 0(a0) -80000ac0: 53 f5 94 18 fdiv.s fa0, fs1, fs1 -80000ac4: 07 24 c1 00 flw fs0, 12(sp) -80000ac8: 87 24 81 00 flw fs1, 8(sp) -80000acc: 13 01 01 02 addi sp, sp, 32 -80000ad0: 67 80 00 00 ret +800005f0 spawn_kernel_all_stub: +800005f0: 13 01 01 fe addi sp, sp, -32 +800005f4: 23 2e 11 00 sw ra, 28(sp) +800005f8: 23 2c 81 00 sw s0, 24(sp) +800005fc: 23 2a 91 00 sw s1, 20(sp) +80000600: 23 28 21 01 sw s2, 16(sp) +80000604: 23 26 31 01 sw s3, 12(sp) +80000608: 23 24 41 01 sw s4, 8(sp) +8000060c: 73 26 50 cc csrr a2, 3269 +80000610: 73 27 30 cc csrr a4, 3267 +80000614: f3 26 00 cc csrr a3, 3264 +80000618: 73 25 00 fc csrr a0, 4032 +8000061c: b7 27 00 80 lui a5, 524290 +80000620: 13 16 26 00 slli a2, a2, 2 +80000624: 93 87 c7 46 addi a5, a5, 1132 +80000628: b3 87 c7 00 add a5, a5, a2 +8000062c: 03 a4 07 00 lw s0, 0(a5) +80000630: 83 24 44 01 lw s1, 20(s0) +80000634: 03 26 04 01 lw a2, 16(s0) +80000638: 33 2a 97 00 slt s4, a4, s1 +8000063c: 93 87 04 00 mv a5, s1 +80000640: 33 0a ca 00 add s4, s4, a2 +80000644: b3 04 e6 02 mul s1, a2, a4 +80000648: 63 54 f7 00 bge a4, a5, 8 +8000064c: 93 07 07 00 mv a5, a4 +80000650: b3 84 f4 00 add s1, s1, a5 +80000654: 83 25 04 00 lw a1, 0(s0) +80000658: 03 27 c4 00 lw a4, 12(s0) +8000065c: 03 a9 05 00 lw s2, 0(a1) +80000660: 83 a9 45 00 lw s3, 4(a1) +80000664: b3 84 a4 02 mul s1, s1, a0 +80000668: b3 07 da 02 mul a5, s4, a3 +8000066c: b3 84 e4 00 add s1, s1, a4 +80000670: b3 84 f4 00 add s1, s1, a5 +80000674: 33 0a 9a 00 add s4, s4, s1 +80000678: b3 09 39 03 mul s3, s2, s3 +8000067c: 63 c0 44 07 blt s1, s4, 96 +80000680: 6f 00 00 08 j 128 +80000684: 03 47 e4 01 lbu a4, 30(s0) +80000688: 83 46 d4 01 lbu a3, 29(s0) +8000068c: 33 d7 e4 40 sra a4, s1, a4 +80000690: b3 07 37 03 mul a5, a4, s3 +80000694: b3 87 f4 40 sub a5, s1, a5 +80000698: 63 80 06 06 beqz a3, 96 +8000069c: 83 46 f4 01 lbu a3, 31(s0) +800006a0: b3 d6 d7 40 sra a3, a5, a3 +800006a4: b3 88 26 03 mul a7, a3, s2 +800006a8: 03 ae 45 01 lw t3, 20(a1) +800006ac: 03 a3 05 01 lw t1, 16(a1) +800006b0: 03 a6 c5 00 lw a2, 12(a1) +800006b4: 03 28 44 00 lw a6, 4(s0) +800006b8: 03 25 84 00 lw a0, 8(s0) +800006bc: 93 84 14 00 addi s1, s1, 1 +800006c0: 33 07 c7 01 add a4, a4, t3 +800006c4: b3 86 66 00 add a3, a3, t1 +800006c8: b3 87 17 41 sub a5, a5, a7 +800006cc: 33 86 c7 00 add a2, a5, a2 +800006d0: e7 00 08 00 jalr a6 +800006d4: 63 06 9a 02 beq s4, s1, 44 +800006d8: 83 25 04 00 lw a1, 0(s0) +800006dc: 83 47 c4 01 lbu a5, 28(s0) +800006e0: e3 92 07 fa bnez a5, -92 +800006e4: 33 c7 34 03 div a4, s1, s3 +800006e8: 83 46 d4 01 lbu a3, 29(s0) +800006ec: b3 07 37 03 mul a5, a4, s3 +800006f0: b3 87 f4 40 sub a5, s1, a5 +800006f4: e3 94 06 fa bnez a3, -88 +800006f8: b3 c6 27 03 div a3, a5, s2 +800006fc: 6f f0 9f fa j -88 +80000700: 03 27 84 01 lw a4, 24(s0) +80000704: 93 07 00 00 mv a5, zero +80000708: 6b c0 e7 00 vx_bar a5, a4 +8000070c: 83 20 c1 01 lw ra, 28(sp) +80000710: 03 24 81 01 lw s0, 24(sp) +80000714: 83 24 41 01 lw s1, 20(sp) +80000718: 03 29 01 01 lw s2, 16(sp) +8000071c: 83 29 c1 00 lw s3, 12(sp) +80000720: 03 2a 81 00 lw s4, 8(sp) +80000724: 13 01 01 02 addi sp, sp, 32 +80000728: 67 80 00 00 ret -80000ad4 __ieee754_sqrtf: -80000ad4: d3 06 05 e0 fmv.x.w a3, fa0 -80000ad8: 37 07 80 7f lui a4, 522240 -80000adc: 93 97 16 00 slli a5, a3, 1 -80000ae0: 93 d7 17 00 srli a5, a5, 1 -80000ae4: 63 f2 e7 0c bgeu a5, a4, 196 -80000ae8: 53 05 05 e0 fmv.x.w a0, fa0 -80000aec: 63 8a 07 0a beqz a5, 180 -80000af0: 93 87 06 00 mv a5, a3 -80000af4: 63 c6 06 0c bltz a3, 204 -80000af8: 33 76 d7 00 and a2, a4, a3 -80000afc: 13 d7 76 41 srai a4, a3, 23 -80000b00: 63 14 06 02 bnez a2, 40 -80000b04: 37 06 80 00 lui a2, 2048 -80000b08: b3 76 d6 00 and a3, a2, a3 -80000b0c: 63 94 06 0c bnez a3, 200 -80000b10: 93 97 17 00 slli a5, a5, 1 -80000b14: 93 95 87 00 slli a1, a5, 8 -80000b18: 13 86 06 00 mv a2, a3 -80000b1c: 93 86 16 00 addi a3, a3, 1 -80000b20: e3 d8 05 fe bgez a1, -16 -80000b24: 33 07 c7 40 sub a4, a4, a2 -80000b28: b7 06 80 00 lui a3, 2048 -80000b2c: 13 86 f6 ff addi a2, a3, -1 -80000b30: b3 f7 c7 00 and a5, a5, a2 -80000b34: 13 07 17 f8 addi a4, a4, -127 -80000b38: b3 e6 d7 00 or a3, a5, a3 -80000b3c: 13 76 17 00 andi a2, a4, 1 -80000b40: 93 97 16 00 slli a5, a3, 1 -80000b44: 63 1a 06 06 bnez a2, 116 -80000b48: 13 58 17 40 srai a6, a4, 1 -80000b4c: 93 06 90 01 addi a3, zero, 25 -80000b50: 13 05 00 00 mv a0, zero -80000b54: 93 05 00 00 mv a1, zero -80000b58: 37 07 00 01 lui a4, 4096 -80000b5c: 33 86 e5 00 add a2, a1, a4 -80000b60: 93 86 f6 ff addi a3, a3, -1 -80000b64: 63 c8 c7 00 blt a5, a2, 16 -80000b68: b3 05 e6 00 add a1, a2, a4 -80000b6c: b3 87 c7 40 sub a5, a5, a2 -80000b70: 33 05 e5 00 add a0, a0, a4 -80000b74: 93 97 17 00 slli a5, a5, 1 -80000b78: 13 57 17 00 srli a4, a4, 1 -80000b7c: e3 90 06 fe bnez a3, -32 -80000b80: 63 86 07 00 beqz a5, 12 -80000b84: 13 05 15 00 addi a0, a0, 1 -80000b88: 13 75 e5 ff andi a0, a0, -2 -80000b8c: 13 55 15 40 srai a0, a0, 1 -80000b90: b7 07 00 3f lui a5, 258048 -80000b94: 33 05 f5 00 add a0, a0, a5 -80000b98: 13 17 78 01 slli a4, a6, 23 -80000b9c: 33 05 a7 00 add a0, a4, a0 -80000ba0: 53 05 05 f0 fmv.w.x fa0, a0 -80000ba4: 67 80 00 00 ret -80000ba8: c3 77 a5 50 fmadd.s fa5, fa0, fa0, fa0 -80000bac: 53 85 07 e0 fmv.x.w a0, fa5 -80000bb0: 53 05 05 f0 fmv.w.x fa0, a0 -80000bb4: 67 80 00 00 ret -80000bb8: 93 97 26 00 slli a5, a3, 2 -80000bbc: 6f f0 df f8 j -116 -80000bc0: d3 77 a5 08 fsub.s fa5, fa0, fa0 -80000bc4: d3 f7 f7 18 fdiv.s fa5, fa5, fa5 -80000bc8: 53 85 07 e0 fmv.x.w a0, fa5 -80000bcc: 53 05 05 f0 fmv.w.x fa0, a0 -80000bd0: 67 80 00 00 ret -80000bd4: 13 06 f0 ff addi a2, zero, -1 -80000bd8: 33 07 c7 40 sub a4, a4, a2 -80000bdc: 6f f0 df f4 j -180 +8000072c spawn_kernel_rem_stub: +8000072c: f3 26 50 cc csrr a3, 3269 +80000730: f3 27 20 cc csrr a5, 3266 +80000734: 37 27 00 80 lui a4, 524290 +80000738: 93 96 26 00 slli a3, a3, 2 +8000073c: 13 07 c7 46 addi a4, a4, 1132 +80000740: 33 07 d7 00 add a4, a4, a3 +80000744: 03 25 07 00 lw a0, 0(a4) +80000748: 83 25 05 00 lw a1, 0(a0) +8000074c: 83 26 c5 00 lw a3, 12(a0) +80000750: 03 47 c5 01 lbu a4, 28(a0) +80000754: 83 a8 05 00 lw a7, 0(a1) +80000758: 03 a6 45 00 lw a2, 4(a1) +8000075c: b3 87 d7 00 add a5, a5, a3 +80000760: 33 86 c8 02 mul a2, a7, a2 +80000764: 63 08 07 04 beqz a4, 80 +80000768: 03 47 e5 01 lbu a4, 30(a0) +8000076c: 83 46 d5 01 lbu a3, 29(a0) +80000770: 33 d7 e7 40 sra a4, a5, a4 +80000774: 33 06 c7 02 mul a2, a4, a2 +80000778: b3 87 c7 40 sub a5, a5, a2 +8000077c: 63 86 06 04 beqz a3, 76 +80000780: 83 46 f5 01 lbu a3, 31(a0) +80000784: 33 d8 d7 40 sra a6, a5, a3 +80000788: 83 a6 05 01 lw a3, 16(a1) +8000078c: 03 ae 45 01 lw t3, 20(a1) +80000790: 03 a6 c5 00 lw a2, 12(a1) +80000794: b3 06 d8 00 add a3, a6, a3 +80000798: 33 08 18 03 mul a6, a6, a7 +8000079c: 03 23 45 00 lw t1, 4(a0) +800007a0: 03 25 85 00 lw a0, 8(a0) +800007a4: 33 07 c7 01 add a4, a4, t3 +800007a8: b3 87 07 41 sub a5, a5, a6 +800007ac: 33 86 c7 00 add a2, a5, a2 +800007b0: 67 00 03 00 jr t1 +800007b4: 33 c7 c7 02 div a4, a5, a2 +800007b8: 83 46 d5 01 lbu a3, 29(a0) +800007bc: 33 06 c7 02 mul a2, a4, a2 +800007c0: b3 87 c7 40 sub a5, a5, a2 +800007c4: e3 9e 06 fa bnez a3, -68 +800007c8: 33 c8 17 03 div a6, a5, a7 +800007cc: 6f f0 df fb j -68 -80000be0 atexit: -80000be0: 93 05 05 00 mv a1, a0 -80000be4: 93 06 00 00 mv a3, zero -80000be8: 13 06 00 00 mv a2, zero -80000bec: 13 05 00 00 mv a0, zero -80000bf0: 6f 00 80 21 j 536 +800007d0 spawn_kernel_all_cb: +800007d0: 13 01 01 ff addi sp, sp, -16 +800007d4: 23 26 11 00 sw ra, 12(sp) +800007d8: 93 07 f0 ff addi a5, zero, -1 +800007dc: 6b 80 07 00 vx_tmc a5 +800007e0: ef f0 1f e1 jal -496 +800007e4: f3 27 30 cc csrr a5, 3267 +800007e8: 93 b7 17 00 seqz a5, a5 +800007ec: 6b 80 07 00 vx_tmc a5 +800007f0: 83 20 c1 00 lw ra, 12(sp) +800007f4: 13 01 01 01 addi sp, sp, 16 +800007f8: 67 80 00 00 ret -80000bf4 __errno: -80000bf4: b7 17 00 80 lui a5, 524289 -80000bf8: 03 a5 47 43 lw a0, 1076(a5) -80000bfc: 67 80 00 00 ret +800007fc vx_spawn_kernel: +800007fc: 13 01 01 fd addi sp, sp, -48 +80000800: 23 26 11 02 sw ra, 44(sp) +80000804: 23 24 81 02 sw s0, 40(sp) +80000808: 23 22 91 02 sw s1, 36(sp) +8000080c: 23 20 21 03 sw s2, 32(sp) +80000810: f3 28 20 fc csrr a7, 4034 +80000814: 73 23 10 fc csrr t1, 4033 +80000818: f3 24 00 fc csrr s1, 4032 +8000081c: f3 27 50 cc csrr a5, 3269 +80000820: 13 07 f0 01 addi a4, zero, 31 +80000824: 63 46 f7 0e blt a4, a5, 236 +80000828: 03 2e 05 00 lw t3, 0(a0) +8000082c: 83 26 45 00 lw a3, 4(a0) +80000830: 03 28 85 00 lw a6, 8(a0) +80000834: b3 0e 93 02 mul t4, t1, s1 +80000838: 13 07 10 00 addi a4, zero, 1 +8000083c: b3 06 de 02 mul a3, t3, a3 +80000840: 33 88 06 03 mul a6, a3, a6 +80000844: 63 d4 0e 01 bge t4, a6, 8 +80000848: 33 47 d8 03 div a4, a6, t4 +8000084c: 63 ce e8 0c blt a7, a4, 220 +80000850: 63 d0 e7 0c bge a5, a4, 192 +80000854: 93 88 f8 ff addi a7, a7, -1 +80000858: b3 4e e8 02 div t4, a6, a4 +8000085c: 13 84 0e 00 mv s0, t4 +80000860: 63 96 f8 00 bne a7, a5, 12 +80000864: 33 67 e8 02 rem a4, a6, a4 +80000868: 33 04 d7 01 add s0, a4, t4 +8000086c: 33 49 94 02 div s2, s0, s1 +80000870: 33 64 94 02 rem s0, s0, s1 +80000874: 63 40 69 0c blt s2, t1, 192 +80000878: 93 0f 10 00 addi t6, zero, 1 +8000087c: 33 4f 69 02 div t5, s2, t1 +80000880: 63 06 0f 00 beqz t5, 12 +80000884: 93 0f 0f 00 mv t6, t5 +80000888: 33 6f 69 02 rem t5, s2, t1 +8000088c: d3 f7 06 d0 fcvt.s.w fa5, a3 +80000890: 13 07 fe ff addi a4, t3, -1 +80000894: 93 82 f6 ff addi t0, a3, -1 +80000898: d3 88 07 e0 fmv.x.w a7, fa5 +8000089c: d3 77 0e d0 fcvt.s.w fa5, t3 +800008a0: 33 7e c7 01 and t3, a4, t3 +800008a4: 37 27 00 80 lui a4, 524290 +800008a8: 53 88 07 e0 fmv.x.w a6, fa5 +800008ac: b3 f6 d2 00 and a3, t0, a3 +800008b0: 93 d8 78 41 srai a7, a7, 23 +800008b4: 13 58 78 41 srai a6, a6, 23 +800008b8: 13 07 c7 46 addi a4, a4, 1132 +800008bc: 93 b6 16 00 seqz a3, a3 +800008c0: 13 3e 1e 00 seqz t3, t3 +800008c4: 93 88 18 f8 addi a7, a7, -127 +800008c8: 13 08 18 f8 addi a6, a6, -127 +800008cc: 23 20 a1 00 sw a0, 0(sp) +800008d0: 23 22 b1 00 sw a1, 4(sp) +800008d4: 23 24 c1 00 sw a2, 8(sp) +800008d8: 23 28 f1 01 sw t6, 16(sp) +800008dc: 23 2a e1 01 sw t5, 20(sp) +800008e0: 23 2c 01 00 sw zero, 24(sp) +800008e4: 23 0e d1 00 sb a3, 28(sp) +800008e8: a3 0e c1 01 sb t3, 29(sp) +800008ec: 23 0f 11 01 sb a7, 30(sp) +800008f0: a3 0f 01 01 sb a6, 31(sp) +800008f4: b3 8e fe 02 mul t4, t4, a5 +800008f8: 93 97 27 00 slli a5, a5, 2 +800008fc: b3 07 f7 00 add a5, a4, a5 +80000900: 23 a0 27 00 sw sp, 0(a5) +80000904: 23 26 d1 01 sw t4, 12(sp) +80000908: 63 4c 20 03 bgtz s2, 56 +8000090c: 63 16 04 06 bnez s0, 108 +80000910: 83 20 c1 02 lw ra, 44(sp) +80000914: 03 24 81 02 lw s0, 40(sp) +80000918: 83 24 41 02 lw s1, 36(sp) +8000091c: 03 29 01 02 lw s2, 32(sp) +80000920: 13 01 01 03 addi sp, sp, 48 +80000924: 67 80 00 00 ret +80000928: 13 87 08 00 mv a4, a7 +8000092c: e3 c4 e7 f2 blt a5, a4, -216 +80000930: 6f f0 1f fe j -32 +80000934: 13 0f 00 00 mv t5, zero +80000938: 93 0f 10 00 addi t6, zero, 1 +8000093c: 6f f0 1f f5 j -176 +80000940: 13 07 09 00 mv a4, s2 +80000944: 63 54 23 01 bge t1, s2, 8 +80000948: 13 07 03 00 mv a4, t1 +8000094c: b7 07 00 80 lui a5, 524288 +80000950: 23 2c e1 00 sw a4, 24(sp) +80000954: 93 87 07 7d addi a5, a5, 2000 +80000958: 6b 10 f7 00 vx_wspawn a4, a5 +8000095c: 93 07 f0 ff addi a5, zero, -1 +80000960: 6b 80 07 00 vx_tmc a5 +80000964: ef f0 df c8 jal -884 +80000968: f3 27 30 cc csrr a5, 3267 +8000096c: 93 b7 17 00 seqz a5, a5 +80000970: 6b 80 07 00 vx_tmc a5 +80000974: e3 0e 04 f8 beqz s0, -100 +80000978: b3 04 99 02 mul s1, s2, s1 +8000097c: 13 09 10 00 addi s2, zero, 1 +80000980: 33 14 89 00 sll s0, s2, s0 +80000984: 13 04 f4 ff addi s0, s0, -1 +80000988: 23 26 91 00 sw s1, 12(sp) +8000098c: 6b 00 04 00 vx_tmc s0 +80000990: ef f0 df d9 jal -612 +80000994: 6b 00 09 00 vx_tmc s2 +80000998: 83 20 c1 02 lw ra, 44(sp) +8000099c: 03 24 81 02 lw s0, 40(sp) +800009a0: 83 24 41 02 lw s1, 36(sp) +800009a4: 03 29 01 02 lw s2, 32(sp) +800009a8: 13 01 01 03 addi sp, sp, 48 +800009ac: 67 80 00 00 ret -80000c00 exit: -80000c00: 13 01 01 ff addi sp, sp, -16 -80000c04: 93 05 00 00 mv a1, zero -80000c08: 23 24 81 00 sw s0, 8(sp) -80000c0c: 23 26 11 00 sw ra, 12(sp) -80000c10: 13 04 05 00 mv s0, a0 -80000c14: ef 00 00 29 jal 656 -80000c18: b7 17 00 80 lui a5, 524289 -80000c1c: 03 a5 07 43 lw a0, 1072(a5) -80000c20: 83 27 c5 03 lw a5, 60(a0) -80000c24: 63 84 07 00 beqz a5, 8 -80000c28: e7 80 07 00 jalr a5 -80000c2c: 13 05 04 00 mv a0, s0 -80000c30: ef f0 1f 86 jal -1952 +800009b0 vx_perf_dump: +800009b0: f3 27 50 cc csrr a5, 3269 +800009b4: 37 07 ff 00 lui a4, 4080 +800009b8: b3 87 e7 00 add a5, a5, a4 +800009bc: 93 97 87 00 slli a5, a5, 8 +800009c0: 73 27 00 b0 csrr a4, mcycle +800009c4: 23 a0 e7 00 sw a4, 0(a5) +800009c8: 73 27 10 b0 csrr a4, 2817 +800009cc: 23 a2 e7 00 sw a4, 4(a5) +800009d0: 73 27 20 b0 csrr a4, minstret +800009d4: 23 a4 e7 00 sw a4, 8(a5) +800009d8: 73 27 30 b0 csrr a4, mhpmcounter3 +800009dc: 23 a6 e7 00 sw a4, 12(a5) +800009e0: 73 27 40 b0 csrr a4, mhpmcounter4 +800009e4: 23 a8 e7 00 sw a4, 16(a5) +800009e8: 73 27 50 b0 csrr a4, mhpmcounter5 +800009ec: 23 aa e7 00 sw a4, 20(a5) +800009f0: 73 27 60 b0 csrr a4, mhpmcounter6 +800009f4: 23 ac e7 00 sw a4, 24(a5) +800009f8: 73 27 70 b0 csrr a4, mhpmcounter7 +800009fc: 23 ae e7 00 sw a4, 28(a5) +80000a00: 73 27 80 b0 csrr a4, mhpmcounter8 +80000a04: 23 a0 e7 02 sw a4, 32(a5) +80000a08: 73 27 90 b0 csrr a4, mhpmcounter9 +80000a0c: 23 a2 e7 02 sw a4, 36(a5) +80000a10: 73 27 a0 b0 csrr a4, mhpmcounter10 +80000a14: 23 a4 e7 02 sw a4, 40(a5) +80000a18: 73 27 b0 b0 csrr a4, mhpmcounter11 +80000a1c: 23 a6 e7 02 sw a4, 44(a5) +80000a20: 73 27 c0 b0 csrr a4, mhpmcounter12 +80000a24: 23 a8 e7 02 sw a4, 48(a5) +80000a28: 73 27 d0 b0 csrr a4, mhpmcounter13 +80000a2c: 23 aa e7 02 sw a4, 52(a5) +80000a30: 73 27 e0 b0 csrr a4, mhpmcounter14 +80000a34: 23 ac e7 02 sw a4, 56(a5) +80000a38: 73 27 f0 b0 csrr a4, mhpmcounter15 +80000a3c: 23 ae e7 02 sw a4, 60(a5) +80000a40: 73 27 00 b1 csrr a4, mhpmcounter16 +80000a44: 23 a0 e7 04 sw a4, 64(a5) +80000a48: 73 27 10 b1 csrr a4, mhpmcounter17 +80000a4c: 23 a2 e7 04 sw a4, 68(a5) +80000a50: 73 27 20 b1 csrr a4, mhpmcounter18 +80000a54: 23 a4 e7 04 sw a4, 72(a5) +80000a58: 73 27 30 b1 csrr a4, mhpmcounter19 +80000a5c: 23 a6 e7 04 sw a4, 76(a5) +80000a60: 73 27 40 b1 csrr a4, mhpmcounter20 +80000a64: 23 a8 e7 04 sw a4, 80(a5) +80000a68: 73 27 50 b1 csrr a4, mhpmcounter21 +80000a6c: 23 aa e7 04 sw a4, 84(a5) +80000a70: 73 27 60 b1 csrr a4, mhpmcounter22 +80000a74: 23 ac e7 04 sw a4, 88(a5) +80000a78: 73 27 70 b1 csrr a4, mhpmcounter23 +80000a7c: 23 ae e7 04 sw a4, 92(a5) +80000a80: 73 27 80 b1 csrr a4, mhpmcounter24 +80000a84: 23 a0 e7 06 sw a4, 96(a5) +80000a88: 73 27 90 b1 csrr a4, mhpmcounter25 +80000a8c: 23 a2 e7 06 sw a4, 100(a5) +80000a90: 73 27 a0 b1 csrr a4, mhpmcounter26 +80000a94: 23 a4 e7 06 sw a4, 104(a5) +80000a98: 73 27 b0 b1 csrr a4, mhpmcounter27 +80000a9c: 23 a6 e7 06 sw a4, 108(a5) +80000aa0: 73 27 c0 b1 csrr a4, mhpmcounter28 +80000aa4: 23 a8 e7 06 sw a4, 112(a5) +80000aa8: 73 27 d0 b1 csrr a4, mhpmcounter29 +80000aac: 23 aa e7 06 sw a4, 116(a5) +80000ab0: 73 27 e0 b1 csrr a4, mhpmcounter30 +80000ab4: 23 ac e7 06 sw a4, 120(a5) +80000ab8: 73 27 f0 b1 csrr a4, mhpmcounter31 +80000abc: 23 ae e7 06 sw a4, 124(a5) +80000ac0: 73 27 00 b8 csrr a4, mcycleh +80000ac4: 23 a0 e7 08 sw a4, 128(a5) +80000ac8: 73 27 10 b8 csrr a4, 2945 +80000acc: 23 a2 e7 08 sw a4, 132(a5) +80000ad0: 73 27 20 b8 csrr a4, minstreth +80000ad4: 23 a4 e7 08 sw a4, 136(a5) +80000ad8: 73 27 30 b8 csrr a4, mhpmcounter3h +80000adc: 23 a6 e7 08 sw a4, 140(a5) +80000ae0: 73 27 40 b8 csrr a4, mhpmcounter4h +80000ae4: 23 a8 e7 08 sw a4, 144(a5) +80000ae8: 73 27 50 b8 csrr a4, mhpmcounter5h +80000aec: 23 aa e7 08 sw a4, 148(a5) +80000af0: 73 27 60 b8 csrr a4, mhpmcounter6h +80000af4: 23 ac e7 08 sw a4, 152(a5) +80000af8: 73 27 70 b8 csrr a4, mhpmcounter7h +80000afc: 23 ae e7 08 sw a4, 156(a5) +80000b00: 73 27 80 b8 csrr a4, mhpmcounter8h +80000b04: 23 a0 e7 0a sw a4, 160(a5) +80000b08: 73 27 90 b8 csrr a4, mhpmcounter9h +80000b0c: 23 a2 e7 0a sw a4, 164(a5) +80000b10: 73 27 a0 b8 csrr a4, mhpmcounter10h +80000b14: 23 a4 e7 0a sw a4, 168(a5) +80000b18: 73 27 b0 b8 csrr a4, mhpmcounter11h +80000b1c: 23 a6 e7 0a sw a4, 172(a5) +80000b20: 73 27 c0 b8 csrr a4, mhpmcounter12h +80000b24: 23 a8 e7 0a sw a4, 176(a5) +80000b28: 73 27 d0 b8 csrr a4, mhpmcounter13h +80000b2c: 23 aa e7 0a sw a4, 180(a5) +80000b30: 73 27 e0 b8 csrr a4, mhpmcounter14h +80000b34: 23 ac e7 0a sw a4, 184(a5) +80000b38: 73 27 f0 b8 csrr a4, mhpmcounter15h +80000b3c: 23 ae e7 0a sw a4, 188(a5) +80000b40: 73 27 00 b9 csrr a4, mhpmcounter16h +80000b44: 23 a0 e7 0c sw a4, 192(a5) +80000b48: 73 27 10 b9 csrr a4, mhpmcounter17h +80000b4c: 23 a2 e7 0c sw a4, 196(a5) +80000b50: 73 27 20 b9 csrr a4, mhpmcounter18h +80000b54: 23 a4 e7 0c sw a4, 200(a5) +80000b58: 73 27 30 b9 csrr a4, mhpmcounter19h +80000b5c: 23 a6 e7 0c sw a4, 204(a5) +80000b60: 73 27 40 b9 csrr a4, mhpmcounter20h +80000b64: 23 a8 e7 0c sw a4, 208(a5) +80000b68: 73 27 50 b9 csrr a4, mhpmcounter21h +80000b6c: 23 aa e7 0c sw a4, 212(a5) +80000b70: 73 27 60 b9 csrr a4, mhpmcounter22h +80000b74: 23 ac e7 0c sw a4, 216(a5) +80000b78: 73 27 70 b9 csrr a4, mhpmcounter23h +80000b7c: 23 ae e7 0c sw a4, 220(a5) +80000b80: 73 27 80 b9 csrr a4, mhpmcounter24h +80000b84: 23 a0 e7 0e sw a4, 224(a5) +80000b88: 73 27 90 b9 csrr a4, mhpmcounter25h +80000b8c: 23 a2 e7 0e sw a4, 228(a5) +80000b90: 73 27 a0 b9 csrr a4, mhpmcounter26h +80000b94: 23 a4 e7 0e sw a4, 232(a5) +80000b98: 73 27 b0 b9 csrr a4, mhpmcounter27h +80000b9c: 23 a6 e7 0e sw a4, 236(a5) +80000ba0: 73 27 c0 b9 csrr a4, mhpmcounter28h +80000ba4: 23 a8 e7 0e sw a4, 240(a5) +80000ba8: 73 27 d0 b9 csrr a4, mhpmcounter29h +80000bac: 23 aa e7 0e sw a4, 244(a5) +80000bb0: 73 27 e0 b9 csrr a4, mhpmcounter30h +80000bb4: 23 ac e7 0e sw a4, 248(a5) +80000bb8: 73 27 f0 b9 csrr a4, mhpmcounter31h +80000bbc: 23 ae e7 0e sw a4, 252(a5) +80000bc0: 67 80 00 00 ret -80000c34 __libc_fini_array: -80000c34: 13 01 01 ff addi sp, sp, -16 -80000c38: 23 24 81 00 sw s0, 8(sp) -80000c3c: b7 17 00 80 lui a5, 524289 -80000c40: 37 14 00 80 lui s0, 524289 -80000c44: 13 04 44 00 addi s0, s0, 4 -80000c48: 93 87 47 00 addi a5, a5, 4 -80000c4c: b3 87 87 40 sub a5, a5, s0 -80000c50: 23 22 91 00 sw s1, 4(sp) -80000c54: 23 26 11 00 sw ra, 12(sp) -80000c58: 93 d4 27 40 srai s1, a5, 2 -80000c5c: 63 80 04 02 beqz s1, 32 -80000c60: 93 87 c7 ff addi a5, a5, -4 -80000c64: 33 84 87 00 add s0, a5, s0 -80000c68: 83 27 04 00 lw a5, 0(s0) -80000c6c: 93 84 f4 ff addi s1, s1, -1 -80000c70: 13 04 c4 ff addi s0, s0, -4 -80000c74: e7 80 07 00 jalr a5 -80000c78: e3 98 04 fe bnez s1, -16 -80000c7c: 83 20 c1 00 lw ra, 12(sp) -80000c80: 03 24 81 00 lw s0, 8(sp) -80000c84: 83 24 41 00 lw s1, 4(sp) -80000c88: 13 01 01 01 addi sp, sp, 16 -80000c8c: 67 80 00 00 ret +80000bc4 sqrtf: +80000bc4: 13 01 01 fe addi sp, sp, -32 +80000bc8: 27 26 81 00 fsw fs0, 12(sp) +80000bcc: 23 2e 11 00 sw ra, 28(sp) +80000bd0: 53 04 a5 20 fmv.s fs0, fa0 +80000bd4: 27 24 91 00 fsw fs1, 8(sp) +80000bd8: ef 00 00 06 jal 96 +80000bdc: b7 27 00 80 lui a5, 524290 +80000be0: 03 a7 87 46 lw a4, 1128(a5) +80000be4: 93 07 f0 ff addi a5, zero, -1 +80000be8: 63 0c f7 00 beq a4, a5, 24 +80000bec: d3 27 84 a0 feq.s a5, fs0, fs0 +80000bf0: 63 88 07 00 beqz a5, 16 +80000bf4: d3 04 00 f0 fmv.w.x fs1, zero +80000bf8: d3 17 94 a0 flt.s a5, fs0, fs1 +80000bfc: 63 9c 07 00 bnez a5, 24 +80000c00: 83 20 c1 01 lw ra, 28(sp) +80000c04: 07 24 c1 00 flw fs0, 12(sp) +80000c08: 87 24 81 00 flw fs1, 8(sp) +80000c0c: 13 01 01 02 addi sp, sp, 32 +80000c10: 67 80 00 00 ret +80000c14: ef 00 40 14 jal 324 +80000c18: 83 20 c1 01 lw ra, 28(sp) +80000c1c: 93 07 10 02 addi a5, zero, 33 +80000c20: 23 20 f5 00 sw a5, 0(a0) +80000c24: 53 f5 94 18 fdiv.s fa0, fs1, fs1 +80000c28: 07 24 c1 00 flw fs0, 12(sp) +80000c2c: 87 24 81 00 flw fs1, 8(sp) +80000c30: 13 01 01 02 addi sp, sp, 32 +80000c34: 67 80 00 00 ret -80000c90 __libc_init_array: -80000c90: 13 01 01 ff addi sp, sp, -16 -80000c94: 23 24 81 00 sw s0, 8(sp) -80000c98: 23 20 21 01 sw s2, 0(sp) -80000c9c: 37 14 00 80 lui s0, 524289 -80000ca0: 37 19 00 80 lui s2, 524289 -80000ca4: 93 07 04 00 mv a5, s0 -80000ca8: 13 09 09 00 mv s2, s2 -80000cac: 33 09 f9 40 sub s2, s2, a5 -80000cb0: 23 26 11 00 sw ra, 12(sp) -80000cb4: 23 22 91 00 sw s1, 4(sp) -80000cb8: 13 59 29 40 srai s2, s2, 2 -80000cbc: 63 00 09 02 beqz s2, 32 -80000cc0: 13 04 04 00 mv s0, s0 -80000cc4: 93 04 00 00 mv s1, zero -80000cc8: 83 27 04 00 lw a5, 0(s0) -80000ccc: 93 84 14 00 addi s1, s1, 1 -80000cd0: 13 04 44 00 addi s0, s0, 4 -80000cd4: e7 80 07 00 jalr a5 -80000cd8: e3 18 99 fe bne s2, s1, -16 -80000cdc: 37 14 00 80 lui s0, 524289 -80000ce0: 37 19 00 80 lui s2, 524289 -80000ce4: 93 07 04 00 mv a5, s0 -80000ce8: 13 09 49 00 addi s2, s2, 4 -80000cec: 33 09 f9 40 sub s2, s2, a5 -80000cf0: 13 59 29 40 srai s2, s2, 2 -80000cf4: 63 00 09 02 beqz s2, 32 -80000cf8: 13 04 04 00 mv s0, s0 -80000cfc: 93 04 00 00 mv s1, zero -80000d00: 83 27 04 00 lw a5, 0(s0) -80000d04: 93 84 14 00 addi s1, s1, 1 -80000d08: 13 04 44 00 addi s0, s0, 4 -80000d0c: e7 80 07 00 jalr a5 -80000d10: e3 18 99 fe bne s2, s1, -16 -80000d14: 83 20 c1 00 lw ra, 12(sp) -80000d18: 03 24 81 00 lw s0, 8(sp) -80000d1c: 83 24 41 00 lw s1, 4(sp) -80000d20: 03 29 01 00 lw s2, 0(sp) -80000d24: 13 01 01 01 addi sp, sp, 16 -80000d28: 67 80 00 00 ret +80000c38 __ieee754_sqrtf: +80000c38: d3 06 05 e0 fmv.x.w a3, fa0 +80000c3c: 37 07 80 7f lui a4, 522240 +80000c40: 93 97 16 00 slli a5, a3, 1 +80000c44: 93 d7 17 00 srli a5, a5, 1 +80000c48: 63 f2 e7 0c bgeu a5, a4, 196 +80000c4c: 53 05 05 e0 fmv.x.w a0, fa0 +80000c50: 63 8a 07 0a beqz a5, 180 +80000c54: 93 87 06 00 mv a5, a3 +80000c58: 63 c6 06 0c bltz a3, 204 +80000c5c: 33 76 d7 00 and a2, a4, a3 +80000c60: 13 d7 76 41 srai a4, a3, 23 +80000c64: 63 14 06 02 bnez a2, 40 +80000c68: 37 06 80 00 lui a2, 2048 +80000c6c: b3 76 d6 00 and a3, a2, a3 +80000c70: 63 94 06 0c bnez a3, 200 +80000c74: 93 97 17 00 slli a5, a5, 1 +80000c78: 93 95 87 00 slli a1, a5, 8 +80000c7c: 13 86 06 00 mv a2, a3 +80000c80: 93 86 16 00 addi a3, a3, 1 +80000c84: e3 d8 05 fe bgez a1, -16 +80000c88: 33 07 c7 40 sub a4, a4, a2 +80000c8c: b7 06 80 00 lui a3, 2048 +80000c90: 13 86 f6 ff addi a2, a3, -1 +80000c94: b3 f7 c7 00 and a5, a5, a2 +80000c98: 13 07 17 f8 addi a4, a4, -127 +80000c9c: b3 e6 d7 00 or a3, a5, a3 +80000ca0: 13 76 17 00 andi a2, a4, 1 +80000ca4: 93 97 16 00 slli a5, a3, 1 +80000ca8: 63 1a 06 06 bnez a2, 116 +80000cac: 13 58 17 40 srai a6, a4, 1 +80000cb0: 93 06 90 01 addi a3, zero, 25 +80000cb4: 13 05 00 00 mv a0, zero +80000cb8: 93 05 00 00 mv a1, zero +80000cbc: 37 07 00 01 lui a4, 4096 +80000cc0: 33 86 e5 00 add a2, a1, a4 +80000cc4: 93 86 f6 ff addi a3, a3, -1 +80000cc8: 63 c8 c7 00 blt a5, a2, 16 +80000ccc: b3 05 e6 00 add a1, a2, a4 +80000cd0: b3 87 c7 40 sub a5, a5, a2 +80000cd4: 33 05 e5 00 add a0, a0, a4 +80000cd8: 93 97 17 00 slli a5, a5, 1 +80000cdc: 13 57 17 00 srli a4, a4, 1 +80000ce0: e3 90 06 fe bnez a3, -32 +80000ce4: 63 86 07 00 beqz a5, 12 +80000ce8: 13 05 15 00 addi a0, a0, 1 +80000cec: 13 75 e5 ff andi a0, a0, -2 +80000cf0: 13 55 15 40 srai a0, a0, 1 +80000cf4: b7 07 00 3f lui a5, 258048 +80000cf8: 33 05 f5 00 add a0, a0, a5 +80000cfc: 13 17 78 01 slli a4, a6, 23 +80000d00: 33 05 a7 00 add a0, a4, a0 +80000d04: 53 05 05 f0 fmv.w.x fa0, a0 +80000d08: 67 80 00 00 ret +80000d0c: c3 77 a5 50 fmadd.s fa5, fa0, fa0, fa0 +80000d10: 53 85 07 e0 fmv.x.w a0, fa5 +80000d14: 53 05 05 f0 fmv.w.x fa0, a0 +80000d18: 67 80 00 00 ret +80000d1c: 93 97 26 00 slli a5, a3, 2 +80000d20: 6f f0 df f8 j -116 +80000d24: d3 77 a5 08 fsub.s fa5, fa0, fa0 +80000d28: d3 f7 f7 18 fdiv.s fa5, fa5, fa5 +80000d2c: 53 85 07 e0 fmv.x.w a0, fa5 +80000d30: 53 05 05 f0 fmv.w.x fa0, a0 +80000d34: 67 80 00 00 ret +80000d38: 13 06 f0 ff addi a2, zero, -1 +80000d3c: 33 07 c7 40 sub a4, a4, a2 +80000d40: 6f f0 df f4 j -180 -80000d2c memset: -80000d2c: 13 03 f0 00 addi t1, zero, 15 -80000d30: 13 07 05 00 mv a4, a0 -80000d34: 63 7e c3 02 bgeu t1, a2, 60 -80000d38: 93 77 f7 00 andi a5, a4, 15 -80000d3c: 63 90 07 0a bnez a5, 160 -80000d40: 63 92 05 08 bnez a1, 132 -80000d44: 93 76 06 ff andi a3, a2, -16 -80000d48: 13 76 f6 00 andi a2, a2, 15 -80000d4c: b3 86 e6 00 add a3, a3, a4 -80000d50: 23 20 b7 00 sw a1, 0(a4) -80000d54: 23 22 b7 00 sw a1, 4(a4) -80000d58: 23 24 b7 00 sw a1, 8(a4) -80000d5c: 23 26 b7 00 sw a1, 12(a4) -80000d60: 13 07 07 01 addi a4, a4, 16 -80000d64: e3 66 d7 fe bltu a4, a3, -20 -80000d68: 63 14 06 00 bnez a2, 8 -80000d6c: 67 80 00 00 ret -80000d70: b3 06 c3 40 sub a3, t1, a2 -80000d74: 93 96 26 00 slli a3, a3, 2 -80000d78: 97 02 00 00 auipc t0, 0 -80000d7c: b3 86 56 00 add a3, a3, t0 -80000d80: 67 80 c6 00 jr 12(a3) -80000d84: 23 07 b7 00 sb a1, 14(a4) -80000d88: a3 06 b7 00 sb a1, 13(a4) -80000d8c: 23 06 b7 00 sb a1, 12(a4) -80000d90: a3 05 b7 00 sb a1, 11(a4) -80000d94: 23 05 b7 00 sb a1, 10(a4) -80000d98: a3 04 b7 00 sb a1, 9(a4) -80000d9c: 23 04 b7 00 sb a1, 8(a4) -80000da0: a3 03 b7 00 sb a1, 7(a4) -80000da4: 23 03 b7 00 sb a1, 6(a4) -80000da8: a3 02 b7 00 sb a1, 5(a4) -80000dac: 23 02 b7 00 sb a1, 4(a4) -80000db0: a3 01 b7 00 sb a1, 3(a4) -80000db4: 23 01 b7 00 sb a1, 2(a4) -80000db8: a3 00 b7 00 sb a1, 1(a4) -80000dbc: 23 00 b7 00 sb a1, 0(a4) -80000dc0: 67 80 00 00 ret -80000dc4: 93 f5 f5 0f andi a1, a1, 255 -80000dc8: 93 96 85 00 slli a3, a1, 8 -80000dcc: b3 e5 d5 00 or a1, a1, a3 -80000dd0: 93 96 05 01 slli a3, a1, 16 -80000dd4: b3 e5 d5 00 or a1, a1, a3 -80000dd8: 6f f0 df f6 j -148 -80000ddc: 93 96 27 00 slli a3, a5, 2 -80000de0: 97 02 00 00 auipc t0, 0 -80000de4: b3 86 56 00 add a3, a3, t0 -80000de8: 93 82 00 00 mv t0, ra -80000dec: e7 80 06 fa jalr -96(a3) -80000df0: 93 80 02 00 mv ra, t0 -80000df4: 93 87 07 ff addi a5, a5, -16 -80000df8: 33 07 f7 40 sub a4, a4, a5 -80000dfc: 33 06 f6 00 add a2, a2, a5 -80000e00: e3 78 c3 f6 bgeu t1, a2, -144 -80000e04: 6f f0 df f3 j -196 +80000d44 atexit: +80000d44: 93 05 05 00 mv a1, a0 +80000d48: 93 06 00 00 mv a3, zero +80000d4c: 13 06 00 00 mv a2, zero +80000d50: 13 05 00 00 mv a0, zero +80000d54: 6f 00 00 12 j 288 -80000e08 __register_exitproc: -80000e08: b7 17 00 80 lui a5, 524289 -80000e0c: 03 a7 07 43 lw a4, 1072(a5) -80000e10: 83 27 87 14 lw a5, 328(a4) -80000e14: 63 8c 07 04 beqz a5, 88 -80000e18: 03 a7 47 00 lw a4, 4(a5) -80000e1c: 13 08 f0 01 addi a6, zero, 31 -80000e20: 63 4e e8 06 blt a6, a4, 124 -80000e24: 13 18 27 00 slli a6, a4, 2 -80000e28: 63 06 05 02 beqz a0, 44 -80000e2c: 33 83 07 01 add t1, a5, a6 -80000e30: 23 24 c3 08 sw a2, 136(t1) -80000e34: 83 a8 87 18 lw a7, 392(a5) -80000e38: 13 06 10 00 addi a2, zero, 1 -80000e3c: 33 16 e6 00 sll a2, a2, a4 -80000e40: b3 e8 c8 00 or a7, a7, a2 -80000e44: 23 a4 17 19 sw a7, 392(a5) -80000e48: 23 24 d3 10 sw a3, 264(t1) -80000e4c: 93 06 20 00 addi a3, zero, 2 -80000e50: 63 04 d5 02 beq a0, a3, 40 -80000e54: 13 07 17 00 addi a4, a4, 1 -80000e58: 23 a2 e7 00 sw a4, 4(a5) -80000e5c: b3 87 07 01 add a5, a5, a6 -80000e60: 23 a4 b7 00 sw a1, 8(a5) -80000e64: 13 05 00 00 mv a0, zero -80000e68: 67 80 00 00 ret -80000e6c: 93 07 c7 14 addi a5, a4, 332 -80000e70: 23 24 f7 14 sw a5, 328(a4) -80000e74: 6f f0 5f fa j -92 -80000e78: 83 a6 c7 18 lw a3, 396(a5) -80000e7c: 13 07 17 00 addi a4, a4, 1 -80000e80: 23 a2 e7 00 sw a4, 4(a5) -80000e84: 33 e6 c6 00 or a2, a3, a2 -80000e88: 23 a6 c7 18 sw a2, 396(a5) -80000e8c: b3 87 07 01 add a5, a5, a6 -80000e90: 23 a4 b7 00 sw a1, 8(a5) -80000e94: 13 05 00 00 mv a0, zero -80000e98: 67 80 00 00 ret -80000e9c: 13 05 f0 ff addi a0, zero, -1 -80000ea0: 67 80 00 00 ret +80000d58 __errno: +80000d58: b7 27 00 80 lui a5, 524290 +80000d5c: 03 a5 47 46 lw a0, 1124(a5) +80000d60: 67 80 00 00 ret -80000ea4 __call_exitprocs: -80000ea4: 13 01 01 fd addi sp, sp, -48 -80000ea8: b7 17 00 80 lui a5, 524289 -80000eac: 23 2c 41 01 sw s4, 24(sp) -80000eb0: 03 aa 07 43 lw s4, 1072(a5) -80000eb4: 23 20 21 03 sw s2, 32(sp) -80000eb8: 23 26 11 02 sw ra, 44(sp) -80000ebc: 03 29 8a 14 lw s2, 328(s4) -80000ec0: 23 24 81 02 sw s0, 40(sp) -80000ec4: 23 22 91 02 sw s1, 36(sp) -80000ec8: 23 2e 31 01 sw s3, 28(sp) -80000ecc: 23 2a 51 01 sw s5, 20(sp) -80000ed0: 23 28 61 01 sw s6, 16(sp) -80000ed4: 23 26 71 01 sw s7, 12(sp) -80000ed8: 23 24 81 01 sw s8, 8(sp) -80000edc: 63 00 09 04 beqz s2, 64 -80000ee0: 13 0b 05 00 mv s6, a0 -80000ee4: 93 8b 05 00 mv s7, a1 -80000ee8: 93 0a 10 00 addi s5, zero, 1 -80000eec: 93 09 f0 ff addi s3, zero, -1 -80000ef0: 83 24 49 00 lw s1, 4(s2) -80000ef4: 13 84 f4 ff addi s0, s1, -1 -80000ef8: 63 42 04 02 bltz s0, 36 -80000efc: 93 94 24 00 slli s1, s1, 2 -80000f00: b3 04 99 00 add s1, s2, s1 -80000f04: 63 84 0b 04 beqz s7, 72 -80000f08: 83 a7 44 10 lw a5, 260(s1) -80000f0c: 63 80 77 05 beq a5, s7, 64 -80000f10: 13 04 f4 ff addi s0, s0, -1 -80000f14: 93 84 c4 ff addi s1, s1, -4 -80000f18: e3 16 34 ff bne s0, s3, -20 -80000f1c: 83 20 c1 02 lw ra, 44(sp) -80000f20: 03 24 81 02 lw s0, 40(sp) -80000f24: 83 24 41 02 lw s1, 36(sp) -80000f28: 03 29 01 02 lw s2, 32(sp) -80000f2c: 83 29 c1 01 lw s3, 28(sp) -80000f30: 03 2a 81 01 lw s4, 24(sp) -80000f34: 83 2a 41 01 lw s5, 20(sp) -80000f38: 03 2b 01 01 lw s6, 16(sp) -80000f3c: 83 2b c1 00 lw s7, 12(sp) -80000f40: 03 2c 81 00 lw s8, 8(sp) -80000f44: 13 01 01 03 addi sp, sp, 48 -80000f48: 67 80 00 00 ret -80000f4c: 83 27 49 00 lw a5, 4(s2) -80000f50: 83 a6 44 00 lw a3, 4(s1) -80000f54: 93 87 f7 ff addi a5, a5, -1 -80000f58: 63 8e 87 04 beq a5, s0, 92 -80000f5c: 23 a2 04 00 sw zero, 4(s1) -80000f60: e3 88 06 fa beqz a3, -80 -80000f64: 83 27 89 18 lw a5, 392(s2) -80000f68: 33 97 8a 00 sll a4, s5, s0 -80000f6c: 03 2c 49 00 lw s8, 4(s2) -80000f70: b3 77 f7 00 and a5, a4, a5 -80000f74: 63 92 07 02 bnez a5, 36 -80000f78: e7 80 06 00 jalr a3 -80000f7c: 03 27 49 00 lw a4, 4(s2) -80000f80: 83 27 8a 14 lw a5, 328(s4) -80000f84: 63 14 87 01 bne a4, s8, 8 -80000f88: e3 04 f9 f8 beq s2, a5, -120 -80000f8c: e3 88 07 f8 beqz a5, -112 -80000f90: 13 89 07 00 mv s2, a5 -80000f94: 6f f0 df f5 j -164 -80000f98: 83 27 c9 18 lw a5, 396(s2) -80000f9c: 83 a5 44 08 lw a1, 132(s1) -80000fa0: 33 77 f7 00 and a4, a4, a5 -80000fa4: 63 1c 07 00 bnez a4, 24 -80000fa8: 13 05 0b 00 mv a0, s6 -80000fac: e7 80 06 00 jalr a3 -80000fb0: 6f f0 df fc j -52 -80000fb4: 23 22 89 00 sw s0, 4(s2) -80000fb8: 6f f0 9f fa j -88 -80000fbc: 13 85 05 00 mv a0, a1 -80000fc0: e7 80 06 00 jalr a3 -80000fc4: 6f f0 9f fb j -72 +80000d64 exit: +80000d64: 13 01 01 ff addi sp, sp, -16 +80000d68: 93 05 00 00 mv a1, zero +80000d6c: 23 24 81 00 sw s0, 8(sp) +80000d70: 23 26 11 00 sw ra, 12(sp) +80000d74: 13 04 05 00 mv s0, a0 +80000d78: ef 00 80 19 jal 408 +80000d7c: b7 27 00 80 lui a5, 524290 +80000d80: 03 a5 07 46 lw a0, 1120(a5) +80000d84: 83 27 c5 03 lw a5, 60(a0) +80000d88: 63 84 07 00 beqz a5, 8 +80000d8c: e7 80 07 00 jalr a5 +80000d90: 13 05 04 00 mv a0, s0 +80000d94: ef f0 8f f1 jal -2280 + +80000d98 memset: +80000d98: 13 03 f0 00 addi t1, zero, 15 +80000d9c: 13 07 05 00 mv a4, a0 +80000da0: 63 7e c3 02 bgeu t1, a2, 60 +80000da4: 93 77 f7 00 andi a5, a4, 15 +80000da8: 63 90 07 0a bnez a5, 160 +80000dac: 63 92 05 08 bnez a1, 132 +80000db0: 93 76 06 ff andi a3, a2, -16 +80000db4: 13 76 f6 00 andi a2, a2, 15 +80000db8: b3 86 e6 00 add a3, a3, a4 +80000dbc: 23 20 b7 00 sw a1, 0(a4) +80000dc0: 23 22 b7 00 sw a1, 4(a4) +80000dc4: 23 24 b7 00 sw a1, 8(a4) +80000dc8: 23 26 b7 00 sw a1, 12(a4) +80000dcc: 13 07 07 01 addi a4, a4, 16 +80000dd0: e3 66 d7 fe bltu a4, a3, -20 +80000dd4: 63 14 06 00 bnez a2, 8 +80000dd8: 67 80 00 00 ret +80000ddc: b3 06 c3 40 sub a3, t1, a2 +80000de0: 93 96 26 00 slli a3, a3, 2 +80000de4: 97 02 00 00 auipc t0, 0 +80000de8: b3 86 56 00 add a3, a3, t0 +80000dec: 67 80 c6 00 jr 12(a3) +80000df0: 23 07 b7 00 sb a1, 14(a4) +80000df4: a3 06 b7 00 sb a1, 13(a4) +80000df8: 23 06 b7 00 sb a1, 12(a4) +80000dfc: a3 05 b7 00 sb a1, 11(a4) +80000e00: 23 05 b7 00 sb a1, 10(a4) +80000e04: a3 04 b7 00 sb a1, 9(a4) +80000e08: 23 04 b7 00 sb a1, 8(a4) +80000e0c: a3 03 b7 00 sb a1, 7(a4) +80000e10: 23 03 b7 00 sb a1, 6(a4) +80000e14: a3 02 b7 00 sb a1, 5(a4) +80000e18: 23 02 b7 00 sb a1, 4(a4) +80000e1c: a3 01 b7 00 sb a1, 3(a4) +80000e20: 23 01 b7 00 sb a1, 2(a4) +80000e24: a3 00 b7 00 sb a1, 1(a4) +80000e28: 23 00 b7 00 sb a1, 0(a4) +80000e2c: 67 80 00 00 ret +80000e30: 93 f5 f5 0f andi a1, a1, 255 +80000e34: 93 96 85 00 slli a3, a1, 8 +80000e38: b3 e5 d5 00 or a1, a1, a3 +80000e3c: 93 96 05 01 slli a3, a1, 16 +80000e40: b3 e5 d5 00 or a1, a1, a3 +80000e44: 6f f0 df f6 j -148 +80000e48: 93 96 27 00 slli a3, a5, 2 +80000e4c: 97 02 00 00 auipc t0, 0 +80000e50: b3 86 56 00 add a3, a3, t0 +80000e54: 93 82 00 00 mv t0, ra +80000e58: e7 80 06 fa jalr -96(a3) +80000e5c: 93 80 02 00 mv ra, t0 +80000e60: 93 87 07 ff addi a5, a5, -16 +80000e64: 33 07 f7 40 sub a4, a4, a5 +80000e68: 33 06 f6 00 add a2, a2, a5 +80000e6c: e3 78 c3 f6 bgeu t1, a2, -144 +80000e70: 6f f0 df f3 j -196 + +80000e74 __register_exitproc: +80000e74: b7 27 00 80 lui a5, 524290 +80000e78: 03 a7 07 46 lw a4, 1120(a5) +80000e7c: 83 27 87 14 lw a5, 328(a4) +80000e80: 63 8c 07 04 beqz a5, 88 +80000e84: 03 a7 47 00 lw a4, 4(a5) +80000e88: 13 08 f0 01 addi a6, zero, 31 +80000e8c: 63 4e e8 06 blt a6, a4, 124 +80000e90: 13 18 27 00 slli a6, a4, 2 +80000e94: 63 06 05 02 beqz a0, 44 +80000e98: 33 83 07 01 add t1, a5, a6 +80000e9c: 23 24 c3 08 sw a2, 136(t1) +80000ea0: 83 a8 87 18 lw a7, 392(a5) +80000ea4: 13 06 10 00 addi a2, zero, 1 +80000ea8: 33 16 e6 00 sll a2, a2, a4 +80000eac: b3 e8 c8 00 or a7, a7, a2 +80000eb0: 23 a4 17 19 sw a7, 392(a5) +80000eb4: 23 24 d3 10 sw a3, 264(t1) +80000eb8: 93 06 20 00 addi a3, zero, 2 +80000ebc: 63 04 d5 02 beq a0, a3, 40 +80000ec0: 13 07 17 00 addi a4, a4, 1 +80000ec4: 23 a2 e7 00 sw a4, 4(a5) +80000ec8: b3 87 07 01 add a5, a5, a6 +80000ecc: 23 a4 b7 00 sw a1, 8(a5) +80000ed0: 13 05 00 00 mv a0, zero +80000ed4: 67 80 00 00 ret +80000ed8: 93 07 c7 14 addi a5, a4, 332 +80000edc: 23 24 f7 14 sw a5, 328(a4) +80000ee0: 6f f0 5f fa j -92 +80000ee4: 83 a6 c7 18 lw a3, 396(a5) +80000ee8: 13 07 17 00 addi a4, a4, 1 +80000eec: 23 a2 e7 00 sw a4, 4(a5) +80000ef0: 33 e6 c6 00 or a2, a3, a2 +80000ef4: 23 a6 c7 18 sw a2, 396(a5) +80000ef8: b3 87 07 01 add a5, a5, a6 +80000efc: 23 a4 b7 00 sw a1, 8(a5) +80000f00: 13 05 00 00 mv a0, zero +80000f04: 67 80 00 00 ret +80000f08: 13 05 f0 ff addi a0, zero, -1 +80000f0c: 67 80 00 00 ret + +80000f10 __call_exitprocs: +80000f10: 13 01 01 fd addi sp, sp, -48 +80000f14: b7 27 00 80 lui a5, 524290 +80000f18: 23 2c 41 01 sw s4, 24(sp) +80000f1c: 03 aa 07 46 lw s4, 1120(a5) +80000f20: 23 20 21 03 sw s2, 32(sp) +80000f24: 23 26 11 02 sw ra, 44(sp) +80000f28: 03 29 8a 14 lw s2, 328(s4) +80000f2c: 23 24 81 02 sw s0, 40(sp) +80000f30: 23 22 91 02 sw s1, 36(sp) +80000f34: 23 2e 31 01 sw s3, 28(sp) +80000f38: 23 2a 51 01 sw s5, 20(sp) +80000f3c: 23 28 61 01 sw s6, 16(sp) +80000f40: 23 26 71 01 sw s7, 12(sp) +80000f44: 23 24 81 01 sw s8, 8(sp) +80000f48: 63 00 09 04 beqz s2, 64 +80000f4c: 13 0b 05 00 mv s6, a0 +80000f50: 93 8b 05 00 mv s7, a1 +80000f54: 93 0a 10 00 addi s5, zero, 1 +80000f58: 93 09 f0 ff addi s3, zero, -1 +80000f5c: 83 24 49 00 lw s1, 4(s2) +80000f60: 13 84 f4 ff addi s0, s1, -1 +80000f64: 63 42 04 02 bltz s0, 36 +80000f68: 93 94 24 00 slli s1, s1, 2 +80000f6c: b3 04 99 00 add s1, s2, s1 +80000f70: 63 84 0b 04 beqz s7, 72 +80000f74: 83 a7 44 10 lw a5, 260(s1) +80000f78: 63 80 77 05 beq a5, s7, 64 +80000f7c: 13 04 f4 ff addi s0, s0, -1 +80000f80: 93 84 c4 ff addi s1, s1, -4 +80000f84: e3 16 34 ff bne s0, s3, -20 +80000f88: 83 20 c1 02 lw ra, 44(sp) +80000f8c: 03 24 81 02 lw s0, 40(sp) +80000f90: 83 24 41 02 lw s1, 36(sp) +80000f94: 03 29 01 02 lw s2, 32(sp) +80000f98: 83 29 c1 01 lw s3, 28(sp) +80000f9c: 03 2a 81 01 lw s4, 24(sp) +80000fa0: 83 2a 41 01 lw s5, 20(sp) +80000fa4: 03 2b 01 01 lw s6, 16(sp) +80000fa8: 83 2b c1 00 lw s7, 12(sp) +80000fac: 03 2c 81 00 lw s8, 8(sp) +80000fb0: 13 01 01 03 addi sp, sp, 48 +80000fb4: 67 80 00 00 ret +80000fb8: 83 27 49 00 lw a5, 4(s2) +80000fbc: 83 a6 44 00 lw a3, 4(s1) +80000fc0: 93 87 f7 ff addi a5, a5, -1 +80000fc4: 63 8e 87 04 beq a5, s0, 92 +80000fc8: 23 a2 04 00 sw zero, 4(s1) +80000fcc: e3 88 06 fa beqz a3, -80 +80000fd0: 83 27 89 18 lw a5, 392(s2) +80000fd4: 33 97 8a 00 sll a4, s5, s0 +80000fd8: 03 2c 49 00 lw s8, 4(s2) +80000fdc: b3 77 f7 00 and a5, a4, a5 +80000fe0: 63 92 07 02 bnez a5, 36 +80000fe4: e7 80 06 00 jalr a3 +80000fe8: 03 27 49 00 lw a4, 4(s2) +80000fec: 83 27 8a 14 lw a5, 328(s4) +80000ff0: 63 14 87 01 bne a4, s8, 8 +80000ff4: e3 04 f9 f8 beq s2, a5, -120 +80000ff8: e3 88 07 f8 beqz a5, -112 +80000ffc: 13 89 07 00 mv s2, a5 +80001000: 6f f0 df f5 j -164 +80001004: 83 27 c9 18 lw a5, 396(s2) +80001008: 83 a5 44 08 lw a1, 132(s1) +8000100c: 33 77 f7 00 and a4, a4, a5 +80001010: 63 1c 07 00 bnez a4, 24 +80001014: 13 05 0b 00 mv a0, s6 +80001018: e7 80 06 00 jalr a3 +8000101c: 6f f0 df fc j -52 +80001020: 23 22 89 00 sw s0, 4(s2) +80001024: 6f f0 9f fa j -88 +80001028: 13 85 05 00 mv a0, a1 +8000102c: e7 80 06 00 jalr a3 +80001030: 6f f0 9f fb j -72 Disassembly of section .init_array: -80001000 __preinit_array_start: -80001000: 50 00 -80001002: 00 80 +80002034 __preinit_array_start: +80002034: 50 00 +80002036: 00 80 Disassembly of section .data: -80001008 impure_data: -80001008: 00 00 -8000100a: 00 00 -8000100c: f4 12 -8000100e: 00 80 -80001010: 5c 13 -80001012: 00 80 -80001014: c4 13 -80001016: 00 80 +80002038 impure_data: +80002038: 00 00 +8000203a: 00 00 +8000203c: 24 23 +8000203e: 00 80 +80002040: 8c 23 +80002042: 00 80 +80002044: f4 23 +80002046: 00 80 ... -800010b0: 01 00 -800010b2: 00 00 -800010b4: 00 00 -800010b6: 00 00 -800010b8: 0e 33 -800010ba: cd ab -800010bc: 34 12 -800010be: 6d e6 -800010c0: ec de -800010c2: 05 00 -800010c4: 0b 00 00 00 +800020e0: 01 00 +800020e2: 00 00 +800020e4: 00 00 +800020e6: 00 00 +800020e8: 0e 33 +800020ea: cd ab +800020ec: 34 12 +800020ee: 6d e6 +800020f0: ec de +800020f2: 05 00 +800020f4: 0b 00 00 00 ... Disassembly of section .sdata: -80001430 _global_impure_ptr: -80001430: 08 10 -80001432: 00 80 +80002460 _global_impure_ptr: +80002460: 38 20 +80002462: 00 80 -80001434 _impure_ptr: -80001434: 08 10 -80001436: 00 80 +80002464 _impure_ptr: +80002464: 38 20 +80002466: 00 80 Disassembly of section .sbss: -80001438 __fdlib_version: +80002468 __fdlib_version: ... Disassembly of section .bss: -8000143c g_wspawn_args: +8000246c g_wspawn_args: ... Disassembly of section .comment: @@ -1141,25 +1174,25 @@ Disassembly of section .comment: 36: 6a 65 38: 63 74 2e 67 bgeu t3, s2, 1640 3c: 69 74 - 3e: 20 65 - 40: 66 33 - 42: 32 63 - 44: 36 31 - 46: 31 61 - 48: 61 32 - 4a: 31 34 - 4c: 64 65 - 4e: 61 38 - 50: 35 35 - 52: 33 36 34 65 - 56: 66 64 - 58: 37 62 61 34 lui tp, 214550 - 5c: 35 31 - 5e: 65 63 - 60: 35 65 - 62: 63 33 66 37 - 66: 34 29 - 68: 00 47 + 3e: 20 32 + 40: 61 32 + 42: 33 65 66 61 + 46: 63 33 35 32 + 4a: 66 39 + 4c: 31 39 + 4e: 65 62 + 50: 64 31 + 52: 65 63 + 54: 31 62 + 56: 65 34 + 58: 35 31 + 5a: 34 36 + 5c: 64 36 + 5e: 61 39 + 60: 66 61 + 62: 32 31 + 64: 62 35 + 66: 33 29 00 47 6a: 43 43 3a 20 fmadd.s ft6, fs4, ft3, ft4, rmm 6e: 28 47 70: 4e 55 @@ -1206,35 +1239,35 @@ Disassembly of section .symtab: 2c: 03 00 02 00 lb zero, 0(tp) 30: 00 00 32: 00 00 - 34: 00 10 + 34: 34 20 36: 00 80 38: 00 00 3a: 00 00 3c: 03 00 03 00 lb zero, 0(t1) 40: 00 00 42: 00 00 - 44: 08 10 + 44: 38 20 46: 00 80 48: 00 00 4a: 00 00 4c: 03 00 04 00 lb zero, 0(s0) 50: 00 00 52: 00 00 - 54: 30 14 + 54: 60 24 56: 00 80 58: 00 00 5a: 00 00 5c: 03 00 05 00 lb zero, 0(a0) 60: 00 00 62: 00 00 - 64: 38 14 + 64: 68 24 66: 00 80 68: 00 00 6a: 00 00 6c: 03 00 06 00 lb zero, 0(a2) 70: 00 00 72: 00 00 - 74: 3c 14 + 74: 6c 24 76: 00 80 78: 00 00 7a: 00 00 @@ -1250,403 +1283,412 @@ Disassembly of section .symtab: ae: f1 ff b0: 0e 00 b2: 00 00 - b4: d4 04 + b4: b8 04 b6: 00 80 b8: 00 00 ba: 00 00 bc: 00 00 be: 02 00 - c0: 15 00 - ... + c0: 1e 00 + c2: 00 00 + c4: f4 04 + c6: 00 80 + c8: 00 00 ca: 00 00 - cc: 04 00 - ce: f1 ff + cc: 00 00 + ce: 02 00 d0: 25 00 - d2: 00 00 - d4: 50 00 - d6: 00 80 - d8: 18 00 - da: 00 00 - dc: 02 00 - de: 02 00 - e0: 33 00 00 00 add zero, zero, zero ... - ec: 04 00 - ee: f1 ff - f0: 57 00 00 00 + da: 00 00 + dc: 04 00 + de: f1 ff + e0: 35 00 + e2: 00 00 + e4: 50 00 + e6: 00 80 + e8: 18 00 + ea: 00 00 + ec: 02 00 + ee: 02 00 + f0: 43 00 00 00 fmadd.s ft0, ft0, ft0, ft0, rne ... fc: 04 00 fe: f1 ff - 100: 63 00 00 00 beqz zero, 0 - 104: 98 00 - 106: 00 80 - 108: 24 00 - 10a: 00 00 - 10c: 02 00 - 10e: 02 00 - 110: 70 00 + 100: 67 00 00 00 jr zero ... + 10c: 04 00 + 10e: f1 ff + 110: 73 00 00 00 ecall + 114: 98 00 + 116: 00 80 + 118: 24 00 11a: 00 00 - 11c: 04 00 - 11e: f1 ff - 120: 7b 00 00 00 - 124: d8 04 - 126: 00 80 - 128: 48 01 + 11c: 02 00 + 11e: 02 00 + 120: 80 00 + ... 12a: 00 00 - 12c: 02 00 - 12e: 02 00 - 130: 91 00 + 12c: 04 00 + 12e: f1 ff + 130: 8e 00 ... 13a: 00 00 13c: 04 00 13e: f1 ff - 140: 9b 00 00 00 - ... - 14c: 04 00 - 14e: f1 ff - 150: a5 00 - ... + 140: 99 00 + 142: 00 00 + 144: f0 05 + 146: 00 80 + 148: 3c 01 + 14a: 00 00 + 14c: 02 00 + 14e: 02 00 + 150: af 00 00 00 + 154: 2c 07 + 156: 00 80 + 158: a4 00 15a: 00 00 - 15c: 04 00 - 15e: f1 ff - 160: c7 00 00 00 fmsub.s ft1, ft0, ft0, ft0, rne - ... - 16c: 04 00 - 16e: f1 ff - 170: af 00 00 00 + 15c: 02 00 + 15e: 02 00 + 160: c5 00 + 162: 00 00 + 164: d0 07 + 166: 00 80 + 168: 2c 00 + 16a: 00 00 + 16c: 02 00 + 16e: 02 00 + 170: d9 00 ... + 17a: 00 00 17c: 04 00 17e: f1 ff - 180: c9 00 + 180: e3 00 00 00 beqz zero, 2048 ... - 18a: 00 00 18c: 04 00 18e: f1 ff - 190: b7 00 00 00 lui ra, 0 + 190: ed 00 ... + 19a: 00 00 19c: 04 00 19e: f1 ff - 1a0: be 00 + 1a0: 01 01 ... 1aa: 00 00 1ac: 04 00 1ae: f1 ff - 1b0: c5 00 + 1b0: f7 00 00 00 ... - 1ba: 00 00 1bc: 04 00 1be: f1 ff - 1c0: d0 00 + 1c0: 03 01 00 00 lb sp, 0(zero) ... - 1ca: 00 00 1cc: 04 00 1ce: f1 ff - 1d0: d9 00 - 1d2: 00 00 - 1d4: 08 10 - 1d6: 00 80 - 1d8: 28 04 - 1da: 00 00 - 1dc: 01 00 - 1de: 04 00 + 1d0: ff 00 00 00 ... + 1dc: 04 00 + 1de: f1 ff + 1e0: 0a 01 + ... + 1ea: 00 00 1ec: 04 00 1ee: f1 ff - 1f0: e5 00 - 1f2: 00 00 - 1f4: 04 10 + 1f0: 13 01 00 00 mv sp, zero + 1f4: 38 20 1f6: 00 80 - 1f8: 00 00 + 1f8: 28 04 1fa: 00 00 - 1fc: 00 00 - 1fe: 03 00 f6 00 lb zero, 15(a2) - 202: 00 00 - 204: 04 10 - 206: 00 80 - 208: 00 00 - 20a: 00 00 - 20c: 00 00 - 20e: 03 00 09 01 lb zero, 16(s2) - 212: 00 00 - 214: 04 10 + 1fc: 01 00 + 1fe: 04 00 + ... + 20c: 04 00 + 20e: f1 ff + 210: 1f 01 00 00 + 214: 38 20 216: 00 80 218: 00 00 21a: 00 00 21c: 00 00 - 21e: 03 00 1a 01 lb zero, 17(s4) + 21e: 04 00 + 220: 30 01 222: 00 00 - 224: 00 10 + 224: 38 20 226: 00 80 228: 00 00 22a: 00 00 22c: 00 00 - 22e: 03 00 2e 01 lb zero, 18(t3) - 232: 00 00 - 234: 00 10 + 22e: 04 00 + 230: 43 01 00 00 fmadd.s ft2, ft0, ft0, ft0, rne + 234: 38 20 236: 00 80 238: 00 00 23a: 00 00 23c: 00 00 - 23e: 03 00 41 01 lb zero, 20(sp) + 23e: 03 00 54 01 lb zero, 21(s0) 242: 00 00 - 244: 00 10 + 244: 34 20 246: 00 80 248: 00 00 24a: 00 00 24c: 00 00 - 24e: 03 00 57 01 lb zero, 21(a4) - ... + 24e: 03 00 68 01 lb zero, 22(a6) + 252: 00 00 + 254: 34 20 + 256: 00 80 + 258: 00 00 25a: 00 00 - 25c: 10 00 - 25e: f1 ff - 260: 65 01 + 25c: 00 00 + 25e: 03 00 7b 01 lb zero, 23(s6) 262: 00 00 - 264: f4 0b + 264: 34 20 266: 00 80 - 268: 0c 00 + 268: 00 00 26a: 00 00 - 26c: 12 00 - 26e: 02 00 - 270: 6d 01 - 272: 00 00 - 274: 00 04 - 276: 00 00 - 278: 00 00 + 26c: 00 00 + 26e: 03 00 91 01 lb zero, 25(sp) + ... 27a: 00 00 27c: 10 00 27e: f1 ff - 280: 7a 01 - 282: 00 00 - 284: 3c 14 + 280: 9f 01 00 00 + 284: 58 0d 286: 00 80 - 288: 80 00 + 288: 0c 00 28a: 00 00 - 28c: 11 00 - 28e: 07 00 88 01 - 292: 00 00 - 294: 30 14 - 296: 00 80 + 28c: 12 00 + 28e: 02 00 + 290: a7 01 00 00 + 294: 00 04 + 296: 00 00 298: 00 00 29a: 00 00 29c: 10 00 - 29e: 05 00 - 2a0: 54 02 + 29e: f1 ff + 2a0: b4 01 2a2: 00 00 - 2a4: 60 0a + 2a4: 6c 24 2a6: 00 80 - 2a8: 74 00 + 2a8: 80 00 2aa: 00 00 - 2ac: 12 00 - 2ae: 02 00 - 2b0: 98 01 + 2ac: 11 00 + 2ae: 07 00 c2 01 2b2: 00 00 - 2b4: 08 18 + 2b4: 60 24 2b6: 00 80 2b8: 00 00 2ba: 00 00 2bc: 10 00 - 2be: f1 ff - 2c0: a9 01 + 2be: 05 00 + 2c0: 82 02 2c2: 00 00 - 2c4: 38 14 + 2c4: c4 0b 2c6: 00 80 - 2c8: 04 00 + 2c8: 74 00 2ca: 00 00 - 2cc: 11 00 - 2ce: 06 00 - 2d0: b9 01 + 2cc: 12 00 + 2ce: 02 00 + 2d0: d2 01 2d2: 00 00 - 2d4: 30 14 + 2d4: 38 28 2d6: 00 80 - 2d8: 04 00 + 2d8: 00 00 2da: 00 00 - 2dc: 11 00 - 2de: 05 00 - 2e0: cc 01 - 2e2: 00 00 - 2e4: 90 0c + 2dc: 10 00 + 2de: f1 ff + 2e0: e3 01 00 00 beqz zero, 2050 + 2e4: 68 24 2e6: 00 80 - 2e8: 9c 00 + 2e8: 04 00 2ea: 00 00 - 2ec: 12 00 - 2ee: 02 00 - 2f0: de 01 - 2f2: 00 00 - 2f4: 34 0c + 2ec: 11 00 + 2ee: 06 00 + 2f0: f3 01 00 00 + 2f4: 60 24 2f6: 00 80 - 2f8: 5c 00 + 2f8: 04 00 2fa: 00 00 - 2fc: 12 00 - 2fe: 02 00 - 300: f0 01 + 2fc: 11 00 + 2fe: 05 00 + 300: 06 02 302: 00 00 - 304: 00 00 - 306: 00 ff - 308: 00 00 + 304: f8 04 + 306: 00 80 + 308: 9c 00 30a: 00 00 - 30c: 10 00 - 30e: f1 ff - 310: fc 01 + 30c: 12 00 + 30e: 02 00 + 310: 18 02 312: 00 00 - 314: 9c 04 + 314: 94 05 316: 00 80 - 318: 00 00 + 318: 5c 00 31a: 00 00 31c: 12 00 31e: 02 00 - 320: 06 02 + 320: 2a 02 322: 00 00 - 324: a4 0e + 324: c4 04 326: 00 80 - 328: 24 01 + 328: 00 00 32a: 00 00 32c: 12 00 32e: 02 00 - 330: 3c 02 + 330: 34 02 332: 00 00 - 334: 00 00 + 334: 10 0f 336: 00 80 - 338: 50 00 + 338: 24 01 33a: 00 00 33c: 12 00 - 33e: 01 00 - 340: 17 02 00 00 auipc tp, 0 - 344: 08 0e + 33e: 02 00 + 340: 6a 02 + 342: 00 00 + 344: 00 00 346: 00 80 - 348: 9c 00 + 348: 50 00 34a: 00 00 34c: 12 00 - 34e: 02 00 - 350: 2b 02 00 00 - 354: bc 14 + 34e: 01 00 + 350: 45 02 + 352: 00 00 + 354: 74 0e 356: 00 80 - 358: 00 00 + 358: 9c 00 35a: 00 00 - 35c: 10 00 - 35e: 07 00 37 02 + 35c: 12 00 + 35e: 02 00 + 360: 59 02 362: 00 00 - 364: 38 14 + 364: ec 24 366: 00 80 368: 00 00 36a: 00 00 36c: 10 00 - 36e: 06 00 - 370: 43 02 00 00 fmadd.s ft4, ft0, ft0, ft0, rne - 374: 2c 0d + 36e: 07 00 65 02 + 372: 00 00 + 374: 68 24 376: 00 80 - 378: dc 00 + 378: 00 00 37a: 00 00 - 37c: 12 00 - 37e: 02 00 - 380: 4a 02 + 37c: 10 00 + 37e: 06 00 + 380: 71 02 382: 00 00 - 384: d4 0a + 384: 98 0d 386: 00 80 - 388: 0c 01 + 388: dc 00 38a: 00 00 38c: 12 00 38e: 02 00 - 390: 5a 02 + 390: 78 02 392: 00 00 - 394: 68 00 + 394: 38 0c 396: 00 80 - 398: 30 00 + 398: 0c 01 39a: 00 00 39c: 12 00 39e: 02 00 - 3a0: 5f 02 00 00 - 3a4: 4c 03 + 3a0: 88 02 + 3a2: 00 00 + 3a4: 68 00 3a6: 00 80 - 3a8: 44 01 + 3a8: 30 00 3aa: 00 00 3ac: 12 00 3ae: 02 00 - 3b0: 8b 02 00 00 - 3b4: e0 0b + 3b0: 8d 02 + 3b2: 00 00 + 3b4: 68 03 3b6: 00 80 - 3b8: 14 00 + 3b8: 44 01 3ba: 00 00 3bc: 12 00 3be: 02 00 - 3c0: c0 01 + 3c0: b9 02 3c2: 00 00 - 3c4: 34 14 + 3c4: 44 0d 3c6: 00 80 - 3c8: 04 00 + 3c8: 14 00 3ca: 00 00 - 3cc: 11 00 - 3ce: 05 00 - 3d0: 92 02 + 3cc: 12 00 + 3ce: 02 00 + 3d0: fa 01 3d2: 00 00 - 3d4: 00 02 + 3d4: 64 24 3d6: 00 80 - 3d8: 4c 01 + 3d8: 04 00 3da: 00 00 - 3dc: 12 00 - 3de: 02 00 - 3e0: b9 02 + 3dc: 11 00 + 3de: 05 00 + 3e0: c0 02 3e2: 00 00 - 3e4: 08 10 + 3e4: 00 02 3e6: 00 80 - 3e8: 00 00 + 3e8: 68 01 3ea: 00 00 - 3ec: 10 00 - 3ee: 04 00 - 3f0: c8 02 - 3f2: 00 00 - 3f4: 38 14 + 3ec: 12 00 + 3ee: 02 00 + 3f0: e7 02 00 00 jalr t0, zero + 3f4: 38 20 3f6: 00 80 3f8: 00 00 3fa: 00 00 3fc: 10 00 - 3fe: 05 00 - 400: f1 00 + 3fe: 04 00 + 400: f6 02 402: 00 00 - 404: bc 14 + 404: 68 24 406: 00 80 408: 00 00 40a: 00 00 40c: 10 00 - 40e: 07 00 cf 02 - 412: 00 00 - 414: bc 00 + 40e: 05 00 + 410: 2b 01 00 00 + 414: ec 24 416: 00 80 - 418: 44 01 + 418: 00 00 41a: 00 00 - 41c: 12 00 - 41e: 02 00 - 420: fa 02 + 41c: 10 00 + 41e: 07 00 fd 02 422: 00 00 - 424: 00 0c + 424: bc 00 426: 00 80 - 428: 34 00 + 428: 44 01 42a: 00 00 42c: 12 00 42e: 02 00 - 430: ec 02 + 430: 28 03 432: 00 00 - 434: 4c 08 + 434: 64 0d 436: 00 80 - 438: 14 02 + 438: 34 00 43a: 00 00 43c: 12 00 43e: 02 00 - 440: f9 02 + 440: 1a 03 442: 00 00 - 444: 90 04 + 444: b0 09 446: 00 80 - 448: 00 00 + 448: 14 02 44a: 00 00 44c: 12 00 44e: 02 00 - 450: ff 02 00 00 - 454: 20 06 + 450: 27 03 00 00 + 454: ac 04 456: 00 80 - 458: 2c 02 + 458: 00 00 45a: 00 00 45c: 12 00 45e: 02 00 + 460: 2d 03 + 462: 00 00 + 464: fc 07 + 466: 00 80 + 468: b4 01 + 46a: 00 00 + 46c: 12 00 + 46e: 02 00 Disassembly of section .strtab: @@ -1656,303 +1698,323 @@ Disassembly of section .strtab: 4: 73 74 61 72 csrrci s0, 1830, 2 8: 74 2e a: 53 2e 6f 00 fadd.s ft8, ft10, ft6, rdn - e: 52 45 - 10: 54 55 - 12: 52 4e - 14: 00 5f - 16: 5f 63 61 6c - 1a: 6c 5f - 1c: 61 74 - 1e: 65 78 - 20: 69 74 - 22: 2e 63 - 24: 00 72 - 26: 65 67 - 28: 69 73 - 2a: 74 65 - 2c: 72 5f - 2e: 66 69 - 30: 6e 69 - 32: 00 70 - 34: 6f 63 6c 5f jal t1, 812534 - 38: 76 6f - 3a: 72 74 - 3c: 65 78 - 3e: 5f 6b 65 72 - 42: 6e 65 - 44: 6c 2d - 46: 37 33 2d 39 lui t1, 234195 - 4a: 38 2d - 4c: 65 33 - 4e: 2d 34 - 50: 64 2d - 52: 30 30 - 54: 2e 63 - 56: 00 70 - 58: 61 72 - 5a: 61 6c - 5c: 6c 65 - 5e: 6c 5f - 60: 62 63 - 62: 00 5f - 64: 5a 38 - 66: 5f 63 6c 5f - 6a: 73 71 72 74 csrrci sp, 1863, 4 - 6e: 66 00 - 70: 76 78 - 72: 5f 73 70 61 - 76: 77 6e 2e 63 - 7a: 00 73 - 7c: 70 61 - 7e: 77 6e 5f 6b - 82: 65 72 - 84: 6e 65 - 86: 6c 5f - 88: 63 61 6c 6c bltu s8, t1, 1730 - 8c: 62 61 - 8e: 63 6b 00 76 bltu zero, zero, 1910 - 92: 78 5f - 94: 70 65 - 96: 72 66 - 98: 2e 63 - 9a: 00 77 - 9c: 66 5f - 9e: 73 71 72 74 csrrci sp, 1863, 4 - a2: 2e 63 - a4: 00 65 - a6: 66 5f - a8: 73 71 72 74 csrrci sp, 1863, 4 - ac: 2e 63 - ae: 00 65 - b0: 72 72 - b2: 6e 6f - b4: 2e 63 - b6: 00 66 - b8: 69 6e - ba: 69 2e - bc: 63 00 69 6e beq s2, t1, 1760 - c0: 69 74 - c2: 2e 63 - c4: 00 5f - c6: 5f 61 74 65 - ca: 78 69 - cc: 74 2e - ce: 63 00 69 6d beq s2, s6, 1728 - d2: 70 75 - d4: 72 65 - d6: 2e 63 - d8: 00 69 - da: 6d 70 - dc: 75 72 - de: 65 5f - e0: 64 61 - e2: 74 61 - e4: 00 5f - e6: 5f 66 69 6e - ea: 69 5f - ec: 61 72 - ee: 72 61 - f0: 79 5f - f2: 65 6e - f4: 64 00 - f6: 5f 5f 66 69 - fa: 6e 69 - fc: 5f 61 72 72 - 100: 61 79 - 102: 5f 73 74 61 - 106: 72 74 - 108: 00 5f - 10a: 5f 69 6e 69 - 10e: 74 5f - 110: 61 72 - 112: 72 61 - 114: 79 5f - 116: 65 6e - 118: 64 00 - 11a: 5f 5f 70 72 - 11e: 65 69 - 120: 6e 69 - 122: 74 5f - 124: 61 72 - 126: 72 61 - 128: 79 5f - 12a: 65 6e - 12c: 64 00 - 12e: 5f 5f 69 6e - 132: 69 74 - 134: 5f 61 72 72 - 138: 61 79 - 13a: 5f 73 74 61 - 13e: 72 74 - 140: 00 5f - 142: 5f 70 72 65 - 146: 69 6e - 148: 69 74 - 14a: 5f 61 72 72 - 14e: 61 79 - 150: 5f 73 74 61 - 154: 72 74 - 156: 00 5f - 158: 5f 73 74 61 - 15c: 63 6b 5f 75 bltu t5, s5, 1878 - 160: 73 61 67 65 csrrsi sp, 1622, 14 - 164: 00 5f - 166: 5f 65 72 72 - 16a: 6e 6f - 16c: 00 5f - 16e: 5f 73 74 61 - 172: 63 6b 5f 73 bltu t5, s5, 1846 - 176: 69 7a - 178: 65 00 - 17a: 67 5f 77 73 - 17e: 70 61 - 180: 77 6e 5f 61 - 184: 72 67 - 186: 73 00 5f 5f - 18a: 53 44 41 54 - 18e: 41 5f - 190: 42 45 - 192: 47 49 4e 5f - 196: 5f 00 5f 5f - 19a: 67 6c 6f 62 - 19e: 61 6c - 1a0: 5f 70 6f 69 - 1a4: 6e 74 - 1a6: 65 72 - 1a8: 00 5f - 1aa: 5f 66 64 6c - 1ae: 69 62 - 1b0: 5f 76 65 72 - 1b4: 73 69 6f 6e csrrsi s2, 1766, 30 - 1b8: 00 5f - 1ba: 67 6c 6f 62 - 1be: 61 6c - 1c0: 5f 69 6d 70 - 1c4: 75 72 - 1c6: 65 5f - 1c8: 70 74 - 1ca: 72 00 - 1cc: 5f 5f 6c 69 - 1d0: 62 63 - 1d2: 5f 69 6e 69 - 1d6: 74 5f - 1d8: 61 72 - 1da: 72 61 - 1dc: 79 00 - 1de: 5f 5f 6c 69 - 1e2: 62 63 - 1e4: 5f 66 69 6e - 1e8: 69 5f - 1ea: 61 72 - 1ec: 72 61 - 1ee: 79 00 - 1f0: 5f 5f 73 74 - 1f4: 61 63 - 1f6: 6b 5f 74 6f - 1fa: 70 00 - 1fc: 76 78 - 1fe: 5f 73 65 74 - 202: 5f 73 70 00 - 206: 5f 5f 63 61 - 20a: 6c 6c - 20c: 5f 65 78 69 - 210: 74 70 - 212: 72 6f - 214: 63 73 00 5f bgeu zero, a6, 1510 - 218: 5f 72 65 67 - 21c: 69 73 - 21e: 74 65 - 220: 72 5f - 222: 65 78 - 224: 69 74 - 226: 70 72 - 228: 6f 63 00 5f jal t1, 26096 - 22c: 5f 42 53 53 - 230: 5f 45 4e 44 - 234: 5f 5f 00 5f - 238: 5f 62 73 73 - 23c: 5f 73 74 61 - 240: 72 74 - 242: 00 6d - 244: 65 6d - 246: 73 65 74 00 csrrsi a0, 7, 8 - 24a: 5f 5f 69 65 - 24e: 65 65 - 250: 37 35 34 5f lui a0, 389955 - 254: 73 71 72 74 csrrci sp, 1863, 4 - 258: 66 00 - 25a: 6d 61 - 25c: 69 6e - 25e: 00 5f - 260: 70 6f - 262: 63 6c 5f 6b bltu t5, s5, 1720 - 266: 65 72 - 268: 6e 65 - 26a: 6c 5f - 26c: 4e 65 - 26e: 61 72 - 270: 65 73 - 272: 74 4e - 274: 65 69 - 276: 67 68 62 6f - 27a: 72 5f - 27c: 77 6f 72 6b - 280: 67 72 6f 75 - 284: 70 5f - 286: 66 61 - 288: 73 74 00 61 csrrci s0, 1552, 0 - 28c: 74 65 - 28e: 78 69 - 290: 74 00 - 292: 5f 70 6f 63 - 296: 6c 5f - 298: 6b 65 72 6e - 29c: 65 6c - 29e: 5f 4e 65 61 - 2a2: 72 65 - 2a4: 73 74 4e 65 csrrci s0, 1620, 28 - 2a8: 69 67 - 2aa: 68 62 - 2ac: 6f 72 5f 77 jal tp, 1015668 - 2b0: 6f 72 6b 67 jal tp, 751222 - 2b4: 72 6f - 2b6: 75 70 - 2b8: 00 5f - 2ba: 5f 44 41 54 - 2be: 41 5f - 2c0: 42 45 - 2c2: 47 49 4e 5f - 2c6: 5f 00 5f 65 - 2ca: 64 61 - 2cc: 74 61 - 2ce: 00 5f - 2d0: 70 6f - 2d2: 63 6c 5f 6b bltu t5, s5, 1720 - 2d6: 65 72 - 2d8: 6e 65 - 2da: 6c 5f - 2dc: 4e 65 - 2de: 61 72 - 2e0: 65 73 - 2e2: 74 4e - 2e4: 65 69 - 2e6: 67 68 62 6f - 2ea: 72 00 - 2ec: 76 78 - 2ee: 5f 70 65 72 - 2f2: 66 5f - 2f4: 64 75 - 2f6: 6d 70 - 2f8: 00 5f - 2fa: 65 78 - 2fc: 69 74 - 2fe: 00 76 - 300: 78 5f - 302: 73 70 61 77 csrci 1910, 2 - 306: 6e 5f - 308: 6b 65 72 6e - 30c: 65 6c - 30e: 00 + e: 6c 61 + 10: 62 65 + 12: 6c 5f + 14: 65 78 + 16: 69 74 + 18: 5f 6e 65 78 + 1c: 74 00 + 1e: 52 45 + 20: 54 55 + 22: 52 4e + 24: 00 5f + 26: 5f 63 61 6c + 2a: 6c 5f + 2c: 61 74 + 2e: 65 78 + 30: 69 74 + 32: 2e 63 + 34: 00 72 + 36: 65 67 + 38: 69 73 + 3a: 74 65 + 3c: 72 5f + 3e: 66 69 + 40: 6e 69 + 42: 00 70 + 44: 6f 63 6c 5f jal t1, 812534 + 48: 76 6f + 4a: 72 74 + 4c: 65 78 + 4e: 5f 6b 65 72 + 52: 6e 65 + 54: 6c 2d + 56: 31 30 + 58: 2d 66 + 5a: 62 2d + 5c: 32 65 + 5e: 2d 30 + 60: 61 2d + 62: 61 61 + 64: 2e 63 + 66: 00 70 + 68: 61 72 + 6a: 61 6c + 6c: 6c 65 + 6e: 6c 5f + 70: 62 63 + 72: 00 5f + 74: 5a 38 + 76: 5f 63 6c 5f + 7a: 73 71 72 74 csrrci sp, 1863, 4 + 7e: 66 00 + 80: 76 78 + 82: 5f 73 79 73 + 86: 63 61 6c 6c bltu s8, t1, 1730 + 8a: 73 2e 63 00 csrrs t3, 6, t1 + 8e: 76 78 + 90: 5f 73 70 61 + 94: 77 6e 2e 63 + 98: 00 73 + 9a: 70 61 + 9c: 77 6e 5f 6b + a0: 65 72 + a2: 6e 65 + a4: 6c 5f + a6: 61 6c + a8: 6c 5f + aa: 73 74 75 62 csrrci s0, 1575, 10 + ae: 00 73 + b0: 70 61 + b2: 77 6e 5f 6b + b6: 65 72 + b8: 6e 65 + ba: 6c 5f + bc: 72 65 + be: 6d 5f + c0: 73 74 75 62 csrrci s0, 1575, 10 + c4: 00 73 + c6: 70 61 + c8: 77 6e 5f 6b + cc: 65 72 + ce: 6e 65 + d0: 6c 5f + d2: 61 6c + d4: 6c 5f + d6: 63 62 00 76 bltu zero, zero, 1892 + da: 78 5f + dc: 70 65 + de: 72 66 + e0: 2e 63 + e2: 00 77 + e4: 66 5f + e6: 73 71 72 74 csrrci sp, 1863, 4 + ea: 2e 63 + ec: 00 65 + ee: 66 5f + f0: 73 71 72 74 csrrci sp, 1863, 4 + f4: 2e 63 + f6: 00 65 + f8: 72 72 + fa: 6e 6f + fc: 2e 63 + fe: 00 5f + 100: 5f 61 74 65 + 104: 78 69 + 106: 74 2e + 108: 63 00 69 6d beq s2, s6, 1728 + 10c: 70 75 + 10e: 72 65 + 110: 2e 63 + 112: 00 69 + 114: 6d 70 + 116: 75 72 + 118: 65 5f + 11a: 64 61 + 11c: 74 61 + 11e: 00 5f + 120: 5f 66 69 6e + 124: 69 5f + 126: 61 72 + 128: 72 61 + 12a: 79 5f + 12c: 65 6e + 12e: 64 00 + 130: 5f 5f 66 69 + 134: 6e 69 + 136: 5f 61 72 72 + 13a: 61 79 + 13c: 5f 73 74 61 + 140: 72 74 + 142: 00 5f + 144: 5f 69 6e 69 + 148: 74 5f + 14a: 61 72 + 14c: 72 61 + 14e: 79 5f + 150: 65 6e + 152: 64 00 + 154: 5f 5f 70 72 + 158: 65 69 + 15a: 6e 69 + 15c: 74 5f + 15e: 61 72 + 160: 72 61 + 162: 79 5f + 164: 65 6e + 166: 64 00 + 168: 5f 5f 69 6e + 16c: 69 74 + 16e: 5f 61 72 72 + 172: 61 79 + 174: 5f 73 74 61 + 178: 72 74 + 17a: 00 5f + 17c: 5f 70 72 65 + 180: 69 6e + 182: 69 74 + 184: 5f 61 72 72 + 188: 61 79 + 18a: 5f 73 74 61 + 18e: 72 74 + 190: 00 5f + 192: 5f 73 74 61 + 196: 63 6b 5f 75 bltu t5, s5, 1878 + 19a: 73 61 67 65 csrrsi sp, 1622, 14 + 19e: 00 5f + 1a0: 5f 65 72 72 + 1a4: 6e 6f + 1a6: 00 5f + 1a8: 5f 73 74 61 + 1ac: 63 6b 5f 73 bltu t5, s5, 1846 + 1b0: 69 7a + 1b2: 65 00 + 1b4: 67 5f 77 73 + 1b8: 70 61 + 1ba: 77 6e 5f 61 + 1be: 72 67 + 1c0: 73 00 5f 5f + 1c4: 53 44 41 54 + 1c8: 41 5f + 1ca: 42 45 + 1cc: 47 49 4e 5f + 1d0: 5f 00 5f 5f + 1d4: 67 6c 6f 62 + 1d8: 61 6c + 1da: 5f 70 6f 69 + 1de: 6e 74 + 1e0: 65 72 + 1e2: 00 5f + 1e4: 5f 66 64 6c + 1e8: 69 62 + 1ea: 5f 76 65 72 + 1ee: 73 69 6f 6e csrrsi s2, 1766, 30 + 1f2: 00 5f + 1f4: 67 6c 6f 62 + 1f8: 61 6c + 1fa: 5f 69 6d 70 + 1fe: 75 72 + 200: 65 5f + 202: 70 74 + 204: 72 00 + 206: 5f 5f 6c 69 + 20a: 62 63 + 20c: 5f 69 6e 69 + 210: 74 5f + 212: 61 72 + 214: 72 61 + 216: 79 00 + 218: 5f 5f 6c 69 + 21c: 62 63 + 21e: 5f 66 69 6e + 222: 69 5f + 224: 61 72 + 226: 72 61 + 228: 79 00 + 22a: 76 78 + 22c: 5f 73 65 74 + 230: 5f 73 70 00 + 234: 5f 5f 63 61 + 238: 6c 6c + 23a: 5f 65 78 69 + 23e: 74 70 + 240: 72 6f + 242: 63 73 00 5f bgeu zero, a6, 1510 + 246: 5f 72 65 67 + 24a: 69 73 + 24c: 74 65 + 24e: 72 5f + 250: 65 78 + 252: 69 74 + 254: 70 72 + 256: 6f 63 00 5f jal t1, 26096 + 25a: 5f 42 53 53 + 25e: 5f 45 4e 44 + 262: 5f 5f 00 5f + 266: 5f 62 73 73 + 26a: 5f 73 74 61 + 26e: 72 74 + 270: 00 6d + 272: 65 6d + 274: 73 65 74 00 csrrsi a0, 7, 8 + 278: 5f 5f 69 65 + 27c: 65 65 + 27e: 37 35 34 5f lui a0, 389955 + 282: 73 71 72 74 csrrci sp, 1863, 4 + 286: 66 00 + 288: 6d 61 + 28a: 69 6e + 28c: 00 5f + 28e: 70 6f + 290: 63 6c 5f 6b bltu t5, s5, 1720 + 294: 65 72 + 296: 6e 65 + 298: 6c 5f + 29a: 4e 65 + 29c: 61 72 + 29e: 65 73 + 2a0: 74 4e + 2a2: 65 69 + 2a4: 67 68 62 6f + 2a8: 72 5f + 2aa: 77 6f 72 6b + 2ae: 67 72 6f 75 + 2b2: 70 5f + 2b4: 66 61 + 2b6: 73 74 00 61 csrrci s0, 1552, 0 + 2ba: 74 65 + 2bc: 78 69 + 2be: 74 00 + 2c0: 5f 70 6f 63 + 2c4: 6c 5f + 2c6: 6b 65 72 6e + 2ca: 65 6c + 2cc: 5f 4e 65 61 + 2d0: 72 65 + 2d2: 73 74 4e 65 csrrci s0, 1620, 28 + 2d6: 69 67 + 2d8: 68 62 + 2da: 6f 72 5f 77 jal tp, 1015668 + 2de: 6f 72 6b 67 jal tp, 751222 + 2e2: 72 6f + 2e4: 75 70 + 2e6: 00 5f + 2e8: 5f 44 41 54 + 2ec: 41 5f + 2ee: 42 45 + 2f0: 47 49 4e 5f + 2f4: 5f 00 5f 65 + 2f8: 64 61 + 2fa: 74 61 + 2fc: 00 5f + 2fe: 70 6f + 300: 63 6c 5f 6b bltu t5, s5, 1720 + 304: 65 72 + 306: 6e 65 + 308: 6c 5f + 30a: 4e 65 + 30c: 61 72 + 30e: 65 73 + 310: 74 4e + 312: 65 69 + 314: 67 68 62 6f + 318: 72 00 + 31a: 76 78 + 31c: 5f 70 65 72 + 320: 66 5f + 322: 64 75 + 324: 6d 70 + 326: 00 5f + 328: 65 78 + 32a: 69 74 + 32c: 00 76 + 32e: 78 5f + 330: 73 70 61 77 csrci 1910, 2 + 334: 6e 5f + 336: 6b 65 72 6e + 33a: 65 6c + 33c: 00 Disassembly of section .shstrtab: diff --git a/tests/opencl/nearn/kernel.pocl b/tests/opencl/nearn/kernel.pocl index 998211db..dacb8f48 100644 Binary files a/tests/opencl/nearn/kernel.pocl and b/tests/opencl/nearn/kernel.pocl differ diff --git a/tests/opencl/printf/Makefile b/tests/opencl/oclprintf/Makefile similarity index 77% rename from tests/opencl/printf/Makefile rename to tests/opencl/oclprintf/Makefile index 88eafa1c..92df9612 100644 --- a/tests/opencl/printf/Makefile +++ b/tests/opencl/oclprintf/Makefile @@ -9,8 +9,8 @@ OPTS ?= -n1 VORTEX_DRV_PATH ?= $(realpath ../../../driver) VORTEX_RT_PATH ?= $(realpath ../../../runtime) -K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -float-abi=hard -code-model=small" -K_CFLAGS += "-v -O3 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" +K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -mattr=+vortex -float-abi=hard -code-model=small" +K_CFLAGS += "-v -O3 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -Xclang -target-feature -Xclang +vortex -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" K_LDFLAGS += "-Wl,-Bstatic,-T$(VORTEX_RT_PATH)/linker/vx_link.ld -Wl,--gc-sections $(VORTEX_RT_PATH)/libvortexrt.a -lm" CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors @@ -35,13 +35,13 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ run-fpga: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-simx: $(PROJECT) kernel.pocl LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/opencl/printf/kernel.cl b/tests/opencl/oclprintf/kernel.cl similarity index 67% rename from tests/opencl/printf/kernel.cl rename to tests/opencl/oclprintf/kernel.cl index 24a03a5c..99499671 100644 --- a/tests/opencl/printf/kernel.cl +++ b/tests/opencl/oclprintf/kernel.cl @@ -1,6 +1,6 @@ -__kernel void test_printf (__global const int *A) +__kernel void oclprintf (__global const int *A) { int gid = get_global_id(0); int value = A[gid]; printf("Print Test! value[%d]=%d\n", gid, value); -} \ No newline at end of file +} diff --git a/tests/opencl/printf/kernel.pocl b/tests/opencl/oclprintf/kernel.pocl similarity index 79% rename from tests/opencl/printf/kernel.pocl rename to tests/opencl/oclprintf/kernel.pocl index 58e103aa..a687db75 100644 Binary files a/tests/opencl/printf/kernel.pocl and b/tests/opencl/oclprintf/kernel.pocl differ diff --git a/tests/opencl/printf/main.cc b/tests/opencl/oclprintf/main.cc similarity index 99% rename from tests/opencl/printf/main.cc rename to tests/opencl/oclprintf/main.cc index 5be62a71..7c0463cf 100644 --- a/tests/opencl/printf/main.cc +++ b/tests/opencl/oclprintf/main.cc @@ -7,7 +7,7 @@ #include #include -#define KERNEL_NAME "test_printf" +#define KERNEL_NAME "oclprintf" #define CL_CHECK(_expr) \ do { \ diff --git a/tests/opencl/oclprintf/oclprintf.dump b/tests/opencl/oclprintf/oclprintf.dump new file mode 100644 index 00000000..490f0995 --- /dev/null +++ b/tests/opencl/oclprintf/oclprintf.dump @@ -0,0 +1,101552 @@ + +/tmp/pocl_vortex_kernel-d3-f2-8a-23-35.elf: file format ELF32-riscv + + +Disassembly of section .init: + +80000000 _start: +80000000: 97 35 00 00 auipc a1, 3 +80000004: 93 85 85 cb addi a1, a1, -840 +80000008: 73 25 10 fc csrr a0, 4033 +8000000c: 6b 10 b5 00 vx_wspawn a0, a1 +80000010: ef 20 90 4a jal 11432 +80000014: 13 05 10 00 addi a0, zero, 1 +80000018: 6b 00 05 00 vx_tmc a0 +8000001c: 17 85 01 00 auipc a0, 24 +80000020: 13 05 c5 b8 addi a0, a0, -1140 +80000024: 17 86 01 00 auipc a2, 24 +80000028: 13 06 c6 c3 addi a2, a2, -964 +8000002c: 33 06 a6 40 sub a2, a2, a0 +80000030: 93 05 00 00 mv a1, zero +80000034: ef 30 40 47 jal 13428 +80000038: 17 35 00 00 auipc a0, 3 +8000003c: 13 05 05 de addi a0, a0, -544 +80000040: ef 30 00 42 jal 13344 +80000044: ef 20 90 53 jal 11576 +80000048: ef 00 00 02 jal 32 +8000004c: 6f 30 80 42 j 13352 + +Disassembly of section .text: + +80000050 register_fini: +80000050: 93 07 00 00 mv a5, zero +80000054: 63 88 07 00 beqz a5, 16 +80000058: 37 35 00 80 lui a0, 524291 +8000005c: 13 05 85 e1 addi a0, a0, -488 +80000060: 6f 30 00 40 j 13312 +80000064: 67 80 00 00 ret + +80000068 main: +80000068: 13 01 01 ff addi sp, sp, -16 +8000006c: 23 26 11 00 sw ra, 12(sp) +80000070: 37 35 00 80 lui a0, 524291 +80000074: 93 05 45 ac addi a1, a0, -1340 +80000078: 37 05 ff 7f lui a0, 524272 +8000007c: 13 06 45 03 addi a2, a0, 52 +80000080: 37 05 ff 7f lui a0, 524272 +80000084: ef 30 40 01 jal 12308 +80000088: 13 05 00 00 mv a0, zero +8000008c: 83 20 c1 00 lw ra, 12(sp) +80000090: 13 01 01 01 addi sp, sp, 16 +80000094: 67 80 00 00 ret + +80000098 __pocl_printf_putchw: +80000098: 83 23 45 01 lw t2, 20(a0) +8000009c: 13 08 c5 01 addi a6, a0, 28 +800000a0: 83 45 c5 01 lbu a1, 28(a0) +800000a4: 93 f6 25 00 andi a3, a1, 2 +800000a8: 13 b7 16 00 seqz a4, a3 +800000ac: 93 f6 25 08 andi a3, a1, 130 +800000b0: 93 c6 26 08 xori a3, a3, 130 +800000b4: 93 b6 16 00 seqz a3, a3 +800000b8: 6f 00 40 00 j 4 +800000bc: 93 f6 16 00 andi a3, a3, 1 +800000c0: 93 02 00 00 mv t0, zero +800000c4: 63 8c 06 00 beqz a3, 24 +800000c8: 6f 00 40 00 j 4 +800000cc: 83 26 85 01 lw a3, 24(a0) +800000d0: 93 c6 06 01 xori a3, a3, 16 +800000d4: 93 b2 16 00 seqz t0, a3 +800000d8: 6f 00 40 00 j 4 +800000dc: 83 26 05 00 lw a3, 0(a0) +800000e0: 83 c7 06 00 lbu a5, 0(a3) +800000e4: 13 c6 07 03 xori a2, a5, 48 +800000e8: 13 36 16 00 seqz a2, a2 +800000ec: 33 66 c7 00 or a2, a4, a2 +800000f0: 13 76 16 00 andi a2, a2, 1 +800000f4: 93 08 00 00 mv a7, zero +800000f8: 63 1c 06 00 bnez a2, 24 +800000fc: 6f 00 40 00 j 4 +80000100: 03 26 85 01 lw a2, 24(a0) +80000104: 13 46 86 00 xori a2, a2, 8 +80000108: 93 38 16 00 seqz a7, a2 +8000010c: 6f 00 40 00 j 4 +80000110: 13 f6 05 03 andi a2, a1, 48 +80000114: 33 33 c0 00 snez t1, a2 +80000118: 13 f6 05 06 andi a2, a1, 96 +8000011c: 13 46 06 04 xori a2, a2, 64 +80000120: 13 3e 16 00 seqz t3, a2 +80000124: 13 06 10 00 addi a2, zero, 1 +80000128: 63 d4 c3 00 bge t2, a2, 8 +8000012c: 6f 00 40 04 j 68 +80000130: 13 f6 f7 0f andi a2, a5, 255 +80000134: 63 14 06 00 bnez a2, 8 +80000138: 6f 00 80 03 j 56 +8000013c: 6f 00 40 00 j 4 +80000140: 13 86 03 00 mv a2, t2 +80000144: 93 87 06 00 mv a5, a3 +80000148: 93 86 17 00 addi a3, a5, 1 +8000014c: 93 03 f6 ff addi t2, a2, -1 +80000150: 83 c7 17 00 lbu a5, 1(a5) +80000154: 13 07 20 00 addi a4, zero, 2 +80000158: 63 54 e6 00 bge a2, a4, 8 +8000015c: 6f 00 00 01 j 16 +80000160: 13 f6 f7 0f andi a2, a5, 255 +80000164: e3 1e 06 fc bnez a2, -36 +80000168: 6f 00 40 00 j 4 +8000016c: 6f 00 40 00 j 4 +80000170: 13 76 13 00 andi a2, t1, 1 +80000174: 93 76 1e 00 andi a3, t3, 1 +80000178: 33 06 d6 00 add a2, a2, a3 +8000017c: b3 86 c3 40 sub a3, t2, a2 +80000180: 13 86 e6 ff addi a2, a3, -2 +80000184: 13 f7 12 00 andi a4, t0, 1 +80000188: 63 14 07 00 bnez a4, 8 +8000018c: 13 86 06 00 mv a2, a3 +80000190: 93 f6 18 00 andi a3, a7, 1 +80000194: b3 03 d6 40 sub t2, a2, a3 +80000198: 93 f5 55 00 andi a1, a1, 5 +8000019c: 63 84 05 00 beqz a1, 8 +800001a0: 6f 00 c0 06 j 108 +800001a4: 93 87 f3 ff addi a5, t2, -1 +800001a8: 93 05 10 00 addi a1, zero, 1 +800001ac: 63 d6 b3 00 bge t2, a1, 12 +800001b0: 93 83 07 00 mv t2, a5 +800001b4: 6f 00 80 05 j 88 +800001b8: 93 05 85 00 addi a1, a0, 8 +800001bc: 93 0e c5 00 addi t4, a0, 12 +800001c0: 93 03 45 00 addi t2, a0, 4 +800001c4: 6f 00 40 00 j 4 +800001c8: 93 86 07 00 mv a3, a5 +800001cc: 83 a7 05 00 lw a5, 0(a1) +800001d0: 03 a7 0e 00 lw a4, 0(t4) +800001d4: 63 f2 e7 02 bgeu a5, a4, 36 +800001d8: 6f 00 40 00 j 4 +800001dc: 03 a7 03 00 lw a4, 0(t2) +800001e0: 13 86 17 00 addi a2, a5, 1 +800001e4: 23 a0 c5 00 sw a2, 0(a1) +800001e8: 33 06 f7 00 add a2, a4, a5 +800001ec: 13 07 00 02 addi a4, zero, 32 +800001f0: 23 00 e6 00 sb a4, 0(a2) +800001f4: 6f 00 40 00 j 4 +800001f8: 93 87 f6 ff addi a5, a3, -1 +800001fc: e3 46 d0 fc bgtz a3, -52 +80000200: 6f 00 40 00 j 4 +80000204: 93 03 f0 ff addi t2, zero, -1 +80000208: 6f 00 40 00 j 4 +8000020c: 93 75 1e 00 andi a1, t3, 1 +80000210: 63 8c 05 02 beqz a1, 56 +80000214: 6f 00 40 00 j 4 +80000218: 93 05 85 00 addi a1, a0, 8 +8000021c: 83 26 85 00 lw a3, 8(a0) +80000220: 03 26 c5 00 lw a2, 12(a0) +80000224: 63 f2 c6 02 bgeu a3, a2, 36 +80000228: 6f 00 40 00 j 4 +8000022c: 03 26 45 00 lw a2, 4(a0) +80000230: 13 87 16 00 addi a4, a3, 1 +80000234: 23 a0 e5 00 sw a4, 0(a1) +80000238: b3 05 d6 00 add a1, a2, a3 +8000023c: 13 06 00 02 addi a2, zero, 32 +80000240: 23 80 c5 00 sb a2, 0(a1) +80000244: 6f 00 40 00 j 4 +80000248: 93 75 13 00 andi a1, t1, 1 +8000024c: 63 84 05 04 beqz a1, 72 +80000250: 6f 00 40 00 j 4 +80000254: 93 05 85 00 addi a1, a0, 8 +80000258: 83 26 85 00 lw a3, 8(a0) +8000025c: 03 26 c5 00 lw a2, 12(a0) +80000260: 63 fa c6 02 bgeu a3, a2, 52 +80000264: 6f 00 40 00 j 4 +80000268: 03 46 08 00 lbu a2, 0(a6) +8000026c: 13 76 06 02 andi a2, a2, 32 +80000270: 13 07 b0 02 addi a4, zero, 43 +80000274: 63 04 06 00 beqz a2, 8 +80000278: 13 07 d0 02 addi a4, zero, 45 +8000027c: 03 26 45 00 lw a2, 4(a0) +80000280: 93 87 16 00 addi a5, a3, 1 +80000284: 23 a0 f5 00 sw a5, 0(a1) +80000288: b3 05 d6 00 add a1, a2, a3 +8000028c: 23 80 e5 00 sb a4, 0(a1) +80000290: 6f 00 40 00 j 4 +80000294: 93 f5 12 00 andi a1, t0, 1 +80000298: 63 88 05 04 beqz a1, 80 +8000029c: 6f 00 40 00 j 4 +800002a0: 93 05 85 00 addi a1, a0, 8 +800002a4: 83 26 85 00 lw a3, 8(a0) +800002a8: 03 26 c5 00 lw a2, 12(a0) +800002ac: 63 f2 c6 02 bgeu a3, a2, 36 +800002b0: 6f 00 40 00 j 4 +800002b4: 03 26 45 00 lw a2, 4(a0) +800002b8: 13 87 16 00 addi a4, a3, 1 +800002bc: 23 a0 e5 00 sw a4, 0(a1) +800002c0: b3 05 d6 00 add a1, a2, a3 +800002c4: 13 06 00 03 addi a2, zero, 48 +800002c8: 23 80 c5 00 sb a2, 0(a1) +800002cc: 6f 00 40 00 j 4 +800002d0: 83 45 08 00 lbu a1, 0(a6) +800002d4: 13 f6 85 00 andi a2, a1, 8 +800002d8: 93 05 80 07 addi a1, zero, 120 +800002dc: 63 04 06 00 beqz a2, 8 +800002e0: 93 05 80 05 addi a1, zero, 88 +800002e4: 6f 00 40 01 j 20 +800002e8: 93 05 00 03 addi a1, zero, 48 +800002ec: 13 f6 18 00 andi a2, a7, 1 +800002f0: 63 0a 06 02 beqz a2, 52 +800002f4: 6f 00 40 00 j 4 +800002f8: 93 06 85 00 addi a3, a0, 8 +800002fc: 03 27 85 00 lw a4, 8(a0) +80000300: 03 26 c5 00 lw a2, 12(a0) +80000304: 63 70 c7 02 bgeu a4, a2, 32 +80000308: 6f 00 40 00 j 4 +8000030c: 03 26 45 00 lw a2, 4(a0) +80000310: 93 07 17 00 addi a5, a4, 1 +80000314: 23 a0 f6 00 sw a5, 0(a3) +80000318: 33 06 e6 00 add a2, a2, a4 +8000031c: 23 00 b6 00 sb a1, 0(a2) +80000320: 6f 00 40 00 j 4 +80000324: 83 45 08 00 lbu a1, 0(a6) +80000328: 93 f5 15 00 andi a1, a1, 1 +8000032c: 63 94 05 00 bnez a1, 8 +80000330: 6f 00 c0 06 j 108 +80000334: 93 87 f3 ff addi a5, t2, -1 +80000338: 93 05 10 00 addi a1, zero, 1 +8000033c: 63 d6 b3 00 bge t2, a1, 12 +80000340: 93 83 07 00 mv t2, a5 +80000344: 6f 00 80 05 j 88 +80000348: 93 05 85 00 addi a1, a0, 8 +8000034c: 93 02 c5 00 addi t0, a0, 12 +80000350: 93 08 45 00 addi a7, a0, 4 +80000354: 6f 00 40 00 j 4 +80000358: 13 87 07 00 mv a4, a5 +8000035c: 83 a7 05 00 lw a5, 0(a1) +80000360: 83 a6 02 00 lw a3, 0(t0) +80000364: 63 f2 d7 02 bgeu a5, a3, 36 +80000368: 6f 00 40 00 j 4 +8000036c: 83 a6 08 00 lw a3, 0(a7) +80000370: 13 86 17 00 addi a2, a5, 1 +80000374: 23 a0 c5 00 sw a2, 0(a1) +80000378: 33 86 f6 00 add a2, a3, a5 +8000037c: 93 06 00 03 addi a3, zero, 48 +80000380: 23 00 d6 00 sb a3, 0(a2) +80000384: 6f 00 40 00 j 4 +80000388: 93 07 f7 ff addi a5, a4, -1 +8000038c: e3 46 e0 fc bgtz a4, -52 +80000390: 6f 00 40 00 j 4 +80000394: 93 03 f0 ff addi t2, zero, -1 +80000398: 6f 00 40 00 j 4 +8000039c: 83 25 05 00 lw a1, 0(a0) +800003a0: 83 c6 05 00 lbu a3, 0(a1) +800003a4: 63 8a 06 04 beqz a3, 84 +800003a8: 6f 00 40 00 j 4 +800003ac: 13 07 85 00 addi a4, a0, 8 +800003b0: 93 02 c5 00 addi t0, a0, 12 +800003b4: 93 08 45 00 addi a7, a0, 4 +800003b8: 6f 00 40 00 j 4 +800003bc: 93 85 15 00 addi a1, a1, 1 +800003c0: 03 26 07 00 lw a2, 0(a4) +800003c4: 83 a7 02 00 lw a5, 0(t0) +800003c8: 63 70 f6 02 bgeu a2, a5, 32 +800003cc: 6f 00 40 00 j 4 +800003d0: 03 a3 08 00 lw t1, 0(a7) +800003d4: 93 07 16 00 addi a5, a2, 1 +800003d8: 23 20 f7 00 sw a5, 0(a4) +800003dc: 33 06 c3 00 add a2, t1, a2 +800003e0: 23 00 d6 00 sb a3, 0(a2) +800003e4: 6f 00 40 00 j 4 +800003e8: 83 c6 05 00 lbu a3, 0(a1) +800003ec: e3 98 06 fc bnez a3, -48 +800003f0: 6f 00 40 00 j 4 +800003f4: 6f 00 40 00 j 4 +800003f8: 83 45 08 00 lbu a1, 0(a6) +800003fc: 93 f5 55 00 andi a1, a1, 5 +80000400: 13 06 10 00 addi a2, zero, 1 +80000404: 63 c6 c3 06 blt t2, a2, 108 +80000408: 6f 00 40 00 j 4 +8000040c: 93 f5 f5 0f andi a1, a1, 255 +80000410: 13 06 40 00 addi a2, zero, 4 +80000414: 63 9e c5 04 bne a1, a2, 92 +80000418: 6f 00 40 00 j 4 +8000041c: 93 05 85 00 addi a1, a0, 8 +80000420: 93 06 c5 00 addi a3, a0, 12 +80000424: 13 08 45 00 addi a6, a0, 4 +80000428: 6f 00 40 00 j 4 +8000042c: 13 87 03 00 mv a4, t2 +80000430: 93 03 f7 ff addi t2, a4, -1 +80000434: 03 a6 05 00 lw a2, 0(a1) +80000438: 83 a7 06 00 lw a5, 0(a3) +8000043c: 63 72 f6 02 bgeu a2, a5, 36 +80000440: 6f 00 40 00 j 4 +80000444: 83 27 08 00 lw a5, 0(a6) +80000448: 13 05 16 00 addi a0, a2, 1 +8000044c: 23 a0 a5 00 sw a0, 0(a1) +80000450: 33 85 c7 00 add a0, a5, a2 +80000454: 13 06 00 02 addi a2, zero, 32 +80000458: 23 00 c5 00 sb a2, 0(a0) +8000045c: 6f 00 40 00 j 4 +80000460: 13 05 10 00 addi a0, zero, 1 +80000464: e3 44 e5 fc blt a0, a4, -56 +80000468: 6f 00 40 00 j 4 +8000046c: 6f 00 40 00 j 4 +80000470: 6f 00 40 00 j 4 +80000474: 67 80 00 00 ret + +80000478 __pocl_printf_ulong: +80000478: 13 01 01 fc addi sp, sp, -64 +8000047c: 83 26 85 01 lw a3, 24(a0) +80000480: 13 c6 06 01 xori a2, a3, 16 +80000484: 13 36 16 00 seqz a2, a2 +80000488: 6f 00 40 00 j 4 +8000048c: 13 76 16 00 andi a2, a2, 1 +80000490: 63 04 06 10 beqz a2, 264 +80000494: 6f 00 40 00 j 4 +80000498: 33 36 b0 00 snez a2, a1 +8000049c: 83 46 c5 01 lbu a3, 28(a0) +800004a0: 13 16 76 00 slli a2, a2, 7 +800004a4: 13 f7 f6 07 andi a4, a3, 127 +800004a8: 33 66 c7 00 or a2, a4, a2 +800004ac: 23 0e c5 00 sb a2, 28(a0) +800004b0: 13 06 01 00 mv a2, sp +800004b4: 13 06 00 00 mv a2, zero +800004b8: 63 8e 05 04 beqz a1, 92 +800004bc: 6f 00 40 00 j 4 +800004c0: 13 f6 86 00 andi a2, a3, 8 +800004c4: 13 08 70 05 addi a6, zero, 87 +800004c8: 63 04 06 00 beqz a2, 8 +800004cc: 13 08 70 03 addi a6, zero, 55 +800004d0: 13 07 00 00 mv a4, zero +800004d4: 6f 00 40 00 j 4 +800004d8: 93 f6 f5 00 andi a3, a1, 15 +800004dc: 93 d5 45 00 srli a1, a1, 4 +800004e0: 93 e7 06 03 ori a5, a3, 48 +800004e4: b3 88 06 01 add a7, a3, a6 +800004e8: 13 06 a0 00 addi a2, zero, 10 +800004ec: 63 e4 c6 00 bltu a3, a2, 8 +800004f0: 93 87 08 00 mv a5, a7 +800004f4: 13 06 17 00 addi a2, a4, 1 +800004f8: 93 06 01 00 mv a3, sp +800004fc: b3 86 e6 00 add a3, a3, a4 +80000500: 23 80 f6 00 sb a5, 0(a3) +80000504: 13 07 06 00 mv a4, a2 +80000508: e3 98 05 fc bnez a1, -48 +8000050c: 6f 00 40 00 j 4 +80000510: 6f 00 40 00 j 4 +80000514: 83 25 05 01 lw a1, 16(a0) +80000518: 93 06 10 00 addi a3, zero, 1 +8000051c: 63 d6 d5 00 bge a1, a3, 12 +80000520: 93 05 06 00 mv a1, a2 +80000524: 6f 00 40 03 j 52 +80000528: 63 66 b6 00 bltu a2, a1, 12 +8000052c: 93 05 06 00 mv a1, a2 +80000530: 6f 00 80 02 j 40 +80000534: 6f 00 40 00 j 4 +80000538: 93 06 01 00 mv a3, sp +8000053c: b3 86 c6 00 add a3, a3, a2 +80000540: 13 07 00 03 addi a4, zero, 48 +80000544: 23 80 e6 00 sb a4, 0(a3) +80000548: 13 06 16 00 addi a2, a2, 1 +8000054c: e3 16 b6 fe bne a2, a1, -20 +80000550: 6f 00 40 00 j 4 +80000554: 6f 00 40 00 j 4 +80000558: 03 26 05 00 lw a2, 0(a0) +8000055c: 63 94 05 00 bnez a1, 8 +80000560: 6f 00 00 03 j 48 +80000564: 6f 00 40 00 j 4 +80000568: 93 06 06 00 mv a3, a2 +8000056c: 93 85 f5 ff addi a1, a1, -1 +80000570: 13 06 01 00 mv a2, sp +80000574: 33 06 b6 00 add a2, a2, a1 +80000578: 03 07 06 00 lb a4, 0(a2) +8000057c: 13 86 16 00 addi a2, a3, 1 +80000580: 23 80 e6 00 sb a4, 0(a3) +80000584: e3 92 05 fe bnez a1, -28 +80000588: 6f 00 40 00 j 4 +8000058c: 6f 00 40 00 j 4 +80000590: 23 00 06 00 sb zero, 0(a2) +80000594: 6f 00 40 0d j 212 +80000598: 13 06 01 00 mv a2, sp +8000059c: 13 06 00 00 mv a2, zero +800005a0: 63 82 05 04 beqz a1, 68 +800005a4: 6f 00 40 00 j 4 +800005a8: 13 06 00 00 mv a2, zero +800005ac: 6f 00 40 00 j 4 +800005b0: 93 08 06 00 mv a7, a2 +800005b4: 93 87 05 00 mv a5, a1 +800005b8: b3 d5 d7 02 divu a1, a5, a3 +800005bc: 33 86 d5 02 mul a2, a1, a3 +800005c0: 33 86 c7 40 sub a2, a5, a2 +800005c4: 13 08 06 03 addi a6, a2, 48 +800005c8: 13 86 18 00 addi a2, a7, 1 +800005cc: 13 07 01 00 mv a4, sp +800005d0: 33 07 17 01 add a4, a4, a7 +800005d4: 23 00 07 01 sb a6, 0(a4) +800005d8: e3 fc d7 fc bgeu a5, a3, -40 +800005dc: 6f 00 40 00 j 4 +800005e0: 6f 00 40 00 j 4 +800005e4: 83 25 05 01 lw a1, 16(a0) +800005e8: 93 06 10 00 addi a3, zero, 1 +800005ec: 63 d6 d5 00 bge a1, a3, 12 +800005f0: 93 05 06 00 mv a1, a2 +800005f4: 6f 00 40 03 j 52 +800005f8: 63 66 b6 00 bltu a2, a1, 12 +800005fc: 93 05 06 00 mv a1, a2 +80000600: 6f 00 80 02 j 40 +80000604: 6f 00 40 00 j 4 +80000608: 93 06 01 00 mv a3, sp +8000060c: b3 86 c6 00 add a3, a3, a2 +80000610: 13 07 00 03 addi a4, zero, 48 +80000614: 23 80 e6 00 sb a4, 0(a3) +80000618: 13 06 16 00 addi a2, a2, 1 +8000061c: e3 16 b6 fe bne a2, a1, -20 +80000620: 6f 00 40 00 j 4 +80000624: 6f 00 40 00 j 4 +80000628: 03 26 05 00 lw a2, 0(a0) +8000062c: 63 94 05 00 bnez a1, 8 +80000630: 6f 00 00 03 j 48 +80000634: 6f 00 40 00 j 4 +80000638: 93 06 06 00 mv a3, a2 +8000063c: 93 85 f5 ff addi a1, a1, -1 +80000640: 13 06 01 00 mv a2, sp +80000644: 33 06 b6 00 add a2, a2, a1 +80000648: 03 07 06 00 lb a4, 0(a2) +8000064c: 13 86 16 00 addi a2, a3, 1 +80000650: 23 80 e6 00 sb a4, 0(a3) +80000654: e3 92 05 fe bnez a1, -28 +80000658: 6f 00 40 00 j 4 +8000065c: 6f 00 40 00 j 4 +80000660: 23 00 06 00 sb zero, 0(a2) +80000664: 6f 00 40 00 j 4 +80000668: 6f 00 40 00 j 4 +8000066c: 13 01 01 04 addi sp, sp, 64 +80000670: 17 03 00 00 auipc t1, 0 +80000674: 67 00 83 a2 jr -1496(t1) + +80000678 __pocl_print_ints_uchar: +80000678: 13 01 01 f8 addi sp, sp, -128 +8000067c: 23 2e 11 06 sw ra, 124(sp) +80000680: 23 2c 81 06 sw s0, 120(sp) +80000684: 23 2a 91 06 sw s1, 116(sp) +80000688: 23 28 21 07 sw s2, 112(sp) +8000068c: 23 26 31 07 sw s3, 108(sp) +80000690: 23 24 41 07 sw s4, 104(sp) +80000694: 23 22 51 07 sw s5, 100(sp) +80000698: 23 20 61 07 sw s6, 96(sp) +8000069c: 23 2e 71 05 sw s7, 92(sp) +800006a0: 23 2c 81 05 sw s8, 88(sp) +800006a4: 23 2a 91 05 sw s9, 84(sp) +800006a8: 23 28 a1 05 sw s10, 80(sp) +800006ac: 23 26 b1 05 sw s11, 76(sp) +800006b0: 93 09 06 00 mv s3, a2 +800006b4: 13 89 05 00 mv s2, a1 +800006b8: 93 04 05 00 mv s1, a0 +800006bc: 13 8d c4 01 addi s10, s1, 28 +800006c0: 03 ca c4 01 lbu s4, 28(s1) +800006c4: 13 b5 19 00 seqz a0, s3 +800006c8: 6f 00 40 00 j 4 +800006cc: 13 75 15 00 andi a0, a0, 1 +800006d0: 63 1c 05 1a bnez a0, 440 +800006d4: 6f 00 40 00 j 4 +800006d8: 93 8a 84 00 addi s5, s1, 8 +800006dc: 13 8b c4 00 addi s6, s1, 12 +800006e0: 93 8b 44 00 addi s7, s1, 4 +800006e4: 13 05 c1 00 addi a0, sp, 12 +800006e8: 13 8c 84 01 addi s8, s1, 24 +800006ec: 93 8c 04 01 addi s9, s1, 16 +800006f0: 63 98 06 00 bnez a3, 16 +800006f4: 6f 00 40 00 j 4 +800006f8: 93 0d 00 00 mv s11, zero +800006fc: 6f 00 c0 02 j 44 +80000700: 23 00 4d 01 sb s4, 0(s10) +80000704: 83 45 09 00 lbu a1, 0(s2) +80000708: 13 85 04 00 mv a0, s1 +8000070c: 97 00 00 00 auipc ra, 0 +80000710: e7 80 c0 d6 jalr -660(ra) +80000714: 13 05 10 00 addi a0, zero, 1 +80000718: 63 84 a9 16 beq s3, a0, 360 +8000071c: 6f 00 40 00 j 4 +80000720: 13 04 10 00 addi s0, zero, 1 +80000724: 6f 00 c0 1a j 428 +80000728: 23 00 4d 01 sb s4, 0(s10) +8000072c: 63 8a 0d 02 beqz s11, 52 +80000730: 6f 00 40 00 j 4 +80000734: 03 a5 0a 00 lw a0, 0(s5) +80000738: 83 25 0b 00 lw a1, 0(s6) +8000073c: 63 72 b5 02 bgeu a0, a1, 36 +80000740: 6f 00 40 00 j 4 +80000744: 83 a5 0b 00 lw a1, 0(s7) +80000748: 13 06 15 00 addi a2, a0, 1 +8000074c: 23 a0 ca 00 sw a2, 0(s5) +80000750: 33 85 a5 00 add a0, a1, a0 +80000754: 93 05 c0 02 addi a1, zero, 44 +80000758: 23 00 b5 00 sb a1, 0(a0) +8000075c: 6f 00 40 00 j 4 +80000760: 33 05 b9 01 add a0, s2, s11 +80000764: 03 05 05 00 lb a0, 0(a0) +80000768: 63 42 05 02 bltz a0, 36 +8000076c: 6f 00 40 00 j 4 +80000770: 83 45 0d 00 lbu a1, 0(s10) +80000774: 93 f5 f5 0d andi a1, a1, 223 +80000778: 23 00 bd 00 sb a1, 0(s10) +8000077c: 13 76 f5 0f andi a2, a0, 255 +80000780: 93 05 00 00 mv a1, zero +80000784: 63 0e 06 04 beqz a2, 92 +80000788: 6f 00 80 01 j 24 +8000078c: 33 05 a0 40 neg a0, a0 +80000790: 83 05 0d 00 lb a1, 0(s10) +80000794: 93 e5 05 02 ori a1, a1, 32 +80000798: 23 00 bd 00 sb a1, 0(s10) +8000079c: 6f 00 40 00 j 4 +800007a0: 03 26 0c 00 lw a2, 0(s8) +800007a4: 93 05 00 00 mv a1, zero +800007a8: 6f 00 40 00 j 4 +800007ac: 93 86 05 00 mv a3, a1 +800007b0: 13 07 05 00 mv a4, a0 +800007b4: 33 55 c7 02 divu a0, a4, a2 +800007b8: b3 05 c5 02 mul a1, a0, a2 +800007bc: b3 05 b7 40 sub a1, a4, a1 +800007c0: 93 87 05 03 addi a5, a1, 48 +800007c4: 93 85 16 00 addi a1, a3, 1 +800007c8: 13 04 c1 00 addi s0, sp, 12 +800007cc: b3 06 d4 00 add a3, s0, a3 +800007d0: 23 80 f6 00 sb a5, 0(a3) +800007d4: e3 7c c7 fc bgeu a4, a2, -40 +800007d8: 6f 00 40 00 j 4 +800007dc: 6f 00 40 00 j 4 +800007e0: 03 a5 0c 00 lw a0, 0(s9) +800007e4: 13 06 10 00 addi a2, zero, 1 +800007e8: 63 56 c5 00 bge a0, a2, 12 +800007ec: 13 85 05 00 mv a0, a1 +800007f0: 6f 00 40 03 j 52 +800007f4: 63 e6 a5 00 bltu a1, a0, 12 +800007f8: 13 85 05 00 mv a0, a1 +800007fc: 6f 00 80 02 j 40 +80000800: 6f 00 40 00 j 4 +80000804: 13 06 c1 00 addi a2, sp, 12 +80000808: 33 06 b6 00 add a2, a2, a1 +8000080c: 93 06 00 03 addi a3, zero, 48 +80000810: 23 00 d6 00 sb a3, 0(a2) +80000814: 93 85 15 00 addi a1, a1, 1 +80000818: e3 96 a5 fe bne a1, a0, -20 +8000081c: 6f 00 40 00 j 4 +80000820: 6f 00 40 00 j 4 +80000824: 83 a5 04 00 lw a1, 0(s1) +80000828: 63 14 05 00 bnez a0, 8 +8000082c: 6f 00 00 03 j 48 +80000830: 6f 00 40 00 j 4 +80000834: 13 86 05 00 mv a2, a1 +80000838: 13 05 f5 ff addi a0, a0, -1 +8000083c: 93 05 c1 00 addi a1, sp, 12 +80000840: b3 85 a5 00 add a1, a1, a0 +80000844: 83 86 05 00 lb a3, 0(a1) +80000848: 93 05 16 00 addi a1, a2, 1 +8000084c: 23 00 d6 00 sb a3, 0(a2) +80000850: e3 12 05 fe bnez a0, -28 +80000854: 6f 00 40 00 j 4 +80000858: 6f 00 40 00 j 4 +8000085c: 23 80 05 00 sb zero, 0(a1) +80000860: 13 85 04 00 mv a0, s1 +80000864: 97 00 00 00 auipc ra, 0 +80000868: e7 80 40 83 jalr -1996(ra) +8000086c: 93 8d 1d 00 addi s11, s11, 1 +80000870: e3 9c 3d eb bne s11, s3, -328 +80000874: 6f 00 40 00 j 4 +80000878: 6f 00 c0 00 j 12 +8000087c: 6f 00 40 00 j 4 +80000880: 6f 00 c0 00 j 12 +80000884: 6f 00 80 00 j 8 +80000888: 6f 00 80 00 j 8 +8000088c: 6f 00 80 00 j 8 +80000890: 6f 00 40 00 j 4 +80000894: 83 2d c1 04 lw s11, 76(sp) +80000898: 03 2d 01 05 lw s10, 80(sp) +8000089c: 83 2c 41 05 lw s9, 84(sp) +800008a0: 03 2c 81 05 lw s8, 88(sp) +800008a4: 83 2b c1 05 lw s7, 92(sp) +800008a8: 03 2b 01 06 lw s6, 96(sp) +800008ac: 83 2a 41 06 lw s5, 100(sp) +800008b0: 03 2a 81 06 lw s4, 104(sp) +800008b4: 83 29 c1 06 lw s3, 108(sp) +800008b8: 03 29 01 07 lw s2, 112(sp) +800008bc: 83 24 41 07 lw s1, 116(sp) +800008c0: 03 24 81 07 lw s0, 120(sp) +800008c4: 83 20 c1 07 lw ra, 124(sp) +800008c8: 13 01 01 08 addi sp, sp, 128 +800008cc: 67 80 00 00 ret +800008d0: 23 00 4d 01 sb s4, 0(s10) +800008d4: 03 a5 0a 00 lw a0, 0(s5) +800008d8: 83 25 0b 00 lw a1, 0(s6) +800008dc: 63 72 b5 02 bgeu a0, a1, 36 +800008e0: 6f 00 40 00 j 4 +800008e4: 83 a5 0b 00 lw a1, 0(s7) +800008e8: 13 06 15 00 addi a2, a0, 1 +800008ec: 23 a0 ca 00 sw a2, 0(s5) +800008f0: 33 85 a5 00 add a0, a1, a0 +800008f4: 93 05 c0 02 addi a1, zero, 44 +800008f8: 23 00 b5 00 sb a1, 0(a0) +800008fc: 6f 00 40 00 j 4 +80000900: 33 05 89 00 add a0, s2, s0 +80000904: 83 45 05 00 lbu a1, 0(a0) +80000908: 13 85 04 00 mv a0, s1 +8000090c: 97 00 00 00 auipc ra, 0 +80000910: e7 80 c0 b6 jalr -1172(ra) +80000914: 13 04 14 00 addi s0, s0, 1 +80000918: e3 02 34 f7 beq s0, s3, -156 +8000091c: 6f f0 5f fb j -76 + +80000920 __pocl_print_ints_ushort: +80000920: 13 01 01 f8 addi sp, sp, -128 +80000924: 23 2e 11 06 sw ra, 124(sp) +80000928: 23 2c 81 06 sw s0, 120(sp) +8000092c: 23 2a 91 06 sw s1, 116(sp) +80000930: 23 28 21 07 sw s2, 112(sp) +80000934: 23 26 31 07 sw s3, 108(sp) +80000938: 23 24 41 07 sw s4, 104(sp) +8000093c: 23 22 51 07 sw s5, 100(sp) +80000940: 23 20 61 07 sw s6, 96(sp) +80000944: 23 2e 71 05 sw s7, 92(sp) +80000948: 23 2c 81 05 sw s8, 88(sp) +8000094c: 23 2a 91 05 sw s9, 84(sp) +80000950: 23 28 a1 05 sw s10, 80(sp) +80000954: 23 26 b1 05 sw s11, 76(sp) +80000958: 93 09 06 00 mv s3, a2 +8000095c: 13 89 05 00 mv s2, a1 +80000960: 93 04 05 00 mv s1, a0 +80000964: 13 8d c4 01 addi s10, s1, 28 +80000968: 03 ca c4 01 lbu s4, 28(s1) +8000096c: 13 b5 19 00 seqz a0, s3 +80000970: 6f 00 40 00 j 4 +80000974: 13 75 15 00 andi a0, a0, 1 +80000978: 63 12 05 1c bnez a0, 452 +8000097c: 6f 00 40 00 j 4 +80000980: 93 8a 84 00 addi s5, s1, 8 +80000984: 13 8b c4 00 addi s6, s1, 12 +80000988: 93 8b 44 00 addi s7, s1, 4 +8000098c: 13 05 c1 00 addi a0, sp, 12 +80000990: 13 8c 84 01 addi s8, s1, 24 +80000994: 93 8c 04 01 addi s9, s1, 16 +80000998: 63 98 06 00 bnez a3, 16 +8000099c: 6f 00 40 00 j 4 +800009a0: 93 0d 00 00 mv s11, zero +800009a4: 6f 00 c0 02 j 44 +800009a8: 23 00 4d 01 sb s4, 0(s10) +800009ac: 83 55 09 00 lhu a1, 0(s2) +800009b0: 13 85 04 00 mv a0, s1 +800009b4: 97 00 00 00 auipc ra, 0 +800009b8: e7 80 40 ac jalr -1340(ra) +800009bc: 13 05 10 00 addi a0, zero, 1 +800009c0: 63 8a a9 16 beq s3, a0, 372 +800009c4: 6f 00 40 00 j 4 +800009c8: 13 04 10 00 addi s0, zero, 1 +800009cc: 6f 00 80 1b j 440 +800009d0: 23 00 4d 01 sb s4, 0(s10) +800009d4: 63 8a 0d 02 beqz s11, 52 +800009d8: 6f 00 40 00 j 4 +800009dc: 03 a5 0a 00 lw a0, 0(s5) +800009e0: 83 25 0b 00 lw a1, 0(s6) +800009e4: 63 72 b5 02 bgeu a0, a1, 36 +800009e8: 6f 00 40 00 j 4 +800009ec: 83 a5 0b 00 lw a1, 0(s7) +800009f0: 13 06 15 00 addi a2, a0, 1 +800009f4: 23 a0 ca 00 sw a2, 0(s5) +800009f8: 33 85 a5 00 add a0, a1, a0 +800009fc: 93 05 c0 02 addi a1, zero, 44 +80000a00: 23 00 b5 00 sb a1, 0(a0) +80000a04: 6f 00 40 00 j 4 +80000a08: 13 95 1d 00 slli a0, s11, 1 +80000a0c: 33 05 a9 00 add a0, s2, a0 +80000a10: 03 15 05 00 lh a0, 0(a0) +80000a14: 63 46 05 02 bltz a0, 44 +80000a18: 6f 00 40 00 j 4 +80000a1c: 83 45 0d 00 lbu a1, 0(s10) +80000a20: 93 f5 f5 0d andi a1, a1, 223 +80000a24: 23 00 bd 00 sb a1, 0(s10) +80000a28: b7 05 01 00 lui a1, 16 +80000a2c: 93 85 f5 ff addi a1, a1, -1 +80000a30: 33 76 b5 00 and a2, a0, a1 +80000a34: 93 05 00 00 mv a1, zero +80000a38: 63 0e 06 04 beqz a2, 92 +80000a3c: 6f 00 80 01 j 24 +80000a40: 33 05 a0 40 neg a0, a0 +80000a44: 83 05 0d 00 lb a1, 0(s10) +80000a48: 93 e5 05 02 ori a1, a1, 32 +80000a4c: 23 00 bd 00 sb a1, 0(s10) +80000a50: 6f 00 40 00 j 4 +80000a54: 03 26 0c 00 lw a2, 0(s8) +80000a58: 93 05 00 00 mv a1, zero +80000a5c: 6f 00 40 00 j 4 +80000a60: 93 86 05 00 mv a3, a1 +80000a64: 13 07 05 00 mv a4, a0 +80000a68: 33 55 c7 02 divu a0, a4, a2 +80000a6c: b3 05 c5 02 mul a1, a0, a2 +80000a70: b3 05 b7 40 sub a1, a4, a1 +80000a74: 93 87 05 03 addi a5, a1, 48 +80000a78: 93 85 16 00 addi a1, a3, 1 +80000a7c: 13 04 c1 00 addi s0, sp, 12 +80000a80: b3 06 d4 00 add a3, s0, a3 +80000a84: 23 80 f6 00 sb a5, 0(a3) +80000a88: e3 7c c7 fc bgeu a4, a2, -40 +80000a8c: 6f 00 40 00 j 4 +80000a90: 6f 00 40 00 j 4 +80000a94: 03 a5 0c 00 lw a0, 0(s9) +80000a98: 13 06 10 00 addi a2, zero, 1 +80000a9c: 63 56 c5 00 bge a0, a2, 12 +80000aa0: 13 85 05 00 mv a0, a1 +80000aa4: 6f 00 40 03 j 52 +80000aa8: 63 e6 a5 00 bltu a1, a0, 12 +80000aac: 13 85 05 00 mv a0, a1 +80000ab0: 6f 00 80 02 j 40 +80000ab4: 6f 00 40 00 j 4 +80000ab8: 13 06 c1 00 addi a2, sp, 12 +80000abc: 33 06 b6 00 add a2, a2, a1 +80000ac0: 93 06 00 03 addi a3, zero, 48 +80000ac4: 23 00 d6 00 sb a3, 0(a2) +80000ac8: 93 85 15 00 addi a1, a1, 1 +80000acc: e3 96 a5 fe bne a1, a0, -20 +80000ad0: 6f 00 40 00 j 4 +80000ad4: 6f 00 40 00 j 4 +80000ad8: 83 a5 04 00 lw a1, 0(s1) +80000adc: 63 14 05 00 bnez a0, 8 +80000ae0: 6f 00 00 03 j 48 +80000ae4: 6f 00 40 00 j 4 +80000ae8: 13 86 05 00 mv a2, a1 +80000aec: 13 05 f5 ff addi a0, a0, -1 +80000af0: 93 05 c1 00 addi a1, sp, 12 +80000af4: b3 85 a5 00 add a1, a1, a0 +80000af8: 83 86 05 00 lb a3, 0(a1) +80000afc: 93 05 16 00 addi a1, a2, 1 +80000b00: 23 00 d6 00 sb a3, 0(a2) +80000b04: e3 12 05 fe bnez a0, -28 +80000b08: 6f 00 40 00 j 4 +80000b0c: 6f 00 40 00 j 4 +80000b10: 23 80 05 00 sb zero, 0(a1) +80000b14: 13 85 04 00 mv a0, s1 +80000b18: 97 f0 ff ff auipc ra, 1048575 +80000b1c: e7 80 00 58 jalr 1408(ra) +80000b20: 93 8d 1d 00 addi s11, s11, 1 +80000b24: e3 96 3d eb bne s11, s3, -340 +80000b28: 6f 00 40 00 j 4 +80000b2c: 6f 00 c0 00 j 12 +80000b30: 6f 00 40 00 j 4 +80000b34: 6f 00 c0 00 j 12 +80000b38: 6f 00 80 00 j 8 +80000b3c: 6f 00 80 00 j 8 +80000b40: 6f 00 80 00 j 8 +80000b44: 6f 00 40 00 j 4 +80000b48: 83 2d c1 04 lw s11, 76(sp) +80000b4c: 03 2d 01 05 lw s10, 80(sp) +80000b50: 83 2c 41 05 lw s9, 84(sp) +80000b54: 03 2c 81 05 lw s8, 88(sp) +80000b58: 83 2b c1 05 lw s7, 92(sp) +80000b5c: 03 2b 01 06 lw s6, 96(sp) +80000b60: 83 2a 41 06 lw s5, 100(sp) +80000b64: 03 2a 81 06 lw s4, 104(sp) +80000b68: 83 29 c1 06 lw s3, 108(sp) +80000b6c: 03 29 01 07 lw s2, 112(sp) +80000b70: 83 24 41 07 lw s1, 116(sp) +80000b74: 03 24 81 07 lw s0, 120(sp) +80000b78: 83 20 c1 07 lw ra, 124(sp) +80000b7c: 13 01 01 08 addi sp, sp, 128 +80000b80: 67 80 00 00 ret +80000b84: 23 00 4d 01 sb s4, 0(s10) +80000b88: 03 a5 0a 00 lw a0, 0(s5) +80000b8c: 83 25 0b 00 lw a1, 0(s6) +80000b90: 63 72 b5 02 bgeu a0, a1, 36 +80000b94: 6f 00 40 00 j 4 +80000b98: 83 a5 0b 00 lw a1, 0(s7) +80000b9c: 13 06 15 00 addi a2, a0, 1 +80000ba0: 23 a0 ca 00 sw a2, 0(s5) +80000ba4: 33 85 a5 00 add a0, a1, a0 +80000ba8: 93 05 c0 02 addi a1, zero, 44 +80000bac: 23 00 b5 00 sb a1, 0(a0) +80000bb0: 6f 00 40 00 j 4 +80000bb4: 13 15 14 00 slli a0, s0, 1 +80000bb8: 33 05 a9 00 add a0, s2, a0 +80000bbc: 83 55 05 00 lhu a1, 0(a0) +80000bc0: 13 85 04 00 mv a0, s1 +80000bc4: 97 00 00 00 auipc ra, 0 +80000bc8: e7 80 40 8b jalr -1868(ra) +80000bcc: 13 04 14 00 addi s0, s0, 1 +80000bd0: e3 00 34 f7 beq s0, s3, -160 +80000bd4: 6f f0 1f fb j -80 + +80000bd8 __pocl_print_ints_uint: +80000bd8: 13 01 01 f8 addi sp, sp, -128 +80000bdc: 23 2e 11 06 sw ra, 124(sp) +80000be0: 23 2c 81 06 sw s0, 120(sp) +80000be4: 23 2a 91 06 sw s1, 116(sp) +80000be8: 23 28 21 07 sw s2, 112(sp) +80000bec: 23 26 31 07 sw s3, 108(sp) +80000bf0: 23 24 41 07 sw s4, 104(sp) +80000bf4: 23 22 51 07 sw s5, 100(sp) +80000bf8: 23 20 61 07 sw s6, 96(sp) +80000bfc: 23 2e 71 05 sw s7, 92(sp) +80000c00: 23 2c 81 05 sw s8, 88(sp) +80000c04: 23 2a 91 05 sw s9, 84(sp) +80000c08: 23 28 a1 05 sw s10, 80(sp) +80000c0c: 23 26 b1 05 sw s11, 76(sp) +80000c10: 93 09 06 00 mv s3, a2 +80000c14: 13 89 05 00 mv s2, a1 +80000c18: 93 04 05 00 mv s1, a0 +80000c1c: 13 8d c4 01 addi s10, s1, 28 +80000c20: 03 ca c4 01 lbu s4, 28(s1) +80000c24: 13 b5 19 00 seqz a0, s3 +80000c28: 6f 00 40 00 j 4 +80000c2c: 13 75 15 00 andi a0, a0, 1 +80000c30: 63 1c 05 1a bnez a0, 440 +80000c34: 6f 00 40 00 j 4 +80000c38: 93 8a 84 00 addi s5, s1, 8 +80000c3c: 13 8b c4 00 addi s6, s1, 12 +80000c40: 93 8b 44 00 addi s7, s1, 4 +80000c44: 13 05 c1 00 addi a0, sp, 12 +80000c48: 13 8c 84 01 addi s8, s1, 24 +80000c4c: 93 8c 04 01 addi s9, s1, 16 +80000c50: 63 98 06 00 bnez a3, 16 +80000c54: 6f 00 40 00 j 4 +80000c58: 93 0d 00 00 mv s11, zero +80000c5c: 6f 00 c0 02 j 44 +80000c60: 23 00 4d 01 sb s4, 0(s10) +80000c64: 83 25 09 00 lw a1, 0(s2) +80000c68: 13 85 04 00 mv a0, s1 +80000c6c: 97 00 00 00 auipc ra, 0 +80000c70: e7 80 c0 80 jalr -2036(ra) +80000c74: 13 05 10 00 addi a0, zero, 1 +80000c78: 63 84 a9 16 beq s3, a0, 360 +80000c7c: 6f 00 40 00 j 4 +80000c80: 13 04 10 00 addi s0, zero, 1 +80000c84: 6f 00 c0 1a j 428 +80000c88: 23 00 4d 01 sb s4, 0(s10) +80000c8c: 63 8a 0d 02 beqz s11, 52 +80000c90: 6f 00 40 00 j 4 +80000c94: 03 a5 0a 00 lw a0, 0(s5) +80000c98: 83 25 0b 00 lw a1, 0(s6) +80000c9c: 63 72 b5 02 bgeu a0, a1, 36 +80000ca0: 6f 00 40 00 j 4 +80000ca4: 83 a5 0b 00 lw a1, 0(s7) +80000ca8: 13 06 15 00 addi a2, a0, 1 +80000cac: 23 a0 ca 00 sw a2, 0(s5) +80000cb0: 33 85 a5 00 add a0, a1, a0 +80000cb4: 93 05 c0 02 addi a1, zero, 44 +80000cb8: 23 00 b5 00 sb a1, 0(a0) +80000cbc: 6f 00 40 00 j 4 +80000cc0: 13 95 2d 00 slli a0, s11, 2 +80000cc4: 33 05 a9 00 add a0, s2, a0 +80000cc8: 03 25 05 00 lw a0, 0(a0) +80000ccc: 63 40 05 02 bltz a0, 32 +80000cd0: 6f 00 40 00 j 4 +80000cd4: 83 45 0d 00 lbu a1, 0(s10) +80000cd8: 93 f5 f5 0d andi a1, a1, 223 +80000cdc: 23 00 bd 00 sb a1, 0(s10) +80000ce0: 93 05 00 00 mv a1, zero +80000ce4: 63 0e 05 04 beqz a0, 92 +80000ce8: 6f 00 80 01 j 24 +80000cec: 33 05 a0 40 neg a0, a0 +80000cf0: 83 05 0d 00 lb a1, 0(s10) +80000cf4: 93 e5 05 02 ori a1, a1, 32 +80000cf8: 23 00 bd 00 sb a1, 0(s10) +80000cfc: 6f 00 40 00 j 4 +80000d00: 03 26 0c 00 lw a2, 0(s8) +80000d04: 93 05 00 00 mv a1, zero +80000d08: 6f 00 40 00 j 4 +80000d0c: 93 86 05 00 mv a3, a1 +80000d10: 13 07 05 00 mv a4, a0 +80000d14: 33 55 c7 02 divu a0, a4, a2 +80000d18: b3 05 c5 02 mul a1, a0, a2 +80000d1c: b3 05 b7 40 sub a1, a4, a1 +80000d20: 93 87 05 03 addi a5, a1, 48 +80000d24: 93 85 16 00 addi a1, a3, 1 +80000d28: 13 04 c1 00 addi s0, sp, 12 +80000d2c: b3 06 d4 00 add a3, s0, a3 +80000d30: 23 80 f6 00 sb a5, 0(a3) +80000d34: e3 7c c7 fc bgeu a4, a2, -40 +80000d38: 6f 00 40 00 j 4 +80000d3c: 6f 00 40 00 j 4 +80000d40: 03 a5 0c 00 lw a0, 0(s9) +80000d44: 13 06 10 00 addi a2, zero, 1 +80000d48: 63 56 c5 00 bge a0, a2, 12 +80000d4c: 13 85 05 00 mv a0, a1 +80000d50: 6f 00 40 03 j 52 +80000d54: 63 e6 a5 00 bltu a1, a0, 12 +80000d58: 13 85 05 00 mv a0, a1 +80000d5c: 6f 00 80 02 j 40 +80000d60: 6f 00 40 00 j 4 +80000d64: 13 06 c1 00 addi a2, sp, 12 +80000d68: 33 06 b6 00 add a2, a2, a1 +80000d6c: 93 06 00 03 addi a3, zero, 48 +80000d70: 23 00 d6 00 sb a3, 0(a2) +80000d74: 93 85 15 00 addi a1, a1, 1 +80000d78: e3 96 a5 fe bne a1, a0, -20 +80000d7c: 6f 00 40 00 j 4 +80000d80: 6f 00 40 00 j 4 +80000d84: 83 a5 04 00 lw a1, 0(s1) +80000d88: 63 14 05 00 bnez a0, 8 +80000d8c: 6f 00 00 03 j 48 +80000d90: 6f 00 40 00 j 4 +80000d94: 13 86 05 00 mv a2, a1 +80000d98: 13 05 f5 ff addi a0, a0, -1 +80000d9c: 93 05 c1 00 addi a1, sp, 12 +80000da0: b3 85 a5 00 add a1, a1, a0 +80000da4: 83 86 05 00 lb a3, 0(a1) +80000da8: 93 05 16 00 addi a1, a2, 1 +80000dac: 23 00 d6 00 sb a3, 0(a2) +80000db0: e3 12 05 fe bnez a0, -28 +80000db4: 6f 00 40 00 j 4 +80000db8: 6f 00 40 00 j 4 +80000dbc: 23 80 05 00 sb zero, 0(a1) +80000dc0: 13 85 04 00 mv a0, s1 +80000dc4: 97 f0 ff ff auipc ra, 1048575 +80000dc8: e7 80 40 2d jalr 724(ra) +80000dcc: 93 8d 1d 00 addi s11, s11, 1 +80000dd0: e3 9c 3d eb bne s11, s3, -328 +80000dd4: 6f 00 40 00 j 4 +80000dd8: 6f 00 c0 00 j 12 +80000ddc: 6f 00 40 00 j 4 +80000de0: 6f 00 c0 00 j 12 +80000de4: 6f 00 80 00 j 8 +80000de8: 6f 00 80 00 j 8 +80000dec: 6f 00 80 00 j 8 +80000df0: 6f 00 40 00 j 4 +80000df4: 83 2d c1 04 lw s11, 76(sp) +80000df8: 03 2d 01 05 lw s10, 80(sp) +80000dfc: 83 2c 41 05 lw s9, 84(sp) +80000e00: 03 2c 81 05 lw s8, 88(sp) +80000e04: 83 2b c1 05 lw s7, 92(sp) +80000e08: 03 2b 01 06 lw s6, 96(sp) +80000e0c: 83 2a 41 06 lw s5, 100(sp) +80000e10: 03 2a 81 06 lw s4, 104(sp) +80000e14: 83 29 c1 06 lw s3, 108(sp) +80000e18: 03 29 01 07 lw s2, 112(sp) +80000e1c: 83 24 41 07 lw s1, 116(sp) +80000e20: 03 24 81 07 lw s0, 120(sp) +80000e24: 83 20 c1 07 lw ra, 124(sp) +80000e28: 13 01 01 08 addi sp, sp, 128 +80000e2c: 67 80 00 00 ret +80000e30: 23 00 4d 01 sb s4, 0(s10) +80000e34: 03 a5 0a 00 lw a0, 0(s5) +80000e38: 83 25 0b 00 lw a1, 0(s6) +80000e3c: 63 72 b5 02 bgeu a0, a1, 36 +80000e40: 6f 00 40 00 j 4 +80000e44: 83 a5 0b 00 lw a1, 0(s7) +80000e48: 13 06 15 00 addi a2, a0, 1 +80000e4c: 23 a0 ca 00 sw a2, 0(s5) +80000e50: 33 85 a5 00 add a0, a1, a0 +80000e54: 93 05 c0 02 addi a1, zero, 44 +80000e58: 23 00 b5 00 sb a1, 0(a0) +80000e5c: 6f 00 40 00 j 4 +80000e60: 13 15 24 00 slli a0, s0, 2 +80000e64: 33 05 a9 00 add a0, s2, a0 +80000e68: 83 25 05 00 lw a1, 0(a0) +80000e6c: 13 85 04 00 mv a0, s1 +80000e70: 97 f0 ff ff auipc ra, 1048575 +80000e74: e7 80 80 60 jalr 1544(ra) +80000e78: 13 04 14 00 addi s0, s0, 1 +80000e7c: e3 00 34 f7 beq s0, s3, -160 +80000e80: 6f f0 1f fb j -80 + +80000e84 __pocl_printf_float_libc: +80000e84: 13 01 01 f3 addi sp, sp, -208 +80000e88: 23 26 11 0c sw ra, 204(sp) +80000e8c: 23 24 81 0c sw s0, 200(sp) +80000e90: 23 22 91 0c sw s1, 196(sp) +80000e94: 23 20 21 0d sw s2, 192(sp) +80000e98: 23 2e 31 0b sw s3, 188(sp) +80000e9c: 27 2c 81 0a fsw fs0, 184(sp) +80000ea0: 53 04 a5 20 fmv.s fs0, fa0 +80000ea4: 93 09 05 00 mv s3, a0 +80000ea8: 13 09 81 03 addi s2, sp, 56 +80000eac: 83 82 d9 01 lb t0, 29(s3) +80000eb0: 83 c4 c9 01 lbu s1, 28(s3) +80000eb4: 93 f5 84 00 andi a1, s1, 8 +80000eb8: 13 85 02 fe addi a0, t0, -32 +80000ebc: 63 84 05 00 beqz a1, 8 +80000ec0: 93 02 05 00 mv t0, a0 +80000ec4: 03 a3 09 01 lw t1, 16(s3) +80000ec8: 13 06 c1 01 addi a2, sp, 28 +80000ecc: 23 0a 01 02 sb zero, 52(sp) +80000ed0: 37 65 25 63 lui a0, 406102 +80000ed4: 13 05 05 43 addi a0, a0, 1072 +80000ed8: 23 28 a1 02 sw a0, 48(sp) +80000edc: 37 75 25 2e lui a0, 189015 +80000ee0: 13 05 55 32 addi a0, a0, 805 +80000ee4: 23 26 a1 02 sw a0, 44(sp) +80000ee8: 37 35 30 64 lui a0, 410371 +80000eec: 13 05 55 e2 addi a0, a0, -475 +80000ef0: 23 24 a1 02 sw a0, 40(sp) +80000ef4: 37 75 25 73 lui a0, 471639 +80000ef8: 13 05 55 32 addi a0, a0, 805 +80000efc: 23 22 a1 02 sw a0, 36(sp) +80000f00: 23 20 a1 02 sw a0, 32(sp) +80000f04: 37 25 25 73 lui a0, 471634 +80000f08: 13 05 55 52 addi a0, a0, 1317 +80000f0c: 23 2e a1 00 sw a0, 28(sp) +80000f10: 13 f7 44 00 andi a4, s1, 4 +80000f14: 37 55 01 80 lui a0, 524309 +80000f18: 93 05 b5 57 addi a1, a0, 1403 +80000f1c: 37 55 01 80 lui a0, 524309 +80000f20: 13 05 15 53 addi a0, a0, 1329 +80000f24: 93 06 05 00 mv a3, a0 +80000f28: 63 04 07 00 beqz a4, 8 +80000f2c: 93 86 05 00 mv a3, a1 +80000f30: 93 f7 04 01 andi a5, s1, 16 +80000f34: b7 55 01 80 lui a1, 524309 +80000f38: 93 85 d5 57 addi a1, a1, 1405 +80000f3c: 13 07 05 00 mv a4, a0 +80000f40: 63 84 07 00 beqz a5, 8 +80000f44: 13 87 05 00 mv a4, a1 +80000f48: 93 f5 04 04 andi a1, s1, 64 +80000f4c: b7 57 01 80 lui a5, 524309 +80000f50: 13 88 f7 57 addi a6, a5, 1407 +80000f54: 93 07 05 00 mv a5, a0 +80000f58: 63 84 05 00 beqz a1, 8 +80000f5c: 93 07 08 00 mv a5, a6 +80000f60: 93 f5 24 00 andi a1, s1, 2 +80000f64: 37 54 01 80 lui s0, 524309 +80000f68: 93 08 14 58 addi a7, s0, 1409 +80000f6c: 13 08 05 00 mv a6, a0 +80000f70: 63 84 05 00 beqz a1, 8 +80000f74: 13 88 08 00 mv a6, a7 +80000f78: 93 f4 14 00 andi s1, s1, 1 +80000f7c: b7 55 01 80 lui a1, 524309 +80000f80: 93 85 35 58 addi a1, a1, 1411 +80000f84: 93 08 05 00 mv a7, a0 +80000f88: 63 84 04 00 beqz s1, 8 +80000f8c: 93 88 05 00 mv a7, a1 +80000f90: 83 a4 49 01 lw s1, 20(s3) +80000f94: b7 55 01 80 lui a1, 524309 +80000f98: 93 85 55 58 addi a1, a1, 1413 +80000f9c: 13 04 f0 ff addi s0, zero, -1 +80000fa0: 63 16 83 00 bne t1, s0, 12 +80000fa4: 93 05 05 00 mv a1, a0 +80000fa8: 13 03 00 00 mv t1, zero +80000fac: 13 f5 f2 0f andi a0, t0, 255 +80000fb0: 23 26 a1 00 sw a0, 12(sp) +80000fb4: 23 24 61 00 sw t1, 8(sp) +80000fb8: 23 22 b1 00 sw a1, 4(sp) +80000fbc: 23 20 91 00 sw s1, 0(sp) +80000fc0: 13 05 09 00 mv a0, s2 +80000fc4: 93 05 00 08 addi a1, zero, 128 +80000fc8: 97 20 00 00 auipc ra, 2 +80000fcc: e7 80 80 69 jalr 1688(ra) +80000fd0: 83 a4 09 00 lw s1, 0(s3) +80000fd4: 53 05 84 20 fmv.s fa0, fs0 +80000fd8: 97 40 01 00 auipc ra, 20 +80000fdc: e7 80 00 ce jalr -800(ra) +80000fe0: 13 07 05 00 mv a4, a0 +80000fe4: 93 87 05 00 mv a5, a1 +80000fe8: 13 85 04 00 mv a0, s1 +80000fec: 93 05 00 4b addi a1, zero, 1200 +80000ff0: 13 06 09 00 mv a2, s2 +80000ff4: 97 20 00 00 auipc ra, 2 +80000ff8: e7 80 c0 66 jalr 1644(ra) +80000ffc: 03 a5 09 00 lw a0, 0(s3) +80001000: a3 07 05 4a sb zero, 1199(a0) +80001004: 03 a5 09 00 lw a0, 0(s3) +80001008: 83 45 05 00 lbu a1, 0(a0) +8000100c: 13 b6 15 00 seqz a2, a1 +80001010: 6f 00 40 00 j 4 +80001014: 13 76 16 00 andi a2, a2, 1 +80001018: 63 1a 06 04 bnez a2, 84 +8000101c: 6f 00 40 00 j 4 +80001020: 13 86 89 00 addi a2, s3, 8 +80001024: 93 86 c9 00 addi a3, s3, 12 +80001028: 13 87 49 00 addi a4, s3, 4 +8000102c: 6f 00 40 00 j 4 +80001030: 13 05 15 00 addi a0, a0, 1 +80001034: 83 27 06 00 lw a5, 0(a2) +80001038: 83 a4 06 00 lw s1, 0(a3) +8000103c: 63 f0 97 02 bgeu a5, s1, 32 +80001040: 6f 00 40 00 j 4 +80001044: 83 24 07 00 lw s1, 0(a4) +80001048: 13 84 17 00 addi s0, a5, 1 +8000104c: 23 20 86 00 sw s0, 0(a2) +80001050: b3 87 f4 00 add a5, s1, a5 +80001054: 23 80 b7 00 sb a1, 0(a5) +80001058: 6f 00 40 00 j 4 +8000105c: 83 45 05 00 lbu a1, 0(a0) +80001060: e3 98 05 fc bnez a1, -48 +80001064: 6f 00 40 00 j 4 +80001068: 6f 00 40 00 j 4 +8000106c: 6f 00 40 00 j 4 +80001070: 07 24 81 0b flw fs0, 184(sp) +80001074: 83 29 c1 0b lw s3, 188(sp) +80001078: 03 29 01 0c lw s2, 192(sp) +8000107c: 83 24 41 0c lw s1, 196(sp) +80001080: 03 24 81 0c lw s0, 200(sp) +80001084: 83 20 c1 0c lw ra, 204(sp) +80001088: 13 01 01 0d addi sp, sp, 208 +8000108c: 67 80 00 00 ret + +80001090 __pocl_print_floats_float: +80001090: 13 01 01 fd addi sp, sp, -48 +80001094: 23 26 11 02 sw ra, 44(sp) +80001098: 23 24 81 02 sw s0, 40(sp) +8000109c: 23 22 91 02 sw s1, 36(sp) +800010a0: 23 20 21 03 sw s2, 32(sp) +800010a4: 23 2e 31 01 sw s3, 28(sp) +800010a8: 23 2c 41 01 sw s4, 24(sp) +800010ac: 23 2a 51 01 sw s5, 20(sp) +800010b0: 23 28 61 01 sw s6, 16(sp) +800010b4: 23 26 71 01 sw s7, 12(sp) +800010b8: 23 24 81 01 sw s8, 8(sp) +800010bc: 93 09 06 00 mv s3, a2 +800010c0: 13 89 05 00 mv s2, a1 +800010c4: 93 04 05 00 mv s1, a0 +800010c8: 13 8c c4 01 addi s8, s1, 28 +800010cc: 03 ca c4 01 lbu s4, 28(s1) +800010d0: 33 25 30 01 sgtz a0, s3 +800010d4: 6f 00 40 00 j 4 +800010d8: 13 75 15 00 andi a0, a0, 1 +800010dc: 63 00 05 02 beqz a0, 32 +800010e0: 6f 00 40 00 j 4 +800010e4: 93 8a 84 00 addi s5, s1, 8 +800010e8: 13 8b c4 00 addi s6, s1, 12 +800010ec: 93 8b 44 00 addi s7, s1, 4 +800010f0: 13 04 00 00 mv s0, zero +800010f4: 6f 00 c0 03 j 60 +800010f8: 6f 00 40 00 j 4 +800010fc: 6f 00 40 00 j 4 +80001100: 03 2c 81 00 lw s8, 8(sp) +80001104: 83 2b c1 00 lw s7, 12(sp) +80001108: 03 2b 01 01 lw s6, 16(sp) +8000110c: 83 2a 41 01 lw s5, 20(sp) +80001110: 03 2a 81 01 lw s4, 24(sp) +80001114: 83 29 c1 01 lw s3, 28(sp) +80001118: 03 29 01 02 lw s2, 32(sp) +8000111c: 83 24 41 02 lw s1, 36(sp) +80001120: 03 24 81 02 lw s0, 40(sp) +80001124: 83 20 c1 02 lw ra, 44(sp) +80001128: 13 01 01 03 addi sp, sp, 48 +8000112c: 67 80 00 00 ret +80001130: 23 00 4c 01 sb s4, 0(s8) +80001134: 63 0a 04 02 beqz s0, 52 +80001138: 6f 00 40 00 j 4 +8000113c: 03 a5 0a 00 lw a0, 0(s5) +80001140: 83 25 0b 00 lw a1, 0(s6) +80001144: 63 72 b5 02 bgeu a0, a1, 36 +80001148: 6f 00 40 00 j 4 +8000114c: 83 a5 0b 00 lw a1, 0(s7) +80001150: 13 06 15 00 addi a2, a0, 1 +80001154: 23 a0 ca 00 sw a2, 0(s5) +80001158: 33 85 a5 00 add a0, a1, a0 +8000115c: 93 05 c0 02 addi a1, zero, 44 +80001160: 23 00 b5 00 sb a1, 0(a0) +80001164: 6f 00 40 00 j 4 +80001168: 13 15 24 00 slli a0, s0, 2 +8000116c: 33 05 a9 00 add a0, s2, a0 +80001170: 07 25 05 00 flw fa0, 0(a0) +80001174: 53 25 a5 a0 feq.s a0, fa0, fa0 +80001178: b3 75 a5 00 and a1, a0, a0 +8000117c: 13 05 00 00 mv a0, zero +80001180: 63 94 05 02 bnez a1, 40 +80001184: 6f 00 40 00 j 4 +80001188: 03 45 0c 00 lbu a0, 0(s8) +8000118c: b7 55 01 80 lui a1, 524309 +80001190: 93 85 85 58 addi a1, a1, 1416 +80001194: 13 55 15 00 srli a0, a0, 1 +80001198: 13 75 45 00 andi a0, a0, 4 +8000119c: 33 05 b5 00 add a0, a0, a1 +800011a0: 03 25 05 00 lw a0, 0(a0) +800011a4: 6f 00 40 00 j 4 +800011a8: b7 85 01 80 lui a1, 524312 +800011ac: 93 85 45 b9 addi a1, a1, -1132 +800011b0: 07 a0 05 00 flw ft0, 0(a1) +800011b4: d3 25 05 a0 feq.s a1, fa0, ft0 +800011b8: 93 c5 15 00 xori a1, a1, 1 +800011bc: 63 9c 05 00 bnez a1, 24 +800011c0: 6f 00 40 00 j 4 +800011c4: 03 05 0c 00 lb a0, 0(s8) +800011c8: 13 65 05 02 ori a0, a0, 32 +800011cc: 23 00 ac 00 sb a0, 0(s8) +800011d0: 6f 00 80 02 j 40 +800011d4: b7 85 01 80 lui a1, 524312 +800011d8: 93 85 85 b9 addi a1, a1, -1128 +800011dc: 07 a0 05 00 flw ft0, 0(a1) +800011e0: d3 25 05 a0 feq.s a1, fa0, ft0 +800011e4: 93 c5 15 00 xori a1, a1, 1 +800011e8: 63 9c 05 02 bnez a1, 56 +800011ec: 6f 00 40 00 j 4 +800011f0: 03 45 0c 00 lbu a0, 0(s8) +800011f4: 6f 00 40 00 j 4 +800011f8: b7 55 01 80 lui a1, 524309 +800011fc: 93 85 05 59 addi a1, a1, 1424 +80001200: 13 55 15 00 srli a0, a0, 1 +80001204: 13 75 45 00 andi a0, a0, 4 +80001208: 33 05 b5 00 add a0, a0, a1 +8000120c: 03 25 05 00 lw a0, 0(a0) +80001210: b7 85 01 80 lui a1, 524312 +80001214: 93 85 85 b9 addi a1, a1, -1128 +80001218: 07 a5 05 00 flw fa0, 0(a1) +8000121c: 6f 00 40 00 j 4 +80001220: 63 00 05 06 beqz a0, 96 +80001224: 6f 00 40 00 j 4 +80001228: 83 a5 04 00 lw a1, 0(s1) +8000122c: 03 46 05 00 lbu a2, 0(a0) +80001230: 63 14 06 00 bnez a2, 8 +80001234: 6f 00 c0 02 j 44 +80001238: 6f 00 40 00 j 4 +8000123c: 93 86 05 00 mv a3, a1 +80001240: 13 07 15 00 addi a4, a0, 1 +80001244: 93 85 16 00 addi a1, a3, 1 +80001248: 23 80 c6 00 sb a2, 0(a3) +8000124c: 03 46 15 00 lbu a2, 1(a0) +80001250: 13 05 07 00 mv a0, a4 +80001254: e3 14 06 fe bnez a2, -24 +80001258: 6f 00 40 00 j 4 +8000125c: 6f 00 40 00 j 4 +80001260: 23 80 05 00 sb zero, 0(a1) +80001264: 03 45 0c 00 lbu a0, 0(s8) +80001268: 13 75 e5 0f andi a0, a0, 254 +8000126c: 23 00 ac 00 sb a0, 0(s8) +80001270: 13 85 04 00 mv a0, s1 +80001274: 97 f0 ff ff auipc ra, 1048575 +80001278: e7 80 40 e2 jalr -476(ra) +8000127c: 6f 00 40 01 j 20 +80001280: 13 85 04 00 mv a0, s1 +80001284: 97 00 00 00 auipc ra, 0 +80001288: e7 80 00 c0 jalr -1024(ra) +8000128c: 6f 00 40 00 j 4 +80001290: 13 04 14 00 addi s0, s0, 1 +80001294: e3 02 34 e7 beq s0, s3, -412 +80001298: 6f f0 9f e9 j -360 + +8000129c __pocl_printf_format_full: +8000129c: 13 01 01 98 addi sp, sp, -1664 +800012a0: 23 2e 11 66 sw ra, 1660(sp) +800012a4: 23 2c 81 66 sw s0, 1656(sp) +800012a8: 23 2a 91 66 sw s1, 1652(sp) +800012ac: 23 28 21 67 sw s2, 1648(sp) +800012b0: 23 26 31 67 sw s3, 1644(sp) +800012b4: 23 24 41 67 sw s4, 1640(sp) +800012b8: 23 22 51 67 sw s5, 1636(sp) +800012bc: 23 20 61 67 sw s6, 1632(sp) +800012c0: 23 2e 71 65 sw s7, 1628(sp) +800012c4: 23 2c 81 65 sw s8, 1624(sp) +800012c8: 23 2a 91 65 sw s9, 1620(sp) +800012cc: 23 28 a1 65 sw s10, 1616(sp) +800012d0: 23 26 b1 65 sw s11, 1612(sp) +800012d4: 13 04 01 68 addi s0, sp, 1664 +800012d8: 13 71 01 fc andi sp, sp, -64 +800012dc: 93 04 05 00 mv s1, a0 +800012e0: 93 03 c1 15 addi t2, sp, 348 +800012e4: 23 a0 74 00 sw t2, 0(s1) +800012e8: 13 8d c4 01 addi s10, s1, 28 +800012ec: 93 8d d4 01 addi s11, s1, 29 +800012f0: 93 89 44 01 addi s3, s1, 20 +800012f4: 13 8a 04 01 addi s4, s1, 16 +800012f8: 13 89 84 01 addi s2, s1, 24 +800012fc: 13 0e 01 0c addi t3, sp, 192 +80001300: 93 0e 01 12 addi t4, sp, 288 +80001304: 13 0f 01 14 addi t5, sp, 320 +80001308: 93 0f 01 08 addi t6, sp, 128 +8000130c: 93 00 d1 15 addi ra, sp, 349 +80001310: 13 8b 84 00 addi s6, s1, 8 +80001314: 13 8c c4 00 addi s8, s1, 12 +80001318: 93 8b 44 00 addi s7, s1, 4 +8000131c: 37 55 01 80 lui a0, 524309 +80001320: 93 0c 85 51 addi s9, a0, 1304 +80001324: 13 05 c1 60 addi a0, sp, 1548 +80001328: 6f 00 40 00 j 4 +8000132c: 6f 00 40 00 j 4 +80001330: 93 86 1c 00 addi a3, s9, 1 +80001334: 03 85 0c 00 lb a0, 0(s9) +80001338: 6f 00 40 00 j 4 +8000133c: 13 16 85 01 slli a2, a0, 24 +80001340: 13 56 86 41 srai a2, a2, 24 +80001344: 13 07 50 02 addi a4, zero, 37 +80001348: 63 4c e6 00 blt a2, a4, 24 +8000134c: 6f 00 40 00 j 4 +80001350: 13 76 f5 0f andi a2, a0, 255 +80001354: 13 07 50 02 addi a4, zero, 37 +80001358: 63 0c e6 00 beq a2, a4, 24 +8000135c: 6f 10 40 31 j 4884 +80001360: 13 76 f5 0f andi a2, a0, 255 +80001364: 63 14 06 00 bnez a2, 8 +80001368: 6f 10 40 47 j 5236 +8000136c: 6f 10 40 30 j 4868 +80001370: 13 86 2c 00 addi a2, s9, 2 +80001374: 03 87 06 00 lb a4, 0(a3) +80001378: 6f 00 40 00 j 4 +8000137c: 93 16 87 01 slli a3, a4, 24 +80001380: 93 d6 86 41 srai a3, a3, 24 +80001384: 93 07 50 02 addi a5, zero, 37 +80001388: 63 ce f6 00 blt a3, a5, 28 +8000138c: 6f 00 40 00 j 4 +80001390: 93 76 f7 0f andi a3, a4, 255 +80001394: 93 07 50 02 addi a5, zero, 37 +80001398: 63 9c f6 00 bne a3, a5, 24 +8000139c: 93 06 06 00 mv a3, a2 +800013a0: 6f 10 40 2d j 4820 +800013a4: 13 75 f7 0f andi a0, a4, 255 +800013a8: 63 14 05 00 bnez a0, 8 +800013ac: 6f 10 40 33 j 4916 +800013b0: 6f 00 40 00 j 4 +800013b4: 93 fa 0a 08 andi s5, s5, 128 +800013b8: 6f 00 40 00 j 4 +800013bc: 6f 00 40 00 j 4 +800013c0: 13 15 87 01 slli a0, a4, 24 +800013c4: 13 55 85 41 srai a0, a0, 24 +800013c8: 93 06 b0 02 addi a3, zero, 43 +800013cc: 63 40 d5 06 blt a0, a3, 96 +800013d0: 6f 00 40 00 j 4 +800013d4: 13 15 87 01 slli a0, a4, 24 +800013d8: 13 55 85 41 srai a0, a0, 24 +800013dc: 93 06 d0 02 addi a3, zero, 45 +800013e0: 63 4e d5 02 blt a0, a3, 60 +800013e4: 6f 00 40 00 j 4 +800013e8: 13 15 87 01 slli a0, a4, 24 +800013ec: 13 55 85 41 srai a0, a0, 24 +800013f0: 93 06 00 03 addi a3, zero, 48 +800013f4: 63 4c d5 00 blt a0, a3, 24 +800013f8: 6f 00 40 00 j 4 +800013fc: 13 75 f7 0f andi a0, a4, 255 +80001400: 93 06 00 03 addi a3, zero, 48 +80001404: 63 02 d5 0e beq a0, a3, 228 +80001408: 6f 00 80 05 j 88 +8000140c: 13 75 f7 0f andi a0, a4, 255 +80001410: 93 06 d0 02 addi a3, zero, 45 +80001414: 63 0a d5 06 beq a0, a3, 116 +80001418: 6f 00 80 04 j 72 +8000141c: 13 75 f7 0f andi a0, a4, 255 +80001420: 93 06 b0 02 addi a3, zero, 43 +80001424: 63 0e d5 06 beq a0, a3, 124 +80001428: 6f 00 80 03 j 56 +8000142c: 13 15 87 01 slli a0, a4, 24 +80001430: 13 55 85 41 srai a0, a0, 24 +80001434: 93 06 30 02 addi a3, zero, 35 +80001438: 63 4c d5 00 blt a0, a3, 24 +8000143c: 6f 00 40 00 j 4 +80001440: 13 75 f7 0f andi a0, a4, 255 +80001444: 93 06 30 02 addi a3, zero, 35 +80001448: 63 04 d5 08 beq a0, a3, 136 +8000144c: 6f 00 40 01 j 20 +80001450: 13 75 f7 0f andi a0, a4, 255 +80001454: 93 06 00 02 addi a3, zero, 32 +80001458: 63 00 d5 06 beq a0, a3, 96 +8000145c: 6f 00 40 00 j 4 +80001460: 6f 00 40 00 j 4 +80001464: 13 05 07 fd addi a0, a4, -48 +80001468: 13 75 f5 0f andi a0, a0, 255 +8000146c: 13 03 00 00 mv t1, zero +80001470: 93 06 90 00 addi a3, zero, 9 +80001474: 63 f6 a6 00 bgeu a3, a0, 12 +80001478: 13 05 06 00 mv a0, a2 +8000147c: 6f 00 00 10 j 256 +80001480: 13 03 00 00 mv t1, zero +80001484: 6f 00 80 09 j 152 +80001488: 13 f5 4a 00 andi a0, s5, 4 +8000148c: 93 07 20 01 addi a5, zero, 18 +80001490: 63 04 05 00 beqz a0, 8 +80001494: 6f 10 80 24 j 4680 +80001498: 93 ea 4a 00 ori s5, s5, 4 +8000149c: 6f 00 00 07 j 112 +800014a0: 13 f5 0a 01 andi a0, s5, 16 +800014a4: 93 07 30 01 addi a5, zero, 19 +800014a8: 63 04 05 00 beqz a0, 8 +800014ac: 6f 10 00 23 j 4656 +800014b0: 93 ea 0a 01 ori s5, s5, 16 +800014b4: 6f 00 80 05 j 88 +800014b8: 13 f5 0a 04 andi a0, s5, 64 +800014bc: 93 07 40 01 addi a5, zero, 20 +800014c0: 63 04 05 00 beqz a0, 8 +800014c4: 6f 10 80 21 j 4632 +800014c8: 93 ea 0a 04 ori s5, s5, 64 +800014cc: 6f 00 00 04 j 64 +800014d0: 13 f5 2a 00 andi a0, s5, 2 +800014d4: 93 07 50 01 addi a5, zero, 21 +800014d8: 63 04 05 00 beqz a0, 8 +800014dc: 6f 10 00 20 j 4608 +800014e0: 93 ea 2a 00 ori s5, s5, 2 +800014e4: 6f 00 80 02 j 40 +800014e8: 13 f5 1a 00 andi a0, s5, 1 +800014ec: 93 07 60 01 addi a5, zero, 22 +800014f0: 63 04 05 00 beqz a0, 8 +800014f4: 6f 10 80 1e j 4584 +800014f8: 13 d5 2a 00 srli a0, s5, 2 +800014fc: 13 45 f5 ff not a0, a0 +80001500: 13 75 15 00 andi a0, a0, 1 +80001504: b3 6a 55 01 or s5, a0, s5 +80001508: 6f 00 40 00 j 4 +8000150c: 13 05 16 00 addi a0, a2, 1 +80001510: 03 47 06 00 lbu a4, 0(a2) +80001514: 13 06 05 00 mv a2, a0 +80001518: 6f f0 5f ea j -348 +8000151c: 13 75 f7 0f andi a0, a4, 255 +80001520: 93 07 70 01 addi a5, zero, 23 +80001524: 93 06 00 03 addi a3, zero, 48 +80001528: 63 18 d5 00 bne a0, a3, 16 +8000152c: 6f 00 40 00 j 4 +80001530: 63 14 03 00 bnez t1, 8 +80001534: 6f 10 40 1a j 4516 +80001538: 93 07 80 01 addi a5, zero, 24 +8000153c: b7 d6 cc 0c lui a3, 52429 +80001540: 93 86 b6 cc addi a3, a3, -821 +80001544: 63 f4 66 00 bgeu a3, t1, 8 +80001548: 6f 10 00 19 j 4496 +8000154c: 93 06 a0 00 addi a3, zero, 10 +80001550: 33 07 d3 02 mul a4, t1, a3 +80001554: 33 05 e5 00 add a0, a0, a4 +80001558: 13 03 05 fd addi t1, a0, -48 +8000155c: 13 05 16 00 addi a0, a2, 1 +80001560: 03 47 06 00 lbu a4, 0(a2) +80001564: 13 06 07 fd addi a2, a4, -48 +80001568: 93 77 f6 0f andi a5, a2, 255 +8000156c: 13 06 05 00 mv a2, a0 +80001570: e3 e6 d7 fa bltu a5, a3, -84 +80001574: 6f 00 40 00 j 4 +80001578: 6f 00 40 00 j 4 +8000157c: 13 76 f7 0f andi a2, a4, 255 +80001580: 13 08 f0 ff addi a6, zero, -1 +80001584: 93 06 e0 02 addi a3, zero, 46 +80001588: 63 04 d6 00 beq a2, a3, 8 +8000158c: 6f 00 40 07 j 116 +80001590: 13 06 15 00 addi a2, a0, 1 +80001594: 03 47 05 00 lbu a4, 0(a0) +80001598: 13 05 07 fd addi a0, a4, -48 +8000159c: 13 75 f5 0f andi a0, a0, 255 +800015a0: 13 08 00 00 mv a6, zero +800015a4: 93 06 90 00 addi a3, zero, 9 +800015a8: 63 f6 a6 00 bgeu a3, a0, 12 +800015ac: 13 05 06 00 mv a0, a2 +800015b0: 6f 00 00 05 j 80 +800015b4: 13 08 00 00 mv a6, zero +800015b8: 6f 00 40 00 j 4 +800015bc: 37 d5 cc 0c lui a0, 52429 +800015c0: 13 05 b5 cc addi a0, a0, -821 +800015c4: 63 54 05 01 bge a0, a6, 8 +800015c8: 6f 10 80 10 j 4360 +800015cc: 13 75 f7 0f andi a0, a4, 255 +800015d0: 93 06 a0 00 addi a3, zero, 10 +800015d4: 33 07 d8 02 mul a4, a6, a3 +800015d8: 33 05 e5 00 add a0, a0, a4 +800015dc: 13 08 05 fd addi a6, a0, -48 +800015e0: 13 05 16 00 addi a0, a2, 1 +800015e4: 03 47 06 00 lbu a4, 0(a2) +800015e8: 13 06 07 fd addi a2, a4, -48 +800015ec: 93 77 f6 0f andi a5, a2, 255 +800015f0: 13 06 05 00 mv a2, a0 +800015f4: e3 e4 d7 fc bltu a5, a3, -56 +800015f8: 6f 00 40 00 j 4 +800015fc: 6f 00 40 00 j 4 +80001600: 93 76 f7 0f andi a3, a4, 255 +80001604: 13 06 00 00 mv a2, zero +80001608: 93 07 60 07 addi a5, zero, 118 +8000160c: 63 84 f6 00 beq a3, a5, 8 +80001610: 6f 00 c0 0c j 204 +80001614: 03 47 05 00 lbu a4, 0(a0) +80001618: 13 06 07 fd addi a2, a4, -48 +8000161c: 13 76 f6 0f andi a2, a2, 255 +80001620: 93 07 20 02 addi a5, zero, 34 +80001624: 93 06 90 00 addi a3, zero, 9 +80001628: 63 f4 c6 00 bgeu a3, a2, 8 +8000162c: 6f 10 c0 0c j 4300 +80001630: 93 06 15 00 addi a3, a0, 1 +80001634: 13 06 00 00 mv a2, zero +80001638: 6f 00 40 00 j 4 +8000163c: 13 75 f7 0f andi a0, a4, 255 +80001640: 93 07 00 02 addi a5, zero, 32 +80001644: 13 07 00 03 addi a4, zero, 48 +80001648: 63 18 e5 00 bne a0, a4, 16 +8000164c: 6f 00 40 00 j 4 +80001650: 63 14 06 00 bnez a2, 8 +80001654: 6f 10 80 07 j 4216 +80001658: 93 07 10 02 addi a5, zero, 33 +8000165c: 37 d7 cc 0c lui a4, 52429 +80001660: 13 07 b7 cc addi a4, a4, -821 +80001664: 63 74 c7 00 bgeu a4, a2, 8 +80001668: 6f 10 40 06 j 4196 +8000166c: 93 08 a0 00 addi a7, zero, 10 +80001670: 33 06 16 03 mul a2, a2, a7 +80001674: 33 05 c5 00 add a0, a0, a2 +80001678: 13 06 05 fd addi a2, a0, -48 +8000167c: 13 85 16 00 addi a0, a3, 1 +80001680: 03 c7 06 00 lbu a4, 0(a3) +80001684: 93 06 07 fd addi a3, a4, -48 +80001688: 93 f7 f6 0f andi a5, a3, 255 +8000168c: 93 06 05 00 mv a3, a0 +80001690: e3 e6 17 fb bltu a5, a7, -84 +80001694: 6f 00 40 00 j 4 +80001698: 6f 00 40 00 j 4 +8000169c: 93 06 80 00 addi a3, zero, 8 +800016a0: 63 46 d6 02 blt a2, a3, 44 +800016a4: 6f 00 40 00 j 4 +800016a8: 93 06 00 01 addi a3, zero, 16 +800016ac: 63 4a d6 00 blt a2, a3, 20 +800016b0: 6f 00 40 00 j 4 +800016b4: 93 06 00 01 addi a3, zero, 16 +800016b8: 63 02 d6 02 beq a2, a3, 36 +800016bc: 6f 10 c0 02 j 4140 +800016c0: 93 06 80 00 addi a3, zero, 8 +800016c4: 63 0c d6 00 beq a2, a3, 24 +800016c8: 6f 10 00 02 j 4128 +800016cc: 93 06 e6 ff addi a3, a2, -2 +800016d0: 93 07 20 00 addi a5, zero, 2 +800016d4: 63 f4 d7 00 bgeu a5, a3, 8 +800016d8: 6f 10 00 01 j 4112 +800016dc: 6f 00 40 00 j 4 +800016e0: 93 16 87 01 slli a3, a4, 24 +800016e4: 93 d6 86 41 srai a3, a3, 24 +800016e8: 93 07 c0 06 addi a5, zero, 108 +800016ec: 63 c2 f6 02 blt a3, a5, 36 +800016f0: 6f 00 40 00 j 4 +800016f4: 93 77 f7 0f andi a5, a4, 255 +800016f8: 93 08 80 00 addi a7, zero, 8 +800016fc: 93 06 10 00 addi a3, zero, 1 +80001700: 93 02 c0 06 addi t0, zero, 108 +80001704: 93 0c 05 00 mv s9, a0 +80001708: 63 8c 57 08 beq a5, t0, 152 +8000170c: 6f 00 c0 05 j 92 +80001710: 93 76 f7 0f andi a3, a4, 255 +80001714: 93 07 80 06 addi a5, zero, 104 +80001718: 63 98 f6 04 bne a3, a5, 80 +8000171c: 6f 00 40 00 j 4 +80001720: 93 0c 15 00 addi s9, a0, 1 +80001724: 03 07 05 00 lb a4, 0(a0) +80001728: 6f 00 40 00 j 4 +8000172c: 93 16 87 01 slli a3, a4, 24 +80001730: 93 d6 86 41 srai a3, a3, 24 +80001734: 93 07 c0 06 addi a5, zero, 108 +80001738: 63 cc f6 00 blt a3, a5, 24 +8000173c: 6f 00 40 00 j 4 +80001740: 93 76 f7 0f andi a3, a4, 255 +80001744: 93 07 c0 06 addi a5, zero, 108 +80001748: 63 8c f6 02 beq a3, a5, 56 +8000174c: 6f 00 40 06 j 100 +80001750: 93 72 f7 0f andi t0, a4, 255 +80001754: 93 08 10 00 addi a7, zero, 1 +80001758: 93 06 20 00 addi a3, zero, 2 +8000175c: 93 07 80 06 addi a5, zero, 104 +80001760: 63 98 f2 04 bne t0, a5, 80 +80001764: 6f 00 c0 03 j 60 +80001768: 6f 00 40 00 j 4 +8000176c: 93 07 30 02 addi a5, zero, 35 +80001770: 93 06 10 00 addi a3, zero, 1 +80001774: 93 08 00 00 mv a7, zero +80001778: 63 0a 06 04 beqz a2, 84 +8000177c: 6f 00 d0 77 j 3964 +80001780: 13 05 25 00 addi a0, a0, 2 +80001784: 03 c7 0c 00 lbu a4, 0(s9) +80001788: 93 08 40 00 addi a7, zero, 4 +8000178c: 93 07 40 02 addi a5, zero, 36 +80001790: 93 02 00 00 mv t0, zero +80001794: 93 0c 05 00 mv s9, a0 +80001798: e3 00 06 76 beqz a2, 3936 +8000179c: 6f 00 00 04 j 64 +800017a0: 33 05 d5 00 add a0, a0, a3 +800017a4: 03 c7 0c 00 lbu a4, 0(s9) +800017a8: 93 0c 05 00 mv s9, a0 +800017ac: 6f 00 c0 00 j 12 +800017b0: 93 08 20 00 addi a7, zero, 2 +800017b4: 6f 00 40 00 j 4 +800017b8: 93 06 00 00 mv a3, zero +800017bc: 13 85 0c 00 mv a0, s9 +800017c0: 93 02 00 00 mv t0, zero +800017c4: 63 1c 06 00 bnez a2, 24 +800017c8: 6f 00 40 00 j 4 +800017cc: 13 06 10 00 addi a2, zero, 1 +800017d0: 93 82 06 00 mv t0, a3 +800017d4: 93 0c 05 00 mv s9, a0 +800017d8: 6f 00 40 00 j 4 +800017dc: 23 00 5d 01 sb s5, 0(s10) +800017e0: 23 80 ed 00 sb a4, 0(s11) +800017e4: 23 a0 69 00 sw t1, 0(s3) +800017e8: 23 20 0a 01 sw a6, 0(s4) +800017ec: 6f 00 40 00 j 4 +800017f0: 13 15 87 01 slli a0, a4, 24 +800017f4: 13 55 85 41 srai a0, a0, 24 +800017f8: 93 06 50 06 addi a3, zero, 101 +800017fc: 63 42 d5 0e blt a0, a3, 228 +80001800: 6f 00 40 00 j 4 +80001804: 13 15 87 01 slli a0, a4, 24 +80001808: 13 55 85 41 srai a0, a0, 24 +8000180c: 93 06 00 07 addi a3, zero, 112 +80001810: 63 42 d5 08 blt a0, a3, 132 +80001814: 6f 00 40 00 j 4 +80001818: 13 15 87 01 slli a0, a4, 24 +8000181c: 13 55 85 41 srai a0, a0, 24 +80001820: 93 06 50 07 addi a3, zero, 117 +80001824: 63 4e d5 02 blt a0, a3, 60 +80001828: 6f 00 40 00 j 4 +8000182c: 13 15 87 01 slli a0, a4, 24 +80001830: 13 55 85 41 srai a0, a0, 24 +80001834: 93 06 80 07 addi a3, zero, 120 +80001838: 63 4c d5 00 blt a0, a3, 24 +8000183c: 6f 00 40 00 j 4 +80001840: 13 75 f7 0f andi a0, a4, 255 +80001844: 93 06 80 07 addi a3, zero, 120 +80001848: 63 0e d5 14 beq a0, a3, 348 +8000184c: 6f 00 50 6a j 3748 +80001850: 13 75 f7 0f andi a0, a4, 255 +80001854: 93 06 50 07 addi a3, zero, 117 +80001858: 63 08 d5 12 beq a0, a3, 304 +8000185c: 6f 00 50 69 j 3732 +80001860: 13 15 87 01 slli a0, a4, 24 +80001864: 13 55 85 41 srai a0, a0, 24 +80001868: 93 06 30 07 addi a3, zero, 115 +8000186c: 63 4c d5 00 blt a0, a3, 24 +80001870: 6f 00 40 00 j 4 +80001874: 13 75 f7 0f andi a0, a4, 255 +80001878: 93 06 30 07 addi a3, zero, 115 +8000187c: e3 0c d5 1c beq a0, a3, 2520 +80001880: 6f 00 10 67 j 3696 +80001884: 13 75 f7 0f andi a0, a4, 255 +80001888: 93 06 00 07 addi a3, zero, 112 +8000188c: e3 00 d5 48 beq a0, a3, 3200 +80001890: 6f 00 10 66 j 3680 +80001894: 13 15 87 01 slli a0, a4, 24 +80001898: 13 55 85 41 srai a0, a0, 24 +8000189c: 93 06 90 06 addi a3, zero, 105 +800018a0: 63 46 d5 02 blt a0, a3, 44 +800018a4: 6f 00 40 00 j 4 +800018a8: 13 15 87 01 slli a0, a4, 24 +800018ac: 13 55 85 41 srai a0, a0, 24 +800018b0: 93 06 e0 06 addi a3, zero, 110 +800018b4: 63 ca a6 0c blt a3, a0, 212 +800018b8: 6f 00 40 00 j 4 +800018bc: 13 75 f7 0f andi a0, a4, 255 +800018c0: 93 06 90 06 addi a3, zero, 105 +800018c4: 63 02 d5 0c beq a0, a3, 196 +800018c8: 6f 00 90 62 j 3624 +800018cc: 13 15 87 01 slli a0, a4, 24 +800018d0: 13 55 85 41 srai a0, a0, 24 +800018d4: 93 06 80 06 addi a3, zero, 104 +800018d8: 63 40 d5 72 blt a0, a3, 1824 +800018dc: 6f 00 50 61 j 3604 +800018e0: 13 15 87 01 slli a0, a4, 24 +800018e4: 13 55 85 41 srai a0, a0, 24 +800018e8: 93 06 10 06 addi a3, zero, 97 +800018ec: 63 40 d5 04 blt a0, a3, 64 +800018f0: 6f 00 40 00 j 4 +800018f4: 13 15 87 01 slli a0, a4, 24 +800018f8: 13 55 85 41 srai a0, a0, 24 +800018fc: 93 06 30 06 addi a3, zero, 99 +80001900: 63 4e d5 00 blt a0, a3, 28 +80001904: 6f 00 40 00 j 4 +80001908: 13 15 87 01 slli a0, a4, 24 +8000190c: 13 55 85 41 srai a0, a0, 24 +80001910: 93 06 40 06 addi a3, zero, 100 +80001914: e3 48 d5 0c blt a0, a3, 2256 +80001918: 6f 00 00 07 j 112 +8000191c: 13 75 f7 0f andi a0, a4, 255 +80001920: 93 06 10 06 addi a3, zero, 97 +80001924: 63 0a d5 6c beq a0, a3, 1748 +80001928: 6f 00 90 5c j 3528 +8000192c: 13 15 87 01 slli a0, a4, 24 +80001930: 13 55 85 41 srai a0, a0, 24 +80001934: 93 06 50 04 addi a3, zero, 69 +80001938: 63 40 d5 04 blt a0, a3, 64 +8000193c: 6f 00 40 00 j 4 +80001940: 13 15 87 01 slli a0, a4, 24 +80001944: 13 55 85 41 srai a0, a0, 24 +80001948: 93 06 80 05 addi a3, zero, 88 +8000194c: 63 4c d5 00 blt a0, a3, 24 +80001950: 6f 00 40 00 j 4 +80001954: 13 75 f7 0f andi a0, a4, 255 +80001958: 93 06 80 05 addi a3, zero, 88 +8000195c: 63 04 d5 04 beq a0, a3, 72 +80001960: 6f 00 10 59 j 3472 +80001964: 13 15 87 01 slli a0, a4, 24 +80001968: 13 55 85 41 srai a0, a0, 24 +8000196c: 93 06 80 04 addi a3, zero, 72 +80001970: 63 44 d5 68 blt a0, a3, 1672 +80001974: 6f 00 d0 57 j 3452 +80001978: 13 75 f7 0f andi a0, a4, 255 +8000197c: 93 06 10 04 addi a3, zero, 65 +80001980: 63 0c d5 66 beq a0, a3, 1656 +80001984: 6f 00 d0 56 j 3436 +80001988: 93 76 f7 0f andi a3, a4, 255 +8000198c: 13 05 80 00 addi a0, zero, 8 +80001990: 93 07 f0 06 addi a5, zero, 111 +80001994: 63 84 f6 00 beq a3, a5, 8 +80001998: 13 05 a0 00 addi a0, zero, 10 +8000199c: 93 87 0a 00 mv a5, s5 +800019a0: 6f 00 80 03 j 56 +800019a4: 93 76 f7 0f andi a3, a4, 255 +800019a8: 13 05 80 00 addi a0, zero, 8 +800019ac: 93 07 f0 06 addi a5, zero, 111 +800019b0: 63 84 f6 00 beq a3, a5, 8 +800019b4: 13 05 00 01 addi a0, zero, 16 +800019b8: 93 07 80 05 addi a5, zero, 88 +800019bc: 63 86 f6 00 beq a3, a5, 12 +800019c0: 93 87 0a 00 mv a5, s5 +800019c4: 6f 00 40 01 j 20 +800019c8: 93 e7 8a 00 ori a5, s5, 8 +800019cc: 23 00 fd 00 sb a5, 0(s10) +800019d0: 13 07 80 05 addi a4, zero, 88 +800019d4: 6f 00 40 00 j 4 +800019d8: 93 76 f7 0f andi a3, a4, 255 +800019dc: 93 c6 56 07 xori a3, a3, 117 +800019e0: 93 b6 16 00 seqz a3, a3 +800019e4: 13 47 a5 00 xori a4, a0, 10 +800019e8: 33 37 e0 00 snez a4, a4 +800019ec: b3 e6 e6 00 or a3, a3, a4 +800019f0: 13 07 10 00 addi a4, zero, 1 +800019f4: 63 4a e8 00 blt a6, a4, 20 +800019f8: 6f 00 40 00 j 4 +800019fc: 13 f7 e7 0f andi a4, a5, 254 +80001a00: 23 00 ed 00 sb a4, 0(s10) +80001a04: 6f 00 c0 01 j 28 +80001a08: 13 07 f0 ff addi a4, zero, -1 +80001a0c: 63 4a 07 01 blt a4, a6, 20 +80001a10: 6f 00 40 00 j 4 +80001a14: 13 07 10 00 addi a4, zero, 1 +80001a18: 23 20 ea 00 sw a4, 0(s4) +80001a1c: 6f 00 40 00 j 4 +80001a20: 23 20 a9 00 sw a0, 0(s2) +80001a24: 6f 00 40 00 j 4 +80001a28: 13 05 20 00 addi a0, zero, 2 +80001a2c: 63 ca a8 00 blt a7, a0, 20 +80001a30: 6f 00 40 00 j 4 +80001a34: 13 05 20 00 addi a0, zero, 2 +80001a38: 63 80 a8 20 beq a7, a0, 512 +80001a3c: 6f 00 c0 3d j 988 +80001a40: 13 05 10 00 addi a0, zero, 1 +80001a44: 63 9a a8 3c bne a7, a0, 980 +80001a48: 6f 00 40 00 j 4 +80001a4c: 6f 00 40 00 j 4 +80001a50: 13 05 80 00 addi a0, zero, 8 +80001a54: 63 4a a6 00 blt a2, a0, 20 +80001a58: 6f 00 40 00 j 4 +80001a5c: 13 05 00 01 addi a0, zero, 16 +80001a60: 63 40 a6 08 blt a2, a0, 128 +80001a64: 6f 00 c0 0e j 236 +80001a68: 13 05 20 00 addi a0, zero, 2 +80001a6c: 63 4a a6 00 blt a2, a0, 20 +80001a70: 6f 00 40 00 j 4 +80001a74: 13 05 20 00 addi a0, zero, 2 +80001a78: 63 0e a6 00 beq a2, a0, 28 +80001a7c: 6f 00 40 03 j 52 +80001a80: 13 85 45 00 addi a0, a1, 4 +80001a84: 23 2c a1 06 sw a0, 120(sp) +80001a88: 03 85 05 00 lb a0, 0(a1) +80001a8c: 23 00 a1 14 sb a0, 320(sp) +80001a90: 6f 00 80 17 j 376 +80001a94: 13 85 45 00 addi a0, a1, 4 +80001a98: 23 2c a1 06 sw a0, 120(sp) +80001a9c: 03 85 05 00 lb a0, 0(a1) +80001aa0: 83 85 15 00 lb a1, 1(a1) +80001aa4: a3 00 b1 14 sb a1, 321(sp) +80001aa8: 23 00 a1 14 sb a0, 320(sp) +80001aac: 6f 00 c0 15 j 348 +80001ab0: 6f 00 40 00 j 4 +80001ab4: 13 85 45 00 addi a0, a1, 4 +80001ab8: 23 2c a1 06 sw a0, 120(sp) +80001abc: 03 85 05 00 lb a0, 0(a1) +80001ac0: 03 87 15 00 lb a4, 1(a1) +80001ac4: 83 87 25 00 lb a5, 2(a1) +80001ac8: 83 85 35 00 lb a1, 3(a1) +80001acc: a3 01 b1 14 sb a1, 323(sp) +80001ad0: 23 01 f1 14 sb a5, 322(sp) +80001ad4: a3 00 e1 14 sb a4, 321(sp) +80001ad8: 23 00 a1 14 sb a0, 320(sp) +80001adc: 6f 00 c0 12 j 300 +80001ae0: 13 85 75 00 addi a0, a1, 7 +80001ae4: 13 75 85 ff andi a0, a0, -8 +80001ae8: 93 05 85 00 addi a1, a0, 8 +80001aec: 23 2c b1 06 sw a1, 120(sp) +80001af0: 03 08 05 00 lb a6, 0(a0) +80001af4: 13 67 15 00 ori a4, a0, 1 +80001af8: 83 08 07 00 lb a7, 0(a4) +80001afc: 93 67 25 00 ori a5, a0, 2 +80001b00: 83 82 07 00 lb t0, 0(a5) +80001b04: 93 65 35 00 ori a1, a0, 3 +80001b08: 03 83 05 00 lb t1, 0(a1) +80001b0c: 13 67 45 00 ori a4, a0, 4 +80001b10: 03 07 07 00 lb a4, 0(a4) +80001b14: 93 67 55 00 ori a5, a0, 5 +80001b18: 83 87 07 00 lb a5, 0(a5) +80001b1c: 93 65 65 00 ori a1, a0, 6 +80001b20: 83 85 05 00 lb a1, 0(a1) +80001b24: 13 65 75 00 ori a0, a0, 7 +80001b28: 03 05 05 00 lb a0, 0(a0) +80001b2c: a3 03 a1 14 sb a0, 327(sp) +80001b30: 23 03 b1 14 sb a1, 326(sp) +80001b34: a3 02 f1 14 sb a5, 325(sp) +80001b38: 23 02 e1 14 sb a4, 324(sp) +80001b3c: a3 01 61 14 sb t1, 323(sp) +80001b40: 23 01 51 14 sb t0, 322(sp) +80001b44: a3 00 11 15 sb a7, 321(sp) +80001b48: 23 00 01 15 sb a6, 320(sp) +80001b4c: 6f 00 c0 0b j 188 +80001b50: 13 85 45 00 addi a0, a1, 4 +80001b54: 23 2c a1 06 sw a0, 120(sp) +80001b58: 03 a5 05 00 lw a0, 0(a1) +80001b5c: 83 05 05 00 lb a1, 0(a0) +80001b60: 23 26 b1 06 sw a1, 108(sp) +80001b64: 83 05 15 00 lb a1, 1(a0) +80001b68: 23 20 b1 06 sw a1, 96(sp) +80001b6c: 83 05 25 00 lb a1, 2(a0) +80001b70: 23 2a b1 04 sw a1, 84(sp) +80001b74: 03 03 35 00 lb t1, 3(a0) +80001b78: 83 03 45 00 lb t2, 4(a0) +80001b7c: 03 0e 55 00 lb t3, 5(a0) +80001b80: 83 0e 65 00 lb t4, 6(a0) +80001b84: 93 82 06 00 mv t0, a3 +80001b88: 93 06 0f 00 mv a3, t5 +80001b8c: 03 0f 75 00 lb t5, 7(a0) +80001b90: 83 0f 85 00 lb t6, 8(a0) +80001b94: 83 00 95 00 lb ra, 9(a0) +80001b98: 83 08 a5 00 lb a7, 10(a0) +80001b9c: 03 08 b5 00 lb a6, 11(a0) +80001ba0: 83 07 c5 00 lb a5, 12(a0) +80001ba4: 03 07 d5 00 lb a4, 13(a0) +80001ba8: 83 05 e5 00 lb a1, 14(a0) +80001bac: 03 05 f5 00 lb a0, 15(a0) +80001bb0: a3 07 a1 14 sb a0, 335(sp) +80001bb4: 23 07 b1 14 sb a1, 334(sp) +80001bb8: a3 06 e1 14 sb a4, 333(sp) +80001bbc: 23 06 f1 14 sb a5, 332(sp) +80001bc0: a3 05 01 15 sb a6, 331(sp) +80001bc4: 23 05 11 15 sb a7, 330(sp) +80001bc8: a3 04 11 14 sb ra, 329(sp) +80001bcc: 23 04 f1 15 sb t6, 328(sp) +80001bd0: a3 03 e1 15 sb t5, 327(sp) +80001bd4: 13 8f 06 00 mv t5, a3 +80001bd8: 93 86 02 00 mv a3, t0 +80001bdc: 23 03 d1 15 sb t4, 326(sp) +80001be0: a3 02 c1 15 sb t3, 325(sp) +80001be4: 23 02 71 14 sb t2, 324(sp) +80001be8: a3 01 61 14 sb t1, 323(sp) +80001bec: 03 25 41 05 lw a0, 84(sp) +80001bf0: 23 01 a1 14 sb a0, 322(sp) +80001bf4: 03 25 01 06 lw a0, 96(sp) +80001bf8: a3 00 a1 14 sb a0, 321(sp) +80001bfc: 03 25 c1 06 lw a0, 108(sp) +80001c00: 23 00 a1 14 sb a0, 320(sp) +80001c04: 6f 00 40 00 j 4 +80001c08: 13 85 04 00 mv a0, s1 +80001c0c: 93 05 0f 00 mv a1, t5 +80001c10: 97 f0 ff ff auipc ra, 1048575 +80001c14: e7 80 80 a6 jalr -1432(ra) +80001c18: 13 0f 01 14 addi t5, sp, 320 +80001c1c: 93 03 c1 15 addi t2, sp, 348 +80001c20: 13 0e 01 0c addi t3, sp, 192 +80001c24: 93 0e 01 12 addi t4, sp, 288 +80001c28: 93 0f 01 08 addi t6, sp, 128 +80001c2c: 93 00 d1 15 addi ra, sp, 349 +80001c30: 83 25 81 07 lw a1, 120(sp) +80001c34: 6f 00 10 05 j 2128 +80001c38: 6f 00 40 00 j 4 +80001c3c: 13 05 80 00 addi a0, zero, 8 +80001c40: 63 4a a6 00 blt a2, a0, 20 +80001c44: 6f 00 40 00 j 4 +80001c48: 13 05 00 01 addi a0, zero, 16 +80001c4c: 63 4a a6 08 blt a2, a0, 148 +80001c50: 6f 00 00 0e j 224 +80001c54: 13 05 20 00 addi a0, zero, 2 +80001c58: 63 4a a6 00 blt a2, a0, 20 +80001c5c: 6f 00 40 00 j 4 +80001c60: 13 05 20 00 addi a0, zero, 2 +80001c64: 63 0e a6 00 beq a2, a0, 28 +80001c68: 6f 00 40 03 j 52 +80001c6c: 13 85 45 00 addi a0, a1, 4 +80001c70: 23 2c a1 06 sw a0, 120(sp) +80001c74: 03 95 05 00 lh a0, 0(a1) +80001c78: 23 10 a1 12 sh a0, 288(sp) +80001c7c: 6f 00 c0 16 j 364 +80001c80: 13 85 45 00 addi a0, a1, 4 +80001c84: 23 2c a1 06 sw a0, 120(sp) +80001c88: 03 95 05 00 lh a0, 0(a1) +80001c8c: 83 95 25 00 lh a1, 2(a1) +80001c90: 23 11 b1 12 sh a1, 290(sp) +80001c94: 23 10 a1 12 sh a0, 288(sp) +80001c98: 6f 00 00 15 j 336 +80001c9c: 6f 00 40 00 j 4 +80001ca0: 13 85 75 00 addi a0, a1, 7 +80001ca4: 13 75 85 ff andi a0, a0, -8 +80001ca8: 93 05 85 00 addi a1, a0, 8 +80001cac: 23 2c b1 06 sw a1, 120(sp) +80001cb0: 83 15 05 00 lh a1, 0(a0) +80001cb4: 13 67 25 00 ori a4, a0, 2 +80001cb8: 03 17 07 00 lh a4, 0(a4) +80001cbc: 93 67 45 00 ori a5, a0, 4 +80001cc0: 83 97 07 00 lh a5, 0(a5) +80001cc4: 13 65 65 00 ori a0, a0, 6 +80001cc8: 03 15 05 00 lh a0, 0(a0) +80001ccc: 23 13 a1 12 sh a0, 294(sp) +80001cd0: 23 12 f1 12 sh a5, 292(sp) +80001cd4: 23 11 e1 12 sh a4, 290(sp) +80001cd8: 23 10 b1 12 sh a1, 288(sp) +80001cdc: 6f 00 c0 10 j 268 +80001ce0: 13 85 45 00 addi a0, a1, 4 +80001ce4: 23 2c a1 06 sw a0, 120(sp) +80001ce8: 03 a5 05 00 lw a0, 0(a1) +80001cec: 03 18 05 00 lh a6, 0(a0) +80001cf0: 83 18 25 00 lh a7, 2(a0) +80001cf4: 83 12 45 00 lh t0, 4(a0) +80001cf8: 03 13 65 00 lh t1, 6(a0) +80001cfc: 03 17 85 00 lh a4, 8(a0) +80001d00: 83 17 a5 00 lh a5, 10(a0) +80001d04: 83 15 c5 00 lh a1, 12(a0) +80001d08: 03 15 e5 00 lh a0, 14(a0) +80001d0c: 23 17 a1 12 sh a0, 302(sp) +80001d10: 23 16 b1 12 sh a1, 300(sp) +80001d14: 23 15 f1 12 sh a5, 298(sp) +80001d18: 23 14 e1 12 sh a4, 296(sp) +80001d1c: 23 13 61 12 sh t1, 294(sp) +80001d20: 23 12 51 12 sh t0, 292(sp) +80001d24: 23 11 11 13 sh a7, 290(sp) +80001d28: 23 10 01 13 sh a6, 288(sp) +80001d2c: 6f 00 c0 0b j 188 +80001d30: 13 85 45 00 addi a0, a1, 4 +80001d34: 23 2c a1 06 sw a0, 120(sp) +80001d38: 03 a5 05 00 lw a0, 0(a1) +80001d3c: 83 15 05 00 lh a1, 0(a0) +80001d40: 23 2a b1 06 sw a1, 116(sp) +80001d44: 83 15 25 00 lh a1, 2(a0) +80001d48: 23 24 b1 06 sw a1, 104(sp) +80001d4c: 83 15 45 00 lh a1, 4(a0) +80001d50: 23 2e b1 04 sw a1, 92(sp) +80001d54: 03 13 65 00 lh t1, 6(a0) +80001d58: 83 13 85 00 lh t2, 8(a0) +80001d5c: 03 1e a5 00 lh t3, 10(a0) +80001d60: 93 82 06 00 mv t0, a3 +80001d64: 93 86 0e 00 mv a3, t4 +80001d68: 83 1e c5 00 lh t4, 12(a0) +80001d6c: 03 1f e5 00 lh t5, 14(a0) +80001d70: 83 1f 05 01 lh t6, 16(a0) +80001d74: 83 10 25 01 lh ra, 18(a0) +80001d78: 83 18 45 01 lh a7, 20(a0) +80001d7c: 03 18 65 01 lh a6, 22(a0) +80001d80: 83 17 85 01 lh a5, 24(a0) +80001d84: 03 17 a5 01 lh a4, 26(a0) +80001d88: 83 15 c5 01 lh a1, 28(a0) +80001d8c: 03 15 e5 01 lh a0, 30(a0) +80001d90: 23 1f a1 12 sh a0, 318(sp) +80001d94: 23 1e b1 12 sh a1, 316(sp) +80001d98: 23 1d e1 12 sh a4, 314(sp) +80001d9c: 23 1c f1 12 sh a5, 312(sp) +80001da0: 23 1b 01 13 sh a6, 310(sp) +80001da4: 23 1a 11 13 sh a7, 308(sp) +80001da8: 23 19 11 12 sh ra, 306(sp) +80001dac: 23 18 f1 13 sh t6, 304(sp) +80001db0: 23 17 e1 13 sh t5, 302(sp) +80001db4: 23 16 d1 13 sh t4, 300(sp) +80001db8: 93 8e 06 00 mv t4, a3 +80001dbc: 93 86 02 00 mv a3, t0 +80001dc0: 23 15 c1 13 sh t3, 298(sp) +80001dc4: 23 14 71 12 sh t2, 296(sp) +80001dc8: 23 13 61 12 sh t1, 294(sp) +80001dcc: 03 25 c1 05 lw a0, 92(sp) +80001dd0: 23 12 a1 12 sh a0, 292(sp) +80001dd4: 03 25 81 06 lw a0, 104(sp) +80001dd8: 23 11 a1 12 sh a0, 290(sp) +80001ddc: 03 25 41 07 lw a0, 116(sp) +80001de0: 23 10 a1 12 sh a0, 288(sp) +80001de4: 6f 00 40 00 j 4 +80001de8: 13 85 04 00 mv a0, s1 +80001dec: 93 85 0e 00 mv a1, t4 +80001df0: 97 f0 ff ff auipc ra, 1048575 +80001df4: e7 80 00 b3 jalr -1232(ra) +80001df8: 93 0e 01 12 addi t4, sp, 288 +80001dfc: 93 03 c1 15 addi t2, sp, 348 +80001e00: 13 0e 01 0c addi t3, sp, 192 +80001e04: 13 0f 01 14 addi t5, sp, 320 +80001e08: 93 0f 01 08 addi t6, sp, 128 +80001e0c: 93 00 d1 15 addi ra, sp, 349 +80001e10: 83 25 81 07 lw a1, 120(sp) +80001e14: 6f 00 00 67 j 1648 +80001e18: 6f 00 40 00 j 4 +80001e1c: 6f 00 40 00 j 4 +80001e20: 13 05 80 00 addi a0, zero, 8 +80001e24: 63 4a a6 00 blt a2, a0, 20 +80001e28: 6f 00 40 00 j 4 +80001e2c: 13 05 00 01 addi a0, zero, 16 +80001e30: 63 48 a6 08 blt a2, a0, 144 +80001e34: 6f 00 c0 0d j 220 +80001e38: 13 05 20 00 addi a0, zero, 2 +80001e3c: 63 4a a6 00 blt a2, a0, 20 +80001e40: 6f 00 40 00 j 4 +80001e44: 13 05 20 00 addi a0, zero, 2 +80001e48: 63 0e a6 00 beq a2, a0, 28 +80001e4c: 6f 00 00 04 j 64 +80001e50: 13 85 45 00 addi a0, a1, 4 +80001e54: 23 2c a1 06 sw a0, 120(sp) +80001e58: 03 a5 05 00 lw a0, 0(a1) +80001e5c: 23 20 a1 0c sw a0, 192(sp) +80001e60: 6f 00 80 16 j 360 +80001e64: 13 85 75 00 addi a0, a1, 7 +80001e68: 13 75 85 ff andi a0, a0, -8 +80001e6c: 93 05 85 00 addi a1, a0, 8 +80001e70: 23 2c b1 06 sw a1, 120(sp) +80001e74: 83 25 05 00 lw a1, 0(a0) +80001e78: 13 65 45 00 ori a0, a0, 4 +80001e7c: 03 25 05 00 lw a0, 0(a0) +80001e80: 23 22 a1 0c sw a0, 196(sp) +80001e84: 23 20 b1 0c sw a1, 192(sp) +80001e88: 6f 00 00 14 j 320 +80001e8c: 6f 00 40 00 j 4 +80001e90: 13 85 45 00 addi a0, a1, 4 +80001e94: 23 2c a1 06 sw a0, 120(sp) +80001e98: 03 a5 05 00 lw a0, 0(a1) +80001e9c: 83 25 05 00 lw a1, 0(a0) +80001ea0: 03 27 45 00 lw a4, 4(a0) +80001ea4: 83 27 85 00 lw a5, 8(a0) +80001ea8: 03 25 c5 00 lw a0, 12(a0) +80001eac: 23 26 a1 0c sw a0, 204(sp) +80001eb0: 23 24 f1 0c sw a5, 200(sp) +80001eb4: 23 22 e1 0c sw a4, 196(sp) +80001eb8: 23 20 b1 0c sw a1, 192(sp) +80001ebc: 6f 00 c0 10 j 268 +80001ec0: 13 85 45 00 addi a0, a1, 4 +80001ec4: 23 2c a1 06 sw a0, 120(sp) +80001ec8: 03 a5 05 00 lw a0, 0(a1) +80001ecc: 03 28 05 00 lw a6, 0(a0) +80001ed0: 83 28 45 00 lw a7, 4(a0) +80001ed4: 83 22 85 00 lw t0, 8(a0) +80001ed8: 03 23 c5 00 lw t1, 12(a0) +80001edc: 03 27 05 01 lw a4, 16(a0) +80001ee0: 83 27 45 01 lw a5, 20(a0) +80001ee4: 83 25 85 01 lw a1, 24(a0) +80001ee8: 03 25 c5 01 lw a0, 28(a0) +80001eec: 23 2e a1 0c sw a0, 220(sp) +80001ef0: 23 2c b1 0c sw a1, 216(sp) +80001ef4: 23 2a f1 0c sw a5, 212(sp) +80001ef8: 23 28 e1 0c sw a4, 208(sp) +80001efc: 23 26 61 0c sw t1, 204(sp) +80001f00: 23 24 51 0c sw t0, 200(sp) +80001f04: 23 22 11 0d sw a7, 196(sp) +80001f08: 23 20 01 0d sw a6, 192(sp) +80001f0c: 6f 00 c0 0b j 188 +80001f10: 13 85 45 00 addi a0, a1, 4 +80001f14: 23 2c a1 06 sw a0, 120(sp) +80001f18: 03 a5 05 00 lw a0, 0(a1) +80001f1c: 83 25 05 00 lw a1, 0(a0) +80001f20: 23 28 b1 06 sw a1, 112(sp) +80001f24: 83 25 45 00 lw a1, 4(a0) +80001f28: 23 22 b1 06 sw a1, 100(sp) +80001f2c: 83 25 85 00 lw a1, 8(a0) +80001f30: 23 2c b1 04 sw a1, 88(sp) +80001f34: 03 23 c5 00 lw t1, 12(a0) +80001f38: 83 23 05 01 lw t2, 16(a0) +80001f3c: 93 02 0e 00 mv t0, t3 +80001f40: 03 2e 45 01 lw t3, 20(a0) +80001f44: 83 2e 85 01 lw t4, 24(a0) +80001f48: 03 2f c5 01 lw t5, 28(a0) +80001f4c: 83 2f 05 02 lw t6, 32(a0) +80001f50: 83 20 45 02 lw ra, 36(a0) +80001f54: 83 28 85 02 lw a7, 40(a0) +80001f58: 03 28 c5 02 lw a6, 44(a0) +80001f5c: 83 27 05 03 lw a5, 48(a0) +80001f60: 13 87 06 00 mv a4, a3 +80001f64: 83 26 45 03 lw a3, 52(a0) +80001f68: 83 25 85 03 lw a1, 56(a0) +80001f6c: 03 25 c5 03 lw a0, 60(a0) +80001f70: 23 2e a1 0e sw a0, 252(sp) +80001f74: 23 2c b1 0e sw a1, 248(sp) +80001f78: 23 2a d1 0e sw a3, 244(sp) +80001f7c: 93 06 07 00 mv a3, a4 +80001f80: 23 28 f1 0e sw a5, 240(sp) +80001f84: 23 26 01 0f sw a6, 236(sp) +80001f88: 23 24 11 0f sw a7, 232(sp) +80001f8c: 23 22 11 0e sw ra, 228(sp) +80001f90: 23 20 f1 0f sw t6, 224(sp) +80001f94: 23 2e e1 0d sw t5, 220(sp) +80001f98: 23 2c d1 0d sw t4, 216(sp) +80001f9c: 23 2a c1 0d sw t3, 212(sp) +80001fa0: 13 8e 02 00 mv t3, t0 +80001fa4: 23 28 71 0c sw t2, 208(sp) +80001fa8: 23 26 61 0c sw t1, 204(sp) +80001fac: 03 25 81 05 lw a0, 88(sp) +80001fb0: 23 24 a1 0c sw a0, 200(sp) +80001fb4: 03 25 41 06 lw a0, 100(sp) +80001fb8: 23 22 a1 0c sw a0, 196(sp) +80001fbc: 03 25 01 07 lw a0, 112(sp) +80001fc0: 23 20 a1 0c sw a0, 192(sp) +80001fc4: 6f 00 40 00 j 4 +80001fc8: 13 85 04 00 mv a0, s1 +80001fcc: 93 05 0e 00 mv a1, t3 +80001fd0: 97 f0 ff ff auipc ra, 1048575 +80001fd4: e7 80 80 c0 jalr -1016(ra) +80001fd8: 13 0e 01 0c addi t3, sp, 192 +80001fdc: 93 03 c1 15 addi t2, sp, 348 +80001fe0: 93 0e 01 12 addi t4, sp, 288 +80001fe4: 13 0f 01 14 addi t5, sp, 320 +80001fe8: 93 0f 01 08 addi t6, sp, 128 +80001fec: 93 00 d1 15 addi ra, sp, 349 +80001ff0: 83 25 81 07 lw a1, 120(sp) +80001ff4: 6f 00 00 49 j 1168 +80001ff8: 13 05 a0 00 addi a0, zero, 10 +80001ffc: 23 20 a9 00 sw a0, 0(s2) +80002000: 13 75 f7 0f andi a0, a4, 255 +80002004: 93 06 70 05 addi a3, zero, 87 +80002008: 63 f4 a6 00 bgeu a3, a0, 8 +8000200c: 6f 00 80 01 j 24 +80002010: 13 e5 8a 00 ori a0, s5, 8 +80002014: 23 00 ad 00 sb a0, 0(s10) +80002018: 13 05 07 02 addi a0, a4, 32 +8000201c: 23 80 ad 00 sb a0, 0(s11) +80002020: 6f 00 40 00 j 4 +80002024: 6f 00 40 00 j 4 +80002028: 13 05 80 00 addi a0, zero, 8 +8000202c: 23 2e 21 07 sw s2, 124(sp) +80002030: 63 4a a6 00 blt a2, a0, 20 +80002034: 6f 00 40 00 j 4 +80002038: 13 05 00 01 addi a0, zero, 16 +8000203c: 63 48 a6 08 blt a2, a0, 144 +80002040: 6f 00 c0 0d j 220 +80002044: 13 05 20 00 addi a0, zero, 2 +80002048: 63 4a a6 00 blt a2, a0, 20 +8000204c: 6f 00 40 00 j 4 +80002050: 13 05 20 00 addi a0, zero, 2 +80002054: 63 0e a6 00 beq a2, a0, 28 +80002058: 6f 00 00 04 j 64 +8000205c: 13 85 45 00 addi a0, a1, 4 +80002060: 23 2c a1 06 sw a0, 120(sp) +80002064: 07 a0 05 00 flw ft0, 0(a1) +80002068: 27 20 01 08 fsw ft0, 128(sp) +8000206c: 6f 00 00 14 j 320 +80002070: 13 85 75 00 addi a0, a1, 7 +80002074: 13 75 85 ff andi a0, a0, -8 +80002078: 93 05 85 00 addi a1, a0, 8 +8000207c: 23 2c b1 06 sw a1, 120(sp) +80002080: 07 20 05 00 flw ft0, 0(a0) +80002084: 13 65 45 00 ori a0, a0, 4 +80002088: 87 20 05 00 flw ft1, 0(a0) +8000208c: 27 22 11 08 fsw ft1, 132(sp) +80002090: 27 20 01 08 fsw ft0, 128(sp) +80002094: 6f 00 80 11 j 280 +80002098: 6f 00 40 00 j 4 +8000209c: 13 85 45 00 addi a0, a1, 4 +800020a0: 23 2c a1 06 sw a0, 120(sp) +800020a4: 03 a5 05 00 lw a0, 0(a1) +800020a8: 07 20 05 00 flw ft0, 0(a0) +800020ac: 87 20 45 00 flw ft1, 4(a0) +800020b0: 07 21 85 00 flw ft2, 8(a0) +800020b4: 87 21 c5 00 flw ft3, 12(a0) +800020b8: 27 26 31 08 fsw ft3, 140(sp) +800020bc: 27 24 21 08 fsw ft2, 136(sp) +800020c0: 27 22 11 08 fsw ft1, 132(sp) +800020c4: 27 20 01 08 fsw ft0, 128(sp) +800020c8: 6f 00 40 0e j 228 +800020cc: 13 85 45 00 addi a0, a1, 4 +800020d0: 23 2c a1 06 sw a0, 120(sp) +800020d4: 03 a5 05 00 lw a0, 0(a1) +800020d8: 07 20 05 00 flw ft0, 0(a0) +800020dc: 87 20 45 00 flw ft1, 4(a0) +800020e0: 07 21 85 00 flw ft2, 8(a0) +800020e4: 87 21 c5 00 flw ft3, 12(a0) +800020e8: 07 22 05 01 flw ft4, 16(a0) +800020ec: 87 22 45 01 flw ft5, 20(a0) +800020f0: 07 23 85 01 flw ft6, 24(a0) +800020f4: 87 23 c5 01 flw ft7, 28(a0) +800020f8: 27 2e 71 08 fsw ft7, 156(sp) +800020fc: 27 2c 61 08 fsw ft6, 152(sp) +80002100: 27 2a 51 08 fsw ft5, 148(sp) +80002104: 27 28 41 08 fsw ft4, 144(sp) +80002108: 27 26 31 08 fsw ft3, 140(sp) +8000210c: 27 24 21 08 fsw ft2, 136(sp) +80002110: 27 22 11 08 fsw ft1, 132(sp) +80002114: 27 20 01 08 fsw ft0, 128(sp) +80002118: 6f 00 40 09 j 148 +8000211c: 13 85 45 00 addi a0, a1, 4 +80002120: 23 2c a1 06 sw a0, 120(sp) +80002124: 03 a5 05 00 lw a0, 0(a1) +80002128: 07 20 05 00 flw ft0, 0(a0) +8000212c: 87 20 45 00 flw ft1, 4(a0) +80002130: 07 21 85 00 flw ft2, 8(a0) +80002134: 87 21 c5 00 flw ft3, 12(a0) +80002138: 07 22 05 01 flw ft4, 16(a0) +8000213c: 87 22 45 01 flw ft5, 20(a0) +80002140: 07 23 85 01 flw ft6, 24(a0) +80002144: 87 23 c5 01 flw ft7, 28(a0) +80002148: 07 25 05 02 flw fa0, 32(a0) +8000214c: 87 25 45 02 flw fa1, 36(a0) +80002150: 07 26 85 02 flw fa2, 40(a0) +80002154: 87 26 c5 02 flw fa3, 44(a0) +80002158: 07 27 05 03 flw fa4, 48(a0) +8000215c: 87 27 45 03 flw fa5, 52(a0) +80002160: 07 28 85 03 flw fa6, 56(a0) +80002164: 87 28 c5 03 flw fa7, 60(a0) +80002168: 27 2e 11 0b fsw fa7, 188(sp) +8000216c: 27 2c 01 0b fsw fa6, 184(sp) +80002170: 27 2a f1 0a fsw fa5, 180(sp) +80002174: 27 28 e1 0a fsw fa4, 176(sp) +80002178: 27 26 d1 0a fsw fa3, 172(sp) +8000217c: 27 24 c1 0a fsw fa2, 168(sp) +80002180: 27 22 b1 0a fsw fa1, 164(sp) +80002184: 27 20 a1 0a fsw fa0, 160(sp) +80002188: 27 2e 71 08 fsw ft7, 156(sp) +8000218c: 27 2c 61 08 fsw ft6, 152(sp) +80002190: 27 2a 51 08 fsw ft5, 148(sp) +80002194: 27 28 41 08 fsw ft4, 144(sp) +80002198: 27 26 31 08 fsw ft3, 140(sp) +8000219c: 27 24 21 08 fsw ft2, 136(sp) +800021a0: 27 22 11 08 fsw ft1, 132(sp) +800021a4: 27 20 01 08 fsw ft0, 128(sp) +800021a8: 6f 00 40 00 j 4 +800021ac: 13 85 04 00 mv a0, s1 +800021b0: 93 85 0f 00 mv a1, t6 +800021b4: 13 89 0f 00 mv s2, t6 +800021b8: 97 f0 ff ff auipc ra, 1048575 +800021bc: e7 80 80 ed jalr -296(ra) +800021c0: 93 0f 09 00 mv t6, s2 +800021c4: 93 03 c1 15 addi t2, sp, 348 +800021c8: 13 0e 01 0c addi t3, sp, 192 +800021cc: 93 0e 01 12 addi t4, sp, 288 +800021d0: 13 0f 01 14 addi t5, sp, 320 +800021d4: 03 29 c1 07 lw s2, 124(sp) +800021d8: 93 00 d1 15 addi ra, sp, 349 +800021dc: 83 25 81 07 lw a1, 120(sp) +800021e0: 6f 00 40 2a j 676 +800021e4: 13 f5 3a 05 andi a0, s5, 83 +800021e8: 13 35 15 00 seqz a0, a0 +800021ec: 93 26 08 00 slti a3, a6, 0 +800021f0: 33 75 d5 00 and a0, a0, a3 +800021f4: 13 46 16 00 xori a2, a2, 1 +800021f8: 13 36 16 00 seqz a2, a2 +800021fc: 33 75 c5 00 and a0, a0, a2 +80002200: 33 75 55 00 and a0, a0, t0 +80002204: 93 07 50 02 addi a5, zero, 37 +80002208: 13 06 10 00 addi a2, zero, 1 +8000220c: 63 16 c5 4e bne a0, a2, 1260 +80002210: 6f 00 40 00 j 4 +80002214: 13 85 45 00 addi a0, a1, 4 +80002218: 23 2c a1 06 sw a0, 120(sp) +8000221c: 03 a5 05 00 lw a0, 0(a1) +80002220: 23 80 a3 00 sb a0, 0(t2) +80002224: 23 80 00 00 sb zero, 0(ra) +80002228: 13 85 04 00 mv a0, s1 +8000222c: 97 e0 ff ff auipc ra, 1048574 +80002230: e7 80 c0 e6 jalr -404(ra) +80002234: 83 25 81 07 lw a1, 120(sp) +80002238: 93 00 d1 15 addi ra, sp, 349 +8000223c: 93 0f 01 08 addi t6, sp, 128 +80002240: 13 0f 01 14 addi t5, sp, 320 +80002244: 93 0e 01 12 addi t4, sp, 288 +80002248: 13 0e 01 0c addi t3, sp, 192 +8000224c: 93 03 c1 15 addi t2, sp, 348 +80002250: 6f 00 40 23 j 564 +80002254: 13 f5 3a 05 andi a0, s5, 83 +80002258: 93 07 60 02 addi a5, zero, 38 +8000225c: 63 1e 05 48 bnez a0, 1180 +80002260: 6f 00 40 00 j 4 +80002264: 13 45 16 00 xori a0, a2, 1 +80002268: 33 35 a0 00 snez a0, a0 +8000226c: 93 c6 12 00 xori a3, t0, 1 +80002270: 13 07 10 00 addi a4, zero, 1 +80002274: 63 04 e6 00 beq a2, a4, 8 +80002278: 6f 00 c0 42 j 1068 +8000227c: 13 f6 16 00 andi a2, a3, 1 +80002280: 63 12 06 42 bnez a2, 1060 +80002284: 6f 00 40 00 j 4 +80002288: 13 87 45 00 addi a4, a1, 4 +8000228c: 03 a5 05 00 lw a0, 0(a1) +80002290: 63 1c 05 08 bnez a0, 152 +80002294: 6f 00 40 00 j 4 +80002298: 37 05 00 80 lui a0, 524288 +8000229c: 13 05 f5 ff addi a0, a0, -1 +800022a0: 63 64 a8 00 bltu a6, a0, 8 +800022a4: 13 08 05 00 mv a6, a0 +800022a8: 63 04 08 68 beqz a6, 1672 +800022ac: 6f 00 40 00 j 4 +800022b0: 03 25 0b 00 lw a0, 0(s6) +800022b4: 83 25 0c 00 lw a1, 0(s8) +800022b8: 63 72 b5 02 bgeu a0, a1, 36 +800022bc: 6f 00 40 00 j 4 +800022c0: 83 a5 0b 00 lw a1, 0(s7) +800022c4: 13 06 15 00 addi a2, a0, 1 +800022c8: 23 20 cb 00 sw a2, 0(s6) +800022cc: 33 85 a5 00 add a0, a1, a0 +800022d0: 93 05 80 02 addi a1, zero, 40 +800022d4: 23 00 b5 00 sb a1, 0(a0) +800022d8: 6f 00 40 00 j 4 +800022dc: 13 05 10 00 addi a0, zero, 1 +800022e0: 63 62 05 55 bltu a0, a6, 1348 +800022e4: 6f 00 c0 64 j 1612 +800022e8: 63 7a 05 03 bgeu a0, a6, 52 +800022ec: 6f 00 40 00 j 4 +800022f0: 83 25 0b 00 lw a1, 0(s6) +800022f4: 03 26 0c 00 lw a2, 0(s8) +800022f8: 63 f2 c5 02 bgeu a1, a2, 36 +800022fc: 6f 00 40 00 j 4 +80002300: 03 a6 0b 00 lw a2, 0(s7) +80002304: 93 86 15 00 addi a3, a1, 1 +80002308: 23 20 db 00 sw a3, 0(s6) +8000230c: b3 05 b6 00 add a1, a2, a1 +80002310: 13 06 00 02 addi a2, zero, 32 +80002314: 23 80 c5 00 sb a2, 0(a1) +80002318: 6f 00 40 00 j 4 +8000231c: 13 05 15 00 addi a0, a0, 1 +80002320: 63 06 65 14 beq a0, t1, 332 +80002324: 6f f0 5f fc j -60 +80002328: 93 08 07 00 mv a7, a4 +8000232c: 13 f6 4a 00 andi a2, s5, 4 +80002330: b7 05 00 80 lui a1, 524288 +80002334: 93 85 f5 ff addi a1, a1, -1 +80002338: 63 64 b8 00 bltu a6, a1, 8 +8000233c: 13 88 05 00 mv a6, a1 +80002340: 83 45 05 00 lbu a1, 0(a0) +80002344: 93 b6 15 00 seqz a3, a1 +80002348: 63 0c 06 0a beqz a2, 184 +8000234c: 6f 00 40 00 j 4 +80002350: 93 f6 16 00 andi a3, a3, 1 +80002354: 13 06 00 00 mv a2, zero +80002358: 63 9a 06 00 bnez a3, 20 +8000235c: 6f 00 40 00 j 4 +80002360: 13 06 00 00 mv a2, zero +80002364: 6f 00 80 01 j 24 +80002368: 6f 00 40 00 j 4 +8000236c: 63 66 66 00 bltu a2, t1, 12 +80002370: 93 85 08 00 mv a1, a7 +80002374: 6f 00 00 11 j 272 +80002378: 6f 00 80 04 j 72 +8000237c: 13 05 15 00 addi a0, a0, 1 +80002380: 63 78 06 03 bgeu a2, a6, 48 +80002384: 6f 00 40 00 j 4 +80002388: 83 26 0b 00 lw a3, 0(s6) +8000238c: 03 27 0c 00 lw a4, 0(s8) +80002390: 63 f0 e6 02 bgeu a3, a4, 32 +80002394: 6f 00 40 00 j 4 +80002398: 03 a7 0b 00 lw a4, 0(s7) +8000239c: 93 87 16 00 addi a5, a3, 1 +800023a0: 23 20 fb 00 sw a5, 0(s6) +800023a4: b3 06 d7 00 add a3, a4, a3 +800023a8: 23 80 b6 00 sb a1, 0(a3) +800023ac: 6f 00 40 00 j 4 +800023b0: 13 06 16 00 addi a2, a2, 1 +800023b4: 83 45 05 00 lbu a1, 0(a0) +800023b8: e3 88 05 fa beqz a1, -80 +800023bc: 6f f0 1f fc j -64 +800023c0: 63 7a 06 03 bgeu a2, a6, 52 +800023c4: 6f 00 40 00 j 4 +800023c8: 03 25 0b 00 lw a0, 0(s6) +800023cc: 83 25 0c 00 lw a1, 0(s8) +800023d0: 63 72 b5 02 bgeu a0, a1, 36 +800023d4: 6f 00 40 00 j 4 +800023d8: 83 a5 0b 00 lw a1, 0(s7) +800023dc: 93 06 15 00 addi a3, a0, 1 +800023e0: 23 20 db 00 sw a3, 0(s6) +800023e4: 33 85 a5 00 add a0, a1, a0 +800023e8: 93 05 00 02 addi a1, zero, 32 +800023ec: 23 00 b5 00 sb a1, 0(a0) +800023f0: 6f 00 40 00 j 4 +800023f4: 13 06 16 00 addi a2, a2, 1 +800023f8: 63 02 66 08 beq a2, t1, 132 +800023fc: 6f f0 5f fc j -60 +80002400: 13 f6 16 00 andi a2, a3, 1 +80002404: 93 06 00 00 mv a3, zero +80002408: 63 1c 06 00 bnez a2, 24 +8000240c: 6f 00 40 00 j 4 +80002410: 13 06 05 00 mv a2, a0 +80002414: 93 06 00 00 mv a3, zero +80002418: 6f 00 00 02 j 32 +8000241c: 6f 00 40 00 j 4 +80002420: 13 06 00 00 mv a2, zero +80002424: 63 fa 66 02 bgeu a3, t1, 52 +80002428: 6f 00 40 00 j 4 +8000242c: 33 06 d3 40 sub a2, t1, a3 +80002430: 93 05 00 00 mv a1, zero +80002434: 6f 00 40 05 j 84 +80002438: 13 07 16 00 addi a4, a2, 1 +8000243c: 93 86 16 00 addi a3, a3, 1 +80002440: 83 47 16 00 lbu a5, 1(a2) +80002444: 13 06 07 00 mv a2, a4 +80002448: e3 8a 07 fc beqz a5, -44 +8000244c: 6f f0 df fe j -20 +80002450: 83 45 05 00 lbu a1, 0(a0) +80002454: 6f 00 40 00 j 4 +80002458: 93 f6 f5 0f andi a3, a1, 255 +8000245c: 63 96 06 00 bnez a3, 12 +80002460: 93 85 08 00 mv a1, a7 +80002464: 6f 00 00 02 j 32 +80002468: 6f 00 00 06 j 96 +8000246c: 93 05 07 00 mv a1, a4 +80002470: 6f 00 40 01 j 20 +80002474: 93 85 08 00 mv a1, a7 +80002478: 6f 00 c0 00 j 12 +8000247c: 93 85 08 00 mv a1, a7 +80002480: 6f 00 40 00 j 4 +80002484: 6f e0 9f ea j -4440 +80002488: 63 fa 05 03 bgeu a1, a6, 52 +8000248c: 6f 00 40 00 j 4 +80002490: 83 26 0b 00 lw a3, 0(s6) +80002494: 03 27 0c 00 lw a4, 0(s8) +80002498: 63 f2 e6 02 bgeu a3, a4, 36 +8000249c: 6f 00 40 00 j 4 +800024a0: 03 a7 0b 00 lw a4, 0(s7) +800024a4: 93 87 16 00 addi a5, a3, 1 +800024a8: 23 20 fb 00 sw a5, 0(s6) +800024ac: b3 06 d7 00 add a3, a4, a3 +800024b0: 13 07 00 02 addi a4, zero, 32 +800024b4: 23 80 e6 00 sb a4, 0(a3) +800024b8: 6f 00 40 00 j 4 +800024bc: 93 85 15 00 addi a1, a1, 1 +800024c0: e3 88 c5 f8 beq a1, a2, -112 +800024c4: 6f f0 5f fc j -60 +800024c8: 13 05 15 00 addi a0, a0, 1 +800024cc: 63 78 06 03 bgeu a2, a6, 48 +800024d0: 6f 00 40 00 j 4 +800024d4: 83 26 0b 00 lw a3, 0(s6) +800024d8: 03 27 0c 00 lw a4, 0(s8) +800024dc: 63 f0 e6 02 bgeu a3, a4, 32 +800024e0: 6f 00 40 00 j 4 +800024e4: 03 a7 0b 00 lw a4, 0(s7) +800024e8: 93 87 16 00 addi a5, a3, 1 +800024ec: 23 20 fb 00 sw a5, 0(s6) +800024f0: b3 06 d7 00 add a3, a4, a3 +800024f4: 23 80 b6 00 sb a1, 0(a3) +800024f8: 6f 00 40 00 j 4 +800024fc: 13 06 16 00 addi a2, a2, 1 +80002500: 83 45 05 00 lbu a1, 0(a0) +80002504: e3 88 05 f6 beqz a1, -144 +80002508: 6f f0 1f fc j -64 +8000250c: 13 f5 3a 05 andi a0, s5, 83 +80002510: 93 07 90 02 addi a5, zero, 41 +80002514: 63 12 05 1e bnez a0, 484 +80002518: 6f 00 40 00 j 4 +8000251c: 93 07 00 03 addi a5, zero, 48 +80002520: 13 05 f0 ff addi a0, zero, -1 +80002524: 63 4a 05 1d blt a0, a6, 468 +80002528: 6f 00 40 00 j 4 +8000252c: 13 45 16 00 xori a0, a2, 1 +80002530: 33 35 a0 00 snez a0, a0 +80002534: 93 c6 12 00 xori a3, t0, 1 +80002538: 13 07 10 00 addi a4, zero, 1 +8000253c: 63 04 e6 00 beq a2, a4, 8 +80002540: 6f 00 80 17 j 376 +80002544: 13 f6 16 00 andi a2, a3, 1 +80002548: 63 18 06 16 bnez a2, 368 +8000254c: 6f 00 40 00 j 4 +80002550: 13 85 45 00 addi a0, a1, 4 +80002554: 23 2c a1 06 sw a0, 120(sp) +80002558: 83 a5 05 00 lw a1, 0(a1) +8000255c: 13 05 00 01 addi a0, zero, 16 +80002560: 23 2e 21 07 sw s2, 124(sp) +80002564: 23 20 a9 00 sw a0, 0(s2) +80002568: 13 f5 5a 05 andi a0, s5, 85 +8000256c: 13 65 25 08 ori a0, a0, 130 +80002570: 23 00 ad 00 sb a0, 0(s10) +80002574: 63 98 05 00 bnez a1, 16 +80002578: 6f 00 40 00 j 4 +8000257c: 83 a5 04 00 lw a1, 0(s1) +80002580: 6f 00 c0 0b j 188 +80002584: 13 06 00 00 mv a2, zero +80002588: 6f 00 40 00 j 4 +8000258c: 13 f7 f5 00 andi a4, a1, 15 +80002590: 93 d5 45 00 srli a1, a1, 4 +80002594: 93 66 07 03 ori a3, a4, 48 +80002598: 13 05 77 05 addi a0, a4, 87 +8000259c: 93 07 a0 00 addi a5, zero, 10 +800025a0: 63 64 f7 00 bltu a4, a5, 8 +800025a4: 93 06 05 00 mv a3, a0 +800025a8: 13 05 16 00 addi a0, a2, 1 +800025ac: 13 07 c1 60 addi a4, sp, 1548 +800025b0: 33 06 c7 00 add a2, a4, a2 +800025b4: 23 00 d6 00 sb a3, 0(a2) +800025b8: 13 06 05 00 mv a2, a0 +800025bc: e3 98 05 fc bnez a1, -48 +800025c0: 6f 00 40 00 j 4 +800025c4: 93 05 10 00 addi a1, zero, 1 +800025c8: 63 4a b8 00 blt a6, a1, 20 +800025cc: 6f 00 40 00 j 4 +800025d0: 63 76 05 01 bgeu a0, a6, 12 +800025d4: 6f 00 40 00 j 4 +800025d8: 6f 00 c0 00 j 12 +800025dc: 83 a5 04 00 lw a1, 0(s1) +800025e0: 6f 00 00 03 j 48 +800025e4: 93 05 c1 60 addi a1, sp, 1548 +800025e8: b3 85 a5 00 add a1, a1, a0 +800025ec: 13 06 00 03 addi a2, zero, 48 +800025f0: 23 80 c5 00 sb a2, 0(a1) +800025f4: 13 05 15 00 addi a0, a0, 1 +800025f8: e3 16 05 ff bne a0, a6, -20 +800025fc: 6f 00 40 00 j 4 +80002600: 83 a5 04 00 lw a1, 0(s1) +80002604: 13 05 08 00 mv a0, a6 +80002608: 63 0a 08 02 beqz a6, 52 +8000260c: 6f 00 40 00 j 4 +80002610: 6f 00 40 00 j 4 +80002614: 13 86 05 00 mv a2, a1 +80002618: 13 05 f5 ff addi a0, a0, -1 +8000261c: 93 05 c1 60 addi a1, sp, 1548 +80002620: b3 85 a5 00 add a1, a1, a0 +80002624: 83 86 05 00 lb a3, 0(a1) +80002628: 93 05 16 00 addi a1, a2, 1 +8000262c: 23 00 d6 00 sb a3, 0(a2) +80002630: e3 12 05 fe bnez a0, -28 +80002634: 6f 00 40 00 j 4 +80002638: 6f 00 40 00 j 4 +8000263c: 23 80 05 00 sb zero, 0(a1) +80002640: 13 85 04 00 mv a0, s1 +80002644: 97 e0 ff ff auipc ra, 1048574 +80002648: e7 80 40 a5 jalr -1452(ra) +8000264c: 93 03 c1 15 addi t2, sp, 348 +80002650: 13 0e 01 0c addi t3, sp, 192 +80002654: 93 0e 01 12 addi t4, sp, 288 +80002658: 13 0f 01 14 addi t5, sp, 320 +8000265c: 93 0f 01 08 addi t6, sp, 128 +80002660: 03 29 c1 07 lw s2, 124(sp) +80002664: 93 00 d1 15 addi ra, sp, 349 +80002668: 83 25 81 07 lw a1, 120(sp) +8000266c: 6f f0 9f e1 j -488 +80002670: 6f 00 40 00 j 4 +80002674: 03 26 0b 00 lw a2, 0(s6) +80002678: 03 27 0c 00 lw a4, 0(s8) +8000267c: 63 68 e6 00 bltu a2, a4, 16 +80002680: 6f 00 40 00 j 4 +80002684: 93 8c 06 00 mv s9, a3 +80002688: 6f e0 9f ca j -4952 +8000268c: 03 a7 0b 00 lw a4, 0(s7) +80002690: 93 07 16 00 addi a5, a2, 1 +80002694: 23 20 fb 00 sw a5, 0(s6) +80002698: 33 06 c7 00 add a2, a4, a2 +8000269c: 23 00 a6 00 sb a0, 0(a2) +800026a0: 6f f0 5f fe j -28 +800026a4: 13 75 15 00 andi a0, a0, 1 +800026a8: 93 07 70 02 addi a5, zero, 39 +800026ac: 63 14 05 00 bnez a0, 8 +800026b0: 93 07 80 02 addi a5, zero, 40 +800026b4: 6f 00 80 04 j 72 +800026b8: 13 75 15 00 andi a0, a0, 1 +800026bc: 93 07 10 03 addi a5, zero, 49 +800026c0: 63 14 05 00 bnez a0, 8 +800026c4: 93 07 20 03 addi a5, zero, 50 +800026c8: 6f 00 40 03 j 52 +800026cc: 6f 00 00 03 j 48 +800026d0: 93 07 90 01 addi a5, zero, 25 +800026d4: 6f 00 80 02 j 40 +800026d8: 6f 00 40 02 j 36 +800026dc: 6f 00 00 02 j 32 +800026e0: 93 07 10 01 addi a5, zero, 17 +800026e4: 6f 00 80 01 j 24 +800026e8: 93 07 20 02 addi a5, zero, 34 +800026ec: 6f 00 c0 00 j 12 +800026f0: 93 07 30 03 addi a5, zero, 51 +800026f4: 6f 00 40 00 j 4 +800026f8: 6f 00 40 00 j 4 +800026fc: 37 55 01 80 lui a0, 524309 +80002700: 13 05 25 54 addi a0, a0, 1346 +80002704: 93 05 00 02 addi a1, zero, 32 +80002708: 6f 00 40 00 j 4 +8000270c: 13 05 15 00 addi a0, a0, 1 +80002710: 03 26 0b 00 lw a2, 0(s6) +80002714: 83 26 0c 00 lw a3, 0(s8) +80002718: 63 70 d6 02 bgeu a2, a3, 32 +8000271c: 6f 00 40 00 j 4 +80002720: 83 a6 0b 00 lw a3, 0(s7) +80002724: 13 07 16 00 addi a4, a2, 1 +80002728: 23 20 eb 00 sw a4, 0(s6) +8000272c: 33 86 c6 00 add a2, a3, a2 +80002730: 23 00 b6 00 sb a1, 0(a2) +80002734: 6f 00 40 00 j 4 +80002738: 83 45 05 00 lbu a1, 0(a0) +8000273c: 37 56 01 80 lui a2, 524309 +80002740: 13 06 26 54 addi a2, a2, 1346 +80002744: 13 06 f6 01 addi a2, a2, 31 +80002748: e3 12 c5 fc bne a0, a2, -60 +8000274c: 6f 00 40 00 j 4 +80002750: 13 f5 77 00 andi a0, a5, 7 +80002754: 93 65 05 03 ori a1, a0, 48 +80002758: 03 25 0b 00 lw a0, 0(s6) +8000275c: 03 26 0c 00 lw a2, 0(s8) +80002760: 63 64 c5 00 bltu a0, a2, 8 +80002764: 6f 00 c0 02 j 44 +80002768: 13 d6 47 00 srli a2, a5, 4 +8000276c: 13 66 06 03 ori a2, a2, 48 +80002770: 83 a6 0b 00 lw a3, 0(s7) +80002774: 13 07 15 00 addi a4, a0, 1 +80002778: 23 20 eb 00 sw a4, 0(s6) +8000277c: 33 85 a6 00 add a0, a3, a0 +80002780: 23 00 c5 00 sb a2, 0(a0) +80002784: 03 25 0b 00 lw a0, 0(s6) +80002788: 03 26 0c 00 lw a2, 0(s8) +8000278c: 6f 00 40 00 j 4 +80002790: 63 64 c5 00 bltu a0, a2, 8 +80002794: 6f 00 40 02 j 36 +80002798: 03 a6 0b 00 lw a2, 0(s7) +8000279c: 93 06 15 00 addi a3, a0, 1 +800027a0: 23 20 db 00 sw a3, 0(s6) +800027a4: 33 05 a6 00 add a0, a2, a0 +800027a8: 23 00 b5 00 sb a1, 0(a0) +800027ac: 03 25 0b 00 lw a0, 0(s6) +800027b0: 03 26 0c 00 lw a2, 0(s8) +800027b4: 6f 00 40 00 j 4 +800027b8: 63 74 c5 02 bgeu a0, a2, 40 +800027bc: 6f 00 40 00 j 4 +800027c0: 83 a5 0b 00 lw a1, 0(s7) +800027c4: 13 06 15 00 addi a2, a0, 1 +800027c8: 23 20 cb 00 sw a2, 0(s6) +800027cc: 33 85 a5 00 add a0, a1, a0 +800027d0: 93 05 a0 00 addi a1, zero, 10 +800027d4: 23 00 b5 00 sb a1, 0(a0) +800027d8: 6f 00 80 00 j 8 +800027dc: 6f 00 80 00 j 8 +800027e0: 6f 00 40 00 j 4 +800027e4: 13 01 04 98 addi sp, s0, -1664 +800027e8: 83 2d c1 64 lw s11, 1612(sp) +800027ec: 03 2d 01 65 lw s10, 1616(sp) +800027f0: 83 2c 41 65 lw s9, 1620(sp) +800027f4: 03 2c 81 65 lw s8, 1624(sp) +800027f8: 83 2b c1 65 lw s7, 1628(sp) +800027fc: 03 2b 01 66 lw s6, 1632(sp) +80002800: 83 2a 41 66 lw s5, 1636(sp) +80002804: 03 2a 81 66 lw s4, 1640(sp) +80002808: 83 29 c1 66 lw s3, 1644(sp) +8000280c: 03 29 01 67 lw s2, 1648(sp) +80002810: 83 24 41 67 lw s1, 1652(sp) +80002814: 03 24 81 67 lw s0, 1656(sp) +80002818: 83 20 c1 67 lw ra, 1660(sp) +8000281c: 13 01 01 68 addi sp, sp, 1664 +80002820: 67 80 00 00 ret +80002824: 03 25 0b 00 lw a0, 0(s6) +80002828: 83 25 0c 00 lw a1, 0(s8) +8000282c: 63 72 b5 02 bgeu a0, a1, 36 +80002830: 6f 00 40 00 j 4 +80002834: 83 a5 0b 00 lw a1, 0(s7) +80002838: 13 06 15 00 addi a2, a0, 1 +8000283c: 23 20 cb 00 sw a2, 0(s6) +80002840: 33 85 a5 00 add a0, a1, a0 +80002844: 93 05 e0 06 addi a1, zero, 110 +80002848: 23 00 b5 00 sb a1, 0(a0) +8000284c: 6f 00 40 00 j 4 +80002850: 13 05 30 00 addi a0, zero, 3 +80002854: 63 6e a8 0c bltu a6, a0, 220 +80002858: 6f 00 40 00 j 4 +8000285c: 03 25 0b 00 lw a0, 0(s6) +80002860: 83 25 0c 00 lw a1, 0(s8) +80002864: 63 72 b5 02 bgeu a0, a1, 36 +80002868: 6f 00 40 00 j 4 +8000286c: 83 a5 0b 00 lw a1, 0(s7) +80002870: 13 06 15 00 addi a2, a0, 1 +80002874: 23 20 cb 00 sw a2, 0(s6) +80002878: 33 85 a5 00 add a0, a1, a0 +8000287c: 93 05 50 07 addi a1, zero, 117 +80002880: 23 00 b5 00 sb a1, 0(a0) +80002884: 6f 00 40 00 j 4 +80002888: 13 05 40 00 addi a0, zero, 4 +8000288c: 63 62 a8 0a bltu a6, a0, 164 +80002890: 6f 00 40 00 j 4 +80002894: 03 25 0b 00 lw a0, 0(s6) +80002898: 83 25 0c 00 lw a1, 0(s8) +8000289c: 63 72 b5 02 bgeu a0, a1, 36 +800028a0: 6f 00 40 00 j 4 +800028a4: 83 a5 0b 00 lw a1, 0(s7) +800028a8: 13 06 15 00 addi a2, a0, 1 +800028ac: 23 20 cb 00 sw a2, 0(s6) +800028b0: 33 85 a5 00 add a0, a1, a0 +800028b4: 93 05 c0 06 addi a1, zero, 108 +800028b8: 23 00 b5 00 sb a1, 0(a0) +800028bc: 6f 00 40 00 j 4 +800028c0: 13 05 50 00 addi a0, zero, 5 +800028c4: 63 66 a8 06 bltu a6, a0, 108 +800028c8: 6f 00 40 00 j 4 +800028cc: 03 25 0b 00 lw a0, 0(s6) +800028d0: 83 25 0c 00 lw a1, 0(s8) +800028d4: 63 72 b5 02 bgeu a0, a1, 36 +800028d8: 6f 00 40 00 j 4 +800028dc: 83 a5 0b 00 lw a1, 0(s7) +800028e0: 13 06 15 00 addi a2, a0, 1 +800028e4: 23 20 cb 00 sw a2, 0(s6) +800028e8: 33 85 a5 00 add a0, a1, a0 +800028ec: 93 05 c0 06 addi a1, zero, 108 +800028f0: 23 00 b5 00 sb a1, 0(a0) +800028f4: 6f 00 40 00 j 4 +800028f8: 13 05 60 00 addi a0, zero, 6 +800028fc: 63 6a a8 02 bltu a6, a0, 52 +80002900: 6f 00 40 00 j 4 +80002904: 03 25 0b 00 lw a0, 0(s6) +80002908: 83 25 0c 00 lw a1, 0(s8) +8000290c: 63 72 b5 02 bgeu a0, a1, 36 +80002910: 6f 00 40 00 j 4 +80002914: 83 a5 0b 00 lw a1, 0(s7) +80002918: 13 06 15 00 addi a2, a0, 1 +8000291c: 23 20 cb 00 sw a2, 0(s6) +80002920: 33 85 a5 00 add a0, a1, a0 +80002924: 93 05 90 02 addi a1, zero, 41 +80002928: 23 00 b5 00 sb a1, 0(a0) +8000292c: 6f 00 40 00 j 4 +80002930: 13 05 70 00 addi a0, zero, 7 +80002934: 63 76 a3 00 bgeu t1, a0, 12 +80002938: 93 05 07 00 mv a1, a4 +8000293c: 6f f0 9f b4 j -1208 +80002940: 13 05 60 00 addi a0, zero, 6 +80002944: 6f f0 5f 9a j -1628 + +80002948 __pocl_printf: +80002948: 13 01 01 fc addi sp, sp, -64 +8000294c: 23 26 11 02 sw ra, 44(sp) +80002950: 23 24 81 02 sw s0, 40(sp) +80002954: 13 84 05 00 mv s0, a1 +80002958: 23 2e 11 03 sw a7, 60(sp) +8000295c: 23 2c 01 03 sw a6, 56(sp) +80002960: 23 2a f1 02 sw a5, 52(sp) +80002964: 23 28 e1 02 sw a4, 48(sp) +80002968: 23 22 01 02 sw zero, 36(sp) +8000296c: 23 20 01 02 sw zero, 32(sp) +80002970: 23 2e 01 00 sw zero, 28(sp) +80002974: 23 2c 01 00 sw zero, 24(sp) +80002978: 23 2a 01 00 sw zero, 20(sp) +8000297c: 23 28 01 00 sw zero, 16(sp) +80002980: 23 26 01 00 sw zero, 12(sp) +80002984: 23 24 01 00 sw zero, 8(sp) +80002988: 23 26 a1 00 sw a0, 12(sp) +8000298c: 23 2a c1 00 sw a2, 20(sp) +80002990: 03 25 04 00 lw a0, 0(s0) +80002994: 23 28 a1 00 sw a0, 16(sp) +80002998: 13 05 01 03 addi a0, sp, 48 +8000299c: 23 22 a1 00 sw a0, 4(sp) +800029a0: 83 25 41 00 lw a1, 4(sp) +800029a4: 13 05 81 00 addi a0, sp, 8 +800029a8: 97 f0 ff ff auipc ra, 1048575 +800029ac: e7 80 40 8f jalr -1804(ra) +800029b0: 03 25 01 01 lw a0, 16(sp) +800029b4: 23 20 a4 00 sw a0, 0(s0) +800029b8: 03 24 81 02 lw s0, 40(sp) +800029bc: 83 20 c1 02 lw ra, 44(sp) +800029c0: 13 01 01 04 addi sp, sp, 64 +800029c4: 67 80 00 00 ret + +800029c8 _pocl_kernel_oclprintf: +800029c8: 13 01 01 fc addi sp, sp, -64 +800029cc: 23 2e 11 02 sw ra, 60(sp) +800029d0: 23 2c 81 02 sw s0, 56(sp) +800029d4: 23 2a 91 02 sw s1, 52(sp) +800029d8: 23 28 21 03 sw s2, 48(sp) +800029dc: 23 26 31 03 sw s3, 44(sp) +800029e0: 23 24 41 03 sw s4, 40(sp) +800029e4: 23 22 51 03 sw s5, 36(sp) +800029e8: 23 20 61 03 sw s6, 32(sp) +800029ec: 23 2e 71 01 sw s7, 28(sp) +800029f0: 23 2c 81 01 sw s8, 24(sp) +800029f4: 23 2a 91 01 sw s9, 20(sp) +800029f8: 23 28 a1 01 sw s10, 16(sp) +800029fc: 23 26 b1 01 sw s11, 12(sp) +80002a00: 13 04 01 04 addi s0, sp, 64 +80002a04: 13 71 c1 ff andi sp, sp, -4 +80002a08: 13 0a 00 00 mv s4, zero +80002a0c: 83 aa 85 01 lw s5, 24(a1) +80002a10: 03 ab c5 01 lw s6, 28(a1) +80002a14: 83 a6 05 02 lw a3, 32(a1) +80002a18: 23 24 d1 00 sw a3, 8(sp) +80002a1c: 83 a6 c5 00 lw a3, 12(a1) +80002a20: 03 a9 45 02 lw s2, 36(a1) +80002a24: 83 a9 85 02 lw s3, 40(a1) +80002a28: 03 ac c5 02 lw s8, 44(a1) +80002a2c: b3 85 ca 02 mul a1, s5, a2 +80002a30: b3 8d b6 00 add s11, a3, a1 +80002a34: 93 95 2d 00 slli a1, s11, 2 +80002a38: b3 0b b5 00 add s7, a0, a1 +80002a3c: 13 0d 00 00 mv s10, zero +80002a40: 93 04 00 00 mv s1, zero +80002a44: 93 8c 0b 00 mv s9, s7 +80002a48: 83 a7 0c 00 lw a5, 0(s9) +80002a4c: 33 87 9d 00 add a4, s11, s1 +80002a50: 13 05 09 00 mv a0, s2 +80002a54: 93 85 09 00 mv a1, s3 +80002a58: 13 06 0c 00 mv a2, s8 +80002a5c: 97 00 00 00 auipc ra, 0 +80002a60: e7 80 c0 ee jalr -276(ra) +80002a64: 93 84 14 00 addi s1, s1, 1 +80002a68: 93 8c 4c 00 addi s9, s9, 4 +80002a6c: e3 ee 54 fd bltu s1, s5, -36 +80002a70: 13 0d 1d 00 addi s10, s10, 1 +80002a74: e3 66 6d fd bltu s10, s6, -52 +80002a78: 13 0a 1a 00 addi s4, s4, 1 +80002a7c: 03 25 81 00 lw a0, 8(sp) +80002a80: e3 6e aa fa bltu s4, a0, -68 +80002a84: 13 01 04 fc addi sp, s0, -64 +80002a88: 83 2d c1 00 lw s11, 12(sp) +80002a8c: 03 2d 01 01 lw s10, 16(sp) +80002a90: 83 2c 41 01 lw s9, 20(sp) +80002a94: 03 2c 81 01 lw s8, 24(sp) +80002a98: 83 2b c1 01 lw s7, 28(sp) +80002a9c: 03 2b 01 02 lw s6, 32(sp) +80002aa0: 83 2a 41 02 lw s5, 36(sp) +80002aa4: 03 2a 81 02 lw s4, 40(sp) +80002aa8: 83 29 c1 02 lw s3, 44(sp) +80002aac: 03 29 01 03 lw s2, 48(sp) +80002ab0: 83 24 41 03 lw s1, 52(sp) +80002ab4: 03 24 81 03 lw s0, 56(sp) +80002ab8: 83 20 c1 03 lw ra, 60(sp) +80002abc: 13 01 01 04 addi sp, sp, 64 +80002ac0: 67 80 00 00 ret + +80002ac4 _pocl_kernel_oclprintf_workgroup: +80002ac4: 13 01 01 fc addi sp, sp, -64 +80002ac8: 23 2e 11 02 sw ra, 60(sp) +80002acc: 23 2c 81 02 sw s0, 56(sp) +80002ad0: 23 2a 91 02 sw s1, 52(sp) +80002ad4: 23 28 21 03 sw s2, 48(sp) +80002ad8: 23 26 31 03 sw s3, 44(sp) +80002adc: 23 24 41 03 sw s4, 40(sp) +80002ae0: 23 22 51 03 sw s5, 36(sp) +80002ae4: 23 20 61 03 sw s6, 32(sp) +80002ae8: 23 2e 71 01 sw s7, 28(sp) +80002aec: 23 2c 81 01 sw s8, 24(sp) +80002af0: 23 2a 91 01 sw s9, 20(sp) +80002af4: 23 28 a1 01 sw s10, 16(sp) +80002af8: 23 26 b1 01 sw s11, 12(sp) +80002afc: 03 25 05 00 lw a0, 0(a0) +80002b00: 93 09 00 00 mv s3, zero +80002b04: 03 25 05 00 lw a0, 0(a0) +80002b08: 03 aa 85 01 lw s4, 24(a1) +80002b0c: 83 aa c5 01 lw s5, 28(a1) +80002b10: 03 ab 05 02 lw s6, 32(a1) +80002b14: 83 a6 c5 00 lw a3, 12(a1) +80002b18: 03 a9 45 02 lw s2, 36(a1) +80002b1c: 83 ab 85 02 lw s7, 40(a1) +80002b20: 03 ad c5 02 lw s10, 44(a1) +80002b24: b3 05 ca 02 mul a1, s4, a2 +80002b28: b3 8d b6 00 add s11, a3, a1 +80002b2c: 93 95 2d 00 slli a1, s11, 2 +80002b30: 33 0c b5 00 add s8, a0, a1 +80002b34: 93 0c 00 00 mv s9, zero +80002b38: 13 04 00 00 mv s0, zero +80002b3c: 93 04 0c 00 mv s1, s8 +80002b40: 83 a7 04 00 lw a5, 0(s1) +80002b44: 33 87 8d 00 add a4, s11, s0 +80002b48: 13 05 09 00 mv a0, s2 +80002b4c: 93 85 0b 00 mv a1, s7 +80002b50: 13 06 0d 00 mv a2, s10 +80002b54: 97 00 00 00 auipc ra, 0 +80002b58: e7 80 40 df jalr -524(ra) +80002b5c: 13 04 14 00 addi s0, s0, 1 +80002b60: 93 84 44 00 addi s1, s1, 4 +80002b64: e3 6e 44 fd bltu s0, s4, -36 +80002b68: 93 8c 1c 00 addi s9, s9, 1 +80002b6c: e3 e6 5c fd bltu s9, s5, -52 +80002b70: 93 89 19 00 addi s3, s3, 1 +80002b74: e3 e0 69 fd bltu s3, s6, -64 +80002b78: 83 2d c1 00 lw s11, 12(sp) +80002b7c: 03 2d 01 01 lw s10, 16(sp) +80002b80: 83 2c 41 01 lw s9, 20(sp) +80002b84: 03 2c 81 01 lw s8, 24(sp) +80002b88: 83 2b c1 01 lw s7, 28(sp) +80002b8c: 03 2b 01 02 lw s6, 32(sp) +80002b90: 83 2a 41 02 lw s5, 36(sp) +80002b94: 03 2a 81 02 lw s4, 40(sp) +80002b98: 83 29 c1 02 lw s3, 44(sp) +80002b9c: 03 29 01 03 lw s2, 48(sp) +80002ba0: 83 24 41 03 lw s1, 52(sp) +80002ba4: 03 24 81 03 lw s0, 56(sp) +80002ba8: 83 20 c1 03 lw ra, 60(sp) +80002bac: 13 01 01 04 addi sp, sp, 64 +80002bb0: 67 80 00 00 ret + +80002bb4 _pocl_kernel_oclprintf_workgroup_fast: +80002bb4: 13 01 01 fc addi sp, sp, -64 +80002bb8: 23 2e 11 02 sw ra, 60(sp) +80002bbc: 23 2c 81 02 sw s0, 56(sp) +80002bc0: 23 2a 91 02 sw s1, 52(sp) +80002bc4: 23 28 21 03 sw s2, 48(sp) +80002bc8: 23 26 31 03 sw s3, 44(sp) +80002bcc: 23 24 41 03 sw s4, 40(sp) +80002bd0: 23 22 51 03 sw s5, 36(sp) +80002bd4: 23 20 61 03 sw s6, 32(sp) +80002bd8: 23 2e 71 01 sw s7, 28(sp) +80002bdc: 23 2c 81 01 sw s8, 24(sp) +80002be0: 23 2a 91 01 sw s9, 20(sp) +80002be4: 23 28 a1 01 sw s10, 16(sp) +80002be8: 23 26 b1 01 sw s11, 12(sp) +80002bec: 93 09 00 00 mv s3, zero +80002bf0: 03 25 05 00 lw a0, 0(a0) +80002bf4: 03 aa 85 01 lw s4, 24(a1) +80002bf8: 83 aa c5 01 lw s5, 28(a1) +80002bfc: 03 ab 05 02 lw s6, 32(a1) +80002c00: 83 a6 c5 00 lw a3, 12(a1) +80002c04: 03 a9 45 02 lw s2, 36(a1) +80002c08: 83 ab 85 02 lw s7, 40(a1) +80002c0c: 03 ad c5 02 lw s10, 44(a1) +80002c10: b3 05 ca 02 mul a1, s4, a2 +80002c14: b3 8d b6 00 add s11, a3, a1 +80002c18: 93 95 2d 00 slli a1, s11, 2 +80002c1c: 33 0c b5 00 add s8, a0, a1 +80002c20: 93 0c 00 00 mv s9, zero +80002c24: 13 04 00 00 mv s0, zero +80002c28: 93 04 0c 00 mv s1, s8 +80002c2c: 83 a7 04 00 lw a5, 0(s1) +80002c30: 33 87 8d 00 add a4, s11, s0 +80002c34: 13 05 09 00 mv a0, s2 +80002c38: 93 85 0b 00 mv a1, s7 +80002c3c: 13 06 0d 00 mv a2, s10 +80002c40: 97 00 00 00 auipc ra, 0 +80002c44: e7 80 80 d0 jalr -760(ra) +80002c48: 13 04 14 00 addi s0, s0, 1 +80002c4c: 93 84 44 00 addi s1, s1, 4 +80002c50: e3 6e 44 fd bltu s0, s4, -36 +80002c54: 93 8c 1c 00 addi s9, s9, 1 +80002c58: e3 e6 5c fd bltu s9, s5, -52 +80002c5c: 93 89 19 00 addi s3, s3, 1 +80002c60: e3 e0 69 fd bltu s3, s6, -64 +80002c64: 83 2d c1 00 lw s11, 12(sp) +80002c68: 03 2d 01 01 lw s10, 16(sp) +80002c6c: 83 2c 41 01 lw s9, 20(sp) +80002c70: 03 2c 81 01 lw s8, 24(sp) +80002c74: 83 2b c1 01 lw s7, 28(sp) +80002c78: 03 2b 01 02 lw s6, 32(sp) +80002c7c: 83 2a 41 02 lw s5, 36(sp) +80002c80: 03 2a 81 02 lw s4, 40(sp) +80002c84: 83 29 c1 02 lw s3, 44(sp) +80002c88: 03 29 01 03 lw s2, 48(sp) +80002c8c: 83 24 41 03 lw s1, 52(sp) +80002c90: 03 24 81 03 lw s0, 56(sp) +80002c94: 83 20 c1 03 lw ra, 60(sp) +80002c98: 13 01 01 04 addi sp, sp, 64 +80002c9c: 67 80 00 00 ret + +80002ca0 _exit: +80002ca0: 63 06 05 00 beqz a0, 12 +80002ca4: 93 01 05 00 mv gp, a0 +80002ca8: 73 00 00 00 ecall + +80002cac label_exit_next: +80002cac: ef 00 00 5a jal 1440 +80002cb0: 13 05 00 00 mv a0, zero +80002cb4: 6b 00 05 00 vx_tmc a0 + +80002cb8 vx_set_sp: +80002cb8: 13 05 f0 ff addi a0, zero, -1 +80002cbc: 6b 00 05 00 vx_tmc a0 +80002cc0: 97 51 01 00 auipc gp, 21 +80002cc4: 93 81 81 d1 addi gp, gp, -744 +80002cc8: 37 01 00 ff lui sp, 1044480 +80002ccc: 73 26 10 cc csrr a2, 3265 +80002cd0: 93 15 a6 00 slli a1, a2, 10 +80002cd4: 33 01 b1 40 sub sp, sp, a1 +80002cd8: f3 26 30 cc csrr a3, 3267 +80002cdc: 63 86 06 00 beqz a3, 12 +80002ce0: 13 05 00 00 mv a0, zero +80002ce4: 6b 00 05 00 vx_tmc a0 + +80002ce8 RETURN: +80002ce8: 67 80 00 00 ret + +80002cec _close: +80002cec: 13 05 f0 ff addi a0, zero, -1 +80002cf0: 67 80 00 00 ret + +80002cf4 _fstat: +80002cf4: 13 05 f0 ff addi a0, zero, -1 +80002cf8: 67 80 00 00 ret + +80002cfc _isatty: +80002cfc: 13 05 00 00 mv a0, zero +80002d00: 67 80 00 00 ret + +80002d04 _lseek: +80002d04: 13 05 00 00 mv a0, zero +80002d08: 67 80 00 00 ret + +80002d0c _read: +80002d0c: 13 05 f0 ff addi a0, zero, -1 +80002d10: 67 80 00 00 ret + +80002d14 _sbrk: +80002d14: 13 05 00 00 mv a0, zero +80002d18: 67 80 00 00 ret + +80002d1c _write: +80002d1c: 13 01 01 ff addi sp, sp, -16 +80002d20: 23 20 21 01 sw s2, 0(sp) +80002d24: 23 26 11 00 sw ra, 12(sp) +80002d28: 23 24 81 00 sw s0, 8(sp) +80002d2c: 23 22 91 00 sw s1, 4(sp) +80002d30: 13 09 06 00 mv s2, a2 +80002d34: 63 5e c0 00 blez a2, 28 +80002d38: 13 84 05 00 mv s0, a1 +80002d3c: b3 84 c5 00 add s1, a1, a2 +80002d40: 03 45 04 00 lbu a0, 0(s0) +80002d44: 13 04 14 00 addi s0, s0, 1 +80002d48: ef 00 c0 12 jal 300 +80002d4c: e3 1a 94 fe bne s0, s1, -12 +80002d50: 83 20 c1 00 lw ra, 12(sp) +80002d54: 03 24 81 00 lw s0, 8(sp) +80002d58: 83 24 41 00 lw s1, 4(sp) +80002d5c: 13 05 09 00 mv a0, s2 +80002d60: 03 29 01 00 lw s2, 0(sp) +80002d64: 13 01 01 01 addi sp, sp, 16 +80002d68: 67 80 00 00 ret + +80002d6c _kill: +80002d6c: 13 05 f0 ff addi a0, zero, -1 +80002d70: 67 80 00 00 ret + +80002d74 _getpid: +80002d74: 73 25 40 f1 csrr a0, mhartid +80002d78: 67 80 00 00 ret + +80002d7c __libc_init_array: +80002d7c: 13 01 01 ff addi sp, sp, -16 +80002d80: 23 24 81 00 sw s0, 8(sp) +80002d84: 23 20 21 01 sw s2, 0(sp) +80002d88: 37 74 01 80 lui s0, 524311 +80002d8c: 37 79 01 80 lui s2, 524311 +80002d90: 93 07 44 1d addi a5, s0, 468 +80002d94: 13 09 49 1d addi s2, s2, 468 +80002d98: 33 09 f9 40 sub s2, s2, a5 +80002d9c: 23 26 11 00 sw ra, 12(sp) +80002da0: 23 22 91 00 sw s1, 4(sp) +80002da4: 13 59 29 40 srai s2, s2, 2 +80002da8: 63 00 09 02 beqz s2, 32 +80002dac: 13 04 44 1d addi s0, s0, 468 +80002db0: 93 04 00 00 mv s1, zero +80002db4: 83 27 04 00 lw a5, 0(s0) +80002db8: 93 84 14 00 addi s1, s1, 1 +80002dbc: 13 04 44 00 addi s0, s0, 4 +80002dc0: e7 80 07 00 jalr a5 +80002dc4: e3 18 99 fe bne s2, s1, -16 +80002dc8: 37 74 01 80 lui s0, 524311 +80002dcc: 37 79 01 80 lui s2, 524311 +80002dd0: 93 07 44 1d addi a5, s0, 468 +80002dd4: 13 09 89 1d addi s2, s2, 472 +80002dd8: 33 09 f9 40 sub s2, s2, a5 +80002ddc: 13 59 29 40 srai s2, s2, 2 +80002de0: 63 00 09 02 beqz s2, 32 +80002de4: 13 04 44 1d addi s0, s0, 468 +80002de8: 93 04 00 00 mv s1, zero +80002dec: 83 27 04 00 lw a5, 0(s0) +80002df0: 93 84 14 00 addi s1, s1, 1 +80002df4: 13 04 44 00 addi s0, s0, 4 +80002df8: e7 80 07 00 jalr a5 +80002dfc: e3 18 99 fe bne s2, s1, -16 +80002e00: 83 20 c1 00 lw ra, 12(sp) +80002e04: 03 24 81 00 lw s0, 8(sp) +80002e08: 83 24 41 00 lw s1, 4(sp) +80002e0c: 03 29 01 00 lw s2, 0(sp) +80002e10: 13 01 01 01 addi sp, sp, 16 +80002e14: 67 80 00 00 ret + +80002e18 __libc_fini_array: +80002e18: 13 01 01 ff addi sp, sp, -16 +80002e1c: 23 24 81 00 sw s0, 8(sp) +80002e20: b7 77 01 80 lui a5, 524311 +80002e24: 37 74 01 80 lui s0, 524311 +80002e28: 13 04 84 1d addi s0, s0, 472 +80002e2c: 93 87 87 1d addi a5, a5, 472 +80002e30: b3 87 87 40 sub a5, a5, s0 +80002e34: 23 22 91 00 sw s1, 4(sp) +80002e38: 23 26 11 00 sw ra, 12(sp) +80002e3c: 93 d4 27 40 srai s1, a5, 2 +80002e40: 63 80 04 02 beqz s1, 32 +80002e44: 93 87 c7 ff addi a5, a5, -4 +80002e48: 33 84 87 00 add s0, a5, s0 +80002e4c: 83 27 04 00 lw a5, 0(s0) +80002e50: 93 84 f4 ff addi s1, s1, -1 +80002e54: 13 04 c4 ff addi s0, s0, -4 +80002e58: e7 80 07 00 jalr a5 +80002e5c: e3 98 04 fe bnez s1, -16 +80002e60: 83 20 c1 00 lw ra, 12(sp) +80002e64: 03 24 81 00 lw s0, 8(sp) +80002e68: 83 24 41 00 lw s1, 4(sp) +80002e6c: 13 01 01 01 addi sp, sp, 16 +80002e70: 67 80 00 00 ret + +80002e74 vx_putchar: +80002e74: f3 22 20 cc csrr t0, 3266 +80002e78: 93 f2 f2 03 andi t0, t0, 63 +80002e7c: 13 03 00 fc addi t1, zero, -64 +80002e80: b3 82 62 00 add t0, t0, t1 +80002e84: 23 80 a2 00 sb a0, 0(t0) +80002e88: 67 80 00 00 ret + +80002e8c spawn_kernel_all_stub: +80002e8c: 13 01 01 fe addi sp, sp, -32 +80002e90: 23 2e 11 00 sw ra, 28(sp) +80002e94: 23 2c 81 00 sw s0, 24(sp) +80002e98: 23 2a 91 00 sw s1, 20(sp) +80002e9c: 23 28 21 01 sw s2, 16(sp) +80002ea0: 23 26 31 01 sw s3, 12(sp) +80002ea4: 23 24 41 01 sw s4, 8(sp) +80002ea8: 73 26 50 cc csrr a2, 3269 +80002eac: 73 27 30 cc csrr a4, 3267 +80002eb0: f3 26 00 cc csrr a3, 3264 +80002eb4: 73 25 00 fc csrr a0, 4032 +80002eb8: b7 87 01 80 lui a5, 524312 +80002ebc: 13 16 26 00 slli a2, a2, 2 +80002ec0: 93 87 c7 bd addi a5, a5, -1060 +80002ec4: b3 87 c7 00 add a5, a5, a2 +80002ec8: 03 a4 07 00 lw s0, 0(a5) +80002ecc: 83 24 44 01 lw s1, 20(s0) +80002ed0: 03 26 04 01 lw a2, 16(s0) +80002ed4: 33 2a 97 00 slt s4, a4, s1 +80002ed8: 93 87 04 00 mv a5, s1 +80002edc: 33 0a ca 00 add s4, s4, a2 +80002ee0: b3 04 e6 02 mul s1, a2, a4 +80002ee4: 63 54 f7 00 bge a4, a5, 8 +80002ee8: 93 07 07 00 mv a5, a4 +80002eec: b3 84 f4 00 add s1, s1, a5 +80002ef0: 83 25 04 00 lw a1, 0(s0) +80002ef4: 03 27 c4 00 lw a4, 12(s0) +80002ef8: 03 a9 05 00 lw s2, 0(a1) +80002efc: 83 a9 45 00 lw s3, 4(a1) +80002f00: b3 84 a4 02 mul s1, s1, a0 +80002f04: b3 07 da 02 mul a5, s4, a3 +80002f08: b3 84 e4 00 add s1, s1, a4 +80002f0c: b3 84 f4 00 add s1, s1, a5 +80002f10: 33 0a 9a 00 add s4, s4, s1 +80002f14: b3 09 39 03 mul s3, s2, s3 +80002f18: 63 c0 44 07 blt s1, s4, 96 +80002f1c: 6f 00 00 08 j 128 +80002f20: 03 47 e4 01 lbu a4, 30(s0) +80002f24: 83 46 d4 01 lbu a3, 29(s0) +80002f28: 33 d7 e4 40 sra a4, s1, a4 +80002f2c: b3 07 37 03 mul a5, a4, s3 +80002f30: b3 87 f4 40 sub a5, s1, a5 +80002f34: 63 80 06 06 beqz a3, 96 +80002f38: 83 46 f4 01 lbu a3, 31(s0) +80002f3c: b3 d6 d7 40 sra a3, a5, a3 +80002f40: b3 88 26 03 mul a7, a3, s2 +80002f44: 03 ae 45 01 lw t3, 20(a1) +80002f48: 03 a3 05 01 lw t1, 16(a1) +80002f4c: 03 a6 c5 00 lw a2, 12(a1) +80002f50: 03 28 44 00 lw a6, 4(s0) +80002f54: 03 25 84 00 lw a0, 8(s0) +80002f58: 93 84 14 00 addi s1, s1, 1 +80002f5c: 33 07 c7 01 add a4, a4, t3 +80002f60: b3 86 66 00 add a3, a3, t1 +80002f64: b3 87 17 41 sub a5, a5, a7 +80002f68: 33 86 c7 00 add a2, a5, a2 +80002f6c: e7 00 08 00 jalr a6 +80002f70: 63 06 9a 02 beq s4, s1, 44 +80002f74: 83 25 04 00 lw a1, 0(s0) +80002f78: 83 47 c4 01 lbu a5, 28(s0) +80002f7c: e3 92 07 fa bnez a5, -92 +80002f80: 33 c7 34 03 div a4, s1, s3 +80002f84: 83 46 d4 01 lbu a3, 29(s0) +80002f88: b3 07 37 03 mul a5, a4, s3 +80002f8c: b3 87 f4 40 sub a5, s1, a5 +80002f90: e3 94 06 fa bnez a3, -88 +80002f94: b3 c6 27 03 div a3, a5, s2 +80002f98: 6f f0 9f fa j -88 +80002f9c: 03 27 84 01 lw a4, 24(s0) +80002fa0: 93 07 00 00 mv a5, zero +80002fa4: 6b c0 e7 00 vx_bar a5, a4 +80002fa8: 83 20 c1 01 lw ra, 28(sp) +80002fac: 03 24 81 01 lw s0, 24(sp) +80002fb0: 83 24 41 01 lw s1, 20(sp) +80002fb4: 03 29 01 01 lw s2, 16(sp) +80002fb8: 83 29 c1 00 lw s3, 12(sp) +80002fbc: 03 2a 81 00 lw s4, 8(sp) +80002fc0: 13 01 01 02 addi sp, sp, 32 +80002fc4: 67 80 00 00 ret + +80002fc8 spawn_kernel_rem_stub: +80002fc8: f3 26 50 cc csrr a3, 3269 +80002fcc: f3 27 20 cc csrr a5, 3266 +80002fd0: 37 87 01 80 lui a4, 524312 +80002fd4: 93 96 26 00 slli a3, a3, 2 +80002fd8: 13 07 c7 bd addi a4, a4, -1060 +80002fdc: 33 07 d7 00 add a4, a4, a3 +80002fe0: 03 25 07 00 lw a0, 0(a4) +80002fe4: 83 25 05 00 lw a1, 0(a0) +80002fe8: 83 26 c5 00 lw a3, 12(a0) +80002fec: 03 47 c5 01 lbu a4, 28(a0) +80002ff0: 83 a8 05 00 lw a7, 0(a1) +80002ff4: 03 a6 45 00 lw a2, 4(a1) +80002ff8: b3 87 d7 00 add a5, a5, a3 +80002ffc: 33 86 c8 02 mul a2, a7, a2 +80003000: 63 08 07 04 beqz a4, 80 +80003004: 03 47 e5 01 lbu a4, 30(a0) +80003008: 83 46 d5 01 lbu a3, 29(a0) +8000300c: 33 d7 e7 40 sra a4, a5, a4 +80003010: 33 06 c7 02 mul a2, a4, a2 +80003014: b3 87 c7 40 sub a5, a5, a2 +80003018: 63 86 06 04 beqz a3, 76 +8000301c: 83 46 f5 01 lbu a3, 31(a0) +80003020: 33 d8 d7 40 sra a6, a5, a3 +80003024: 83 a6 05 01 lw a3, 16(a1) +80003028: 03 ae 45 01 lw t3, 20(a1) +8000302c: 03 a6 c5 00 lw a2, 12(a1) +80003030: b3 06 d8 00 add a3, a6, a3 +80003034: 33 08 18 03 mul a6, a6, a7 +80003038: 03 23 45 00 lw t1, 4(a0) +8000303c: 03 25 85 00 lw a0, 8(a0) +80003040: 33 07 c7 01 add a4, a4, t3 +80003044: b3 87 07 41 sub a5, a5, a6 +80003048: 33 86 c7 00 add a2, a5, a2 +8000304c: 67 00 03 00 jr t1 +80003050: 33 c7 c7 02 div a4, a5, a2 +80003054: 83 46 d5 01 lbu a3, 29(a0) +80003058: 33 06 c7 02 mul a2, a4, a2 +8000305c: b3 87 c7 40 sub a5, a5, a2 +80003060: e3 9e 06 fa bnez a3, -68 +80003064: 33 c8 17 03 div a6, a5, a7 +80003068: 6f f0 df fb j -68 + +8000306c spawn_kernel_all_cb: +8000306c: 13 01 01 ff addi sp, sp, -16 +80003070: 23 26 11 00 sw ra, 12(sp) +80003074: 93 07 f0 ff addi a5, zero, -1 +80003078: 6b 80 07 00 vx_tmc a5 +8000307c: ef f0 1f e1 jal -496 +80003080: f3 27 30 cc csrr a5, 3267 +80003084: 93 b7 17 00 seqz a5, a5 +80003088: 6b 80 07 00 vx_tmc a5 +8000308c: 83 20 c1 00 lw ra, 12(sp) +80003090: 13 01 01 01 addi sp, sp, 16 +80003094: 67 80 00 00 ret + +80003098 vx_spawn_kernel: +80003098: 13 01 01 fd addi sp, sp, -48 +8000309c: 23 26 11 02 sw ra, 44(sp) +800030a0: 23 24 81 02 sw s0, 40(sp) +800030a4: 23 22 91 02 sw s1, 36(sp) +800030a8: 23 20 21 03 sw s2, 32(sp) +800030ac: f3 28 20 fc csrr a7, 4034 +800030b0: 73 23 10 fc csrr t1, 4033 +800030b4: f3 24 00 fc csrr s1, 4032 +800030b8: f3 27 50 cc csrr a5, 3269 +800030bc: 13 07 f0 01 addi a4, zero, 31 +800030c0: 63 46 f7 0e blt a4, a5, 236 +800030c4: 03 2e 05 00 lw t3, 0(a0) +800030c8: 83 26 45 00 lw a3, 4(a0) +800030cc: 03 28 85 00 lw a6, 8(a0) +800030d0: b3 0e 93 02 mul t4, t1, s1 +800030d4: 13 07 10 00 addi a4, zero, 1 +800030d8: b3 06 de 02 mul a3, t3, a3 +800030dc: 33 88 06 03 mul a6, a3, a6 +800030e0: 63 d4 0e 01 bge t4, a6, 8 +800030e4: 33 47 d8 03 div a4, a6, t4 +800030e8: 63 ce e8 0c blt a7, a4, 220 +800030ec: 63 d0 e7 0c bge a5, a4, 192 +800030f0: 93 88 f8 ff addi a7, a7, -1 +800030f4: b3 4e e8 02 div t4, a6, a4 +800030f8: 13 84 0e 00 mv s0, t4 +800030fc: 63 96 f8 00 bne a7, a5, 12 +80003100: 33 67 e8 02 rem a4, a6, a4 +80003104: 33 04 d7 01 add s0, a4, t4 +80003108: 33 49 94 02 div s2, s0, s1 +8000310c: 33 64 94 02 rem s0, s0, s1 +80003110: 63 40 69 0c blt s2, t1, 192 +80003114: 93 0f 10 00 addi t6, zero, 1 +80003118: 33 4f 69 02 div t5, s2, t1 +8000311c: 63 06 0f 00 beqz t5, 12 +80003120: 93 0f 0f 00 mv t6, t5 +80003124: 33 6f 69 02 rem t5, s2, t1 +80003128: d3 f7 06 d0 fcvt.s.w fa5, a3 +8000312c: 13 07 fe ff addi a4, t3, -1 +80003130: 93 82 f6 ff addi t0, a3, -1 +80003134: d3 88 07 e0 fmv.x.w a7, fa5 +80003138: d3 77 0e d0 fcvt.s.w fa5, t3 +8000313c: 33 7e c7 01 and t3, a4, t3 +80003140: 37 87 01 80 lui a4, 524312 +80003144: 53 88 07 e0 fmv.x.w a6, fa5 +80003148: b3 f6 d2 00 and a3, t0, a3 +8000314c: 93 d8 78 41 srai a7, a7, 23 +80003150: 13 58 78 41 srai a6, a6, 23 +80003154: 13 07 c7 bd addi a4, a4, -1060 +80003158: 93 b6 16 00 seqz a3, a3 +8000315c: 13 3e 1e 00 seqz t3, t3 +80003160: 93 88 18 f8 addi a7, a7, -127 +80003164: 13 08 18 f8 addi a6, a6, -127 +80003168: 23 20 a1 00 sw a0, 0(sp) +8000316c: 23 22 b1 00 sw a1, 4(sp) +80003170: 23 24 c1 00 sw a2, 8(sp) +80003174: 23 28 f1 01 sw t6, 16(sp) +80003178: 23 2a e1 01 sw t5, 20(sp) +8000317c: 23 2c 01 00 sw zero, 24(sp) +80003180: 23 0e d1 00 sb a3, 28(sp) +80003184: a3 0e c1 01 sb t3, 29(sp) +80003188: 23 0f 11 01 sb a7, 30(sp) +8000318c: a3 0f 01 01 sb a6, 31(sp) +80003190: b3 8e fe 02 mul t4, t4, a5 +80003194: 93 97 27 00 slli a5, a5, 2 +80003198: b3 07 f7 00 add a5, a4, a5 +8000319c: 23 a0 27 00 sw sp, 0(a5) +800031a0: 23 26 d1 01 sw t4, 12(sp) +800031a4: 63 4c 20 03 bgtz s2, 56 +800031a8: 63 16 04 06 bnez s0, 108 +800031ac: 83 20 c1 02 lw ra, 44(sp) +800031b0: 03 24 81 02 lw s0, 40(sp) +800031b4: 83 24 41 02 lw s1, 36(sp) +800031b8: 03 29 01 02 lw s2, 32(sp) +800031bc: 13 01 01 03 addi sp, sp, 48 +800031c0: 67 80 00 00 ret +800031c4: 13 87 08 00 mv a4, a7 +800031c8: e3 c4 e7 f2 blt a5, a4, -216 +800031cc: 6f f0 1f fe j -32 +800031d0: 13 0f 00 00 mv t5, zero +800031d4: 93 0f 10 00 addi t6, zero, 1 +800031d8: 6f f0 1f f5 j -176 +800031dc: 13 07 09 00 mv a4, s2 +800031e0: 63 54 23 01 bge t1, s2, 8 +800031e4: 13 07 03 00 mv a4, t1 +800031e8: b7 37 00 80 lui a5, 524291 +800031ec: 23 2c e1 00 sw a4, 24(sp) +800031f0: 93 87 c7 06 addi a5, a5, 108 +800031f4: 6b 10 f7 00 vx_wspawn a4, a5 +800031f8: 93 07 f0 ff addi a5, zero, -1 +800031fc: 6b 80 07 00 vx_tmc a5 +80003200: ef f0 df c8 jal -884 +80003204: f3 27 30 cc csrr a5, 3267 +80003208: 93 b7 17 00 seqz a5, a5 +8000320c: 6b 80 07 00 vx_tmc a5 +80003210: e3 0e 04 f8 beqz s0, -100 +80003214: b3 04 99 02 mul s1, s2, s1 +80003218: 13 09 10 00 addi s2, zero, 1 +8000321c: 33 14 89 00 sll s0, s2, s0 +80003220: 13 04 f4 ff addi s0, s0, -1 +80003224: 23 26 91 00 sw s1, 12(sp) +80003228: 6b 00 04 00 vx_tmc s0 +8000322c: ef f0 df d9 jal -612 +80003230: 6b 00 09 00 vx_tmc s2 +80003234: 83 20 c1 02 lw ra, 44(sp) +80003238: 03 24 81 02 lw s0, 40(sp) +8000323c: 83 24 41 02 lw s1, 36(sp) +80003240: 03 29 01 02 lw s2, 32(sp) +80003244: 13 01 01 03 addi sp, sp, 48 +80003248: 67 80 00 00 ret + +8000324c vx_perf_dump: +8000324c: f3 27 50 cc csrr a5, 3269 +80003250: 37 07 ff 00 lui a4, 4080 +80003254: b3 87 e7 00 add a5, a5, a4 +80003258: 93 97 87 00 slli a5, a5, 8 +8000325c: 73 27 00 b0 csrr a4, mcycle +80003260: 23 a0 e7 00 sw a4, 0(a5) +80003264: 73 27 10 b0 csrr a4, 2817 +80003268: 23 a2 e7 00 sw a4, 4(a5) +8000326c: 73 27 20 b0 csrr a4, minstret +80003270: 23 a4 e7 00 sw a4, 8(a5) +80003274: 73 27 30 b0 csrr a4, mhpmcounter3 +80003278: 23 a6 e7 00 sw a4, 12(a5) +8000327c: 73 27 40 b0 csrr a4, mhpmcounter4 +80003280: 23 a8 e7 00 sw a4, 16(a5) +80003284: 73 27 50 b0 csrr a4, mhpmcounter5 +80003288: 23 aa e7 00 sw a4, 20(a5) +8000328c: 73 27 60 b0 csrr a4, mhpmcounter6 +80003290: 23 ac e7 00 sw a4, 24(a5) +80003294: 73 27 70 b0 csrr a4, mhpmcounter7 +80003298: 23 ae e7 00 sw a4, 28(a5) +8000329c: 73 27 80 b0 csrr a4, mhpmcounter8 +800032a0: 23 a0 e7 02 sw a4, 32(a5) +800032a4: 73 27 90 b0 csrr a4, mhpmcounter9 +800032a8: 23 a2 e7 02 sw a4, 36(a5) +800032ac: 73 27 a0 b0 csrr a4, mhpmcounter10 +800032b0: 23 a4 e7 02 sw a4, 40(a5) +800032b4: 73 27 b0 b0 csrr a4, mhpmcounter11 +800032b8: 23 a6 e7 02 sw a4, 44(a5) +800032bc: 73 27 c0 b0 csrr a4, mhpmcounter12 +800032c0: 23 a8 e7 02 sw a4, 48(a5) +800032c4: 73 27 d0 b0 csrr a4, mhpmcounter13 +800032c8: 23 aa e7 02 sw a4, 52(a5) +800032cc: 73 27 e0 b0 csrr a4, mhpmcounter14 +800032d0: 23 ac e7 02 sw a4, 56(a5) +800032d4: 73 27 f0 b0 csrr a4, mhpmcounter15 +800032d8: 23 ae e7 02 sw a4, 60(a5) +800032dc: 73 27 00 b1 csrr a4, mhpmcounter16 +800032e0: 23 a0 e7 04 sw a4, 64(a5) +800032e4: 73 27 10 b1 csrr a4, mhpmcounter17 +800032e8: 23 a2 e7 04 sw a4, 68(a5) +800032ec: 73 27 20 b1 csrr a4, mhpmcounter18 +800032f0: 23 a4 e7 04 sw a4, 72(a5) +800032f4: 73 27 30 b1 csrr a4, mhpmcounter19 +800032f8: 23 a6 e7 04 sw a4, 76(a5) +800032fc: 73 27 40 b1 csrr a4, mhpmcounter20 +80003300: 23 a8 e7 04 sw a4, 80(a5) +80003304: 73 27 50 b1 csrr a4, mhpmcounter21 +80003308: 23 aa e7 04 sw a4, 84(a5) +8000330c: 73 27 60 b1 csrr a4, mhpmcounter22 +80003310: 23 ac e7 04 sw a4, 88(a5) +80003314: 73 27 70 b1 csrr a4, mhpmcounter23 +80003318: 23 ae e7 04 sw a4, 92(a5) +8000331c: 73 27 80 b1 csrr a4, mhpmcounter24 +80003320: 23 a0 e7 06 sw a4, 96(a5) +80003324: 73 27 90 b1 csrr a4, mhpmcounter25 +80003328: 23 a2 e7 06 sw a4, 100(a5) +8000332c: 73 27 a0 b1 csrr a4, mhpmcounter26 +80003330: 23 a4 e7 06 sw a4, 104(a5) +80003334: 73 27 b0 b1 csrr a4, mhpmcounter27 +80003338: 23 a6 e7 06 sw a4, 108(a5) +8000333c: 73 27 c0 b1 csrr a4, mhpmcounter28 +80003340: 23 a8 e7 06 sw a4, 112(a5) +80003344: 73 27 d0 b1 csrr a4, mhpmcounter29 +80003348: 23 aa e7 06 sw a4, 116(a5) +8000334c: 73 27 e0 b1 csrr a4, mhpmcounter30 +80003350: 23 ac e7 06 sw a4, 120(a5) +80003354: 73 27 f0 b1 csrr a4, mhpmcounter31 +80003358: 23 ae e7 06 sw a4, 124(a5) +8000335c: 73 27 00 b8 csrr a4, mcycleh +80003360: 23 a0 e7 08 sw a4, 128(a5) +80003364: 73 27 10 b8 csrr a4, 2945 +80003368: 23 a2 e7 08 sw a4, 132(a5) +8000336c: 73 27 20 b8 csrr a4, minstreth +80003370: 23 a4 e7 08 sw a4, 136(a5) +80003374: 73 27 30 b8 csrr a4, mhpmcounter3h +80003378: 23 a6 e7 08 sw a4, 140(a5) +8000337c: 73 27 40 b8 csrr a4, mhpmcounter4h +80003380: 23 a8 e7 08 sw a4, 144(a5) +80003384: 73 27 50 b8 csrr a4, mhpmcounter5h +80003388: 23 aa e7 08 sw a4, 148(a5) +8000338c: 73 27 60 b8 csrr a4, mhpmcounter6h +80003390: 23 ac e7 08 sw a4, 152(a5) +80003394: 73 27 70 b8 csrr a4, mhpmcounter7h +80003398: 23 ae e7 08 sw a4, 156(a5) +8000339c: 73 27 80 b8 csrr a4, mhpmcounter8h +800033a0: 23 a0 e7 0a sw a4, 160(a5) +800033a4: 73 27 90 b8 csrr a4, mhpmcounter9h +800033a8: 23 a2 e7 0a sw a4, 164(a5) +800033ac: 73 27 a0 b8 csrr a4, mhpmcounter10h +800033b0: 23 a4 e7 0a sw a4, 168(a5) +800033b4: 73 27 b0 b8 csrr a4, mhpmcounter11h +800033b8: 23 a6 e7 0a sw a4, 172(a5) +800033bc: 73 27 c0 b8 csrr a4, mhpmcounter12h +800033c0: 23 a8 e7 0a sw a4, 176(a5) +800033c4: 73 27 d0 b8 csrr a4, mhpmcounter13h +800033c8: 23 aa e7 0a sw a4, 180(a5) +800033cc: 73 27 e0 b8 csrr a4, mhpmcounter14h +800033d0: 23 ac e7 0a sw a4, 184(a5) +800033d4: 73 27 f0 b8 csrr a4, mhpmcounter15h +800033d8: 23 ae e7 0a sw a4, 188(a5) +800033dc: 73 27 00 b9 csrr a4, mhpmcounter16h +800033e0: 23 a0 e7 0c sw a4, 192(a5) +800033e4: 73 27 10 b9 csrr a4, mhpmcounter17h +800033e8: 23 a2 e7 0c sw a4, 196(a5) +800033ec: 73 27 20 b9 csrr a4, mhpmcounter18h +800033f0: 23 a4 e7 0c sw a4, 200(a5) +800033f4: 73 27 30 b9 csrr a4, mhpmcounter19h +800033f8: 23 a6 e7 0c sw a4, 204(a5) +800033fc: 73 27 40 b9 csrr a4, mhpmcounter20h +80003400: 23 a8 e7 0c sw a4, 208(a5) +80003404: 73 27 50 b9 csrr a4, mhpmcounter21h +80003408: 23 aa e7 0c sw a4, 212(a5) +8000340c: 73 27 60 b9 csrr a4, mhpmcounter22h +80003410: 23 ac e7 0c sw a4, 216(a5) +80003414: 73 27 70 b9 csrr a4, mhpmcounter23h +80003418: 23 ae e7 0c sw a4, 220(a5) +8000341c: 73 27 80 b9 csrr a4, mhpmcounter24h +80003420: 23 a0 e7 0e sw a4, 224(a5) +80003424: 73 27 90 b9 csrr a4, mhpmcounter25h +80003428: 23 a2 e7 0e sw a4, 228(a5) +8000342c: 73 27 a0 b9 csrr a4, mhpmcounter26h +80003430: 23 a4 e7 0e sw a4, 232(a5) +80003434: 73 27 b0 b9 csrr a4, mhpmcounter27h +80003438: 23 a6 e7 0e sw a4, 236(a5) +8000343c: 73 27 c0 b9 csrr a4, mhpmcounter28h +80003440: 23 a8 e7 0e sw a4, 240(a5) +80003444: 73 27 d0 b9 csrr a4, mhpmcounter29h +80003448: 23 aa e7 0e sw a4, 244(a5) +8000344c: 73 27 e0 b9 csrr a4, mhpmcounter30h +80003450: 23 ac e7 0e sw a4, 248(a5) +80003454: 73 27 f0 b9 csrr a4, mhpmcounter31h +80003458: 23 ae e7 0e sw a4, 252(a5) +8000345c: 67 80 00 00 ret + +80003460 atexit: +80003460: 93 05 05 00 mv a1, a0 +80003464: 93 06 00 00 mv a3, zero +80003468: 13 06 00 00 mv a2, zero +8000346c: 13 05 00 00 mv a0, zero +80003470: 6f 20 d0 59 j 11676 + +80003474 exit: +80003474: 13 01 01 ff addi sp, sp, -16 +80003478: 93 05 00 00 mv a1, zero +8000347c: 23 24 81 00 sw s0, 8(sp) +80003480: 23 26 11 00 sw ra, 12(sp) +80003484: 13 04 05 00 mv s0, a0 +80003488: ef 20 10 62 jal 11808 +8000348c: b7 87 01 80 lui a5, 524312 +80003490: 03 a5 07 b9 lw a0, -1136(a5) +80003494: 83 27 c5 03 lw a5, 60(a0) +80003498: 63 84 07 00 beqz a5, 8 +8000349c: e7 80 07 00 jalr a5 +800034a0: 13 05 04 00 mv a0, s0 +800034a4: ef f0 cf ff jal -2052 + +800034a8 memset: +800034a8: 13 03 f0 00 addi t1, zero, 15 +800034ac: 13 07 05 00 mv a4, a0 +800034b0: 63 7e c3 02 bgeu t1, a2, 60 +800034b4: 93 77 f7 00 andi a5, a4, 15 +800034b8: 63 90 07 0a bnez a5, 160 +800034bc: 63 92 05 08 bnez a1, 132 +800034c0: 93 76 06 ff andi a3, a2, -16 +800034c4: 13 76 f6 00 andi a2, a2, 15 +800034c8: b3 86 e6 00 add a3, a3, a4 +800034cc: 23 20 b7 00 sw a1, 0(a4) +800034d0: 23 22 b7 00 sw a1, 4(a4) +800034d4: 23 24 b7 00 sw a1, 8(a4) +800034d8: 23 26 b7 00 sw a1, 12(a4) +800034dc: 13 07 07 01 addi a4, a4, 16 +800034e0: e3 66 d7 fe bltu a4, a3, -20 +800034e4: 63 14 06 00 bnez a2, 8 +800034e8: 67 80 00 00 ret +800034ec: b3 06 c3 40 sub a3, t1, a2 +800034f0: 93 96 26 00 slli a3, a3, 2 +800034f4: 97 02 00 00 auipc t0, 0 +800034f8: b3 86 56 00 add a3, a3, t0 +800034fc: 67 80 c6 00 jr 12(a3) +80003500: 23 07 b7 00 sb a1, 14(a4) +80003504: a3 06 b7 00 sb a1, 13(a4) +80003508: 23 06 b7 00 sb a1, 12(a4) +8000350c: a3 05 b7 00 sb a1, 11(a4) +80003510: 23 05 b7 00 sb a1, 10(a4) +80003514: a3 04 b7 00 sb a1, 9(a4) +80003518: 23 04 b7 00 sb a1, 8(a4) +8000351c: a3 03 b7 00 sb a1, 7(a4) +80003520: 23 03 b7 00 sb a1, 6(a4) +80003524: a3 02 b7 00 sb a1, 5(a4) +80003528: 23 02 b7 00 sb a1, 4(a4) +8000352c: a3 01 b7 00 sb a1, 3(a4) +80003530: 23 01 b7 00 sb a1, 2(a4) +80003534: a3 00 b7 00 sb a1, 1(a4) +80003538: 23 00 b7 00 sb a1, 0(a4) +8000353c: 67 80 00 00 ret +80003540: 93 f5 f5 0f andi a1, a1, 255 +80003544: 93 96 85 00 slli a3, a1, 8 +80003548: b3 e5 d5 00 or a1, a1, a3 +8000354c: 93 96 05 01 slli a3, a1, 16 +80003550: b3 e5 d5 00 or a1, a1, a3 +80003554: 6f f0 df f6 j -148 +80003558: 93 96 27 00 slli a3, a5, 2 +8000355c: 97 02 00 00 auipc t0, 0 +80003560: b3 86 56 00 add a3, a3, t0 +80003564: 93 82 00 00 mv t0, ra +80003568: e7 80 06 fa jalr -96(a3) +8000356c: 93 80 02 00 mv ra, t0 +80003570: 93 87 07 ff addi a5, a5, -16 +80003574: 33 07 f7 40 sub a4, a4, a5 +80003578: 33 06 f6 00 add a2, a2, a5 +8000357c: e3 78 c3 f6 bgeu t1, a2, -144 +80003580: 6f f0 df f3 j -196 + +80003584 _snprintf_r: +80003584: 13 01 01 f7 addi sp, sp, -144 +80003588: 23 2c 81 06 sw s0, 120(sp) +8000358c: 23 2e 11 06 sw ra, 124(sp) +80003590: 23 2a 91 06 sw s1, 116(sp) +80003594: 23 20 e1 08 sw a4, 128(sp) +80003598: 23 22 f1 08 sw a5, 132(sp) +8000359c: 23 24 01 09 sw a6, 136(sp) +800035a0: 23 26 11 09 sw a7, 140(sp) +800035a4: 13 03 06 00 mv t1, a2 +800035a8: 13 04 05 00 mv s0, a0 +800035ac: 63 42 06 0a bltz a2, 164 +800035b0: 93 07 80 20 addi a5, zero, 520 +800035b4: 23 1a f1 00 sh a5, 20(sp) +800035b8: 23 24 b1 00 sw a1, 8(sp) +800035bc: 23 2c b1 00 sw a1, 24(sp) +800035c0: 13 86 06 00 mv a2, a3 +800035c4: 93 06 01 08 addi a3, sp, 128 +800035c8: 63 06 03 04 beqz t1, 76 +800035cc: 13 03 f3 ff addi t1, t1, -1 +800035d0: 93 04 f0 ff addi s1, zero, -1 +800035d4: 93 05 81 00 addi a1, sp, 8 +800035d8: 23 28 61 00 sw t1, 16(sp) +800035dc: 23 2e 61 00 sw t1, 28(sp) +800035e0: 23 1b 91 00 sh s1, 22(sp) +800035e4: 23 22 d1 00 sw a3, 4(sp) +800035e8: ef 00 c0 15 jal 348 +800035ec: 63 56 95 00 bge a0, s1, 12 +800035f0: 93 07 b0 08 addi a5, zero, 139 +800035f4: 23 20 f4 00 sw a5, 0(s0) +800035f8: 83 27 81 00 lw a5, 8(sp) +800035fc: 23 80 07 00 sb zero, 0(a5) +80003600: 83 20 c1 07 lw ra, 124(sp) +80003604: 03 24 81 07 lw s0, 120(sp) +80003608: 83 24 41 07 lw s1, 116(sp) +8000360c: 13 01 01 09 addi sp, sp, 144 +80003610: 67 80 00 00 ret +80003614: 93 04 f0 ff addi s1, zero, -1 +80003618: 93 05 81 00 addi a1, sp, 8 +8000361c: 23 28 01 00 sw zero, 16(sp) +80003620: 23 2e 01 00 sw zero, 28(sp) +80003624: 23 1b 91 00 sh s1, 22(sp) +80003628: 23 22 d1 00 sw a3, 4(sp) +8000362c: ef 00 80 11 jal 280 +80003630: 63 56 95 00 bge a0, s1, 12 +80003634: 93 07 b0 08 addi a5, zero, 139 +80003638: 23 20 f4 00 sw a5, 0(s0) +8000363c: 83 20 c1 07 lw ra, 124(sp) +80003640: 03 24 81 07 lw s0, 120(sp) +80003644: 83 24 41 07 lw s1, 116(sp) +80003648: 13 01 01 09 addi sp, sp, 144 +8000364c: 67 80 00 00 ret +80003650: 93 07 b0 08 addi a5, zero, 139 +80003654: 23 20 f5 00 sw a5, 0(a0) +80003658: 13 05 f0 ff addi a0, zero, -1 +8000365c: 6f f0 1f fe j -32 + +80003660 snprintf: +80003660: 13 01 01 f6 addi sp, sp, -160 +80003664: 23 2c 81 06 sw s0, 120(sp) +80003668: 23 2a f1 08 sw a5, 148(sp) +8000366c: 23 2e 11 06 sw ra, 124(sp) +80003670: b7 87 01 80 lui a5, 524312 +80003674: 23 2a 91 06 sw s1, 116(sp) +80003678: 23 26 d1 08 sw a3, 140(sp) +8000367c: 23 28 e1 08 sw a4, 144(sp) +80003680: 23 2c 01 09 sw a6, 152(sp) +80003684: 23 2e 11 09 sw a7, 156(sp) +80003688: 03 a4 c7 b9 lw s0, -1124(a5) +8000368c: 63 c4 05 0a bltz a1, 168 +80003690: 93 07 80 20 addi a5, zero, 520 +80003694: 23 1a f1 00 sh a5, 20(sp) +80003698: 23 24 a1 00 sw a0, 8(sp) +8000369c: 23 2c a1 00 sw a0, 24(sp) +800036a0: 93 06 c1 08 addi a3, sp, 140 +800036a4: 63 88 05 04 beqz a1, 80 +800036a8: 93 87 f5 ff addi a5, a1, -1 +800036ac: 93 04 f0 ff addi s1, zero, -1 +800036b0: 93 05 81 00 addi a1, sp, 8 +800036b4: 13 05 04 00 mv a0, s0 +800036b8: 23 28 f1 00 sw a5, 16(sp) +800036bc: 23 2e f1 00 sw a5, 28(sp) +800036c0: 23 1b 91 00 sh s1, 22(sp) +800036c4: 23 22 d1 00 sw a3, 4(sp) +800036c8: ef 00 c0 07 jal 124 +800036cc: 63 56 95 00 bge a0, s1, 12 +800036d0: 93 07 b0 08 addi a5, zero, 139 +800036d4: 23 20 f4 00 sw a5, 0(s0) +800036d8: 83 27 81 00 lw a5, 8(sp) +800036dc: 23 80 07 00 sb zero, 0(a5) +800036e0: 83 20 c1 07 lw ra, 124(sp) +800036e4: 03 24 81 07 lw s0, 120(sp) +800036e8: 83 24 41 07 lw s1, 116(sp) +800036ec: 13 01 01 0a addi sp, sp, 160 +800036f0: 67 80 00 00 ret +800036f4: 93 04 f0 ff addi s1, zero, -1 +800036f8: 93 05 81 00 addi a1, sp, 8 +800036fc: 13 05 04 00 mv a0, s0 +80003700: 23 28 01 00 sw zero, 16(sp) +80003704: 23 2e 01 00 sw zero, 28(sp) +80003708: 23 1b 91 00 sh s1, 22(sp) +8000370c: 23 22 d1 00 sw a3, 4(sp) +80003710: ef 00 40 03 jal 52 +80003714: 63 56 95 00 bge a0, s1, 12 +80003718: 93 07 b0 08 addi a5, zero, 139 +8000371c: 23 20 f4 00 sw a5, 0(s0) +80003720: 83 20 c1 07 lw ra, 124(sp) +80003724: 03 24 81 07 lw s0, 120(sp) +80003728: 83 24 41 07 lw s1, 116(sp) +8000372c: 13 01 01 0a addi sp, sp, 160 +80003730: 67 80 00 00 ret +80003734: 93 07 b0 08 addi a5, zero, 139 +80003738: 23 20 f4 00 sw a5, 0(s0) +8000373c: 13 05 f0 ff addi a0, zero, -1 +80003740: 6f f0 1f fe j -32 + +80003744 _svfprintf_r: +80003744: 13 01 01 e1 addi sp, sp, -496 +80003748: 23 26 11 1e sw ra, 492(sp) +8000374c: 23 2a 51 1d sw s5, 468(sp) +80003750: 23 28 61 1d sw s6, 464(sp) +80003754: 23 20 a1 1d sw s10, 448(sp) +80003758: 13 8b 05 00 mv s6, a1 +8000375c: 13 0d 06 00 mv s10, a2 +80003760: 23 26 d1 00 sw a3, 12(sp) +80003764: 23 24 81 1e sw s0, 488(sp) +80003768: 23 22 91 1e sw s1, 484(sp) +8000376c: 23 20 21 1f sw s2, 480(sp) +80003770: 23 2e 31 1d sw s3, 476(sp) +80003774: 23 2c 41 1d sw s4, 472(sp) +80003778: 23 26 71 1d sw s7, 460(sp) +8000377c: 23 24 81 1d sw s8, 456(sp) +80003780: 23 22 91 1d sw s9, 452(sp) +80003784: 23 2e b1 1b sw s11, 444(sp) +80003788: 93 0a 05 00 mv s5, a0 +8000378c: ef 50 d0 43 jal 23612 +80003790: 83 27 05 00 lw a5, 0(a0) +80003794: 13 85 07 00 mv a0, a5 +80003798: 23 20 f1 04 sw a5, 64(sp) +8000379c: ef 70 10 0d jal 30928 +800037a0: 83 57 cb 00 lhu a5, 12(s6) +800037a4: 23 28 01 0e sw zero, 240(sp) +800037a8: 23 2a 01 0e sw zero, 244(sp) +800037ac: 23 2c 01 0e sw zero, 248(sp) +800037b0: 23 2e 01 0e sw zero, 252(sp) +800037b4: 93 f7 07 08 andi a5, a5, 128 +800037b8: 23 2e a1 02 sw a0, 60(sp) +800037bc: 63 88 07 00 beqz a5, 16 +800037c0: 83 27 0b 01 lw a5, 16(s6) +800037c4: 63 94 07 00 bnez a5, 8 +800037c8: 6f 10 c0 5b j 5564 +800037cc: b7 57 01 80 lui a5, 524309 +800037d0: 93 87 c7 5d addi a5, a5, 1500 +800037d4: 23 2a f1 00 sw a5, 20(sp) +800037d8: 83 47 0d 00 lbu a5, 0(s10) +800037dc: 93 0b c1 10 addi s7, sp, 268 +800037e0: b7 59 01 80 lui s3, 524309 +800037e4: 23 22 71 0f sw s7, 228(sp) +800037e8: 23 26 01 0e sw zero, 236(sp) +800037ec: 23 24 01 0e sw zero, 232(sp) +800037f0: 23 28 01 00 sw zero, 16(sp) +800037f4: 23 2c 01 00 sw zero, 24(sp) +800037f8: 23 22 01 04 sw zero, 68(sp) +800037fc: 23 2c 01 02 sw zero, 56(sp) +80003800: 23 24 01 04 sw zero, 72(sp) +80003804: 23 26 01 04 sw zero, 76(sp) +80003808: 23 22 01 00 sw zero, 4(sp) +8000380c: 93 88 0b 00 mv a7, s7 +80003810: 93 89 89 75 addi s3, s3, 1880 +80003814: 63 80 07 22 beqz a5, 544 +80003818: 13 04 0d 00 mv s0, s10 +8000381c: 93 06 50 02 addi a3, zero, 37 +80003820: 63 82 d7 3c beq a5, a3, 964 +80003824: 83 47 14 00 lbu a5, 1(s0) +80003828: 13 04 14 00 addi s0, s0, 1 +8000382c: e3 9a 07 fe bnez a5, -12 +80003830: b3 04 a4 41 sub s1, s0, s10 +80003834: 63 00 a4 21 beq s0, s10, 512 +80003838: 83 26 c1 0e lw a3, 236(sp) +8000383c: 83 27 81 0e lw a5, 232(sp) +80003840: 23 a0 a8 01 sw s10, 0(a7) +80003844: b3 86 96 00 add a3, a3, s1 +80003848: 93 87 17 00 addi a5, a5, 1 +8000384c: 23 a2 98 00 sw s1, 4(a7) +80003850: 23 26 d1 0e sw a3, 236(sp) +80003854: 23 24 f1 0e sw a5, 232(sp) +80003858: 93 06 70 00 addi a3, zero, 7 +8000385c: 93 88 88 00 addi a7, a7, 8 +80003860: 63 ca f6 38 blt a3, a5, 916 +80003864: 03 27 41 00 lw a4, 4(sp) +80003868: 83 47 04 00 lbu a5, 0(s0) +8000386c: 33 07 97 00 add a4, a4, s1 +80003870: 23 22 e1 00 sw a4, 4(sp) +80003874: 63 80 07 1c beqz a5, 448 +80003878: 83 44 14 00 lbu s1, 1(s0) +8000387c: a3 03 01 0c sb zero, 199(sp) +80003880: 13 04 14 00 addi s0, s0, 1 +80003884: 13 03 f0 ff addi t1, zero, -1 +80003888: 13 0a 00 00 mv s4, zero +8000388c: 13 09 00 00 mv s2, zero +80003890: 13 0c a0 05 addi s8, zero, 90 +80003894: 93 0c 90 00 addi s9, zero, 9 +80003898: 93 0d a0 02 addi s11, zero, 42 +8000389c: 13 04 14 00 addi s0, s0, 1 +800038a0: 93 87 04 fe addi a5, s1, -32 +800038a4: 63 64 fc 04 bltu s8, a5, 72 +800038a8: 03 27 41 01 lw a4, 20(sp) +800038ac: 93 97 27 00 slli a5, a5, 2 +800038b0: b3 87 e7 00 add a5, a5, a4 +800038b4: 83 a7 07 00 lw a5, 0(a5) +800038b8: 67 80 07 00 jr a5 +800038bc: 13 0a 00 00 mv s4, zero +800038c0: 93 87 04 fd addi a5, s1, -48 +800038c4: 83 44 04 00 lbu s1, 0(s0) +800038c8: 93 16 2a 00 slli a3, s4, 2 +800038cc: 33 8a 46 01 add s4, a3, s4 +800038d0: 13 1a 1a 00 slli s4, s4, 1 +800038d4: 33 8a 47 01 add s4, a5, s4 +800038d8: 93 87 04 fd addi a5, s1, -48 +800038dc: 13 04 14 00 addi s0, s0, 1 +800038e0: e3 f2 fc fe bgeu s9, a5, -28 +800038e4: 93 87 04 fe addi a5, s1, -32 +800038e8: e3 70 fc fc bgeu s8, a5, -64 +800038ec: 63 84 04 14 beqz s1, 328 +800038f0: 23 06 91 14 sb s1, 332(sp) +800038f4: a3 03 01 0c sb zero, 199(sp) +800038f8: 13 0c 10 00 addi s8, zero, 1 +800038fc: 93 0c 10 00 addi s9, zero, 1 +80003900: 13 0d c1 14 addi s10, sp, 332 +80003904: 93 0d 00 00 mv s11, zero +80003908: 13 03 00 00 mv t1, zero +8000390c: 23 26 01 02 sw zero, 44(sp) +80003910: 23 2a 01 02 sw zero, 52(sp) +80003914: 23 28 01 02 sw zero, 48(sp) +80003918: 93 7f 29 00 andi t6, s2, 2 +8000391c: 63 84 0f 00 beqz t6, 8 +80003920: 13 0c 2c 00 addi s8, s8, 2 +80003924: 13 7f 49 08 andi t5, s2, 132 +80003928: 83 27 c1 0e lw a5, 236(sp) +8000392c: 63 16 0f 00 bnez t5, 12 +80003930: 33 08 8a 41 sub a6, s4, s8 +80003934: e3 40 00 73 bgtz a6, 3872 +80003938: 83 46 71 0c lbu a3, 199(sp) +8000393c: 63 8a 06 02 beqz a3, 52 +80003940: 83 26 81 0e lw a3, 232(sp) +80003944: 13 06 71 0c addi a2, sp, 199 +80003948: 23 a0 c8 00 sw a2, 0(a7) +8000394c: 93 87 17 00 addi a5, a5, 1 +80003950: 13 06 10 00 addi a2, zero, 1 +80003954: 93 86 16 00 addi a3, a3, 1 +80003958: 23 a2 c8 00 sw a2, 4(a7) +8000395c: 23 26 f1 0e sw a5, 236(sp) +80003960: 23 24 d1 0e sw a3, 232(sp) +80003964: 13 06 70 00 addi a2, zero, 7 +80003968: 93 88 88 00 addi a7, a7, 8 +8000396c: 63 40 d6 60 blt a2, a3, 1536 +80003970: 63 8c 0f 02 beqz t6, 56 +80003974: 83 26 81 0e lw a3, 232(sp) +80003978: 13 06 81 0c addi a2, sp, 200 +8000397c: 23 a0 c8 00 sw a2, 0(a7) +80003980: 93 87 27 00 addi a5, a5, 2 +80003984: 13 06 20 00 addi a2, zero, 2 +80003988: 93 86 16 00 addi a3, a3, 1 +8000398c: 23 a2 c8 00 sw a2, 4(a7) +80003990: 23 26 f1 0e sw a5, 236(sp) +80003994: 23 24 d1 0e sw a3, 232(sp) +80003998: 13 06 70 00 addi a2, zero, 7 +8000399c: 93 88 88 00 addi a7, a7, 8 +800039a0: 63 54 d6 00 bge a2, a3, 8 +800039a4: 6f 00 10 7b j 4016 +800039a8: 93 06 00 08 addi a3, zero, 128 +800039ac: e3 02 df 4e beq t5, a3, 3300 +800039b0: 33 03 93 41 sub t1, t1, s9 +800039b4: e3 4a 60 5a bgtz t1, 3508 +800039b8: 93 76 09 10 andi a3, s2, 256 +800039bc: e3 9e 06 38 bnez a3, 2972 +800039c0: 03 27 81 0e lw a4, 232(sp) +800039c4: b3 87 97 01 add a5, a5, s9 +800039c8: 23 a0 a8 01 sw s10, 0(a7) +800039cc: 13 07 17 00 addi a4, a4, 1 +800039d0: 23 a2 98 01 sw s9, 4(a7) +800039d4: 23 26 f1 0e sw a5, 236(sp) +800039d8: 23 24 e1 0e sw a4, 232(sp) +800039dc: 93 06 70 00 addi a3, zero, 7 +800039e0: 63 c0 e6 6e blt a3, a4, 1760 +800039e4: 93 88 88 00 addi a7, a7, 8 +800039e8: 13 79 49 00 andi s2, s2, 4 +800039ec: 63 06 09 00 beqz s2, 12 +800039f0: b3 04 8a 41 sub s1, s4, s8 +800039f4: 63 46 90 6e bgtz s1, 1772 +800039f8: 63 54 8a 01 bge s4, s8, 8 +800039fc: 13 0a 0c 00 mv s4, s8 +80003a00: 03 27 41 00 lw a4, 4(sp) +80003a04: 33 07 47 01 add a4, a4, s4 +80003a08: 23 22 e1 00 sw a4, 4(sp) +80003a0c: e3 9c 07 60 bnez a5, 3608 +80003a10: 23 24 01 0e sw zero, 232(sp) +80003a14: 63 88 0d 00 beqz s11, 16 +80003a18: 93 85 0d 00 mv a1, s11 +80003a1c: 13 85 0a 00 mv a0, s5 +80003a20: ef 20 d0 2e jal 10988 +80003a24: 93 88 0b 00 mv a7, s7 +80003a28: 13 0d 04 00 mv s10, s0 +80003a2c: 83 47 0d 00 lbu a5, 0(s10) +80003a30: e3 94 07 de bnez a5, -536 +80003a34: 83 27 c1 0e lw a5, 236(sp) +80003a38: 63 84 07 00 beqz a5, 8 +80003a3c: 6f 10 90 39 j 7064 +80003a40: 83 57 cb 00 lhu a5, 12(s6) +80003a44: 93 f7 07 04 andi a5, a5, 64 +80003a48: 63 84 07 00 beqz a5, 8 +80003a4c: 6f 20 80 3f j 9208 +80003a50: 83 20 c1 1e lw ra, 492(sp) +80003a54: 03 24 81 1e lw s0, 488(sp) +80003a58: 03 25 41 00 lw a0, 4(sp) +80003a5c: 83 24 41 1e lw s1, 484(sp) +80003a60: 03 29 01 1e lw s2, 480(sp) +80003a64: 83 29 c1 1d lw s3, 476(sp) +80003a68: 03 2a 81 1d lw s4, 472(sp) +80003a6c: 83 2a 41 1d lw s5, 468(sp) +80003a70: 03 2b 01 1d lw s6, 464(sp) +80003a74: 83 2b c1 1c lw s7, 460(sp) +80003a78: 03 2c 81 1c lw s8, 456(sp) +80003a7c: 83 2c 41 1c lw s9, 452(sp) +80003a80: 03 2d 01 1c lw s10, 448(sp) +80003a84: 83 2d c1 1b lw s11, 444(sp) +80003a88: 13 01 01 1f addi sp, sp, 496 +80003a8c: 67 80 00 00 ret +80003a90: 13 85 0a 00 mv a0, s5 +80003a94: 23 2e 11 01 sw a7, 28(sp) +80003a98: 23 24 61 00 sw t1, 8(sp) +80003a9c: ef 50 d0 12 jal 22828 +80003aa0: 83 27 45 00 lw a5, 4(a0) +80003aa4: 13 85 07 00 mv a0, a5 +80003aa8: 23 26 f1 04 sw a5, 76(sp) +80003aac: ef 70 00 5c jal 30144 +80003ab0: 93 07 05 00 mv a5, a0 +80003ab4: 13 85 0a 00 mv a0, s5 +80003ab8: 93 84 07 00 mv s1, a5 +80003abc: 23 24 f1 04 sw a5, 72(sp) +80003ac0: ef 50 90 10 jal 22792 +80003ac4: 83 27 85 00 lw a5, 8(a0) +80003ac8: 03 23 81 00 lw t1, 8(sp) +80003acc: 83 28 c1 01 lw a7, 28(sp) +80003ad0: 23 2c f1 02 sw a5, 56(sp) +80003ad4: 63 84 04 00 beqz s1, 8 +80003ad8: 6f 10 c0 15 j 4444 +80003adc: 83 44 04 00 lbu s1, 0(s0) +80003ae0: 6f f0 df db j -580 +80003ae4: 83 44 04 00 lbu s1, 0(s0) +80003ae8: 13 69 09 02 ori s2, s2, 32 +80003aec: 6f f0 1f db j -592 +80003af0: 13 69 09 01 ori s2, s2, 16 +80003af4: 93 77 09 02 andi a5, s2, 32 +80003af8: 63 88 07 6c beqz a5, 1744 +80003afc: 83 27 c1 00 lw a5, 12(sp) +80003b00: 93 87 77 00 addi a5, a5, 7 +80003b04: 93 f7 87 ff andi a5, a5, -8 +80003b08: 03 a7 47 00 lw a4, 4(a5) +80003b0c: 83 ad 07 00 lw s11, 0(a5) +80003b10: 93 87 87 00 addi a5, a5, 8 +80003b14: 23 26 f1 00 sw a5, 12(sp) +80003b18: 93 0c 07 00 mv s9, a4 +80003b1c: 63 40 07 6e bltz a4, 1760 +80003b20: 13 07 f0 ff addi a4, zero, -1 +80003b24: 13 0c 09 00 mv s8, s2 +80003b28: e3 0c e3 00 beq t1, a4, 2072 +80003b2c: 33 e7 9d 01 or a4, s11, s9 +80003b30: 13 7c f9 f7 andi s8, s2, -129 +80003b34: e3 16 07 00 bnez a4, 2060 +80003b38: e3 1a 03 00 bnez t1, 2068 +80003b3c: 13 09 0c 00 mv s2, s8 +80003b40: 13 03 00 00 mv t1, zero +80003b44: 93 0c 00 00 mv s9, zero +80003b48: 13 0d 01 1b addi s10, sp, 432 +80003b4c: 13 8c 0c 00 mv s8, s9 +80003b50: 63 d4 6c 00 bge s9, t1, 8 +80003b54: 13 0c 03 00 mv s8, t1 +80003b58: 83 47 71 0c lbu a5, 199(sp) +80003b5c: 23 26 01 02 sw zero, 44(sp) +80003b60: 23 2a 01 02 sw zero, 52(sp) +80003b64: 23 28 01 02 sw zero, 48(sp) +80003b68: 93 0d 00 00 mv s11, zero +80003b6c: e3 86 07 da beqz a5, -596 +80003b70: 13 0c 1c 00 addi s8, s8, 1 +80003b74: 6f f0 5f da j -604 +80003b78: 13 69 09 01 ori s2, s2, 16 +80003b7c: 93 77 09 02 andi a5, s2, 32 +80003b80: 63 8c 07 60 beqz a5, 1560 +80003b84: 83 27 c1 00 lw a5, 12(sp) +80003b88: 13 87 77 00 addi a4, a5, 7 +80003b8c: 13 77 87 ff andi a4, a4, -8 +80003b90: 83 2d 07 00 lw s11, 0(a4) +80003b94: 83 2c 47 00 lw s9, 4(a4) +80003b98: 93 07 87 00 addi a5, a4, 8 +80003b9c: 23 26 f1 00 sw a5, 12(sp) +80003ba0: 13 7c f9 bf andi s8, s2, -1025 +80003ba4: 13 07 00 00 mv a4, zero +80003ba8: a3 03 01 0c sb zero, 199(sp) +80003bac: 93 06 f0 ff addi a3, zero, -1 +80003bb0: 63 0a d3 66 beq t1, a3, 1652 +80003bb4: b3 e6 9d 01 or a3, s11, s9 +80003bb8: 13 79 fc f7 andi s2, s8, -129 +80003bbc: e3 98 06 48 bnez a3, 3216 +80003bc0: e3 1e 03 12 bnez t1, 2364 +80003bc4: e3 1e 07 f6 bnez a4, -132 +80003bc8: 93 7c 1c 00 andi s9, s8, 1 +80003bcc: 13 0d 01 1b addi s10, sp, 432 +80003bd0: e3 8e 0c f6 beqz s9, -132 +80003bd4: 93 07 00 03 addi a5, zero, 48 +80003bd8: a3 07 f1 1a sb a5, 431(sp) +80003bdc: 13 0d f1 1a addi s10, sp, 431 +80003be0: 6f f0 df f6 j -148 +80003be4: b3 04 a4 41 sub s1, s0, s10 +80003be8: e3 18 a4 c5 bne s0, s10, -944 +80003bec: 83 47 04 00 lbu a5, 0(s0) +80003bf0: 6f f0 5f c8 j -892 +80003bf4: 13 06 41 0e addi a2, sp, 228 +80003bf8: 93 05 0b 00 mv a1, s6 +80003bfc: 13 85 0a 00 mv a0, s5 +80003c00: ef 70 00 5a jal 30112 +80003c04: e3 1e 05 e2 bnez a0, -452 +80003c08: 93 88 0b 00 mv a7, s7 +80003c0c: 6f f0 9f c5 j -936 +80003c10: 93 77 89 00 andi a5, s2, 8 +80003c14: 63 84 07 00 beqz a5, 8 +80003c18: 6f 10 80 07 j 4216 +80003c1c: 83 27 c1 00 lw a5, 12(sp) +80003c20: 13 05 01 0b addi a0, sp, 176 +80003c24: 23 2e 11 01 sw a7, 28(sp) +80003c28: 93 87 77 00 addi a5, a5, 7 +80003c2c: 93 f7 87 ff andi a5, a5, -8 +80003c30: 83 a5 07 00 lw a1, 0(a5) +80003c34: 03 a6 47 00 lw a2, 4(a5) +80003c38: 93 87 87 00 addi a5, a5, 8 +80003c3c: 23 24 61 00 sw t1, 8(sp) +80003c40: 23 26 f1 00 sw a5, 12(sp) +80003c44: ef 10 01 18 jal 70016 +80003c48: 83 27 01 0b lw a5, 176(sp) +80003c4c: 83 28 c1 01 lw a7, 28(sp) +80003c50: 03 23 81 00 lw t1, 8(sp) +80003c54: 23 28 f1 0e sw a5, 240(sp) +80003c58: 83 27 41 0b lw a5, 180(sp) +80003c5c: 23 2a f1 0e sw a5, 244(sp) +80003c60: 83 27 81 0b lw a5, 184(sp) +80003c64: 23 2c f1 0e sw a5, 248(sp) +80003c68: 83 27 c1 0b lw a5, 188(sp) +80003c6c: 23 2e f1 0e sw a5, 252(sp) +80003c70: 13 05 01 0f addi a0, sp, 240 +80003c74: 23 2e 11 01 sw a7, 28(sp) +80003c78: 23 24 61 00 sw t1, 8(sp) +80003c7c: ef 50 00 6e jal 22240 +80003c80: 23 26 a1 0c sw a0, 204(sp) +80003c84: 93 07 20 00 addi a5, zero, 2 +80003c88: 03 23 81 00 lw t1, 8(sp) +80003c8c: 83 28 c1 01 lw a7, 28(sp) +80003c90: 63 14 f5 00 bne a0, a5, 8 +80003c94: 6f 10 c0 5e j 5612 +80003c98: 93 07 10 00 addi a5, zero, 1 +80003c9c: 63 14 f5 00 bne a0, a5, 8 +80003ca0: 6f 10 90 00 j 6152 +80003ca4: 93 07 10 06 addi a5, zero, 97 +80003ca8: 63 94 f4 00 bne s1, a5, 8 +80003cac: 6f 20 40 12 j 8484 +80003cb0: 93 07 10 04 addi a5, zero, 65 +80003cb4: 63 94 f4 00 bne s1, a5, 8 +80003cb8: 6f 10 d0 46 j 7276 +80003cbc: 93 fc f4 fd andi s9, s1, -33 +80003cc0: 93 07 f0 ff addi a5, zero, -1 +80003cc4: 23 2c 91 07 sw s9, 120(sp) +80003cc8: 63 14 f3 00 bne t1, a5, 8 +80003ccc: 6f 10 90 15 j 6488 +80003cd0: 93 07 70 04 addi a5, zero, 71 +80003cd4: 63 94 fc 00 bne s9, a5, 8 +80003cd8: 6f 20 80 17 j 8568 +80003cdc: 03 2e c1 0f lw t3, 252(sp) +80003ce0: 23 24 21 07 sw s2, 104(sp) +80003ce4: 83 2e 01 0f lw t4, 240(sp) +80003ce8: 03 2f 41 0f lw t5, 244(sp) +80003cec: 83 2f 81 0f lw t6, 248(sp) +80003cf0: 93 67 09 10 ori a5, s2, 256 +80003cf4: 63 54 0e 00 bgez t3, 8 +80003cf8: 6f 20 00 2a j 8864 +80003cfc: 23 2e 01 06 sw zero, 124(sp) +80003d00: 13 89 07 00 mv s2, a5 +80003d04: 93 0d 00 00 mv s11, zero +80003d08: 93 07 60 04 addi a5, zero, 70 +80003d0c: 63 94 fc 00 bne s9, a5, 8 +80003d10: 6f 10 d0 21 j 6684 +80003d14: 93 07 50 04 addi a5, zero, 69 +80003d18: 23 24 11 03 sw a7, 40(sp) +80003d1c: 63 84 fc 00 beq s9, a5, 8 +80003d20: 6f 10 d0 29 j 6812 +80003d24: 93 0c 13 00 addi s9, t1, 1 +80003d28: 13 0c 01 0b addi s8, sp, 176 +80003d2c: 13 08 c1 0d addi a6, sp, 220 +80003d30: 93 86 0c 00 mv a3, s9 +80003d34: 93 07 01 0d addi a5, sp, 208 +80003d38: 13 07 c1 0c addi a4, sp, 204 +80003d3c: 13 06 20 00 addi a2, zero, 2 +80003d40: 93 05 0c 00 mv a1, s8 +80003d44: 13 85 0a 00 mv a0, s5 +80003d48: 23 22 61 02 sw t1, 36(sp) +80003d4c: 23 28 d1 0b sw t4, 176(sp) +80003d50: 23 20 d1 03 sw t4, 32(sp) +80003d54: 23 2a e1 0b sw t5, 180(sp) +80003d58: 23 2e e1 01 sw t5, 28(sp) +80003d5c: 23 2c f1 0b sw t6, 184(sp) +80003d60: 23 28 f1 01 sw t6, 16(sp) +80003d64: 23 2e c1 0b sw t3, 188(sp) +80003d68: 23 24 c1 01 sw t3, 8(sp) +80003d6c: ef 40 c0 32 jal 17196 +80003d70: 03 2e 81 00 lw t3, 8(sp) +80003d74: 83 2f 01 01 lw t6, 16(sp) +80003d78: 03 2f c1 01 lw t5, 28(sp) +80003d7c: 83 2e 01 02 lw t4, 32(sp) +80003d80: 03 23 41 02 lw t1, 36(sp) +80003d84: 83 28 81 02 lw a7, 40(sp) +80003d88: 33 08 95 01 add a6, a0, s9 +80003d8c: 13 0d 05 00 mv s10, a0 +80003d90: 93 0c 01 0a addi s9, sp, 160 +80003d94: 93 85 0c 00 mv a1, s9 +80003d98: 13 05 0c 00 mv a0, s8 +80003d9c: 23 2e 01 01 sw a6, 28(sp) +80003da0: 23 28 11 01 sw a7, 16(sp) +80003da4: 23 24 61 00 sw t1, 8(sp) +80003da8: 23 28 d1 0b sw t4, 176(sp) +80003dac: 23 2a e1 0b sw t5, 180(sp) +80003db0: 23 2c f1 0b sw t6, 184(sp) +80003db4: 23 2e c1 0b sw t3, 188(sp) +80003db8: 23 20 01 0a sw zero, 160(sp) +80003dbc: 23 22 01 0a sw zero, 164(sp) +80003dc0: 23 24 01 0a sw zero, 168(sp) +80003dc4: 23 26 01 0a sw zero, 172(sp) +80003dc8: ef d0 10 29 jal 55952 +80003dcc: 03 28 c1 01 lw a6, 28(sp) +80003dd0: 03 23 81 00 lw t1, 8(sp) +80003dd4: 83 28 01 01 lw a7, 16(sp) +80003dd8: 93 07 08 00 mv a5, a6 +80003ddc: 63 02 05 02 beqz a0, 36 +80003de0: 83 27 c1 0d lw a5, 220(sp) +80003de4: 63 fe 07 01 bgeu a5, a6, 28 +80003de8: 13 06 00 03 addi a2, zero, 48 +80003dec: 93 86 17 00 addi a3, a5, 1 +80003df0: 23 2e d1 0c sw a3, 220(sp) +80003df4: 23 80 c7 00 sb a2, 0(a5) +80003df8: 83 27 c1 0d lw a5, 220(sp) +80003dfc: e3 e8 07 ff bltu a5, a6, -16 +80003e00: 03 27 c1 0c lw a4, 204(sp) +80003e04: b3 87 a7 41 sub a5, a5, s10 +80003e08: 23 28 f1 00 sw a5, 16(sp) +80003e0c: 23 28 e1 02 sw a4, 48(sp) +80003e10: 03 27 81 07 lw a4, 120(sp) +80003e14: 93 07 70 04 addi a5, zero, 71 +80003e18: 63 14 f7 00 bne a4, a5, 8 +80003e1c: 6f 10 50 02 j 6180 +80003e20: 03 27 81 07 lw a4, 120(sp) +80003e24: 93 07 60 04 addi a5, zero, 70 +80003e28: 63 14 f7 00 bne a4, a5, 8 +80003e2c: 6f 10 50 27 j 6772 +80003e30: 83 27 01 03 lw a5, 48(sp) +80003e34: 03 27 81 07 lw a4, 120(sp) +80003e38: 93 05 10 04 addi a1, zero, 65 +80003e3c: 93 87 f7 ff addi a5, a5, -1 +80003e40: 23 26 f1 0c sw a5, 204(sp) +80003e44: 93 f6 f4 0f andi a3, s1, 255 +80003e48: 13 06 00 00 mv a2, zero +80003e4c: 63 18 b7 00 bne a4, a1, 16 +80003e50: 93 86 f6 00 addi a3, a3, 15 +80003e54: 93 f6 f6 0f andi a3, a3, 255 +80003e58: 13 06 10 00 addi a2, zero, 1 +80003e5c: 23 0a d1 0c sb a3, 212(sp) +80003e60: 93 06 b0 02 addi a3, zero, 43 +80003e64: 63 da 07 00 bgez a5, 20 +80003e68: 03 27 01 03 lw a4, 48(sp) +80003e6c: 93 07 10 00 addi a5, zero, 1 +80003e70: 93 06 d0 02 addi a3, zero, 45 +80003e74: b3 87 e7 40 sub a5, a5, a4 +80003e78: a3 0a d1 0c sb a3, 213(sp) +80003e7c: 93 06 90 00 addi a3, zero, 9 +80003e80: 63 c4 f6 00 blt a3, a5, 8 +80003e84: 6f 20 00 23 j 8752 +80003e88: 13 08 31 0e addi a6, sp, 227 +80003e8c: 13 05 08 00 mv a0, a6 +80003e90: 13 06 a0 00 addi a2, zero, 10 +80003e94: 13 0e 30 06 addi t3, zero, 99 +80003e98: b3 e6 c7 02 rem a3, a5, a2 +80003e9c: 93 05 05 00 mv a1, a0 +80003ea0: 13 83 07 00 mv t1, a5 +80003ea4: 13 05 f5 ff addi a0, a0, -1 +80003ea8: 93 86 06 03 addi a3, a3, 48 +80003eac: a3 8f d5 fe sb a3, -1(a1) +80003eb0: b3 c7 c7 02 div a5, a5, a2 +80003eb4: e3 42 6e fe blt t3, t1, -28 +80003eb8: 93 87 07 03 addi a5, a5, 48 +80003ebc: 13 f6 f7 0f andi a2, a5, 255 +80003ec0: a3 0f c5 fe sb a2, -1(a0) +80003ec4: 93 87 e5 ff addi a5, a1, -2 +80003ec8: 63 e4 07 01 bltu a5, a6, 8 +80003ecc: 6f 20 40 33 j 9012 +80003ed0: 93 06 61 0d addi a3, sp, 214 +80003ed4: 6f 00 80 00 j 8 +80003ed8: 03 c6 07 00 lbu a2, 0(a5) +80003edc: 23 80 c6 00 sb a2, 0(a3) +80003ee0: 93 87 17 00 addi a5, a5, 1 +80003ee4: 93 86 16 00 addi a3, a3, 1 +80003ee8: e3 98 07 ff bne a5, a6, -16 +80003eec: 93 07 51 0e addi a5, sp, 229 +80003ef0: b3 87 b7 40 sub a5, a5, a1 +80003ef4: 13 07 61 0d addi a4, sp, 214 +80003ef8: b3 07 f7 00 add a5, a4, a5 +80003efc: 93 06 41 0d addi a3, sp, 212 +80003f00: b3 87 d7 40 sub a5, a5, a3 +80003f04: 23 22 f1 04 sw a5, 68(sp) +80003f08: 03 27 01 01 lw a4, 16(sp) +80003f0c: 83 26 41 04 lw a3, 68(sp) +80003f10: 93 07 10 00 addi a5, zero, 1 +80003f14: b3 0c d7 00 add s9, a4, a3 +80003f18: 63 c4 e7 00 blt a5, a4, 8 +80003f1c: 6f 20 80 1c j 8648 +80003f20: 83 27 c1 03 lw a5, 60(sp) +80003f24: b3 8c fc 00 add s9, s9, a5 +80003f28: 83 27 81 06 lw a5, 104(sp) +80003f2c: 13 cc fc ff not s8, s9 +80003f30: 13 5c fc 41 srai s8, s8, 31 +80003f34: 13 f9 f7 bf andi s2, a5, -1025 +80003f38: 13 69 09 10 ori s2, s2, 256 +80003f3c: 33 fc 8c 01 and s8, s9, s8 +80003f40: 23 26 01 02 sw zero, 44(sp) +80003f44: 23 2a 01 02 sw zero, 52(sp) +80003f48: 23 28 01 02 sw zero, 48(sp) +80003f4c: 83 27 c1 07 lw a5, 124(sp) +80003f50: 63 94 07 00 bnez a5, 8 +80003f54: 6f 10 00 76 j 5984 +80003f58: 93 07 d0 02 addi a5, zero, 45 +80003f5c: a3 03 f1 0c sb a5, 199(sp) +80003f60: 13 03 00 00 mv t1, zero +80003f64: 13 0c 1c 00 addi s8, s8, 1 +80003f68: 6f f0 1f 9b j -1616 +80003f6c: 13 06 41 0e addi a2, sp, 228 +80003f70: 93 05 0b 00 mv a1, s6 +80003f74: 13 85 0a 00 mv a0, s5 +80003f78: 23 20 61 02 sw t1, 32(sp) +80003f7c: 23 2e e1 01 sw t5, 28(sp) +80003f80: 23 24 f1 01 sw t6, 8(sp) +80003f84: ef 70 c0 21 jal 29212 +80003f88: e3 18 05 0a bnez a0, 2224 +80003f8c: 83 27 c1 0e lw a5, 236(sp) +80003f90: 03 23 01 02 lw t1, 32(sp) +80003f94: 03 2f c1 01 lw t5, 28(sp) +80003f98: 83 2f 81 00 lw t6, 8(sp) +80003f9c: 93 88 0b 00 mv a7, s7 +80003fa0: 6f f0 1f 9d j -1584 +80003fa4: 03 26 81 0e lw a2, 232(sp) +80003fa8: 03 27 01 01 lw a4, 16(sp) +80003fac: 93 06 10 00 addi a3, zero, 1 +80003fb0: 23 a0 a8 01 sw s10, 0(a7) +80003fb4: 93 87 17 00 addi a5, a5, 1 +80003fb8: 93 04 16 00 addi s1, a2, 1 +80003fbc: 93 8c 88 00 addi s9, a7, 8 +80003fc0: e3 dc e6 32 bge a3, a4, 2872 +80003fc4: 93 06 10 00 addi a3, zero, 1 +80003fc8: 23 a2 d8 00 sw a3, 4(a7) +80003fcc: 23 26 f1 0e sw a5, 236(sp) +80003fd0: 23 24 91 0e sw s1, 232(sp) +80003fd4: 93 06 70 00 addi a3, zero, 7 +80003fd8: e3 c6 96 3e blt a3, s1, 3052 +80003fdc: 03 27 c1 03 lw a4, 60(sp) +80003fe0: 83 26 01 04 lw a3, 64(sp) +80003fe4: 93 84 14 00 addi s1, s1, 1 +80003fe8: b3 87 e7 00 add a5, a5, a4 +80003fec: 23 a0 dc 00 sw a3, 0(s9) +80003ff0: 23 a2 ec 00 sw a4, 4(s9) +80003ff4: 23 26 f1 0e sw a5, 236(sp) +80003ff8: 23 24 91 0e sw s1, 232(sp) +80003ffc: 93 06 70 00 addi a3, zero, 7 +80004000: 93 8c 8c 00 addi s9, s9, 8 +80004004: e3 c2 96 3e blt a3, s1, 3044 +80004008: 83 26 01 0f lw a3, 240(sp) +8000400c: 13 88 14 00 addi a6, s1, 1 +80004010: 93 05 01 0a addi a1, sp, 160 +80004014: 23 28 d1 0a sw a3, 176(sp) +80004018: 83 26 41 0f lw a3, 244(sp) +8000401c: 13 05 01 0b addi a0, sp, 176 +80004020: 23 2e f1 00 sw a5, 28(sp) +80004024: 23 2a d1 0a sw a3, 180(sp) +80004028: 83 26 81 0f lw a3, 248(sp) +8000402c: 23 24 01 01 sw a6, 8(sp) +80004030: 23 20 01 0a sw zero, 160(sp) +80004034: 23 2c d1 0a sw a3, 184(sp) +80004038: 83 26 c1 0f lw a3, 252(sp) +8000403c: 23 22 01 0a sw zero, 164(sp) +80004040: 23 24 01 0a sw zero, 168(sp) +80004044: 23 2e d1 0a sw a3, 188(sp) +80004048: 23 26 01 0a sw zero, 172(sp) +8000404c: ef d0 d0 00 jal 55308 +80004050: 83 27 01 01 lw a5, 16(sp) +80004054: 03 28 81 00 lw a6, 8(sp) +80004058: 93 88 8c 00 addi a7, s9, 8 +8000405c: 93 86 f7 ff addi a3, a5, -1 +80004060: 13 06 08 00 mv a2, a6 +80004064: 83 27 c1 01 lw a5, 28(sp) +80004068: e3 0c 05 2a beqz a0, 2744 +8000406c: 13 07 1d 00 addi a4, s10, 1 +80004070: b3 87 d7 00 add a5, a5, a3 +80004074: 23 a0 ec 00 sw a4, 0(s9) +80004078: 23 a2 dc 00 sw a3, 4(s9) +8000407c: 23 26 f1 0e sw a5, 236(sp) +80004080: 23 24 01 0f sw a6, 232(sp) +80004084: 13 07 70 00 addi a4, zero, 7 +80004088: e3 4a 07 77 blt a4, a6, 3956 +8000408c: 13 87 0c 01 addi a4, s9, 16 +80004090: 13 86 24 00 addi a2, s1, 2 +80004094: 93 8c 08 00 mv s9, a7 +80004098: 93 08 07 00 mv a7, a4 +8000409c: 83 26 41 04 lw a3, 68(sp) +800040a0: 13 07 41 0d addi a4, sp, 212 +800040a4: 23 a0 ec 00 sw a4, 0(s9) +800040a8: b3 87 f6 00 add a5, a3, a5 +800040ac: 23 a2 dc 00 sw a3, 4(s9) +800040b0: 23 26 f1 0e sw a5, 236(sp) +800040b4: 23 24 c1 0e sw a2, 232(sp) +800040b8: 13 07 70 00 addi a4, zero, 7 +800040bc: e3 56 c7 92 bge a4, a2, -1748 +800040c0: 13 06 41 0e addi a2, sp, 228 +800040c4: 93 05 0b 00 mv a1, s6 +800040c8: 13 85 0a 00 mv a0, s5 +800040cc: ef 70 40 0d jal 28884 +800040d0: 63 14 05 76 bnez a0, 1896 +800040d4: 83 27 c1 0e lw a5, 236(sp) +800040d8: 93 88 0b 00 mv a7, s7 +800040dc: 6f f0 df 90 j -1780 +800040e0: 93 06 00 01 addi a3, zero, 16 +800040e4: 03 27 81 0e lw a4, 232(sp) +800040e8: 63 c4 96 00 blt a3, s1, 8 +800040ec: 6f 10 d0 02 j 6188 +800040f0: b7 56 01 80 lui a3, 524309 +800040f4: 93 8e 86 74 addi t4, a3, 1864 +800040f8: 13 09 00 01 addi s2, zero, 16 +800040fc: 93 0c 70 00 addi s9, zero, 7 +80004100: 6f 00 c0 00 j 12 +80004104: 93 84 04 ff addi s1, s1, -16 +80004108: 63 5a 99 04 bge s2, s1, 84 +8000410c: 93 87 07 01 addi a5, a5, 16 +80004110: 13 07 17 00 addi a4, a4, 1 +80004114: 23 a0 d8 01 sw t4, 0(a7) +80004118: 23 a2 28 01 sw s2, 4(a7) +8000411c: 23 26 f1 0e sw a5, 236(sp) +80004120: 23 24 e1 0e sw a4, 232(sp) +80004124: 93 88 88 00 addi a7, a7, 8 +80004128: e3 de ec fc bge s9, a4, -36 +8000412c: 13 06 41 0e addi a2, sp, 228 +80004130: 93 05 0b 00 mv a1, s6 +80004134: 13 85 0a 00 mv a0, s5 +80004138: 23 24 d1 01 sw t4, 8(sp) +8000413c: ef 70 40 06 jal 28772 +80004140: 63 1c 05 6e bnez a0, 1784 +80004144: 93 84 04 ff addi s1, s1, -16 +80004148: 83 27 c1 0e lw a5, 236(sp) +8000414c: 03 27 81 0e lw a4, 232(sp) +80004150: 83 2e 81 00 lw t4, 8(sp) +80004154: 93 88 0b 00 mv a7, s7 +80004158: e3 4a 99 fa blt s2, s1, -76 +8000415c: b3 87 97 00 add a5, a5, s1 +80004160: 13 07 17 00 addi a4, a4, 1 +80004164: 23 a0 d8 01 sw t4, 0(a7) +80004168: 23 a2 98 00 sw s1, 4(a7) +8000416c: 23 26 f1 0e sw a5, 236(sp) +80004170: 23 24 e1 0e sw a4, 232(sp) +80004174: 93 06 70 00 addi a3, zero, 7 +80004178: e3 d0 e6 88 bge a3, a4, -1920 +8000417c: 13 06 41 0e addi a2, sp, 228 +80004180: 93 05 0b 00 mv a1, s6 +80004184: 13 85 0a 00 mv a0, s5 +80004188: ef 70 80 01 jal 28696 +8000418c: 63 16 05 6a bnez a0, 1708 +80004190: 83 27 c1 0e lw a5, 236(sp) +80004194: 6f f0 5f 86 j -1948 +80004198: 83 26 c1 00 lw a3, 12(sp) +8000419c: 93 77 09 01 andi a5, s2, 16 +800041a0: 13 87 46 00 addi a4, a3, 4 +800041a4: e3 9e 07 2c bnez a5, 2780 +800041a8: 93 77 09 04 andi a5, s2, 64 +800041ac: 63 94 07 00 bnez a5, 8 +800041b0: 6f 10 c0 2d j 4828 +800041b4: 83 27 c1 00 lw a5, 12(sp) +800041b8: 93 0c 00 00 mv s9, zero +800041bc: 23 26 e1 00 sw a4, 12(sp) +800041c0: 83 dd 07 00 lhu s11, 0(a5) +800041c4: 6f f0 df 9d j -1572 +800041c8: 83 26 c1 00 lw a3, 12(sp) +800041cc: 93 77 09 01 andi a5, s2, 16 +800041d0: 13 87 46 00 addi a4, a3, 4 +800041d4: e3 9c 07 28 bnez a5, 2712 +800041d8: 93 77 09 04 andi a5, s2, 64 +800041dc: 63 94 07 00 bnez a5, 8 +800041e0: 6f 10 00 27 j 4720 +800041e4: 83 27 c1 00 lw a5, 12(sp) +800041e8: 23 26 e1 00 sw a4, 12(sp) +800041ec: 83 9d 07 00 lh s11, 0(a5) +800041f0: 93 dc fd 41 srai s9, s11, 31 +800041f4: 13 87 0c 00 mv a4, s9 +800041f8: e3 54 07 92 bgez a4, -1752 +800041fc: 33 37 b0 01 snez a4, s11 +80004200: b3 07 90 41 neg a5, s9 +80004204: b3 8c e7 40 sub s9, a5, a4 +80004208: 13 07 d0 02 addi a4, zero, 45 +8000420c: a3 03 e1 0c sb a4, 199(sp) +80004210: 93 06 f0 ff addi a3, zero, -1 +80004214: b3 0d b0 41 neg s11, s11 +80004218: 13 0c 09 00 mv s8, s2 +8000421c: 13 07 10 00 addi a4, zero, 1 +80004220: e3 1a d3 98 bne t1, a3, -1644 +80004224: 93 06 10 00 addi a3, zero, 1 +80004228: 63 0c d7 10 beq a4, a3, 280 +8000422c: 93 06 20 00 addi a3, zero, 2 +80004230: 63 02 d7 2e beq a4, a3, 740 +80004234: 13 0d 01 1b addi s10, sp, 432 +80004238: 13 96 dc 01 slli a2, s9, 29 +8000423c: 93 f6 7d 00 andi a3, s11, 7 +80004240: 93 dd 3d 00 srli s11, s11, 3 +80004244: 93 86 06 03 addi a3, a3, 48 +80004248: b3 6d b6 01 or s11, a2, s11 +8000424c: 93 dc 3c 00 srli s9, s9, 3 +80004250: a3 0f dd fe sb a3, -1(s10) +80004254: 33 e6 9d 01 or a2, s11, s9 +80004258: 93 05 0d 00 mv a1, s10 +8000425c: 13 0d fd ff addi s10, s10, -1 +80004260: e3 1c 06 fc bnez a2, -40 +80004264: 93 77 1c 00 andi a5, s8, 1 +80004268: 63 80 07 2e beqz a5, 736 +8000426c: 93 07 00 03 addi a5, zero, 48 +80004270: 63 8c f6 2c beq a3, a5, 728 +80004274: 93 85 e5 ff addi a1, a1, -2 +80004278: a3 0f fd fe sb a5, -1(s10) +8000427c: 93 07 01 1b addi a5, sp, 432 +80004280: b3 8c b7 40 sub s9, a5, a1 +80004284: 13 09 0c 00 mv s2, s8 +80004288: 13 8d 05 00 mv s10, a1 +8000428c: 6f f0 1f 8c j -1856 +80004290: 83 27 c1 00 lw a5, 12(sp) +80004294: a3 03 01 0c sb zero, 199(sp) +80004298: 03 ad 07 00 lw s10, 0(a5) +8000429c: 93 86 47 00 addi a3, a5, 4 +800042a0: e3 06 0d 30 beqz s10, 2828 +800042a4: 93 07 f0 ff addi a5, zero, -1 +800042a8: 63 14 f3 00 bne t1, a5, 8 +800042ac: 6f 10 80 10 j 4360 +800042b0: 13 06 03 00 mv a2, t1 +800042b4: 93 05 00 00 mv a1, zero +800042b8: 13 05 0d 00 mv a0, s10 +800042bc: 23 2e d1 00 sw a3, 28(sp) +800042c0: 23 26 11 01 sw a7, 12(sp) +800042c4: 23 24 61 00 sw t1, 8(sp) +800042c8: ef 50 10 0d jal 22736 +800042cc: 03 23 81 00 lw t1, 8(sp) +800042d0: 83 28 c1 00 lw a7, 12(sp) +800042d4: 83 26 c1 01 lw a3, 28(sp) +800042d8: 93 0d 05 00 mv s11, a0 +800042dc: 63 14 05 00 bnez a0, 8 +800042e0: 6f 10 40 56 j 5476 +800042e4: b3 0c a5 41 sub s9, a0, s10 +800042e8: 83 47 71 0c lbu a5, 199(sp) +800042ec: 13 cc fc ff not s8, s9 +800042f0: 13 5c fc 41 srai s8, s8, 31 +800042f4: 23 26 d1 00 sw a3, 12(sp) +800042f8: 23 26 01 02 sw zero, 44(sp) +800042fc: 23 2a 01 02 sw zero, 52(sp) +80004300: 23 28 01 02 sw zero, 48(sp) +80004304: 33 fc 8c 01 and s8, s9, s8 +80004308: 93 0d 00 00 mv s11, zero +8000430c: 13 03 00 00 mv t1, zero +80004310: e3 90 07 86 bnez a5, -1952 +80004314: 6f f0 4f e0 j -2556 +80004318: 03 27 c1 00 lw a4, 12(sp) +8000431c: a3 03 01 0c sb zero, 199(sp) +80004320: 13 0c 10 00 addi s8, zero, 1 +80004324: 83 27 07 00 lw a5, 0(a4) +80004328: 13 07 47 00 addi a4, a4, 4 +8000432c: 23 26 e1 00 sw a4, 12(sp) +80004330: 23 06 f1 14 sb a5, 332(sp) +80004334: 93 0c 10 00 addi s9, zero, 1 +80004338: 13 0d c1 14 addi s10, sp, 332 +8000433c: 6f f0 8f dc j -2616 +80004340: e3 94 0c 4e bnez s9, 3304 +80004344: 13 07 90 00 addi a4, zero, 9 +80004348: e3 60 b7 4f bltu a4, s11, 3296 +8000434c: 93 8d 0d 03 addi s11, s11, 48 +80004350: a3 07 b1 1b sb s11, 431(sp) +80004354: 13 09 0c 00 mv s2, s8 +80004358: 93 0c 10 00 addi s9, zero, 1 +8000435c: 13 0d f1 1a addi s10, sp, 431 +80004360: 6f f0 cf fe j -2068 +80004364: 83 44 04 00 lbu s1, 0(s0) +80004368: 13 69 49 00 ori s2, s2, 4 +8000436c: 6f f0 0f d3 j -2768 +80004370: 93 07 b0 02 addi a5, zero, 43 +80004374: 83 44 04 00 lbu s1, 0(s0) +80004378: a3 03 f1 0c sb a5, 199(sp) +8000437c: 6f f0 0f d2 j -2784 +80004380: 83 44 04 00 lbu s1, 0(s0) +80004384: 13 69 09 08 ori s2, s2, 128 +80004388: 6f f0 4f d1 j -2796 +8000438c: 83 44 04 00 lbu s1, 0(s0) +80004390: 93 06 14 00 addi a3, s0, 1 +80004394: 63 94 b4 01 bne s1, s11, 8 +80004398: 6f 10 d0 61 j 7708 +8000439c: 93 87 04 fd addi a5, s1, -48 +800043a0: 13 84 06 00 mv s0, a3 +800043a4: 13 03 00 00 mv t1, zero +800043a8: 63 ec fc ce bltu s9, a5, -2824 +800043ac: 83 44 04 00 lbu s1, 0(s0) +800043b0: 93 16 23 00 slli a3, t1, 2 +800043b4: 33 83 66 00 add t1, a3, t1 +800043b8: 13 13 13 00 slli t1, t1, 1 +800043bc: 33 03 f3 00 add t1, t1, a5 +800043c0: 93 87 04 fd addi a5, s1, -48 +800043c4: 13 04 14 00 addi s0, s0, 1 +800043c8: e3 f2 fc fe bgeu s9, a5, -28 +800043cc: 6f f0 4f cd j -2860 +800043d0: 83 27 c1 00 lw a5, 12(sp) +800043d4: 83 44 04 00 lbu s1, 0(s0) +800043d8: 03 aa 07 00 lw s4, 0(a5) +800043dc: 93 87 47 00 addi a5, a5, 4 +800043e0: 23 26 f1 00 sw a5, 12(sp) +800043e4: 63 5c 0a ca bgez s4, -2888 +800043e8: 33 0a 40 41 neg s4, s4 +800043ec: 13 69 49 00 ori s2, s2, 4 +800043f0: 6f f0 cf ca j -2900 +800043f4: 83 44 04 00 lbu s1, 0(s0) +800043f8: 13 69 19 00 ori s2, s2, 1 +800043fc: 6f f0 0f ca j -2912 +80004400: 83 47 71 0c lbu a5, 199(sp) +80004404: 83 44 04 00 lbu s1, 0(s0) +80004408: 63 9a 07 c8 bnez a5, -2924 +8000440c: 93 07 00 02 addi a5, zero, 32 +80004410: a3 03 f1 0c sb a5, 199(sp) +80004414: 6f f0 8f c8 j -2936 +80004418: 13 6c 09 01 ori s8, s2, 16 +8000441c: 93 77 0c 02 andi a5, s8, 32 +80004420: 63 8a 07 76 beqz a5, 1908 +80004424: 83 27 c1 00 lw a5, 12(sp) +80004428: 13 87 77 00 addi a4, a5, 7 +8000442c: 13 77 87 ff andi a4, a4, -8 +80004430: 93 07 87 00 addi a5, a4, 8 +80004434: 83 2d 07 00 lw s11, 0(a4) +80004438: 83 2c 47 00 lw s9, 4(a4) +8000443c: 23 26 f1 00 sw a5, 12(sp) +80004440: 13 07 10 00 addi a4, zero, 1 +80004444: 6f f0 4f f6 j -2204 +80004448: 83 27 c1 00 lw a5, 12(sp) +8000444c: 37 87 ff ff lui a4, 1048568 +80004450: 13 47 07 83 xori a4, a4, -2000 +80004454: 83 ad 07 00 lw s11, 0(a5) +80004458: 23 14 e1 0c sh a4, 200(sp) +8000445c: 93 87 47 00 addi a5, a5, 4 +80004460: 37 57 01 80 lui a4, 524309 +80004464: 23 26 f1 00 sw a5, 12(sp) +80004468: 93 07 87 5a addi a5, a4, 1448 +8000446c: 93 0c 00 00 mv s9, zero +80004470: 13 6c 29 00 ori s8, s2, 2 +80004474: 23 2c f1 00 sw a5, 24(sp) +80004478: 13 07 20 00 addi a4, zero, 2 +8000447c: 93 04 80 07 addi s1, zero, 120 +80004480: 6f f0 8f f2 j -2264 +80004484: 83 44 04 00 lbu s1, 0(s0) +80004488: 13 69 89 00 ori s2, s2, 8 +8000448c: 6f f0 0f c1 j -3056 +80004490: 83 44 04 00 lbu s1, 0(s0) +80004494: 93 07 c0 06 addi a5, zero, 108 +80004498: e3 86 f4 0c beq s1, a5, 2252 +8000449c: 13 69 09 01 ori s2, s2, 16 +800044a0: 6f f0 cf bf j -3076 +800044a4: 83 44 04 00 lbu s1, 0(s0) +800044a8: 93 07 80 06 addi a5, zero, 104 +800044ac: e3 84 f4 08 beq s1, a5, 2184 +800044b0: 13 69 09 04 ori s2, s2, 64 +800044b4: 6f f0 8f be j -3096 +800044b8: 83 26 c1 00 lw a3, 12(sp) +800044bc: 93 77 09 02 andi a5, s2, 32 +800044c0: 03 a7 06 00 lw a4, 0(a3) +800044c4: 93 86 46 00 addi a3, a3, 4 +800044c8: 23 26 d1 00 sw a3, 12(sp) +800044cc: 63 98 07 74 bnez a5, 1872 +800044d0: 93 77 09 01 andi a5, s2, 16 +800044d4: e3 9a 07 62 bnez a5, 3636 +800044d8: 93 77 09 04 andi a5, s2, 64 +800044dc: 63 84 07 00 beqz a5, 8 +800044e0: 6f 10 c0 08 j 4236 +800044e4: 13 79 09 20 andi s2, s2, 512 +800044e8: e3 00 09 62 beqz s2, 3616 +800044ec: 83 27 41 00 lw a5, 4(sp) +800044f0: 13 0d 04 00 mv s10, s0 +800044f4: 23 00 f7 00 sb a5, 0(a4) +800044f8: 6f f0 4f d3 j -2764 +800044fc: 93 06 10 00 addi a3, zero, 1 +80004500: 63 14 d7 00 bne a4, a3, 8 +80004504: 6f 10 90 13 j 6456 +80004508: 93 06 20 00 addi a3, zero, 2 +8000450c: 13 0c 09 00 mv s8, s2 +80004510: e3 12 d7 d2 bne a4, a3, -732 +80004514: 13 0d 01 1b addi s10, sp, 432 +80004518: 83 27 81 01 lw a5, 24(sp) +8000451c: 93 f6 fd 00 andi a3, s11, 15 +80004520: 93 dd 4d 00 srli s11, s11, 4 +80004524: b3 86 d7 00 add a3, a5, a3 +80004528: 03 c6 06 00 lbu a2, 0(a3) +8000452c: 93 96 cc 01 slli a3, s9, 28 +80004530: b3 ed b6 01 or s11, a3, s11 +80004534: 93 dc 4c 00 srli s9, s9, 4 +80004538: a3 0f cd fe sb a2, -1(s10) +8000453c: b3 e6 9d 01 or a3, s11, s9 +80004540: 13 0d fd ff addi s10, s10, -1 +80004544: e3 9a 06 fc bnez a3, -44 +80004548: 93 07 01 1b addi a5, sp, 432 +8000454c: b3 8c a7 41 sub s9, a5, s10 +80004550: 13 09 0c 00 mv s2, s8 +80004554: 6f f0 8f df j -2568 +80004558: 93 06 50 06 addi a3, zero, 101 +8000455c: e3 d4 96 a4 bge a3, s1, -1464 +80004560: 83 26 01 0f lw a3, 240(sp) +80004564: 93 05 01 0a addi a1, sp, 160 +80004568: 13 05 01 0b addi a0, sp, 176 +8000456c: 23 28 d1 0a sw a3, 176(sp) +80004570: 83 26 41 0f lw a3, 244(sp) +80004574: 23 2e f1 00 sw a5, 28(sp) +80004578: 23 24 11 01 sw a7, 8(sp) +8000457c: 23 2a d1 0a sw a3, 180(sp) +80004580: 83 26 81 0f lw a3, 248(sp) +80004584: 23 20 01 0a sw zero, 160(sp) +80004588: 23 22 01 0a sw zero, 164(sp) +8000458c: 23 2c d1 0a sw a3, 184(sp) +80004590: 83 26 c1 0f lw a3, 252(sp) +80004594: 23 24 01 0a sw zero, 168(sp) +80004598: 23 26 01 0a sw zero, 172(sp) +8000459c: 23 2e d1 0a sw a3, 188(sp) +800045a0: ef d0 80 2b jal 53944 +800045a4: 83 28 81 00 lw a7, 8(sp) +800045a8: 83 27 c1 01 lw a5, 28(sp) +800045ac: 63 1c 05 3c bnez a0, 984 +800045b0: 03 27 81 0e lw a4, 232(sp) +800045b4: b7 56 01 80 lui a3, 524309 +800045b8: 93 86 86 5d addi a3, a3, 1496 +800045bc: 23 a0 d8 00 sw a3, 0(a7) +800045c0: 93 87 17 00 addi a5, a5, 1 +800045c4: 93 06 10 00 addi a3, zero, 1 +800045c8: 13 07 17 00 addi a4, a4, 1 +800045cc: 23 a2 d8 00 sw a3, 4(a7) +800045d0: 23 26 f1 0e sw a5, 236(sp) +800045d4: 23 24 e1 0e sw a4, 232(sp) +800045d8: 93 06 70 00 addi a3, zero, 7 +800045dc: 93 88 88 00 addi a7, a7, 8 +800045e0: e3 c4 e6 42 blt a3, a4, 3112 +800045e4: 03 27 c1 0c lw a4, 204(sp) +800045e8: 83 26 01 01 lw a3, 16(sp) +800045ec: 63 50 d7 62 bge a4, a3, 1568 +800045f0: 03 27 01 04 lw a4, 64(sp) +800045f4: 83 26 c1 03 lw a3, 60(sp) +800045f8: 93 88 88 00 addi a7, a7, 8 +800045fc: 23 ac e8 fe sw a4, -8(a7) +80004600: 03 27 81 0e lw a4, 232(sp) +80004604: b3 87 d7 00 add a5, a5, a3 +80004608: 23 ae d8 fe sw a3, -4(a7) +8000460c: 13 07 17 00 addi a4, a4, 1 +80004610: 23 26 f1 0e sw a5, 236(sp) +80004614: 23 24 e1 0e sw a4, 232(sp) +80004618: 93 06 70 00 addi a3, zero, 7 +8000461c: 63 c4 e6 72 blt a3, a4, 1832 +80004620: 03 27 01 01 lw a4, 16(sp) +80004624: 93 04 f7 ff addi s1, a4, -1 +80004628: 63 50 90 bc blez s1, -3136 +8000462c: 93 06 00 01 addi a3, zero, 16 +80004630: 03 27 81 0e lw a4, 232(sp) +80004634: e3 da 96 3e bge a3, s1, 3060 +80004638: 93 0c 00 01 addi s9, zero, 16 +8000463c: 13 0d 70 00 addi s10, zero, 7 +80004640: 6f 00 c0 00 j 12 +80004644: 93 84 04 ff addi s1, s1, -16 +80004648: e3 d0 9c 3e bge s9, s1, 3040 +8000464c: 93 87 07 01 addi a5, a5, 16 +80004650: 13 07 17 00 addi a4, a4, 1 +80004654: 23 a0 38 01 sw s3, 0(a7) +80004658: 23 a2 98 01 sw s9, 4(a7) +8000465c: 23 26 f1 0e sw a5, 236(sp) +80004660: 23 24 e1 0e sw a4, 232(sp) +80004664: 93 88 88 00 addi a7, a7, 8 +80004668: e3 5e ed fc bge s10, a4, -36 +8000466c: 13 06 41 0e addi a2, sp, 228 +80004670: 93 05 0b 00 mv a1, s6 +80004674: 13 85 0a 00 mv a0, s5 +80004678: ef 60 90 32 jal 27432 +8000467c: 63 1e 05 1a bnez a0, 444 +80004680: 83 27 c1 0e lw a5, 236(sp) +80004684: 03 27 81 0e lw a4, 232(sp) +80004688: 93 88 0b 00 mv a7, s7 +8000468c: 6f f0 9f fb j -72 +80004690: 33 08 8a 41 sub a6, s4, s8 +80004694: 63 5e 00 b1 blez a6, -3300 +80004698: 13 06 00 01 addi a2, zero, 16 +8000469c: 83 26 81 0e lw a3, 232(sp) +800046a0: 63 5c 06 07 bge a2, a6, 120 +800046a4: 13 0e 00 01 addi t3, zero, 16 +800046a8: 93 0e 70 00 addi t4, zero, 7 +800046ac: 6f 00 c0 00 j 12 +800046b0: 13 08 08 ff addi a6, a6, -16 +800046b4: 63 52 0e 07 bge t3, a6, 100 +800046b8: 93 87 07 01 addi a5, a5, 16 +800046bc: 93 86 16 00 addi a3, a3, 1 +800046c0: 23 a0 38 01 sw s3, 0(a7) +800046c4: 23 a2 c8 01 sw t3, 4(a7) +800046c8: 23 26 f1 0e sw a5, 236(sp) +800046cc: 23 24 d1 0e sw a3, 232(sp) +800046d0: 93 88 88 00 addi a7, a7, 8 +800046d4: e3 de de fc bge t4, a3, -36 +800046d8: 13 06 41 0e addi a2, sp, 228 +800046dc: 93 05 0b 00 mv a1, s6 +800046e0: 13 85 0a 00 mv a0, s5 +800046e4: 23 2e 01 01 sw a6, 28(sp) +800046e8: 23 24 61 00 sw t1, 8(sp) +800046ec: ef 60 50 2b jal 27316 +800046f0: 63 14 05 14 bnez a0, 328 +800046f4: 03 28 c1 01 lw a6, 28(sp) +800046f8: 13 0e 00 01 addi t3, zero, 16 +800046fc: 83 27 c1 0e lw a5, 236(sp) +80004700: 13 08 08 ff addi a6, a6, -16 +80004704: 83 26 81 0e lw a3, 232(sp) +80004708: 03 23 81 00 lw t1, 8(sp) +8000470c: 93 88 0b 00 mv a7, s7 +80004710: 93 0e 70 00 addi t4, zero, 7 +80004714: e3 42 0e fb blt t3, a6, -92 +80004718: b3 87 07 01 add a5, a5, a6 +8000471c: 93 86 16 00 addi a3, a3, 1 +80004720: 23 a0 38 01 sw s3, 0(a7) +80004724: 23 a2 08 01 sw a6, 4(a7) +80004728: 23 26 f1 0e sw a5, 236(sp) +8000472c: 23 24 d1 0e sw a3, 232(sp) +80004730: 13 06 70 00 addi a2, zero, 7 +80004734: 93 88 88 00 addi a7, a7, 8 +80004738: 63 5c d6 a6 bge a2, a3, -3464 +8000473c: 13 06 41 0e addi a2, sp, 228 +80004740: 93 05 0b 00 mv a1, s6 +80004744: 13 85 0a 00 mv a0, s5 +80004748: 23 24 61 00 sw t1, 8(sp) +8000474c: ef 60 50 25 jal 27220 +80004750: 63 14 05 0e bnez a0, 232 +80004754: 03 23 81 00 lw t1, 8(sp) +80004758: 83 27 c1 0e lw a5, 236(sp) +8000475c: 93 88 0b 00 mv a7, s7 +80004760: 33 03 93 41 sub t1, t1, s9 +80004764: 63 5a 60 a4 blez t1, -3500 +80004768: 13 06 00 01 addi a2, zero, 16 +8000476c: 83 26 81 0e lw a3, 232(sp) +80004770: 63 58 66 06 bge a2, t1, 112 +80004774: 13 08 00 01 addi a6, zero, 16 +80004778: 13 0e 70 00 addi t3, zero, 7 +8000477c: 6f 00 c0 00 j 12 +80004780: 13 03 03 ff addi t1, t1, -16 +80004784: 63 5e 68 04 bge a6, t1, 92 +80004788: 93 87 07 01 addi a5, a5, 16 +8000478c: 93 86 16 00 addi a3, a3, 1 +80004790: 23 a0 38 01 sw s3, 0(a7) +80004794: 23 a2 08 01 sw a6, 4(a7) +80004798: 23 26 f1 0e sw a5, 236(sp) +8000479c: 23 24 d1 0e sw a3, 232(sp) +800047a0: 93 88 88 00 addi a7, a7, 8 +800047a4: e3 5e de fc bge t3, a3, -36 +800047a8: 13 06 41 0e addi a2, sp, 228 +800047ac: 93 05 0b 00 mv a1, s6 +800047b0: 13 85 0a 00 mv a0, s5 +800047b4: 23 24 61 00 sw t1, 8(sp) +800047b8: ef 60 90 1e jal 27112 +800047bc: 63 1e 05 06 bnez a0, 124 +800047c0: 03 23 81 00 lw t1, 8(sp) +800047c4: 13 08 00 01 addi a6, zero, 16 +800047c8: 83 27 c1 0e lw a5, 236(sp) +800047cc: 13 03 03 ff addi t1, t1, -16 +800047d0: 83 26 81 0e lw a3, 232(sp) +800047d4: 93 88 0b 00 mv a7, s7 +800047d8: 13 0e 70 00 addi t3, zero, 7 +800047dc: e3 46 68 fa blt a6, t1, -84 +800047e0: b3 87 67 00 add a5, a5, t1 +800047e4: 93 86 16 00 addi a3, a3, 1 +800047e8: 23 a0 38 01 sw s3, 0(a7) +800047ec: 23 a2 68 00 sw t1, 4(a7) +800047f0: 23 26 f1 0e sw a5, 236(sp) +800047f4: 23 24 d1 0e sw a3, 232(sp) +800047f8: 13 06 70 00 addi a2, zero, 7 +800047fc: 93 88 88 00 addi a7, a7, 8 +80004800: 63 5c d6 9a bge a2, a3, -3656 +80004804: 13 06 41 0e addi a2, sp, 228 +80004808: 93 05 0b 00 mv a1, s6 +8000480c: 13 85 0a 00 mv a0, s5 +80004810: ef 60 10 19 jal 27024 +80004814: 63 12 05 02 bnez a0, 36 +80004818: 83 27 c1 0e lw a5, 236(sp) +8000481c: 93 88 0b 00 mv a7, s7 +80004820: 6f f0 8f 99 j -3688 +80004824: 13 06 41 0e addi a2, sp, 228 +80004828: 93 05 0b 00 mv a1, s6 +8000482c: 13 85 0a 00 mv a0, s5 +80004830: ef 60 10 17 jal 26992 +80004834: 63 0e 05 9c beqz a0, -3620 +80004838: 63 84 0d a0 beqz s11, -3576 +8000483c: 93 85 0d 00 mv a1, s11 +80004840: 13 85 0a 00 mv a0, s5 +80004844: ef 10 90 4c jal 7368 +80004848: 6f f0 8f 9f j -3592 +8000484c: 13 0c 09 00 mv s8, s2 +80004850: 6f f0 5f 9d j -1580 +80004854: 37 57 01 80 lui a4, 524309 +80004858: 13 06 00 01 addi a2, zero, 16 +8000485c: 83 26 81 0e lw a3, 232(sp) +80004860: 93 0e 87 74 addi t4, a4, 1864 +80004864: 13 0e 00 01 addi t3, zero, 16 +80004868: 93 02 70 00 addi t0, zero, 7 +8000486c: 63 48 06 01 blt a2, a6, 16 +80004870: 6f 00 40 08 j 132 +80004874: 13 08 08 ff addi a6, a6, -16 +80004878: 63 5e 0e 07 bge t3, a6, 124 +8000487c: 93 87 07 01 addi a5, a5, 16 +80004880: 93 86 16 00 addi a3, a3, 1 +80004884: 23 a0 d8 01 sw t4, 0(a7) +80004888: 23 a2 c8 01 sw t3, 4(a7) +8000488c: 23 26 f1 0e sw a5, 236(sp) +80004890: 23 24 d1 0e sw a3, 232(sp) +80004894: 93 88 88 00 addi a7, a7, 8 +80004898: e3 de d2 fc bge t0, a3, -36 +8000489c: 13 06 41 0e addi a2, sp, 228 +800048a0: 93 05 0b 00 mv a1, s6 +800048a4: 13 85 0a 00 mv a0, s5 +800048a8: 23 24 d1 03 sw t4, 40(sp) +800048ac: 23 22 01 03 sw a6, 36(sp) +800048b0: 23 20 61 02 sw t1, 32(sp) +800048b4: 23 2e e1 01 sw t5, 28(sp) +800048b8: 23 24 f1 01 sw t6, 8(sp) +800048bc: ef 60 50 0e jal 26852 +800048c0: e3 1c 05 f6 bnez a0, -136 +800048c4: 03 28 41 02 lw a6, 36(sp) +800048c8: 13 0e 00 01 addi t3, zero, 16 +800048cc: 83 27 c1 0e lw a5, 236(sp) +800048d0: 13 08 08 ff addi a6, a6, -16 +800048d4: 83 26 81 0e lw a3, 232(sp) +800048d8: 83 2e 81 02 lw t4, 40(sp) +800048dc: 03 23 01 02 lw t1, 32(sp) +800048e0: 03 2f c1 01 lw t5, 28(sp) +800048e4: 83 2f 81 00 lw t6, 8(sp) +800048e8: 93 88 0b 00 mv a7, s7 +800048ec: 93 02 70 00 addi t0, zero, 7 +800048f0: e3 46 0e f9 blt t3, a6, -116 +800048f4: b3 87 07 01 add a5, a5, a6 +800048f8: 93 86 16 00 addi a3, a3, 1 +800048fc: 23 a0 d8 01 sw t4, 0(a7) +80004900: 23 a2 08 01 sw a6, 4(a7) +80004904: 23 26 f1 0e sw a5, 236(sp) +80004908: 23 24 d1 0e sw a3, 232(sp) +8000490c: 13 06 70 00 addi a2, zero, 7 +80004910: 93 88 88 00 addi a7, a7, 8 +80004914: 63 44 d6 00 blt a2, a3, 8 +80004918: 6f f0 0f 82 j -4064 +8000491c: 13 06 41 0e addi a2, sp, 228 +80004920: 93 05 0b 00 mv a1, s6 +80004924: 13 85 0a 00 mv a0, s5 +80004928: 23 20 61 02 sw t1, 32(sp) +8000492c: 23 2e e1 01 sw t5, 28(sp) +80004930: 23 24 f1 01 sw t6, 8(sp) +80004934: ef 60 d0 06 jal 26732 +80004938: e3 10 05 f0 bnez a0, -256 +8000493c: 83 27 c1 0e lw a5, 236(sp) +80004940: 03 23 01 02 lw t1, 32(sp) +80004944: 03 2f c1 01 lw t5, 28(sp) +80004948: 83 2f 81 00 lw t6, 8(sp) +8000494c: 93 88 0b 00 mv a7, s7 +80004950: 6f e0 9f fe j -4120 +80004954: 13 06 41 0e addi a2, sp, 228 +80004958: 93 05 0b 00 mv a1, s6 +8000495c: 13 85 0a 00 mv a0, s5 +80004960: 23 2e 61 00 sw t1, 28(sp) +80004964: 23 24 e1 01 sw t5, 8(sp) +80004968: ef 60 90 03 jal 26680 +8000496c: e3 16 05 ec bnez a0, -308 +80004970: 83 27 c1 0e lw a5, 236(sp) +80004974: 03 23 c1 01 lw t1, 28(sp) +80004978: 03 2f 81 00 lw t5, 8(sp) +8000497c: 93 88 0b 00 mv a7, s7 +80004980: 6f f0 8f 82 j -4056 +80004984: 83 25 c1 0c lw a1, 204(sp) +80004988: 63 5c b0 78 blez a1, 1944 +8000498c: 03 27 01 03 lw a4, 48(sp) +80004990: 83 26 01 01 lw a3, 16(sp) +80004994: 93 04 07 00 mv s1, a4 +80004998: 63 c6 e6 32 blt a3, a4, 812 +8000499c: 63 56 90 02 blez s1, 44 +800049a0: 83 26 81 0e lw a3, 232(sp) +800049a4: b3 87 97 00 add a5, a5, s1 +800049a8: 23 a0 a8 01 sw s10, 0(a7) +800049ac: 93 86 16 00 addi a3, a3, 1 +800049b0: 23 a2 98 00 sw s1, 4(a7) +800049b4: 23 26 f1 0e sw a5, 236(sp) +800049b8: 23 24 d1 0e sw a3, 232(sp) +800049bc: 13 06 70 00 addi a2, zero, 7 +800049c0: 93 88 88 00 addi a7, a7, 8 +800049c4: e3 40 d6 36 blt a2, a3, 2912 +800049c8: 93 c6 f4 ff not a3, s1 +800049cc: 03 27 01 03 lw a4, 48(sp) +800049d0: 93 d6 f6 41 srai a3, a3, 31 +800049d4: b3 f4 d4 00 and s1, s1, a3 +800049d8: b3 04 97 40 sub s1, a4, s1 +800049dc: 63 48 90 3e bgtz s1, 1008 +800049e0: 03 27 01 03 lw a4, 48(sp) +800049e4: 93 76 09 40 andi a3, s2, 1024 +800049e8: b3 04 ed 00 add s1, s10, a4 +800049ec: 63 94 06 44 bnez a3, 1096 +800049f0: 83 25 c1 0c lw a1, 204(sp) +800049f4: 03 27 01 01 lw a4, 16(sp) +800049f8: 63 c6 e5 00 blt a1, a4, 12 +800049fc: 93 76 19 00 andi a3, s2, 1 +80004a00: e3 86 06 34 beqz a3, 2892 +80004a04: 83 26 01 04 lw a3, 64(sp) +80004a08: 03 27 c1 03 lw a4, 60(sp) +80004a0c: 13 06 70 00 addi a2, zero, 7 +80004a10: 23 a0 d8 00 sw a3, 0(a7) +80004a14: 83 26 81 0e lw a3, 232(sp) +80004a18: b3 87 e7 00 add a5, a5, a4 +80004a1c: 23 a2 e8 00 sw a4, 4(a7) +80004a20: 93 86 16 00 addi a3, a3, 1 +80004a24: 23 26 f1 0e sw a5, 236(sp) +80004a28: 23 24 d1 0e sw a3, 232(sp) +80004a2c: 93 88 88 00 addi a7, a7, 8 +80004a30: e3 4c d6 4c blt a2, a3, 3288 +80004a34: 83 26 01 01 lw a3, 16(sp) +80004a38: 33 07 dd 00 add a4, s10, a3 +80004a3c: 33 86 b6 40 sub a2, a3, a1 +80004a40: 33 07 97 40 sub a4, a4, s1 +80004a44: 93 0c 06 00 mv s9, a2 +80004a48: 63 54 c7 00 bge a4, a2, 8 +80004a4c: 93 0c 07 00 mv s9, a4 +80004a50: 63 56 90 03 blez s9, 44 +80004a54: 03 27 81 0e lw a4, 232(sp) +80004a58: b3 87 97 01 add a5, a5, s9 +80004a5c: 23 a0 98 00 sw s1, 0(a7) +80004a60: 13 07 17 00 addi a4, a4, 1 +80004a64: 23 a2 98 01 sw s9, 4(a7) +80004a68: 23 26 f1 0e sw a5, 236(sp) +80004a6c: 23 24 e1 0e sw a4, 232(sp) +80004a70: 93 06 70 00 addi a3, zero, 7 +80004a74: 93 88 88 00 addi a7, a7, 8 +80004a78: e3 cc e6 5e blt a3, a4, 3576 +80004a7c: 13 c7 fc ff not a4, s9 +80004a80: 13 57 f7 41 srai a4, a4, 31 +80004a84: 33 f7 ec 00 and a4, s9, a4 +80004a88: b3 04 e6 40 sub s1, a2, a4 +80004a8c: 63 44 90 00 bgtz s1, 8 +80004a90: 6f e0 9f f5 j -4264 +80004a94: 93 06 00 01 addi a3, zero, 16 +80004a98: 03 27 81 0e lw a4, 232(sp) +80004a9c: 63 d6 96 78 bge a3, s1, 1932 +80004aa0: 93 0c 00 01 addi s9, zero, 16 +80004aa4: 13 0d 70 00 addi s10, zero, 7 +80004aa8: 6f 00 c0 00 j 12 +80004aac: 93 84 04 ff addi s1, s1, -16 +80004ab0: 63 dc 9c 76 bge s9, s1, 1912 +80004ab4: 93 87 07 01 addi a5, a5, 16 +80004ab8: 13 07 17 00 addi a4, a4, 1 +80004abc: 23 a0 38 01 sw s3, 0(a7) +80004ac0: 23 a2 98 01 sw s9, 4(a7) +80004ac4: 23 26 f1 0e sw a5, 236(sp) +80004ac8: 23 24 e1 0e sw a4, 232(sp) +80004acc: 93 88 88 00 addi a7, a7, 8 +80004ad0: e3 5e ed fc bge s10, a4, -36 +80004ad4: 13 06 41 0e addi a2, sp, 228 +80004ad8: 93 05 0b 00 mv a1, s6 +80004adc: 13 85 0a 00 mv a0, s5 +80004ae0: ef 60 00 6c jal 26304 +80004ae4: e3 1a 05 d4 bnez a0, -684 +80004ae8: 83 27 c1 0e lw a5, 236(sp) +80004aec: 03 27 81 0e lw a4, 232(sp) +80004af0: 93 88 0b 00 mv a7, s7 +80004af4: 6f f0 9f fb j -72 +80004af8: 93 75 19 00 andi a1, s2, 1 +80004afc: 63 94 05 cc bnez a1, -2872 +80004b00: 23 a2 d8 00 sw a3, 4(a7) +80004b04: 23 26 f1 0e sw a5, 236(sp) +80004b08: 23 24 91 0e sw s1, 232(sp) +80004b0c: 13 07 70 00 addi a4, zero, 7 +80004b10: 63 46 97 4e blt a4, s1, 1260 +80004b14: 13 06 26 00 addi a2, a2, 2 +80004b18: 93 88 08 01 addi a7, a7, 16 +80004b1c: 6f f0 0f d8 j -2688 +80004b20: 63 5e d0 d6 blez a3, -2692 +80004b24: 13 07 00 01 addi a4, zero, 16 +80004b28: 63 44 d7 00 blt a4, a3, 8 +80004b2c: 6f 10 00 68 j 5760 +80004b30: 13 0d 70 00 addi s10, zero, 7 +80004b34: 6f 00 00 01 j 16 +80004b38: 93 86 06 ff addi a3, a3, -16 +80004b3c: e3 50 d7 0c bge a4, a3, 2240 +80004b40: 13 88 14 00 addi a6, s1, 1 +80004b44: 93 87 07 01 addi a5, a5, 16 +80004b48: 23 a0 3c 01 sw s3, 0(s9) +80004b4c: 23 a2 ec 00 sw a4, 4(s9) +80004b50: 23 26 f1 0e sw a5, 236(sp) +80004b54: 23 24 01 0f sw a6, 232(sp) +80004b58: 93 04 08 00 mv s1, a6 +80004b5c: 93 8c 8c 00 addi s9, s9, 8 +80004b60: e3 5c 0d fd bge s10, a6, -40 +80004b64: 13 06 41 0e addi a2, sp, 228 +80004b68: 93 05 0b 00 mv a1, s6 +80004b6c: 13 85 0a 00 mv a0, s5 +80004b70: 23 24 d1 00 sw a3, 8(sp) +80004b74: ef 60 c0 62 jal 26156 +80004b78: e3 10 05 cc bnez a0, -832 +80004b7c: 83 27 c1 0e lw a5, 236(sp) +80004b80: 83 24 81 0e lw s1, 232(sp) +80004b84: 83 26 81 00 lw a3, 8(sp) +80004b88: 93 8c 0b 00 mv s9, s7 +80004b8c: 13 07 00 01 addi a4, zero, 16 +80004b90: 6f f0 9f fa j -88 +80004b94: 83 26 c1 00 lw a3, 12(sp) +80004b98: 93 77 0c 01 andi a5, s8, 16 +80004b9c: 13 87 46 00 addi a4, a3, 4 +80004ba0: 63 9c 07 0a bnez a5, 184 +80004ba4: 93 77 0c 04 andi a5, s8, 64 +80004ba8: e3 84 07 08 beqz a5, 2184 +80004bac: 83 27 c1 00 lw a5, 12(sp) +80004bb0: 93 0c 00 00 mv s9, zero +80004bb4: 23 26 e1 00 sw a4, 12(sp) +80004bb8: 83 dd 07 00 lhu s11, 0(a5) +80004bbc: 13 07 10 00 addi a4, zero, 1 +80004bc0: 6f e0 9f fe j -4120 +80004bc4: 13 06 41 0e addi a2, sp, 228 +80004bc8: 93 05 0b 00 mv a1, s6 +80004bcc: 13 85 0a 00 mv a0, s5 +80004bd0: ef 60 00 5d jal 26064 +80004bd4: e3 12 05 c6 bnez a0, -924 +80004bd8: 83 27 c1 0e lw a5, 236(sp) +80004bdc: 83 24 81 0e lw s1, 232(sp) +80004be0: 93 8c 0b 00 mv s9, s7 +80004be4: 6f f0 8f bf j -3080 +80004be8: 13 06 41 0e addi a2, sp, 228 +80004bec: 93 05 0b 00 mv a1, s6 +80004bf0: 13 85 0a 00 mv a0, s5 +80004bf4: ef 60 c0 5a jal 26028 +80004bf8: e3 10 05 c4 bnez a0, -960 +80004bfc: 83 27 c1 0e lw a5, 236(sp) +80004c00: 83 24 81 0e lw s1, 232(sp) +80004c04: 93 8c 0b 00 mv s9, s7 +80004c08: 6f f0 0f c0 j -3072 +80004c0c: 13 77 19 00 andi a4, s2, 1 +80004c10: 63 14 07 00 bnez a4, 8 +80004c14: 6f e0 5f dd j -4652 +80004c18: 6f f0 9f 9d j -1576 +80004c1c: 83 26 41 00 lw a3, 4(sp) +80004c20: 13 0d 04 00 mv s10, s0 +80004c24: 93 d7 f6 41 srai a5, a3, 31 +80004c28: 23 20 d7 00 sw a3, 0(a4) +80004c2c: 23 22 f7 00 sw a5, 4(a4) +80004c30: 6f e0 df df j -4612 +80004c34: 83 27 81 03 lw a5, 56(sp) +80004c38: 83 44 04 00 lbu s1, 0(s0) +80004c3c: 63 94 07 00 bnez a5, 8 +80004c40: 6f e0 df c5 j -5028 +80004c44: 83 c7 07 00 lbu a5, 0(a5) +80004c48: 63 94 07 00 bnez a5, 8 +80004c4c: 6f e0 1f c5 j -5040 +80004c50: 13 69 09 40 ori s2, s2, 1024 +80004c54: 6f e0 9f c4 j -5048 +80004c58: 23 26 e1 00 sw a4, 12(sp) +80004c5c: 83 ad 06 00 lw s11, 0(a3) +80004c60: 93 0c 00 00 mv s9, zero +80004c64: 13 07 10 00 addi a4, zero, 1 +80004c68: 6f e0 1f f4 j -4288 +80004c6c: 83 ad 06 00 lw s11, 0(a3) +80004c70: 23 26 e1 00 sw a4, 12(sp) +80004c74: 93 dc fd 41 srai s9, s11, 31 +80004c78: 13 87 0c 00 mv a4, s9 +80004c7c: 6f e0 1f ea j -4448 +80004c80: 83 ad 06 00 lw s11, 0(a3) +80004c84: 93 0c 00 00 mv s9, zero +80004c88: 23 26 e1 00 sw a4, 12(sp) +80004c8c: 6f e0 5f f1 j -4332 +80004c90: 03 27 c1 00 lw a4, 12(sp) +80004c94: 83 27 07 00 lw a5, 0(a4) +80004c98: 13 07 47 00 addi a4, a4, 4 +80004c9c: 23 26 e1 00 sw a4, 12(sp) +80004ca0: 83 a5 07 00 lw a1, 0(a5) +80004ca4: 03 a6 47 00 lw a2, 4(a5) +80004ca8: 83 a6 87 00 lw a3, 8(a5) +80004cac: 83 a7 c7 00 lw a5, 12(a5) +80004cb0: 23 28 b1 0e sw a1, 240(sp) +80004cb4: 23 2a c1 0e sw a2, 244(sp) +80004cb8: 23 2c d1 0e sw a3, 248(sp) +80004cbc: 23 2e f1 0e sw a5, 252(sp) +80004cc0: 6f e0 1f fb j -4176 +80004cc4: 93 84 06 00 mv s1, a3 +80004cc8: e3 4c 90 cc bgtz s1, -808 +80004ccc: 6f f0 df cf j -772 +80004cd0: 13 0c 09 00 mv s8, s2 +80004cd4: 6f f0 8f f4 j -2232 +80004cd8: b7 57 01 80 lui a5, 524309 +80004cdc: 93 87 87 5a addi a5, a5, 1448 +80004ce0: 23 2c f1 00 sw a5, 24(sp) +80004ce4: 93 77 09 02 andi a5, s2, 32 +80004ce8: 63 86 07 2c beqz a5, 716 +80004cec: 83 27 c1 00 lw a5, 12(sp) +80004cf0: 13 87 77 00 addi a4, a5, 7 +80004cf4: 13 77 87 ff andi a4, a4, -8 +80004cf8: 83 2d 07 00 lw s11, 0(a4) +80004cfc: 83 2c 47 00 lw s9, 4(a4) +80004d00: 93 07 87 00 addi a5, a4, 8 +80004d04: 23 26 f1 00 sw a5, 12(sp) +80004d08: 13 77 19 00 andi a4, s2, 1 +80004d0c: 63 0e 07 00 beqz a4, 28 +80004d10: 33 e7 9d 01 or a4, s11, s9 +80004d14: 63 0a 07 00 beqz a4, 20 +80004d18: 13 07 00 03 addi a4, zero, 48 +80004d1c: 23 04 e1 0c sb a4, 200(sp) +80004d20: a3 04 91 0c sb s1, 201(sp) +80004d24: 13 69 29 00 ori s2, s2, 2 +80004d28: 13 7c f9 bf andi s8, s2, -1025 +80004d2c: 13 07 20 00 addi a4, zero, 2 +80004d30: 6f e0 9f e7 j -4488 +80004d34: 83 44 14 00 lbu s1, 1(s0) +80004d38: 13 69 09 20 ori s2, s2, 512 +80004d3c: 13 04 14 00 addi s0, s0, 1 +80004d40: 6f e0 df b5 j -5284 +80004d44: 13 06 41 0e addi a2, sp, 228 +80004d48: 93 05 0b 00 mv a1, s6 +80004d4c: 13 85 0a 00 mv a0, s5 +80004d50: ef 60 00 45 jal 25680 +80004d54: e3 12 05 ae bnez a0, -1308 +80004d58: 83 27 c1 0e lw a5, 236(sp) +80004d5c: 93 88 0b 00 mv a7, s7 +80004d60: 6f f0 1f 8c j -1856 +80004d64: 83 44 14 00 lbu s1, 1(s0) +80004d68: 13 69 09 02 ori s2, s2, 32 +80004d6c: 13 04 14 00 addi s0, s0, 1 +80004d70: 6f e0 df b2 j -5332 +80004d74: b7 57 01 80 lui a5, 524309 +80004d78: 93 87 c7 5b addi a5, a5, 1468 +80004d7c: 23 2c f1 00 sw a5, 24(sp) +80004d80: 6f f0 5f f6 j -156 +80004d84: 93 05 00 04 addi a1, zero, 64 +80004d88: 13 85 0a 00 mv a0, s5 +80004d8c: ef 40 40 65 jal 18004 +80004d90: 23 20 ab 00 sw a0, 0(s6) +80004d94: 23 28 ab 00 sw a0, 16(s6) +80004d98: 63 14 05 00 bnez a0, 8 +80004d9c: 6f 10 c0 43 j 5180 +80004da0: 93 07 00 04 addi a5, zero, 64 +80004da4: 23 2a fb 00 sw a5, 20(s6) +80004da8: 6f e0 5f a2 j -5596 +80004dac: 93 07 60 00 addi a5, zero, 6 +80004db0: 93 0c 03 00 mv s9, t1 +80004db4: 63 e8 67 78 bltu a5, t1, 1936 +80004db8: 37 57 01 80 lui a4, 524309 +80004dbc: 13 8c 0c 00 mv s8, s9 +80004dc0: 23 26 d1 00 sw a3, 12(sp) +80004dc4: 13 0d 07 5d addi s10, a4, 1488 +80004dc8: 6f e0 df b3 j -5316 +80004dcc: 13 06 00 01 addi a2, zero, 16 +80004dd0: 83 26 81 0e lw a3, 232(sp) +80004dd4: 63 5a 96 6e bge a2, s1, 1780 +80004dd8: 93 0c 00 01 addi s9, zero, 16 +80004ddc: 13 08 70 00 addi a6, zero, 7 +80004de0: 6f 00 c0 00 j 12 +80004de4: 93 84 04 ff addi s1, s1, -16 +80004de8: 63 d0 9c 6e bge s9, s1, 1760 +80004dec: 93 87 07 01 addi a5, a5, 16 +80004df0: 93 86 16 00 addi a3, a3, 1 +80004df4: 23 a0 38 01 sw s3, 0(a7) +80004df8: 23 a2 98 01 sw s9, 4(a7) +80004dfc: 23 26 f1 0e sw a5, 236(sp) +80004e00: 23 24 d1 0e sw a3, 232(sp) +80004e04: 93 88 88 00 addi a7, a7, 8 +80004e08: e3 5e d8 fc bge a6, a3, -36 +80004e0c: 13 06 41 0e addi a2, sp, 228 +80004e10: 93 05 0b 00 mv a1, s6 +80004e14: 13 85 0a 00 mv a0, s5 +80004e18: ef 60 80 38 jal 25480 +80004e1c: e3 1e 05 a0 bnez a0, -1508 +80004e20: 83 27 c1 0e lw a5, 236(sp) +80004e24: 83 26 81 0e lw a3, 232(sp) +80004e28: 93 88 0b 00 mv a7, s7 +80004e2c: 13 08 70 00 addi a6, zero, 7 +80004e30: 6f f0 5f fb j -76 +80004e34: 03 27 01 01 lw a4, 16(sp) +80004e38: 13 0e 70 00 addi t3, zero, 7 +80004e3c: 13 08 00 01 addi a6, zero, 16 +80004e40: 33 07 ed 00 add a4, s10, a4 +80004e44: 23 24 e1 00 sw a4, 8(sp) +80004e48: 03 27 41 03 lw a4, 52(sp) +80004e4c: 63 0e 07 0a beqz a4, 188 +80004e50: 03 27 c1 02 lw a4, 44(sp) +80004e54: 63 1e 07 0a bnez a4, 188 +80004e58: 03 27 81 03 lw a4, 56(sp) +80004e5c: 13 07 f7 ff addi a4, a4, -1 +80004e60: 23 2c e1 02 sw a4, 56(sp) +80004e64: 03 27 41 03 lw a4, 52(sp) +80004e68: 13 07 f7 ff addi a4, a4, -1 +80004e6c: 23 2a e1 02 sw a4, 52(sp) +80004e70: 83 26 c1 04 lw a3, 76(sp) +80004e74: 03 27 81 04 lw a4, 72(sp) +80004e78: 93 88 88 00 addi a7, a7, 8 +80004e7c: 23 ac d8 fe sw a3, -8(a7) +80004e80: 83 26 81 0e lw a3, 232(sp) +80004e84: b3 87 e7 00 add a5, a5, a4 +80004e88: 23 ae e8 fe sw a4, -4(a7) +80004e8c: 93 86 16 00 addi a3, a3, 1 +80004e90: 23 26 f1 0e sw a5, 236(sp) +80004e94: 23 24 d1 0e sw a3, 232(sp) +80004e98: 63 4e de 12 blt t3, a3, 316 +80004e9c: 03 27 81 03 lw a4, 56(sp) +80004ea0: 83 46 07 00 lbu a3, 0(a4) +80004ea4: 03 27 81 00 lw a4, 8(sp) +80004ea8: 93 8c 06 00 mv s9, a3 +80004eac: 33 06 97 40 sub a2, a4, s1 +80004eb0: 63 54 d6 00 bge a2, a3, 8 +80004eb4: 93 0c 06 00 mv s9, a2 +80004eb8: 63 58 90 03 blez s9, 48 +80004ebc: 83 26 81 0e lw a3, 232(sp) +80004ec0: b3 87 97 01 add a5, a5, s9 +80004ec4: 23 a0 98 00 sw s1, 0(a7) +80004ec8: 93 86 16 00 addi a3, a3, 1 +80004ecc: 23 a2 98 01 sw s9, 4(a7) +80004ed0: 23 26 f1 0e sw a5, 236(sp) +80004ed4: 23 24 d1 0e sw a3, 232(sp) +80004ed8: 63 4c de 36 blt t3, a3, 888 +80004edc: 03 27 81 03 lw a4, 56(sp) +80004ee0: 93 88 88 00 addi a7, a7, 8 +80004ee4: 83 46 07 00 lbu a3, 0(a4) +80004ee8: 13 c6 fc ff not a2, s9 +80004eec: 13 56 f6 41 srai a2, a2, 31 +80004ef0: b3 fc cc 00 and s9, s9, a2 +80004ef4: b3 8c 96 41 sub s9, a3, s9 +80004ef8: 63 44 90 03 bgtz s9, 40 +80004efc: b3 84 d4 00 add s1, s1, a3 +80004f00: 03 27 41 03 lw a4, 52(sp) +80004f04: e3 16 07 f4 bnez a4, -180 +80004f08: 03 27 c1 02 lw a4, 44(sp) +80004f0c: 63 00 07 72 beqz a4, 1824 +80004f10: 03 27 c1 02 lw a4, 44(sp) +80004f14: 13 07 f7 ff addi a4, a4, -1 +80004f18: 23 26 e1 02 sw a4, 44(sp) +80004f1c: 6f f0 5f f5 j -172 +80004f20: 83 26 81 0e lw a3, 232(sp) +80004f24: 63 48 98 01 blt a6, s9, 16 +80004f28: 6f 00 c0 05 j 92 +80004f2c: 93 8c 0c ff addi s9, s9, -16 +80004f30: 63 5a 98 05 bge a6, s9, 84 +80004f34: 93 87 07 01 addi a5, a5, 16 +80004f38: 93 86 16 00 addi a3, a3, 1 +80004f3c: 23 a0 38 01 sw s3, 0(a7) +80004f40: 23 a2 08 01 sw a6, 4(a7) +80004f44: 23 26 f1 0e sw a5, 236(sp) +80004f48: 23 24 d1 0e sw a3, 232(sp) +80004f4c: 93 88 88 00 addi a7, a7, 8 +80004f50: e3 5e de fc bge t3, a3, -36 +80004f54: 13 06 41 0e addi a2, sp, 228 +80004f58: 93 05 0b 00 mv a1, s6 +80004f5c: 13 85 0a 00 mv a0, s5 +80004f60: ef 60 00 24 jal 25152 +80004f64: e3 1a 05 8c bnez a0, -1836 +80004f68: 13 08 00 01 addi a6, zero, 16 +80004f6c: 93 8c 0c ff addi s9, s9, -16 +80004f70: 83 27 c1 0e lw a5, 236(sp) +80004f74: 83 26 81 0e lw a3, 232(sp) +80004f78: 93 88 0b 00 mv a7, s7 +80004f7c: 13 0e 70 00 addi t3, zero, 7 +80004f80: e3 4a 98 fb blt a6, s9, -76 +80004f84: b3 87 97 01 add a5, a5, s9 +80004f88: 93 86 16 00 addi a3, a3, 1 +80004f8c: 23 a0 38 01 sw s3, 0(a7) +80004f90: 23 a2 98 01 sw s9, 4(a7) +80004f94: 23 26 f1 0e sw a5, 236(sp) +80004f98: 23 24 d1 0e sw a3, 232(sp) +80004f9c: 63 46 de 72 blt t3, a3, 1836 +80004fa0: 03 27 81 03 lw a4, 56(sp) +80004fa4: 93 88 88 00 addi a7, a7, 8 +80004fa8: 83 46 07 00 lbu a3, 0(a4) +80004fac: b3 84 d4 00 add s1, s1, a3 +80004fb0: 6f f0 1f f5 j -176 +80004fb4: 83 26 c1 00 lw a3, 12(sp) +80004fb8: 93 77 09 01 andi a5, s2, 16 +80004fbc: 13 87 46 00 addi a4, a3, 4 +80004fc0: 63 86 07 22 beqz a5, 556 +80004fc4: 83 ad 06 00 lw s11, 0(a3) +80004fc8: 93 0c 00 00 mv s9, zero +80004fcc: 23 26 e1 00 sw a4, 12(sp) +80004fd0: 6f f0 9f d3 j -712 +80004fd4: 13 06 41 0e addi a2, sp, 228 +80004fd8: 93 05 0b 00 mv a1, s6 +80004fdc: 13 85 0a 00 mv a0, s5 +80004fe0: ef 60 00 1c jal 25024 +80004fe4: e3 1a 05 84 bnez a0, -1964 +80004fe8: 83 27 c1 0e lw a5, 236(sp) +80004fec: 93 88 0b 00 mv a7, s7 +80004ff0: 13 08 00 01 addi a6, zero, 16 +80004ff4: 13 0e 70 00 addi t3, zero, 7 +80004ff8: 6f f0 5f ea j -348 +80004ffc: 13 06 41 0e addi a2, sp, 228 +80005000: 93 05 0b 00 mv a1, s6 +80005004: 13 85 0a 00 mv a0, s5 +80005008: ef 60 80 19 jal 24984 +8000500c: e3 16 05 82 bnez a0, -2004 +80005010: 03 26 81 0e lw a2, 232(sp) +80005014: 83 27 c1 0e lw a5, 236(sp) +80005018: 93 08 41 11 addi a7, sp, 276 +8000501c: 13 06 16 00 addi a2, a2, 1 +80005020: 93 8c 0b 00 mv s9, s7 +80005024: 6f f0 8f 87 j -3976 +80005028: 13 79 0c 40 andi s2, s8, 1024 +8000502c: 23 28 01 00 sw zero, 16(sp) +80005030: 13 0d 01 1b addi s10, sp, 432 +80005034: 6f 00 40 03 j 52 +80005038: 13 06 a0 00 addi a2, zero, 10 +8000503c: 93 06 00 00 mv a3, zero +80005040: 13 85 0d 00 mv a0, s11 +80005044: 93 85 0c 00 mv a1, s9 +80005048: 23 2e 11 01 sw a7, 28(sp) +8000504c: 23 24 61 00 sw t1, 8(sp) +80005050: ef a0 d0 75 jal 44892 +80005054: 03 23 81 00 lw t1, 8(sp) +80005058: 83 28 c1 01 lw a7, 28(sp) +8000505c: 63 88 0c 4a beqz s9, 1200 +80005060: 93 0d 05 00 mv s11, a0 +80005064: 93 8c 05 00 mv s9, a1 +80005068: 13 06 a0 00 addi a2, zero, 10 +8000506c: 93 06 00 00 mv a3, zero +80005070: 13 85 0d 00 mv a0, s11 +80005074: 93 85 0c 00 mv a1, s9 +80005078: 23 2e 11 01 sw a7, 28(sp) +8000507c: 23 24 61 00 sw t1, 8(sp) +80005080: ef b0 00 36 jal 45920 +80005084: 83 27 01 01 lw a5, 16(sp) +80005088: 13 05 05 03 addi a0, a0, 48 +8000508c: a3 0f ad fe sb a0, -1(s10) +80005090: 93 87 17 00 addi a5, a5, 1 +80005094: 23 28 f1 00 sw a5, 16(sp) +80005098: 03 23 81 00 lw t1, 8(sp) +8000509c: 83 28 c1 01 lw a7, 28(sp) +800050a0: 13 0d fd ff addi s10, s10, -1 +800050a4: e3 0a 09 f8 beqz s2, -108 +800050a8: 03 27 81 03 lw a4, 56(sp) +800050ac: 83 46 07 00 lbu a3, 0(a4) +800050b0: e3 94 d7 f8 bne a5, a3, -120 +800050b4: 13 07 f0 0f addi a4, zero, 255 +800050b8: e3 80 e7 f8 beq a5, a4, -128 +800050bc: 63 96 0c 00 bnez s9, 12 +800050c0: 93 07 90 00 addi a5, zero, 9 +800050c4: 63 f2 b7 c9 bgeu a5, s11, -2940 +800050c8: 83 27 81 04 lw a5, 72(sp) +800050cc: 83 25 c1 04 lw a1, 76(sp) +800050d0: 23 2e 11 01 sw a7, 28(sp) +800050d4: 33 0d fd 40 sub s10, s10, a5 +800050d8: 13 86 07 00 mv a2, a5 +800050dc: 13 05 0d 00 mv a0, s10 +800050e0: 23 24 61 00 sw t1, 8(sp) +800050e4: ef 60 40 01 jal 24596 +800050e8: 83 27 81 03 lw a5, 56(sp) +800050ec: 13 06 a0 00 addi a2, zero, 10 +800050f0: 93 06 00 00 mv a3, zero +800050f4: 03 ce 17 00 lbu t3, 1(a5) +800050f8: 13 85 0d 00 mv a0, s11 +800050fc: 93 85 0c 00 mv a1, s9 +80005100: 33 3e c0 01 snez t3, t3 +80005104: b3 87 c7 01 add a5, a5, t3 +80005108: 23 2c f1 02 sw a5, 56(sp) +8000510c: ef a0 10 6a jal 44704 +80005110: 03 23 81 00 lw t1, 8(sp) +80005114: 83 28 c1 01 lw a7, 28(sp) +80005118: 23 28 01 00 sw zero, 16(sp) +8000511c: 6f f0 5f f4 j -188 +80005120: 83 26 81 0e lw a3, 232(sp) +80005124: 37 56 01 80 lui a2, 524309 +80005128: 13 06 86 5d addi a2, a2, 1496 +8000512c: 23 a0 c8 00 sw a2, 0(a7) +80005130: 93 87 17 00 addi a5, a5, 1 +80005134: 13 06 10 00 addi a2, zero, 1 +80005138: 93 86 16 00 addi a3, a3, 1 +8000513c: 23 a2 c8 00 sw a2, 4(a7) +80005140: 23 26 f1 0e sw a5, 236(sp) +80005144: 23 24 d1 0e sw a3, 232(sp) +80005148: 13 06 70 00 addi a2, zero, 7 +8000514c: 93 88 88 00 addi a7, a7, 8 +80005150: 63 4c d6 06 blt a2, a3, 120 +80005154: 63 92 05 1c bnez a1, 452 +80005158: 03 27 01 01 lw a4, 16(sp) +8000515c: 93 76 19 00 andi a3, s2, 1 +80005160: b3 e6 e6 00 or a3, a3, a4 +80005164: 63 94 06 00 bnez a3, 8 +80005168: 6f e0 1f 88 j -6016 +8000516c: 83 26 01 04 lw a3, 64(sp) +80005170: 03 27 c1 03 lw a4, 60(sp) +80005174: 13 06 70 00 addi a2, zero, 7 +80005178: 23 a0 d8 00 sw a3, 0(a7) +8000517c: 83 26 81 0e lw a3, 232(sp) +80005180: b3 87 e7 00 add a5, a5, a4 +80005184: 23 a2 e8 00 sw a4, 4(a7) +80005188: 93 86 16 00 addi a3, a3, 1 +8000518c: 23 26 f1 0e sw a5, 236(sp) +80005190: 23 24 d1 0e sw a3, 232(sp) +80005194: 63 42 d6 46 blt a2, a3, 1124 +80005198: 93 88 88 00 addi a7, a7, 8 +8000519c: 03 27 01 01 lw a4, 16(sp) +800051a0: 93 86 16 00 addi a3, a3, 1 +800051a4: 23 a0 a8 01 sw s10, 0(a7) +800051a8: b3 87 e7 00 add a5, a5, a4 +800051ac: 23 a2 e8 00 sw a4, 4(a7) +800051b0: 23 26 f1 0e sw a5, 236(sp) +800051b4: 23 24 d1 0e sw a3, 232(sp) +800051b8: 13 07 70 00 addi a4, zero, 7 +800051bc: 63 44 d7 00 blt a4, a3, 8 +800051c0: 6f e0 5f 82 j -6108 +800051c4: 6f e0 df ef j -4356 +800051c8: 13 06 41 0e addi a2, sp, 228 +800051cc: 93 05 0b 00 mv a1, s6 +800051d0: 13 85 0a 00 mv a0, s5 +800051d4: ef 50 d0 7c jal 24524 +800051d8: 63 10 05 e6 bnez a0, -2464 +800051dc: 83 25 c1 0c lw a1, 204(sp) +800051e0: 83 27 c1 0e lw a5, 236(sp) +800051e4: 93 88 0b 00 mv a7, s7 +800051e8: 6f f0 df f6 j -148 +800051ec: 93 77 09 04 andi a5, s2, 64 +800051f0: 63 80 07 28 beqz a5, 640 +800051f4: 83 27 c1 00 lw a5, 12(sp) +800051f8: 93 0c 00 00 mv s9, zero +800051fc: 23 26 e1 00 sw a4, 12(sp) +80005200: 83 dd 07 00 lhu s11, 0(a5) +80005204: 6f f0 5f b0 j -1276 +80005208: 13 06 41 0e addi a2, sp, 228 +8000520c: 93 05 0b 00 mv a1, s6 +80005210: 13 85 0a 00 mv a0, s5 +80005214: ef 50 d0 78 jal 24460 +80005218: 63 10 05 e2 bnez a0, -2528 +8000521c: 83 27 c1 0e lw a5, 236(sp) +80005220: 93 88 0b 00 mv a7, s7 +80005224: 6f f0 0f bc j -3136 +80005228: 23 a0 38 01 sw s3, 0(a7) +8000522c: 23 a2 98 00 sw s1, 4(a7) +80005230: b3 87 97 00 add a5, a5, s1 +80005234: 13 07 17 00 addi a4, a4, 1 +80005238: 23 26 f1 0e sw a5, 236(sp) +8000523c: 23 24 e1 0e sw a4, 232(sp) +80005240: 93 06 70 00 addi a3, zero, 7 +80005244: 63 c4 e6 00 blt a3, a4, 8 +80005248: 6f e0 cf f9 j -6244 +8000524c: 6f e0 5f e7 j -4492 +80005250: 13 06 41 0e addi a2, sp, 228 +80005254: 93 05 0b 00 mv a1, s6 +80005258: 13 85 0a 00 mv a0, s5 +8000525c: ef 50 50 74 jal 24388 +80005260: 63 1c 05 dc bnez a0, -2600 +80005264: 83 27 81 03 lw a5, 56(sp) +80005268: 93 88 0b 00 mv a7, s7 +8000526c: 13 08 00 01 addi a6, zero, 16 +80005270: 83 c6 07 00 lbu a3, 0(a5) +80005274: 13 0e 70 00 addi t3, zero, 7 +80005278: 83 27 c1 0e lw a5, 236(sp) +8000527c: 6f f0 df c6 j -916 +80005280: 83 27 01 0f lw a5, 240(sp) +80005284: 93 05 01 0a addi a1, sp, 160 +80005288: 13 05 01 0b addi a0, sp, 176 +8000528c: 23 28 f1 0a sw a5, 176(sp) +80005290: 83 27 41 0f lw a5, 244(sp) +80005294: 23 24 11 01 sw a7, 8(sp) +80005298: 23 20 01 0a sw zero, 160(sp) +8000529c: 23 2a f1 0a sw a5, 180(sp) +800052a0: 83 27 81 0f lw a5, 248(sp) +800052a4: 23 22 01 0a sw zero, 164(sp) +800052a8: 23 24 01 0a sw zero, 168(sp) +800052ac: 23 2c f1 0a sw a5, 184(sp) +800052b0: 83 27 c1 0f lw a5, 252(sp) +800052b4: 23 26 01 0a sw zero, 172(sp) +800052b8: 23 2e f1 0a sw a5, 188(sp) +800052bc: ef c0 50 01 jal 51220 +800052c0: 83 28 81 00 lw a7, 8(sp) +800052c4: 63 4c 05 42 bltz a0, 1080 +800052c8: 83 47 71 0c lbu a5, 199(sp) +800052cc: 13 07 70 04 addi a4, zero, 71 +800052d0: 63 54 97 24 bge a4, s1, 584 +800052d4: 37 57 01 80 lui a4, 524309 +800052d8: 13 0d c7 59 addi s10, a4, 1436 +800052dc: 23 26 01 02 sw zero, 44(sp) +800052e0: 23 2a 01 02 sw zero, 52(sp) +800052e4: 23 28 01 02 sw zero, 48(sp) +800052e8: 13 79 f9 f7 andi s2, s2, -129 +800052ec: 13 0c 30 00 addi s8, zero, 3 +800052f0: 93 0d 00 00 mv s11, zero +800052f4: 93 0c 30 00 addi s9, zero, 3 +800052f8: 13 03 00 00 mv t1, zero +800052fc: 63 84 07 00 beqz a5, 8 +80005300: 6f e0 1f 87 j -6032 +80005304: 6f e0 4f e1 j -6636 +80005308: 83 27 41 00 lw a5, 4(sp) +8000530c: 13 0d 04 00 mv s10, s0 +80005310: 23 20 f7 00 sw a5, 0(a4) +80005314: 6f e0 8f f1 j -6376 +80005318: 83 26 01 04 lw a3, 64(sp) +8000531c: 03 27 c1 03 lw a4, 60(sp) +80005320: 13 06 70 00 addi a2, zero, 7 +80005324: 23 a0 d8 00 sw a3, 0(a7) +80005328: 83 26 81 0e lw a3, 232(sp) +8000532c: b3 87 e7 00 add a5, a5, a4 +80005330: 23 a2 e8 00 sw a4, 4(a7) +80005334: 93 86 16 00 addi a3, a3, 1 +80005338: 23 26 f1 0e sw a5, 236(sp) +8000533c: 23 24 d1 0e sw a3, 232(sp) +80005340: 93 88 88 00 addi a7, a7, 8 +80005344: 63 4a d6 2a blt a2, a3, 692 +80005348: e3 da 05 e4 bgez a1, -428 +8000534c: 13 06 00 ff addi a2, zero, -16 +80005350: b3 04 b0 40 neg s1, a1 +80005354: e3 d6 c5 28 bge a1, a2, 2700 +80005358: 93 0c 00 01 addi s9, zero, 16 +8000535c: 13 08 70 00 addi a6, zero, 7 +80005360: 6f 00 c0 00 j 12 +80005364: 93 84 04 ff addi s1, s1, -16 +80005368: e3 dc 9c 26 bge s9, s1, 2680 +8000536c: 93 87 07 01 addi a5, a5, 16 +80005370: 93 86 16 00 addi a3, a3, 1 +80005374: 23 a0 38 01 sw s3, 0(a7) +80005378: 23 a2 98 01 sw s9, 4(a7) +8000537c: 23 26 f1 0e sw a5, 236(sp) +80005380: 23 24 d1 0e sw a3, 232(sp) +80005384: 93 88 88 00 addi a7, a7, 8 +80005388: e3 5e d8 fc bge a6, a3, -36 +8000538c: 13 06 41 0e addi a2, sp, 228 +80005390: 93 05 0b 00 mv a1, s6 +80005394: 13 85 0a 00 mv a0, s5 +80005398: ef 50 90 60 jal 24072 +8000539c: 63 1e 05 c8 bnez a0, -2916 +800053a0: 83 27 c1 0e lw a5, 236(sp) +800053a4: 83 26 81 0e lw a3, 232(sp) +800053a8: 93 88 0b 00 mv a7, s7 +800053ac: 13 08 70 00 addi a6, zero, 7 +800053b0: 6f f0 5f fb j -76 +800053b4: 13 05 0d 00 mv a0, s10 +800053b8: 23 24 11 01 sw a7, 8(sp) +800053bc: 23 26 d1 00 sw a3, 12(sp) +800053c0: ef 50 d0 4a jal 23724 +800053c4: 83 47 71 0c lbu a5, 199(sp) +800053c8: 13 4c f5 ff not s8, a0 +800053cc: 13 5c fc 41 srai s8, s8, 31 +800053d0: 23 26 01 02 sw zero, 44(sp) +800053d4: 23 2a 01 02 sw zero, 52(sp) +800053d8: 23 28 01 02 sw zero, 48(sp) +800053dc: 83 28 81 00 lw a7, 8(sp) +800053e0: 93 0c 05 00 mv s9, a0 +800053e4: 33 7c 85 01 and s8, a0, s8 +800053e8: 93 0d 00 00 mv s11, zero +800053ec: 13 03 00 00 mv t1, zero +800053f0: 63 84 07 00 beqz a5, 8 +800053f4: 6f e0 cf f7 j -6276 +800053f8: 6f e0 0f d2 j -6880 +800053fc: 13 86 14 00 addi a2, s1, 1 +80005400: 13 87 8c 00 addi a4, s9, 8 +80005404: b3 87 d7 00 add a5, a5, a3 +80005408: 23 a2 dc 00 sw a3, 4(s9) +8000540c: 23 a0 3c 01 sw s3, 0(s9) +80005410: 23 26 f1 0e sw a5, 236(sp) +80005414: 23 24 c1 0e sw a2, 232(sp) +80005418: 93 06 70 00 addi a3, zero, 7 +8000541c: e3 c0 c6 be blt a3, a2, -1056 +80005420: 13 06 16 00 addi a2, a2, 1 +80005424: 93 08 87 00 addi a7, a4, 8 +80005428: 93 0c 07 00 mv s9, a4 +8000542c: 6f e0 1f c7 j -5008 +80005430: 93 77 0c 20 andi a5, s8, 512 +80005434: 63 84 07 18 beqz a5, 392 +80005438: 83 27 c1 00 lw a5, 12(sp) +8000543c: 93 0c 00 00 mv s9, zero +80005440: 23 26 e1 00 sw a4, 12(sp) +80005444: 83 cd 07 00 lbu s11, 0(a5) +80005448: 13 07 10 00 addi a4, zero, 1 +8000544c: 6f e0 cf f5 j -6308 +80005450: 93 77 09 20 andi a5, s2, 512 +80005454: 63 88 07 14 beqz a5, 336 +80005458: 83 27 c1 00 lw a5, 12(sp) +8000545c: 23 26 e1 00 sw a4, 12(sp) +80005460: 83 8d 07 00 lb s11, 0(a5) +80005464: 93 dc fd 41 srai s9, s11, 31 +80005468: 13 87 0c 00 mv a4, s9 +8000546c: 6f e0 0f eb j -6480 +80005470: 93 77 09 20 andi a5, s2, 512 +80005474: 63 8e 07 10 beqz a5, 284 +80005478: 83 27 c1 00 lw a5, 12(sp) +8000547c: 93 0c 00 00 mv s9, zero +80005480: 23 26 e1 00 sw a4, 12(sp) +80005484: 83 cd 07 00 lbu s11, 0(a5) +80005488: 6f f0 1f 88 j -1920 +8000548c: 93 77 09 20 andi a5, s2, 512 +80005490: 63 86 07 0e beqz a5, 236 +80005494: 83 27 c1 00 lw a5, 12(sp) +80005498: 93 0c 00 00 mv s9, zero +8000549c: 23 26 e1 00 sw a4, 12(sp) +800054a0: 83 cd 07 00 lbu s11, 0(a5) +800054a4: 6f e0 cf ef j -6404 +800054a8: 83 27 c1 0f lw a5, 252(sp) +800054ac: 63 c0 07 14 bltz a5, 320 +800054b0: 83 47 71 0c lbu a5, 199(sp) +800054b4: 13 07 70 04 addi a4, zero, 71 +800054b8: 63 52 97 42 bge a4, s1, 1060 +800054bc: 37 57 01 80 lui a4, 524309 +800054c0: 13 0d 47 5a addi s10, a4, 1444 +800054c4: 6f f0 9f e1 j -488 +800054c8: b3 87 97 00 add a5, a5, s1 +800054cc: 93 86 16 00 addi a3, a3, 1 +800054d0: 23 a0 38 01 sw s3, 0(a7) +800054d4: 23 a2 98 00 sw s1, 4(a7) +800054d8: 23 26 f1 0e sw a5, 236(sp) +800054dc: 23 24 d1 0e sw a3, 232(sp) +800054e0: 13 06 70 00 addi a2, zero, 7 +800054e4: 93 88 88 00 addi a7, a7, 8 +800054e8: 63 5c d6 ce bge a2, a3, -2824 +800054ec: 13 06 41 0e addi a2, sp, 228 +800054f0: 93 05 0b 00 mv a1, s6 +800054f4: 13 85 0a 00 mv a0, s5 +800054f8: ef 50 90 4a jal 23720 +800054fc: 63 1e 05 b2 bnez a0, -3268 +80005500: 83 27 c1 0e lw a5, 236(sp) +80005504: 93 88 0b 00 mv a7, s7 +80005508: 6f f0 8f cd j -2856 +8000550c: 93 07 90 00 addi a5, zero, 9 +80005510: e3 e8 b7 b5 bltu a5, s11, -1200 +80005514: 6f f0 4f 83 j -4044 +80005518: 37 57 01 80 lui a4, 524309 +8000551c: 13 0d 87 59 addi s10, a4, 1432 +80005520: 6f f0 df db j -580 +80005524: 13 06 41 0e addi a2, sp, 228 +80005528: 93 05 0b 00 mv a1, s6 +8000552c: 13 85 0a 00 mv a0, s5 +80005530: ef 50 10 47 jal 23664 +80005534: 63 12 05 b0 bnez a0, -3324 +80005538: 83 27 c1 0e lw a5, 236(sp) +8000553c: 93 88 0b 00 mv a7, s7 +80005540: 6f f0 8f c8 j -2936 +80005544: 93 0c 60 00 addi s9, zero, 6 +80005548: 6f f0 1f 87 j -1936 +8000554c: 83 26 01 01 lw a3, 16(sp) +80005550: 33 07 dd 00 add a4, s10, a3 +80005554: 33 86 b6 40 sub a2, a3, a1 +80005558: 33 03 97 40 sub t1, a4, s1 +8000555c: 93 0c 06 00 mv s9, a2 +80005560: 63 5e c3 d0 bge t1, a2, -2788 +80005564: 93 0c 03 00 mv s9, t1 +80005568: 6f f0 4f d1 j -2796 +8000556c: 83 27 41 00 lw a5, 4(sp) +80005570: 13 0d 04 00 mv s10, s0 +80005574: 23 10 f7 00 sh a5, 0(a4) +80005578: 6f e0 4f cb j -6988 +8000557c: 83 27 c1 00 lw a5, 12(sp) +80005580: 93 0c 00 00 mv s9, zero +80005584: 23 26 e1 00 sw a4, 12(sp) +80005588: 83 ad 07 00 lw s11, 0(a5) +8000558c: 6f e0 4f e1 j -6636 +80005590: 83 27 c1 00 lw a5, 12(sp) +80005594: 93 0c 00 00 mv s9, zero +80005598: 23 26 e1 00 sw a4, 12(sp) +8000559c: 83 ad 07 00 lw s11, 0(a5) +800055a0: 6f f0 8f f6 j -2200 +800055a4: 83 27 c1 00 lw a5, 12(sp) +800055a8: 23 26 e1 00 sw a4, 12(sp) +800055ac: 83 ad 07 00 lw s11, 0(a5) +800055b0: 93 dc fd 41 srai s9, s11, 31 +800055b4: 13 87 0c 00 mv a4, s9 +800055b8: 6f e0 4f d6 j -6812 +800055bc: 83 27 c1 00 lw a5, 12(sp) +800055c0: 93 0c 00 00 mv s9, zero +800055c4: 23 26 e1 00 sw a4, 12(sp) +800055c8: 83 ad 07 00 lw s11, 0(a5) +800055cc: 13 07 10 00 addi a4, zero, 1 +800055d0: 6f e0 8f dd j -6696 +800055d4: 13 06 41 0e addi a2, sp, 228 +800055d8: 93 05 0b 00 mv a1, s6 +800055dc: 13 85 0a 00 mv a0, s5 +800055e0: ef 50 10 3c jal 23488 +800055e4: 83 57 cb 00 lhu a5, 12(s6) +800055e8: 6f e0 cf c5 j -7076 +800055ec: 93 07 d0 02 addi a5, zero, 45 +800055f0: a3 03 f1 0c sb a5, 199(sp) +800055f4: 6f f0 1f ec j -320 +800055f8: 13 06 41 0e addi a2, sp, 228 +800055fc: 93 05 0b 00 mv a1, s6 +80005600: 13 85 0a 00 mv a0, s5 +80005604: ef 50 d0 39 jal 23452 +80005608: 63 18 05 a2 bnez a0, -3536 +8000560c: 83 25 c1 0c lw a1, 204(sp) +80005610: 83 27 c1 0e lw a5, 236(sp) +80005614: 83 26 81 0e lw a3, 232(sp) +80005618: 93 88 0b 00 mv a7, s7 +8000561c: e3 d0 05 b8 bgez a1, -1152 +80005620: 6f f0 df d2 j -724 +80005624: 13 03 60 00 addi t1, zero, 6 +80005628: 6f e0 4f eb j -6476 +8000562c: 03 27 01 01 lw a4, 16(sp) +80005630: b3 06 ed 00 add a3, s10, a4 +80005634: 63 fe 96 ba bgeu a3, s1, -3140 +80005638: 93 84 06 00 mv s1, a3 +8000563c: 6f f0 4f bb j -3148 +80005640: 03 27 01 03 lw a4, 48(sp) +80005644: 93 07 d0 ff addi a5, zero, -3 +80005648: 63 44 f7 00 blt a4, a5, 8 +8000564c: 63 5a e3 00 bge t1, a4, 20 +80005650: 93 84 e4 ff addi s1, s1, -2 +80005654: 93 f7 f4 fd andi a5, s1, -33 +80005658: 23 2c f1 06 sw a5, 120(sp) +8000565c: 6f e0 4f fd j -6188 +80005660: 83 27 01 01 lw a5, 16(sp) +80005664: 03 27 01 03 lw a4, 48(sp) +80005668: 63 40 f7 28 blt a4, a5, 640 +8000566c: 83 27 81 06 lw a5, 104(sp) +80005670: 93 0c 07 00 mv s9, a4 +80005674: 93 f7 17 00 andi a5, a5, 1 +80005678: 63 86 07 00 beqz a5, 12 +8000567c: 83 27 c1 03 lw a5, 60(sp) +80005680: b3 0c f7 00 add s9, a4, a5 +80005684: 83 27 81 06 lw a5, 104(sp) +80005688: 93 f7 07 40 andi a5, a5, 1024 +8000568c: 63 86 07 00 beqz a5, 12 +80005690: 83 27 01 03 lw a5, 48(sp) +80005694: e3 40 f0 06 bgtz a5, 2144 +80005698: 13 cc fc ff not s8, s9 +8000569c: 13 5c fc 41 srai s8, s8, 31 +800056a0: 33 fc 8c 01 and s8, s9, s8 +800056a4: 93 04 70 06 addi s1, zero, 103 +800056a8: 23 26 01 02 sw zero, 44(sp) +800056ac: 23 2a 01 02 sw zero, 52(sp) +800056b0: 6f e0 df 89 j -5988 +800056b4: 83 47 71 0c lbu a5, 199(sp) +800056b8: 13 03 00 00 mv t1, zero +800056bc: 63 84 07 00 beqz a5, 8 +800056c0: 6f e0 0f cb j -6992 +800056c4: 6f e0 4f a5 j -7596 +800056c8: 13 06 41 0e addi a2, sp, 228 +800056cc: 93 05 0b 00 mv a1, s6 +800056d0: 13 85 0a 00 mv a0, s5 +800056d4: ef 50 d0 2c jal 23244 +800056d8: 63 10 05 96 bnez a0, -3744 +800056dc: 83 27 81 03 lw a5, 56(sp) +800056e0: 93 88 0b 00 mv a7, s7 +800056e4: 13 08 00 01 addi a6, zero, 16 +800056e8: 83 c6 07 00 lbu a3, 0(a5) +800056ec: 13 0e 70 00 addi t3, zero, 7 +800056f0: 83 27 c1 0e lw a5, 236(sp) +800056f4: b3 84 d4 00 add s1, s1, a3 +800056f8: 6f f0 9f 80 j -2040 +800056fc: 93 07 d0 02 addi a5, zero, 45 +80005700: a3 03 f1 0c sb a5, 199(sp) +80005704: 6f f0 9f bc j -1080 +80005708: 13 06 41 0e addi a2, sp, 228 +8000570c: 93 05 0b 00 mv a1, s6 +80005710: 13 85 0a 00 mv a0, s5 +80005714: ef 50 d0 28 jal 23180 +80005718: 63 10 05 92 bnez a0, -3808 +8000571c: 83 25 c1 0c lw a1, 204(sp) +80005720: 83 27 c1 0e lw a5, 236(sp) +80005724: 93 88 0b 00 mv a7, s7 +80005728: 6f f0 cf b0 j -3316 +8000572c: 13 0c 01 0b addi s8, sp, 176 +80005730: 93 06 03 00 mv a3, t1 +80005734: 13 08 c1 0d addi a6, sp, 220 +80005738: 93 07 01 0d addi a5, sp, 208 +8000573c: 13 07 c1 0c addi a4, sp, 204 +80005740: 13 06 30 00 addi a2, zero, 3 +80005744: 93 05 0c 00 mv a1, s8 +80005748: 13 85 0a 00 mv a0, s5 +8000574c: 23 24 11 03 sw a7, 40(sp) +80005750: 23 22 61 02 sw t1, 36(sp) +80005754: 23 28 d1 0b sw t4, 176(sp) +80005758: 23 20 d1 03 sw t4, 32(sp) +8000575c: 23 2a e1 0b sw t5, 180(sp) +80005760: 23 2e e1 01 sw t5, 28(sp) +80005764: 23 2c f1 0b sw t6, 184(sp) +80005768: 23 28 f1 01 sw t6, 16(sp) +8000576c: 23 2e c1 0b sw t3, 188(sp) +80005770: 23 24 c1 01 sw t3, 8(sp) +80005774: ef 20 50 12 jal 10532 +80005778: 03 2e 81 00 lw t3, 8(sp) +8000577c: 83 2f 01 01 lw t6, 16(sp) +80005780: 03 2f c1 01 lw t5, 28(sp) +80005784: 83 2e 01 02 lw t4, 32(sp) +80005788: 03 23 41 02 lw t1, 36(sp) +8000578c: 83 28 81 02 lw a7, 40(sp) +80005790: 13 0d 05 00 mv s10, a0 +80005794: 93 07 60 04 addi a5, zero, 70 +80005798: 33 08 6d 00 add a6, s10, t1 +8000579c: 63 9c fc 68 bne s9, a5, 1688 +800057a0: 83 46 0d 00 lbu a3, 0(s10) +800057a4: 93 07 00 03 addi a5, zero, 48 +800057a8: e3 88 f6 14 beq a3, a5, 2384 +800057ac: 93 0c 01 0a addi s9, sp, 160 +800057b0: 83 27 c1 0c lw a5, 204(sp) +800057b4: 33 08 f8 00 add a6, a6, a5 +800057b8: 6f e0 cf dd j -6692 +800057bc: 13 0c 01 0b addi s8, sp, 176 +800057c0: 93 07 01 0d addi a5, sp, 208 +800057c4: 93 06 03 00 mv a3, t1 +800057c8: 13 08 c1 0d addi a6, sp, 220 +800057cc: 13 07 c1 0c addi a4, sp, 204 +800057d0: 13 06 20 00 addi a2, zero, 2 +800057d4: 93 05 0c 00 mv a1, s8 +800057d8: 13 85 0a 00 mv a0, s5 +800057dc: 23 22 61 02 sw t1, 36(sp) +800057e0: 23 28 d1 0b sw t4, 176(sp) +800057e4: 23 20 d1 03 sw t4, 32(sp) +800057e8: 23 2a e1 0b sw t5, 180(sp) +800057ec: 23 2e e1 01 sw t5, 28(sp) +800057f0: 23 2c f1 0b sw t6, 184(sp) +800057f4: 23 28 f1 01 sw t6, 16(sp) +800057f8: 23 2e c1 0b sw t3, 188(sp) +800057fc: 23 24 c1 01 sw t3, 8(sp) +80005800: ef 20 90 09 jal 10392 +80005804: 93 07 70 04 addi a5, zero, 71 +80005808: 03 2e 81 00 lw t3, 8(sp) +8000580c: 83 2f 01 01 lw t6, 16(sp) +80005810: 03 2f c1 01 lw t5, 28(sp) +80005814: 83 2e 01 02 lw t4, 32(sp) +80005818: 03 23 41 02 lw t1, 36(sp) +8000581c: 83 28 81 02 lw a7, 40(sp) +80005820: 13 0d 05 00 mv s10, a0 +80005824: e3 98 fc f6 bne s9, a5, -144 +80005828: 83 27 81 06 lw a5, 104(sp) +8000582c: 93 f7 17 00 andi a5, a5, 1 +80005830: 63 9c 07 5e bnez a5, 1528 +80005834: 13 07 70 04 addi a4, zero, 71 +80005838: 83 27 c1 0d lw a5, 220(sp) +8000583c: 23 2c e1 06 sw a4, 120(sp) +80005840: 6f e0 0f dc j -6720 +80005844: 83 47 71 0c lbu a5, 199(sp) +80005848: 23 26 d1 00 sw a3, 12(sp) +8000584c: 23 26 01 02 sw zero, 44(sp) +80005850: 23 2a 01 02 sw zero, 52(sp) +80005854: 23 28 01 02 sw zero, 48(sp) +80005858: 13 0c 03 00 mv s8, t1 +8000585c: 93 0c 03 00 mv s9, t1 +80005860: 13 03 00 00 mv t1, zero +80005864: 63 84 07 00 beqz a5, 8 +80005868: 6f e0 8f b0 j -7416 +8000586c: 6f e0 cf 8a j -8020 +80005870: 13 06 41 0e addi a2, sp, 228 +80005874: 93 05 0b 00 mv a1, s6 +80005878: 13 85 0a 00 mv a0, s5 +8000587c: ef 50 50 12 jal 22820 +80005880: 63 04 05 00 beqz a0, 8 +80005884: 6f e0 5f fb j -4172 +80005888: 83 24 c1 0c lw s1, 204(sp) +8000588c: 03 27 01 01 lw a4, 16(sp) +80005890: 83 27 c1 0e lw a5, 236(sp) +80005894: 93 88 0b 00 mv a7, s7 +80005898: 33 06 97 40 sub a2, a4, s1 +8000589c: 6f f0 0f 9e j -3616 +800058a0: 83 27 81 06 lw a5, 104(sp) +800058a4: 03 27 01 03 lw a4, 48(sp) +800058a8: 93 f7 17 00 andi a5, a5, 1 +800058ac: b3 e7 67 00 or a5, a5, t1 +800058b0: e3 54 e0 0c blez a4, 2248 +800058b4: 63 98 07 6c bnez a5, 1744 +800058b8: 83 2c 01 03 lw s9, 48(sp) +800058bc: 93 04 60 06 addi s1, zero, 102 +800058c0: 83 27 81 06 lw a5, 104(sp) +800058c4: 93 f7 07 40 andi a5, a5, 1024 +800058c8: 63 98 07 62 bnez a5, 1584 +800058cc: 13 cc fc ff not s8, s9 +800058d0: 13 5c fc 41 srai s8, s8, 31 +800058d4: 33 fc 8c 01 and s8, s9, s8 +800058d8: 6f f0 1f dd j -560 +800058dc: 37 57 01 80 lui a4, 524309 +800058e0: 13 0d 07 5a addi s10, a4, 1440 +800058e4: 6f f0 9f 9f j -1544 +800058e8: 83 27 01 01 lw a5, 16(sp) +800058ec: 03 27 c1 03 lw a4, 60(sp) +800058f0: 93 04 70 06 addi s1, zero, 103 +800058f4: b3 8c e7 00 add s9, a5, a4 +800058f8: 83 27 01 03 lw a5, 48(sp) +800058fc: e3 42 f0 fc bgtz a5, -60 +80005900: b3 8c fc 40 sub s9, s9, a5 +80005904: 93 8c 1c 00 addi s9, s9, 1 +80005908: 13 cc fc ff not s8, s9 +8000590c: 13 5c fc 41 srai s8, s8, 31 +80005910: 33 fc 8c 01 and s8, s9, s8 +80005914: 6f f0 5f d9 j -620 +80005918: b7 56 01 80 lui a3, 524309 +8000591c: 93 8e 86 74 addi t4, a3, 1864 +80005920: 6f e0 df 83 j -6084 +80005924: 93 07 00 03 addi a5, zero, 48 +80005928: 23 04 f1 0c sb a5, 200(sp) +8000592c: 93 07 80 05 addi a5, zero, 88 +80005930: 13 67 29 00 ori a4, s2, 2 +80005934: a3 04 f1 0c sb a5, 201(sp) +80005938: 23 24 e1 06 sw a4, 104(sp) +8000593c: 93 07 30 06 addi a5, zero, 99 +80005940: 93 0d 00 00 mv s11, zero +80005944: 13 0d c1 14 addi s10, sp, 332 +80005948: 63 ce 67 44 blt a5, t1, 1116 +8000594c: 03 2e c1 0f lw t3, 252(sp) +80005950: 93 fc f4 fd andi s9, s1, -33 +80005954: 23 2c 91 07 sw s9, 120(sp) +80005958: 23 2e 01 06 sw zero, 124(sp) +8000595c: 83 2e 01 0f lw t4, 240(sp) +80005960: 03 2f 41 0f lw t5, 244(sp) +80005964: 83 2f 81 0f lw t6, 248(sp) +80005968: 13 69 29 10 ori s2, s2, 258 +8000596c: 63 42 0e 3c bltz t3, 964 +80005970: 93 07 10 06 addi a5, zero, 97 +80005974: 63 88 f4 62 beq s1, a5, 1584 +80005978: 93 07 10 04 addi a5, zero, 65 +8000597c: 63 84 f4 00 beq s1, a5, 8 +80005980: 6f e0 8f b8 j -7288 +80005984: 13 0c 01 0b addi s8, sp, 176 +80005988: 13 05 0c 00 mv a0, s8 +8000598c: 23 26 11 03 sw a7, 44(sp) +80005990: 23 24 61 02 sw t1, 40(sp) +80005994: 23 28 d1 0b sw t4, 176(sp) +80005998: 23 2a e1 0b sw t5, 180(sp) +8000599c: 23 2c f1 0b sw t6, 184(sp) +800059a0: 23 2e c1 0b sw t3, 188(sp) +800059a4: ef f0 80 64 jal 63048 +800059a8: 13 06 c1 0c addi a2, sp, 204 +800059ac: ef 50 c0 41 jal 21532 +800059b0: 13 86 05 00 mv a2, a1 +800059b4: 93 05 05 00 mv a1, a0 +800059b8: 13 05 0c 00 mv a0, s8 +800059bc: ef f0 80 40 jal 62472 +800059c0: 93 07 01 09 addi a5, sp, 144 +800059c4: 93 85 07 00 mv a1, a5 +800059c8: 23 24 f1 00 sw a5, 8(sp) +800059cc: 83 27 01 0b lw a5, 176(sp) +800059d0: 93 0c 01 0a addi s9, sp, 160 +800059d4: 13 06 01 08 addi a2, sp, 128 +800059d8: 23 28 f1 08 sw a5, 144(sp) +800059dc: 83 27 41 0b lw a5, 180(sp) +800059e0: 13 85 0c 00 mv a0, s9 +800059e4: 23 26 c1 06 sw a2, 108(sp) +800059e8: 23 2a f1 08 sw a5, 148(sp) +800059ec: 83 27 81 0b lw a5, 184(sp) +800059f0: 23 20 01 08 sw zero, 128(sp) +800059f4: 23 22 01 08 sw zero, 132(sp) +800059f8: 23 2c f1 08 sw a5, 152(sp) +800059fc: 83 27 c1 0b lw a5, 188(sp) +80005a00: 23 24 01 08 sw zero, 136(sp) +80005a04: 23 2e f1 08 sw a5, 156(sp) +80005a08: b7 07 fc 3f lui a5, 262080 +80005a0c: 23 26 f1 08 sw a5, 140(sp) +80005a10: ef c0 c0 20 jal 49676 +80005a14: 03 28 01 0a lw a6, 160(sp) +80005a18: 03 2e 41 0a lw t3, 164(sp) +80005a1c: 83 2e 81 0a lw t4, 168(sp) +80005a20: 03 2f c1 0a lw t5, 172(sp) +80005a24: 93 85 0c 00 mv a1, s9 +80005a28: 13 05 0c 00 mv a0, s8 +80005a2c: 23 28 01 0b sw a6, 176(sp) +80005a30: 23 22 01 03 sw a6, 36(sp) +80005a34: 23 2a c1 0b sw t3, 180(sp) +80005a38: 23 20 c1 03 sw t3, 32(sp) +80005a3c: 23 2c d1 0b sw t4, 184(sp) +80005a40: 23 2e d1 01 sw t4, 28(sp) +80005a44: 23 2e e1 0b sw t5, 188(sp) +80005a48: 23 28 e1 01 sw t5, 16(sp) +80005a4c: 23 20 01 0a sw zero, 160(sp) +80005a50: 23 22 01 0a sw zero, 164(sp) +80005a54: 23 24 01 0a sw zero, 168(sp) +80005a58: 23 26 01 0a sw zero, 172(sp) +80005a5c: ef b0 d0 5f jal 48636 +80005a60: 03 2f 01 01 lw t5, 16(sp) +80005a64: 83 2e c1 01 lw t4, 28(sp) +80005a68: 03 2e 01 02 lw t3, 32(sp) +80005a6c: 03 28 41 02 lw a6, 36(sp) +80005a70: 03 23 81 02 lw t1, 40(sp) +80005a74: 83 28 c1 02 lw a7, 44(sp) +80005a78: 63 16 05 00 bnez a0, 12 +80005a7c: 93 07 10 00 addi a5, zero, 1 +80005a80: 23 26 f1 0c sw a5, 204(sp) +80005a84: b7 57 01 80 lui a5, 524309 +80005a88: 93 87 c7 5b addi a5, a5, 1468 +80005a8c: 23 22 f1 06 sw a5, 100(sp) +80005a90: 93 06 f3 ff addi a3, t1, -1 +80005a94: 93 07 0d 00 mv a5, s10 +80005a98: 6f 00 40 09 j 148 +80005a9c: 93 85 0c 00 mv a1, s9 +80005aa0: 13 05 0c 00 mv a0, s8 +80005aa4: 23 20 c1 06 sw a2, 96(sp) +80005aa8: 23 2e f1 05 sw t6, 92(sp) +80005aac: 23 2c 51 04 sw t0, 88(sp) +80005ab0: 23 2a 71 04 sw t2, 84(sp) +80005ab4: 23 28 f1 04 sw a5, 80(sp) +80005ab8: 23 2a 11 03 sw a7, 52(sp) +80005abc: 23 28 61 02 sw t1, 48(sp) +80005ac0: 23 28 71 0a sw t2, 176(sp) +80005ac4: 23 26 71 02 sw t2, 44(sp) +80005ac8: 23 2a 51 0a sw t0, 180(sp) +80005acc: 23 24 51 02 sw t0, 40(sp) +80005ad0: 23 2c f1 0b sw t6, 184(sp) +80005ad4: 23 22 f1 03 sw t6, 36(sp) +80005ad8: 23 2e c1 0a sw a2, 188(sp) +80005adc: 23 20 c1 02 sw a2, 32(sp) +80005ae0: 23 20 01 0a sw zero, 160(sp) +80005ae4: 23 22 01 0a sw zero, 164(sp) +80005ae8: 23 24 01 0a sw zero, 168(sp) +80005aec: 23 26 01 0a sw zero, 172(sp) +80005af0: ef b0 90 56 jal 48488 +80005af4: 83 26 c1 01 lw a3, 28(sp) +80005af8: 03 2f 01 02 lw t5, 32(sp) +80005afc: 83 2e 41 02 lw t4, 36(sp) +80005b00: 03 2e 81 02 lw t3, 40(sp) +80005b04: 03 28 c1 02 lw a6, 44(sp) +80005b08: 03 23 01 03 lw t1, 48(sp) +80005b0c: 83 28 41 03 lw a7, 52(sp) +80005b10: 83 27 01 05 lw a5, 80(sp) +80005b14: 83 23 41 05 lw t2, 84(sp) +80005b18: 83 22 81 05 lw t0, 88(sp) +80005b1c: 83 2f c1 05 lw t6, 92(sp) +80005b20: 03 26 01 06 lw a2, 96(sp) +80005b24: 93 86 f6 ff addi a3, a3, -1 +80005b28: 63 0e 05 10 beqz a0, 284 +80005b2c: 03 26 81 00 lw a2, 8(sp) +80005b30: 93 85 0c 00 mv a1, s9 +80005b34: 23 2a f1 02 sw a5, 52(sp) +80005b38: 13 05 0c 00 mv a0, s8 +80005b3c: b7 07 03 40 lui a5, 262192 +80005b40: 23 28 d1 04 sw a3, 80(sp) +80005b44: 23 28 11 03 sw a7, 48(sp) +80005b48: 23 26 61 02 sw t1, 44(sp) +80005b4c: 23 2e f1 08 sw a5, 156(sp) +80005b50: 23 26 e1 0b sw t5, 172(sp) +80005b54: 23 20 01 0b sw a6, 160(sp) +80005b58: 23 22 c1 0b sw t3, 164(sp) +80005b5c: 23 24 d1 0b sw t4, 168(sp) +80005b60: 23 28 01 08 sw zero, 144(sp) +80005b64: 23 2a 01 08 sw zero, 148(sp) +80005b68: 23 2c 01 08 sw zero, 152(sp) +80005b6c: ef c0 00 0b jal 49328 +80005b70: 83 2e 01 0b lw t4, 176(sp) +80005b74: 03 2e 41 0b lw t3, 180(sp) +80005b78: 03 28 81 0b lw a6, 184(sp) +80005b7c: 03 26 c1 0b lw a2, 188(sp) +80005b80: 13 05 0c 00 mv a0, s8 +80005b84: 23 24 d1 03 sw t4, 40(sp) +80005b88: 23 22 c1 03 sw t3, 36(sp) +80005b8c: 23 20 01 03 sw a6, 32(sp) +80005b90: 23 2e c1 00 sw a2, 28(sp) +80005b94: ef e0 90 62 jal 60968 +80005b98: 93 05 05 00 mv a1, a0 +80005b9c: 23 28 a1 00 sw a0, 16(sp) +80005ba0: 13 05 0c 00 mv a0, s8 +80005ba4: ef e0 50 7c jal 61380 +80005ba8: 03 26 c1 01 lw a2, 28(sp) +80005bac: 83 2e 81 02 lw t4, 40(sp) +80005bb0: 03 2e 41 02 lw t3, 36(sp) +80005bb4: 23 2e c1 08 sw a2, 156(sp) +80005bb8: 03 26 01 0b lw a2, 176(sp) +80005bbc: 03 28 01 02 lw a6, 32(sp) +80005bc0: 83 25 81 00 lw a1, 8(sp) +80005bc4: 23 20 c1 08 sw a2, 128(sp) +80005bc8: 03 26 41 0b lw a2, 180(sp) +80005bcc: 13 85 0c 00 mv a0, s9 +80005bd0: 23 28 d1 09 sw t4, 144(sp) +80005bd4: 23 22 c1 08 sw a2, 132(sp) +80005bd8: 03 26 81 0b lw a2, 184(sp) +80005bdc: 23 2a c1 09 sw t3, 148(sp) +80005be0: 23 2c 01 09 sw a6, 152(sp) +80005be4: 23 24 c1 08 sw a2, 136(sp) +80005be8: 03 26 c1 0b lw a2, 188(sp) +80005bec: 23 26 c1 08 sw a2, 140(sp) +80005bf0: 03 26 c1 06 lw a2, 108(sp) +80005bf4: ef d0 00 30 jal 54016 +80005bf8: 03 27 41 06 lw a4, 100(sp) +80005bfc: 83 27 01 01 lw a5, 16(sp) +80005c00: 83 26 01 05 lw a3, 80(sp) +80005c04: 83 23 01 0a lw t2, 160(sp) +80005c08: 33 06 f7 00 add a2, a4, a5 +80005c0c: 83 45 06 00 lbu a1, 0(a2) +80005c10: 83 27 41 03 lw a5, 52(sp) +80005c14: 83 22 41 0a lw t0, 164(sp) +80005c18: 83 2f 81 0a lw t6, 168(sp) +80005c1c: 03 26 c1 0a lw a2, 172(sp) +80005c20: 23 2a f1 06 sw a5, 116(sp) +80005c24: 23 80 b7 00 sb a1, 0(a5) +80005c28: 23 28 d1 06 sw a3, 112(sp) +80005c2c: 13 07 f0 ff addi a4, zero, -1 +80005c30: 23 2e d1 00 sw a3, 28(sp) +80005c34: 03 23 c1 02 lw t1, 44(sp) +80005c38: 83 28 01 03 lw a7, 48(sp) +80005c3c: 93 87 17 00 addi a5, a5, 1 +80005c40: e3 9e e6 e4 bne a3, a4, -420 +80005c44: b7 06 fe 3f lui a3, 262112 +80005c48: 93 85 0c 00 mv a1, s9 +80005c4c: 13 05 0c 00 mv a0, s8 +80005c50: 23 20 f1 02 sw a5, 32(sp) +80005c54: 23 2e 11 01 sw a7, 28(sp) +80005c58: 23 24 61 00 sw t1, 8(sp) +80005c5c: 23 28 71 0a sw t2, 176(sp) +80005c60: 23 28 71 02 sw t2, 48(sp) +80005c64: 23 2a 51 0a sw t0, 180(sp) +80005c68: 23 26 51 02 sw t0, 44(sp) +80005c6c: 23 2c f1 0b sw t6, 184(sp) +80005c70: 23 24 f1 03 sw t6, 40(sp) +80005c74: 23 2e c1 0a sw a2, 188(sp) +80005c78: 23 22 c1 02 sw a2, 36(sp) +80005c7c: 23 20 01 0a sw zero, 160(sp) +80005c80: 23 22 01 0a sw zero, 164(sp) +80005c84: 23 24 01 0a sw zero, 168(sp) +80005c88: 23 26 d1 0a sw a3, 172(sp) +80005c8c: ef b0 90 4f jal 48376 +80005c90: 03 23 81 00 lw t1, 8(sp) +80005c94: 83 28 c1 01 lw a7, 28(sp) +80005c98: 83 27 01 02 lw a5, 32(sp) +80005c9c: 63 44 a0 0a bgtz a0, 168 +80005ca0: 83 23 01 03 lw t2, 48(sp) +80005ca4: 83 22 c1 02 lw t0, 44(sp) +80005ca8: 83 2f 81 02 lw t6, 40(sp) +80005cac: 03 26 41 02 lw a2, 36(sp) +80005cb0: b7 06 fe 3f lui a3, 262112 +80005cb4: 93 85 0c 00 mv a1, s9 +80005cb8: 13 05 0c 00 mv a0, s8 +80005cbc: 23 28 71 0a sw t2, 176(sp) +80005cc0: 23 2a 51 0a sw t0, 180(sp) +80005cc4: 23 2c f1 0b sw t6, 184(sp) +80005cc8: 23 2e c1 0a sw a2, 188(sp) +80005ccc: 23 20 01 0a sw zero, 160(sp) +80005cd0: 23 22 01 0a sw zero, 164(sp) +80005cd4: 23 24 01 0a sw zero, 168(sp) +80005cd8: 23 26 d1 0a sw a3, 172(sp) +80005cdc: ef b0 d0 37 jal 47996 +80005ce0: 03 23 81 00 lw t1, 8(sp) +80005ce4: 83 28 c1 01 lw a7, 28(sp) +80005ce8: 83 27 01 02 lw a5, 32(sp) +80005cec: 63 18 05 00 bnez a0, 16 +80005cf0: 03 27 01 01 lw a4, 16(sp) +80005cf4: 93 76 17 00 andi a3, a4, 1 +80005cf8: 63 96 06 04 bnez a3, 76 +80005cfc: 03 27 01 07 lw a4, 112(sp) +80005d00: 13 06 00 03 addi a2, zero, 48 +80005d04: 93 06 17 00 addi a3, a4, 1 +80005d08: b3 86 d7 00 add a3, a5, a3 +80005d0c: 63 54 07 00 bgez a4, 8 +80005d10: 6f e0 0f 8f j -7952 +80005d14: 93 87 17 00 addi a5, a5, 1 +80005d18: a3 8f c7 fe sb a2, -1(a5) +80005d1c: e3 9c d7 fe bne a5, a3, -8 +80005d20: 6f e0 0f 8e j -7968 +80005d24: 23 24 21 07 sw s2, 104(sp) +80005d28: 93 0d 00 00 mv s11, zero +80005d2c: 13 89 02 00 mv s2, t0 +80005d30: b7 07 00 80 lui a5, 524288 +80005d34: 33 ce c7 01 xor t3, a5, t3 +80005d38: 93 07 d0 02 addi a5, zero, 45 +80005d3c: 23 2e f1 06 sw a5, 124(sp) +80005d40: 6f f0 1f c3 j -976 +80005d44: 03 27 41 07 lw a4, 116(sp) +80005d48: 93 86 07 00 mv a3, a5 +80005d4c: 23 2e e1 0c sw a4, 220(sp) +80005d50: 03 27 41 06 lw a4, 100(sp) +80005d54: 03 c6 f7 ff lbu a2, -1(a5) +80005d58: 83 45 f7 00 lbu a1, 15(a4) +80005d5c: 63 10 b6 02 bne a2, a1, 32 +80005d60: 13 05 00 03 addi a0, zero, 48 +80005d64: a3 8f a6 fe sb a0, -1(a3) +80005d68: 83 26 c1 0d lw a3, 220(sp) +80005d6c: 13 86 f6 ff addi a2, a3, -1 +80005d70: 23 2e c1 0c sw a2, 220(sp) +80005d74: 03 c6 f6 ff lbu a2, -1(a3) +80005d78: e3 86 c5 fe beq a1, a2, -20 +80005d7c: 93 05 16 00 addi a1, a2, 1 +80005d80: 13 05 90 03 addi a0, zero, 57 +80005d84: 93 f5 f5 0f andi a1, a1, 255 +80005d88: 63 06 a6 00 beq a2, a0, 12 +80005d8c: a3 8f b6 fe sb a1, -1(a3) +80005d90: 6f e0 0f 87 j -8080 +80005d94: 03 27 41 06 lw a4, 100(sp) +80005d98: 83 45 a7 00 lbu a1, 10(a4) +80005d9c: a3 8f b6 fe sb a1, -1(a3) +80005da0: 6f e0 0f 86 j -8096 +80005da4: 93 05 13 00 addi a1, t1, 1 +80005da8: 13 85 0a 00 mv a0, s5 +80005dac: 23 28 11 01 sw a7, 16(sp) +80005db0: 23 24 61 00 sw t1, 8(sp) +80005db4: ef 30 c0 62 jal 13868 +80005db8: 03 23 81 00 lw t1, 8(sp) +80005dbc: 83 28 01 01 lw a7, 16(sp) +80005dc0: 13 0d 05 00 mv s10, a0 +80005dc4: 63 04 05 42 beqz a0, 1064 +80005dc8: 93 0d 05 00 mv s11, a0 +80005dcc: 6f f0 1f b8 j -1152 +80005dd0: 93 07 00 03 addi a5, zero, 48 +80005dd4: 23 04 f1 0c sb a5, 200(sp) +80005dd8: 93 07 80 07 addi a5, zero, 120 +80005ddc: 6f f0 5f b5 j -1196 +80005de0: b3 87 97 00 add a5, a5, s1 +80005de4: 93 86 16 00 addi a3, a3, 1 +80005de8: 23 a0 38 01 sw s3, 0(a7) +80005dec: 23 a2 98 00 sw s1, 4(a7) +80005df0: 23 26 f1 0e sw a5, 236(sp) +80005df4: 23 24 d1 0e sw a3, 232(sp) +80005df8: 13 06 70 00 addi a2, zero, 7 +80005dfc: 63 5e d6 b8 bge a2, a3, -3172 +80005e00: 13 06 41 0e addi a2, sp, 228 +80005e04: 93 05 0b 00 mv a1, s6 +80005e08: 13 85 0a 00 mv a0, s5 +80005e0c: ef 50 40 39 jal 21396 +80005e10: 63 04 05 00 beqz a0, 8 +80005e14: 6f e0 5f a2 j -5596 +80005e18: 83 27 c1 0e lw a5, 236(sp) +80005e1c: 83 26 81 0e lw a3, 232(sp) +80005e20: 93 88 0b 00 mv a7, s7 +80005e24: 6f f0 8f b7 j -3208 +80005e28: 93 07 70 04 addi a5, zero, 71 +80005e2c: 33 08 6d 00 add a6, s10, t1 +80005e30: 23 2c f1 06 sw a5, 120(sp) +80005e34: 93 0c 01 0a addi s9, sp, 160 +80005e38: 6f d0 df f5 j -8356 +80005e3c: 13 0c 09 00 mv s8, s2 +80005e40: 6f e0 cf d0 j -6900 +80005e44: 93 07 f0 ff addi a5, zero, -1 +80005e48: 23 22 f1 00 sw a5, 4(sp) +80005e4c: 6f d0 5f c0 j -9212 +80005e50: 63 14 03 00 bnez t1, 8 +80005e54: 13 03 10 00 addi t1, zero, 1 +80005e58: 03 2e c1 0f lw t3, 252(sp) +80005e5c: 83 2e 01 0f lw t4, 240(sp) +80005e60: 03 2f 41 0f lw t5, 244(sp) +80005e64: 83 2f 81 0f lw t6, 248(sp) +80005e68: 93 62 09 10 ori t0, s2, 256 +80005e6c: e3 4c 0e ea bltz t3, -328 +80005e70: 13 0c 01 0b addi s8, sp, 176 +80005e74: 93 06 03 00 mv a3, t1 +80005e78: 13 08 c1 0d addi a6, sp, 220 +80005e7c: 93 07 01 0d addi a5, sp, 208 +80005e80: 13 07 c1 0c addi a4, sp, 204 +80005e84: 13 06 20 00 addi a2, zero, 2 +80005e88: 93 05 0c 00 mv a1, s8 +80005e8c: 13 85 0a 00 mv a0, s5 +80005e90: 23 26 51 02 sw t0, 44(sp) +80005e94: 23 24 11 03 sw a7, 40(sp) +80005e98: 23 22 61 02 sw t1, 36(sp) +80005e9c: 23 28 d1 0b sw t4, 176(sp) +80005ea0: 23 20 d1 03 sw t4, 32(sp) +80005ea4: 23 2a e1 0b sw t5, 180(sp) +80005ea8: 23 2e e1 01 sw t5, 28(sp) +80005eac: 23 2c f1 0b sw t6, 184(sp) +80005eb0: 23 28 f1 01 sw t6, 16(sp) +80005eb4: 23 2e c1 0b sw t3, 188(sp) +80005eb8: 23 24 c1 01 sw t3, 8(sp) +80005ebc: ef 20 c0 1d jal 8668 +80005ec0: 83 22 c1 02 lw t0, 44(sp) +80005ec4: 23 24 21 07 sw s2, 104(sp) +80005ec8: 03 2e 81 00 lw t3, 8(sp) +80005ecc: 83 2f 01 01 lw t6, 16(sp) +80005ed0: 03 2f c1 01 lw t5, 28(sp) +80005ed4: 83 2e 01 02 lw t4, 32(sp) +80005ed8: 03 23 41 02 lw t1, 36(sp) +80005edc: 83 28 81 02 lw a7, 40(sp) +80005ee0: 13 0d 05 00 mv s10, a0 +80005ee4: 13 89 02 00 mv s2, t0 +80005ee8: 93 0d 00 00 mv s11, zero +80005eec: 23 2e 01 06 sw zero, 124(sp) +80005ef0: 6f f0 9f 93 j -1736 +80005ef4: 93 04 70 06 addi s1, zero, 103 +80005ef8: 83 27 81 03 lw a5, 56(sp) +80005efc: 93 06 f0 0f addi a3, zero, 255 +80005f00: 23 26 01 02 sw zero, 44(sp) +80005f04: 83 c7 07 00 lbu a5, 0(a5) +80005f08: 23 2a 01 02 sw zero, 52(sp) +80005f0c: 63 88 d7 04 beq a5, a3, 80 +80005f10: 03 27 01 03 lw a4, 48(sp) +80005f14: 63 d4 e7 04 bge a5, a4, 72 +80005f18: b3 07 f7 40 sub a5, a4, a5 +80005f1c: 03 27 81 03 lw a4, 56(sp) +80005f20: 23 28 f1 02 sw a5, 48(sp) +80005f24: 83 47 17 00 lbu a5, 1(a4) +80005f28: 63 8e 07 00 beqz a5, 28 +80005f2c: 03 26 41 03 lw a2, 52(sp) +80005f30: 13 07 17 00 addi a4, a4, 1 +80005f34: 23 2c e1 02 sw a4, 56(sp) +80005f38: 13 06 16 00 addi a2, a2, 1 +80005f3c: 23 2a c1 02 sw a2, 52(sp) +80005f40: 6f f0 df fc j -52 +80005f44: 03 27 c1 02 lw a4, 44(sp) +80005f48: 83 27 81 03 lw a5, 56(sp) +80005f4c: 13 07 17 00 addi a4, a4, 1 +80005f50: 83 c7 07 00 lbu a5, 0(a5) +80005f54: 23 26 e1 02 sw a4, 44(sp) +80005f58: 6f f0 5f fb j -76 +80005f5c: 03 27 c1 02 lw a4, 44(sp) +80005f60: 83 27 41 03 lw a5, 52(sp) +80005f64: b3 87 e7 00 add a5, a5, a4 +80005f68: 03 27 81 04 lw a4, 72(sp) +80005f6c: b3 87 e7 02 mul a5, a5, a4 +80005f70: b3 8c 97 01 add s9, a5, s9 +80005f74: 13 cc fc ff not s8, s9 +80005f78: 13 5c fc 41 srai s8, s8, 31 +80005f7c: 33 fc 8c 01 and s8, s9, s8 +80005f80: 6f d0 df fc j -8244 +80005f84: 83 27 c1 03 lw a5, 60(sp) +80005f88: 93 04 60 06 addi s1, zero, 102 +80005f8c: b3 0c f7 00 add s9, a4, a5 +80005f90: b3 8c 6c 00 add s9, s9, t1 +80005f94: 6f f0 df 92 j -1748 +80005f98: 93 0d 00 00 mv s11, zero +80005f9c: 13 89 07 00 mv s2, a5 +80005fa0: 6f f0 1f d9 j -624 +80005fa4: 13 0c 01 0b addi s8, sp, 176 +80005fa8: 13 05 0c 00 mv a0, s8 +80005fac: 23 26 11 03 sw a7, 44(sp) +80005fb0: 23 24 61 02 sw t1, 40(sp) +80005fb4: 23 28 d1 0b sw t4, 176(sp) +80005fb8: 23 2a e1 0b sw t5, 180(sp) +80005fbc: 23 2c f1 0b sw t6, 184(sp) +80005fc0: 23 2e c1 0b sw t3, 188(sp) +80005fc4: ef f0 80 02 jal 61480 +80005fc8: 13 06 c1 0c addi a2, sp, 204 +80005fcc: ef 40 d0 5f jal 19964 +80005fd0: 13 86 05 00 mv a2, a1 +80005fd4: 93 05 05 00 mv a1, a0 +80005fd8: 13 05 0c 00 mv a0, s8 +80005fdc: ef e0 90 5e jal 60904 +80005fe0: 93 07 01 09 addi a5, sp, 144 +80005fe4: 93 85 07 00 mv a1, a5 +80005fe8: 23 24 f1 00 sw a5, 8(sp) +80005fec: 83 27 01 0b lw a5, 176(sp) +80005ff0: 93 0c 01 0a addi s9, sp, 160 +80005ff4: 13 06 01 08 addi a2, sp, 128 +80005ff8: 23 28 f1 08 sw a5, 144(sp) +80005ffc: 83 27 41 0b lw a5, 180(sp) +80006000: 13 85 0c 00 mv a0, s9 +80006004: 23 26 c1 06 sw a2, 108(sp) +80006008: 23 2a f1 08 sw a5, 148(sp) +8000600c: 83 27 81 0b lw a5, 184(sp) +80006010: 23 20 01 08 sw zero, 128(sp) +80006014: 23 22 01 08 sw zero, 132(sp) +80006018: 23 2c f1 08 sw a5, 152(sp) +8000601c: 83 27 c1 0b lw a5, 188(sp) +80006020: 23 24 01 08 sw zero, 136(sp) +80006024: 23 2e f1 08 sw a5, 156(sp) +80006028: b7 07 fc 3f lui a5, 262080 +8000602c: 23 26 f1 08 sw a5, 140(sp) +80006030: ef b0 d0 3e jal 48108 +80006034: 03 28 01 0a lw a6, 160(sp) +80006038: 03 2e 41 0a lw t3, 164(sp) +8000603c: 83 2e 81 0a lw t4, 168(sp) +80006040: 03 2f c1 0a lw t5, 172(sp) +80006044: 93 85 0c 00 mv a1, s9 +80006048: 13 05 0c 00 mv a0, s8 +8000604c: 23 28 01 0b sw a6, 176(sp) +80006050: 23 22 01 03 sw a6, 36(sp) +80006054: 23 2a c1 0b sw t3, 180(sp) +80006058: 23 20 c1 03 sw t3, 32(sp) +8000605c: 23 2c d1 0b sw t4, 184(sp) +80006060: 23 2e d1 01 sw t4, 28(sp) +80006064: 23 2e e1 0b sw t5, 188(sp) +80006068: 23 28 e1 01 sw t5, 16(sp) +8000606c: 23 20 01 0a sw zero, 160(sp) +80006070: 23 22 01 0a sw zero, 164(sp) +80006074: 23 24 01 0a sw zero, 168(sp) +80006078: 23 26 01 0a sw zero, 172(sp) +8000607c: ef b0 c0 7d jal 47068 +80006080: 03 2f 01 01 lw t5, 16(sp) +80006084: 83 2e c1 01 lw t4, 28(sp) +80006088: 03 2e 01 02 lw t3, 32(sp) +8000608c: 03 28 41 02 lw a6, 36(sp) +80006090: 03 23 81 02 lw t1, 40(sp) +80006094: 83 28 c1 02 lw a7, 44(sp) +80006098: 63 16 05 00 bnez a0, 12 +8000609c: 93 07 10 00 addi a5, zero, 1 +800060a0: 23 26 f1 0c sw a5, 204(sp) +800060a4: b7 57 01 80 lui a5, 524309 +800060a8: 93 87 87 5a addi a5, a5, 1448 +800060ac: 23 22 f1 06 sw a5, 100(sp) +800060b0: 6f f0 1f 9e j -1568 +800060b4: 93 06 61 0d addi a3, sp, 214 +800060b8: 63 18 06 00 bnez a2, 16 +800060bc: 93 06 00 03 addi a3, zero, 48 +800060c0: 23 0b d1 0c sb a3, 214(sp) +800060c4: 93 06 71 0d addi a3, sp, 215 +800060c8: 13 07 01 1b addi a4, sp, 432 +800060cc: 93 87 07 03 addi a5, a5, 48 +800060d0: 33 86 e6 40 sub a2, a3, a4 +800060d4: 23 80 f6 00 sb a5, 0(a3) +800060d8: 93 07 d6 0d addi a5, a2, 221 +800060dc: 23 22 f1 04 sw a5, 68(sp) +800060e0: 6f d0 9f e2 j -8664 +800060e4: 83 27 81 06 lw a5, 104(sp) +800060e8: 93 f7 17 00 andi a5, a5, 1 +800060ec: 63 94 07 00 bnez a5, 8 +800060f0: 6f d0 9f e3 j -8648 +800060f4: 6f d0 df e2 j -8660 +800060f8: 93 0c 01 0a addi s9, sp, 160 +800060fc: 93 85 0c 00 mv a1, s9 +80006100: 13 05 0c 00 mv a0, s8 +80006104: 23 26 01 03 sw a6, 44(sp) +80006108: 23 24 11 03 sw a7, 40(sp) +8000610c: 23 22 61 02 sw t1, 36(sp) +80006110: 23 28 d1 0b sw t4, 176(sp) +80006114: 23 20 d1 03 sw t4, 32(sp) +80006118: 23 2a e1 0b sw t5, 180(sp) +8000611c: 23 2e e1 01 sw t5, 28(sp) +80006120: 23 2c f1 0b sw t6, 184(sp) +80006124: 23 28 f1 01 sw t6, 16(sp) +80006128: 23 2e c1 0b sw t3, 188(sp) +8000612c: 23 24 c1 01 sw t3, 8(sp) +80006130: 23 20 01 0a sw zero, 160(sp) +80006134: 23 22 01 0a sw zero, 164(sp) +80006138: 23 24 01 0a sw zero, 168(sp) +8000613c: 23 26 01 0a sw zero, 172(sp) +80006140: ef b0 80 71 jal 46872 +80006144: 03 2e 81 00 lw t3, 8(sp) +80006148: 83 2f 01 01 lw t6, 16(sp) +8000614c: 03 2f c1 01 lw t5, 28(sp) +80006150: 83 2e 01 02 lw t4, 32(sp) +80006154: 03 23 41 02 lw t1, 36(sp) +80006158: 83 28 81 02 lw a7, 40(sp) +8000615c: 03 28 c1 02 lw a6, 44(sp) +80006160: 63 08 05 e4 beqz a0, -2480 +80006164: 93 07 10 00 addi a5, zero, 1 +80006168: b3 87 67 40 sub a5, a5, t1 +8000616c: 23 26 f1 0c sw a5, 204(sp) +80006170: 33 08 f8 00 add a6, a6, a5 +80006174: 6f d0 1f c2 j -9184 +80006178: 63 9a 07 00 bnez a5, 20 +8000617c: 13 0c 10 00 addi s8, zero, 1 +80006180: 93 04 60 06 addi s1, zero, 102 +80006184: 93 0c 10 00 addi s9, zero, 1 +80006188: 6f f0 0f d2 j -2784 +8000618c: 83 27 c1 03 lw a5, 60(sp) +80006190: 93 04 60 06 addi s1, zero, 102 +80006194: 93 8c 17 00 addi s9, a5, 1 +80006198: b3 8c 6c 00 add s9, s9, t1 +8000619c: 13 cc fc ff not s8, s9 +800061a0: 13 5c fc 41 srai s8, s8, 31 +800061a4: 33 fc 8c 01 and s8, s9, s8 +800061a8: 6f f0 0f d0 j -2816 +800061ac: 13 87 08 00 mv a4, a7 +800061b0: 6f f0 4f a5 j -3500 +800061b4: 83 27 c1 00 lw a5, 12(sp) +800061b8: 03 a3 07 00 lw t1, 0(a5) +800061bc: 93 87 47 00 addi a5, a5, 4 +800061c0: 63 54 03 00 bgez t1, 8 +800061c4: 13 03 f0 ff addi t1, zero, -1 +800061c8: 83 44 14 00 lbu s1, 1(s0) +800061cc: 23 26 f1 00 sw a5, 12(sp) +800061d0: 13 84 06 00 mv s0, a3 +800061d4: 6f d0 8f ec j -10552 +800061d8: 93 07 c0 00 addi a5, zero, 12 +800061dc: 23 a0 fa 00 sw a5, 0(s5) +800061e0: 93 07 f0 ff addi a5, zero, -1 +800061e4: 23 22 f1 00 sw a5, 4(sp) +800061e8: 6f d0 9f 86 j -10136 +800061ec: 83 57 cb 00 lhu a5, 12(s6) +800061f0: 13 e7 07 04 ori a4, a5, 64 +800061f4: 93 07 07 00 mv a5, a4 +800061f8: 23 16 eb 00 sh a4, 12(s6) +800061fc: 6f d0 9f 84 j -10168 +80006200: 93 07 20 00 addi a5, zero, 2 +80006204: 23 22 f1 04 sw a5, 68(sp) +80006208: 6f d0 1f d0 j -8960 + +8000620c __register_exitproc: +8000620c: b7 87 01 80 lui a5, 524312 +80006210: 03 a7 07 b9 lw a4, -1136(a5) +80006214: 83 27 87 14 lw a5, 328(a4) +80006218: 63 8c 07 04 beqz a5, 88 +8000621c: 03 a7 47 00 lw a4, 4(a5) +80006220: 13 08 f0 01 addi a6, zero, 31 +80006224: 63 4e e8 06 blt a6, a4, 124 +80006228: 13 18 27 00 slli a6, a4, 2 +8000622c: 63 06 05 02 beqz a0, 44 +80006230: 33 83 07 01 add t1, a5, a6 +80006234: 23 24 c3 08 sw a2, 136(t1) +80006238: 83 a8 87 18 lw a7, 392(a5) +8000623c: 13 06 10 00 addi a2, zero, 1 +80006240: 33 16 e6 00 sll a2, a2, a4 +80006244: b3 e8 c8 00 or a7, a7, a2 +80006248: 23 a4 17 19 sw a7, 392(a5) +8000624c: 23 24 d3 10 sw a3, 264(t1) +80006250: 93 06 20 00 addi a3, zero, 2 +80006254: 63 04 d5 02 beq a0, a3, 40 +80006258: 13 07 17 00 addi a4, a4, 1 +8000625c: 23 a2 e7 00 sw a4, 4(a5) +80006260: b3 87 07 01 add a5, a5, a6 +80006264: 23 a4 b7 00 sw a1, 8(a5) +80006268: 13 05 00 00 mv a0, zero +8000626c: 67 80 00 00 ret +80006270: 93 07 c7 14 addi a5, a4, 332 +80006274: 23 24 f7 14 sw a5, 328(a4) +80006278: 6f f0 5f fa j -92 +8000627c: 83 a6 c7 18 lw a3, 396(a5) +80006280: 13 07 17 00 addi a4, a4, 1 +80006284: 23 a2 e7 00 sw a4, 4(a5) +80006288: 33 e6 c6 00 or a2, a3, a2 +8000628c: 23 a6 c7 18 sw a2, 396(a5) +80006290: b3 87 07 01 add a5, a5, a6 +80006294: 23 a4 b7 00 sw a1, 8(a5) +80006298: 13 05 00 00 mv a0, zero +8000629c: 67 80 00 00 ret +800062a0: 13 05 f0 ff addi a0, zero, -1 +800062a4: 67 80 00 00 ret + +800062a8 __call_exitprocs: +800062a8: 13 01 01 fd addi sp, sp, -48 +800062ac: b7 87 01 80 lui a5, 524312 +800062b0: 23 2c 41 01 sw s4, 24(sp) +800062b4: 03 aa 07 b9 lw s4, -1136(a5) +800062b8: 23 20 21 03 sw s2, 32(sp) +800062bc: 23 26 11 02 sw ra, 44(sp) +800062c0: 03 29 8a 14 lw s2, 328(s4) +800062c4: 23 24 81 02 sw s0, 40(sp) +800062c8: 23 22 91 02 sw s1, 36(sp) +800062cc: 23 2e 31 01 sw s3, 28(sp) +800062d0: 23 2a 51 01 sw s5, 20(sp) +800062d4: 23 28 61 01 sw s6, 16(sp) +800062d8: 23 26 71 01 sw s7, 12(sp) +800062dc: 23 24 81 01 sw s8, 8(sp) +800062e0: 63 00 09 04 beqz s2, 64 +800062e4: 13 0b 05 00 mv s6, a0 +800062e8: 93 8b 05 00 mv s7, a1 +800062ec: 93 0a 10 00 addi s5, zero, 1 +800062f0: 93 09 f0 ff addi s3, zero, -1 +800062f4: 83 24 49 00 lw s1, 4(s2) +800062f8: 13 84 f4 ff addi s0, s1, -1 +800062fc: 63 42 04 02 bltz s0, 36 +80006300: 93 94 24 00 slli s1, s1, 2 +80006304: b3 04 99 00 add s1, s2, s1 +80006308: 63 84 0b 04 beqz s7, 72 +8000630c: 83 a7 44 10 lw a5, 260(s1) +80006310: 63 80 77 05 beq a5, s7, 64 +80006314: 13 04 f4 ff addi s0, s0, -1 +80006318: 93 84 c4 ff addi s1, s1, -4 +8000631c: e3 16 34 ff bne s0, s3, -20 +80006320: 83 20 c1 02 lw ra, 44(sp) +80006324: 03 24 81 02 lw s0, 40(sp) +80006328: 83 24 41 02 lw s1, 36(sp) +8000632c: 03 29 01 02 lw s2, 32(sp) +80006330: 83 29 c1 01 lw s3, 28(sp) +80006334: 03 2a 81 01 lw s4, 24(sp) +80006338: 83 2a 41 01 lw s5, 20(sp) +8000633c: 03 2b 01 01 lw s6, 16(sp) +80006340: 83 2b c1 00 lw s7, 12(sp) +80006344: 03 2c 81 00 lw s8, 8(sp) +80006348: 13 01 01 03 addi sp, sp, 48 +8000634c: 67 80 00 00 ret +80006350: 83 27 49 00 lw a5, 4(s2) +80006354: 83 a6 44 00 lw a3, 4(s1) +80006358: 93 87 f7 ff addi a5, a5, -1 +8000635c: 63 8e 87 04 beq a5, s0, 92 +80006360: 23 a2 04 00 sw zero, 4(s1) +80006364: e3 88 06 fa beqz a3, -80 +80006368: 83 27 89 18 lw a5, 392(s2) +8000636c: 33 97 8a 00 sll a4, s5, s0 +80006370: 03 2c 49 00 lw s8, 4(s2) +80006374: b3 77 f7 00 and a5, a4, a5 +80006378: 63 92 07 02 bnez a5, 36 +8000637c: e7 80 06 00 jalr a3 +80006380: 03 27 49 00 lw a4, 4(s2) +80006384: 83 27 8a 14 lw a5, 328(s4) +80006388: 63 14 87 01 bne a4, s8, 8 +8000638c: e3 04 f9 f8 beq s2, a5, -120 +80006390: e3 88 07 f8 beqz a5, -112 +80006394: 13 89 07 00 mv s2, a5 +80006398: 6f f0 df f5 j -164 +8000639c: 83 27 c9 18 lw a5, 396(s2) +800063a0: 83 a5 44 08 lw a1, 132(s1) +800063a4: 33 77 f7 00 and a4, a4, a5 +800063a8: 63 1c 07 00 bnez a4, 24 +800063ac: 13 05 0b 00 mv a0, s6 +800063b0: e7 80 06 00 jalr a3 +800063b4: 6f f0 df fc j -52 +800063b8: 23 22 89 00 sw s0, 4(s2) +800063bc: 6f f0 9f fa j -88 +800063c0: 13 85 05 00 mv a0, a1 +800063c4: e7 80 06 00 jalr a3 +800063c8: 6f f0 9f fb j -72 + +800063cc _malloc_trim_r: +800063cc: 13 01 01 fe addi sp, sp, -32 +800063d0: 23 26 31 01 sw s3, 12(sp) +800063d4: b7 79 01 80 lui s3, 524311 +800063d8: 23 2c 81 00 sw s0, 24(sp) +800063dc: 23 2a 91 00 sw s1, 20(sp) +800063e0: 23 28 21 01 sw s2, 16(sp) +800063e4: 23 24 41 01 sw s4, 8(sp) +800063e8: 23 2e 11 00 sw ra, 28(sp) +800063ec: 13 8a 05 00 mv s4, a1 +800063f0: 13 09 05 00 mv s2, a0 +800063f4: 93 89 09 60 addi s3, s3, 1536 +800063f8: ef 30 50 07 jal 14452 +800063fc: 03 a7 89 00 lw a4, 8(s3) +80006400: b7 17 00 00 lui a5, 1 +80006404: 13 84 f7 fe addi s0, a5, -17 +80006408: 83 24 47 00 lw s1, 4(a4) +8000640c: 33 04 44 41 sub s0, s0, s4 +80006410: 93 f4 c4 ff andi s1, s1, -4 +80006414: 33 04 94 00 add s0, s0, s1 +80006418: 13 54 c4 00 srli s0, s0, 12 +8000641c: 13 04 f4 ff addi s0, s0, -1 +80006420: 13 14 c4 00 slli s0, s0, 12 +80006424: 63 4e f4 00 blt s0, a5, 28 +80006428: 93 05 00 00 mv a1, zero +8000642c: 13 05 09 00 mv a0, s2 +80006430: ef 40 50 24 jal 19012 +80006434: 83 a7 89 00 lw a5, 8(s3) +80006438: b3 87 97 00 add a5, a5, s1 +8000643c: 63 08 f5 02 beq a0, a5, 48 +80006440: 13 05 09 00 mv a0, s2 +80006444: ef 30 d0 02 jal 14380 +80006448: 83 20 c1 01 lw ra, 28(sp) +8000644c: 03 24 81 01 lw s0, 24(sp) +80006450: 83 24 41 01 lw s1, 20(sp) +80006454: 03 29 01 01 lw s2, 16(sp) +80006458: 83 29 c1 00 lw s3, 12(sp) +8000645c: 03 2a 81 00 lw s4, 8(sp) +80006460: 13 05 00 00 mv a0, zero +80006464: 13 01 01 02 addi sp, sp, 32 +80006468: 67 80 00 00 ret +8000646c: b3 05 80 40 neg a1, s0 +80006470: 13 05 09 00 mv a0, s2 +80006474: ef 40 10 20 jal 18944 +80006478: 93 07 f0 ff addi a5, zero, -1 +8000647c: 63 0a f5 04 beq a0, a5, 84 +80006480: b7 87 01 80 lui a5, 524312 +80006484: 93 87 47 bb addi a5, a5, -1100 +80006488: 03 a7 07 00 lw a4, 0(a5) +8000648c: 83 a6 89 00 lw a3, 8(s3) +80006490: b3 84 84 40 sub s1, s1, s0 +80006494: 93 e4 14 00 ori s1, s1, 1 +80006498: 33 04 87 40 sub s0, a4, s0 +8000649c: 13 05 09 00 mv a0, s2 +800064a0: 23 a2 96 00 sw s1, 4(a3) +800064a4: 23 a0 87 00 sw s0, 0(a5) +800064a8: ef 30 80 7c jal 14280 +800064ac: 83 20 c1 01 lw ra, 28(sp) +800064b0: 03 24 81 01 lw s0, 24(sp) +800064b4: 83 24 41 01 lw s1, 20(sp) +800064b8: 03 29 01 01 lw s2, 16(sp) +800064bc: 83 29 c1 00 lw s3, 12(sp) +800064c0: 03 2a 81 00 lw s4, 8(sp) +800064c4: 13 05 10 00 addi a0, zero, 1 +800064c8: 13 01 01 02 addi sp, sp, 32 +800064cc: 67 80 00 00 ret +800064d0: 93 05 00 00 mv a1, zero +800064d4: 13 05 09 00 mv a0, s2 +800064d8: ef 40 d0 19 jal 18844 +800064dc: 03 a7 89 00 lw a4, 8(s3) +800064e0: 93 06 f0 00 addi a3, zero, 15 +800064e4: b3 07 e5 40 sub a5, a0, a4 +800064e8: e3 dc f6 f4 bge a3, a5, -168 +800064ec: b7 86 01 80 lui a3, 524312 +800064f0: 83 a6 06 ba lw a3, -1120(a3) +800064f4: 93 e7 17 00 ori a5, a5, 1 +800064f8: 23 22 f7 00 sw a5, 4(a4) +800064fc: 33 05 d5 40 sub a0, a0, a3 +80006500: b7 86 01 80 lui a3, 524312 +80006504: 23 aa a6 ba sw a0, -1100(a3) +80006508: 6f f0 9f f3 j -200 + +8000650c _free_r: +8000650c: 63 8a 05 12 beqz a1, 308 +80006510: 13 01 01 ff addi sp, sp, -16 +80006514: 23 24 81 00 sw s0, 8(sp) +80006518: 23 22 91 00 sw s1, 4(sp) +8000651c: 13 84 05 00 mv s0, a1 +80006520: 93 04 05 00 mv s1, a0 +80006524: 23 26 11 00 sw ra, 12(sp) +80006528: ef 30 40 74 jal 14148 +8000652c: 03 28 c4 ff lw a6, -4(s0) +80006530: 13 07 84 ff addi a4, s0, -8 +80006534: b7 75 01 80 lui a1, 524311 +80006538: 93 77 e8 ff andi a5, a6, -2 +8000653c: 33 06 f7 00 add a2, a4, a5 +80006540: 93 85 05 60 addi a1, a1, 1536 +80006544: 83 26 46 00 lw a3, 4(a2) +80006548: 03 a5 85 00 lw a0, 8(a1) +8000654c: 93 f6 c6 ff andi a3, a3, -4 +80006550: 63 0a c5 1a beq a0, a2, 436 +80006554: 23 22 d6 00 sw a3, 4(a2) +80006558: 13 78 18 00 andi a6, a6, 1 +8000655c: 33 05 d6 00 add a0, a2, a3 +80006560: 63 10 08 0a bnez a6, 160 +80006564: 03 23 84 ff lw t1, -8(s0) +80006568: 03 28 45 00 lw a6, 4(a0) +8000656c: 37 75 01 80 lui a0, 524311 +80006570: 33 07 67 40 sub a4, a4, t1 +80006574: 83 28 87 00 lw a7, 8(a4) +80006578: 13 05 85 60 addi a0, a0, 1544 +8000657c: b3 87 67 00 add a5, a5, t1 +80006580: 13 78 18 00 andi a6, a6, 1 +80006584: 63 80 a8 14 beq a7, a0, 320 +80006588: 03 23 c7 00 lw t1, 12(a4) +8000658c: 23 a6 68 00 sw t1, 12(a7) +80006590: 23 24 13 01 sw a7, 8(t1) +80006594: 63 04 08 1e beqz a6, 488 +80006598: 93 e6 17 00 ori a3, a5, 1 +8000659c: 23 22 d7 00 sw a3, 4(a4) +800065a0: 23 20 f6 00 sw a5, 0(a2) +800065a4: 93 06 f0 1f addi a3, zero, 511 +800065a8: 63 e8 f6 0a bltu a3, a5, 176 +800065ac: 93 f6 87 ff andi a3, a5, -8 +800065b0: 93 86 86 00 addi a3, a3, 8 +800065b4: 03 a5 45 00 lw a0, 4(a1) +800065b8: b3 86 d5 00 add a3, a1, a3 +800065bc: 03 a6 06 00 lw a2, 0(a3) +800065c0: 13 d8 57 00 srli a6, a5, 5 +800065c4: 93 07 10 00 addi a5, zero, 1 +800065c8: b3 97 07 01 sll a5, a5, a6 +800065cc: b3 e7 a7 00 or a5, a5, a0 +800065d0: 13 85 86 ff addi a0, a3, -8 +800065d4: 23 26 a7 00 sw a0, 12(a4) +800065d8: 23 24 c7 00 sw a2, 8(a4) +800065dc: 23 a2 f5 00 sw a5, 4(a1) +800065e0: 23 a0 e6 00 sw a4, 0(a3) +800065e4: 23 26 e6 00 sw a4, 12(a2) +800065e8: 03 24 81 00 lw s0, 8(sp) +800065ec: 83 20 c1 00 lw ra, 12(sp) +800065f0: 13 85 04 00 mv a0, s1 +800065f4: 83 24 41 00 lw s1, 4(sp) +800065f8: 13 01 01 01 addi sp, sp, 16 +800065fc: 6f 30 40 67 j 13940 +80006600: 03 25 45 00 lw a0, 4(a0) +80006604: 13 75 15 00 andi a0, a0, 1 +80006608: 63 1e 05 02 bnez a0, 60 +8000660c: 37 75 01 80 lui a0, 524311 +80006610: b3 87 d7 00 add a5, a5, a3 +80006614: 13 05 85 60 addi a0, a0, 1544 +80006618: 83 26 86 00 lw a3, 8(a2) +8000661c: 93 e8 17 00 ori a7, a5, 1 +80006620: 33 08 f7 00 add a6, a4, a5 +80006624: 63 88 a6 16 beq a3, a0, 368 +80006628: 03 26 c6 00 lw a2, 12(a2) +8000662c: 23 a6 c6 00 sw a2, 12(a3) +80006630: 23 24 d6 00 sw a3, 8(a2) +80006634: 23 22 17 01 sw a7, 4(a4) +80006638: 23 20 f8 00 sw a5, 0(a6) +8000663c: 6f f0 9f f6 j -152 +80006640: 67 80 00 00 ret +80006644: 93 e6 17 00 ori a3, a5, 1 +80006648: 23 2e d4 fe sw a3, -4(s0) +8000664c: 23 20 f6 00 sw a5, 0(a2) +80006650: 93 06 f0 1f addi a3, zero, 511 +80006654: e3 fc f6 f4 bgeu a3, a5, -168 +80006658: 93 d6 97 00 srli a3, a5, 9 +8000665c: 13 06 40 00 addi a2, zero, 4 +80006660: 63 6c d6 0e bltu a2, a3, 248 +80006664: 93 d6 67 00 srli a3, a5, 6 +80006668: 13 88 96 03 addi a6, a3, 57 +8000666c: 13 86 86 03 addi a2, a3, 56 +80006670: 13 18 38 00 slli a6, a6, 3 +80006674: 33 88 05 01 add a6, a1, a6 +80006678: 83 26 08 00 lw a3, 0(a6) +8000667c: 13 08 88 ff addi a6, a6, -8 +80006680: 63 08 d8 12 beq a6, a3, 304 +80006684: 03 a6 46 00 lw a2, 4(a3) +80006688: 13 76 c6 ff andi a2, a2, -4 +8000668c: 63 f6 c7 00 bgeu a5, a2, 12 +80006690: 83 a6 86 00 lw a3, 8(a3) +80006694: e3 18 d8 fe bne a6, a3, -16 +80006698: 03 a8 c6 00 lw a6, 12(a3) +8000669c: 23 26 07 01 sw a6, 12(a4) +800066a0: 23 24 d7 00 sw a3, 8(a4) +800066a4: 03 24 81 00 lw s0, 8(sp) +800066a8: 83 20 c1 00 lw ra, 12(sp) +800066ac: 23 24 e8 00 sw a4, 8(a6) +800066b0: 13 85 04 00 mv a0, s1 +800066b4: 83 24 41 00 lw s1, 4(sp) +800066b8: 23 a6 e6 00 sw a4, 12(a3) +800066bc: 13 01 01 01 addi sp, sp, 16 +800066c0: 6f 30 00 5b j 13744 +800066c4: 63 16 08 14 bnez a6, 332 +800066c8: 83 25 c6 00 lw a1, 12(a2) +800066cc: 03 26 86 00 lw a2, 8(a2) +800066d0: b3 87 f6 00 add a5, a3, a5 +800066d4: 03 24 81 00 lw s0, 8(sp) +800066d8: 23 26 b6 00 sw a1, 12(a2) +800066dc: 23 a4 c5 00 sw a2, 8(a1) +800066e0: 93 e6 17 00 ori a3, a5, 1 +800066e4: 83 20 c1 00 lw ra, 12(sp) +800066e8: 23 22 d7 00 sw a3, 4(a4) +800066ec: 13 85 04 00 mv a0, s1 +800066f0: 33 07 f7 00 add a4, a4, a5 +800066f4: 83 24 41 00 lw s1, 4(sp) +800066f8: 23 20 f7 00 sw a5, 0(a4) +800066fc: 13 01 01 01 addi sp, sp, 16 +80006700: 6f 30 00 57 j 13680 +80006704: 13 78 18 00 andi a6, a6, 1 +80006708: b3 87 d7 00 add a5, a5, a3 +8000670c: 63 10 08 02 bnez a6, 32 +80006710: 03 25 84 ff lw a0, -8(s0) +80006714: 33 07 a7 40 sub a4, a4, a0 +80006718: 83 26 c7 00 lw a3, 12(a4) +8000671c: 03 26 87 00 lw a2, 8(a4) +80006720: b3 87 a7 00 add a5, a5, a0 +80006724: 23 26 d6 00 sw a3, 12(a2) +80006728: 23 a4 c6 00 sw a2, 8(a3) +8000672c: b7 86 01 80 lui a3, 524312 +80006730: 13 e6 17 00 ori a2, a5, 1 +80006734: 83 a6 46 ba lw a3, -1116(a3) +80006738: 23 22 c7 00 sw a2, 4(a4) +8000673c: 23 a4 e5 00 sw a4, 8(a1) +80006740: e3 e4 d7 ea bltu a5, a3, -344 +80006744: b7 87 01 80 lui a5, 524312 +80006748: 83 a5 07 bb lw a1, -1104(a5) +8000674c: 13 85 04 00 mv a0, s1 +80006750: ef f0 df c7 jal -900 +80006754: 6f f0 5f e9 j -364 +80006758: 13 06 40 01 addi a2, zero, 20 +8000675c: 63 74 d6 02 bgeu a2, a3, 40 +80006760: 13 06 40 05 addi a2, zero, 84 +80006764: 63 64 d6 06 bltu a2, a3, 104 +80006768: 93 d6 c7 00 srli a3, a5, 12 +8000676c: 13 88 f6 06 addi a6, a3, 111 +80006770: 13 86 e6 06 addi a2, a3, 110 +80006774: 13 18 38 00 slli a6, a6, 3 +80006778: 6f f0 df ef j -260 +8000677c: b3 87 d7 00 add a5, a5, a3 +80006780: 6f f0 9f e9 j -360 +80006784: 13 88 c6 05 addi a6, a3, 92 +80006788: 13 86 b6 05 addi a2, a3, 91 +8000678c: 13 18 38 00 slli a6, a6, 3 +80006790: 6f f0 5f ee j -284 +80006794: 23 aa e5 00 sw a4, 20(a1) +80006798: 23 a8 e5 00 sw a4, 16(a1) +8000679c: 23 26 a7 00 sw a0, 12(a4) +800067a0: 23 24 a7 00 sw a0, 8(a4) +800067a4: 23 22 17 01 sw a7, 4(a4) +800067a8: 23 20 f8 00 sw a5, 0(a6) +800067ac: 6f f0 df e3 j -452 +800067b0: 03 a5 45 00 lw a0, 4(a1) +800067b4: 13 56 26 40 srai a2, a2, 2 +800067b8: 93 07 10 00 addi a5, zero, 1 +800067bc: 33 96 c7 00 sll a2, a5, a2 +800067c0: 33 66 a6 00 or a2, a2, a0 +800067c4: 23 a2 c5 00 sw a2, 4(a1) +800067c8: 6f f0 5f ed j -300 +800067cc: 13 06 40 15 addi a2, zero, 340 +800067d0: 63 6c d6 00 bltu a2, a3, 24 +800067d4: 93 d6 f7 00 srli a3, a5, 15 +800067d8: 13 88 86 07 addi a6, a3, 120 +800067dc: 13 86 76 07 addi a2, a3, 119 +800067e0: 13 18 38 00 slli a6, a6, 3 +800067e4: 6f f0 1f e9 j -368 +800067e8: 13 06 40 55 addi a2, zero, 1364 +800067ec: 63 6c d6 00 bltu a2, a3, 24 +800067f0: 93 d6 27 01 srli a3, a5, 18 +800067f4: 13 88 d6 07 addi a6, a3, 125 +800067f8: 13 86 c6 07 addi a2, a3, 124 +800067fc: 13 18 38 00 slli a6, a6, 3 +80006800: 6f f0 5f e7 j -396 +80006804: 13 08 80 3f addi a6, zero, 1016 +80006808: 13 06 e0 07 addi a2, zero, 126 +8000680c: 6f f0 9f e6 j -408 +80006810: 93 e6 17 00 ori a3, a5, 1 +80006814: 23 22 d7 00 sw a3, 4(a4) +80006818: 23 20 f6 00 sw a5, 0(a2) +8000681c: 6f f0 df dc j -564 + +80006820 eshdn1: +80006820: 93 06 45 00 addi a3, a0, 4 +80006824: 93 07 00 00 mv a5, zero +80006828: 13 05 a5 01 addi a0, a0, 26 +8000682c: 37 88 ff ff lui a6, 1048568 +80006830: 6f 00 c0 01 j 28 +80006834: 93 97 17 00 slli a5, a5, 1 +80006838: 23 90 e6 00 sh a4, 0(a3) +8000683c: 93 97 07 01 slli a5, a5, 16 +80006840: 93 86 26 00 addi a3, a3, 2 +80006844: 93 d7 07 01 srli a5, a5, 16 +80006848: 63 0e d5 02 beq a0, a3, 60 +8000684c: 03 d7 06 00 lhu a4, 0(a3) +80006850: 13 76 17 00 andi a2, a4, 1 +80006854: 63 04 06 00 beqz a2, 8 +80006858: 93 e7 17 00 ori a5, a5, 1 +8000685c: 13 57 17 00 srli a4, a4, 1 +80006860: 13 f6 27 00 andi a2, a5, 2 +80006864: b3 65 07 01 or a1, a4, a6 +80006868: e3 06 06 fc beqz a2, -52 +8000686c: 93 97 17 00 slli a5, a5, 1 +80006870: 23 90 b6 00 sh a1, 0(a3) +80006874: 93 97 07 01 slli a5, a5, 16 +80006878: 93 86 26 00 addi a3, a3, 2 +8000687c: 93 d7 07 01 srli a5, a5, 16 +80006880: e3 16 d5 fc bne a0, a3, -52 +80006884: 67 80 00 00 ret + +80006888 eshup1: +80006888: 93 06 85 01 addi a3, a0, 24 +8000688c: 13 07 00 00 mv a4, zero +80006890: 13 05 25 00 addi a0, a0, 2 +80006894: 6f 00 c0 01 j 28 +80006898: 13 17 17 00 slli a4, a4, 1 +8000689c: 23 90 f6 00 sh a5, 0(a3) +800068a0: 13 17 07 01 slli a4, a4, 16 +800068a4: 93 86 e6 ff addi a3, a3, -2 +800068a8: 13 57 07 01 srli a4, a4, 16 +800068ac: 63 04 d5 04 beq a0, a3, 72 +800068b0: 83 d7 06 00 lhu a5, 0(a3) +800068b4: 13 96 07 01 slli a2, a5, 16 +800068b8: 13 56 06 41 srai a2, a2, 16 +800068bc: 93 97 17 00 slli a5, a5, 1 +800068c0: 63 54 06 00 bgez a2, 8 +800068c4: 13 67 17 00 ori a4, a4, 1 +800068c8: 93 97 07 01 slli a5, a5, 16 +800068cc: 93 d7 07 01 srli a5, a5, 16 +800068d0: 13 76 27 00 andi a2, a4, 2 +800068d4: 93 e5 17 00 ori a1, a5, 1 +800068d8: e3 00 06 fc beqz a2, -64 +800068dc: 13 17 17 00 slli a4, a4, 1 +800068e0: 23 90 b6 00 sh a1, 0(a3) +800068e4: 13 17 07 01 slli a4, a4, 16 +800068e8: 93 86 e6 ff addi a3, a3, -2 +800068ec: 13 57 07 01 srli a4, a4, 16 +800068f0: e3 10 d5 fc bne a0, a3, -64 +800068f4: 67 80 00 00 ret + +800068f8 m16m: +800068f8: 13 01 01 fe addi sp, sp, -32 +800068fc: 37 0e 01 00 lui t3, 16 +80006900: 23 1d 01 00 sh zero, 26(sp) +80006904: 23 1e 01 00 sh zero, 28(sp) +80006908: 93 85 85 01 addi a1, a1, 24 +8000690c: 93 07 c1 01 addi a5, sp, 28 +80006910: 13 08 81 00 addi a6, sp, 8 +80006914: 13 0e fe ff addi t3, t3, -1 +80006918: 03 d7 05 00 lhu a4, 0(a1) +8000691c: 93 87 e7 ff addi a5, a5, -2 +80006920: 93 85 e5 ff addi a1, a1, -2 +80006924: 63 18 07 02 bnez a4, 48 +80006928: 23 9f 07 fe sh zero, -2(a5) +8000692c: e3 96 07 ff bne a5, a6, -20 +80006930: 13 06 46 00 addi a2, a2, 4 +80006934: 93 06 e1 01 addi a3, sp, 30 +80006938: 03 d7 07 00 lhu a4, 0(a5) +8000693c: 93 87 27 00 addi a5, a5, 2 +80006940: 13 06 26 00 addi a2, a2, 2 +80006944: 23 1f e6 fe sh a4, -2(a2) +80006948: e3 98 d7 fe bne a5, a3, -16 +8000694c: 13 01 01 02 addi sp, sp, 32 +80006950: 67 80 00 00 ret +80006954: 33 07 a7 02 mul a4, a4, a0 +80006958: 83 d8 27 00 lhu a7, 2(a5) +8000695c: 03 d3 07 00 lhu t1, 0(a5) +80006960: b3 76 c7 01 and a3, a4, t3 +80006964: b3 86 16 01 add a3, a3, a7 +80006968: 13 57 07 01 srli a4, a4, 16 +8000696c: 93 d8 06 01 srli a7, a3, 16 +80006970: 33 07 67 00 add a4, a4, t1 +80006974: 33 07 17 01 add a4, a4, a7 +80006978: 93 58 07 01 srli a7, a4, 16 +8000697c: 23 91 d7 00 sh a3, 2(a5) +80006980: 23 90 e7 00 sh a4, 0(a5) +80006984: 23 9f 17 ff sh a7, -2(a5) +80006988: e3 98 07 f9 bne a5, a6, -112 +8000698c: 6f f0 5f fa j -92 + +80006990 eisnan.part.0: +80006990: 13 07 25 01 addi a4, a0, 18 +80006994: 83 57 05 00 lhu a5, 0(a0) +80006998: 13 05 25 00 addi a0, a0, 2 +8000699c: 63 98 07 00 bnez a5, 16 +800069a0: e3 1a e5 fe bne a0, a4, -12 +800069a4: 13 05 00 00 mv a0, zero +800069a8: 67 80 00 00 ret +800069ac: 13 05 10 00 addi a0, zero, 1 +800069b0: 67 80 00 00 ret + +800069b4 eneg: +800069b4: 13 01 01 ff addi sp, sp, -16 +800069b8: 23 22 91 00 sw s1, 4(sp) +800069bc: 83 54 25 01 lhu s1, 18(a0) +800069c0: 23 24 81 00 sw s0, 8(sp) +800069c4: 23 26 11 00 sw ra, 12(sp) +800069c8: 93 c7 f4 ff not a5, s1 +800069cc: 13 97 17 01 slli a4, a5, 17 +800069d0: 13 04 05 00 mv s0, a0 +800069d4: 63 16 07 00 bnez a4, 12 +800069d8: ef f0 9f fb jal -72 +800069dc: 63 18 05 00 bnez a0, 16 +800069e0: b7 87 ff ff lui a5, 1048568 +800069e4: b3 c4 f4 00 xor s1, s1, a5 +800069e8: 23 19 94 00 sh s1, 18(s0) +800069ec: 83 20 c1 00 lw ra, 12(sp) +800069f0: 03 24 81 00 lw s0, 8(sp) +800069f4: 83 24 41 00 lw s1, 4(sp) +800069f8: 13 01 01 01 addi sp, sp, 16 +800069fc: 67 80 00 00 ret + +80006a00 eisneg: +80006a00: 13 01 01 ff addi sp, sp, -16 +80006a04: 23 24 81 00 sw s0, 8(sp) +80006a08: 03 54 25 01 lhu s0, 18(a0) +80006a0c: 23 26 11 00 sw ra, 12(sp) +80006a10: 93 47 f4 ff not a5, s0 +80006a14: 13 97 17 01 slli a4, a5, 17 +80006a18: 63 1a 07 00 bnez a4, 20 +80006a1c: ef f0 5f f7 jal -140 +80006a20: 93 07 05 00 mv a5, a0 +80006a24: 13 05 00 00 mv a0, zero +80006a28: 63 94 07 00 bnez a5, 8 +80006a2c: 13 55 f4 00 srli a0, s0, 15 +80006a30: 83 20 c1 00 lw ra, 12(sp) +80006a34: 03 24 81 00 lw s0, 8(sp) +80006a38: 13 01 01 01 addi sp, sp, 16 +80006a3c: 67 80 00 00 ret + +80006a40 emovi: +80006a40: 83 57 25 01 lhu a5, 18(a0) +80006a44: 13 01 01 fd addi sp, sp, -48 +80006a48: 23 24 81 02 sw s0, 40(sp) +80006a4c: 93 d7 f7 00 srli a5, a5, 15 +80006a50: 23 22 91 02 sw s1, 36(sp) +80006a54: 23 26 11 02 sw ra, 44(sp) +80006a58: 23 20 21 03 sw s2, 32(sp) +80006a5c: 23 2e 31 01 sw s3, 28(sp) +80006a60: b3 07 f0 40 neg a5, a5 +80006a64: 23 90 f5 00 sh a5, 0(a1) +80006a68: 83 57 25 01 lhu a5, 18(a0) +80006a6c: 37 87 00 00 lui a4, 8 +80006a70: 13 07 f7 ff addi a4, a4, -1 +80006a74: b3 77 f7 00 and a5, a4, a5 +80006a78: 23 91 f5 00 sh a5, 2(a1) +80006a7c: 93 04 05 00 mv s1, a0 +80006a80: 13 04 05 01 addi s0, a0, 16 +80006a84: 63 82 e7 04 beq a5, a4, 68 +80006a88: 93 87 65 00 addi a5, a1, 6 +80006a8c: 23 92 05 00 sh zero, 4(a1) +80006a90: 13 05 e5 ff addi a0, a0, -2 +80006a94: 03 57 04 00 lhu a4, 0(s0) +80006a98: 13 04 e4 ff addi s0, s0, -2 +80006a9c: 93 87 27 00 addi a5, a5, 2 +80006aa0: 23 9f e7 fe sh a4, -2(a5) +80006aa4: e3 18 85 fe bne a0, s0, -16 +80006aa8: 23 9c 05 00 sh zero, 24(a1) +80006aac: 83 20 c1 02 lw ra, 44(sp) +80006ab0: 03 24 81 02 lw s0, 40(sp) +80006ab4: 83 24 41 02 lw s1, 36(sp) +80006ab8: 03 29 01 02 lw s2, 32(sp) +80006abc: 83 29 c1 01 lw s3, 28(sp) +80006ac0: 13 01 01 03 addi sp, sp, 48 +80006ac4: 67 80 00 00 ret +80006ac8: 03 57 25 01 lhu a4, 18(a0) +80006acc: 13 89 45 00 addi s2, a1, 4 +80006ad0: 33 f7 e7 00 and a4, a5, a4 +80006ad4: 63 1c f7 02 bne a4, a5, 56 +80006ad8: 23 26 b1 00 sw a1, 12(sp) +80006adc: ef f0 5f eb jal -332 +80006ae0: 83 25 c1 00 lw a1, 12(sp) +80006ae4: 63 04 05 02 beqz a0, 40 +80006ae8: 93 87 65 00 addi a5, a1, 6 +80006aec: 23 92 05 00 sh zero, 4(a1) +80006af0: 13 85 c4 ff addi a0, s1, -4 +80006af4: 03 57 04 00 lhu a4, 0(s0) +80006af8: 13 04 e4 ff addi s0, s0, -2 +80006afc: 93 87 27 00 addi a5, a5, 2 +80006b00: 23 9f e7 fe sh a4, -2(a5) +80006b04: e3 18 85 fe bne a0, s0, -16 +80006b08: 6f f0 5f fa j -92 +80006b0c: 93 89 a5 01 addi s3, a1, 26 +80006b10: 13 09 29 00 addi s2, s2, 2 +80006b14: 23 1f 09 fe sh zero, -2(s2) +80006b18: e3 9c 29 ff bne s3, s2, -8 +80006b1c: 83 20 c1 02 lw ra, 44(sp) +80006b20: 03 24 81 02 lw s0, 40(sp) +80006b24: 83 24 41 02 lw s1, 36(sp) +80006b28: 03 29 01 02 lw s2, 32(sp) +80006b2c: 83 29 c1 01 lw s3, 28(sp) +80006b30: 13 01 01 03 addi sp, sp, 48 +80006b34: 67 80 00 00 ret + +80006b38 ecmp: +80006b38: 83 57 25 01 lhu a5, 18(a0) +80006b3c: 13 01 01 fb addi sp, sp, -80 +80006b40: 23 24 81 04 sw s0, 72(sp) +80006b44: 93 c7 f7 ff not a5, a5 +80006b48: 23 22 91 04 sw s1, 68(sp) +80006b4c: 23 26 11 04 sw ra, 76(sp) +80006b50: 13 97 17 01 slli a4, a5, 17 +80006b54: 93 04 05 00 mv s1, a0 +80006b58: 13 84 05 00 mv s0, a1 +80006b5c: 63 16 07 00 bnez a4, 12 +80006b60: ef f0 1f e3 jal -464 +80006b64: 63 12 05 08 bnez a0, 132 +80006b68: 83 57 24 01 lhu a5, 18(s0) +80006b6c: 93 c7 f7 ff not a5, a5 +80006b70: 13 97 17 01 slli a4, a5, 17 +80006b74: 63 04 07 06 beqz a4, 104 +80006b78: 93 05 81 00 addi a1, sp, 8 +80006b7c: 13 85 04 00 mv a0, s1 +80006b80: ef f0 1f ec jal -320 +80006b84: 93 05 41 02 addi a1, sp, 36 +80006b88: 13 05 04 00 mv a0, s0 +80006b8c: ef f0 5f eb jal -332 +80006b90: 83 55 81 00 lhu a1, 8(sp) +80006b94: 03 55 41 02 lhu a0, 36(sp) +80006b98: 63 0c b5 04 beq a0, a1, 88 +80006b9c: 93 07 a1 00 addi a5, sp, 10 +80006ba0: 13 07 61 02 addi a4, sp, 38 +80006ba4: 13 06 01 02 addi a2, sp, 32 +80006ba8: 83 d6 07 00 lhu a3, 0(a5) +80006bac: 93 87 27 00 addi a5, a5, 2 +80006bb0: 63 9a 06 08 bnez a3, 148 +80006bb4: 83 56 07 00 lhu a3, 0(a4) +80006bb8: 13 07 27 00 addi a4, a4, 2 +80006bbc: 63 94 06 08 bnez a3, 136 +80006bc0: e3 94 c7 fe bne a5, a2, -24 +80006bc4: 13 05 00 00 mv a0, zero +80006bc8: 83 20 c1 04 lw ra, 76(sp) +80006bcc: 03 24 81 04 lw s0, 72(sp) +80006bd0: 83 24 41 04 lw s1, 68(sp) +80006bd4: 13 01 01 05 addi sp, sp, 80 +80006bd8: 67 80 00 00 ret +80006bdc: 13 05 04 00 mv a0, s0 +80006be0: ef f0 1f db jal -592 +80006be4: e3 0a 05 f8 beqz a0, -108 +80006be8: 13 05 e0 ff addi a0, zero, -2 +80006bec: 6f f0 df fd j -36 +80006bf0: 13 35 15 00 seqz a0, a0 +80006bf4: 03 56 a1 00 lhu a2, 10(sp) +80006bf8: 83 56 61 02 lhu a3, 38(sp) +80006bfc: 33 05 a0 40 neg a0, a0 +80006c00: 13 07 a1 00 addi a4, sp, 10 +80006c04: 93 07 61 02 addi a5, sp, 38 +80006c08: 13 75 25 00 andi a0, a0, 2 +80006c0c: 13 05 f5 ff addi a0, a0, -1 +80006c10: 93 05 c1 03 addi a1, sp, 60 +80006c14: 93 87 27 00 addi a5, a5, 2 +80006c18: 13 07 27 00 addi a4, a4, 2 +80006c1c: 63 1e d6 00 bne a2, a3, 28 +80006c20: e3 82 b7 fa beq a5, a1, -92 +80006c24: 03 56 07 00 lhu a2, 0(a4) +80006c28: 83 d6 07 00 lhu a3, 0(a5) +80006c2c: 13 07 27 00 addi a4, a4, 2 +80006c30: 93 87 27 00 addi a5, a5, 2 +80006c34: e3 06 d6 fe beq a2, a3, -20 +80006c38: e3 e8 c6 f8 bltu a3, a2, -112 +80006c3c: 33 05 a0 40 neg a0, a0 +80006c40: 6f f0 9f f8 j -120 +80006c44: 13 05 10 00 addi a0, zero, 1 +80006c48: e3 80 05 f8 beqz a1, -128 +80006c4c: 13 05 f0 ff addi a0, zero, -1 +80006c50: 6f f0 9f f7 j -136 + +80006c54 eisinf.part.0: +80006c54: 13 01 01 ff addi sp, sp, -16 +80006c58: 23 26 11 00 sw ra, 12(sp) +80006c5c: ef f0 5f d3 jal -716 +80006c60: 83 20 c1 00 lw ra, 12(sp) +80006c64: 13 35 15 00 seqz a0, a0 +80006c68: 13 01 01 01 addi sp, sp, 16 +80006c6c: 67 80 00 00 ret + +80006c70 eshift.part.0: +80006c70: 13 01 01 fe addi sp, sp, -32 +80006c74: 23 2c 81 00 sw s0, 24(sp) +80006c78: 23 2a 91 00 sw s1, 20(sp) +80006c7c: 23 2e 11 00 sw ra, 28(sp) +80006c80: 23 28 21 01 sw s2, 16(sp) +80006c84: 23 26 31 01 sw s3, 12(sp) +80006c88: 93 84 05 00 mv s1, a1 +80006c8c: 13 04 05 00 mv s0, a0 +80006c90: 63 c4 05 0a bltz a1, 168 +80006c94: 93 07 f0 00 addi a5, zero, 15 +80006c98: 13 86 05 00 mv a2, a1 +80006c9c: 13 05 45 00 addi a0, a0, 4 +80006ca0: 93 06 84 01 addi a3, s0, 24 +80006ca4: 93 05 f0 00 addi a1, zero, 15 +80006ca8: 63 d4 97 02 bge a5, s1, 40 +80006cac: 93 07 05 00 mv a5, a0 +80006cb0: 03 d7 27 00 lhu a4, 2(a5) +80006cb4: 93 87 27 00 addi a5, a5, 2 +80006cb8: 23 9f e7 fe sh a4, -2(a5) +80006cbc: e3 9a d7 fe bne a5, a3, -12 +80006cc0: 23 1c 04 00 sh zero, 24(s0) +80006cc4: 13 06 06 ff addi a2, a2, -16 +80006cc8: e3 c2 c5 fe blt a1, a2, -28 +80006ccc: 93 f4 f4 00 andi s1, s1, 15 +80006cd0: 93 07 70 00 addi a5, zero, 7 +80006cd4: 63 d8 97 02 bge a5, s1, 48 +80006cd8: 13 07 84 01 addi a4, s0, 24 +80006cdc: 93 05 24 00 addi a1, s0, 2 +80006ce0: 93 07 00 00 mv a5, zero +80006ce4: 83 56 07 00 lhu a3, 0(a4) +80006ce8: 13 07 e7 ff addi a4, a4, -2 +80006cec: 13 96 86 00 slli a2, a3, 8 +80006cf0: b3 e7 c7 00 or a5, a5, a2 +80006cf4: 23 11 f7 00 sh a5, 2(a4) +80006cf8: 93 d7 86 00 srli a5, a3, 8 +80006cfc: e3 14 b7 fe bne a4, a1, -24 +80006d00: 93 84 84 ff addi s1, s1, -8 +80006d04: 63 8a 04 00 beqz s1, 20 +80006d08: 93 84 f4 ff addi s1, s1, -1 +80006d0c: 13 05 04 00 mv a0, s0 +80006d10: ef f0 9f b7 jal -1160 +80006d14: e3 9a 04 fe bnez s1, -12 +80006d18: 13 05 00 00 mv a0, zero +80006d1c: 83 20 c1 01 lw ra, 28(sp) +80006d20: 03 24 81 01 lw s0, 24(sp) +80006d24: 83 24 41 01 lw s1, 20(sp) +80006d28: 03 29 01 01 lw s2, 16(sp) +80006d2c: 83 29 c1 00 lw s3, 12(sp) +80006d30: 13 01 01 02 addi sp, sp, 32 +80006d34: 67 80 00 00 ret +80006d38: 93 07 10 ff addi a5, zero, -15 +80006d3c: 33 09 b0 40 neg s2, a1 +80006d40: 63 dc f5 12 bge a1, a5, 312 +80006d44: 93 05 85 01 addi a1, a0, 24 +80006d48: 93 09 00 00 mv s3, zero +80006d4c: 93 06 45 00 addi a3, a0, 4 +80006d50: 13 06 f0 00 addi a2, zero, 15 +80006d54: 03 57 84 01 lhu a4, 24(s0) +80006d58: 93 87 05 00 mv a5, a1 +80006d5c: b3 e9 e9 00 or s3, s3, a4 +80006d60: 03 d7 e7 ff lhu a4, -2(a5) +80006d64: 93 87 e7 ff addi a5, a5, -2 +80006d68: 23 91 e7 00 sh a4, 2(a5) +80006d6c: e3 9a d7 fe bne a5, a3, -12 +80006d70: 23 12 04 00 sh zero, 4(s0) +80006d74: 13 09 09 ff addi s2, s2, -16 +80006d78: e3 4e 26 fd blt a2, s2, -36 +80006d7c: 93 07 00 ff addi a5, zero, -16 +80006d80: 13 07 10 ff addi a4, zero, -15 +80006d84: b3 87 97 40 sub a5, a5, s1 +80006d88: 13 09 00 00 mv s2, zero +80006d8c: 63 c4 e4 0a blt s1, a4, 168 +80006d90: 33 09 f9 00 add s2, s2, a5 +80006d94: 93 07 70 00 addi a5, zero, 7 +80006d98: 63 d6 27 05 bge a5, s2, 76 +80006d9c: 93 99 09 01 slli s3, s3, 16 +80006da0: 93 d9 09 41 srai s3, s3, 16 +80006da4: 83 47 84 01 lbu a5, 24(s0) +80006da8: 93 05 a4 01 addi a1, s0, 26 +80006dac: b3 e9 f9 00 or s3, s3, a5 +80006db0: 93 99 09 01 slli s3, s3, 16 +80006db4: 93 d9 09 01 srli s3, s3, 16 +80006db8: 93 07 00 00 mv a5, zero +80006dbc: 03 d6 06 00 lhu a2, 0(a3) +80006dc0: 93 86 26 00 addi a3, a3, 2 +80006dc4: 13 57 86 00 srli a4, a2, 8 +80006dc8: 33 e7 e7 00 or a4, a5, a4 +80006dcc: 93 17 86 00 slli a5, a2, 8 +80006dd0: 93 97 07 01 slli a5, a5, 16 +80006dd4: 23 9f e6 fe sh a4, -2(a3) +80006dd8: 93 d7 07 01 srli a5, a5, 16 +80006ddc: e3 90 b6 fe bne a3, a1, -32 +80006de0: 13 09 89 ff addi s2, s2, -8 +80006de4: 63 0c 09 06 beqz s2, 120 +80006de8: 83 57 84 01 lhu a5, 24(s0) +80006dec: 13 09 f9 ff addi s2, s2, -1 +80006df0: 13 05 04 00 mv a0, s0 +80006df4: 93 f7 17 00 andi a5, a5, 1 +80006df8: b3 e9 37 01 or s3, a5, s3 +80006dfc: ef f0 5f a2 jal -1500 +80006e00: e3 14 09 fe bnez s2, -24 +80006e04: 93 97 09 01 slli a5, s3, 16 +80006e08: 93 d7 07 41 srai a5, a5, 16 +80006e0c: 63 90 07 04 bnez a5, 64 +80006e10: 13 95 09 01 slli a0, s3, 16 +80006e14: 13 55 05 01 srli a0, a0, 16 +80006e18: 83 20 c1 01 lw ra, 28(sp) +80006e1c: 03 24 81 01 lw s0, 24(sp) +80006e20: 83 24 41 01 lw s1, 20(sp) +80006e24: 03 29 01 01 lw s2, 16(sp) +80006e28: 83 29 c1 00 lw s3, 12(sp) +80006e2c: 13 01 01 02 addi sp, sp, 32 +80006e30: 67 80 00 00 ret +80006e34: 13 f9 07 ff andi s2, a5, -16 +80006e38: 33 09 20 41 neg s2, s2 +80006e3c: 33 09 f9 00 add s2, s2, a5 +80006e40: 93 07 70 00 addi a5, zero, 7 +80006e44: e3 d0 27 fb bge a5, s2, -96 +80006e48: 6f f0 5f f5 j -172 +80006e4c: 93 09 10 00 addi s3, zero, 1 +80006e50: 13 95 09 01 slli a0, s3, 16 +80006e54: 13 55 05 01 srli a0, a0, 16 +80006e58: 6f f0 1f fc j -64 +80006e5c: 13 85 09 00 mv a0, s3 +80006e60: 63 98 09 00 bnez s3, 16 +80006e64: 13 15 05 01 slli a0, a0, 16 +80006e68: 13 55 05 01 srli a0, a0, 16 +80006e6c: 6f f0 1f eb j -336 +80006e70: 13 05 10 00 addi a0, zero, 1 +80006e74: 6f f0 1f ff j -16 +80006e78: 93 07 90 ff addi a5, zero, -7 +80006e7c: 93 09 00 00 mv s3, zero +80006e80: e3 d4 f5 f6 bge a1, a5, -152 +80006e84: 93 06 44 00 addi a3, s0, 4 +80006e88: 6f f0 df f1 j -228 + +80006e8c enormlz: +80006e8c: 83 57 45 00 lhu a5, 4(a0) +80006e90: 13 01 01 ff addi sp, sp, -16 +80006e94: 23 22 91 00 sw s1, 4(sp) +80006e98: 23 26 11 00 sw ra, 12(sp) +80006e9c: 23 24 81 00 sw s0, 8(sp) +80006ea0: 23 20 21 01 sw s2, 0(sp) +80006ea4: 93 04 05 00 mv s1, a0 +80006ea8: 63 9c 07 0c bnez a5, 216 +80006eac: 03 57 65 00 lhu a4, 6(a0) +80006eb0: 13 04 00 00 mv s0, zero +80006eb4: 93 17 07 01 slli a5, a4, 16 +80006eb8: 93 d7 07 41 srai a5, a5, 16 +80006ebc: 63 c4 07 0a bltz a5, 168 +80006ec0: 93 06 a5 01 addi a3, a0, 26 +80006ec4: 13 06 00 0a addi a2, zero, 160 +80006ec8: 63 18 07 02 bnez a4, 48 +80006ecc: 93 87 64 00 addi a5, s1, 6 +80006ed0: 6f 00 80 00 j 8 +80006ed4: 03 d7 07 00 lhu a4, 0(a5) +80006ed8: 93 87 27 00 addi a5, a5, 2 +80006edc: 23 9e e7 fe sh a4, -4(a5) +80006ee0: e3 9a f6 fe bne a3, a5, -12 +80006ee4: 23 9c 04 00 sh zero, 24(s1) +80006ee8: 13 04 04 01 addi s0, s0, 16 +80006eec: 63 0c c4 06 beq s0, a2, 120 +80006ef0: 03 d7 64 00 lhu a4, 6(s1) +80006ef4: e3 0c 07 fc beqz a4, -40 +80006ef8: 93 77 07 f0 andi a5, a4, -256 +80006efc: 63 90 07 04 bnez a5, 64 +80006f00: 13 85 84 01 addi a0, s1, 24 +80006f04: 93 85 24 00 addi a1, s1, 2 +80006f08: 93 07 00 00 mv a5, zero +80006f0c: 13 07 05 00 mv a4, a0 +80006f10: 83 56 07 00 lhu a3, 0(a4) +80006f14: 13 07 e7 ff addi a4, a4, -2 +80006f18: 13 96 86 00 slli a2, a3, 8 +80006f1c: b3 e7 c7 00 or a5, a5, a2 +80006f20: 23 11 f7 00 sh a5, 2(a4) +80006f24: 93 d7 86 00 srli a5, a3, 8 +80006f28: e3 94 e5 fe bne a1, a4, -24 +80006f2c: 03 d7 64 00 lhu a4, 6(s1) +80006f30: 13 04 84 00 addi s0, s0, 8 +80006f34: 93 77 07 f0 andi a5, a4, -256 +80006f38: e3 88 07 fc beqz a5, -48 +80006f3c: 13 09 00 0a addi s2, zero, 160 +80006f40: 6f 00 40 01 j 20 +80006f44: 13 04 14 00 addi s0, s0, 1 +80006f48: ef f0 1f 94 jal -1728 +80006f4c: 63 4c 89 00 blt s2, s0, 24 +80006f50: 03 d7 64 00 lhu a4, 6(s1) +80006f54: 13 17 07 01 slli a4, a4, 16 +80006f58: 13 57 07 41 srai a4, a4, 16 +80006f5c: 13 85 04 00 mv a0, s1 +80006f60: e3 52 07 fe bgez a4, -28 +80006f64: 83 20 c1 00 lw ra, 12(sp) +80006f68: 13 05 04 00 mv a0, s0 +80006f6c: 03 24 81 00 lw s0, 8(sp) +80006f70: 83 24 41 00 lw s1, 4(sp) +80006f74: 03 29 01 00 lw s2, 0(sp) +80006f78: 13 01 01 01 addi sp, sp, 16 +80006f7c: 67 80 00 00 ret +80006f80: 13 f7 07 f0 andi a4, a5, -256 +80006f84: 13 04 00 00 mv s0, zero +80006f88: 63 10 07 04 bnez a4, 64 +80006f8c: 13 09 f0 f6 addi s2, zero, -145 +80006f90: 6f 00 40 01 j 20 +80006f94: 13 04 f4 ff addi s0, s0, -1 +80006f98: ef f0 9f 88 jal -1912 +80006f9c: e3 04 24 fd beq s0, s2, -56 +80006fa0: 83 d7 44 00 lhu a5, 4(s1) +80006fa4: 13 85 04 00 mv a0, s1 +80006fa8: e3 96 07 fe bnez a5, -20 +80006fac: 83 20 c1 00 lw ra, 12(sp) +80006fb0: 13 05 04 00 mv a0, s0 +80006fb4: 03 24 81 00 lw s0, 8(sp) +80006fb8: 83 24 41 00 lw s1, 4(sp) +80006fbc: 03 29 01 00 lw s2, 0(sp) +80006fc0: 13 01 01 01 addi sp, sp, 16 +80006fc4: 67 80 00 00 ret +80006fc8: 93 06 45 00 addi a3, a0, 4 +80006fcc: 93 05 a5 01 addi a1, a0, 26 +80006fd0: 13 07 00 00 mv a4, zero +80006fd4: 6f 00 80 00 j 8 +80006fd8: 83 d7 06 00 lhu a5, 0(a3) +80006fdc: 13 d6 87 00 srli a2, a5, 8 +80006fe0: 33 67 c7 00 or a4, a4, a2 +80006fe4: 93 97 87 00 slli a5, a5, 8 +80006fe8: 23 90 e6 00 sh a4, 0(a3) +80006fec: 13 97 07 01 slli a4, a5, 16 +80006ff0: 93 86 26 00 addi a3, a3, 2 +80006ff4: 13 57 07 01 srli a4, a4, 16 +80006ff8: e3 90 b6 fe bne a3, a1, -32 +80006ffc: 83 d7 44 00 lhu a5, 4(s1) +80007000: 13 04 80 ff addi s0, zero, -8 +80007004: 6f f0 9f f8 j -120 + +80007008 emdnorm: +80007008: 13 01 01 fe addi sp, sp, -32 +8000700c: 23 2c 81 00 sw s0, 24(sp) +80007010: 23 2a 91 00 sw s1, 20(sp) +80007014: 23 28 21 01 sw s2, 16(sp) +80007018: 23 26 31 01 sw s3, 12(sp) +8000701c: 23 24 41 01 sw s4, 8(sp) +80007020: 23 22 51 01 sw s5, 4(sp) +80007024: 13 89 06 00 mv s2, a3 +80007028: 93 84 07 00 mv s1, a5 +8000702c: 23 2e 11 00 sw ra, 28(sp) +80007030: 13 04 05 00 mv s0, a0 +80007034: 93 89 05 00 mv s3, a1 +80007038: 13 0a 06 00 mv s4, a2 +8000703c: 93 0a 07 00 mv s5, a4 +80007040: ef f0 df e4 jal -436 +80007044: 93 07 00 09 addi a5, zero, 144 +80007048: 33 09 a9 40 sub s2, s2, a0 +8000704c: 63 dc a7 16 bge a5, a0, 376 +80007050: b7 87 00 00 lui a5, 8 +80007054: 93 87 e7 ff addi a5, a5, -2 +80007058: 63 da 27 1f bge a5, s2, 500 +8000705c: 63 84 0a 1c beqz s5, 456 +80007060: 03 a5 44 00 lw a0, 4(s1) +80007064: 83 a7 04 00 lw a5, 0(s1) +80007068: 63 0a f5 06 beq a0, a5, 116 +8000706c: 13 87 a4 01 addi a4, s1, 26 +80007070: 93 87 44 03 addi a5, s1, 52 +80007074: 13 07 27 00 addi a4, a4, 2 +80007078: 23 1f 07 fe sh zero, -2(a4) +8000707c: e3 1c f7 fe bne a4, a5, -8 +80007080: 93 07 80 03 addi a5, zero, 56 +80007084: 63 0c f5 32 beq a0, a5, 824 +80007088: 63 d0 a7 16 bge a5, a0, 352 +8000708c: 93 07 00 04 addi a5, zero, 64 +80007090: 63 0c f5 2e beq a0, a5, 760 +80007094: 93 07 10 07 addi a5, zero, 113 +80007098: 63 18 f5 34 bne a0, a5, 848 +8000709c: b7 87 00 40 lui a5, 262152 +800070a0: 93 87 f7 ff addi a5, a5, -1 +800070a4: 13 07 a0 00 addi a4, zero, 10 +800070a8: 23 aa f4 00 sw a5, 20(s1) +800070ac: b7 87 ff ff lui a5, 1048568 +800070b0: 23 a4 e4 00 sw a4, 8(s1) +800070b4: 23 9c f4 00 sh a5, 24(s1) +800070b8: 23 a6 e4 00 sw a4, 12(s1) +800070bc: 93 07 a0 00 addi a5, zero, 10 +800070c0: 37 87 00 00 lui a4, 8 +800070c4: 93 87 87 00 addi a5, a5, 8 +800070c8: 93 97 17 00 slli a5, a5, 1 +800070cc: b3 87 f4 00 add a5, s1, a5 +800070d0: 23 95 e7 00 sh a4, 10(a5) +800070d4: 23 a0 a4 00 sw a0, 0(s1) +800070d8: 63 58 20 1b blez s2, 432 +800070dc: 83 a5 84 00 lw a1, 8(s1) +800070e0: 83 d7 44 01 lhu a5, 20(s1) +800070e4: 13 08 f0 08 addi a6, zero, 143 +800070e8: 13 96 15 00 slli a2, a1, 1 +800070ec: 33 06 c4 00 add a2, s0, a2 +800070f0: 03 57 06 00 lhu a4, 0(a2) +800070f4: b3 76 f7 00 and a3, a4, a5 +800070f8: 63 4a a8 02 blt a6, a0, 52 +800070fc: 13 08 b0 00 addi a6, zero, 11 +80007100: 63 46 b8 02 blt a6, a1, 44 +80007104: 93 07 06 00 mv a5, a2 +80007108: 93 05 84 01 addi a1, s0, 24 +8000710c: 03 d7 27 00 lhu a4, 2(a5) +80007110: 63 04 07 00 beqz a4, 8 +80007114: 93 e6 16 00 ori a3, a3, 1 +80007118: 23 91 07 00 sh zero, 2(a5) +8000711c: 93 87 27 00 addi a5, a5, 2 +80007120: e3 96 f5 fe bne a1, a5, -20 +80007124: 03 57 06 00 lhu a4, 0(a2) +80007128: 83 d7 44 01 lhu a5, 20(s1) +8000712c: 93 c7 f7 ff not a5, a5 +80007130: b3 f7 e7 00 and a5, a5, a4 +80007134: 23 10 f6 00 sh a5, 0(a2) +80007138: 83 d7 64 01 lhu a5, 22(s1) +8000713c: 33 f7 d7 00 and a4, a5, a3 +80007140: 63 00 07 04 beqz a4, 64 +80007144: 63 84 d7 1a beq a5, a3, 424 +80007148: 13 86 24 03 addi a2, s1, 50 +8000714c: 93 06 84 01 addi a3, s0, 24 +80007150: 93 84 c4 01 addi s1, s1, 28 +80007154: 13 07 00 00 mv a4, zero +80007158: 83 57 06 00 lhu a5, 0(a2) +8000715c: 83 d5 06 00 lhu a1, 0(a3) +80007160: 93 86 e6 ff addi a3, a3, -2 +80007164: 13 06 e6 ff addi a2, a2, -2 +80007168: b3 87 b7 00 add a5, a5, a1 +8000716c: b3 87 e7 00 add a5, a5, a4 +80007170: 13 d7 07 01 srli a4, a5, 16 +80007174: 23 91 f6 00 sh a5, 2(a3) +80007178: 13 77 17 00 andi a4, a4, 1 +8000717c: e3 1e 96 fc bne a2, s1, -36 +80007180: 63 58 20 19 blez s2, 400 +80007184: 83 57 44 00 lhu a5, 4(s0) +80007188: 63 9e 07 12 bnez a5, 316 +8000718c: b7 87 00 00 lui a5, 8 +80007190: 23 1c 04 00 sh zero, 24(s0) +80007194: 93 87 e7 ff addi a5, a5, -2 +80007198: 63 c8 27 09 blt a5, s2, 144 +8000719c: 23 11 24 01 sh s2, 2(s0) +800071a0: 83 20 c1 01 lw ra, 28(sp) +800071a4: 03 24 81 01 lw s0, 24(sp) +800071a8: 83 24 41 01 lw s1, 20(sp) +800071ac: 03 29 01 01 lw s2, 16(sp) +800071b0: 83 29 c1 00 lw s3, 12(sp) +800071b4: 03 2a 81 00 lw s4, 8(sp) +800071b8: 83 2a 41 00 lw s5, 4(sp) +800071bc: 13 01 01 02 addi sp, sp, 32 +800071c0: 67 80 00 00 ret +800071c4: 63 54 09 0e bgez s2, 232 +800071c8: 93 07 00 f7 addi a5, zero, -144 +800071cc: 63 5c f9 08 bge s2, a5, 152 +800071d0: 93 07 24 00 addi a5, s0, 2 +800071d4: 13 04 a4 01 addi s0, s0, 26 +800071d8: 93 87 27 00 addi a5, a5, 2 +800071dc: 23 9f 07 fe sh zero, -2(a5) +800071e0: e3 9c 87 fe bne a5, s0, -8 +800071e4: 6f f0 df fb j -68 +800071e8: 93 07 80 01 addi a5, zero, 24 +800071ec: 63 08 f5 16 beq a0, a5, 368 +800071f0: 93 07 50 03 addi a5, zero, 53 +800071f4: 63 1a f5 1e bne a0, a5, 500 +800071f8: 37 17 00 00 lui a4, 1 +800071fc: b7 07 00 04 lui a5, 16384 +80007200: 93 06 60 00 addi a3, zero, 6 +80007204: 93 87 f7 7f addi a5, a5, 2047 +80007208: 13 07 07 80 addi a4, a4, -2048 +8000720c: 23 aa f4 00 sw a5, 20(s1) +80007210: 23 a4 d4 00 sw a3, 8(s1) +80007214: 23 9c e4 00 sh a4, 24(s1) +80007218: 23 a6 d4 00 sw a3, 12(s1) +8000721c: 93 07 60 00 addi a5, zero, 6 +80007220: 6f f0 5f ea j -348 +80007224: 23 1c 04 00 sh zero, 24(s0) +80007228: b7 87 ff ff lui a5, 1048568 +8000722c: 93 c7 f7 ff not a5, a5 +80007230: 23 11 f4 00 sh a5, 2(s0) +80007234: 93 07 44 00 addi a5, s0, 4 +80007238: 13 04 84 01 addi s0, s0, 24 +8000723c: 23 90 07 00 sh zero, 0(a5) +80007240: 93 87 27 00 addi a5, a5, 2 +80007244: e3 1c f4 fe bne s0, a5, -8 +80007248: 6f f0 9f f5 j -168 +8000724c: 93 07 24 00 addi a5, s0, 2 +80007250: 13 04 a4 01 addi s0, s0, 26 +80007254: 93 87 27 00 addi a5, a5, 2 +80007258: 23 9f 07 fe sh zero, -2(a5) +8000725c: e3 9c 87 fe bne a5, s0, -8 +80007260: 6f f0 1f f4 j -192 +80007264: 93 05 09 00 mv a1, s2 +80007268: 13 05 04 00 mv a0, s0 +8000726c: ef f0 5f a0 jal -1532 +80007270: 63 04 05 00 beqz a0, 8 +80007274: 93 09 10 00 addi s3, zero, 1 +80007278: 63 8c 0a 0c beqz s5, 216 +8000727c: 03 a5 44 00 lw a0, 4(s1) +80007280: 83 a7 04 00 lw a5, 0(s1) +80007284: e3 14 f5 de bne a0, a5, -536 +80007288: 93 07 00 09 addi a5, zero, 144 +8000728c: 63 04 f5 0a beq a0, a5, 168 +80007290: 83 57 84 01 lhu a5, 24(s0) +80007294: 13 05 04 00 mv a0, s0 +80007298: 93 f7 17 00 andi a5, a5, 1 +8000729c: b3 e9 f9 00 or s3, s3, a5 +800072a0: ef f0 0f d8 jal -2688 +800072a4: 03 a5 44 00 lw a0, 4(s1) +800072a8: 6f f0 5f e3 j -460 +800072ac: e3 80 0a ee beqz s5, -288 +800072b0: 03 a5 44 00 lw a0, 4(s1) +800072b4: 83 a7 04 00 lw a5, 0(s1) +800072b8: e3 1a f5 da bne a0, a5, -588 +800072bc: e3 40 20 e3 bgtz s2, -480 +800072c0: 6f f0 9f fc j -56 +800072c4: 13 05 04 00 mv a0, s0 +800072c8: ef f0 8f d5 jal -2728 +800072cc: b7 87 00 00 lui a5, 8 +800072d0: 13 09 19 00 addi s2, s2, 1 +800072d4: 23 1c 04 00 sh zero, 24(s0) +800072d8: 93 87 e7 ff addi a5, a5, -2 +800072dc: e3 c6 27 f5 blt a5, s2, -180 +800072e0: e3 5e 09 ea bgez s2, -324 +800072e4: 23 11 04 00 sh zero, 2(s0) +800072e8: 6f f0 9f eb j -328 +800072ec: 63 94 09 0c bnez s3, 200 +800072f0: 83 a7 c4 00 lw a5, 12(s1) +800072f4: 03 d7 84 01 lhu a4, 24(s1) +800072f8: 93 97 17 00 slli a5, a5, 1 +800072fc: b3 07 f4 00 add a5, s0, a5 +80007300: 83 d7 07 00 lhu a5, 0(a5) +80007304: b3 f7 e7 00 and a5, a5, a4 +80007308: e3 90 07 e4 bnez a5, -448 +8000730c: e3 4c 20 e7 bgtz s2, -392 +80007310: 93 07 00 09 addi a5, zero, 144 +80007314: 63 06 f5 00 beq a0, a5, 12 +80007318: 13 05 04 00 mv a0, s0 +8000731c: ef f0 cf d6 jal -2708 +80007320: 83 57 44 00 lhu a5, 4(s0) +80007324: e3 90 07 fa bnez a5, -96 +80007328: 23 1c 04 00 sh zero, 24(s0) +8000732c: e3 4c 09 fa bltz s2, -72 +80007330: 6f f0 df e6 j -404 +80007334: 03 a6 84 00 lw a2, 8(s1) +80007338: 83 d7 44 01 lhu a5, 20(s1) +8000733c: 13 16 16 00 slli a2, a2, 1 +80007340: 33 06 c4 00 add a2, s0, a2 +80007344: 03 57 06 00 lhu a4, 0(a2) +80007348: b3 f6 e7 00 and a3, a5, a4 +8000734c: 6f f0 1f de j -544 +80007350: 23 1c 04 00 sh zero, 24(s0) +80007354: 23 11 04 00 sh zero, 2(s0) +80007358: 6f f0 9f e4 j -440 +8000735c: b7 07 80 00 lui a5, 2048 +80007360: 93 87 f7 0f addi a5, a5, 255 +80007364: 13 07 40 00 addi a4, zero, 4 +80007368: 23 aa f4 00 sw a5, 20(s1) +8000736c: 93 07 00 10 addi a5, zero, 256 +80007370: 23 a4 e4 00 sw a4, 8(s1) +80007374: 23 9c f4 00 sh a5, 24(s1) +80007378: 23 a6 e4 00 sw a4, 12(s1) +8000737c: 93 07 40 00 addi a5, zero, 4 +80007380: 13 07 00 10 addi a4, zero, 256 +80007384: 6f f0 1f d4 j -704 +80007388: 93 07 70 00 addi a5, zero, 7 +8000738c: 23 a4 f4 00 sw a5, 8(s1) +80007390: b7 07 01 80 lui a5, 524304 +80007394: 93 87 f7 ff addi a5, a5, -1 +80007398: 23 aa f4 00 sw a5, 20(s1) +8000739c: 93 07 10 00 addi a5, zero, 1 +800073a0: 23 9c f4 00 sh a5, 24(s1) +800073a4: 93 07 60 00 addi a5, zero, 6 +800073a8: 23 a6 f4 00 sw a5, 12(s1) +800073ac: 13 07 10 00 addi a4, zero, 1 +800073b0: 6f f0 5f d1 j -748 +800073b4: e3 0a 0a d8 beqz s4, -620 +800073b8: 6f f0 9f dc j -568 +800073bc: b7 07 80 00 lui a5, 2048 +800073c0: 93 87 f7 0f addi a5, a5, 255 +800073c4: 13 07 60 00 addi a4, zero, 6 +800073c8: 23 aa f4 00 sw a5, 20(s1) +800073cc: 93 07 00 10 addi a5, zero, 256 +800073d0: 23 a4 e4 00 sw a4, 8(s1) +800073d4: 23 9c f4 00 sh a5, 24(s1) +800073d8: 23 a6 e4 00 sw a4, 12(s1) +800073dc: 93 07 60 00 addi a5, zero, 6 +800073e0: 13 07 00 10 addi a4, zero, 256 +800073e4: 6f f0 1f ce j -800 +800073e8: 93 07 c0 00 addi a5, zero, 12 +800073ec: 23 a4 f4 00 sw a5, 8(s1) +800073f0: b7 07 01 80 lui a5, 524304 +800073f4: 93 87 f7 ff addi a5, a5, -1 +800073f8: 23 aa f4 00 sw a5, 20(s1) +800073fc: 93 07 10 00 addi a5, zero, 1 +80007400: 23 9c f4 00 sh a5, 24(s1) +80007404: 93 07 b0 00 addi a5, zero, 11 +80007408: 23 a6 f4 00 sw a5, 12(s1) +8000740c: 13 07 10 00 addi a4, zero, 1 +80007410: 6f f0 5f cb j -844 + +80007414 eiremain: +80007414: 13 01 01 fd addi sp, sp, -48 +80007418: 23 22 91 02 sw s1, 36(sp) +8000741c: 23 2e 31 01 sw s3, 28(sp) +80007420: 93 84 05 00 mv s1, a1 +80007424: 83 59 25 00 lhu s3, 2(a0) +80007428: 23 26 11 02 sw ra, 44(sp) +8000742c: 23 24 81 02 sw s0, 40(sp) +80007430: 23 20 21 03 sw s2, 32(sp) +80007434: 23 2c 41 01 sw s4, 24(sp) +80007438: 13 09 06 00 mv s2, a2 +8000743c: 23 2a 51 01 sw s5, 20(sp) +80007440: 23 28 61 01 sw s6, 16(sp) +80007444: 23 26 71 01 sw s7, 12(sp) +80007448: 23 24 81 01 sw s8, 8(sp) +8000744c: 23 22 91 01 sw s9, 4(sp) +80007450: 23 20 a1 01 sw s10, 0(sp) +80007454: 13 0a 05 00 mv s4, a0 +80007458: ef f0 5f a3 jal -1484 +8000745c: 03 d4 24 00 lhu s0, 2(s1) +80007460: 93 07 05 00 mv a5, a0 +80007464: 13 85 04 00 mv a0, s1 +80007468: b3 89 f9 40 sub s3, s3, a5 +8000746c: 93 0a 49 03 addi s5, s2, 52 +80007470: ef f0 df a1 jal -1508 +80007474: 33 04 a4 40 sub s0, s0, a0 +80007478: 13 07 e9 04 addi a4, s2, 78 +8000747c: 93 87 0a 00 mv a5, s5 +80007480: 93 87 27 00 addi a5, a5, 2 +80007484: 23 9f 07 fe sh zero, -2(a5) +80007488: e3 9c e7 fe bne a5, a4, -8 +8000748c: 63 4a 34 09 blt s0, s3, 148 +80007490: 93 0b 4a 00 addi s7, s4, 4 +80007494: 13 8b 44 00 addi s6, s1, 4 +80007498: 93 89 f9 ff addi s3, s3, -1 +8000749c: 93 0c aa 01 addi s9, s4, 26 +800074a0: 13 8c 24 00 addi s8, s1, 2 +800074a4: 13 07 0b 00 mv a4, s6 +800074a8: 93 87 0b 00 mv a5, s7 +800074ac: 03 d6 07 00 lhu a2, 0(a5) +800074b0: 83 56 07 00 lhu a3, 0(a4) +800074b4: 93 87 27 00 addi a5, a5, 2 +800074b8: 13 07 27 00 addi a4, a4, 2 +800074bc: 63 1a d6 0a bne a2, a3, 180 +800074c0: e3 96 97 ff bne a5, s9, -20 +800074c4: 13 06 8a 01 addi a2, s4, 24 +800074c8: 13 87 84 01 addi a4, s1, 24 +800074cc: 93 06 00 00 mv a3, zero +800074d0: 83 57 07 00 lhu a5, 0(a4) +800074d4: 83 55 06 00 lhu a1, 0(a2) +800074d8: 13 07 e7 ff addi a4, a4, -2 +800074dc: b3 87 d7 40 sub a5, a5, a3 +800074e0: b3 87 b7 40 sub a5, a5, a1 +800074e4: 93 d6 07 01 srli a3, a5, 16 +800074e8: 23 11 f7 00 sh a5, 2(a4) +800074ec: 93 f6 16 00 andi a3, a3, 1 +800074f0: 13 06 e6 ff addi a2, a2, -2 +800074f4: e3 1e ec fc bne s8, a4, -36 +800074f8: 13 0d 10 00 addi s10, zero, 1 +800074fc: 13 85 0a 00 mv a0, s5 +80007500: ef f0 8f b8 jal -3192 +80007504: 83 57 c9 04 lhu a5, 76(s2) +80007508: 13 04 f4 ff addi s0, s0, -1 +8000750c: 13 85 04 00 mv a0, s1 +80007510: 33 6d fd 00 or s10, s10, a5 +80007514: 23 16 a9 05 sh s10, 76(s2) +80007518: ef f0 0f b7 jal -3216 +8000751c: e3 14 34 f9 bne s0, s3, -120 +80007520: 93 06 04 00 mv a3, s0 +80007524: 03 24 81 02 lw s0, 40(sp) +80007528: 83 20 c1 02 lw ra, 44(sp) +8000752c: 83 29 c1 01 lw s3, 28(sp) +80007530: 03 2a 81 01 lw s4, 24(sp) +80007534: 83 2a 41 01 lw s5, 20(sp) +80007538: 03 2b 01 01 lw s6, 16(sp) +8000753c: 83 2b c1 00 lw s7, 12(sp) +80007540: 03 2c 81 00 lw s8, 8(sp) +80007544: 83 2c 41 00 lw s9, 4(sp) +80007548: 03 2d 01 00 lw s10, 0(sp) +8000754c: 93 07 09 00 mv a5, s2 +80007550: 13 85 04 00 mv a0, s1 +80007554: 03 29 01 02 lw s2, 32(sp) +80007558: 83 24 41 02 lw s1, 36(sp) +8000755c: 13 07 00 00 mv a4, zero +80007560: 13 06 00 00 mv a2, zero +80007564: 93 05 00 00 mv a1, zero +80007568: 13 01 01 03 addi sp, sp, 48 +8000756c: 6f f0 df a9 j -1380 +80007570: 13 0d 00 00 mv s10, zero +80007574: e3 e4 c6 f8 bltu a3, a2, -120 +80007578: 6f f0 df f4 j -180 + +8000757c emovo.isra.0: +8000757c: 03 57 05 00 lhu a4, 0(a0) +80007580: 83 57 25 00 lhu a5, 2(a0) +80007584: 63 06 07 00 beqz a4, 12 +80007588: 37 87 00 00 lui a4, 8 +8000758c: b3 e7 e7 00 or a5, a5, a4 +80007590: 23 99 f5 00 sh a5, 18(a1) +80007594: 03 57 25 00 lhu a4, 2(a0) +80007598: b7 87 00 00 lui a5, 8 +8000759c: 93 87 f7 ff addi a5, a5, -1 +800075a0: 63 04 f7 02 beq a4, a5, 40 +800075a4: 93 07 65 00 addi a5, a0, 6 +800075a8: 93 85 05 01 addi a1, a1, 16 +800075ac: 13 05 85 01 addi a0, a0, 24 +800075b0: 03 d7 07 00 lhu a4, 0(a5) +800075b4: 93 87 27 00 addi a5, a5, 2 +800075b8: 93 85 e5 ff addi a1, a1, -2 +800075bc: 23 91 e5 00 sh a4, 2(a1) +800075c0: e3 98 a7 fe bne a5, a0, -16 +800075c4: 67 80 00 00 ret +800075c8: 93 07 65 00 addi a5, a0, 6 +800075cc: 13 05 a5 01 addi a0, a0, 26 +800075d0: 03 d7 07 00 lhu a4, 0(a5) +800075d4: 93 87 27 00 addi a5, a5, 2 +800075d8: 63 1a 07 02 bnez a4, 52 +800075dc: e3 9a a7 fe bne a5, a0, -12 +800075e0: 13 87 25 01 addi a4, a1, 18 +800075e4: 93 87 05 00 mv a5, a1 +800075e8: 93 87 27 00 addi a5, a5, 2 +800075ec: 23 9f 07 fe sh zero, -2(a5) +800075f0: e3 1c f7 fe bne a4, a5, -8 +800075f4: 83 d7 25 01 lhu a5, 18(a1) +800075f8: 37 87 00 00 lui a4, 8 +800075fc: 13 07 f7 ff addi a4, a4, -1 +80007600: b3 e7 e7 00 or a5, a5, a4 +80007604: 23 99 f5 00 sh a5, 18(a1) +80007608: 67 80 00 00 ret +8000760c: 13 87 05 01 addi a4, a1, 16 +80007610: 93 87 05 00 mv a5, a1 +80007614: 93 87 27 00 addi a5, a5, 2 +80007618: 23 9f 07 fe sh zero, -2(a5) +8000761c: e3 1c f7 fe bne a4, a5, -8 +80007620: b7 c7 ff 7f lui a5, 524284 +80007624: 23 a8 f5 00 sw a5, 16(a1) +80007628: 67 80 00 00 ret + +8000762c emul: +8000762c: 13 01 01 f7 addi sp, sp, -144 +80007630: 23 28 61 07 sw s6, 112(sp) +80007634: 03 5b 25 01 lhu s6, 18(a0) +80007638: b7 87 00 00 lui a5, 8 +8000763c: 93 87 f7 ff addi a5, a5, -1 +80007640: 23 2c 41 07 sw s4, 120(sp) +80007644: 33 fa 67 01 and s4, a5, s6 +80007648: 13 1a 0a 01 slli s4, s4, 16 +8000764c: 23 24 81 08 sw s0, 136(sp) +80007650: 23 22 91 08 sw s1, 132(sp) +80007654: 23 20 21 09 sw s2, 128(sp) +80007658: 23 2e 31 07 sw s3, 124(sp) +8000765c: 23 26 11 08 sw ra, 140(sp) +80007660: 23 2a 51 07 sw s5, 116(sp) +80007664: 23 26 71 07 sw s7, 108(sp) +80007668: 23 24 81 07 sw s8, 104(sp) +8000766c: 23 22 91 07 sw s9, 100(sp) +80007670: 13 5a 0a 01 srli s4, s4, 16 +80007674: 93 04 05 00 mv s1, a0 +80007678: 13 89 05 00 mv s2, a1 +8000767c: 13 04 06 00 mv s0, a2 +80007680: 93 89 06 00 mv s3, a3 +80007684: 63 12 fa 10 bne s4, a5, 260 +80007688: ef f0 8f b0 jal -3320 +8000768c: 63 1a 05 28 bnez a0, 660 +80007690: 83 5a 29 01 lhu s5, 18(s2) +80007694: b3 77 5a 01 and a5, s4, s5 +80007698: 63 82 47 2b beq a5, s4, 676 +8000769c: 13 85 04 00 mv a0, s1 +800076a0: ef f0 4f db jal -2636 +800076a4: 63 0e 05 2e beqz a0, 764 +800076a8: b7 55 01 80 lui a1, 524309 +800076ac: 93 85 05 79 addi a1, a1, 1936 +800076b0: 13 05 09 00 mv a0, s2 +800076b4: ef f0 4f c8 jal -2940 +800076b8: 63 06 05 36 beqz a0, 876 +800076bc: 83 5a 29 01 lhu s5, 18(s2) +800076c0: b7 87 00 00 lui a5, 8 +800076c4: 93 87 f7 ff addi a5, a5, -1 +800076c8: b3 fa 57 01 and s5, a5, s5 +800076cc: 93 9a 0a 01 slli s5, s5, 16 +800076d0: 93 da 0a 01 srli s5, s5, 16 +800076d4: 63 94 fa 2c bne s5, a5, 712 +800076d8: 13 05 09 00 mv a0, s2 +800076dc: ef f0 8f d7 jal -2696 +800076e0: 63 10 05 32 bnez a0, 800 +800076e4: 83 d7 24 01 lhu a5, 18(s1) +800076e8: b3 f7 fa 00 and a5, s5, a5 +800076ec: 63 98 57 0b bne a5, s5, 176 +800076f0: 13 85 04 00 mv a0, s1 +800076f4: ef f0 0f d6 jal -2720 +800076f8: 63 18 05 00 bnez a0, 16 +800076fc: 13 05 09 00 mv a0, s2 +80007700: ef f0 4f d5 jal -2732 +80007704: 63 0c 05 08 beqz a0, 152 +80007708: 13 85 04 00 mv a0, s1 +8000770c: ef f0 4f af jal -3340 +80007710: 93 04 05 00 mv s1, a0 +80007714: 13 05 09 00 mv a0, s2 +80007718: ef f0 8f ae jal -3352 +8000771c: b3 84 a4 40 sub s1, s1, a0 +80007720: b3 34 90 00 snez s1, s1 +80007724: 93 94 f4 00 slli s1, s1, 15 +80007728: 23 19 94 00 sh s1, 18(s0) +8000772c: 13 07 24 01 addi a4, s0, 18 +80007730: 93 07 04 00 mv a5, s0 +80007734: 93 87 27 00 addi a5, a5, 2 +80007738: 23 9f 07 fe sh zero, -2(a5) +8000773c: e3 1c f7 fe bne a4, a5, -8 +80007740: 83 57 24 01 lhu a5, 18(s0) +80007744: 37 87 00 00 lui a4, 8 +80007748: 13 07 f7 ff addi a4, a4, -1 +8000774c: b3 e7 e7 00 or a5, a5, a4 +80007750: 23 19 f4 00 sh a5, 18(s0) +80007754: 83 20 c1 08 lw ra, 140(sp) +80007758: 03 24 81 08 lw s0, 136(sp) +8000775c: 83 24 41 08 lw s1, 132(sp) +80007760: 03 29 01 08 lw s2, 128(sp) +80007764: 83 29 c1 07 lw s3, 124(sp) +80007768: 03 2a 81 07 lw s4, 120(sp) +8000776c: 83 2a 41 07 lw s5, 116(sp) +80007770: 03 2b 01 07 lw s6, 112(sp) +80007774: 83 2b c1 06 lw s7, 108(sp) +80007778: 03 2c 81 06 lw s8, 104(sp) +8000777c: 83 2c 41 06 lw s9, 100(sp) +80007780: 13 01 01 09 addi sp, sp, 144 +80007784: 67 80 00 00 ret +80007788: 83 da 25 01 lhu s5, 18(a1) +8000778c: 33 f7 57 01 and a4, a5, s5 +80007790: 13 17 07 01 slli a4, a4, 16 +80007794: 13 57 07 01 srli a4, a4, 16 +80007798: 63 0a f7 04 beq a4, a5, 84 +8000779c: 13 85 04 00 mv a0, s1 +800077a0: 93 05 c1 00 addi a1, sp, 12 +800077a4: ef f0 cf a9 jal -3428 +800077a8: 13 05 09 00 mv a0, s2 +800077ac: 93 05 81 02 addi a1, sp, 40 +800077b0: ef f0 0f a9 jal -3440 +800077b4: 83 54 e1 00 lhu s1, 14(sp) +800077b8: 03 59 a1 02 lhu s2, 42(sp) +800077bc: 63 9c 04 04 bnez s1, 88 +800077c0: 93 07 01 01 addi a5, sp, 16 +800077c4: 93 06 41 02 addi a3, sp, 36 +800077c8: 63 88 d7 20 beq a5, a3, 528 +800077cc: 03 d7 07 00 lhu a4, 0(a5) +800077d0: 93 87 27 00 addi a5, a5, 2 +800077d4: e3 0a 07 fe beqz a4, -12 +800077d8: 13 05 c1 00 addi a0, sp, 12 +800077dc: ef f0 0f eb jal -2384 +800077e0: 03 57 a1 02 lhu a4, 42(sp) +800077e4: b3 04 a0 40 neg s1, a0 +800077e8: 6f 00 00 03 j 48 +800077ec: 13 85 05 00 mv a0, a1 +800077f0: ef f0 0f 9a jal -3680 +800077f4: e3 06 05 ec beqz a0, -308 +800077f8: 13 07 49 01 addi a4, s2, 20 +800077fc: 83 57 09 00 lhu a5, 0(s2) +80007800: 13 09 29 00 addi s2, s2, 2 +80007804: 13 04 24 00 addi s0, s0, 2 +80007808: 23 1f f4 fe sh a5, -2(s0) +8000780c: e3 18 e9 fe bne s2, a4, -16 +80007810: 6f f0 5f f4 j -188 +80007814: 13 07 09 00 mv a4, s2 +80007818: 93 0a 09 00 mv s5, s2 +8000781c: 93 07 c1 02 addi a5, sp, 44 +80007820: 93 06 01 04 addi a3, sp, 64 +80007824: 63 12 07 02 bnez a4, 36 +80007828: 63 82 f6 1c beq a3, a5, 452 +8000782c: 03 d7 07 00 lhu a4, 0(a5) +80007830: 93 87 27 00 addi a5, a5, 2 +80007834: e3 0a 07 fe beqz a4, -12 +80007838: 13 05 81 02 addi a0, sp, 40 +8000783c: ef f0 0f e5 jal -2480 +80007840: 03 57 a1 02 lhu a4, 42(sp) +80007844: b3 0a a9 40 sub s5, s2, a0 +80007848: 83 57 81 02 lhu a5, 40(sp) +8000784c: 13 8c 89 03 addi s8, s3, 56 +80007850: 23 9b e9 02 sh a4, 54(s3) +80007854: 23 9a f9 02 sh a5, 52(s3) +80007858: 13 87 e9 04 addi a4, s3, 78 +8000785c: 93 07 0c 00 mv a5, s8 +80007860: 23 90 07 00 sh zero, 0(a5) +80007864: 93 87 27 00 addi a5, a5, 2 +80007868: e3 1c f7 fe bne a4, a5, -8 +8000786c: 13 8a c9 04 addi s4, s3, 76 +80007870: 93 0b 00 00 mv s7, zero +80007874: 13 09 41 02 addi s2, sp, 36 +80007878: 93 0c 01 01 addi s9, sp, 16 +8000787c: 13 0b 61 04 addi s6, sp, 70 +80007880: 03 55 09 00 lhu a0, 0(s2) +80007884: 13 09 e9 ff addi s2, s2, -2 +80007888: 63 18 05 0c bnez a0, 208 +8000788c: 03 d7 c9 04 lhu a4, 76(s3) +80007890: 93 07 0a 00 mv a5, s4 +80007894: b3 eb eb 00 or s7, s7, a4 +80007898: 03 d7 e7 ff lhu a4, -2(a5) +8000789c: 93 87 e7 ff addi a5, a5, -2 +800078a0: 23 91 e7 00 sh a4, 2(a5) +800078a4: e3 9a 87 ff bne a5, s8, -12 +800078a8: 23 9c 09 02 sh zero, 56(s3) +800078ac: e3 1a 99 fd bne s2, s9, -44 +800078b0: 13 87 49 03 addi a4, s3, 52 +800078b4: 93 07 81 02 addi a5, sp, 40 +800078b8: 93 05 21 04 addi a1, sp, 66 +800078bc: 03 56 07 00 lhu a2, 0(a4) +800078c0: 93 87 27 00 addi a5, a5, 2 +800078c4: 13 07 27 00 addi a4, a4, 2 +800078c8: 23 9f c7 fe sh a2, -2(a5) +800078cc: e3 98 f5 fe bne a1, a5, -16 +800078d0: b7 c6 ff ff lui a3, 1048572 +800078d4: b3 84 54 01 add s1, s1, s5 +800078d8: 93 86 26 00 addi a3, a3, 2 +800078dc: 93 85 0b 00 mv a1, s7 +800078e0: 13 05 81 02 addi a0, sp, 40 +800078e4: 93 87 09 00 mv a5, s3 +800078e8: 13 07 00 04 addi a4, zero, 64 +800078ec: b3 86 d4 00 add a3, s1, a3 +800078f0: 13 06 00 00 mv a2, zero +800078f4: ef f0 4f f1 jal -2284 +800078f8: 03 57 81 02 lhu a4, 40(sp) +800078fc: 83 57 c1 00 lhu a5, 12(sp) +80007900: 93 05 04 00 mv a1, s0 +80007904: 13 05 81 02 addi a0, sp, 40 +80007908: b3 87 e7 40 sub a5, a5, a4 +8000790c: b3 37 f0 00 snez a5, a5 +80007910: b3 07 f0 40 neg a5, a5 +80007914: 23 14 f1 02 sh a5, 40(sp) +80007918: ef f0 5f c6 jal -924 +8000791c: 6f f0 9f e3 j -456 +80007920: 13 87 44 01 addi a4, s1, 20 +80007924: 83 d7 04 00 lhu a5, 0(s1) +80007928: 93 84 24 00 addi s1, s1, 2 +8000792c: 13 04 24 00 addi s0, s0, 2 +80007930: 23 1f f4 fe sh a5, -2(s0) +80007934: e3 98 e4 fe bne s1, a4, -16 +80007938: 6f f0 df e1 j -484 +8000793c: 13 05 09 00 mv a0, s2 +80007940: ef f0 0f 85 jal -4016 +80007944: e3 1a 05 ea bnez a0, -332 +80007948: 13 85 04 00 mv a0, s1 +8000794c: ef f0 8f b0 jal -3320 +80007950: e3 08 05 d6 beqz a0, -656 +80007954: 6f f0 5f d5 j -684 +80007958: 13 06 41 04 addi a2, sp, 68 +8000795c: 93 05 81 02 addi a1, sp, 40 +80007960: ef e0 9f f9 jal -4200 +80007964: 93 05 0a 00 mv a1, s4 +80007968: 13 06 00 00 mv a2, zero +8000796c: 13 07 c1 05 addi a4, sp, 92 +80007970: 03 d8 05 00 lhu a6, 0(a1) +80007974: 83 57 07 00 lhu a5, 0(a4) +80007978: 93 85 e5 ff addi a1, a1, -2 +8000797c: 13 07 e7 ff addi a4, a4, -2 +80007980: b3 87 07 01 add a5, a5, a6 +80007984: b3 87 c7 00 add a5, a5, a2 +80007988: 13 d6 07 01 srli a2, a5, 16 +8000798c: 23 91 f5 00 sh a5, 2(a1) +80007990: 13 76 16 00 andi a2, a2, 1 +80007994: e3 1e 67 fd bne a4, s6, -36 +80007998: 6f f0 5f ef j -268 +8000799c: 03 db 24 01 lhu s6, 18(s1) +800079a0: b7 87 00 00 lui a5, 8 +800079a4: 93 87 f7 ff addi a5, a5, -1 +800079a8: 33 fb 67 01 and s6, a5, s6 +800079ac: 13 1b 0b 01 slli s6, s6, 16 +800079b0: 13 5b 0b 01 srli s6, s6, 16 +800079b4: e3 14 fb de bne s6, a5, -536 +800079b8: 13 85 04 00 mv a0, s1 +800079bc: ef f0 8f a9 jal -3432 +800079c0: e3 14 05 d4 bnez a0, -696 +800079c4: 83 57 29 01 lhu a5, 18(s2) +800079c8: 93 c7 f7 ff not a5, a5 +800079cc: 13 97 17 01 slli a4, a5, 17 +800079d0: e3 16 07 dc bnez a4, -564 +800079d4: 6f f0 9f d2 j -728 +800079d8: 93 07 44 01 addi a5, s0, 20 +800079dc: 13 04 24 00 addi s0, s0, 2 +800079e0: 23 1f 04 fe sh zero, -2(s0) +800079e4: e3 9c 87 fe bne a5, s0, -8 +800079e8: 6f f0 df d6 j -660 +800079ec: 93 07 44 01 addi a5, s0, 20 +800079f0: 13 04 24 00 addi s0, s0, 2 +800079f4: 23 1f 04 fe sh zero, -2(s0) +800079f8: e3 1c f4 fe bne s0, a5, -8 +800079fc: 6f f0 9f d5 j -680 +80007a00: b7 55 01 80 lui a1, 524309 +80007a04: 93 85 05 79 addi a1, a1, 1936 +80007a08: 13 85 04 00 mv a0, s1 +80007a0c: ef f0 cf 92 jal -3796 +80007a10: 63 0a 05 00 beqz a0, 20 +80007a14: 83 d7 24 01 lhu a5, 18(s1) +80007a18: b3 f7 fa 00 and a5, s5, a5 +80007a1c: e3 8e 57 f9 beq a5, s5, -100 +80007a20: 6f f0 5f fa j -92 +80007a24: 13 07 04 01 addi a4, s0, 16 +80007a28: 93 07 04 00 mv a5, s0 +80007a2c: 93 87 27 00 addi a5, a5, 2 +80007a30: 23 9f 07 fe sh zero, -2(a5) +80007a34: e3 9c e7 fe bne a5, a4, -8 +80007a38: b7 c7 ff 7f lui a5, 524284 +80007a3c: 23 28 f4 00 sw a5, 16(s0) +80007a40: 6f f0 5f d1 j -748 + +80007a44 ediv: +80007a44: 83 57 25 01 lhu a5, 18(a0) +80007a48: 13 01 01 f5 addi sp, sp, -176 +80007a4c: 23 24 81 0a sw s0, 168(sp) +80007a50: 93 c7 f7 ff not a5, a5 +80007a54: 23 22 91 0a sw s1, 164(sp) +80007a58: 23 20 21 0b sw s2, 160(sp) +80007a5c: 23 2e 31 09 sw s3, 156(sp) +80007a60: 23 26 11 0a sw ra, 172(sp) +80007a64: 23 2c 41 09 sw s4, 152(sp) +80007a68: 23 2a 51 09 sw s5, 148(sp) +80007a6c: 23 28 61 09 sw s6, 144(sp) +80007a70: 23 26 71 09 sw s7, 140(sp) +80007a74: 23 24 81 09 sw s8, 136(sp) +80007a78: 23 22 91 09 sw s9, 132(sp) +80007a7c: 23 20 a1 09 sw s10, 128(sp) +80007a80: 23 2e b1 07 sw s11, 124(sp) +80007a84: 13 97 17 01 slli a4, a5, 17 +80007a88: 13 09 05 00 mv s2, a0 +80007a8c: 93 89 05 00 mv s3, a1 +80007a90: 13 04 06 00 mv s0, a2 +80007a94: 93 84 06 00 mv s1, a3 +80007a98: 63 16 07 00 bnez a4, 12 +80007a9c: ef e0 5f ef jal -4364 +80007aa0: 63 18 05 38 bnez a0, 912 +80007aa4: 83 d7 29 01 lhu a5, 18(s3) +80007aa8: 93 c7 f7 ff not a5, a5 +80007aac: 13 97 17 01 slli a4, a5, 17 +80007ab0: 63 0e 07 08 beqz a4, 156 +80007ab4: 37 5a 01 80 lui s4, 524309 +80007ab8: 93 05 0a 79 addi a1, s4, 1936 +80007abc: 13 05 09 00 mv a0, s2 +80007ac0: ef f0 8f 87 jal -3976 +80007ac4: 63 04 05 10 beqz a0, 264 +80007ac8: 03 5a 29 01 lhu s4, 18(s2) +80007acc: 03 d7 29 01 lhu a4, 18(s3) +80007ad0: b7 87 00 00 lui a5, 8 +80007ad4: 93 87 f7 ff addi a5, a5, -1 +80007ad8: 33 fa 47 01 and s4, a5, s4 +80007adc: b3 fa e7 00 and s5, a5, a4 +80007ae0: 63 1a fa 08 bne s4, a5, 148 +80007ae4: 13 05 09 00 mv a0, s2 +80007ae8: ef f0 cf 96 jal -3732 +80007aec: 63 08 05 10 beqz a0, 272 +80007af0: 63 98 4a 01 bne s5, s4, 16 +80007af4: 13 85 09 00 mv a0, s3 +80007af8: ef f0 cf 95 jal -3748 +80007afc: 63 10 05 0e bnez a0, 224 +80007b00: 93 07 44 01 addi a5, s0, 20 +80007b04: 13 04 24 00 addi s0, s0, 2 +80007b08: 23 1f 04 fe sh zero, -2(s0) +80007b0c: e3 1c f4 fe bne s0, a5, -8 +80007b10: 83 20 c1 0a lw ra, 172(sp) +80007b14: 03 24 81 0a lw s0, 168(sp) +80007b18: 83 24 41 0a lw s1, 164(sp) +80007b1c: 03 29 01 0a lw s2, 160(sp) +80007b20: 83 29 c1 09 lw s3, 156(sp) +80007b24: 03 2a 81 09 lw s4, 152(sp) +80007b28: 83 2a 41 09 lw s5, 148(sp) +80007b2c: 03 2b 01 09 lw s6, 144(sp) +80007b30: 83 2b c1 08 lw s7, 140(sp) +80007b34: 03 2c 81 08 lw s8, 136(sp) +80007b38: 83 2c 41 08 lw s9, 132(sp) +80007b3c: 03 2d 01 08 lw s10, 128(sp) +80007b40: 83 2d c1 07 lw s11, 124(sp) +80007b44: 13 01 01 0b addi sp, sp, 176 +80007b48: 67 80 00 00 ret +80007b4c: 13 85 09 00 mv a0, s3 +80007b50: ef e0 1f e4 jal -4544 +80007b54: e3 00 05 f6 beqz a0, -160 +80007b58: 13 87 49 01 addi a4, s3, 20 +80007b5c: 83 d7 09 00 lhu a5, 0(s3) +80007b60: 93 89 29 00 addi s3, s3, 2 +80007b64: 13 04 24 00 addi s0, s0, 2 +80007b68: 23 1f f4 fe sh a5, -2(s0) +80007b6c: e3 98 e9 fe bne s3, a4, -16 +80007b70: 6f f0 1f fa j -96 +80007b74: 63 86 fa 08 beq s5, a5, 140 +80007b78: 13 05 09 00 mv a0, s2 +80007b7c: 93 05 c1 01 addi a1, sp, 28 +80007b80: ef e0 1f ec jal -4416 +80007b84: 93 05 81 03 addi a1, sp, 56 +80007b88: 13 85 09 00 mv a0, s3 +80007b8c: ef e0 5f eb jal -4428 +80007b90: 83 5b a1 03 lhu s7, 58(sp) +80007b94: 03 59 e1 01 lhu s2, 30(sp) +80007b98: 63 92 0b 0c bnez s7, 196 +80007b9c: 93 07 c1 03 addi a5, sp, 60 +80007ba0: 93 0d 01 05 addi s11, sp, 80 +80007ba4: 63 8e fd 34 beq s11, a5, 860 +80007ba8: 03 d7 07 00 lhu a4, 0(a5) +80007bac: 93 87 27 00 addi a5, a5, 2 +80007bb0: e3 0a 07 fe beqz a4, -12 +80007bb4: 13 05 81 03 addi a0, sp, 56 +80007bb8: ef f0 4f ad jal -3372 +80007bbc: b3 07 a0 40 neg a5, a0 +80007bc0: 03 56 e1 01 lhu a2, 30(sp) +80007bc4: 23 26 f1 00 sw a5, 12(sp) +80007bc8: 6f 00 c0 09 j 156 +80007bcc: 93 05 0a 79 addi a1, s4, 1936 +80007bd0: 13 85 09 00 mv a0, s3 +80007bd4: ef e0 5f f6 jal -4252 +80007bd8: e3 18 05 ee bnez a0, -272 +80007bdc: 13 07 04 01 addi a4, s0, 16 +80007be0: 93 07 04 00 mv a5, s0 +80007be4: 93 87 27 00 addi a5, a5, 2 +80007be8: 23 9f 07 fe sh zero, -2(a5) +80007bec: e3 9c e7 fe bne a5, a4, -8 +80007bf0: b7 c7 ff 7f lui a5, 524284 +80007bf4: 23 28 f4 00 sw a5, 16(s0) +80007bf8: 6f f0 9f f1 j -232 +80007bfc: e3 9e 4a f7 bne s5, s4, -132 +80007c00: 13 85 09 00 mv a0, s3 +80007c04: ef f0 0f 85 jal -4016 +80007c08: e3 08 05 f6 beqz a0, -144 +80007c0c: 13 05 09 00 mv a0, s2 +80007c10: ef e0 1f df jal -4624 +80007c14: 93 04 05 00 mv s1, a0 +80007c18: 13 85 09 00 mv a0, s3 +80007c1c: ef e0 5f de jal -4636 +80007c20: b3 87 a4 40 sub a5, s1, a0 +80007c24: b3 37 f0 00 snez a5, a5 +80007c28: 93 97 f7 00 slli a5, a5, 15 +80007c2c: 23 19 f4 00 sh a5, 18(s0) +80007c30: 13 07 24 01 addi a4, s0, 18 +80007c34: 93 07 04 00 mv a5, s0 +80007c38: 93 87 27 00 addi a5, a5, 2 +80007c3c: 23 9f 07 fe sh zero, -2(a5) +80007c40: e3 9c e7 fe bne a5, a4, -8 +80007c44: 83 57 24 01 lhu a5, 18(s0) +80007c48: 37 87 00 00 lui a4, 8 +80007c4c: 13 07 f7 ff addi a4, a4, -1 +80007c50: b3 e7 e7 00 or a5, a5, a4 +80007c54: 23 19 f4 00 sh a5, 18(s0) +80007c58: 6f f0 9f eb j -328 +80007c5c: 23 26 71 01 sw s7, 12(sp) +80007c60: 13 06 09 00 mv a2, s2 +80007c64: 23 24 21 01 sw s2, 8(sp) +80007c68: 93 07 01 02 addi a5, sp, 32 +80007c6c: 93 06 41 03 addi a3, sp, 52 +80007c70: 63 12 06 02 bnez a2, 36 +80007c74: 63 80 f6 2a beq a3, a5, 672 +80007c78: 03 d7 07 00 lhu a4, 0(a5) +80007c7c: 93 87 27 00 addi a5, a5, 2 +80007c80: e3 0a 07 fe beqz a4, -12 +80007c84: 13 05 c1 01 addi a0, sp, 28 +80007c88: ef f0 4f a0 jal -3580 +80007c8c: b3 07 a9 40 sub a5, s2, a0 +80007c90: 23 24 f1 00 sw a5, 8(sp) +80007c94: 03 27 81 03 lw a4, 56(sp) +80007c98: 13 8d 84 03 addi s10, s1, 56 +80007c9c: 93 07 0d 00 mv a5, s10 +80007ca0: 23 aa e4 02 sw a4, 52(s1) +80007ca4: 13 89 e4 04 addi s2, s1, 78 +80007ca8: 93 87 27 00 addi a5, a5, 2 +80007cac: 23 9f 07 fe sh zero, -2(a5) +80007cb0: e3 1c f9 fe bne s2, a5, -8 +80007cb4: 13 05 81 03 addi a0, sp, 56 +80007cb8: ef e0 9f b6 jal -5272 +80007cbc: 03 5c 21 02 lhu s8, 34(sp) +80007cc0: 37 0a 01 00 lui s4, 16 +80007cc4: 93 0d 01 05 addi s11, sp, 80 +80007cc8: 93 1a 0c 01 slli s5, s8, 16 +80007ccc: b3 8a 8a 41 sub s5, s5, s8 +80007cd0: 13 0b a1 03 addi s6, sp, 58 +80007cd4: 13 0a fa ff addi s4, s4, -1 +80007cd8: 93 0c e1 06 addi s9, sp, 110 +80007cdc: 93 09 61 05 addi s3, sp, 86 +80007ce0: 83 57 c1 03 lhu a5, 60(sp) +80007ce4: 03 57 e1 03 lhu a4, 62(sp) +80007ce8: 93 0b 0a 00 mv s7, s4 +80007cec: 93 97 07 01 slli a5, a5, 16 +80007cf0: b3 87 e7 00 add a5, a5, a4 +80007cf4: 63 e8 fa 00 bltu s5, a5, 16 +80007cf8: b3 d7 87 03 divu a5, a5, s8 +80007cfc: 93 9b 07 01 slli s7, a5, 16 +80007d00: 93 db 0b 01 srli s7, s7, 16 +80007d04: 13 06 41 05 addi a2, sp, 84 +80007d08: 93 05 c1 01 addi a1, sp, 28 +80007d0c: 13 85 0b 00 mv a0, s7 +80007d10: ef e0 9f be jal -5144 +80007d14: 13 07 c1 03 addi a4, sp, 60 +80007d18: 93 07 81 05 addi a5, sp, 88 +80007d1c: 83 d5 07 00 lhu a1, 0(a5) +80007d20: 03 56 07 00 lhu a2, 0(a4) +80007d24: 93 87 27 00 addi a5, a5, 2 +80007d28: 13 07 27 00 addi a4, a4, 2 +80007d2c: 63 90 c5 12 bne a1, a2, 288 +80007d30: e3 96 97 ff bne a5, s9, -20 +80007d34: 93 07 00 00 mv a5, zero +80007d38: 93 05 c1 06 addi a1, sp, 108 +80007d3c: 13 86 0d 00 mv a2, s11 +80007d40: 03 57 06 00 lhu a4, 0(a2) +80007d44: 03 d8 05 00 lhu a6, 0(a1) +80007d48: 13 06 e6 ff addi a2, a2, -2 +80007d4c: 33 07 f7 40 sub a4, a4, a5 +80007d50: 33 07 07 41 sub a4, a4, a6 +80007d54: 93 57 07 01 srli a5, a4, 16 +80007d58: 23 11 e6 00 sh a4, 2(a2) +80007d5c: 93 f7 17 00 andi a5, a5, 1 +80007d60: 93 85 e5 ff addi a1, a1, -2 +80007d64: e3 1e 66 fd bne a2, s6, -36 +80007d68: 23 10 7d 01 sh s7, 0(s10) +80007d6c: 93 07 c1 03 addi a5, sp, 60 +80007d70: 03 d7 27 00 lhu a4, 2(a5) +80007d74: 93 87 27 00 addi a5, a5, 2 +80007d78: 23 9f e7 fe sh a4, -2(a5) +80007d7c: e3 9a b7 ff bne a5, s11, -12 +80007d80: 23 18 01 04 sh zero, 80(sp) +80007d84: 13 0d 2d 00 addi s10, s10, 2 +80007d88: e3 1c a9 f5 bne s2, s10, -168 +80007d8c: 93 05 00 00 mv a1, zero +80007d90: 93 07 c1 03 addi a5, sp, 60 +80007d94: 93 06 21 05 addi a3, sp, 82 +80007d98: 03 d7 07 00 lhu a4, 0(a5) +80007d9c: 93 87 27 00 addi a5, a5, 2 +80007da0: b3 e5 e5 00 or a1, a1, a4 +80007da4: e3 9a d7 fe bne a5, a3, -12 +80007da8: 93 97 05 01 slli a5, a1, 16 +80007dac: 93 d7 07 41 srai a5, a5, 16 +80007db0: 63 84 07 00 beqz a5, 8 +80007db4: 93 05 10 00 addi a1, zero, 1 +80007db8: 93 95 05 01 slli a1, a1, 16 +80007dbc: 93 d5 05 01 srli a1, a1, 16 +80007dc0: 13 87 44 03 addi a4, s1, 52 +80007dc4: 93 07 81 03 addi a5, sp, 56 +80007dc8: 03 56 07 00 lhu a2, 0(a4) +80007dcc: 93 87 27 00 addi a5, a5, 2 +80007dd0: 13 07 27 00 addi a4, a4, 2 +80007dd4: 23 9f c7 fe sh a2, -2(a5) +80007dd8: e3 98 f6 fe bne a3, a5, -16 +80007ddc: 83 27 c1 00 lw a5, 12(sp) +80007de0: 03 27 81 00 lw a4, 8(sp) +80007de4: b7 46 00 00 lui a3, 4 +80007de8: 93 86 f6 ff addi a3, a3, -1 +80007dec: b3 8b e7 40 sub s7, a5, a4 +80007df0: 13 05 81 03 addi a0, sp, 56 +80007df4: 93 87 04 00 mv a5, s1 +80007df8: 13 07 00 04 addi a4, zero, 64 +80007dfc: b3 86 db 00 add a3, s7, a3 +80007e00: 13 06 00 00 mv a2, zero +80007e04: ef f0 4f a0 jal -3580 +80007e08: 03 57 81 03 lhu a4, 56(sp) +80007e0c: 83 57 c1 01 lhu a5, 28(sp) +80007e10: 93 05 04 00 mv a1, s0 +80007e14: 13 05 81 03 addi a0, sp, 56 +80007e18: b3 87 e7 40 sub a5, a5, a4 +80007e1c: b3 37 f0 00 snez a5, a5 +80007e20: b3 07 f0 40 neg a5, a5 +80007e24: 23 1c f1 02 sh a5, 56(sp) +80007e28: ef f0 4f f5 jal -2220 +80007e2c: 6f f0 5f ce j -796 +80007e30: 13 07 49 01 addi a4, s2, 20 +80007e34: 83 57 09 00 lhu a5, 0(s2) +80007e38: 13 09 29 00 addi s2, s2, 2 +80007e3c: 13 04 24 00 addi s0, s0, 2 +80007e40: 23 1f f4 fe sh a5, -2(s0) +80007e44: e3 18 e9 fe bne s2, a4, -16 +80007e48: 6f f0 9f cc j -824 +80007e4c: e3 74 b6 ee bgeu a2, a1, -280 +80007e50: 93 87 fb ff addi a5, s7, -1 +80007e54: 93 98 07 01 slli a7, a5, 16 +80007e58: 93 d8 08 01 srli a7, a7, 16 +80007e5c: 93 07 00 00 mv a5, zero +80007e60: 93 05 41 03 addi a1, sp, 52 +80007e64: 13 06 c1 06 addi a2, sp, 108 +80007e68: 03 57 06 00 lhu a4, 0(a2) +80007e6c: 03 d8 05 00 lhu a6, 0(a1) +80007e70: 13 06 e6 ff addi a2, a2, -2 +80007e74: 33 07 f7 40 sub a4, a4, a5 +80007e78: 33 07 07 41 sub a4, a4, a6 +80007e7c: 93 57 07 01 srli a5, a4, 16 +80007e80: 23 11 e6 00 sh a4, 2(a2) +80007e84: 93 f7 17 00 andi a5, a5, 1 +80007e88: 93 85 e5 ff addi a1, a1, -2 +80007e8c: e3 1e 36 fd bne a2, s3, -36 +80007e90: 13 07 c1 03 addi a4, sp, 60 +80007e94: 93 07 81 05 addi a5, sp, 88 +80007e98: 83 d5 07 00 lhu a1, 0(a5) +80007e9c: 03 56 07 00 lhu a2, 0(a4) +80007ea0: 93 87 27 00 addi a5, a5, 2 +80007ea4: 13 07 27 00 addi a4, a4, 2 +80007ea8: 63 98 c5 00 bne a1, a2, 16 +80007eac: e3 96 97 ff bne a5, s9, -20 +80007eb0: 93 8b 08 00 mv s7, a7 +80007eb4: 6f f0 1f e8 j -384 +80007eb8: e3 7c b6 fe bgeu a2, a1, -8 +80007ebc: 93 87 eb ff addi a5, s7, -2 +80007ec0: 93 9b 07 01 slli s7, a5, 16 +80007ec4: 93 db 0b 01 srli s7, s7, 16 +80007ec8: 13 06 00 00 mv a2, zero +80007ecc: 93 05 41 03 addi a1, sp, 52 +80007ed0: 13 07 c1 06 addi a4, sp, 108 +80007ed4: 83 57 07 00 lhu a5, 0(a4) +80007ed8: 03 d8 05 00 lhu a6, 0(a1) +80007edc: 13 07 e7 ff addi a4, a4, -2 +80007ee0: b3 87 c7 40 sub a5, a5, a2 +80007ee4: b3 87 07 41 sub a5, a5, a6 +80007ee8: 13 d6 07 01 srli a2, a5, 16 +80007eec: 23 11 f7 00 sh a5, 2(a4) +80007ef0: 13 76 16 00 andi a2, a2, 1 +80007ef4: 93 85 e5 ff addi a1, a1, -2 +80007ef8: e3 1e 37 fd bne a4, s3, -36 +80007efc: 6f f0 9f e3 j -456 +80007f00: 93 07 44 01 addi a5, s0, 20 +80007f04: 13 04 24 00 addi s0, s0, 2 +80007f08: 23 1f 04 fe sh zero, -2(s0) +80007f0c: e3 9c 87 fe bne a5, s0, -8 +80007f10: 6f f0 1f c0 j -1024 +80007f14: 03 57 c1 01 lhu a4, 28(sp) +80007f18: 83 57 81 03 lhu a5, 56(sp) +80007f1c: 63 04 f7 00 beq a4, a5, 8 +80007f20: 37 86 00 00 lui a2, 8 +80007f24: 23 19 c4 00 sh a2, 18(s0) +80007f28: 13 07 24 01 addi a4, s0, 18 +80007f2c: 93 07 04 00 mv a5, s0 +80007f30: 93 87 27 00 addi a5, a5, 2 +80007f34: 23 9f 07 fe sh zero, -2(a5) +80007f38: e3 1c f7 fe bne a4, a5, -8 +80007f3c: 83 57 24 01 lhu a5, 18(s0) +80007f40: 37 87 00 00 lui a4, 8 +80007f44: 13 07 f7 ff addi a4, a4, -1 +80007f48: b3 e7 e7 00 or a5, a5, a4 +80007f4c: 23 19 f4 00 sh a5, 18(s0) +80007f50: 6f f0 1f bc j -1088 + +80007f54 e113toe.isra.0: +80007f54: 13 01 01 fd addi sp, sp, -48 +80007f58: 23 24 81 02 sw s0, 40(sp) +80007f5c: 23 26 11 02 sw ra, 44(sp) +80007f60: 13 84 05 00 mv s0, a1 +80007f64: 93 07 41 00 addi a5, sp, 4 +80007f68: 13 07 e1 01 addi a4, sp, 30 +80007f6c: 93 87 27 00 addi a5, a5, 2 +80007f70: 23 9f 07 fe sh zero, -2(a5) +80007f74: e3 9c e7 fe bne a5, a4, -8 +80007f78: 03 56 e5 00 lhu a2, 14(a0) +80007f7c: 93 17 06 01 slli a5, a2, 16 +80007f80: 93 d7 07 41 srai a5, a5, 16 +80007f84: 63 ca 07 06 bltz a5, 116 +80007f88: b7 87 00 00 lui a5, 8 +80007f8c: 93 87 f7 ff addi a5, a5, -1 +80007f90: 23 12 01 00 sh zero, 4(sp) +80007f94: 33 76 f6 00 and a2, a2, a5 +80007f98: 63 0c f6 06 beq a2, a5, 120 +80007f9c: 93 07 e5 00 addi a5, a0, 14 +80007fa0: 23 13 c1 00 sh a2, 6(sp) +80007fa4: 13 07 a1 00 addi a4, sp, 10 +80007fa8: 83 d6 e7 ff lhu a3, -2(a5) +80007fac: 93 87 e7 ff addi a5, a5, -2 +80007fb0: 13 07 27 00 addi a4, a4, 2 +80007fb4: 23 1f d7 fe sh a3, -2(a4) +80007fb8: e3 18 f5 fe bne a0, a5, -16 +80007fbc: 63 12 06 02 bnez a2, 36 +80007fc0: 23 14 01 00 sh zero, 8(sp) +80007fc4: 93 05 04 00 mv a1, s0 +80007fc8: 13 05 41 00 addi a0, sp, 4 +80007fcc: ef f0 0f db jal -2640 +80007fd0: 83 20 c1 02 lw ra, 44(sp) +80007fd4: 03 24 81 02 lw s0, 40(sp) +80007fd8: 13 01 01 03 addi sp, sp, 48 +80007fdc: 67 80 00 00 ret +80007fe0: 93 07 10 00 addi a5, zero, 1 +80007fe4: 93 05 f0 ff addi a1, zero, -1 +80007fe8: 13 05 41 00 addi a0, sp, 4 +80007fec: 23 14 f1 00 sh a5, 8(sp) +80007ff0: ef e0 1f c8 jal -4992 +80007ff4: 6f f0 1f fd j -48 +80007ff8: 93 07 f0 ff addi a5, zero, -1 +80007ffc: 23 12 f1 00 sh a5, 4(sp) +80008000: b7 87 00 00 lui a5, 8 +80008004: 93 87 f7 ff addi a5, a5, -1 +80008008: 33 76 f6 00 and a2, a2, a5 +8000800c: e3 18 f6 f8 bne a2, a5, -112 +80008010: 93 07 05 00 mv a5, a0 +80008014: 93 06 e5 00 addi a3, a0, 14 +80008018: 03 d7 07 00 lhu a4, 0(a5) +8000801c: 93 87 27 00 addi a5, a5, 2 +80008020: 63 1c 07 04 bnez a4, 88 +80008024: e3 9a d7 fe bne a5, a3, -12 +80008028: 13 07 44 01 addi a4, s0, 20 +8000802c: 93 07 04 00 mv a5, s0 +80008030: 93 87 27 00 addi a5, a5, 2 +80008034: 23 9f 07 fe sh zero, -2(a5) +80008038: e3 1c f7 fe bne a4, a5, -8 +8000803c: 13 07 24 01 addi a4, s0, 18 +80008040: 93 07 04 00 mv a5, s0 +80008044: 93 87 27 00 addi a5, a5, 2 +80008048: 23 9f 07 fe sh zero, -2(a5) +8000804c: e3 1c f7 fe bne a4, a5, -8 +80008050: 83 57 24 01 lhu a5, 18(s0) +80008054: 37 87 00 00 lui a4, 8 +80008058: 13 07 f7 ff addi a4, a4, -1 +8000805c: b3 e7 e7 00 or a5, a5, a4 +80008060: 23 19 f4 00 sh a5, 18(s0) +80008064: 83 17 e5 00 lh a5, 14(a0) +80008068: e3 d4 07 f6 bgez a5, -152 +8000806c: 13 05 04 00 mv a0, s0 +80008070: ef e0 5f 94 jal -5820 +80008074: 6f f0 df f5 j -164 +80008078: 13 07 04 01 addi a4, s0, 16 +8000807c: 93 07 04 00 mv a5, s0 +80008080: 93 87 27 00 addi a5, a5, 2 +80008084: 23 9f 07 fe sh zero, -2(a5) +80008088: e3 1c f7 fe bne a4, a5, -8 +8000808c: b7 c7 ff 7f lui a5, 524284 +80008090: 23 28 f4 00 sw a5, 16(s0) +80008094: 6f f0 df f3 j -196 + +80008098 _ldtoa_r: +80008098: 83 a8 c5 00 lw a7, 12(a1) +8000809c: 13 01 01 e1 addi sp, sp, -496 +800080a0: 83 ae 05 00 lw t4, 0(a1) +800080a4: 03 ae 45 00 lw t3, 4(a1) +800080a8: 03 a3 85 00 lw t1, 8(a1) +800080ac: 23 2e 11 03 sw a7, 60(sp) +800080b0: 83 25 05 04 lw a1, 64(a0) +800080b4: 93 08 f0 ff addi a7, zero, -1 +800080b8: 23 20 11 17 sw a7, 352(sp) +800080bc: 93 08 00 09 addi a7, zero, 144 +800080c0: 23 24 81 1e sw s0, 488(sp) +800080c4: 23 2c 41 1d sw s4, 472(sp) +800080c8: 23 26 11 1e sw ra, 492(sp) +800080cc: 23 22 91 1e sw s1, 484(sp) +800080d0: 23 20 21 1f sw s2, 480(sp) +800080d4: 23 2e 31 1d sw s3, 476(sp) +800080d8: 23 2a 51 1d sw s5, 468(sp) +800080dc: 23 28 61 1d sw s6, 464(sp) +800080e0: 23 26 71 1d sw s7, 460(sp) +800080e4: 23 24 81 1d sw s8, 456(sp) +800080e8: 23 22 91 1d sw s9, 452(sp) +800080ec: 23 20 a1 1d sw s10, 448(sp) +800080f0: 23 2e b1 1b sw s11, 444(sp) +800080f4: 23 28 d1 03 sw t4, 48(sp) +800080f8: 23 2a c1 03 sw t3, 52(sp) +800080fc: 23 2c 61 02 sw t1, 56(sp) +80008100: 23 22 11 17 sw a7, 356(sp) +80008104: 23 24 c1 00 sw a2, 8(sp) +80008108: 23 28 d1 00 sw a3, 16(sp) +8000810c: 23 2a e1 00 sw a4, 20(sp) +80008110: 23 2e 01 01 sw a6, 28(sp) +80008114: 13 0a 05 00 mv s4, a0 +80008118: 13 84 07 00 mv s0, a5 +8000811c: 63 80 05 02 beqz a1, 32 +80008120: 03 27 45 04 lw a4, 68(a0) +80008124: 93 07 10 00 addi a5, zero, 1 +80008128: b3 97 e7 00 sll a5, a5, a4 +8000812c: 23 a2 e5 00 sw a4, 4(a1) +80008130: 23 a4 f5 00 sw a5, 8(a1) +80008134: ef 10 90 3e jal 7144 +80008138: 23 20 0a 04 sw zero, 64(s4) +8000813c: 93 09 01 06 addi s3, sp, 96 +80008140: 93 85 09 00 mv a1, s3 +80008144: 13 05 01 03 addi a0, sp, 48 +80008148: ef f0 df e0 jal -500 +8000814c: 13 85 09 00 mv a0, s3 +80008150: ef e0 1f 8b jal -5968 +80008154: 03 27 81 00 lw a4, 8(sp) +80008158: 33 35 a0 00 snez a0, a0 +8000815c: 23 20 a4 00 sw a0, 0(s0) +80008160: 93 07 30 00 addi a5, zero, 3 +80008164: e3 02 f7 14 beq a4, a5, 2372 +80008168: 93 07 40 01 addi a5, zero, 20 +8000816c: 23 26 f1 00 sw a5, 12(sp) +80008170: e3 1e 07 60 bnez a4, 3612 +80008174: 83 57 21 07 lhu a5, 114(sp) +80008178: 03 27 41 16 lw a4, 356(sp) +8000817c: 93 c7 f7 ff not a5, a5 +80008180: 23 2c e1 00 sw a4, 24(sp) +80008184: 13 97 17 01 slli a4, a5, 17 +80008188: 63 18 07 00 bnez a4, 16 +8000818c: 13 85 09 00 mv a0, s3 +80008190: ef e0 1f 80 jal -6144 +80008194: e3 16 05 40 bnez a0, 3084 +80008198: 93 07 00 09 addi a5, zero, 144 +8000819c: 23 22 f1 16 sw a5, 356(sp) +800081a0: 13 07 c1 07 addi a4, sp, 124 +800081a4: 93 87 09 00 mv a5, s3 +800081a8: 13 06 41 07 addi a2, sp, 116 +800081ac: 83 d6 07 00 lhu a3, 0(a5) +800081b0: 93 87 27 00 addi a5, a5, 2 +800081b4: 13 07 27 00 addi a4, a4, 2 +800081b8: 23 1f d7 fe sh a3, -2(a4) +800081bc: e3 98 c7 fe bne a5, a2, -16 +800081c0: 03 56 e1 08 lhu a2, 142(sp) +800081c4: 23 22 01 00 sw zero, 4(sp) +800081c8: 93 17 06 01 slli a5, a2, 16 +800081cc: 93 d7 07 41 srai a5, a5, 16 +800081d0: 63 de 07 00 bgez a5, 28 +800081d4: 13 16 16 01 slli a2, a2, 17 +800081d8: b7 07 01 00 lui a5, 16 +800081dc: 13 56 16 01 srli a2, a2, 17 +800081e0: 93 87 f7 ff addi a5, a5, -1 +800081e4: 23 17 c1 08 sh a2, 142(sp) +800081e8: 23 22 f1 00 sw a5, 4(sp) +800081ec: b7 5a 01 80 lui s5, 524309 +800081f0: 93 87 0a 79 addi a5, s5, 1936 +800081f4: 93 8b 47 01 addi s7, a5, 20 +800081f8: 93 06 00 00 mv a3, zero +800081fc: 93 07 81 09 addi a5, sp, 152 +80008200: 13 87 0b 00 mv a4, s7 +80008204: 93 0d c1 0a addi s11, sp, 172 +80008208: 6f 00 80 00 j 8 +8000820c: 83 56 07 00 lhu a3, 0(a4) +80008210: 93 87 27 00 addi a5, a5, 2 +80008214: 23 9f d7 fe sh a3, -2(a5) +80008218: 13 07 27 00 addi a4, a4, 2 +8000821c: e3 98 b7 ff bne a5, s11, -16 +80008220: 63 02 06 16 beqz a2, 356 +80008224: b7 87 00 00 lui a5, 8 +80008228: 93 87 f7 ff addi a5, a5, -1 +8000822c: e3 0c f6 58 beq a2, a5, 3480 +80008230: 83 17 c1 08 lh a5, 140(sp) +80008234: e3 de 07 5c bgez a5, 3548 +80008238: 93 05 c1 07 addi a1, sp, 124 +8000823c: 13 85 0b 00 mv a0, s7 +80008240: ef e0 9f 8f jal -5896 +80008244: 63 0c 05 14 beqz a0, 344 +80008248: e3 4c 05 0c bltz a0, 2264 +8000824c: 83 57 e1 08 lhu a5, 142(sp) +80008250: e3 92 07 66 bnez a5, 3684 +80008254: 83 17 c1 08 lh a5, 140(sp) +80008258: 93 04 00 00 mv s1, zero +8000825c: 13 09 01 16 addi s2, sp, 352 +80008260: 63 c8 07 02 bltz a5, 48 +80008264: b7 57 01 80 lui a5, 524309 +80008268: 93 87 07 79 addi a5, a5, 1936 +8000826c: 13 84 87 11 addi s0, a5, 280 +80008270: 13 06 c1 07 addi a2, sp, 124 +80008274: 93 06 09 00 mv a3, s2 +80008278: 93 05 06 00 mv a1, a2 +8000827c: 13 05 04 00 mv a0, s0 +80008280: ef f0 cf ba jal -3156 +80008284: 83 17 c1 08 lh a5, 140(sp) +80008288: 93 84 f4 ff addi s1, s1, -1 +8000828c: e3 d2 07 fe bgez a5, -28 +80008290: 13 04 01 0d addi s0, sp, 208 +80008294: 13 0b 81 0e addi s6, sp, 232 +80008298: 13 07 04 00 mv a4, s0 +8000829c: 93 07 c1 07 addi a5, sp, 124 +800082a0: 13 06 01 09 addi a2, sp, 144 +800082a4: 83 d6 07 00 lhu a3, 0(a5) +800082a8: 93 87 27 00 addi a5, a5, 2 +800082ac: 13 07 27 00 addi a4, a4, 2 +800082b0: 23 1f d7 fe sh a3, -2(a4) +800082b4: e3 98 c7 fe bne a5, a2, -16 +800082b8: 93 06 00 00 mv a3, zero +800082bc: 93 07 81 09 addi a5, sp, 152 +800082c0: 13 87 0b 00 mv a4, s7 +800082c4: 6f 00 80 00 j 8 +800082c8: 83 56 07 00 lhu a3, 0(a4) +800082cc: 93 87 27 00 addi a5, a5, 2 +800082d0: 23 9f d7 fe sh a3, -2(a5) +800082d4: 13 07 27 00 addi a4, a4, 2 +800082d8: e3 98 b7 ff bne a5, s11, -16 +800082dc: b7 57 01 80 lui a5, 524309 +800082e0: 13 87 07 79 addi a4, a5, 1936 +800082e4: 93 87 07 79 addi a5, a5, 1936 +800082e8: 37 fd ff ff lui s10, 1048575 +800082ec: 93 0c 87 02 addi s9, a4, 40 +800082f0: 93 0d c7 12 addi s11, a4, 300 +800082f4: 13 8c 87 11 addi s8, a5, 280 +800082f8: 6f 00 c0 00 j 12 +800082fc: 93 8d 4d 01 addi s11, s11, 20 +80008300: 93 8c 4c 01 addi s9, s9, 20 +80008304: 93 05 04 00 mv a1, s0 +80008308: 13 85 0b 00 mv a0, s7 +8000830c: ef e0 df 82 jal -6100 +80008310: 93 07 05 00 mv a5, a0 +80008314: 93 05 04 00 mv a1, s0 +80008318: 13 85 0d 00 mv a0, s11 +8000831c: 63 56 f0 04 blez a5, 76 +80008320: ef e0 9f 81 jal -6120 +80008324: 93 07 05 00 mv a5, a0 +80008328: 93 06 09 00 mv a3, s2 +8000832c: 13 06 04 00 mv a2, s0 +80008330: 93 05 04 00 mv a1, s0 +80008334: 13 85 0c 00 mv a0, s9 +80008338: 63 c0 07 02 bltz a5, 32 +8000833c: ef f0 0f af jal -3344 +80008340: 13 06 81 09 addi a2, sp, 152 +80008344: 93 06 09 00 mv a3, s2 +80008348: 93 05 06 00 mv a1, a2 +8000834c: 13 85 0c 00 mv a0, s9 +80008350: ef f0 cf ad jal -3364 +80008354: b3 84 a4 01 add s1, s1, s10 +80008358: 93 57 fd 01 srli a5, s10, 31 +8000835c: 33 8d a7 01 add s10, a5, s10 +80008360: 13 5d 1d 40 srai s10, s10, 1 +80008364: e3 9c 8c f9 bne s9, s8, -104 +80008368: 13 06 81 09 addi a2, sp, 152 +8000836c: 93 06 09 00 mv a3, s2 +80008370: 93 85 0b 00 mv a1, s7 +80008374: 13 05 06 00 mv a0, a2 +80008378: ef f0 cf ec jal -2356 +8000837c: 93 0c 41 12 addi s9, sp, 292 +80008380: 6f 00 00 03 j 48 +80008384: 93 07 c1 07 addi a5, sp, 124 +80008388: 93 06 e1 08 addi a3, sp, 142 +8000838c: 03 d7 07 00 lhu a4, 0(a5) +80008390: 93 87 27 00 addi a5, a5, 2 +80008394: e3 12 07 ea bnez a4, -348 +80008398: e3 9a d7 fe bne a5, a3, -12 +8000839c: 93 04 00 00 mv s1, zero +800083a0: 93 0c 41 12 addi s9, sp, 292 +800083a4: 13 09 01 16 addi s2, sp, 352 +800083a8: 13 04 01 0d addi s0, sp, 208 +800083ac: 13 0b 81 0e addi s6, sp, 232 +800083b0: 93 05 04 00 mv a1, s0 +800083b4: 13 05 81 09 addi a0, sp, 152 +800083b8: ef e0 8f e8 jal -6520 +800083bc: 13 07 81 09 addi a4, sp, 152 +800083c0: 93 07 04 00 mv a5, s0 +800083c4: 83 d6 07 00 lhu a3, 0(a5) +800083c8: 93 87 27 00 addi a5, a5, 2 +800083cc: 13 07 27 00 addi a4, a4, 2 +800083d0: 23 1f d7 fe sh a3, -2(a4) +800083d4: e3 98 67 ff bne a5, s6, -16 +800083d8: 93 05 04 00 mv a1, s0 +800083dc: 13 05 c1 07 addi a0, sp, 124 +800083e0: 23 18 01 0a sh zero, 176(sp) +800083e4: ef e0 cf e5 jal -6564 +800083e8: 93 07 c1 07 addi a5, sp, 124 +800083ec: 03 57 04 00 lhu a4, 0(s0) +800083f0: 13 04 24 00 addi s0, s0, 2 +800083f4: 93 87 27 00 addi a5, a5, 2 +800083f8: 23 9f e7 fe sh a4, -2(a5) +800083fc: e3 18 64 ff bne s0, s6, -16 +80008400: 13 05 81 09 addi a0, sp, 152 +80008404: 13 06 09 00 mv a2, s2 +80008408: 93 05 c1 07 addi a1, sp, 124 +8000840c: 23 1a 01 08 sh zero, 148(sp) +80008410: ef f0 4f 80 jal -4092 +80008414: 03 55 c1 1a lhu a0, 428(sp) +80008418: 63 14 05 1c bnez a0, 456 +8000841c: 13 0d 41 09 addi s10, sp, 148 +80008420: 13 04 e1 07 addi s0, sp, 126 +80008424: 93 0b 61 0b addi s7, sp, 182 +80008428: 93 85 0a 79 addi a1, s5, 1936 +8000842c: 13 05 c1 07 addi a0, sp, 124 +80008430: ef e0 8f f0 jal -6392 +80008434: 63 06 05 1a beqz a0, 428 +80008438: 13 07 00 00 mv a4, zero +8000843c: 93 06 0d 00 mv a3, s10 +80008440: 6f 00 c0 01 j 28 +80008444: 13 17 17 00 slli a4, a4, 1 +80008448: 23 90 f6 00 sh a5, 0(a3) +8000844c: 13 17 07 01 slli a4, a4, 16 +80008450: 93 86 e6 ff addi a3, a3, -2 +80008454: 13 57 07 01 srli a4, a4, 16 +80008458: 63 84 86 04 beq a3, s0, 72 +8000845c: 83 d7 06 00 lhu a5, 0(a3) +80008460: 13 96 07 01 slli a2, a5, 16 +80008464: 13 56 06 41 srai a2, a2, 16 +80008468: 93 97 17 00 slli a5, a5, 1 +8000846c: 63 54 06 00 bgez a2, 8 +80008470: 13 67 17 00 ori a4, a4, 1 +80008474: 93 97 07 01 slli a5, a5, 16 +80008478: 93 d7 07 01 srli a5, a5, 16 +8000847c: 13 76 27 00 andi a2, a4, 2 +80008480: 93 e5 17 00 ori a1, a5, 1 +80008484: e3 00 06 fc beqz a2, -64 +80008488: 13 17 17 00 slli a4, a4, 1 +8000848c: 23 90 b6 00 sh a1, 0(a3) +80008490: 13 17 07 01 slli a4, a4, 16 +80008494: 93 86 e6 ff addi a3, a3, -2 +80008498: 13 57 07 01 srli a4, a4, 16 +8000849c: e3 90 86 fc bne a3, s0, -64 +800084a0: 13 07 41 0b addi a4, sp, 180 +800084a4: 93 07 c1 07 addi a5, sp, 124 +800084a8: 83 d6 07 00 lhu a3, 0(a5) +800084ac: 93 87 27 00 addi a5, a5, 2 +800084b0: 13 07 27 00 addi a4, a4, 2 +800084b4: 23 1f d7 fe sh a3, -2(a4) +800084b8: e3 98 a7 ff bne a5, s10, -16 +800084bc: 23 16 01 0c sh zero, 204(sp) +800084c0: 13 07 00 00 mv a4, zero +800084c4: 93 06 c1 0c addi a3, sp, 204 +800084c8: 6f 00 c0 01 j 28 +800084cc: 13 17 17 00 slli a4, a4, 1 +800084d0: 23 90 f6 00 sh a5, 0(a3) +800084d4: 13 17 07 01 slli a4, a4, 16 +800084d8: 93 86 e6 ff addi a3, a3, -2 +800084dc: 13 57 07 01 srli a4, a4, 16 +800084e0: 63 84 76 05 beq a3, s7, 72 +800084e4: 83 d7 06 00 lhu a5, 0(a3) +800084e8: 13 96 07 01 slli a2, a5, 16 +800084ec: 13 56 06 41 srai a2, a2, 16 +800084f0: 93 97 17 00 slli a5, a5, 1 +800084f4: 63 54 06 00 bgez a2, 8 +800084f8: 13 67 17 00 ori a4, a4, 1 +800084fc: 93 97 07 01 slli a5, a5, 16 +80008500: 93 d7 07 01 srli a5, a5, 16 +80008504: 13 76 27 00 andi a2, a4, 2 +80008508: 93 e5 17 00 ori a1, a5, 1 +8000850c: e3 00 06 fc beqz a2, -64 +80008510: 13 17 17 00 slli a4, a4, 1 +80008514: 23 90 b6 00 sh a1, 0(a3) +80008518: 13 17 07 01 slli a4, a4, 16 +8000851c: 93 86 e6 ff addi a3, a3, -2 +80008520: 13 57 07 01 srli a4, a4, 16 +80008524: e3 90 76 fd bne a3, s7, -64 +80008528: 13 07 00 00 mv a4, zero +8000852c: 93 06 c1 0c addi a3, sp, 204 +80008530: 6f 00 c0 01 j 28 +80008534: 13 17 17 00 slli a4, a4, 1 +80008538: 23 90 f6 00 sh a5, 0(a3) +8000853c: 13 17 07 01 slli a4, a4, 16 +80008540: 93 86 e6 ff addi a3, a3, -2 +80008544: 13 57 07 01 srli a4, a4, 16 +80008548: 63 84 76 05 beq a3, s7, 72 +8000854c: 83 d7 06 00 lhu a5, 0(a3) +80008550: 13 96 07 01 slli a2, a5, 16 +80008554: 13 56 06 41 srai a2, a2, 16 +80008558: 93 97 17 00 slli a5, a5, 1 +8000855c: 63 54 06 00 bgez a2, 8 +80008560: 13 67 17 00 ori a4, a4, 1 +80008564: 93 97 07 01 slli a5, a5, 16 +80008568: 93 d7 07 01 srli a5, a5, 16 +8000856c: 13 76 27 00 andi a2, a4, 2 +80008570: 93 e5 17 00 ori a1, a5, 1 +80008574: e3 00 06 fc beqz a2, -64 +80008578: 13 17 17 00 slli a4, a4, 1 +8000857c: 23 90 b6 00 sh a1, 0(a3) +80008580: 13 17 07 01 slli a4, a4, 16 +80008584: 93 86 e6 ff addi a3, a3, -2 +80008588: 13 57 07 01 srli a4, a4, 16 +8000858c: e3 90 76 fd bne a3, s7, -64 +80008590: 13 06 00 00 mv a2, zero +80008594: 93 06 0d 00 mv a3, s10 +80008598: 13 07 c1 0c addi a4, sp, 204 +8000859c: 83 d5 06 00 lhu a1, 0(a3) +800085a0: 83 57 07 00 lhu a5, 0(a4) +800085a4: 93 86 e6 ff addi a3, a3, -2 +800085a8: 13 07 e7 ff addi a4, a4, -2 +800085ac: b3 87 b7 00 add a5, a5, a1 +800085b0: b3 87 c7 00 add a5, a5, a2 +800085b4: 13 d6 07 01 srli a2, a5, 16 +800085b8: 23 91 f6 00 sh a5, 2(a3) +800085bc: 13 76 16 00 andi a2, a2, 1 +800085c0: e3 1e 77 fd bne a4, s7, -36 +800085c4: 13 05 81 09 addi a0, sp, 152 +800085c8: 13 06 09 00 mv a2, s2 +800085cc: 93 05 c1 07 addi a1, sp, 124 +800085d0: ef e0 5f e4 jal -4540 +800085d4: 03 55 c1 1a lhu a0, 428(sp) +800085d8: 93 84 f4 ff addi s1, s1, -1 +800085dc: e3 06 05 e4 beqz a0, -436 +800085e0: 83 27 41 00 lw a5, 4(sp) +800085e4: 83 26 81 00 lw a3, 8(sp) +800085e8: 13 07 30 00 addi a4, zero, 3 +800085ec: b3 37 f0 00 snez a5, a5 +800085f0: b3 07 f0 40 neg a5, a5 +800085f4: 93 f7 d7 00 andi a5, a5, 13 +800085f8: 93 87 07 02 addi a5, a5, 32 +800085fc: 23 02 f1 12 sb a5, 292(sp) +80008600: 83 27 c1 00 lw a5, 12(sp) +80008604: 63 94 e6 00 bne a3, a4, 8 +80008608: b3 87 97 00 add a5, a5, s1 +8000860c: 13 07 a0 02 addi a4, zero, 42 +80008610: 13 84 07 00 mv s0, a5 +80008614: 63 54 f7 00 bge a4, a5, 8 +80008618: 13 04 a0 02 addi s0, zero, 42 +8000861c: 13 07 a0 00 addi a4, zero, 10 +80008620: 63 08 e5 4c beq a0, a4, 1232 +80008624: 13 05 05 03 addi a0, a0, 48 +80008628: 13 07 e0 02 addi a4, zero, 46 +8000862c: a3 02 a1 12 sb a0, 293(sp) +80008630: 23 03 e1 12 sb a4, 294(sp) +80008634: e3 ce 07 1e bltz a5, 2556 +80008638: 93 07 71 12 addi a5, sp, 295 +8000863c: 23 22 f1 00 sw a5, 4(sp) +80008640: 93 0b 00 00 mv s7, zero +80008644: 13 0d 41 0b addi s10, sp, 180 +80008648: 13 0b 41 09 addi s6, sp, 148 +8000864c: 13 0c e1 07 addi s8, sp, 126 +80008650: 93 0d 61 0b addi s11, sp, 182 +80008654: 13 06 00 00 mv a2, zero +80008658: 93 05 0b 00 mv a1, s6 +8000865c: 6f 00 c0 01 j 28 +80008660: 13 16 16 00 slli a2, a2, 1 +80008664: 23 90 f5 00 sh a5, 0(a1) +80008668: 13 16 06 01 slli a2, a2, 16 +8000866c: 93 85 e5 ff addi a1, a1, -2 +80008670: 13 56 06 01 srli a2, a2, 16 +80008674: 63 84 85 05 beq a1, s8, 72 +80008678: 83 d7 05 00 lhu a5, 0(a1) +8000867c: 13 95 07 01 slli a0, a5, 16 +80008680: 13 55 05 41 srai a0, a0, 16 +80008684: 93 97 17 00 slli a5, a5, 1 +80008688: 63 54 05 00 bgez a0, 8 +8000868c: 13 66 16 00 ori a2, a2, 1 +80008690: 93 97 07 01 slli a5, a5, 16 +80008694: 93 d7 07 01 srli a5, a5, 16 +80008698: 13 75 26 00 andi a0, a2, 2 +8000869c: 93 e8 17 00 ori a7, a5, 1 +800086a0: e3 00 05 fc beqz a0, -64 +800086a4: 13 16 16 00 slli a2, a2, 1 +800086a8: 23 90 15 01 sh a7, 0(a1) +800086ac: 13 16 06 01 slli a2, a2, 16 +800086b0: 93 85 e5 ff addi a1, a1, -2 +800086b4: 13 56 06 01 srli a2, a2, 16 +800086b8: e3 90 85 fd bne a1, s8, -64 +800086bc: 13 06 0d 00 mv a2, s10 +800086c0: 93 07 c1 07 addi a5, sp, 124 +800086c4: 83 d5 07 00 lhu a1, 0(a5) +800086c8: 93 87 27 00 addi a5, a5, 2 +800086cc: 13 06 26 00 addi a2, a2, 2 +800086d0: 23 1f b6 fe sh a1, -2(a2) +800086d4: e3 98 67 ff bne a5, s6, -16 +800086d8: 23 16 01 0c sh zero, 204(sp) +800086dc: 13 06 00 00 mv a2, zero +800086e0: 93 05 c1 0c addi a1, sp, 204 +800086e4: 6f 00 c0 01 j 28 +800086e8: 13 16 16 00 slli a2, a2, 1 +800086ec: 23 90 f5 00 sh a5, 0(a1) +800086f0: 13 16 06 01 slli a2, a2, 16 +800086f4: 93 85 e5 ff addi a1, a1, -2 +800086f8: 13 56 06 01 srli a2, a2, 16 +800086fc: 63 84 b5 05 beq a1, s11, 72 +80008700: 83 d7 05 00 lhu a5, 0(a1) +80008704: 13 95 07 01 slli a0, a5, 16 +80008708: 13 55 05 41 srai a0, a0, 16 +8000870c: 93 97 17 00 slli a5, a5, 1 +80008710: 63 54 05 00 bgez a0, 8 +80008714: 13 66 16 00 ori a2, a2, 1 +80008718: 93 97 07 01 slli a5, a5, 16 +8000871c: 93 d7 07 01 srli a5, a5, 16 +80008720: 13 75 26 00 andi a0, a2, 2 +80008724: 93 e8 17 00 ori a7, a5, 1 +80008728: e3 00 05 fc beqz a0, -64 +8000872c: 13 16 16 00 slli a2, a2, 1 +80008730: 23 90 15 01 sh a7, 0(a1) +80008734: 13 16 06 01 slli a2, a2, 16 +80008738: 93 85 e5 ff addi a1, a1, -2 +8000873c: 13 56 06 01 srli a2, a2, 16 +80008740: e3 90 b5 fd bne a1, s11, -64 +80008744: 13 06 00 00 mv a2, zero +80008748: 93 05 c1 0c addi a1, sp, 204 +8000874c: 6f 00 c0 01 j 28 +80008750: 13 16 16 00 slli a2, a2, 1 +80008754: 23 90 f5 00 sh a5, 0(a1) +80008758: 13 16 06 01 slli a2, a2, 16 +8000875c: 93 85 e5 ff addi a1, a1, -2 +80008760: 13 56 06 01 srli a2, a2, 16 +80008764: 63 84 b5 05 beq a1, s11, 72 +80008768: 83 d7 05 00 lhu a5, 0(a1) +8000876c: 13 95 07 01 slli a0, a5, 16 +80008770: 13 55 05 41 srai a0, a0, 16 +80008774: 93 97 17 00 slli a5, a5, 1 +80008778: 63 54 05 00 bgez a0, 8 +8000877c: 13 66 16 00 ori a2, a2, 1 +80008780: 93 97 07 01 slli a5, a5, 16 +80008784: 93 d7 07 01 srli a5, a5, 16 +80008788: 13 75 26 00 andi a0, a2, 2 +8000878c: 93 e8 17 00 ori a7, a5, 1 +80008790: e3 00 05 fc beqz a0, -64 +80008794: 13 16 16 00 slli a2, a2, 1 +80008798: 23 90 15 01 sh a7, 0(a1) +8000879c: 13 16 06 01 slli a2, a2, 16 +800087a0: 93 85 e5 ff addi a1, a1, -2 +800087a4: 13 56 06 01 srli a2, a2, 16 +800087a8: e3 90 b5 fd bne a1, s11, -64 +800087ac: 13 05 00 00 mv a0, zero +800087b0: 93 05 0b 00 mv a1, s6 +800087b4: 13 06 c1 0c addi a2, sp, 204 +800087b8: 83 d8 05 00 lhu a7, 0(a1) +800087bc: 83 57 06 00 lhu a5, 0(a2) +800087c0: 93 85 e5 ff addi a1, a1, -2 +800087c4: 13 06 e6 ff addi a2, a2, -2 +800087c8: b3 87 17 01 add a5, a5, a7 +800087cc: b3 87 a7 00 add a5, a5, a0 +800087d0: 13 d5 07 01 srli a0, a5, 16 +800087d4: 23 91 f5 00 sh a5, 2(a1) +800087d8: 13 75 15 00 andi a0, a0, 1 +800087dc: e3 1e b6 fd bne a2, s11, -36 +800087e0: 13 06 09 00 mv a2, s2 +800087e4: 93 05 c1 07 addi a1, sp, 124 +800087e8: 13 05 81 09 addi a0, sp, 152 +800087ec: ef e0 9f c2 jal -5080 +800087f0: 83 57 c1 1a lhu a5, 428(sp) +800087f4: 03 27 41 00 lw a4, 4(sp) +800087f8: 93 85 07 03 addi a1, a5, 48 +800087fc: 33 06 77 01 add a2, a4, s7 +80008800: 23 00 b6 00 sb a1, 0(a2) +80008804: 93 8b 1b 00 addi s7, s7, 1 +80008808: e3 56 74 e5 bge s0, s7, -436 +8000880c: 13 45 f4 ff not a0, s0 +80008810: 13 55 f5 41 srai a0, a0, 31 +80008814: 33 75 a4 00 and a0, s0, a0 +80008818: 13 09 15 00 addi s2, a0, 1 +8000881c: 33 09 27 01 add s2, a4, s2 +80008820: b3 0b a7 00 add s7, a4, a0 +80008824: 13 07 40 00 addi a4, zero, 4 +80008828: 63 5e f7 04 bge a4, a5, 92 +8000882c: 13 07 50 00 addi a4, zero, 5 +80008830: e3 86 e7 02 beq a5, a4, 2092 +80008834: 83 47 e9 ff lbu a5, -2(s2) +80008838: 13 07 e9 ff addi a4, s2, -2 +8000883c: 93 f7 f7 07 andi a5, a5, 127 +80008840: 63 4a 04 7a bltz s0, 1972 +80008844: 93 06 e0 02 addi a3, zero, 46 +80008848: 13 06 80 03 addi a2, zero, 56 +8000884c: 93 05 00 03 addi a1, zero, 48 +80008850: 63 8e d7 00 beq a5, a3, 28 +80008854: 63 58 f6 7a bge a2, a5, 1968 +80008858: 83 47 f7 ff lbu a5, -1(a4) +8000885c: 23 00 b7 00 sb a1, 0(a4) +80008860: 13 07 f7 ff addi a4, a4, -1 +80008864: 93 f7 f7 07 andi a5, a5, 127 +80008868: 6f f0 9f fe j -24 +8000886c: 83 47 f7 ff lbu a5, -1(a4) +80008870: 93 06 80 03 addi a3, zero, 56 +80008874: e3 fa f6 02 bgeu a3, a5, 2100 +80008878: 93 07 10 03 addi a5, zero, 49 +8000887c: 93 84 14 00 addi s1, s1, 1 +80008880: a3 0f f7 fe sb a5, -1(a4) +80008884: b7 55 01 80 lui a1, 524309 +80008888: 13 86 04 00 mv a2, s1 +8000888c: 93 85 c5 78 addi a1, a1, 1932 +80008890: 13 85 0b 00 mv a0, s7 +80008894: ef 20 c0 6a jal 9900 +80008898: 83 57 21 07 lhu a5, 114(sp) +8000889c: 03 27 81 01 lw a4, 24(sp) +800088a0: 23 28 91 16 sw s1, 368(sp) +800088a4: 93 c7 f7 ff not a5, a5 +800088a8: 23 22 e1 16 sw a4, 356(sp) +800088ac: 13 97 17 01 slli a4, a5, 17 +800088b0: 63 1e 07 00 bnez a4, 28 +800088b4: 13 85 09 00 mv a0, s3 +800088b8: ef e0 cf b9 jal -7268 +800088bc: 63 10 05 22 bnez a0, 544 +800088c0: 13 85 09 00 mv a0, s3 +800088c4: ef e0 cf 8c jal -7988 +800088c8: 63 1a 05 20 bnez a0, 532 +800088cc: 83 26 41 01 lw a3, 20(sp) +800088d0: 03 47 41 12 lbu a4, 292(sp) +800088d4: 93 87 14 00 addi a5, s1, 1 +800088d8: 23 a0 f6 00 sw a5, 0(a3) +800088dc: 93 87 0c 00 mv a5, s9 +800088e0: 63 0a 07 02 beqz a4, 52 +800088e4: 93 06 e0 02 addi a3, zero, 46 +800088e8: 63 0c d7 1c beq a4, a3, 472 +800088ec: 03 c7 17 00 lbu a4, 1(a5) +800088f0: 93 87 17 00 addi a5, a5, 1 +800088f4: e3 1a 07 fe bnez a4, -12 +800088f8: 93 06 50 04 addi a3, zero, 69 +800088fc: 63 e6 fc 00 bltu s9, a5, 12 +80008900: 6f 00 40 01 j 20 +80008904: 63 88 97 01 beq a5, s9, 16 +80008908: 03 c7 f7 ff lbu a4, -1(a5) +8000890c: 93 87 f7 ff addi a5, a5, -1 +80008910: e3 1a d7 fe bne a4, a3, -12 +80008914: 23 80 07 00 sb zero, 0(a5) +80008918: 93 87 0c 00 mv a5, s9 +8000891c: 93 06 00 02 addi a3, zero, 32 +80008920: 13 06 d0 02 addi a2, zero, 45 +80008924: 03 c7 07 00 lbu a4, 0(a5) +80008928: 63 04 d7 00 beq a4, a3, 8 +8000892c: 63 16 c7 00 bne a4, a2, 12 +80008930: 93 87 17 00 addi a5, a5, 1 +80008934: 6f f0 1f ff j -16 +80008938: 13 84 0c 00 mv s0, s9 +8000893c: 6f 00 c0 00 j 12 +80008940: 03 c7 07 00 lbu a4, 0(a5) +80008944: 13 84 06 00 mv s0, a3 +80008948: 23 00 e4 00 sb a4, 0(s0) +8000894c: 93 06 14 00 addi a3, s0, 1 +80008950: 93 87 17 00 addi a5, a5, 1 +80008954: e3 16 07 fe bnez a4, -20 +80008958: 83 26 81 00 lw a3, 8(sp) +8000895c: 93 07 20 00 addi a5, zero, 2 +80008960: 03 47 f4 ff lbu a4, -1(s0) +80008964: 63 86 f6 12 beq a3, a5, 300 +80008968: 83 27 c1 00 lw a5, 12(sp) +8000896c: 93 86 07 00 mv a3, a5 +80008970: 63 d4 97 00 bge a5, s1, 8 +80008974: 93 86 04 00 mv a3, s1 +80008978: 93 07 00 03 addi a5, zero, 48 +8000897c: 63 16 f7 02 bne a4, a5, 44 +80008980: b3 07 94 41 sub a5, s0, s9 +80008984: 63 d2 f6 02 bge a3, a5, 36 +80008988: 13 06 00 03 addi a2, zero, 48 +8000898c: 6f 00 80 00 j 8 +80008990: 63 dc e6 00 bge a3, a4, 24 +80008994: 83 47 e4 ff lbu a5, -2(s0) +80008998: a3 0f 04 fe sb zero, -1(s0) +8000899c: 13 04 f4 ff addi s0, s0, -1 +800089a0: 33 07 94 41 sub a4, s0, s9 +800089a4: e3 86 c7 fe beq a5, a2, -20 +800089a8: 03 27 81 00 lw a4, 8(sp) +800089ac: 93 07 30 00 addi a5, zero, 3 +800089b0: 63 02 f7 0a beq a4, a5, 164 +800089b4: 83 27 01 01 lw a5, 16(sp) +800089b8: 23 22 0a 04 sw zero, 68(s4) +800089bc: 93 86 97 00 addi a3, a5, 9 +800089c0: 93 07 70 01 addi a5, zero, 23 +800089c4: 63 f2 d7 0c bgeu a5, a3, 196 +800089c8: 13 07 10 00 addi a4, zero, 1 +800089cc: 93 07 40 00 addi a5, zero, 4 +800089d0: 93 97 17 00 slli a5, a5, 1 +800089d4: 13 86 47 01 addi a2, a5, 20 +800089d8: 93 05 07 00 mv a1, a4 +800089dc: 13 07 17 00 addi a4, a4, 1 +800089e0: e3 f8 c6 fe bgeu a3, a2, -16 +800089e4: 23 22 ba 04 sw a1, 68(s4) +800089e8: 13 05 0a 00 mv a0, s4 +800089ec: ef 10 80 28 jal 4744 +800089f0: 23 20 aa 04 sw a0, 64(s4) +800089f4: 93 85 0c 00 mv a1, s9 +800089f8: 93 04 05 00 mv s1, a0 +800089fc: ef 20 00 5c jal 9664 +80008a00: 83 27 c1 01 lw a5, 28(sp) +80008a04: 63 88 07 00 beqz a5, 16 +80008a08: 33 04 94 41 sub s0, s0, s9 +80008a0c: 33 84 84 00 add s0, s1, s0 +80008a10: 23 a0 87 00 sw s0, 0(a5) +80008a14: 83 20 c1 1e lw ra, 492(sp) +80008a18: 03 24 81 1e lw s0, 488(sp) +80008a1c: 03 29 01 1e lw s2, 480(sp) +80008a20: 83 29 c1 1d lw s3, 476(sp) +80008a24: 03 2a 81 1d lw s4, 472(sp) +80008a28: 83 2a 41 1d lw s5, 468(sp) +80008a2c: 03 2b 01 1d lw s6, 464(sp) +80008a30: 83 2b c1 1c lw s7, 460(sp) +80008a34: 03 2c 81 1c lw s8, 456(sp) +80008a38: 83 2c 41 1c lw s9, 452(sp) +80008a3c: 03 2d 01 1c lw s10, 448(sp) +80008a40: 83 2d c1 1b lw s11, 444(sp) +80008a44: 13 85 04 00 mv a0, s1 +80008a48: 83 24 41 1e lw s1, 484(sp) +80008a4c: 13 01 01 1f addi sp, sp, 496 +80008a50: 67 80 00 00 ret +80008a54: 83 27 c1 00 lw a5, 12(sp) +80008a58: b3 84 97 00 add s1, a5, s1 +80008a5c: 63 ce 04 52 bltz s1, 1340 +80008a60: 83 27 41 01 lw a5, 20(sp) +80008a64: 03 27 01 01 lw a4, 16(sp) +80008a68: 83 a7 07 00 lw a5, 0(a5) +80008a6c: b3 07 f7 00 add a5, a4, a5 +80008a70: 23 28 f1 00 sw a5, 16(sp) +80008a74: 83 27 01 01 lw a5, 16(sp) +80008a78: 23 22 0a 04 sw zero, 68(s4) +80008a7c: 93 86 37 00 addi a3, a5, 3 +80008a80: 93 07 70 01 addi a5, zero, 23 +80008a84: e3 e2 d7 f4 bltu a5, a3, -188 +80008a88: 93 05 00 00 mv a1, zero +80008a8c: 6f f0 df f5 j -164 +80008a90: 93 07 00 03 addi a5, zero, 48 +80008a94: e3 10 f7 f2 bne a4, a5, -224 +80008a98: b3 07 94 41 sub a5, s0, s9 +80008a9c: 93 06 10 00 addi a3, zero, 1 +80008aa0: e3 c4 f6 ee blt a3, a5, -280 +80008aa4: 6f f0 1f f1 j -240 +80008aa8: 03 2c 01 01 lw s8, 16(sp) +80008aac: 23 26 81 01 sw s8, 12(sp) +80008ab0: 93 07 a0 02 addi a5, zero, 42 +80008ab4: 63 d0 87 ed bge a5, s8, -2368 +80008ab8: 23 26 f1 00 sw a5, 12(sp) +80008abc: 6f f0 8f eb j -2376 +80008ac0: 03 c7 07 00 lbu a4, 0(a5) +80008ac4: e3 0a 07 e2 beqz a4, -460 +80008ac8: 03 c7 17 00 lbu a4, 1(a5) +80008acc: 93 87 17 00 addi a5, a5, 1 +80008ad0: a3 8f e7 fe sb a4, -1(a5) +80008ad4: e3 1a 07 fe bnez a4, -12 +80008ad8: 6f f0 1f e2 j -480 +80008adc: 03 27 41 01 lw a4, 20(sp) +80008ae0: b7 27 00 00 lui a5, 2 +80008ae4: 93 87 f7 70 addi a5, a5, 1807 +80008ae8: 23 20 f7 00 sw a5, 0(a4) +80008aec: 6f f0 df e2 j -468 +80008af0: 13 07 10 03 addi a4, zero, 49 +80008af4: a3 02 e1 12 sb a4, 293(sp) +80008af8: 13 07 e0 02 addi a4, zero, 46 +80008afc: 23 03 e1 12 sb a4, 294(sp) +80008b00: 93 84 14 00 addi s1, s1, 1 +80008b04: 63 5e f0 2a blez a5, 700 +80008b08: 93 07 00 03 addi a5, zero, 48 +80008b0c: a3 03 f1 12 sb a5, 295(sp) +80008b10: 93 07 81 12 addi a5, sp, 296 +80008b14: 13 04 f4 ff addi s0, s0, -1 +80008b18: 23 22 f1 00 sw a5, 4(sp) +80008b1c: 6f f0 5f b2 j -1244 +80008b20: 13 0d 41 0b addi s10, sp, 180 +80008b24: 13 07 0d 00 mv a4, s10 +80008b28: 93 07 c1 07 addi a5, sp, 124 +80008b2c: 13 06 01 09 addi a2, sp, 144 +80008b30: 83 d6 07 00 lhu a3, 0(a5) +80008b34: 93 87 27 00 addi a5, a5, 2 +80008b38: 13 07 27 00 addi a4, a4, 2 +80008b3c: 23 1f d7 fe sh a3, -2(a4) +80008b40: e3 98 c7 fe bne a5, a2, -16 +80008b44: b7 47 00 00 lui a5, 4 +80008b48: 93 87 e7 08 addi a5, a5, 142 +80008b4c: 23 13 f1 0c sh a5, 198(sp) +80008b50: b7 57 01 80 lui a5, 524309 +80008b54: 93 87 07 79 addi a5, a5, 1936 +80008b58: 13 8b 87 0c addi s6, a5, 200 +80008b5c: b7 87 00 00 lui a5, 8 +80008b60: 93 87 f7 ff addi a5, a5, -1 +80008b64: 23 22 f1 02 sw a5, 36(sp) +80008b68: b7 c7 ff ff lui a5, 1048572 +80008b6c: 93 87 27 00 addi a5, a5, 2 +80008b70: 13 0e 00 01 addi t3, zero, 16 +80008b74: 93 04 00 00 mv s1, zero +80008b78: 93 0c 41 12 addi s9, sp, 292 +80008b7c: 13 09 01 16 addi s2, sp, 352 +80008b80: 13 04 01 0d addi s0, sp, 208 +80008b84: 13 0c a1 0a addi s8, sp, 170 +80008b88: 23 24 f1 02 sw a5, 40(sp) +80008b8c: 93 06 09 00 mv a3, s2 +80008b90: 13 06 81 09 addi a2, sp, 152 +80008b94: 93 05 0d 00 mv a1, s10 +80008b98: 13 05 0b 00 mv a0, s6 +80008b9c: 23 20 c1 03 sw t3, 32(sp) +80008ba0: ef e0 5f ea jal -4444 +80008ba4: 03 2e 01 02 lw t3, 32(sp) +80008ba8: 13 07 c1 04 addi a4, sp, 76 +80008bac: 93 07 81 09 addi a5, sp, 152 +80008bb0: 83 d6 07 00 lhu a3, 0(a5) +80008bb4: 93 87 27 00 addi a5, a5, 2 +80008bb8: 13 07 27 00 addi a4, a4, 2 +80008bbc: 23 1f d7 fe sh a3, -2(a4) +80008bc0: e3 98 b7 ff bne a5, s11, -16 +80008bc4: 83 27 41 02 lw a5, 36(sp) +80008bc8: 83 55 e1 05 lhu a1, 94(sp) +80008bcc: 33 f6 f5 00 and a2, a1, a5 +80008bd0: 83 27 81 02 lw a5, 40(sp) +80008bd4: 33 05 f6 00 add a0, a2, a5 +80008bd8: 63 5a a0 3c blez a0, 980 +80008bdc: 13 06 00 09 addi a2, zero, 144 +80008be0: 33 06 a6 40 sub a2, a2, a0 +80008be4: 13 07 04 00 mv a4, s0 +80008be8: 93 07 c1 04 addi a5, sp, 76 +80008bec: 83 d6 07 00 lhu a3, 0(a5) +80008bf0: 93 87 27 00 addi a5, a5, 2 +80008bf4: 13 07 27 00 addi a4, a4, 2 +80008bf8: 23 1f d7 fe sh a3, -2(a4) +80008bfc: e3 98 37 ff bne a5, s3, -16 +80008c00: 63 58 c0 06 blez a2, 112 +80008c04: 93 07 f0 00 addi a5, zero, 15 +80008c08: 13 07 04 00 mv a4, s0 +80008c0c: 63 dc c7 02 bge a5, a2, 56 +80008c10: 13 06 06 ff addi a2, a2, -16 +80008c14: 93 56 46 00 srli a3, a2, 4 +80008c18: 13 87 16 00 addi a4, a3, 1 +80008c1c: 13 17 17 00 slli a4, a4, 1 +80008c20: 33 07 e4 00 add a4, s0, a4 +80008c24: 93 07 04 00 mv a5, s0 +80008c28: 93 87 27 00 addi a5, a5, 2 +80008c2c: 23 9f 07 fe sh zero, -2(a5) +80008c30: e3 9c e7 fe bne a5, a4, -8 +80008c34: 13 06 00 08 addi a2, zero, 128 +80008c38: 33 06 a6 40 sub a2, a2, a0 +80008c3c: 93 96 46 00 slli a3, a3, 4 +80008c40: 33 06 d6 40 sub a2, a2, a3 +80008c44: b7 57 01 80 lui a5, 524309 +80008c48: 93 87 07 79 addi a5, a5, 1936 +80008c4c: 13 16 16 00 slli a2, a2, 1 +80008c50: 33 86 c7 00 add a2, a5, a2 +80008c54: 83 56 06 23 lhu a3, 560(a2) +80008c58: 83 57 07 00 lhu a5, 0(a4) +80008c5c: b3 f7 d7 00 and a5, a5, a3 +80008c60: 23 10 f7 00 sh a5, 0(a4) +80008c64: 93 95 05 01 slli a1, a1, 16 +80008c68: 93 d5 05 41 srai a1, a1, 16 +80008c6c: 63 c2 05 16 bltz a1, 356 +80008c70: 93 07 81 09 addi a5, sp, 152 +80008c74: 13 07 04 00 mv a4, s0 +80008c78: 03 d6 07 00 lhu a2, 0(a5) +80008c7c: 83 56 07 00 lhu a3, 0(a4) +80008c80: 93 87 27 00 addi a5, a5, 2 +80008c84: 13 07 27 00 addi a4, a4, 2 +80008c88: 63 14 d6 02 bne a2, a3, 40 +80008c8c: e3 16 fc fe bne s8, a5, -20 +80008c90: 13 07 0d 00 mv a4, s10 +80008c94: 93 07 81 09 addi a5, sp, 152 +80008c98: 83 d6 07 00 lhu a3, 0(a5) +80008c9c: 93 87 27 00 addi a5, a5, 2 +80008ca0: 13 07 27 00 addi a4, a4, 2 +80008ca4: 23 1f d7 fe sh a3, -2(a4) +80008ca8: e3 98 b7 ff bne a5, s11, -16 +80008cac: b3 84 c4 01 add s1, s1, t3 +80008cb0: b7 57 01 80 lui a5, 524309 +80008cb4: 93 87 07 79 addi a5, a5, 1936 +80008cb8: 13 0b 4b 01 addi s6, s6, 20 +80008cbc: 93 87 c7 12 addi a5, a5, 300 +80008cc0: 13 5e 1e 00 srli t3, t3, 1 +80008cc4: e3 14 fb ec bne s6, a5, -312 +80008cc8: 83 57 61 0c lhu a5, 198(sp) +80008ccc: 03 57 e1 08 lhu a4, 142(sp) +80008cd0: 13 06 81 0c addi a2, sp, 200 +80008cd4: b3 87 e7 00 add a5, a5, a4 +80008cd8: 37 c7 ff ff lui a4, 1048572 +80008cdc: 13 07 27 f7 addi a4, a4, -142 +80008ce0: b3 87 e7 00 add a5, a5, a4 +80008ce4: 23 13 f1 0c sh a5, 198(sp) +80008ce8: 13 07 c1 07 addi a4, sp, 124 +80008cec: 93 07 0d 00 mv a5, s10 +80008cf0: 83 d6 07 00 lhu a3, 0(a5) +80008cf4: 93 87 27 00 addi a5, a5, 2 +80008cf8: 13 07 27 00 addi a4, a4, 2 +80008cfc: 23 1f d7 fe sh a3, -2(a4) +80008d00: e3 98 c7 fe bne a5, a2, -16 +80008d04: 13 07 00 00 mv a4, zero +80008d08: 93 07 81 09 addi a5, sp, 152 +80008d0c: 6f 00 80 00 j 8 +80008d10: 03 d7 0b 00 lhu a4, 0(s7) +80008d14: 93 87 27 00 addi a5, a5, 2 +80008d18: 23 9f e7 fe sh a4, -2(a5) +80008d1c: 93 8b 2b 00 addi s7, s7, 2 +80008d20: e3 98 b7 ff bne a5, s11, -16 +80008d24: b7 57 01 80 lui a5, 524309 +80008d28: 13 87 07 79 addi a4, a5, 1936 +80008d2c: 93 87 07 79 addi a5, a5, 1936 +80008d30: b7 1d 00 00 lui s11, 1 +80008d34: 13 0b 87 02 addi s6, a4, 40 +80008d38: 93 8b 87 11 addi s7, a5, 280 +80008d3c: 6f 00 00 01 j 16 +80008d40: 93 dd 1d 00 srli s11, s11, 1 +80008d44: 63 04 7b 2b beq s6, s7, 680 +80008d48: 13 0b 4b 01 addi s6, s6, 20 +80008d4c: 93 05 0d 00 mv a1, s10 +80008d50: 13 85 0b 00 mv a0, s7 +80008d54: ef d0 5f de jal -8732 +80008d58: 13 07 05 00 mv a4, a0 +80008d5c: 93 05 0d 00 mv a1, s10 +80008d60: 13 05 0b 00 mv a0, s6 +80008d64: 63 44 e0 28 bgtz a4, 648 +80008d68: ef d0 1f dd jal -8752 +80008d6c: e3 4a a0 fc bgtz a0, -44 +80008d70: 93 06 09 00 mv a3, s2 +80008d74: 13 06 0d 00 mv a2, s10 +80008d78: 93 05 0d 00 mv a1, s10 +80008d7c: 13 05 0b 00 mv a0, s6 +80008d80: ef e0 5f cc jal -4924 +80008d84: 13 06 81 09 addi a2, sp, 152 +80008d88: 93 06 09 00 mv a3, s2 +80008d8c: 93 05 06 00 mv a1, a2 +80008d90: 13 05 0b 00 mv a0, s6 +80008d94: ef e0 9f 89 jal -5992 +80008d98: b3 84 b4 01 add s1, s1, s11 +80008d9c: 6f f0 5f fa j -92 +80008da0: 93 0c 41 12 addi s9, sp, 292 +80008da4: b7 55 01 80 lui a1, 524309 +80008da8: 93 85 85 76 addi a1, a1, 1896 +80008dac: 13 85 0c 00 mv a0, s9 +80008db0: b7 24 00 00 lui s1, 2 +80008db4: ef 20 c0 18 jal 8588 +80008db8: 93 84 f4 70 addi s1, s1, 1807 +80008dbc: 6f f0 df ad j -1316 +80008dc0: 93 0b 71 12 addi s7, sp, 295 +80008dc4: e3 90 07 ac bnez a5, -1344 +80008dc8: 23 22 71 01 sw s7, 4(sp) +80008dcc: 6f f0 5f 87 j -1932 +80008dd0: 93 07 c1 04 addi a5, sp, 76 +80008dd4: 13 07 04 00 mv a4, s0 +80008dd8: 6f 00 c0 00 j 12 +80008ddc: 93 06 e1 05 addi a3, sp, 94 +80008de0: e3 88 f6 e8 beq a3, a5, -368 +80008de4: 03 d6 07 00 lhu a2, 0(a5) +80008de8: 83 56 07 00 lhu a3, 0(a4) +80008dec: 93 87 27 00 addi a5, a5, 2 +80008df0: 13 07 27 00 addi a4, a4, 2 +80008df4: e3 04 d6 fe beq a2, a3, -24 +80008df8: 83 57 21 0e lhu a5, 226(sp) +80008dfc: 03 27 41 02 lw a4, 36(sp) +80008e00: b3 77 f7 00 and a5, a4, a5 +80008e04: 63 94 e7 02 bne a5, a4, 40 +80008e08: 13 05 04 00 mv a0, s0 +80008e0c: 23 20 c1 03 sw t3, 32(sp) +80008e10: ef d0 1f b8 jal -9344 +80008e14: 03 2e 01 02 lw t3, 32(sp) +80008e18: e3 1c 05 e4 bnez a0, -424 +80008e1c: 13 05 04 00 mv a0, s0 +80008e20: ef d0 5f e3 jal -8652 +80008e24: 03 2e 01 02 lw t3, 32(sp) +80008e28: e3 14 05 e4 bnez a0, -440 +80008e2c: 93 05 c1 0e addi a1, sp, 236 +80008e30: 13 85 0b 00 mv a0, s7 +80008e34: 23 20 c1 03 sw t3, 32(sp) +80008e38: ef d0 9f c0 jal -9208 +80008e3c: 93 05 81 10 addi a1, sp, 264 +80008e40: 13 05 04 00 mv a0, s0 +80008e44: ef d0 df bf jal -9220 +80008e48: 03 56 c1 0e lhu a2, 236(sp) +80008e4c: 03 55 a1 10 lhu a0, 266(sp) +80008e50: 83 5e e1 0e lhu t4, 238(sp) +80008e54: 13 46 f6 ff not a2, a2 +80008e58: 13 16 06 01 slli a2, a2, 16 +80008e5c: 13 56 06 01 srli a2, a2, 16 +80008e60: 23 16 c1 0e sh a2, 236(sp) +80008e64: b3 85 ae 40 sub a1, t4, a0 +80008e68: 03 2e 01 02 lw t3, 32(sp) +80008e6c: 93 06 05 00 mv a3, a0 +80008e70: 63 5e b0 06 blez a1, 124 +80008e74: 93 86 0c 00 mv a3, s9 +80008e78: 13 07 81 10 addi a4, sp, 264 +80008e7c: 93 07 01 12 addi a5, sp, 288 +80008e80: 83 55 07 00 lhu a1, 0(a4) +80008e84: 13 07 27 00 addi a4, a4, 2 +80008e88: 93 86 26 00 addi a3, a3, 2 +80008e8c: 23 9f b6 fe sh a1, -2(a3) +80008e90: e3 18 f7 fe bne a4, a5, -16 +80008e94: 23 1e 01 12 sh zero, 316(sp) +80008e98: 13 07 81 10 addi a4, sp, 264 +80008e9c: 93 06 c1 0e addi a3, sp, 236 +80008ea0: 6f 00 80 00 j 8 +80008ea4: 03 d6 06 00 lhu a2, 0(a3) +80008ea8: 13 07 27 00 addi a4, a4, 2 +80008eac: 23 1f c7 fe sh a2, -2(a4) +80008eb0: 93 86 26 00 addi a3, a3, 2 +80008eb4: e3 18 f7 fe bne a4, a5, -16 +80008eb8: 23 10 01 12 sh zero, 288(sp) +80008ebc: 13 07 c1 0e addi a4, sp, 236 +80008ec0: 93 87 0c 00 mv a5, s9 +80008ec4: 13 0f c1 13 addi t5, sp, 316 +80008ec8: 83 d6 07 00 lhu a3, 0(a5) +80008ecc: 93 87 27 00 addi a5, a5, 2 +80008ed0: 13 07 27 00 addi a4, a4, 2 +80008ed4: 23 1f d7 fe sh a3, -2(a4) +80008ed8: e3 98 e7 ff bne a5, t5, -16 +80008edc: 83 56 a1 10 lhu a3, 266(sp) +80008ee0: b3 05 d5 41 sub a1, a0, t4 +80008ee4: 23 12 01 10 sh zero, 260(sp) +80008ee8: 13 85 06 00 mv a0, a3 +80008eec: 63 80 05 2e beqz a1, 736 +80008ef0: 23 26 d1 02 sw a3, 44(sp) +80008ef4: 93 07 f0 f6 addi a5, zero, -145 +80008ef8: 63 ce f5 06 blt a1, a5, 124 +80008efc: 13 05 c1 0e addi a0, sp, 236 +80008f00: 23 20 c1 03 sw t3, 32(sp) +80008f04: ef d0 df d6 jal -8852 +80008f08: 03 2e 01 02 lw t3, 32(sp) +80008f0c: 83 26 c1 02 lw a3, 44(sp) +80008f10: 93 05 05 00 mv a1, a0 +80008f14: 93 07 01 12 addi a5, sp, 288 +80008f18: 13 06 41 10 addi a2, sp, 260 +80008f1c: 03 55 c1 0e lhu a0, 236(sp) +80008f20: 03 57 81 10 lhu a4, 264(sp) +80008f24: 63 00 e5 30 beq a0, a4, 768 +80008f28: 13 05 00 00 mv a0, zero +80008f2c: 03 d7 07 00 lhu a4, 0(a5) +80008f30: 83 5e 06 00 lhu t4, 0(a2) +80008f34: 93 87 e7 ff addi a5, a5, -2 +80008f38: 33 07 a7 40 sub a4, a4, a0 +80008f3c: 33 07 d7 41 sub a4, a4, t4 +80008f40: 13 55 07 01 srli a0, a4, 16 +80008f44: 23 91 e7 00 sh a4, 2(a5) +80008f48: 13 07 a1 10 addi a4, sp, 266 +80008f4c: 13 75 15 00 andi a0, a0, 1 +80008f50: 13 06 e6 ff addi a2, a2, -2 +80008f54: e3 9c e7 fc bne a5, a4, -40 +80008f58: 13 06 10 00 addi a2, zero, 1 +80008f5c: 93 07 09 00 mv a5, s2 +80008f60: 13 07 00 04 addi a4, zero, 64 +80008f64: 13 05 81 10 addi a0, sp, 264 +80008f68: 23 20 c1 03 sw t3, 32(sp) +80008f6c: ef e0 cf 89 jal -8036 +80008f70: 03 2e 01 02 lw t3, 32(sp) +80008f74: 93 05 04 00 mv a1, s0 +80008f78: 13 05 81 10 addi a0, sp, 264 +80008f7c: 23 20 c1 03 sw t3, 32(sp) +80008f80: ef e0 cf df jal -6660 +80008f84: 03 2e 01 02 lw t3, 32(sp) +80008f88: 6f f0 9f ce j -792 +80008f8c: 83 27 01 01 lw a5, 16(sp) +80008f90: 13 8c f7 ff addi s8, a5, -1 +80008f94: 6f f0 9f b1 j -1256 +80008f98: 83 27 41 01 lw a5, 20(sp) +80008f9c: 23 02 01 12 sb zero, 292(sp) +80008fa0: 13 84 0c 00 mv s0, s9 +80008fa4: 23 a0 07 00 sw zero, 0(a5) +80008fa8: 6f f0 df ac j -1332 +80008fac: 93 07 04 00 mv a5, s0 +80008fb0: 13 07 41 0e addi a4, sp, 228 +80008fb4: 93 87 27 00 addi a5, a5, 2 +80008fb8: 23 9f 07 fe sh zero, -2(a5) +80008fbc: e3 9c e7 fe bne a5, a4, -8 +80008fc0: 6f f0 5f ca j -860 +80008fc4: 83 27 41 00 lw a5, 4(sp) +80008fc8: 93 0c 41 12 addi s9, sp, 292 +80008fcc: 63 8a 07 06 beqz a5, 116 +80008fd0: b7 55 01 80 lui a1, 524309 +80008fd4: 93 85 05 77 addi a1, a1, 1904 +80008fd8: 13 85 0c 00 mv a0, s9 +80008fdc: b7 24 00 00 lui s1, 2 +80008fe0: ef 10 10 76 jal 8032 +80008fe4: 93 84 f4 70 addi s1, s1, 1807 +80008fe8: 6f f0 1f 8b j -1872 +80008fec: 13 0b 81 0e addi s6, sp, 232 +80008ff0: 6f f0 0f bc j -3136 +80008ff4: 93 07 10 03 addi a5, zero, 49 +80008ff8: 23 0f f9 fe sb a5, -2(s2) +80008ffc: 93 84 14 00 addi s1, s1, 1 +80009000: 6f f0 5f 88 j -1916 +80009004: 93 87 17 00 addi a5, a5, 1 +80009008: 23 00 f7 00 sb a5, 0(a4) +8000900c: 6f f0 9f 87 j -1928 +80009010: 93 0c 41 12 addi s9, sp, 292 +80009014: b7 55 01 80 lui a1, 524309 +80009018: 93 85 85 78 addi a1, a1, 1928 +8000901c: 13 85 0c 00 mv a0, s9 +80009020: b7 24 00 00 lui s1, 2 +80009024: ef 10 d0 71 jal 7964 +80009028: 93 84 f4 70 addi s1, s1, 1807 +8000902c: 6f f0 df 86 j -1940 +80009030: 83 57 c1 1a lhu a5, 428(sp) +80009034: 93 0b 61 12 addi s7, sp, 294 +80009038: 13 09 71 12 addi s2, sp, 295 +8000903c: 6f f0 8f fe j -2072 +80009040: b7 55 01 80 lui a1, 524309 +80009044: 93 85 c5 77 addi a1, a1, 1916 +80009048: 13 85 0c 00 mv a0, s9 +8000904c: b7 24 00 00 lui s1, 2 +80009050: ef 10 10 6f jal 7920 +80009054: 93 84 f4 70 addi s1, s1, 1807 +80009058: 6f f0 1f 84 j -1984 +8000905c: 93 05 81 09 addi a1, sp, 152 +80009060: 13 05 c1 07 addi a0, sp, 124 +80009064: ef e0 8f d1 jal -6888 +80009068: 93 85 0a 79 addi a1, s5, 1936 +8000906c: 13 05 81 09 addi a0, sp, 152 +80009070: ef d0 9f ac jal -9528 +80009074: 63 10 05 fc bnez a0, -2112 +80009078: e3 46 04 80 bltz s0, -2036 +8000907c: 83 47 e9 ff lbu a5, -2(s2) +80009080: 13 87 27 fd addi a4, a5, -46 +80009084: 13 37 17 00 seqz a4, a4 +80009088: 13 47 f7 ff not a4, a4 +8000908c: 33 87 eb 00 add a4, s7, a4 +80009090: 03 47 07 00 lbu a4, 0(a4) +80009094: 13 77 17 00 andi a4, a4, 1 +80009098: 63 06 07 fe beqz a4, -2068 +8000909c: 13 07 e9 ff addi a4, s2, -2 +800090a0: 93 f7 f7 07 andi a5, a5, 127 +800090a4: 6f f0 0f fa j -2144 +800090a8: 93 87 17 00 addi a5, a5, 1 +800090ac: a3 0f f7 fe sb a5, -1(a4) +800090b0: 6f f0 4f fd j -2092 +800090b4: 13 04 01 0d addi s0, sp, 208 +800090b8: 93 05 04 00 mv a1, s0 +800090bc: 13 05 c1 07 addi a0, sp, 124 +800090c0: 37 4d 00 00 lui s10, 4 +800090c4: ef d0 df 97 jal -9860 +800090c8: 93 04 00 00 mv s1, zero +800090cc: 13 0b 81 0e addi s6, sp, 232 +800090d0: 13 09 c1 0c addi s2, sp, 204 +800090d4: 93 0c 21 0d addi s9, sp, 210 +800090d8: 13 0d ed ff addi s10, s10, -2 +800090dc: 13 0c 50 fd addi s8, zero, -43 +800090e0: 83 57 81 0e lhu a5, 232(sp) +800090e4: 93 f7 77 00 andi a5, a5, 7 +800090e8: 63 98 07 0c bnez a5, 208 +800090ec: 13 07 41 0b addi a4, sp, 180 +800090f0: 93 07 04 00 mv a5, s0 +800090f4: 83 d6 07 00 lhu a3, 0(a5) +800090f8: 93 87 27 00 addi a5, a5, 2 +800090fc: 13 07 27 00 addi a4, a4, 2 +80009100: 23 1f d7 fe sh a3, -2(a4) +80009104: e3 98 67 ff bne a5, s6, -16 +80009108: 13 05 41 0b addi a0, sp, 180 +8000910c: 23 16 01 0c sh zero, 204(sp) +80009110: ef d0 0f f1 jal -10480 +80009114: 13 05 41 0b addi a0, sp, 180 +80009118: ef d0 8f f0 jal -10488 +8000911c: 13 06 00 00 mv a2, zero +80009120: 93 06 09 00 mv a3, s2 +80009124: 13 07 0b 00 mv a4, s6 +80009128: 83 d5 06 00 lhu a1, 0(a3) +8000912c: 83 57 07 00 lhu a5, 0(a4) +80009130: 93 86 e6 ff addi a3, a3, -2 +80009134: 13 07 e7 ff addi a4, a4, -2 +80009138: b3 87 b7 00 add a5, a5, a1 +8000913c: b3 87 c7 00 add a5, a5, a2 +80009140: 13 d6 07 01 srli a2, a5, 16 +80009144: 23 91 f6 00 sh a5, 2(a3) +80009148: 13 76 16 00 andi a2, a2, 1 +8000914c: e3 1e 97 fd bne a4, s9, -36 +80009150: 83 57 61 0b lhu a5, 182(sp) +80009154: 03 57 81 0b lhu a4, 184(sp) +80009158: 93 87 37 00 addi a5, a5, 3 +8000915c: 23 1b f1 0a sh a5, 182(sp) +80009160: 63 00 07 02 beqz a4, 32 +80009164: 13 05 41 0b addi a0, sp, 180 +80009168: ef d0 8f eb jal -10568 +8000916c: 83 57 61 0b lhu a5, 182(sp) +80009170: 03 57 81 0b lhu a4, 184(sp) +80009174: 93 87 17 00 addi a5, a5, 1 +80009178: 23 1b f1 0a sh a5, 182(sp) +8000917c: e3 14 07 fe bnez a4, -24 +80009180: 83 57 c1 0c lhu a5, 204(sp) +80009184: 63 9a 07 02 bnez a5, 52 +80009188: 83 57 61 0b lhu a5, 182(sp) +8000918c: 63 66 fd 02 bltu s10, a5, 44 +80009190: 13 07 04 00 mv a4, s0 +80009194: 93 07 41 0b addi a5, sp, 180 +80009198: 83 d6 07 00 lhu a3, 0(a5) +8000919c: 93 87 27 00 addi a5, a5, 2 +800091a0: 13 07 27 00 addi a4, a4, 2 +800091a4: 23 1f d7 fe sh a3, -2(a4) +800091a8: e3 98 27 ff bne a5, s2, -16 +800091ac: 23 14 01 0e sh zero, 232(sp) +800091b0: 93 84 f4 ff addi s1, s1, -1 +800091b4: e3 96 84 f3 bne s1, s8, -212 +800091b8: 93 05 c1 07 addi a1, sp, 124 +800091bc: 13 05 04 00 mv a0, s0 +800091c0: ef e0 cf bb jal -7236 +800091c4: 13 09 01 16 addi s2, sp, 352 +800091c8: 6f f0 0f 8d j -3888 +800091cc: 13 07 c1 10 addi a4, sp, 268 +800091d0: 93 07 01 0f addi a5, sp, 240 +800091d4: 83 de 07 00 lhu t4, 0(a5) +800091d8: 03 56 07 00 lhu a2, 0(a4) +800091dc: 93 87 27 00 addi a5, a5, 2 +800091e0: 13 07 27 00 addi a4, a4, 2 +800091e4: 63 98 ce 02 bne t4, a2, 48 +800091e8: 13 06 61 10 addi a2, sp, 262 +800091ec: e3 94 c7 fe bne a5, a2, -24 +800091f0: 03 57 c1 0e lhu a4, 236(sp) +800091f4: 83 57 81 10 lhu a5, 264(sp) +800091f8: 63 02 f7 06 beq a4, a5, 100 +800091fc: 93 07 04 00 mv a5, s0 +80009200: 13 07 41 0e addi a4, sp, 228 +80009204: 93 87 27 00 addi a5, a5, 2 +80009208: 23 9f 07 fe sh zero, -2(a5) +8000920c: e3 9c e7 fe bne a5, a4, -8 +80009210: 6f f0 1f a6 j -1440 +80009214: 63 66 d6 0d bltu a2, t4, 204 +80009218: 93 07 01 12 addi a5, sp, 288 +8000921c: 13 06 41 10 addi a2, sp, 260 +80009220: 6f f0 df cf j -772 +80009224: 13 05 00 00 mv a0, zero +80009228: 13 0f e1 0e addi t5, sp, 238 +8000922c: 83 de 07 00 lhu t4, 0(a5) +80009230: 03 57 06 00 lhu a4, 0(a2) +80009234: 93 87 e7 ff addi a5, a5, -2 +80009238: 13 06 e6 ff addi a2, a2, -2 +8000923c: 33 07 d7 01 add a4, a4, t4 +80009240: 33 07 a7 00 add a4, a4, a0 +80009244: 13 55 07 01 srli a0, a4, 16 +80009248: 23 91 e7 00 sh a4, 2(a5) +8000924c: 13 75 15 00 andi a0, a0, 1 +80009250: e3 1e e6 fd bne a2, t5, -36 +80009254: 13 06 00 00 mv a2, zero +80009258: 6f f0 5f d0 j -764 +8000925c: 13 87 06 00 mv a4, a3 +80009260: 63 92 06 06 bnez a3, 100 +80009264: 83 17 e1 10 lh a5, 270(sp) +80009268: 63 ce 07 04 bltz a5, 92 +8000926c: 93 06 01 12 addi a3, sp, 288 +80009270: 6f 00 00 02 j 32 +80009274: 23 90 f6 00 sh a5, 0(a3) +80009278: 13 17 17 00 slli a4, a4, 1 +8000927c: 13 17 07 01 slli a4, a4, 16 +80009280: 93 86 e6 ff addi a3, a3, -2 +80009284: 93 07 a1 10 addi a5, sp, 266 +80009288: 13 57 07 01 srli a4, a4, 16 +8000928c: e3 84 f6 ce beq a3, a5, -792 +80009290: 83 d7 06 00 lhu a5, 0(a3) +80009294: 13 96 07 01 slli a2, a5, 16 +80009298: 13 56 06 41 srai a2, a2, 16 +8000929c: 93 97 17 00 slli a5, a5, 1 +800092a0: 63 54 06 00 bgez a2, 8 +800092a4: 13 67 17 00 ori a4, a4, 1 +800092a8: 93 97 07 01 slli a5, a5, 16 +800092ac: 93 d7 07 01 srli a5, a5, 16 +800092b0: 13 76 27 00 andi a2, a4, 2 +800092b4: 93 e5 17 00 ori a1, a5, 1 +800092b8: e3 0e 06 fa beqz a2, -68 +800092bc: 23 90 b6 00 sh a1, 0(a3) +800092c0: 6f f0 9f fb j -72 +800092c4: 13 06 c1 10 addi a2, sp, 268 +800092c8: 93 07 01 12 addi a5, sp, 288 +800092cc: 63 12 07 08 bnez a4, 132 +800092d0: 63 82 c7 08 beq a5, a2, 132 +800092d4: 03 57 06 00 lhu a4, 0(a2) +800092d8: 13 06 26 00 addi a2, a2, 2 +800092dc: 6f f0 1f ff j -16 +800092e0: 13 86 0c 00 mv a2, s9 +800092e4: 13 07 81 10 addi a4, sp, 264 +800092e8: 93 07 01 12 addi a5, sp, 288 +800092ec: 03 55 07 00 lhu a0, 0(a4) +800092f0: 13 07 27 00 addi a4, a4, 2 +800092f4: 13 06 26 00 addi a2, a2, 2 +800092f8: 23 1f a6 fe sh a0, -2(a2) +800092fc: e3 18 f7 fe bne a4, a5, -16 +80009300: 23 1e 01 12 sh zero, 316(sp) +80009304: 13 05 81 10 addi a0, sp, 264 +80009308: 13 07 c1 0e addi a4, sp, 236 +8000930c: 13 06 41 10 addi a2, sp, 260 +80009310: 83 5e 07 00 lhu t4, 0(a4) +80009314: 13 07 27 00 addi a4, a4, 2 +80009318: 13 05 25 00 addi a0, a0, 2 +8000931c: 23 1f d5 ff sh t4, -2(a0) +80009320: e3 18 c7 fe bne a4, a2, -16 +80009324: 23 10 01 12 sh zero, 288(sp) +80009328: 13 05 c1 0e addi a0, sp, 236 +8000932c: 13 87 0c 00 mv a4, s9 +80009330: 13 0f c1 13 addi t5, sp, 316 +80009334: 83 5e 07 00 lhu t4, 0(a4) +80009338: 13 07 27 00 addi a4, a4, 2 +8000933c: 13 05 25 00 addi a0, a0, 2 +80009340: 23 1f d5 ff sh t4, -2(a0) +80009344: e3 18 e7 ff bne a4, t5, -16 +80009348: 23 12 01 10 sh zero, 260(sp) +8000934c: 6f f0 1f bd j -1072 +80009350: 13 85 16 00 addi a0, a3, 1 +80009354: 23 15 a1 10 sh a0, 266(sp) +80009358: 6f f0 df c1 j -996 + +8000935c _ldcheck: +8000935c: 03 27 85 00 lw a4, 8(a0) +80009360: 83 27 c5 00 lw a5, 12(a0) +80009364: 03 26 05 00 lw a2, 0(a0) +80009368: 83 26 45 00 lw a3, 4(a0) +8000936c: 13 01 01 fc addi sp, sp, -64 +80009370: 13 05 01 00 mv a0, sp +80009374: 93 05 41 01 addi a1, sp, 20 +80009378: 23 24 e1 00 sw a4, 8(sp) +8000937c: 23 26 f1 00 sw a5, 12(sp) +80009380: 23 2e 11 02 sw ra, 60(sp) +80009384: 23 20 c1 00 sw a2, 0(sp) +80009388: 23 22 d1 00 sw a3, 4(sp) +8000938c: ef e0 9f bc jal -5176 +80009390: 83 57 61 02 lhu a5, 38(sp) +80009394: 13 05 00 00 mv a0, zero +80009398: 93 c7 f7 ff not a5, a5 +8000939c: 13 97 17 01 slli a4, a5, 17 +800093a0: 63 1a 07 00 bnez a4, 20 +800093a4: 13 05 41 01 addi a0, sp, 20 +800093a8: ef d0 8f de jal -10776 +800093ac: 13 35 15 00 seqz a0, a0 +800093b0: 13 05 15 00 addi a0, a0, 1 +800093b4: 83 20 c1 03 lw ra, 60(sp) +800093b8: 13 01 01 04 addi sp, sp, 64 +800093bc: 67 80 00 00 ret + +800093c0 __localeconv_l: +800093c0: 13 05 05 0f addi a0, a0, 240 +800093c4: 67 80 00 00 ret + +800093c8 _localeconv_r: +800093c8: 37 85 01 80 lui a0, 524312 +800093cc: 13 05 85 af addi a0, a0, -1288 +800093d0: 67 80 00 00 ret + +800093d4 localeconv: +800093d4: 37 85 01 80 lui a0, 524312 +800093d8: 13 05 85 af addi a0, a0, -1288 +800093dc: 67 80 00 00 ret + +800093e0 _malloc_r: +800093e0: 13 01 01 fd addi sp, sp, -48 +800093e4: 23 2e 31 01 sw s3, 28(sp) +800093e8: 23 26 11 02 sw ra, 44(sp) +800093ec: 23 24 81 02 sw s0, 40(sp) +800093f0: 23 22 91 02 sw s1, 36(sp) +800093f4: 23 20 21 03 sw s2, 32(sp) +800093f8: 23 2c 41 01 sw s4, 24(sp) +800093fc: 23 2a 51 01 sw s5, 20(sp) +80009400: 23 28 61 01 sw s6, 16(sp) +80009404: 23 26 71 01 sw s7, 12(sp) +80009408: 23 24 81 01 sw s8, 8(sp) +8000940c: 23 22 91 01 sw s9, 4(sp) +80009410: 93 87 b5 00 addi a5, a1, 11 +80009414: 13 07 60 01 addi a4, zero, 22 +80009418: 93 09 05 00 mv s3, a0 +8000941c: 63 66 f7 06 bltu a4, a5, 108 +80009420: 93 07 00 01 addi a5, zero, 16 +80009424: 63 e6 b7 1e bltu a5, a1, 492 +80009428: ef 00 50 04 jal 2116 +8000942c: 93 04 00 01 addi s1, zero, 16 +80009430: 13 06 20 00 addi a2, zero, 2 +80009434: 93 07 80 01 addi a5, zero, 24 +80009438: 37 79 01 80 lui s2, 524311 +8000943c: 13 09 09 60 addi s2, s2, 1536 +80009440: b3 07 f9 00 add a5, s2, a5 +80009444: 03 a4 47 00 lw s0, 4(a5) +80009448: 13 87 87 ff addi a4, a5, -8 +8000944c: 63 0a e4 20 beq s0, a4, 532 +80009450: 83 27 44 00 lw a5, 4(s0) +80009454: 83 26 c4 00 lw a3, 12(s0) +80009458: 03 26 84 00 lw a2, 8(s0) +8000945c: 93 f7 c7 ff andi a5, a5, -4 +80009460: b3 07 f4 00 add a5, s0, a5 +80009464: 03 a7 47 00 lw a4, 4(a5) +80009468: 23 26 d6 00 sw a3, 12(a2) +8000946c: 23 a4 c6 00 sw a2, 8(a3) +80009470: 13 67 17 00 ori a4, a4, 1 +80009474: 13 85 09 00 mv a0, s3 +80009478: 23 a2 e7 00 sw a4, 4(a5) +8000947c: ef 00 40 7f jal 2036 +80009480: 13 05 84 00 addi a0, s0, 8 +80009484: 6f 00 80 19 j 408 +80009488: 93 f4 87 ff andi s1, a5, -8 +8000948c: 63 c2 07 18 bltz a5, 388 +80009490: 63 e0 b4 18 bltu s1, a1, 384 +80009494: ef 00 80 7d jal 2008 +80009498: 93 07 70 1f addi a5, zero, 503 +8000949c: 63 f6 97 46 bgeu a5, s1, 1132 +800094a0: 93 d7 94 00 srli a5, s1, 9 +800094a4: 63 86 07 1a beqz a5, 428 +800094a8: 13 07 40 00 addi a4, zero, 4 +800094ac: 63 6c f7 3c bltu a4, a5, 984 +800094b0: 93 d7 64 00 srli a5, s1, 6 +800094b4: 13 86 97 03 addi a2, a5, 57 +800094b8: 13 85 87 03 addi a0, a5, 56 +800094bc: 93 16 36 00 slli a3, a2, 3 +800094c0: 37 79 01 80 lui s2, 524311 +800094c4: 13 09 09 60 addi s2, s2, 1536 +800094c8: b3 06 d9 00 add a3, s2, a3 +800094cc: 03 a4 46 00 lw s0, 4(a3) +800094d0: 93 86 86 ff addi a3, a3, -8 +800094d4: 63 86 86 02 beq a3, s0, 44 +800094d8: 93 05 f0 00 addi a1, zero, 15 +800094dc: 6f 00 00 01 j 16 +800094e0: 63 5c 07 32 bgez a4, 824 +800094e4: 03 24 c4 00 lw s0, 12(s0) +800094e8: 63 8c 86 00 beq a3, s0, 24 +800094ec: 83 27 44 00 lw a5, 4(s0) +800094f0: 93 f7 c7 ff andi a5, a5, -4 +800094f4: 33 87 97 40 sub a4, a5, s1 +800094f8: e3 d4 e5 fe bge a1, a4, -24 +800094fc: 13 06 05 00 mv a2, a0 +80009500: 03 24 09 01 lw s0, 16(s2) +80009504: 93 08 89 00 addi a7, s2, 8 +80009508: 63 08 14 17 beq s0, a7, 368 +8000950c: 03 25 44 00 lw a0, 4(s0) +80009510: 93 06 f0 00 addi a3, zero, 15 +80009514: 13 75 c5 ff andi a0, a0, -4 +80009518: b3 07 95 40 sub a5, a0, s1 +8000951c: 63 cc f6 40 blt a3, a5, 1048 +80009520: 23 2a 19 01 sw a7, 20(s2) +80009524: 23 28 19 01 sw a7, 16(s2) +80009528: 63 d6 07 3e bgez a5, 1004 +8000952c: 93 07 f0 1f addi a5, zero, 511 +80009530: 63 ea a7 2e bltu a5, a0, 756 +80009534: 93 77 85 ff andi a5, a0, -8 +80009538: 93 87 87 00 addi a5, a5, 8 +8000953c: 83 25 49 00 lw a1, 4(s2) +80009540: b3 07 f9 00 add a5, s2, a5 +80009544: 83 a6 07 00 lw a3, 0(a5) +80009548: 13 55 55 00 srli a0, a0, 5 +8000954c: 13 07 10 00 addi a4, zero, 1 +80009550: 33 17 a7 00 sll a4, a4, a0 +80009554: 33 67 b7 00 or a4, a4, a1 +80009558: 93 85 87 ff addi a1, a5, -8 +8000955c: 23 26 b4 00 sw a1, 12(s0) +80009560: 23 24 d4 00 sw a3, 8(s0) +80009564: 23 22 e9 00 sw a4, 4(s2) +80009568: 23 a0 87 00 sw s0, 0(a5) +8000956c: 23 a6 86 00 sw s0, 12(a3) +80009570: 93 57 26 40 srai a5, a2, 2 +80009574: 93 05 10 00 addi a1, zero, 1 +80009578: b3 95 f5 00 sll a1, a1, a5 +8000957c: 63 68 b7 10 bltu a4, a1, 272 +80009580: b3 f7 e5 00 and a5, a1, a4 +80009584: 63 94 07 02 bnez a5, 40 +80009588: 93 95 15 00 slli a1, a1, 1 +8000958c: 13 76 c6 ff andi a2, a2, -4 +80009590: b3 f7 e5 00 and a5, a1, a4 +80009594: 13 06 46 00 addi a2, a2, 4 +80009598: 63 9a 07 00 bnez a5, 20 +8000959c: 93 95 15 00 slli a1, a1, 1 +800095a0: b3 f7 e5 00 and a5, a1, a4 +800095a4: 13 06 46 00 addi a2, a2, 4 +800095a8: e3 8a 07 fe beqz a5, -12 +800095ac: 13 08 f0 00 addi a6, zero, 15 +800095b0: 13 13 36 00 slli t1, a2, 3 +800095b4: 33 03 69 00 add t1, s2, t1 +800095b8: 13 05 03 00 mv a0, t1 +800095bc: 83 27 c5 00 lw a5, 12(a0) +800095c0: 13 0e 06 00 mv t3, a2 +800095c4: 63 02 f5 2e beq a0, a5, 740 +800095c8: 03 a7 47 00 lw a4, 4(a5) +800095cc: 13 84 07 00 mv s0, a5 +800095d0: 83 a7 c7 00 lw a5, 12(a5) +800095d4: 13 77 c7 ff andi a4, a4, -4 +800095d8: b3 06 97 40 sub a3, a4, s1 +800095dc: 63 42 d8 2e blt a6, a3, 740 +800095e0: e3 c2 06 fe bltz a3, -28 +800095e4: 33 07 e4 00 add a4, s0, a4 +800095e8: 83 26 47 00 lw a3, 4(a4) +800095ec: 03 26 84 00 lw a2, 8(s0) +800095f0: 13 85 09 00 mv a0, s3 +800095f4: 93 e6 16 00 ori a3, a3, 1 +800095f8: 23 22 d7 00 sw a3, 4(a4) +800095fc: 23 26 f6 00 sw a5, 12(a2) +80009600: 23 a4 c7 00 sw a2, 8(a5) +80009604: ef 00 c0 66 jal 1644 +80009608: 13 05 84 00 addi a0, s0, 8 +8000960c: 6f 00 00 01 j 16 +80009610: 93 07 c0 00 addi a5, zero, 12 +80009614: 23 a0 f9 00 sw a5, 0(s3) +80009618: 13 05 00 00 mv a0, zero +8000961c: 83 20 c1 02 lw ra, 44(sp) +80009620: 03 24 81 02 lw s0, 40(sp) +80009624: 83 24 41 02 lw s1, 36(sp) +80009628: 03 29 01 02 lw s2, 32(sp) +8000962c: 83 29 c1 01 lw s3, 28(sp) +80009630: 03 2a 81 01 lw s4, 24(sp) +80009634: 83 2a 41 01 lw s5, 20(sp) +80009638: 03 2b 01 01 lw s6, 16(sp) +8000963c: 83 2b c1 00 lw s7, 12(sp) +80009640: 03 2c 81 00 lw s8, 8(sp) +80009644: 83 2c 41 00 lw s9, 4(sp) +80009648: 13 01 01 03 addi sp, sp, 48 +8000964c: 67 80 00 00 ret +80009650: 93 06 00 20 addi a3, zero, 512 +80009654: 13 06 00 04 addi a2, zero, 64 +80009658: 13 05 f0 03 addi a0, zero, 63 +8000965c: 6f f0 5f e6 j -412 +80009660: 03 a4 c7 00 lw s0, 12(a5) +80009664: 13 06 26 00 addi a2, a2, 2 +80009668: e3 94 87 de bne a5, s0, -536 +8000966c: 03 24 09 01 lw s0, 16(s2) +80009670: 93 08 89 00 addi a7, s2, 8 +80009674: e3 1c 14 e9 bne s0, a7, -360 +80009678: 03 27 49 00 lw a4, 4(s2) +8000967c: 93 57 26 40 srai a5, a2, 2 +80009680: 93 05 10 00 addi a1, zero, 1 +80009684: b3 95 f5 00 sll a1, a1, a5 +80009688: e3 7c b7 ee bgeu a4, a1, -264 +8000968c: 03 24 89 00 lw s0, 8(s2) +80009690: 83 2a 44 00 lw s5, 4(s0) +80009694: 13 fb ca ff andi s6, s5, -4 +80009698: 63 68 9b 00 bltu s6, s1, 16 +8000969c: b3 07 9b 40 sub a5, s6, s1 +800096a0: 13 07 f0 00 addi a4, zero, 15 +800096a4: 63 46 f7 14 blt a4, a5, 332 +800096a8: b7 87 01 80 lui a5, 524312 +800096ac: b7 8c 01 80 lui s9, 524312 +800096b0: 83 aa 07 bb lw s5, -1104(a5) +800096b4: 03 a7 0c ba lw a4, -1120(s9) +800096b8: 93 07 f0 ff addi a5, zero, -1 +800096bc: 33 0a 64 01 add s4, s0, s6 +800096c0: b3 8a 54 01 add s5, s1, s5 +800096c4: 63 0a f7 34 beq a4, a5, 852 +800096c8: b7 17 00 00 lui a5, 1 +800096cc: 93 87 f7 00 addi a5, a5, 15 +800096d0: b3 8a fa 00 add s5, s5, a5 +800096d4: b7 f7 ff ff lui a5, 1048575 +800096d8: b3 fa fa 00 and s5, s5, a5 +800096dc: 93 85 0a 00 mv a1, s5 +800096e0: 13 85 09 00 mv a0, s3 +800096e4: ef 10 00 79 jal 6032 +800096e8: 93 07 f0 ff addi a5, zero, -1 +800096ec: 93 0b 05 00 mv s7, a0 +800096f0: 63 0c f5 28 beq a0, a5, 664 +800096f4: 63 68 45 29 bltu a0, s4, 656 +800096f8: 37 8c 01 80 lui s8, 524312 +800096fc: 13 0c 4c bb addi s8, s8, -1100 +80009700: 83 25 0c 00 lw a1, 0(s8) +80009704: b3 85 ba 00 add a1, s5, a1 +80009708: 23 20 bc 00 sw a1, 0(s8) +8000970c: 93 87 05 00 mv a5, a1 +80009710: 63 04 aa 3a beq s4, a0, 936 +80009714: 83 a6 0c ba lw a3, -1120(s9) +80009718: 13 07 f0 ff addi a4, zero, -1 +8000971c: 63 8c e6 3a beq a3, a4, 952 +80009720: 33 8a 4b 41 sub s4, s7, s4 +80009724: b3 07 fa 00 add a5, s4, a5 +80009728: 23 20 fc 00 sw a5, 0(s8) +8000972c: 93 fc 7b 00 andi s9, s7, 7 +80009730: 63 86 0c 30 beqz s9, 780 +80009734: b7 17 00 00 lui a5, 1 +80009738: b3 8b 9b 41 sub s7, s7, s9 +8000973c: 93 85 87 00 addi a1, a5, 8 +80009740: 93 8b 8b 00 addi s7, s7, 8 +80009744: b3 85 95 41 sub a1, a1, s9 +80009748: b3 8a 5b 01 add s5, s7, s5 +8000974c: 93 87 f7 ff addi a5, a5, -1 +80009750: b3 85 55 41 sub a1, a1, s5 +80009754: 33 fa f5 00 and s4, a1, a5 +80009758: 93 05 0a 00 mv a1, s4 +8000975c: 13 85 09 00 mv a0, s3 +80009760: ef 10 40 71 jal 5908 +80009764: 93 07 f0 ff addi a5, zero, -1 +80009768: 63 00 f5 3c beq a0, a5, 960 +8000976c: 33 05 75 41 sub a0, a0, s7 +80009770: b3 0a 45 01 add s5, a0, s4 +80009774: 83 25 0c 00 lw a1, 0(s8) +80009778: 23 24 79 01 sw s7, 8(s2) +8000977c: 93 ea 1a 00 ori s5, s5, 1 +80009780: b3 05 ba 00 add a1, s4, a1 +80009784: 23 20 bc 00 sw a1, 0(s8) +80009788: 23 a2 5b 01 sw s5, 4(s7) +8000978c: 63 08 24 35 beq s0, s2, 848 +80009790: 93 06 f0 00 addi a3, zero, 15 +80009794: 63 f8 66 35 bgeu a3, s6, 848 +80009798: 03 27 44 00 lw a4, 4(s0) +8000979c: 93 07 4b ff addi a5, s6, -12 +800097a0: 93 f7 87 ff andi a5, a5, -8 +800097a4: 13 77 17 00 andi a4, a4, 1 +800097a8: 33 67 f7 00 or a4, a4, a5 +800097ac: 23 22 e4 00 sw a4, 4(s0) +800097b0: 13 06 50 00 addi a2, zero, 5 +800097b4: 33 07 f4 00 add a4, s0, a5 +800097b8: 23 22 c7 00 sw a2, 4(a4) +800097bc: 23 24 c7 00 sw a2, 8(a4) +800097c0: 63 ee f6 36 bltu a3, a5, 892 +800097c4: 83 aa 4b 00 lw s5, 4(s7) +800097c8: 13 84 0b 00 mv s0, s7 +800097cc: b7 87 01 80 lui a5, 524312 +800097d0: 03 a7 c7 ba lw a4, -1108(a5) +800097d4: 63 74 b7 00 bgeu a4, a1, 8 +800097d8: 23 a6 b7 ba sw a1, -1108(a5) +800097dc: b7 87 01 80 lui a5, 524312 +800097e0: 03 a7 87 ba lw a4, -1112(a5) +800097e4: 63 76 b7 1a bgeu a4, a1, 428 +800097e8: 23 a4 b7 ba sw a1, -1112(a5) +800097ec: 6f 00 40 1a j 420 +800097f0: 13 e7 14 00 ori a4, s1, 1 +800097f4: 23 22 e4 00 sw a4, 4(s0) +800097f8: b3 04 94 00 add s1, s0, s1 +800097fc: 23 24 99 00 sw s1, 8(s2) +80009800: 93 e7 17 00 ori a5, a5, 1 +80009804: 13 85 09 00 mv a0, s3 +80009808: 23 a2 f4 00 sw a5, 4(s1) +8000980c: ef 00 40 46 jal 1124 +80009810: 13 05 84 00 addi a0, s0, 8 +80009814: 6f f0 9f e0 j -504 +80009818: 83 26 c4 00 lw a3, 12(s0) +8000981c: 03 26 84 00 lw a2, 8(s0) +80009820: 6f f0 1f c4 j -960 +80009824: 93 57 95 00 srli a5, a0, 9 +80009828: 13 07 40 00 addi a4, zero, 4 +8000982c: 63 72 f7 14 bgeu a4, a5, 324 +80009830: 13 07 40 01 addi a4, zero, 20 +80009834: 63 6a f7 22 bltu a4, a5, 564 +80009838: 93 86 c7 05 addi a3, a5, 92 +8000983c: 93 85 b7 05 addi a1, a5, 91 +80009840: 93 96 36 00 slli a3, a3, 3 +80009844: b3 06 d9 00 add a3, s2, a3 +80009848: 83 a7 06 00 lw a5, 0(a3) +8000984c: 93 86 86 ff addi a3, a3, -8 +80009850: 63 88 f6 1c beq a3, a5, 464 +80009854: 03 a7 47 00 lw a4, 4(a5) +80009858: 13 77 c7 ff andi a4, a4, -4 +8000985c: 63 76 e5 00 bgeu a0, a4, 12 +80009860: 83 a7 87 00 lw a5, 8(a5) +80009864: e3 98 f6 fe bne a3, a5, -16 +80009868: 83 a6 c7 00 lw a3, 12(a5) +8000986c: 03 27 49 00 lw a4, 4(s2) +80009870: 23 26 d4 00 sw a3, 12(s0) +80009874: 23 24 f4 00 sw a5, 8(s0) +80009878: 23 a4 86 00 sw s0, 8(a3) +8000987c: 23 a6 87 00 sw s0, 12(a5) +80009880: 6f f0 1f cf j -784 +80009884: 13 07 40 01 addi a4, zero, 20 +80009888: 63 76 f7 12 bgeu a4, a5, 300 +8000988c: 13 07 40 05 addi a4, zero, 84 +80009890: 63 6a f7 1e bltu a4, a5, 500 +80009894: 93 d7 c4 00 srli a5, s1, 12 +80009898: 13 86 f7 06 addi a2, a5, 111 +8000989c: 13 85 e7 06 addi a0, a5, 110 +800098a0: 93 16 36 00 slli a3, a2, 3 +800098a4: 6f f0 df c1 j -996 +800098a8: 13 0e 1e 00 addi t3, t3, 1 +800098ac: 93 77 3e 00 andi a5, t3, 3 +800098b0: 13 05 85 00 addi a0, a0, 8 +800098b4: 63 8e 07 10 beqz a5, 284 +800098b8: 83 27 c5 00 lw a5, 12(a0) +800098bc: 6f f0 9f d0 j -760 +800098c0: 03 26 84 00 lw a2, 8(s0) +800098c4: 93 e5 14 00 ori a1, s1, 1 +800098c8: 23 22 b4 00 sw a1, 4(s0) +800098cc: 23 26 f6 00 sw a5, 12(a2) +800098d0: 23 a4 c7 00 sw a2, 8(a5) +800098d4: b3 04 94 00 add s1, s0, s1 +800098d8: 23 2a 99 00 sw s1, 20(s2) +800098dc: 23 28 99 00 sw s1, 16(s2) +800098e0: 93 e7 16 00 ori a5, a3, 1 +800098e4: 23 a6 14 01 sw a7, 12(s1) +800098e8: 23 a4 14 01 sw a7, 8(s1) +800098ec: 23 a2 f4 00 sw a5, 4(s1) +800098f0: 33 07 e4 00 add a4, s0, a4 +800098f4: 13 85 09 00 mv a0, s3 +800098f8: 23 20 d7 00 sw a3, 0(a4) +800098fc: ef 00 40 37 jal 884 +80009900: 13 05 84 00 addi a0, s0, 8 +80009904: 6f f0 9f d1 j -744 +80009908: 13 d6 34 00 srli a2, s1, 3 +8000990c: 93 87 84 00 addi a5, s1, 8 +80009910: 6f f0 9f b2 j -1240 +80009914: 33 07 a4 00 add a4, s0, a0 +80009918: 83 27 47 00 lw a5, 4(a4) +8000991c: 13 85 09 00 mv a0, s3 +80009920: 93 e7 17 00 ori a5, a5, 1 +80009924: 23 22 f7 00 sw a5, 4(a4) +80009928: ef 00 80 34 jal 840 +8000992c: 13 05 84 00 addi a0, s0, 8 +80009930: 6f f0 df ce j -788 +80009934: 13 e7 14 00 ori a4, s1, 1 +80009938: 23 22 e4 00 sw a4, 4(s0) +8000993c: b3 04 94 00 add s1, s0, s1 +80009940: 23 2a 99 00 sw s1, 20(s2) +80009944: 23 28 99 00 sw s1, 16(s2) +80009948: 13 e7 17 00 ori a4, a5, 1 +8000994c: 23 a6 14 01 sw a7, 12(s1) +80009950: 23 a4 14 01 sw a7, 8(s1) +80009954: 23 a2 e4 00 sw a4, 4(s1) +80009958: 33 05 a4 00 add a0, s0, a0 +8000995c: 23 20 f5 00 sw a5, 0(a0) +80009960: 13 85 09 00 mv a0, s3 +80009964: ef 00 c0 30 jal 780 +80009968: 13 05 84 00 addi a0, s0, 8 +8000996c: 6f f0 1f cb j -848 +80009970: 93 57 65 00 srli a5, a0, 6 +80009974: 93 86 97 03 addi a3, a5, 57 +80009978: 93 85 87 03 addi a1, a5, 56 +8000997c: 93 96 36 00 slli a3, a3, 3 +80009980: 6f f0 5f ec j -316 +80009984: 63 0e 24 11 beq s0, s2, 284 +80009988: 03 24 89 00 lw s0, 8(s2) +8000998c: 83 2a 44 00 lw s5, 4(s0) +80009990: 93 fa ca ff andi s5, s5, -4 +80009994: b3 87 9a 40 sub a5, s5, s1 +80009998: 63 e6 9a 00 bltu s5, s1, 12 +8000999c: 13 07 f0 00 addi a4, zero, 15 +800099a0: e3 48 f7 e4 blt a4, a5, -432 +800099a4: 13 85 09 00 mv a0, s3 +800099a8: ef 00 80 2c jal 712 +800099ac: 13 05 00 00 mv a0, zero +800099b0: 6f f0 df c6 j -916 +800099b4: 13 86 c7 05 addi a2, a5, 92 +800099b8: 13 85 b7 05 addi a0, a5, 91 +800099bc: 93 16 36 00 slli a3, a2, 3 +800099c0: 6f f0 1f b0 j -1280 +800099c4: 83 27 83 00 lw a5, 8(t1) +800099c8: 13 06 f6 ff addi a2, a2, -1 +800099cc: 63 92 67 1c bne a5, t1, 452 +800099d0: 93 77 36 00 andi a5, a2, 3 +800099d4: 13 03 83 ff addi t1, t1, -8 +800099d8: e3 96 07 fe bnez a5, -20 +800099dc: 03 27 49 00 lw a4, 4(s2) +800099e0: 93 c7 f5 ff not a5, a1 +800099e4: b3 f7 e7 00 and a5, a5, a4 +800099e8: 23 22 f9 00 sw a5, 4(s2) +800099ec: 93 95 15 00 slli a1, a1, 1 +800099f0: e3 ee b7 c8 bltu a5, a1, -868 +800099f4: e3 8c 05 c8 beqz a1, -872 +800099f8: 33 f7 f5 00 and a4, a1, a5 +800099fc: 63 1a 07 00 bnez a4, 20 +80009a00: 93 95 15 00 slli a1, a1, 1 +80009a04: 33 f7 f5 00 and a4, a1, a5 +80009a08: 13 0e 4e 00 addi t3, t3, 4 +80009a0c: e3 0a 07 fe beqz a4, -12 +80009a10: 13 06 0e 00 mv a2, t3 +80009a14: 6f f0 df b9 j -1124 +80009a18: 93 8a 0a 01 addi s5, s5, 16 +80009a1c: 6f f0 1f cc j -832 +80009a20: 03 25 49 00 lw a0, 4(s2) +80009a24: 93 d5 25 40 srai a1, a1, 2 +80009a28: 13 07 10 00 addi a4, zero, 1 +80009a2c: 33 17 b7 00 sll a4, a4, a1 +80009a30: 33 67 a7 00 or a4, a4, a0 +80009a34: 23 22 e9 00 sw a4, 4(s2) +80009a38: 6f f0 9f e3 j -456 +80009a3c: b3 85 5b 01 add a1, s7, s5 +80009a40: b3 05 b0 40 neg a1, a1 +80009a44: 93 95 45 01 slli a1, a1, 20 +80009a48: 13 da 45 01 srli s4, a1, 20 +80009a4c: 93 05 0a 00 mv a1, s4 +80009a50: 13 85 09 00 mv a0, s3 +80009a54: ef 10 00 42 jal 5152 +80009a58: 93 07 f0 ff addi a5, zero, -1 +80009a5c: e3 18 f5 d0 bne a0, a5, -752 +80009a60: 13 0a 00 00 mv s4, zero +80009a64: 6f f0 1f d1 j -752 +80009a68: 13 07 40 05 addi a4, zero, 84 +80009a6c: 63 62 f7 08 bltu a4, a5, 132 +80009a70: 93 57 c5 00 srli a5, a0, 12 +80009a74: 93 86 f7 06 addi a3, a5, 111 +80009a78: 93 85 e7 06 addi a1, a5, 110 +80009a7c: 93 96 36 00 slli a3, a3, 3 +80009a80: 6f f0 5f dc j -572 +80009a84: 13 07 40 15 addi a4, zero, 340 +80009a88: 63 62 f7 08 bltu a4, a5, 132 +80009a8c: 93 d7 f4 00 srli a5, s1, 15 +80009a90: 13 86 87 07 addi a2, a5, 120 +80009a94: 13 85 77 07 addi a0, a5, 119 +80009a98: 93 16 36 00 slli a3, a2, 3 +80009a9c: 6f f0 5f a2 j -1500 +80009aa0: 37 8c 01 80 lui s8, 524312 +80009aa4: 13 0c 4c bb addi s8, s8, -1100 +80009aa8: 83 27 0c 00 lw a5, 0(s8) +80009aac: b3 87 fa 00 add a5, s5, a5 +80009ab0: 23 20 fc 00 sw a5, 0(s8) +80009ab4: 6f f0 1f c6 j -928 +80009ab8: 13 17 4a 01 slli a4, s4, 20 +80009abc: e3 1c 07 c4 bnez a4, -936 +80009ac0: 03 24 89 00 lw s0, 8(s2) +80009ac4: b3 0a 5b 01 add s5, s6, s5 +80009ac8: 93 ea 1a 00 ori s5, s5, 1 +80009acc: 23 22 54 01 sw s5, 4(s0) +80009ad0: 6f f0 df cf j -772 +80009ad4: 23 a0 7c bb sw s7, -1120(s9) +80009ad8: 6f f0 5f c5 j -940 +80009adc: 13 84 0b 00 mv s0, s7 +80009ae0: 6f f0 df ce j -788 +80009ae4: 93 07 10 00 addi a5, zero, 1 +80009ae8: 23 a2 fb 00 sw a5, 4(s7) +80009aec: 6f f0 9f eb j -328 +80009af0: 13 07 40 15 addi a4, zero, 340 +80009af4: 63 62 f7 06 bltu a4, a5, 100 +80009af8: 93 57 f5 00 srli a5, a0, 15 +80009afc: 93 86 87 07 addi a3, a5, 120 +80009b00: 93 85 77 07 addi a1, a5, 119 +80009b04: 93 96 36 00 slli a3, a3, 3 +80009b08: 6f f0 df d3 j -708 +80009b0c: 13 07 40 55 addi a4, zero, 1364 +80009b10: 63 62 f7 06 bltu a4, a5, 100 +80009b14: 93 d7 24 01 srli a5, s1, 18 +80009b18: 13 86 d7 07 addi a2, a5, 125 +80009b1c: 13 85 c7 07 addi a0, a5, 124 +80009b20: 93 16 36 00 slli a3, a2, 3 +80009b24: 6f f0 df 99 j -1636 +80009b28: 93 8c 8c ff addi s9, s9, -8 +80009b2c: b3 8a 9a 01 add s5, s5, s9 +80009b30: b3 8a 7a 41 sub s5, s5, s7 +80009b34: 13 0a 00 00 mv s4, zero +80009b38: 6f f0 df c3 j -964 +80009b3c: 93 05 84 00 addi a1, s0, 8 +80009b40: 13 85 09 00 mv a0, s3 +80009b44: ef c0 9f 9c jal -13880 +80009b48: 03 24 89 00 lw s0, 8(s2) +80009b4c: 83 25 0c 00 lw a1, 0(s8) +80009b50: 83 2a 44 00 lw s5, 4(s0) +80009b54: 6f f0 9f c7 j -904 +80009b58: 13 07 40 55 addi a4, zero, 1364 +80009b5c: 63 64 f7 02 bltu a4, a5, 40 +80009b60: 93 57 25 01 srli a5, a0, 18 +80009b64: 93 86 d7 07 addi a3, a5, 125 +80009b68: 93 85 c7 07 addi a1, a5, 124 +80009b6c: 93 96 36 00 slli a3, a3, 3 +80009b70: 6f f0 5f cd j -812 +80009b74: 93 06 80 3f addi a3, zero, 1016 +80009b78: 13 06 f0 07 addi a2, zero, 127 +80009b7c: 13 05 e0 07 addi a0, zero, 126 +80009b80: 6f f0 1f 94 j -1728 +80009b84: 93 06 80 3f addi a3, zero, 1016 +80009b88: 93 05 e0 07 addi a1, zero, 126 +80009b8c: 6f f0 9f cb j -840 +80009b90: 83 27 49 00 lw a5, 4(s2) +80009b94: 6f f0 9f e5 j -424 + +80009b98 memchr: +80009b98: 93 77 35 00 andi a5, a0, 3 +80009b9c: 93 f6 f5 0f andi a3, a1, 255 +80009ba0: 63 8a 07 02 beqz a5, 52 +80009ba4: 93 07 f6 ff addi a5, a2, -1 +80009ba8: 63 0e 06 02 beqz a2, 60 +80009bac: 13 06 f0 ff addi a2, zero, -1 +80009bb0: 6f 00 80 01 j 24 +80009bb4: 13 05 15 00 addi a0, a0, 1 +80009bb8: 13 77 35 00 andi a4, a0, 3 +80009bbc: 63 0e 07 00 beqz a4, 28 +80009bc0: 93 87 f7 ff addi a5, a5, -1 +80009bc4: 63 80 c7 02 beq a5, a2, 32 +80009bc8: 03 47 05 00 lbu a4, 0(a0) +80009bcc: e3 14 d7 fe bne a4, a3, -24 +80009bd0: 67 80 00 00 ret +80009bd4: 93 07 06 00 mv a5, a2 +80009bd8: 13 07 30 00 addi a4, zero, 3 +80009bdc: 63 66 f7 02 bltu a4, a5, 44 +80009be0: 63 96 07 00 bnez a5, 12 +80009be4: 13 05 00 00 mv a0, zero +80009be8: 67 80 00 00 ret +80009bec: b3 07 f5 00 add a5, a0, a5 +80009bf0: 6f 00 c0 00 j 12 +80009bf4: 13 05 15 00 addi a0, a0, 1 +80009bf8: e3 86 a7 fe beq a5, a0, -20 +80009bfc: 03 47 05 00 lbu a4, 0(a0) +80009c00: e3 1a d7 fe bne a4, a3, -12 +80009c04: 67 80 00 00 ret +80009c08: 37 07 01 00 lui a4, 16 +80009c0c: 93 98 85 00 slli a7, a1, 8 +80009c10: 13 07 f7 ff addi a4, a4, -1 +80009c14: b3 f8 e8 00 and a7, a7, a4 +80009c18: 93 f5 f5 0f andi a1, a1, 255 +80009c1c: b3 e5 b8 00 or a1, a7, a1 +80009c20: 93 98 05 01 slli a7, a1, 16 +80009c24: b3 e8 b8 00 or a7, a7, a1 +80009c28: 37 08 ff fe lui a6, 1044464 +80009c2c: b7 85 80 80 lui a1, 526344 +80009c30: 13 08 f8 ef addi a6, a6, -257 +80009c34: 93 85 05 08 addi a1, a1, 128 +80009c38: 13 03 30 00 addi t1, zero, 3 +80009c3c: 03 27 05 00 lw a4, 0(a0) +80009c40: 33 c7 e8 00 xor a4, a7, a4 +80009c44: 33 06 07 01 add a2, a4, a6 +80009c48: 13 47 f7 ff not a4, a4 +80009c4c: 33 77 e6 00 and a4, a2, a4 +80009c50: 33 77 b7 00 and a4, a4, a1 +80009c54: e3 1c 07 f8 bnez a4, -104 +80009c58: 93 87 c7 ff addi a5, a5, -4 +80009c5c: 13 05 45 00 addi a0, a0, 4 +80009c60: e3 6e f3 fc bltu t1, a5, -36 +80009c64: e3 94 07 f8 bnez a5, -120 +80009c68: 6f f0 df f7 j -132 + +80009c6c __malloc_lock: +80009c6c: 67 80 00 00 ret + +80009c70 __malloc_unlock: +80009c70: 67 80 00 00 ret + +80009c74 _Balloc: +80009c74: 83 27 c5 04 lw a5, 76(a0) +80009c78: 13 01 01 ff addi sp, sp, -16 +80009c7c: 23 24 81 00 sw s0, 8(sp) +80009c80: 23 22 91 00 sw s1, 4(sp) +80009c84: 23 26 11 00 sw ra, 12(sp) +80009c88: 23 20 21 01 sw s2, 0(sp) +80009c8c: 13 04 05 00 mv s0, a0 +80009c90: 93 84 05 00 mv s1, a1 +80009c94: 63 8e 07 02 beqz a5, 60 +80009c98: 13 95 24 00 slli a0, s1, 2 +80009c9c: b3 87 a7 00 add a5, a5, a0 +80009ca0: 03 a5 07 00 lw a0, 0(a5) +80009ca4: 63 06 05 04 beqz a0, 76 +80009ca8: 03 27 05 00 lw a4, 0(a0) +80009cac: 23 a0 e7 00 sw a4, 0(a5) +80009cb0: 23 28 05 00 sw zero, 16(a0) +80009cb4: 23 26 05 00 sw zero, 12(a0) +80009cb8: 83 20 c1 00 lw ra, 12(sp) +80009cbc: 03 24 81 00 lw s0, 8(sp) +80009cc0: 83 24 41 00 lw s1, 4(sp) +80009cc4: 03 29 01 00 lw s2, 0(sp) +80009cc8: 13 01 01 01 addi sp, sp, 16 +80009ccc: 67 80 00 00 ret +80009cd0: 13 06 10 02 addi a2, zero, 33 +80009cd4: 93 05 40 00 addi a1, zero, 4 +80009cd8: ef 20 80 6d jal 9944 +80009cdc: 23 26 a4 04 sw a0, 76(s0) +80009ce0: 93 07 05 00 mv a5, a0 +80009ce4: e3 1a 05 fa bnez a0, -76 +80009ce8: 13 05 00 00 mv a0, zero +80009cec: 6f f0 df fc j -52 +80009cf0: 13 09 10 00 addi s2, zero, 1 +80009cf4: 33 19 99 00 sll s2, s2, s1 +80009cf8: 13 06 59 00 addi a2, s2, 5 +80009cfc: 13 16 26 00 slli a2, a2, 2 +80009d00: 93 05 10 00 addi a1, zero, 1 +80009d04: 13 05 04 00 mv a0, s0 +80009d08: ef 20 80 6a jal 9896 +80009d0c: e3 0e 05 fc beqz a0, -36 +80009d10: 23 22 95 00 sw s1, 4(a0) +80009d14: 23 24 25 01 sw s2, 8(a0) +80009d18: 6f f0 9f f9 j -104 + +80009d1c _Bfree: +80009d1c: 63 80 05 02 beqz a1, 32 +80009d20: 03 a7 45 00 lw a4, 4(a1) +80009d24: 83 27 c5 04 lw a5, 76(a0) +80009d28: 13 17 27 00 slli a4, a4, 2 +80009d2c: b3 87 e7 00 add a5, a5, a4 +80009d30: 03 a7 07 00 lw a4, 0(a5) +80009d34: 23 a0 e5 00 sw a4, 0(a1) +80009d38: 23 a0 b7 00 sw a1, 0(a5) +80009d3c: 67 80 00 00 ret + +80009d40 __multadd: +80009d40: 13 01 01 fe addi sp, sp, -32 +80009d44: 23 2a 91 00 sw s1, 20(sp) +80009d48: 83 a4 05 01 lw s1, 16(a1) +80009d4c: 37 03 01 00 lui t1, 16 +80009d50: 23 2c 81 00 sw s0, 24(sp) +80009d54: 23 28 21 01 sw s2, 16(sp) +80009d58: 23 26 31 01 sw s3, 12(sp) +80009d5c: 23 2e 11 00 sw ra, 28(sp) +80009d60: 23 24 41 01 sw s4, 8(sp) +80009d64: 13 89 05 00 mv s2, a1 +80009d68: 93 09 05 00 mv s3, a0 +80009d6c: 13 84 06 00 mv s0, a3 +80009d70: 13 88 45 01 addi a6, a1, 20 +80009d74: 93 08 00 00 mv a7, zero +80009d78: 13 03 f3 ff addi t1, t1, -1 +80009d7c: 83 27 08 00 lw a5, 0(a6) +80009d80: 13 08 48 00 addi a6, a6, 4 +80009d84: 93 88 18 00 addi a7, a7, 1 +80009d88: b3 f6 67 00 and a3, a5, t1 +80009d8c: b3 86 c6 02 mul a3, a3, a2 +80009d90: 93 d7 07 01 srli a5, a5, 16 +80009d94: b3 87 c7 02 mul a5, a5, a2 +80009d98: b3 86 86 00 add a3, a3, s0 +80009d9c: 13 de 06 01 srli t3, a3, 16 +80009da0: 33 f7 66 00 and a4, a3, t1 +80009da4: b3 86 c7 01 add a3, a5, t3 +80009da8: 93 97 06 01 slli a5, a3, 16 +80009dac: 33 87 e7 00 add a4, a5, a4 +80009db0: 23 2e e8 fe sw a4, -4(a6) +80009db4: 13 d4 06 01 srli s0, a3, 16 +80009db8: e3 c2 98 fc blt a7, s1, -60 +80009dbc: 63 02 04 02 beqz s0, 36 +80009dc0: 83 27 89 00 lw a5, 8(s2) +80009dc4: 63 d0 f4 04 bge s1, a5, 64 +80009dc8: 93 87 44 00 addi a5, s1, 4 +80009dcc: 93 97 27 00 slli a5, a5, 2 +80009dd0: b3 07 f9 00 add a5, s2, a5 +80009dd4: 23 a2 87 00 sw s0, 4(a5) +80009dd8: 93 84 14 00 addi s1, s1, 1 +80009ddc: 23 28 99 00 sw s1, 16(s2) +80009de0: 83 20 c1 01 lw ra, 28(sp) +80009de4: 03 24 81 01 lw s0, 24(sp) +80009de8: 83 24 41 01 lw s1, 20(sp) +80009dec: 83 29 c1 00 lw s3, 12(sp) +80009df0: 03 2a 81 00 lw s4, 8(sp) +80009df4: 13 05 09 00 mv a0, s2 +80009df8: 03 29 01 01 lw s2, 16(sp) +80009dfc: 13 01 01 02 addi sp, sp, 32 +80009e00: 67 80 00 00 ret +80009e04: 83 25 49 00 lw a1, 4(s2) +80009e08: 13 85 09 00 mv a0, s3 +80009e0c: 93 85 15 00 addi a1, a1, 1 +80009e10: ef f0 5f e6 jal -412 +80009e14: 13 0a 05 00 mv s4, a0 +80009e18: 63 0c 05 04 beqz a0, 88 +80009e1c: 03 26 09 01 lw a2, 16(s2) +80009e20: 93 05 c9 00 addi a1, s2, 12 +80009e24: 13 05 c5 00 addi a0, a0, 12 +80009e28: 13 06 26 00 addi a2, a2, 2 +80009e2c: 13 16 26 00 slli a2, a2, 2 +80009e30: ef 20 c0 7c jal 10188 +80009e34: 03 27 49 00 lw a4, 4(s2) +80009e38: 83 a7 c9 04 lw a5, 76(s3) +80009e3c: 13 17 27 00 slli a4, a4, 2 +80009e40: b3 87 e7 00 add a5, a5, a4 +80009e44: 03 a7 07 00 lw a4, 0(a5) +80009e48: 23 20 e9 00 sw a4, 0(s2) +80009e4c: 23 a0 27 01 sw s2, 0(a5) +80009e50: 93 87 44 00 addi a5, s1, 4 +80009e54: 13 09 0a 00 mv s2, s4 +80009e58: 93 97 27 00 slli a5, a5, 2 +80009e5c: b3 07 f9 00 add a5, s2, a5 +80009e60: 23 a2 87 00 sw s0, 4(a5) +80009e64: 93 84 14 00 addi s1, s1, 1 +80009e68: 23 28 99 00 sw s1, 16(s2) +80009e6c: 6f f0 5f f7 j -140 +80009e70: b7 66 01 80 lui a3, 524310 +80009e74: 37 65 01 80 lui a0, 524310 +80009e78: 93 86 46 9e addi a3, a3, -1564 +80009e7c: 13 06 00 00 mv a2, zero +80009e80: 93 05 50 0b addi a1, zero, 181 +80009e84: 13 05 85 9f addi a0, a0, -1544 +80009e88: ef 20 c0 4b jal 9404 + +80009e8c __s2b: +80009e8c: 13 01 01 fe addi sp, sp, -32 +80009e90: 23 2c 81 00 sw s0, 24(sp) +80009e94: 23 2a 91 00 sw s1, 20(sp) +80009e98: 23 28 21 01 sw s2, 16(sp) +80009e9c: 23 26 31 01 sw s3, 12(sp) +80009ea0: 23 24 41 01 sw s4, 8(sp) +80009ea4: 13 88 86 00 addi a6, a3, 8 +80009ea8: 93 07 90 00 addi a5, zero, 9 +80009eac: 23 2e 11 00 sw ra, 28(sp) +80009eb0: 23 22 51 01 sw s5, 4(sp) +80009eb4: 33 48 f8 02 div a6, a6, a5 +80009eb8: 93 89 06 00 mv s3, a3 +80009ebc: 13 09 05 00 mv s2, a0 +80009ec0: 13 84 05 00 mv s0, a1 +80009ec4: 13 0a 06 00 mv s4, a2 +80009ec8: 93 04 07 00 mv s1, a4 +80009ecc: 63 d8 d7 0c bge a5, a3, 208 +80009ed0: 93 07 10 00 addi a5, zero, 1 +80009ed4: 93 05 00 00 mv a1, zero +80009ed8: 93 97 17 00 slli a5, a5, 1 +80009edc: 93 85 15 00 addi a1, a1, 1 +80009ee0: e3 cc 07 ff blt a5, a6, -8 +80009ee4: 13 05 09 00 mv a0, s2 +80009ee8: ef f0 df d8 jal -628 +80009eec: 93 05 05 00 mv a1, a0 +80009ef0: 63 0a 05 0a beqz a0, 180 +80009ef4: 93 07 10 00 addi a5, zero, 1 +80009ef8: 23 28 f5 00 sw a5, 16(a0) +80009efc: 23 2a 95 00 sw s1, 20(a0) +80009f00: 93 07 90 00 addi a5, zero, 9 +80009f04: 63 d6 47 09 bge a5, s4, 140 +80009f08: 93 0a 94 00 addi s5, s0, 9 +80009f0c: 93 84 0a 00 mv s1, s5 +80009f10: 33 04 44 01 add s0, s0, s4 +80009f14: 83 c6 04 00 lbu a3, 0(s1) +80009f18: 13 06 a0 00 addi a2, zero, 10 +80009f1c: 13 05 09 00 mv a0, s2 +80009f20: 93 86 06 fd addi a3, a3, -48 +80009f24: ef f0 df e1 jal -484 +80009f28: 93 84 14 00 addi s1, s1, 1 +80009f2c: 93 05 05 00 mv a1, a0 +80009f30: e3 92 84 fe bne s1, s0, -28 +80009f34: 13 04 8a ff addi s0, s4, -8 +80009f38: 33 84 8a 00 add s0, s5, s0 +80009f3c: 63 56 3a 03 bge s4, s3, 44 +80009f40: b3 89 49 41 sub s3, s3, s4 +80009f44: b3 09 34 01 add s3, s0, s3 +80009f48: 83 46 04 00 lbu a3, 0(s0) +80009f4c: 13 06 a0 00 addi a2, zero, 10 +80009f50: 13 05 09 00 mv a0, s2 +80009f54: 93 86 06 fd addi a3, a3, -48 +80009f58: ef f0 9f de jal -536 +80009f5c: 13 04 14 00 addi s0, s0, 1 +80009f60: 93 05 05 00 mv a1, a0 +80009f64: e3 92 89 fe bne s3, s0, -28 +80009f68: 83 20 c1 01 lw ra, 28(sp) +80009f6c: 03 24 81 01 lw s0, 24(sp) +80009f70: 83 24 41 01 lw s1, 20(sp) +80009f74: 03 29 01 01 lw s2, 16(sp) +80009f78: 83 29 c1 00 lw s3, 12(sp) +80009f7c: 03 2a 81 00 lw s4, 8(sp) +80009f80: 83 2a 41 00 lw s5, 4(sp) +80009f84: 13 85 05 00 mv a0, a1 +80009f88: 13 01 01 02 addi sp, sp, 32 +80009f8c: 67 80 00 00 ret +80009f90: 13 04 a4 00 addi s0, s0, 10 +80009f94: 13 0a 90 00 addi s4, zero, 9 +80009f98: 6f f0 5f fa j -92 +80009f9c: 93 05 00 00 mv a1, zero +80009fa0: 6f f0 5f f4 j -188 +80009fa4: b7 66 01 80 lui a3, 524310 +80009fa8: 37 65 01 80 lui a0, 524310 +80009fac: 93 86 46 9e addi a3, a3, -1564 +80009fb0: 13 06 00 00 mv a2, zero +80009fb4: 93 05 e0 0c addi a1, zero, 206 +80009fb8: 13 05 85 9f addi a0, a0, -1544 +80009fbc: ef 20 80 38 jal 9096 + +80009fc0 __hi0bits: +80009fc0: 37 07 ff ff lui a4, 1048560 +80009fc4: 33 77 e5 00 and a4, a0, a4 +80009fc8: 93 07 05 00 mv a5, a0 +80009fcc: 13 05 00 00 mv a0, zero +80009fd0: 63 16 07 00 bnez a4, 12 +80009fd4: 93 97 07 01 slli a5, a5, 16 +80009fd8: 13 05 00 01 addi a0, zero, 16 +80009fdc: 37 07 00 ff lui a4, 1044480 +80009fe0: 33 f7 e7 00 and a4, a5, a4 +80009fe4: 63 16 07 00 bnez a4, 12 +80009fe8: 13 05 85 00 addi a0, a0, 8 +80009fec: 93 97 87 00 slli a5, a5, 8 +80009ff0: 37 07 00 f0 lui a4, 983040 +80009ff4: 33 f7 e7 00 and a4, a5, a4 +80009ff8: 63 16 07 00 bnez a4, 12 +80009ffc: 13 05 45 00 addi a0, a0, 4 +8000a000: 93 97 47 00 slli a5, a5, 4 +8000a004: 37 07 00 c0 lui a4, 786432 +8000a008: 33 f7 e7 00 and a4, a5, a4 +8000a00c: 63 16 07 00 bnez a4, 12 +8000a010: 13 05 25 00 addi a0, a0, 2 +8000a014: 93 97 27 00 slli a5, a5, 2 +8000a018: 63 c8 07 00 bltz a5, 16 +8000a01c: 13 97 17 00 slli a4, a5, 1 +8000a020: 13 05 15 00 addi a0, a0, 1 +8000a024: 63 54 07 00 bgez a4, 8 +8000a028: 67 80 00 00 ret +8000a02c: 13 05 00 02 addi a0, zero, 32 +8000a030: 67 80 00 00 ret + +8000a034 __lo0bits: +8000a034: 83 27 05 00 lw a5, 0(a0) +8000a038: 13 07 05 00 mv a4, a0 +8000a03c: 93 f6 77 00 andi a3, a5, 7 +8000a040: 63 84 06 02 beqz a3, 40 +8000a044: 93 f6 17 00 andi a3, a5, 1 +8000a048: 13 05 00 00 mv a0, zero +8000a04c: 63 9e 06 06 bnez a3, 124 +8000a050: 93 f6 27 00 andi a3, a5, 2 +8000a054: 63 80 06 08 beqz a3, 128 +8000a058: 93 d7 17 00 srli a5, a5, 1 +8000a05c: 23 20 f7 00 sw a5, 0(a4) +8000a060: 13 05 10 00 addi a0, zero, 1 +8000a064: 67 80 00 00 ret +8000a068: 93 96 07 01 slli a3, a5, 16 +8000a06c: 93 d6 06 01 srli a3, a3, 16 +8000a070: 13 05 00 00 mv a0, zero +8000a074: 63 96 06 00 bnez a3, 12 +8000a078: 93 d7 07 01 srli a5, a5, 16 +8000a07c: 13 05 00 01 addi a0, zero, 16 +8000a080: 93 f6 f7 0f andi a3, a5, 255 +8000a084: 63 96 06 00 bnez a3, 12 +8000a088: 13 05 85 00 addi a0, a0, 8 +8000a08c: 93 d7 87 00 srli a5, a5, 8 +8000a090: 93 f6 f7 00 andi a3, a5, 15 +8000a094: 63 96 06 00 bnez a3, 12 +8000a098: 13 05 45 00 addi a0, a0, 4 +8000a09c: 93 d7 47 00 srli a5, a5, 4 +8000a0a0: 93 f6 37 00 andi a3, a5, 3 +8000a0a4: 63 96 06 00 bnez a3, 12 +8000a0a8: 13 05 25 00 addi a0, a0, 2 +8000a0ac: 93 d7 27 00 srli a5, a5, 2 +8000a0b0: 93 f6 17 00 andi a3, a5, 1 +8000a0b4: 63 9c 06 00 bnez a3, 24 +8000a0b8: 93 d7 17 00 srli a5, a5, 1 +8000a0bc: 13 05 15 00 addi a0, a0, 1 +8000a0c0: 63 96 07 00 bnez a5, 12 +8000a0c4: 13 05 00 02 addi a0, zero, 32 +8000a0c8: 67 80 00 00 ret +8000a0cc: 23 20 f7 00 sw a5, 0(a4) +8000a0d0: 67 80 00 00 ret +8000a0d4: 93 d7 27 00 srli a5, a5, 2 +8000a0d8: 23 20 f7 00 sw a5, 0(a4) +8000a0dc: 13 05 20 00 addi a0, zero, 2 +8000a0e0: 67 80 00 00 ret + +8000a0e4 __i2b: +8000a0e4: 13 01 01 ff addi sp, sp, -16 +8000a0e8: 23 24 81 00 sw s0, 8(sp) +8000a0ec: 13 84 05 00 mv s0, a1 +8000a0f0: 93 05 10 00 addi a1, zero, 1 +8000a0f4: 23 26 11 00 sw ra, 12(sp) +8000a0f8: ef f0 df b7 jal -1156 +8000a0fc: 63 00 05 02 beqz a0, 32 +8000a100: 83 20 c1 00 lw ra, 12(sp) +8000a104: 23 2a 85 00 sw s0, 20(a0) +8000a108: 03 24 81 00 lw s0, 8(sp) +8000a10c: 13 07 10 00 addi a4, zero, 1 +8000a110: 23 28 e5 00 sw a4, 16(a0) +8000a114: 13 01 01 01 addi sp, sp, 16 +8000a118: 67 80 00 00 ret +8000a11c: b7 66 01 80 lui a3, 524310 +8000a120: 37 65 01 80 lui a0, 524310 +8000a124: 93 86 46 9e addi a3, a3, -1564 +8000a128: 13 06 00 00 mv a2, zero +8000a12c: 93 05 00 14 addi a1, zero, 320 +8000a130: 13 05 85 9f addi a0, a0, -1544 +8000a134: ef 20 00 21 jal 8720 + +8000a138 __multiply: +8000a138: 13 01 01 fe addi sp, sp, -32 +8000a13c: 23 28 21 01 sw s2, 16(sp) +8000a140: 23 26 31 01 sw s3, 12(sp) +8000a144: 03 a9 05 01 lw s2, 16(a1) +8000a148: 83 29 06 01 lw s3, 16(a2) +8000a14c: 23 2a 91 00 sw s1, 20(sp) +8000a150: 23 24 41 01 sw s4, 8(sp) +8000a154: 23 2e 11 00 sw ra, 28(sp) +8000a158: 23 2c 81 00 sw s0, 24(sp) +8000a15c: 13 8a 05 00 mv s4, a1 +8000a160: 93 04 06 00 mv s1, a2 +8000a164: 63 4c 39 01 blt s2, s3, 24 +8000a168: 13 87 09 00 mv a4, s3 +8000a16c: 93 84 05 00 mv s1, a1 +8000a170: 93 09 09 00 mv s3, s2 +8000a174: 13 0a 06 00 mv s4, a2 +8000a178: 13 09 07 00 mv s2, a4 +8000a17c: 83 a7 84 00 lw a5, 8(s1) +8000a180: 83 a5 44 00 lw a1, 4(s1) +8000a184: 33 84 29 01 add s0, s3, s2 +8000a188: b3 a7 87 00 slt a5, a5, s0 +8000a18c: b3 85 f5 00 add a1, a1, a5 +8000a190: ef f0 5f ae jal -1308 +8000a194: 63 0c 05 1a beqz a0, 440 +8000a198: 13 03 45 01 addi t1, a0, 20 +8000a19c: 93 18 24 00 slli a7, s0, 2 +8000a1a0: b3 08 13 01 add a7, t1, a7 +8000a1a4: 93 07 03 00 mv a5, t1 +8000a1a8: 63 78 13 01 bgeu t1, a7, 16 +8000a1ac: 23 a0 07 00 sw zero, 0(a5) +8000a1b0: 93 87 47 00 addi a5, a5, 4 +8000a1b4: e3 ec 17 ff bltu a5, a7, -8 +8000a1b8: 13 08 4a 01 addi a6, s4, 20 +8000a1bc: 13 1e 29 00 slli t3, s2, 2 +8000a1c0: 93 8e 44 01 addi t4, s1, 20 +8000a1c4: 93 95 29 00 slli a1, s3, 2 +8000a1c8: 33 0e c8 01 add t3, a6, t3 +8000a1cc: b3 85 be 00 add a1, t4, a1 +8000a1d0: 63 7c c8 0b bgeu a6, t3, 184 +8000a1d4: 93 87 54 01 addi a5, s1, 21 +8000a1d8: 13 0f 40 00 addi t5, zero, 4 +8000a1dc: 63 fe f5 14 bgeu a1, a5, 348 +8000a1e0: 37 06 01 00 lui a2, 16 +8000a1e4: 13 06 f6 ff addi a2, a2, -1 +8000a1e8: 6f 00 00 01 j 16 +8000a1ec: 13 08 48 00 addi a6, a6, 4 +8000a1f0: 13 03 43 00 addi t1, t1, 4 +8000a1f4: 63 7a c8 09 bgeu a6, t3, 148 +8000a1f8: 83 2f 08 00 lw t6, 0(a6) +8000a1fc: b3 f4 cf 00 and s1, t6, a2 +8000a200: 63 94 04 0c bnez s1, 200 +8000a204: 93 df 0f 01 srli t6, t6, 16 +8000a208: e3 82 0f fe beqz t6, -28 +8000a20c: 03 27 03 00 lw a4, 0(t1) +8000a210: 93 02 03 00 mv t0, t1 +8000a214: 93 86 0e 00 mv a3, t4 +8000a218: 93 04 07 00 mv s1, a4 +8000a21c: 93 03 00 00 mv t2, zero +8000a220: 83 a7 06 00 lw a5, 0(a3) +8000a224: 93 d9 04 01 srli s3, s1, 16 +8000a228: 33 77 c7 00 and a4, a4, a2 +8000a22c: b3 f7 c7 00 and a5, a5, a2 +8000a230: b3 87 f7 03 mul a5, a5, t6 +8000a234: 83 a4 42 00 lw s1, 4(t0) +8000a238: 93 82 42 00 addi t0, t0, 4 +8000a23c: 93 86 46 00 addi a3, a3, 4 +8000a240: 33 f9 c4 00 and s2, s1, a2 +8000a244: b3 87 37 01 add a5, a5, s3 +8000a248: b3 87 77 00 add a5, a5, t2 +8000a24c: 93 93 07 01 slli t2, a5, 16 +8000a250: 33 e7 e3 00 or a4, t2, a4 +8000a254: 23 ae e2 fe sw a4, -4(t0) +8000a258: 03 d7 e6 ff lhu a4, -2(a3) +8000a25c: 93 d7 07 01 srli a5, a5, 16 +8000a260: 33 07 f7 03 mul a4, a4, t6 +8000a264: 33 07 27 01 add a4, a4, s2 +8000a268: 33 07 f7 00 add a4, a4, a5 +8000a26c: 93 53 07 01 srli t2, a4, 16 +8000a270: e3 e8 b6 fa bltu a3, a1, -80 +8000a274: b3 07 e3 01 add a5, t1, t5 +8000a278: 23 a0 e7 00 sw a4, 0(a5) +8000a27c: 13 08 48 00 addi a6, a6, 4 +8000a280: 13 03 43 00 addi t1, t1, 4 +8000a284: e3 6a c8 f7 bltu a6, t3, -140 +8000a288: 63 48 80 00 bgtz s0, 16 +8000a28c: 6f 00 80 01 j 24 +8000a290: 13 04 f4 ff addi s0, s0, -1 +8000a294: 63 08 04 00 beqz s0, 16 +8000a298: 83 a7 c8 ff lw a5, -4(a7) +8000a29c: 93 88 c8 ff addi a7, a7, -4 +8000a2a0: e3 88 07 fe beqz a5, -16 +8000a2a4: 83 20 c1 01 lw ra, 28(sp) +8000a2a8: 23 28 85 00 sw s0, 16(a0) +8000a2ac: 03 24 81 01 lw s0, 24(sp) +8000a2b0: 83 24 41 01 lw s1, 20(sp) +8000a2b4: 03 29 01 01 lw s2, 16(sp) +8000a2b8: 83 29 c1 00 lw s3, 12(sp) +8000a2bc: 03 2a 81 00 lw s4, 8(sp) +8000a2c0: 13 01 01 02 addi sp, sp, 32 +8000a2c4: 67 80 00 00 ret +8000a2c8: 93 03 03 00 mv t2, t1 +8000a2cc: 93 82 0e 00 mv t0, t4 +8000a2d0: 13 09 00 00 mv s2, zero +8000a2d4: 03 a7 02 00 lw a4, 0(t0) +8000a2d8: 83 af 03 00 lw t6, 0(t2) +8000a2dc: 93 83 43 00 addi t2, t2, 4 +8000a2e0: b3 76 c7 00 and a3, a4, a2 +8000a2e4: b3 86 96 02 mul a3, a3, s1 +8000a2e8: 93 57 07 01 srli a5, a4, 16 +8000a2ec: 33 f7 cf 00 and a4, t6, a2 +8000a2f0: 93 df 0f 01 srli t6, t6, 16 +8000a2f4: 93 82 42 00 addi t0, t0, 4 +8000a2f8: b3 87 97 02 mul a5, a5, s1 +8000a2fc: b3 86 e6 00 add a3, a3, a4 +8000a300: b3 86 26 01 add a3, a3, s2 +8000a304: 13 d7 06 01 srli a4, a3, 16 +8000a308: b3 f6 c6 00 and a3, a3, a2 +8000a30c: b3 87 f7 01 add a5, a5, t6 +8000a310: b3 87 e7 00 add a5, a5, a4 +8000a314: 13 97 07 01 slli a4, a5, 16 +8000a318: b3 66 d7 00 or a3, a4, a3 +8000a31c: 23 ae d3 fe sw a3, -4(t2) +8000a320: 13 d9 07 01 srli s2, a5, 16 +8000a324: e3 e8 b2 fa bltu t0, a1, -80 +8000a328: b3 07 e3 01 add a5, t1, t5 +8000a32c: 23 a0 27 01 sw s2, 0(a5) +8000a330: 83 2f 08 00 lw t6, 0(a6) +8000a334: 6f f0 1f ed j -304 +8000a338: 33 8f 95 40 sub t5, a1, s1 +8000a33c: 13 0f bf fe addi t5, t5, -21 +8000a340: 13 7f cf ff andi t5, t5, -4 +8000a344: 13 0f 4f 00 addi t5, t5, 4 +8000a348: 6f f0 9f e9 j -360 +8000a34c: b7 66 01 80 lui a3, 524310 +8000a350: 37 65 01 80 lui a0, 524310 +8000a354: 93 86 46 9e addi a3, a3, -1564 +8000a358: 13 06 00 00 mv a2, zero +8000a35c: 93 05 d0 15 addi a1, zero, 349 +8000a360: 13 05 85 9f addi a0, a0, -1544 +8000a364: ef 10 10 7e jal 8160 + +8000a368 __pow5mult: +8000a368: 13 01 01 fe addi sp, sp, -32 +8000a36c: 23 2c 81 00 sw s0, 24(sp) +8000a370: 23 26 31 01 sw s3, 12(sp) +8000a374: 23 24 41 01 sw s4, 8(sp) +8000a378: 23 2e 11 00 sw ra, 28(sp) +8000a37c: 23 2a 91 00 sw s1, 20(sp) +8000a380: 23 28 21 01 sw s2, 16(sp) +8000a384: 93 77 36 00 andi a5, a2, 3 +8000a388: 13 04 06 00 mv s0, a2 +8000a38c: 93 09 05 00 mv s3, a0 +8000a390: 13 8a 05 00 mv s4, a1 +8000a394: 63 94 07 0c bnez a5, 200 +8000a398: 13 54 24 40 srai s0, s0, 2 +8000a39c: 13 09 0a 00 mv s2, s4 +8000a3a0: 63 08 04 06 beqz s0, 112 +8000a3a4: 83 a4 89 04 lw s1, 72(s3) +8000a3a8: 63 8e 04 0c beqz s1, 220 +8000a3ac: 93 77 14 00 andi a5, s0, 1 +8000a3b0: 13 09 0a 00 mv s2, s4 +8000a3b4: 63 90 07 02 bnez a5, 32 +8000a3b8: 13 54 14 40 srai s0, s0, 1 +8000a3bc: 63 0a 04 04 beqz s0, 84 +8000a3c0: 03 a5 04 00 lw a0, 0(s1) +8000a3c4: 63 08 05 06 beqz a0, 112 +8000a3c8: 93 04 05 00 mv s1, a0 +8000a3cc: 93 77 14 00 andi a5, s0, 1 +8000a3d0: e3 84 07 fe beqz a5, -24 +8000a3d4: 13 86 04 00 mv a2, s1 +8000a3d8: 93 05 09 00 mv a1, s2 +8000a3dc: 13 85 09 00 mv a0, s3 +8000a3e0: ef f0 9f d5 jal -680 +8000a3e4: 63 08 09 06 beqz s2, 112 +8000a3e8: 03 27 49 00 lw a4, 4(s2) +8000a3ec: 83 a7 c9 04 lw a5, 76(s3) +8000a3f0: 13 54 14 40 srai s0, s0, 1 +8000a3f4: 13 17 27 00 slli a4, a4, 2 +8000a3f8: b3 87 e7 00 add a5, a5, a4 +8000a3fc: 03 a7 07 00 lw a4, 0(a5) +8000a400: 23 20 e9 00 sw a4, 0(s2) +8000a404: 23 a0 27 01 sw s2, 0(a5) +8000a408: 13 09 05 00 mv s2, a0 +8000a40c: e3 1a 04 fa bnez s0, -76 +8000a410: 83 20 c1 01 lw ra, 28(sp) +8000a414: 03 24 81 01 lw s0, 24(sp) +8000a418: 83 24 41 01 lw s1, 20(sp) +8000a41c: 83 29 c1 00 lw s3, 12(sp) +8000a420: 03 2a 81 00 lw s4, 8(sp) +8000a424: 13 05 09 00 mv a0, s2 +8000a428: 03 29 01 01 lw s2, 16(sp) +8000a42c: 13 01 01 02 addi sp, sp, 32 +8000a430: 67 80 00 00 ret +8000a434: 13 86 04 00 mv a2, s1 +8000a438: 93 85 04 00 mv a1, s1 +8000a43c: 13 85 09 00 mv a0, s3 +8000a440: ef f0 9f cf jal -776 +8000a444: 23 a0 a4 00 sw a0, 0(s1) +8000a448: 23 20 05 00 sw zero, 0(a0) +8000a44c: 93 04 05 00 mv s1, a0 +8000a450: 6f f0 df f7 j -132 +8000a454: 13 09 05 00 mv s2, a0 +8000a458: 6f f0 1f f6 j -160 +8000a45c: 93 87 f7 ff addi a5, a5, -1 +8000a460: 37 67 01 80 lui a4, 524310 +8000a464: 13 07 07 a5 addi a4, a4, -1456 +8000a468: 93 97 27 00 slli a5, a5, 2 +8000a46c: b3 07 f7 00 add a5, a4, a5 +8000a470: 03 a6 07 00 lw a2, 0(a5) +8000a474: 93 06 00 00 mv a3, zero +8000a478: ef f0 9f 8c jal -1848 +8000a47c: 13 0a 05 00 mv s4, a0 +8000a480: 6f f0 9f f1 j -232 +8000a484: 93 05 10 27 addi a1, zero, 625 +8000a488: 13 85 09 00 mv a0, s3 +8000a48c: ef f0 9f c5 jal -936 +8000a490: 23 a4 a9 04 sw a0, 72(s3) +8000a494: 93 04 05 00 mv s1, a0 +8000a498: 23 20 05 00 sw zero, 0(a0) +8000a49c: 6f f0 1f f1 j -240 + +8000a4a0 __lshift: +8000a4a0: 13 01 01 fe addi sp, sp, -32 +8000a4a4: 23 24 41 01 sw s4, 8(sp) +8000a4a8: 03 aa 05 01 lw s4, 16(a1) +8000a4ac: 83 a7 85 00 lw a5, 8(a1) +8000a4b0: 23 26 31 01 sw s3, 12(sp) +8000a4b4: 93 59 56 40 srai s3, a2, 5 +8000a4b8: 33 8a 49 01 add s4, s3, s4 +8000a4bc: 23 2c 81 00 sw s0, 24(sp) +8000a4c0: 23 2a 91 00 sw s1, 20(sp) +8000a4c4: 23 28 21 01 sw s2, 16(sp) +8000a4c8: 23 22 51 01 sw s5, 4(sp) +8000a4cc: 23 2e 11 00 sw ra, 28(sp) +8000a4d0: 13 09 1a 00 addi s2, s4, 1 +8000a4d4: 93 84 05 00 mv s1, a1 +8000a4d8: 13 04 06 00 mv s0, a2 +8000a4dc: 83 a5 45 00 lw a1, 4(a1) +8000a4e0: 93 0a 05 00 mv s5, a0 +8000a4e4: 63 d8 27 01 bge a5, s2, 16 +8000a4e8: 93 97 17 00 slli a5, a5, 1 +8000a4ec: 93 85 15 00 addi a1, a1, 1 +8000a4f0: e3 cc 27 ff blt a5, s2, -8 +8000a4f4: 13 85 0a 00 mv a0, s5 +8000a4f8: ef f0 cf f7 jal -2180 +8000a4fc: 63 0c 05 10 beqz a0, 280 +8000a500: 13 08 45 01 addi a6, a0, 20 +8000a504: 63 54 30 03 blez s3, 40 +8000a508: 93 89 59 00 addi s3, s3, 5 +8000a50c: 93 99 29 00 slli s3, s3, 2 +8000a510: 33 07 35 01 add a4, a0, s3 +8000a514: 93 07 08 00 mv a5, a6 +8000a518: 93 87 47 00 addi a5, a5, 4 +8000a51c: 23 ae 07 fe sw zero, -4(a5) +8000a520: e3 9c e7 fe bne a5, a4, -8 +8000a524: 93 89 c9 fe addi s3, s3, -20 +8000a528: 33 08 38 01 add a6, a6, s3 +8000a52c: 03 a7 04 01 lw a4, 16(s1) +8000a530: 93 87 44 01 addi a5, s1, 20 +8000a534: 13 73 f4 01 andi t1, s0, 31 +8000a538: 13 16 27 00 slli a2, a4, 2 +8000a53c: 33 86 c7 00 add a2, a5, a2 +8000a540: 63 04 03 0a beqz t1, 168 +8000a544: 93 05 00 02 addi a1, zero, 32 +8000a548: b3 85 65 40 sub a1, a1, t1 +8000a54c: 93 08 08 00 mv a7, a6 +8000a550: 93 06 00 00 mv a3, zero +8000a554: 03 a7 07 00 lw a4, 0(a5) +8000a558: 93 88 48 00 addi a7, a7, 4 +8000a55c: 93 87 47 00 addi a5, a5, 4 +8000a560: 33 17 67 00 sll a4, a4, t1 +8000a564: 33 67 d7 00 or a4, a4, a3 +8000a568: 23 ae e8 fe sw a4, -4(a7) +8000a56c: 03 a7 c7 ff lw a4, -4(a5) +8000a570: b3 56 b7 00 srl a3, a4, a1 +8000a574: e3 e0 c7 fe bltu a5, a2, -32 +8000a578: 13 87 54 01 addi a4, s1, 21 +8000a57c: 93 07 40 00 addi a5, zero, 4 +8000a580: 63 6a e6 00 bltu a2, a4, 20 +8000a584: b3 07 96 40 sub a5, a2, s1 +8000a588: 93 87 b7 fe addi a5, a5, -21 +8000a58c: 93 f7 c7 ff andi a5, a5, -4 +8000a590: 93 87 47 00 addi a5, a5, 4 +8000a594: 33 08 f8 00 add a6, a6, a5 +8000a598: 23 20 d8 00 sw a3, 0(a6) +8000a59c: 63 84 06 00 beqz a3, 8 +8000a5a0: 13 0a 09 00 mv s4, s2 +8000a5a4: 03 a7 44 00 lw a4, 4(s1) +8000a5a8: 83 a7 ca 04 lw a5, 76(s5) +8000a5ac: 83 20 c1 01 lw ra, 28(sp) +8000a5b0: 13 17 27 00 slli a4, a4, 2 +8000a5b4: b3 87 e7 00 add a5, a5, a4 +8000a5b8: 03 a7 07 00 lw a4, 0(a5) +8000a5bc: 23 28 45 01 sw s4, 16(a0) +8000a5c0: 03 24 81 01 lw s0, 24(sp) +8000a5c4: 23 a0 e4 00 sw a4, 0(s1) +8000a5c8: 23 a0 97 00 sw s1, 0(a5) +8000a5cc: 03 29 01 01 lw s2, 16(sp) +8000a5d0: 83 24 41 01 lw s1, 20(sp) +8000a5d4: 83 29 c1 00 lw s3, 12(sp) +8000a5d8: 03 2a 81 00 lw s4, 8(sp) +8000a5dc: 83 2a 41 00 lw s5, 4(sp) +8000a5e0: 13 01 01 02 addi sp, sp, 32 +8000a5e4: 67 80 00 00 ret +8000a5e8: 03 a7 07 00 lw a4, 0(a5) +8000a5ec: 93 87 47 00 addi a5, a5, 4 +8000a5f0: 13 08 48 00 addi a6, a6, 4 +8000a5f4: 23 2e e8 fe sw a4, -4(a6) +8000a5f8: e3 f6 c7 fa bgeu a5, a2, -84 +8000a5fc: 03 a7 07 00 lw a4, 0(a5) +8000a600: 93 87 47 00 addi a5, a5, 4 +8000a604: 13 08 48 00 addi a6, a6, 4 +8000a608: 23 2e e8 fe sw a4, -4(a6) +8000a60c: e3 ee c7 fc bltu a5, a2, -36 +8000a610: 6f f0 5f f9 j -108 +8000a614: b7 66 01 80 lui a3, 524310 +8000a618: 37 65 01 80 lui a0, 524310 +8000a61c: 93 86 46 9e addi a3, a3, -1564 +8000a620: 13 06 00 00 mv a2, zero +8000a624: 93 05 90 1d addi a1, zero, 473 +8000a628: 13 05 85 9f addi a0, a0, -1544 +8000a62c: ef 10 90 51 jal 7448 + +8000a630 __mcmp: +8000a630: 03 27 05 01 lw a4, 16(a0) +8000a634: 83 a7 05 01 lw a5, 16(a1) +8000a638: 13 08 05 00 mv a6, a0 +8000a63c: 33 05 f7 40 sub a0, a4, a5 +8000a640: 63 14 f7 04 bne a4, a5, 72 +8000a644: 93 97 27 00 slli a5, a5, 2 +8000a648: 13 08 48 01 addi a6, a6, 20 +8000a64c: 93 85 45 01 addi a1, a1, 20 +8000a650: 33 07 f8 00 add a4, a6, a5 +8000a654: b3 87 f5 00 add a5, a1, a5 +8000a658: 6f 00 80 00 j 8 +8000a65c: 63 76 e8 02 bgeu a6, a4, 44 +8000a660: 83 26 c7 ff lw a3, -4(a4) +8000a664: 03 a6 c7 ff lw a2, -4(a5) +8000a668: 13 07 c7 ff addi a4, a4, -4 +8000a66c: 93 87 c7 ff addi a5, a5, -4 +8000a670: e3 86 c6 fe beq a3, a2, -20 +8000a674: b3 b6 c6 00 sltu a3, a3, a2 +8000a678: 33 05 d0 40 neg a0, a3 +8000a67c: 13 75 e5 ff andi a0, a0, -2 +8000a680: 13 05 15 00 addi a0, a0, 1 +8000a684: 67 80 00 00 ret +8000a688: 67 80 00 00 ret + +8000a68c __mdiff: +8000a68c: 83 a7 05 01 lw a5, 16(a1) +8000a690: 03 27 06 01 lw a4, 16(a2) +8000a694: 13 01 01 ff addi sp, sp, -16 +8000a698: 23 24 81 00 sw s0, 8(sp) +8000a69c: 23 22 91 00 sw s1, 4(sp) +8000a6a0: 23 20 21 01 sw s2, 0(sp) +8000a6a4: 23 26 11 00 sw ra, 12(sp) +8000a6a8: 93 84 05 00 mv s1, a1 +8000a6ac: 13 04 06 00 mv s0, a2 +8000a6b0: 33 89 e7 40 sub s2, a5, a4 +8000a6b4: 63 94 e7 1a bne a5, a4, 424 +8000a6b8: 93 16 27 00 slli a3, a4, 2 +8000a6bc: 93 85 45 01 addi a1, a1, 20 +8000a6c0: 13 07 46 01 addi a4, a2, 20 +8000a6c4: b3 87 d5 00 add a5, a1, a3 +8000a6c8: 33 07 d7 00 add a4, a4, a3 +8000a6cc: 6f 00 80 00 j 8 +8000a6d0: 63 fc f5 18 bgeu a1, a5, 408 +8000a6d4: 03 a6 c7 ff lw a2, -4(a5) +8000a6d8: 83 26 c7 ff lw a3, -4(a4) +8000a6dc: 93 87 c7 ff addi a5, a5, -4 +8000a6e0: 13 07 c7 ff addi a4, a4, -4 +8000a6e4: e3 06 d6 fe beq a2, a3, -20 +8000a6e8: 63 60 d6 16 bltu a2, a3, 352 +8000a6ec: 83 a5 44 00 lw a1, 4(s1) +8000a6f0: ef f0 4f d8 jal -2684 +8000a6f4: 63 02 05 1a beqz a0, 420 +8000a6f8: 03 ae 04 01 lw t3, 16(s1) +8000a6fc: 83 22 04 01 lw t0, 16(s0) +8000a700: 93 8f 44 01 addi t6, s1, 20 +8000a704: 93 1e 2e 00 slli t4, t3, 2 +8000a708: 13 08 44 01 addi a6, s0, 20 +8000a70c: 93 92 22 00 slli t0, t0, 2 +8000a710: 93 03 45 01 addi t2, a0, 20 +8000a714: b7 08 01 00 lui a7, 16 +8000a718: 23 26 25 01 sw s2, 12(a0) +8000a71c: b3 8e df 01 add t4, t6, t4 +8000a720: b3 02 58 00 add t0, a6, t0 +8000a724: 13 8f 03 00 mv t5, t2 +8000a728: 13 83 0f 00 mv t1, t6 +8000a72c: 93 07 00 00 mv a5, zero +8000a730: 93 88 f8 ff addi a7, a7, -1 +8000a734: 03 27 03 00 lw a4, 0(t1) +8000a738: 83 25 08 00 lw a1, 0(a6) +8000a73c: 13 0f 4f 00 addi t5, t5, 4 +8000a740: b3 76 17 01 and a3, a4, a7 +8000a744: b3 86 f6 00 add a3, a3, a5 +8000a748: b3 f7 15 01 and a5, a1, a7 +8000a74c: b3 86 f6 40 sub a3, a3, a5 +8000a750: 93 d5 05 01 srli a1, a1, 16 +8000a754: 93 57 07 01 srli a5, a4, 16 +8000a758: b3 87 b7 40 sub a5, a5, a1 +8000a75c: 13 d7 06 41 srai a4, a3, 16 +8000a760: b3 87 e7 00 add a5, a5, a4 +8000a764: 13 97 07 01 slli a4, a5, 16 +8000a768: b3 f6 16 01 and a3, a3, a7 +8000a76c: b3 66 d7 00 or a3, a4, a3 +8000a770: 13 08 48 00 addi a6, a6, 4 +8000a774: 23 2e df fe sw a3, -4(t5) +8000a778: 13 03 43 00 addi t1, t1, 4 +8000a77c: 93 d7 07 41 srai a5, a5, 16 +8000a780: e3 6a 58 fa bltu a6, t0, -76 +8000a784: b3 85 82 40 sub a1, t0, s0 +8000a788: 93 85 b5 fe addi a1, a1, -21 +8000a78c: 13 04 54 01 addi s0, s0, 21 +8000a790: 93 d5 25 00 srli a1, a1, 2 +8000a794: 13 07 00 00 mv a4, zero +8000a798: 63 e4 82 00 bltu t0, s0, 8 +8000a79c: 13 97 25 00 slli a4, a1, 2 +8000a7a0: 33 87 e3 00 add a4, t2, a4 +8000a7a4: 13 08 40 00 addi a6, zero, 4 +8000a7a8: 63 e6 82 00 bltu t0, s0, 12 +8000a7ac: 93 85 15 00 addi a1, a1, 1 +8000a7b0: 13 98 25 00 slli a6, a1, 2 +8000a7b4: b3 8f 0f 01 add t6, t6, a6 +8000a7b8: b3 83 03 01 add t2, t2, a6 +8000a7bc: 63 fe df 05 bgeu t6, t4, 92 +8000a7c0: b7 08 01 00 lui a7, 16 +8000a7c4: 13 88 03 00 mv a6, t2 +8000a7c8: 93 85 0f 00 mv a1, t6 +8000a7cc: 93 88 f8 ff addi a7, a7, -1 +8000a7d0: 03 a7 05 00 lw a4, 0(a1) +8000a7d4: 13 08 48 00 addi a6, a6, 4 +8000a7d8: 93 85 45 00 addi a1, a1, 4 +8000a7dc: 33 76 17 01 and a2, a4, a7 +8000a7e0: 33 06 f6 00 add a2, a2, a5 +8000a7e4: 93 56 06 41 srai a3, a2, 16 +8000a7e8: 93 57 07 01 srli a5, a4, 16 +8000a7ec: b3 87 d7 00 add a5, a5, a3 +8000a7f0: 93 96 07 01 slli a3, a5, 16 +8000a7f4: 33 76 16 01 and a2, a2, a7 +8000a7f8: b3 e6 c6 00 or a3, a3, a2 +8000a7fc: 23 2e d8 fe sw a3, -4(a6) +8000a800: 93 d7 07 41 srai a5, a5, 16 +8000a804: e3 e6 d5 fd bltu a1, t4, -52 +8000a808: 13 87 fe ff addi a4, t4, -1 +8000a80c: b3 0f f7 41 sub t6, a4, t6 +8000a810: 13 f7 cf ff andi a4, t6, -4 +8000a814: 33 87 e3 00 add a4, t2, a4 +8000a818: 63 9a 06 00 bnez a3, 20 +8000a81c: 83 27 c7 ff lw a5, -4(a4) +8000a820: 13 0e fe ff addi t3, t3, -1 +8000a824: 13 07 c7 ff addi a4, a4, -4 +8000a828: e3 8a 07 fe beqz a5, -12 +8000a82c: 83 20 c1 00 lw ra, 12(sp) +8000a830: 03 24 81 00 lw s0, 8(sp) +8000a834: 23 28 c5 01 sw t3, 16(a0) +8000a838: 83 24 41 00 lw s1, 4(sp) +8000a83c: 03 29 01 00 lw s2, 0(sp) +8000a840: 13 01 01 01 addi sp, sp, 16 +8000a844: 67 80 00 00 ret +8000a848: 93 87 04 00 mv a5, s1 +8000a84c: 13 09 10 00 addi s2, zero, 1 +8000a850: 93 04 04 00 mv s1, s0 +8000a854: 13 84 07 00 mv s0, a5 +8000a858: 6f f0 5f e9 j -364 +8000a85c: e3 46 09 fe bltz s2, -20 +8000a860: 13 09 00 00 mv s2, zero +8000a864: 6f f0 9f e8 j -376 +8000a868: 93 05 00 00 mv a1, zero +8000a86c: ef f0 8f c0 jal -3064 +8000a870: 63 02 05 04 beqz a0, 68 +8000a874: 83 20 c1 00 lw ra, 12(sp) +8000a878: 03 24 81 00 lw s0, 8(sp) +8000a87c: 93 07 10 00 addi a5, zero, 1 +8000a880: 23 28 f5 00 sw a5, 16(a0) +8000a884: 23 2a 05 00 sw zero, 20(a0) +8000a888: 83 24 41 00 lw s1, 4(sp) +8000a88c: 03 29 01 00 lw s2, 0(sp) +8000a890: 13 01 01 01 addi sp, sp, 16 +8000a894: 67 80 00 00 ret +8000a898: b7 66 01 80 lui a3, 524310 +8000a89c: 37 65 01 80 lui a0, 524310 +8000a8a0: 93 86 46 9e addi a3, a3, -1564 +8000a8a4: 13 06 00 00 mv a2, zero +8000a8a8: 93 05 00 24 addi a1, zero, 576 +8000a8ac: 13 05 85 9f addi a0, a0, -1544 +8000a8b0: ef 10 50 29 jal 6804 +8000a8b4: b7 66 01 80 lui a3, 524310 +8000a8b8: 37 65 01 80 lui a0, 524310 +8000a8bc: 93 86 46 9e addi a3, a3, -1564 +8000a8c0: 13 06 00 00 mv a2, zero +8000a8c4: 93 05 20 23 addi a1, zero, 562 +8000a8c8: 13 05 85 9f addi a0, a0, -1544 +8000a8cc: ef 10 90 27 jal 6776 + +8000a8d0 __ulp: +8000a8d0: b7 07 f0 7f lui a5, 524032 +8000a8d4: b3 f5 b7 00 and a1, a5, a1 +8000a8d8: b7 07 c0 fc lui a5, 1035264 +8000a8dc: b3 85 f5 00 add a1, a1, a5 +8000a8e0: 63 58 b0 00 blez a1, 16 +8000a8e4: 93 07 00 00 mv a5, zero +8000a8e8: 13 85 07 00 mv a0, a5 +8000a8ec: 67 80 00 00 ret +8000a8f0: b3 05 b0 40 neg a1, a1 +8000a8f4: 93 d5 45 41 srai a1, a1, 20 +8000a8f8: 93 07 30 01 addi a5, zero, 19 +8000a8fc: 63 c8 b7 00 blt a5, a1, 16 +8000a900: b7 07 08 00 lui a5, 128 +8000a904: b3 d5 b7 40 sra a1, a5, a1 +8000a908: 6f f0 df fd j -36 +8000a90c: 13 87 c5 fe addi a4, a1, -20 +8000a910: 93 06 e0 01 addi a3, zero, 30 +8000a914: 93 05 00 00 mv a1, zero +8000a918: 93 07 10 00 addi a5, zero, 1 +8000a91c: e3 c6 e6 fc blt a3, a4, -52 +8000a920: b7 07 00 80 lui a5, 524288 +8000a924: b3 d7 e7 00 srl a5, a5, a4 +8000a928: 13 85 07 00 mv a0, a5 +8000a92c: 67 80 00 00 ret + +8000a930 __b2d: +8000a930: 13 01 01 fe addi sp, sp, -32 +8000a934: 23 2a 91 00 sw s1, 20(sp) +8000a938: 83 24 05 01 lw s1, 16(a0) +8000a93c: 23 2c 81 00 sw s0, 24(sp) +8000a940: 13 04 45 01 addi s0, a0, 20 +8000a944: 93 94 24 00 slli s1, s1, 2 +8000a948: b3 04 94 00 add s1, s0, s1 +8000a94c: 23 28 21 01 sw s2, 16(sp) +8000a950: 03 a9 c4 ff lw s2, -4(s1) +8000a954: 23 26 31 01 sw s3, 12(sp) +8000a958: 23 24 41 01 sw s4, 8(sp) +8000a95c: 13 05 09 00 mv a0, s2 +8000a960: 93 89 05 00 mv s3, a1 +8000a964: 23 2e 11 00 sw ra, 28(sp) +8000a968: ef f0 8f e5 jal -2472 +8000a96c: 13 07 00 02 addi a4, zero, 32 +8000a970: b3 07 a7 40 sub a5, a4, a0 +8000a974: 23 a0 f9 00 sw a5, 0(s3) +8000a978: 93 07 a0 00 addi a5, zero, 10 +8000a97c: 13 8a c4 ff addi s4, s1, -4 +8000a980: 63 d0 a7 08 bge a5, a0, 128 +8000a984: 13 05 55 ff addi a0, a0, -11 +8000a988: 63 70 44 05 bgeu s0, s4, 64 +8000a98c: 83 a7 84 ff lw a5, -8(s1) +8000a990: 63 00 05 04 beqz a0, 64 +8000a994: b3 06 a7 40 sub a3, a4, a0 +8000a998: 33 d7 d7 00 srl a4, a5, a3 +8000a99c: 33 19 a9 00 sll s2, s2, a0 +8000a9a0: 33 69 e9 00 or s2, s2, a4 +8000a9a4: 13 86 84 ff addi a2, s1, -8 +8000a9a8: 37 07 f0 3f lui a4, 261888 +8000a9ac: 33 67 e9 00 or a4, s2, a4 +8000a9b0: b3 97 a7 00 sll a5, a5, a0 +8000a9b4: 63 72 c4 02 bgeu s0, a2, 36 +8000a9b8: 03 a6 44 ff lw a2, -12(s1) +8000a9bc: b3 56 d6 00 srl a3, a2, a3 +8000a9c0: b3 e7 d7 00 or a5, a5, a3 +8000a9c4: 6f 00 40 01 j 20 +8000a9c8: 93 07 00 00 mv a5, zero +8000a9cc: 63 14 05 06 bnez a0, 104 +8000a9d0: 37 07 f0 3f lui a4, 261888 +8000a9d4: 33 67 e9 00 or a4, s2, a4 +8000a9d8: 83 20 c1 01 lw ra, 28(sp) +8000a9dc: 03 24 81 01 lw s0, 24(sp) +8000a9e0: 83 24 41 01 lw s1, 20(sp) +8000a9e4: 03 29 01 01 lw s2, 16(sp) +8000a9e8: 83 29 c1 00 lw s3, 12(sp) +8000a9ec: 03 2a 81 00 lw s4, 8(sp) +8000a9f0: 13 85 07 00 mv a0, a5 +8000a9f4: 93 05 07 00 mv a1, a4 +8000a9f8: 13 01 01 02 addi sp, sp, 32 +8000a9fc: 67 80 00 00 ret +8000aa00: 93 06 b0 00 addi a3, zero, 11 +8000aa04: b3 86 a6 40 sub a3, a3, a0 +8000aa08: b7 07 f0 3f lui a5, 261888 +8000aa0c: 33 57 d9 00 srl a4, s2, a3 +8000aa10: 33 67 f7 00 or a4, a4, a5 +8000aa14: 93 07 00 00 mv a5, zero +8000aa18: 63 76 44 01 bgeu s0, s4, 12 +8000aa1c: 83 a7 84 ff lw a5, -8(s1) +8000aa20: b3 d7 d7 00 srl a5, a5, a3 +8000aa24: 13 05 55 01 addi a0, a0, 21 +8000aa28: 33 15 a9 00 sll a0, s2, a0 +8000aa2c: b3 67 f5 00 or a5, a0, a5 +8000aa30: 6f f0 9f fa j -88 +8000aa34: 33 15 a9 00 sll a0, s2, a0 +8000aa38: 37 07 f0 3f lui a4, 261888 +8000aa3c: 33 67 e5 00 or a4, a0, a4 +8000aa40: 93 07 00 00 mv a5, zero +8000aa44: 6f f0 5f f9 j -108 + +8000aa48 __d2b: +8000aa48: 13 01 01 fd addi sp, sp, -48 +8000aa4c: 23 2c 41 01 sw s4, 24(sp) +8000aa50: 13 8a 05 00 mv s4, a1 +8000aa54: 93 05 10 00 addi a1, zero, 1 +8000aa58: 23 22 91 02 sw s1, 36(sp) +8000aa5c: 23 20 21 03 sw s2, 32(sp) +8000aa60: 23 2e 31 01 sw s3, 28(sp) +8000aa64: 23 26 11 02 sw ra, 44(sp) +8000aa68: 23 24 81 02 sw s0, 40(sp) +8000aa6c: 23 2a 51 01 sw s5, 20(sp) +8000aa70: 93 04 06 00 mv s1, a2 +8000aa74: 93 89 06 00 mv s3, a3 +8000aa78: 13 09 07 00 mv s2, a4 +8000aa7c: ef f0 8f 9f jal -3592 +8000aa80: 63 0a 05 10 beqz a0, 276 +8000aa84: 93 d7 44 01 srli a5, s1, 20 +8000aa88: 37 07 10 00 lui a4, 256 +8000aa8c: 13 06 f7 ff addi a2, a4, -1 +8000aa90: 93 96 57 01 slli a3, a5, 21 +8000aa94: 13 04 05 00 mv s0, a0 +8000aa98: 33 76 96 00 and a2, a2, s1 +8000aa9c: 93 fa f7 7f andi s5, a5, 2047 +8000aaa0: 63 84 06 00 beqz a3, 8 +8000aaa4: 33 66 e6 00 or a2, a2, a4 +8000aaa8: 23 26 c1 00 sw a2, 12(sp) +8000aaac: 63 08 0a 08 beqz s4, 144 +8000aab0: 13 05 81 00 addi a0, sp, 8 +8000aab4: 23 24 41 01 sw s4, 8(sp) +8000aab8: ef f0 cf d7 jal -2692 +8000aabc: 03 27 c1 00 lw a4, 12(sp) +8000aac0: 93 07 05 00 mv a5, a0 +8000aac4: 63 02 05 0c beqz a0, 196 +8000aac8: 03 26 81 00 lw a2, 8(sp) +8000aacc: 93 06 00 02 addi a3, zero, 32 +8000aad0: b3 86 a6 40 sub a3, a3, a0 +8000aad4: b3 16 d7 00 sll a3, a4, a3 +8000aad8: b3 e6 c6 00 or a3, a3, a2 +8000aadc: 33 57 a7 00 srl a4, a4, a0 +8000aae0: 23 2a d4 00 sw a3, 20(s0) +8000aae4: 23 26 e1 00 sw a4, 12(sp) +8000aae8: b3 34 e0 00 snez s1, a4 +8000aaec: 93 84 14 00 addi s1, s1, 1 +8000aaf0: 23 2c e4 00 sw a4, 24(s0) +8000aaf4: 23 28 94 00 sw s1, 16(s0) +8000aaf8: 63 84 0a 06 beqz s5, 104 +8000aafc: 93 8a da bc addi s5, s5, -1075 +8000ab00: b3 8a fa 00 add s5, s5, a5 +8000ab04: 13 05 50 03 addi a0, zero, 53 +8000ab08: 23 a0 59 01 sw s5, 0(s3) +8000ab0c: b3 07 f5 40 sub a5, a0, a5 +8000ab10: 23 20 f9 00 sw a5, 0(s2) +8000ab14: 83 20 c1 02 lw ra, 44(sp) +8000ab18: 13 05 04 00 mv a0, s0 +8000ab1c: 03 24 81 02 lw s0, 40(sp) +8000ab20: 83 24 41 02 lw s1, 36(sp) +8000ab24: 03 29 01 02 lw s2, 32(sp) +8000ab28: 83 29 c1 01 lw s3, 28(sp) +8000ab2c: 03 2a 81 01 lw s4, 24(sp) +8000ab30: 83 2a 41 01 lw s5, 20(sp) +8000ab34: 13 01 01 03 addi sp, sp, 48 +8000ab38: 67 80 00 00 ret +8000ab3c: 13 05 c1 00 addi a0, sp, 12 +8000ab40: ef f0 4f cf jal -2828 +8000ab44: 93 07 10 00 addi a5, zero, 1 +8000ab48: 23 28 f4 00 sw a5, 16(s0) +8000ab4c: 83 27 c1 00 lw a5, 12(sp) +8000ab50: 93 04 10 00 addi s1, zero, 1 +8000ab54: 23 2a f4 00 sw a5, 20(s0) +8000ab58: 93 07 05 02 addi a5, a0, 32 +8000ab5c: e3 90 0a fa bnez s5, -96 +8000ab60: 13 97 24 00 slli a4, s1, 2 +8000ab64: 33 07 e4 00 add a4, s0, a4 +8000ab68: 03 25 07 01 lw a0, 16(a4) +8000ab6c: 93 87 e7 bc addi a5, a5, -1074 +8000ab70: 23 a0 f9 00 sw a5, 0(s3) +8000ab74: ef f0 cf c4 jal -2996 +8000ab78: 93 94 54 00 slli s1, s1, 5 +8000ab7c: b3 84 a4 40 sub s1, s1, a0 +8000ab80: 23 20 99 00 sw s1, 0(s2) +8000ab84: 6f f0 1f f9 j -112 +8000ab88: 83 26 81 00 lw a3, 8(sp) +8000ab8c: 23 2a d4 00 sw a3, 20(s0) +8000ab90: 6f f0 9f f5 j -168 +8000ab94: b7 66 01 80 lui a3, 524310 +8000ab98: 37 65 01 80 lui a0, 524310 +8000ab9c: 93 86 46 9e addi a3, a3, -1564 +8000aba0: 13 06 00 00 mv a2, zero +8000aba4: 93 05 a0 30 addi a1, zero, 778 +8000aba8: 13 05 85 9f addi a0, a0, -1544 +8000abac: ef 10 80 79 jal 6040 + +8000abb0 __ratio: +8000abb0: 13 01 01 fd addi sp, sp, -48 +8000abb4: 23 20 21 03 sw s2, 32(sp) +8000abb8: 13 89 05 00 mv s2, a1 +8000abbc: 93 05 81 00 addi a1, sp, 8 +8000abc0: 23 26 11 02 sw ra, 44(sp) +8000abc4: 23 24 81 02 sw s0, 40(sp) +8000abc8: 23 22 91 02 sw s1, 36(sp) +8000abcc: 23 2e 31 01 sw s3, 28(sp) +8000abd0: 93 09 05 00 mv s3, a0 +8000abd4: ef f0 df d5 jal -676 +8000abd8: 93 04 05 00 mv s1, a0 +8000abdc: 13 84 05 00 mv s0, a1 +8000abe0: 13 05 09 00 mv a0, s2 +8000abe4: 93 05 c1 00 addi a1, sp, 12 +8000abe8: ef f0 9f d4 jal -696 +8000abec: 83 27 09 01 lw a5, 16(s2) +8000abf0: 03 a7 09 01 lw a4, 16(s3) +8000abf4: 83 26 c1 00 lw a3, 12(sp) +8000abf8: 33 07 f7 40 sub a4, a4, a5 +8000abfc: 83 27 81 00 lw a5, 8(sp) +8000ac00: 13 17 57 00 slli a4, a4, 5 +8000ac04: b3 87 d7 40 sub a5, a5, a3 +8000ac08: b3 07 f7 00 add a5, a4, a5 +8000ac0c: 93 06 05 00 mv a3, a0 +8000ac10: 63 5e f0 02 blez a5, 60 +8000ac14: 93 97 47 01 slli a5, a5, 20 +8000ac18: 33 84 87 00 add s0, a5, s0 +8000ac1c: 13 86 06 00 mv a2, a3 +8000ac20: 13 85 04 00 mv a0, s1 +8000ac24: 93 86 05 00 mv a3, a1 +8000ac28: 93 05 04 00 mv a1, s0 +8000ac2c: ef 50 50 3c jal 23492 +8000ac30: 83 20 c1 02 lw ra, 44(sp) +8000ac34: 03 24 81 02 lw s0, 40(sp) +8000ac38: 83 24 41 02 lw s1, 36(sp) +8000ac3c: 03 29 01 02 lw s2, 32(sp) +8000ac40: 83 29 c1 01 lw s3, 28(sp) +8000ac44: 13 01 01 03 addi sp, sp, 48 +8000ac48: 67 80 00 00 ret +8000ac4c: 13 97 47 01 slli a4, a5, 20 +8000ac50: b3 85 e5 40 sub a1, a1, a4 +8000ac54: 6f f0 9f fc j -56 + +8000ac58 _mprec_log10: +8000ac58: 13 01 01 ff addi sp, sp, -16 +8000ac5c: 23 20 21 01 sw s2, 0(sp) +8000ac60: 23 26 11 00 sw ra, 12(sp) +8000ac64: 23 24 81 00 sw s0, 8(sp) +8000ac68: 23 22 91 00 sw s1, 4(sp) +8000ac6c: 93 07 70 01 addi a5, zero, 23 +8000ac70: 13 09 05 00 mv s2, a0 +8000ac74: 63 da a7 04 bge a5, a0, 84 +8000ac78: 37 87 01 80 lui a4, 524312 +8000ac7c: 83 27 87 b7 lw a5, -1160(a4) +8000ac80: 83 25 c7 b7 lw a1, -1156(a4) +8000ac84: 37 87 01 80 lui a4, 524312 +8000ac88: 03 24 07 b8 lw s0, -1152(a4) +8000ac8c: 83 24 47 b8 lw s1, -1148(a4) +8000ac90: 13 85 07 00 mv a0, a5 +8000ac94: 13 06 04 00 mv a2, s0 +8000ac98: 93 86 04 00 mv a3, s1 +8000ac9c: ef 60 40 41 jal 25620 +8000aca0: 13 09 f9 ff addi s2, s2, -1 +8000aca4: 93 07 05 00 mv a5, a0 +8000aca8: e3 14 09 fe bnez s2, -24 +8000acac: 83 20 c1 00 lw ra, 12(sp) +8000acb0: 03 24 81 00 lw s0, 8(sp) +8000acb4: 83 24 41 00 lw s1, 4(sp) +8000acb8: 03 29 01 00 lw s2, 0(sp) +8000acbc: 13 85 07 00 mv a0, a5 +8000acc0: 13 01 01 01 addi sp, sp, 16 +8000acc4: 67 80 00 00 ret +8000acc8: b7 67 01 80 lui a5, 524310 +8000accc: 13 19 35 00 slli s2, a0, 3 +8000acd0: 93 87 07 a5 addi a5, a5, -1456 +8000acd4: 33 89 27 01 add s2, a5, s2 +8000acd8: 83 27 09 01 lw a5, 16(s2) +8000acdc: 83 20 c1 00 lw ra, 12(sp) +8000ace0: 03 24 81 00 lw s0, 8(sp) +8000ace4: 83 25 49 01 lw a1, 20(s2) +8000ace8: 83 24 41 00 lw s1, 4(sp) +8000acec: 03 29 01 00 lw s2, 0(sp) +8000acf0: 13 85 07 00 mv a0, a5 +8000acf4: 13 01 01 01 addi sp, sp, 16 +8000acf8: 67 80 00 00 ret + +8000acfc __copybits: +8000acfc: 83 26 06 01 lw a3, 16(a2) +8000ad00: 93 85 f5 ff addi a1, a1, -1 +8000ad04: 93 d5 55 40 srai a1, a1, 5 +8000ad08: 93 85 15 00 addi a1, a1, 1 +8000ad0c: 93 07 46 01 addi a5, a2, 20 +8000ad10: 93 96 26 00 slli a3, a3, 2 +8000ad14: 93 95 25 00 slli a1, a1, 2 +8000ad18: b3 86 d7 00 add a3, a5, a3 +8000ad1c: b3 05 b5 00 add a1, a0, a1 +8000ad20: 63 f8 d7 02 bgeu a5, a3, 48 +8000ad24: 13 07 05 00 mv a4, a0 +8000ad28: 03 a8 07 00 lw a6, 0(a5) +8000ad2c: 93 87 47 00 addi a5, a5, 4 +8000ad30: 13 07 47 00 addi a4, a4, 4 +8000ad34: 23 2e 07 ff sw a6, -4(a4) +8000ad38: e3 e8 d7 fe bltu a5, a3, -16 +8000ad3c: b3 87 c6 40 sub a5, a3, a2 +8000ad40: 93 87 b7 fe addi a5, a5, -21 +8000ad44: 93 f7 c7 ff andi a5, a5, -4 +8000ad48: 93 87 47 00 addi a5, a5, 4 +8000ad4c: 33 05 f5 00 add a0, a0, a5 +8000ad50: 63 78 b5 00 bgeu a0, a1, 16 +8000ad54: 13 05 45 00 addi a0, a0, 4 +8000ad58: 23 2e 05 fe sw zero, -4(a0) +8000ad5c: e3 6c b5 fe bltu a0, a1, -8 +8000ad60: 67 80 00 00 ret + +8000ad64 __any_on: +8000ad64: 03 27 05 01 lw a4, 16(a0) +8000ad68: 13 d6 55 40 srai a2, a1, 5 +8000ad6c: 93 06 45 01 addi a3, a0, 20 +8000ad70: 63 52 c7 02 bge a4, a2, 36 +8000ad74: 93 17 27 00 slli a5, a4, 2 +8000ad78: b3 87 f6 00 add a5, a3, a5 +8000ad7c: 63 f2 f6 04 bgeu a3, a5, 68 +8000ad80: 03 a7 c7 ff lw a4, -4(a5) +8000ad84: 93 87 c7 ff addi a5, a5, -4 +8000ad88: e3 0a 07 fe beqz a4, -12 +8000ad8c: 13 05 10 00 addi a0, zero, 1 +8000ad90: 67 80 00 00 ret +8000ad94: 93 17 26 00 slli a5, a2, 2 +8000ad98: b3 87 f6 00 add a5, a3, a5 +8000ad9c: e3 50 e6 fe bge a2, a4, -32 +8000ada0: 93 f5 f5 01 andi a1, a1, 31 +8000ada4: e3 8c 05 fc beqz a1, -40 +8000ada8: 03 a6 07 00 lw a2, 0(a5) +8000adac: 13 05 10 00 addi a0, zero, 1 +8000adb0: 33 57 b6 00 srl a4, a2, a1 +8000adb4: b3 15 b7 00 sll a1, a4, a1 +8000adb8: e3 02 b6 fc beq a2, a1, -60 +8000adbc: 67 80 00 00 ret +8000adc0: 13 05 00 00 mv a0, zero +8000adc4: 67 80 00 00 ret + +8000adc8 frexp: +8000adc8: 13 01 01 ff addi sp, sp, -16 +8000adcc: 23 22 91 00 sw s1, 4(sp) +8000add0: b7 04 00 80 lui s1, 524288 +8000add4: 23 24 81 00 sw s0, 8(sp) +8000add8: 23 26 11 00 sw ra, 12(sp) +8000addc: 93 c4 f4 ff not s1, s1 +8000ade0: 13 04 06 00 mv s0, a2 +8000ade4: 23 20 06 00 sw zero, 0(a2) +8000ade8: b3 f6 b4 00 and a3, s1, a1 +8000adec: 37 06 f0 7f lui a2, 524032 +8000adf0: 93 87 05 00 mv a5, a1 +8000adf4: 13 07 05 00 mv a4, a0 +8000adf8: 63 d0 c6 06 bge a3, a2, 96 +8000adfc: b3 e8 a6 00 or a7, a3, a0 +8000ae00: 63 8c 08 04 beqz a7, 88 +8000ae04: 33 f6 c5 00 and a2, a1, a2 +8000ae08: 13 88 05 00 mv a6, a1 +8000ae0c: 93 08 00 00 mv a7, zero +8000ae10: 63 12 06 02 bnez a2, 36 +8000ae14: b7 87 01 80 lui a5, 524312 +8000ae18: 83 a6 c7 b8 lw a3, -1140(a5) +8000ae1c: 03 a6 87 b8 lw a2, -1144(a5) +8000ae20: ef 60 00 29 jal 25232 +8000ae24: 13 07 05 00 mv a4, a0 +8000ae28: 13 88 05 00 mv a6, a1 +8000ae2c: b3 f6 b4 00 and a3, s1, a1 +8000ae30: 93 08 a0 fc addi a7, zero, -54 +8000ae34: 93 d6 46 41 srai a3, a3, 20 +8000ae38: b7 07 10 80 lui a5, 524544 +8000ae3c: 93 87 f7 ff addi a5, a5, -1 +8000ae40: 93 86 26 c0 addi a3, a3, -1022 +8000ae44: 33 78 f8 00 and a6, a6, a5 +8000ae48: b3 86 16 01 add a3, a3, a7 +8000ae4c: b7 07 e0 3f lui a5, 261632 +8000ae50: b3 67 f8 00 or a5, a6, a5 +8000ae54: 23 20 d4 00 sw a3, 0(s0) +8000ae58: 83 20 c1 00 lw ra, 12(sp) +8000ae5c: 03 24 81 00 lw s0, 8(sp) +8000ae60: 83 24 41 00 lw s1, 4(sp) +8000ae64: 13 05 07 00 mv a0, a4 +8000ae68: 93 85 07 00 mv a1, a5 +8000ae6c: 13 01 01 01 addi sp, sp, 16 +8000ae70: 67 80 00 00 ret + +8000ae74 _sbrk_r: +8000ae74: 13 01 01 ff addi sp, sp, -16 +8000ae78: 23 24 81 00 sw s0, 8(sp) +8000ae7c: 23 22 91 00 sw s1, 4(sp) +8000ae80: 13 04 05 00 mv s0, a0 +8000ae84: b7 84 01 80 lui s1, 524312 +8000ae88: 13 85 05 00 mv a0, a1 +8000ae8c: 23 26 11 00 sw ra, 12(sp) +8000ae90: 23 ae 04 c4 sw zero, -932(s1) +8000ae94: ef 70 1f e8 jal -33152 +8000ae98: 93 07 f0 ff addi a5, zero, -1 +8000ae9c: 63 0c f5 00 beq a0, a5, 24 +8000aea0: 83 20 c1 00 lw ra, 12(sp) +8000aea4: 03 24 81 00 lw s0, 8(sp) +8000aea8: 83 24 41 00 lw s1, 4(sp) +8000aeac: 13 01 01 01 addi sp, sp, 16 +8000aeb0: 67 80 00 00 ret +8000aeb4: 83 a7 c4 c5 lw a5, -932(s1) +8000aeb8: e3 84 07 fe beqz a5, -24 +8000aebc: 83 20 c1 00 lw ra, 12(sp) +8000aec0: 23 20 f4 00 sw a5, 0(s0) +8000aec4: 03 24 81 00 lw s0, 8(sp) +8000aec8: 83 24 41 00 lw s1, 4(sp) +8000aecc: 13 01 01 01 addi sp, sp, 16 +8000aed0: 67 80 00 00 ret + +8000aed4 _sprintf_r: +8000aed4: 13 01 01 f6 addi sp, sp, -160 +8000aed8: 93 0e c1 08 addi t4, sp, 140 +8000aedc: 23 2a f1 08 sw a5, 148(sp) +8000aee0: 37 03 00 80 lui t1, 524288 +8000aee4: b7 07 ff ff lui a5, 1048560 +8000aee8: 13 8e 05 00 mv t3, a1 +8000aeec: 13 43 f3 ff not t1, t1 +8000aef0: 23 26 d1 08 sw a3, 140(sp) +8000aef4: 93 87 87 20 addi a5, a5, 520 +8000aef8: 93 05 81 00 addi a1, sp, 8 +8000aefc: 93 86 0e 00 mv a3, t4 +8000af00: 23 2e 11 06 sw ra, 124(sp) +8000af04: 23 2a f1 00 sw a5, 20(sp) +8000af08: 23 28 e1 08 sw a4, 144(sp) +8000af0c: 23 2c 01 09 sw a6, 152(sp) +8000af10: 23 2e 11 09 sw a7, 156(sp) +8000af14: 23 24 c1 01 sw t3, 8(sp) +8000af18: 23 2c c1 01 sw t3, 24(sp) +8000af1c: 23 2e 61 00 sw t1, 28(sp) +8000af20: 23 28 61 00 sw t1, 16(sp) +8000af24: 23 22 d1 01 sw t4, 4(sp) +8000af28: ef 80 df 81 jal -30692 +8000af2c: 83 27 81 00 lw a5, 8(sp) +8000af30: 23 80 07 00 sb zero, 0(a5) +8000af34: 83 20 c1 07 lw ra, 124(sp) +8000af38: 13 01 01 0a addi sp, sp, 160 +8000af3c: 67 80 00 00 ret + +8000af40 sprintf: +8000af40: 13 0e 05 00 mv t3, a0 +8000af44: 37 85 01 80 lui a0, 524312 +8000af48: 13 01 01 f6 addi sp, sp, -160 +8000af4c: 03 25 c5 b9 lw a0, -1124(a0) +8000af50: 93 0e 81 08 addi t4, sp, 136 +8000af54: 23 2a f1 08 sw a5, 148(sp) +8000af58: 37 03 00 80 lui t1, 524288 +8000af5c: b7 07 ff ff lui a5, 1048560 +8000af60: 13 43 f3 ff not t1, t1 +8000af64: 23 24 c1 08 sw a2, 136(sp) +8000af68: 23 26 d1 08 sw a3, 140(sp) +8000af6c: 93 87 87 20 addi a5, a5, 520 +8000af70: 13 86 05 00 mv a2, a1 +8000af74: 93 86 0e 00 mv a3, t4 +8000af78: 93 05 81 00 addi a1, sp, 8 +8000af7c: 23 2e 11 06 sw ra, 124(sp) +8000af80: 23 2a f1 00 sw a5, 20(sp) +8000af84: 23 28 e1 08 sw a4, 144(sp) +8000af88: 23 2c 01 09 sw a6, 152(sp) +8000af8c: 23 2e 11 09 sw a7, 156(sp) +8000af90: 23 24 c1 01 sw t3, 8(sp) +8000af94: 23 2c c1 01 sw t3, 24(sp) +8000af98: 23 2e 61 00 sw t1, 28(sp) +8000af9c: 23 28 61 00 sw t1, 16(sp) +8000afa0: 23 22 d1 01 sw t4, 4(sp) +8000afa4: ef 80 0f fa jal -30816 +8000afa8: 83 27 81 00 lw a5, 8(sp) +8000afac: 23 80 07 00 sb zero, 0(a5) +8000afb0: 83 20 c1 07 lw ra, 124(sp) +8000afb4: 13 01 01 0a addi sp, sp, 160 +8000afb8: 67 80 00 00 ret + +8000afbc strcpy: +8000afbc: b3 67 b5 00 or a5, a0, a1 +8000afc0: 93 f7 37 00 andi a5, a5, 3 +8000afc4: 63 92 07 08 bnez a5, 132 +8000afc8: 03 a7 05 00 lw a4, 0(a1) +8000afcc: b7 86 7f 7f lui a3, 522232 +8000afd0: 93 86 f6 f7 addi a3, a3, -129 +8000afd4: b3 77 d7 00 and a5, a4, a3 +8000afd8: b3 87 d7 00 add a5, a5, a3 +8000afdc: b3 e7 e7 00 or a5, a5, a4 +8000afe0: b3 e7 d7 00 or a5, a5, a3 +8000afe4: 13 06 f0 ff addi a2, zero, -1 +8000afe8: 63 9e c7 06 bne a5, a2, 124 +8000afec: 13 06 05 00 mv a2, a0 +8000aff0: 13 08 f0 ff addi a6, zero, -1 +8000aff4: 23 20 e6 00 sw a4, 0(a2) +8000aff8: 03 a7 45 00 lw a4, 4(a1) +8000affc: 93 85 45 00 addi a1, a1, 4 +8000b000: 13 06 46 00 addi a2, a2, 4 +8000b004: b3 77 d7 00 and a5, a4, a3 +8000b008: b3 87 d7 00 add a5, a5, a3 +8000b00c: b3 e7 e7 00 or a5, a5, a4 +8000b010: b3 e7 d7 00 or a5, a5, a3 +8000b014: e3 80 07 ff beq a5, a6, -32 +8000b018: 83 c7 05 00 lbu a5, 0(a1) +8000b01c: 03 c7 15 00 lbu a4, 1(a1) +8000b020: 83 c6 25 00 lbu a3, 2(a1) +8000b024: 23 00 f6 00 sb a5, 0(a2) +8000b028: 63 8a 07 00 beqz a5, 20 +8000b02c: a3 00 e6 00 sb a4, 1(a2) +8000b030: 63 06 07 00 beqz a4, 12 +8000b034: 23 01 d6 00 sb a3, 2(a2) +8000b038: 63 94 06 00 bnez a3, 8 +8000b03c: 67 80 00 00 ret +8000b040: a3 01 06 00 sb zero, 3(a2) +8000b044: 67 80 00 00 ret +8000b048: 93 07 05 00 mv a5, a0 +8000b04c: 03 c7 05 00 lbu a4, 0(a1) +8000b050: 93 87 17 00 addi a5, a5, 1 +8000b054: 93 85 15 00 addi a1, a1, 1 +8000b058: a3 8f e7 fe sb a4, -1(a5) +8000b05c: e3 18 07 fe bnez a4, -16 +8000b060: 67 80 00 00 ret +8000b064: 13 06 05 00 mv a2, a0 +8000b068: 6f f0 1f fb j -80 + +8000b06c strlen: +8000b06c: 93 77 35 00 andi a5, a0, 3 +8000b070: 13 07 05 00 mv a4, a0 +8000b074: 63 9c 07 04 bnez a5, 88 +8000b078: b7 86 7f 7f lui a3, 522232 +8000b07c: 93 86 f6 f7 addi a3, a3, -129 +8000b080: 93 05 f0 ff addi a1, zero, -1 +8000b084: 03 26 07 00 lw a2, 0(a4) +8000b088: 13 07 47 00 addi a4, a4, 4 +8000b08c: b3 77 d6 00 and a5, a2, a3 +8000b090: b3 87 d7 00 add a5, a5, a3 +8000b094: b3 e7 c7 00 or a5, a5, a2 +8000b098: b3 e7 d7 00 or a5, a5, a3 +8000b09c: e3 84 b7 fe beq a5, a1, -24 +8000b0a0: 83 46 c7 ff lbu a3, -4(a4) +8000b0a4: 03 46 d7 ff lbu a2, -3(a4) +8000b0a8: 83 47 e7 ff lbu a5, -2(a4) +8000b0ac: 33 07 a7 40 sub a4, a4, a0 +8000b0b0: 63 80 06 04 beqz a3, 64 +8000b0b4: 63 0a 06 02 beqz a2, 52 +8000b0b8: 33 35 f0 00 snez a0, a5 +8000b0bc: 33 05 e5 00 add a0, a0, a4 +8000b0c0: 13 05 e5 ff addi a0, a0, -2 +8000b0c4: 67 80 00 00 ret +8000b0c8: e3 88 06 fa beqz a3, -80 +8000b0cc: 83 47 07 00 lbu a5, 0(a4) +8000b0d0: 13 07 17 00 addi a4, a4, 1 +8000b0d4: 93 76 37 00 andi a3, a4, 3 +8000b0d8: e3 98 07 fe bnez a5, -16 +8000b0dc: 33 07 a7 40 sub a4, a4, a0 +8000b0e0: 13 05 f7 ff addi a0, a4, -1 +8000b0e4: 67 80 00 00 ret +8000b0e8: 13 05 d7 ff addi a0, a4, -3 +8000b0ec: 67 80 00 00 ret +8000b0f0: 13 05 c7 ff addi a0, a4, -4 +8000b0f4: 67 80 00 00 ret + +8000b0f8 strncpy: +8000b0f8: b3 e7 a5 00 or a5, a1, a0 +8000b0fc: 93 f7 37 00 andi a5, a5, 3 +8000b100: 13 07 05 00 mv a4, a0 +8000b104: 63 98 07 06 bnez a5, 112 +8000b108: 93 07 30 00 addi a5, zero, 3 +8000b10c: 63 f4 c7 06 bgeu a5, a2, 104 +8000b110: 37 03 ff fe lui t1, 1044464 +8000b114: b7 88 80 80 lui a7, 526344 +8000b118: 13 03 f3 ef addi t1, t1, -257 +8000b11c: 93 88 08 08 addi a7, a7, 128 +8000b120: 13 0e 30 00 addi t3, zero, 3 +8000b124: 83 a6 05 00 lw a3, 0(a1) +8000b128: b3 87 66 00 add a5, a3, t1 +8000b12c: 13 c8 f6 ff not a6, a3 +8000b130: b3 f7 07 01 and a5, a5, a6 +8000b134: b3 f7 17 01 and a5, a5, a7 +8000b138: 63 9e 07 02 bnez a5, 60 +8000b13c: 23 20 d7 00 sw a3, 0(a4) +8000b140: 13 06 c6 ff addi a2, a2, -4 +8000b144: 13 07 47 00 addi a4, a4, 4 +8000b148: 93 85 45 00 addi a1, a1, 4 +8000b14c: e3 6c ce fc bltu t3, a2, -40 +8000b150: 93 85 15 00 addi a1, a1, 1 +8000b154: 93 07 17 00 addi a5, a4, 1 +8000b158: 63 04 06 02 beqz a2, 40 +8000b15c: 83 c6 f5 ff lbu a3, -1(a1) +8000b160: 13 08 f6 ff addi a6, a2, -1 +8000b164: a3 8f d7 fe sb a3, -1(a5) +8000b168: 63 8e 06 00 beqz a3, 28 +8000b16c: 13 87 07 00 mv a4, a5 +8000b170: 13 06 08 00 mv a2, a6 +8000b174: 93 85 15 00 addi a1, a1, 1 +8000b178: 93 07 17 00 addi a5, a4, 1 +8000b17c: e3 10 06 fe bnez a2, -32 +8000b180: 67 80 00 00 ret +8000b184: 33 06 c7 00 add a2, a4, a2 +8000b188: 63 0a 08 00 beqz a6, 20 +8000b18c: 93 87 17 00 addi a5, a5, 1 +8000b190: a3 8f 07 fe sb zero, -1(a5) +8000b194: e3 9c c7 fe bne a5, a2, -8 +8000b198: 67 80 00 00 ret +8000b19c: 67 80 00 00 ret + +8000b1a0 __ssprint_r: +8000b1a0: 83 27 86 00 lw a5, 8(a2) +8000b1a4: 13 01 01 fd addi sp, sp, -48 +8000b1a8: 23 2a 51 01 sw s5, 20(sp) +8000b1ac: 23 26 11 02 sw ra, 44(sp) +8000b1b0: 23 24 81 02 sw s0, 40(sp) +8000b1b4: 23 22 91 02 sw s1, 36(sp) +8000b1b8: 23 20 21 03 sw s2, 32(sp) +8000b1bc: 23 2e 31 01 sw s3, 28(sp) +8000b1c0: 23 2c 41 01 sw s4, 24(sp) +8000b1c4: 23 28 61 01 sw s6, 16(sp) +8000b1c8: 23 26 71 01 sw s7, 12(sp) +8000b1cc: 23 24 81 01 sw s8, 8(sp) +8000b1d0: 93 0a 06 00 mv s5, a2 +8000b1d4: 63 88 07 14 beqz a5, 336 +8000b1d8: 13 0b 05 00 mv s6, a0 +8000b1dc: 83 29 06 00 lw s3, 0(a2) +8000b1e0: 03 a5 05 00 lw a0, 0(a1) +8000b1e4: 83 a4 85 00 lw s1, 8(a1) +8000b1e8: 13 84 05 00 mv s0, a1 +8000b1ec: 6f 00 40 0d j 212 +8000b1f0: 83 57 c4 00 lhu a5, 12(s0) +8000b1f4: 13 f7 07 48 andi a4, a5, 1152 +8000b1f8: 63 0a 07 08 beqz a4, 148 +8000b1fc: 83 26 44 01 lw a3, 20(s0) +8000b200: 83 25 04 01 lw a1, 16(s0) +8000b204: 13 07 19 00 addi a4, s2, 1 +8000b208: 93 94 16 00 slli s1, a3, 1 +8000b20c: b3 86 d4 00 add a3, s1, a3 +8000b210: 93 d4 f6 01 srli s1, a3, 31 +8000b214: 33 0a b5 40 sub s4, a0, a1 +8000b218: b3 84 d4 00 add s1, s1, a3 +8000b21c: 93 d4 14 40 srai s1, s1, 1 +8000b220: 33 07 47 01 add a4, a4, s4 +8000b224: 13 86 04 00 mv a2, s1 +8000b228: 63 f6 e4 00 bgeu s1, a4, 12 +8000b22c: 93 04 07 00 mv s1, a4 +8000b230: 13 06 07 00 mv a2, a4 +8000b234: 93 f7 07 40 andi a5, a5, 1024 +8000b238: 63 86 07 0a beqz a5, 172 +8000b23c: 93 05 06 00 mv a1, a2 +8000b240: 13 05 0b 00 mv a0, s6 +8000b244: ef e0 cf 99 jal -7780 +8000b248: 13 0c 05 00 mv s8, a0 +8000b24c: 63 0a 05 0a beqz a0, 180 +8000b250: 83 25 04 01 lw a1, 16(s0) +8000b254: 13 06 0a 00 mv a2, s4 +8000b258: ef 10 40 3a jal 5028 +8000b25c: 83 57 c4 00 lhu a5, 12(s0) +8000b260: 93 f7 f7 b7 andi a5, a5, -1153 +8000b264: 93 e7 07 08 ori a5, a5, 128 +8000b268: 23 16 f4 00 sh a5, 12(s0) +8000b26c: 33 05 4c 01 add a0, s8, s4 +8000b270: 33 8a 44 41 sub s4, s1, s4 +8000b274: 23 2a 94 00 sw s1, 20(s0) +8000b278: 23 24 44 01 sw s4, 8(s0) +8000b27c: 23 28 84 01 sw s8, 16(s0) +8000b280: 23 20 a4 00 sw a0, 0(s0) +8000b284: 93 04 09 00 mv s1, s2 +8000b288: 13 0a 09 00 mv s4, s2 +8000b28c: 13 06 0a 00 mv a2, s4 +8000b290: 93 85 0b 00 mv a1, s7 +8000b294: ef 10 40 48 jal 5252 +8000b298: 03 27 84 00 lw a4, 8(s0) +8000b29c: 03 25 04 00 lw a0, 0(s0) +8000b2a0: 83 a7 8a 00 lw a5, 8(s5) +8000b2a4: b3 04 97 40 sub s1, a4, s1 +8000b2a8: 33 05 45 01 add a0, a0, s4 +8000b2ac: 23 24 94 00 sw s1, 8(s0) +8000b2b0: 23 20 a4 00 sw a0, 0(s0) +8000b2b4: 33 89 27 41 sub s2, a5, s2 +8000b2b8: 23 a4 2a 01 sw s2, 8(s5) +8000b2bc: 63 04 09 06 beqz s2, 104 +8000b2c0: 03 a9 49 00 lw s2, 4(s3) +8000b2c4: 83 ab 09 00 lw s7, 0(s3) +8000b2c8: 13 8a 04 00 mv s4, s1 +8000b2cc: 93 89 89 00 addi s3, s3, 8 +8000b2d0: e3 08 09 fe beqz s2, -16 +8000b2d4: e3 7e 99 f0 bgeu s2, s1, -228 +8000b2d8: 93 04 09 00 mv s1, s2 +8000b2dc: 13 0a 09 00 mv s4, s2 +8000b2e0: 6f f0 df fa j -84 +8000b2e4: 13 05 0b 00 mv a0, s6 +8000b2e8: ef 10 00 55 jal 5456 +8000b2ec: 13 0c 05 00 mv s8, a0 +8000b2f0: e3 1e 05 f6 bnez a0, -132 +8000b2f4: 83 25 04 01 lw a1, 16(s0) +8000b2f8: 13 05 0b 00 mv a0, s6 +8000b2fc: ef b0 0f a1 jal -19952 +8000b300: 93 07 c0 00 addi a5, zero, 12 +8000b304: 23 20 fb 00 sw a5, 0(s6) +8000b308: 83 57 c4 00 lhu a5, 12(s0) +8000b30c: 13 05 f0 ff addi a0, zero, -1 +8000b310: 93 e7 07 04 ori a5, a5, 64 +8000b314: 23 16 f4 00 sh a5, 12(s0) +8000b318: 23 a4 0a 00 sw zero, 8(s5) +8000b31c: 23 a2 0a 00 sw zero, 4(s5) +8000b320: 6f 00 c0 00 j 12 +8000b324: 23 a2 0a 00 sw zero, 4(s5) +8000b328: 13 05 00 00 mv a0, zero +8000b32c: 83 20 c1 02 lw ra, 44(sp) +8000b330: 03 24 81 02 lw s0, 40(sp) +8000b334: 83 24 41 02 lw s1, 36(sp) +8000b338: 03 29 01 02 lw s2, 32(sp) +8000b33c: 83 29 c1 01 lw s3, 28(sp) +8000b340: 03 2a 81 01 lw s4, 24(sp) +8000b344: 83 2a 41 01 lw s5, 20(sp) +8000b348: 03 2b 01 01 lw s6, 16(sp) +8000b34c: 83 2b c1 00 lw s7, 12(sp) +8000b350: 03 2c 81 00 lw s8, 8(sp) +8000b354: 13 01 01 03 addi sp, sp, 48 +8000b358: 67 80 00 00 ret + +8000b35c _svfiprintf_r: +8000b35c: 83 d7 c5 00 lhu a5, 12(a1) +8000b360: 13 01 01 ed addi sp, sp, -304 +8000b364: 23 2c 41 11 sw s4, 280(sp) +8000b368: 23 28 61 11 sw s6, 272(sp) +8000b36c: 23 20 a1 11 sw s10, 256(sp) +8000b370: 23 26 11 12 sw ra, 300(sp) +8000b374: 23 24 81 12 sw s0, 296(sp) +8000b378: 23 22 91 12 sw s1, 292(sp) +8000b37c: 23 20 21 13 sw s2, 288(sp) +8000b380: 23 2e 31 11 sw s3, 284(sp) +8000b384: 23 2a 51 11 sw s5, 276(sp) +8000b388: 23 26 71 11 sw s7, 268(sp) +8000b38c: 23 24 81 11 sw s8, 264(sp) +8000b390: 23 22 91 11 sw s9, 260(sp) +8000b394: 23 2e b1 0f sw s11, 252(sp) +8000b398: 93 f7 07 08 andi a5, a5, 128 +8000b39c: 23 26 d1 00 sw a3, 12(sp) +8000b3a0: 13 8a 05 00 mv s4, a1 +8000b3a4: 13 0b 05 00 mv s6, a0 +8000b3a8: 13 0d 06 00 mv s10, a2 +8000b3ac: 63 86 07 00 beqz a5, 12 +8000b3b0: 83 a7 05 01 lw a5, 16(a1) +8000b3b4: e3 86 07 56 beqz a5, 3436 +8000b3b8: b7 67 01 80 lui a5, 524310 +8000b3bc: 93 0a c1 04 addi s5, sp, 76 +8000b3c0: 93 87 87 b7 addi a5, a5, -1160 +8000b3c4: b7 6b 01 80 lui s7, 524310 +8000b3c8: b7 64 01 80 lui s1, 524310 +8000b3cc: 23 20 51 05 sw s5, 64(sp) +8000b3d0: 23 24 01 04 sw zero, 72(sp) +8000b3d4: 23 22 01 04 sw zero, 68(sp) +8000b3d8: 13 87 0a 00 mv a4, s5 +8000b3dc: 23 28 01 00 sw zero, 16(sp) +8000b3e0: 23 22 01 02 sw zero, 36(sp) +8000b3e4: 23 24 01 02 sw zero, 40(sp) +8000b3e8: 23 26 01 02 sw zero, 44(sp) +8000b3ec: 23 24 01 00 sw zero, 8(sp) +8000b3f0: 23 2a f1 00 sw a5, 20(sp) +8000b3f4: 93 8b 4b ce addi s7, s7, -796 +8000b3f8: 93 84 44 cf addi s1, s1, -780 +8000b3fc: 83 47 0d 00 lbu a5, 0(s10) +8000b400: 63 80 07 20 beqz a5, 512 +8000b404: 13 04 0d 00 mv s0, s10 +8000b408: 93 06 50 02 addi a3, zero, 37 +8000b40c: 63 86 d7 38 beq a5, a3, 908 +8000b410: 83 47 14 00 lbu a5, 1(s0) +8000b414: 13 04 14 00 addi s0, s0, 1 +8000b418: e3 9a 07 fe bnez a5, -12 +8000b41c: 33 09 a4 41 sub s2, s0, s10 +8000b420: 63 00 a4 1f beq s0, s10, 480 +8000b424: 83 26 81 04 lw a3, 72(sp) +8000b428: 83 27 41 04 lw a5, 68(sp) +8000b42c: 23 20 a7 01 sw s10, 0(a4) +8000b430: b3 86 26 01 add a3, a3, s2 +8000b434: 93 87 17 00 addi a5, a5, 1 +8000b438: 23 22 27 01 sw s2, 4(a4) +8000b43c: 23 24 d1 04 sw a3, 72(sp) +8000b440: 23 22 f1 04 sw a5, 68(sp) +8000b444: 93 06 70 00 addi a3, zero, 7 +8000b448: 13 07 87 00 addi a4, a4, 8 +8000b44c: 63 ce f6 34 blt a3, a5, 860 +8000b450: 83 26 81 00 lw a3, 8(sp) +8000b454: 83 47 04 00 lbu a5, 0(s0) +8000b458: b3 86 26 01 add a3, a3, s2 +8000b45c: 23 24 d1 00 sw a3, 8(sp) +8000b460: 63 80 07 1a beqz a5, 416 +8000b464: 83 46 14 00 lbu a3, 1(s0) +8000b468: 13 0d 14 00 addi s10, s0, 1 +8000b46c: a3 0d 01 02 sb zero, 59(sp) +8000b470: 93 0c f0 ff addi s9, zero, -1 +8000b474: 13 04 00 00 mv s0, zero +8000b478: 93 0d 00 00 mv s11, zero +8000b47c: 13 09 a0 05 addi s2, zero, 90 +8000b480: 13 0c 90 00 addi s8, zero, 9 +8000b484: 93 09 a0 02 addi s3, zero, 42 +8000b488: 13 0d 1d 00 addi s10, s10, 1 +8000b48c: 93 87 06 fe addi a5, a3, -32 +8000b490: 63 64 f9 04 bltu s2, a5, 72 +8000b494: 03 26 41 01 lw a2, 20(sp) +8000b498: 93 97 27 00 slli a5, a5, 2 +8000b49c: b3 87 c7 00 add a5, a5, a2 +8000b4a0: 83 a7 07 00 lw a5, 0(a5) +8000b4a4: 67 80 07 00 jr a5 +8000b4a8: 13 04 00 00 mv s0, zero +8000b4ac: 93 87 06 fd addi a5, a3, -48 +8000b4b0: 83 46 0d 00 lbu a3, 0(s10) +8000b4b4: 93 15 24 00 slli a1, s0, 2 +8000b4b8: 33 84 85 00 add s0, a1, s0 +8000b4bc: 13 14 14 00 slli s0, s0, 1 +8000b4c0: 33 84 87 00 add s0, a5, s0 +8000b4c4: 93 87 06 fd addi a5, a3, -48 +8000b4c8: 13 0d 1d 00 addi s10, s10, 1 +8000b4cc: e3 72 fc fe bgeu s8, a5, -28 +8000b4d0: 93 87 06 fe addi a5, a3, -32 +8000b4d4: e3 70 f9 fc bgeu s2, a5, -64 +8000b4d8: 63 84 06 12 beqz a3, 296 +8000b4dc: 23 06 d1 08 sb a3, 140(sp) +8000b4e0: a3 0d 01 02 sb zero, 59(sp) +8000b4e4: 13 09 10 00 addi s2, zero, 1 +8000b4e8: 13 0c 10 00 addi s8, zero, 1 +8000b4ec: 93 09 c1 08 addi s3, sp, 140 +8000b4f0: 93 0c 00 00 mv s9, zero +8000b4f4: 13 ff 2d 00 andi t5, s11, 2 +8000b4f8: 63 04 0f 00 beqz t5, 8 +8000b4fc: 13 09 29 00 addi s2, s2, 2 +8000b500: 13 fe 4d 08 andi t3, s11, 132 +8000b504: 83 27 81 04 lw a5, 72(sp) +8000b508: 03 26 41 04 lw a2, 68(sp) +8000b50c: 63 16 0e 00 bnez t3, 12 +8000b510: b3 06 24 41 sub a3, s0, s2 +8000b514: e3 4a d0 02 bgtz a3, 2100 +8000b518: 83 46 b1 03 lbu a3, 59(sp) +8000b51c: 13 05 16 00 addi a0, a2, 1 +8000b520: 93 05 87 00 addi a1, a4, 8 +8000b524: 63 80 06 04 beqz a3, 64 +8000b528: 93 06 b1 03 addi a3, sp, 59 +8000b52c: 93 87 17 00 addi a5, a5, 1 +8000b530: 23 20 d7 00 sw a3, 0(a4) +8000b534: 93 06 10 00 addi a3, zero, 1 +8000b538: 23 22 d7 00 sw a3, 4(a4) +8000b53c: 23 24 f1 04 sw a5, 72(sp) +8000b540: 23 22 a1 04 sw a0, 68(sp) +8000b544: 93 06 70 00 addi a3, zero, 7 +8000b548: e3 ce a6 0c blt a3, a0, 2268 +8000b54c: 93 0f 26 00 addi t6, a2, 2 +8000b550: 93 06 07 01 addi a3, a4, 16 +8000b554: 13 06 05 00 mv a2, a0 +8000b558: 13 87 05 00 mv a4, a1 +8000b55c: 13 85 0f 00 mv a0, t6 +8000b560: 93 85 06 00 mv a1, a3 +8000b564: 63 0c 0f 02 beqz t5, 56 +8000b568: 93 06 c1 03 addi a3, sp, 60 +8000b56c: 23 20 d7 00 sw a3, 0(a4) +8000b570: 93 87 27 00 addi a5, a5, 2 +8000b574: 93 06 20 00 addi a3, zero, 2 +8000b578: 23 22 d7 00 sw a3, 4(a4) +8000b57c: 23 24 f1 04 sw a5, 72(sp) +8000b580: 23 22 a1 04 sw a0, 68(sp) +8000b584: 13 07 70 00 addi a4, zero, 7 +8000b588: e3 4c a7 0c blt a4, a0, 2264 +8000b58c: 13 06 05 00 mv a2, a0 +8000b590: 13 87 05 00 mv a4, a1 +8000b594: 13 05 15 00 addi a0, a0, 1 +8000b598: 93 85 85 00 addi a1, a1, 8 +8000b59c: 93 06 00 08 addi a3, zero, 128 +8000b5a0: 63 02 de 60 beq t3, a3, 1540 +8000b5a4: b3 8c 8c 41 sub s9, s9, s8 +8000b5a8: 63 46 90 6b bgtz s9, 1708 +8000b5ac: b3 07 fc 00 add a5, s8, a5 +8000b5b0: 23 20 37 01 sw s3, 0(a4) +8000b5b4: 23 22 87 01 sw s8, 4(a4) +8000b5b8: 23 24 f1 04 sw a5, 72(sp) +8000b5bc: 23 22 a1 04 sw a0, 68(sp) +8000b5c0: 13 07 70 00 addi a4, zero, 7 +8000b5c4: 63 42 a7 74 blt a4, a0, 1860 +8000b5c8: 93 f8 4d 00 andi a7, s11, 4 +8000b5cc: 63 86 08 00 beqz a7, 12 +8000b5d0: 33 0c 24 41 sub s8, s0, s2 +8000b5d4: 63 48 80 1f bgtz s8, 496 +8000b5d8: 63 54 24 01 bge s0, s2, 8 +8000b5dc: 13 04 09 00 mv s0, s2 +8000b5e0: 03 27 81 00 lw a4, 8(sp) +8000b5e4: 33 07 87 00 add a4, a4, s0 +8000b5e8: 23 24 e1 00 sw a4, 8(sp) +8000b5ec: 63 9e 07 72 bnez a5, 1852 +8000b5f0: 83 47 0d 00 lbu a5, 0(s10) +8000b5f4: 23 22 01 04 sw zero, 68(sp) +8000b5f8: 13 87 0a 00 mv a4, s5 +8000b5fc: e3 94 07 e0 bnez a5, -504 +8000b600: 83 27 81 04 lw a5, 72(sp) +8000b604: e3 92 07 4c bnez a5, 3268 +8000b608: 83 57 ca 00 lhu a5, 12(s4) +8000b60c: 93 f7 07 04 andi a5, a5, 64 +8000b610: e3 98 07 4e bnez a5, 3312 +8000b614: 83 20 c1 12 lw ra, 300(sp) +8000b618: 03 24 81 12 lw s0, 296(sp) +8000b61c: 03 25 81 00 lw a0, 8(sp) +8000b620: 83 24 41 12 lw s1, 292(sp) +8000b624: 03 29 01 12 lw s2, 288(sp) +8000b628: 83 29 c1 11 lw s3, 284(sp) +8000b62c: 03 2a 81 11 lw s4, 280(sp) +8000b630: 83 2a 41 11 lw s5, 276(sp) +8000b634: 03 2b 01 11 lw s6, 272(sp) +8000b638: 83 2b c1 10 lw s7, 268(sp) +8000b63c: 03 2c 81 10 lw s8, 264(sp) +8000b640: 83 2c 41 10 lw s9, 260(sp) +8000b644: 03 2d 01 10 lw s10, 256(sp) +8000b648: 83 2d c1 0f lw s11, 252(sp) +8000b64c: 13 01 01 13 addi sp, sp, 304 +8000b650: 67 80 00 00 ret +8000b654: 13 05 0b 00 mv a0, s6 +8000b658: 23 2c e1 00 sw a4, 24(sp) +8000b65c: ef d0 df d6 jal -8852 +8000b660: 83 27 45 00 lw a5, 4(a0) +8000b664: 13 85 07 00 mv a0, a5 +8000b668: 23 26 f1 02 sw a5, 44(sp) +8000b66c: ef f0 1f a0 jal -1536 +8000b670: 93 07 05 00 mv a5, a0 +8000b674: 13 05 0b 00 mv a0, s6 +8000b678: 23 24 f1 02 sw a5, 40(sp) +8000b67c: ef d0 df d4 jal -8884 +8000b680: 03 27 85 00 lw a4, 8(a0) +8000b684: 83 27 81 02 lw a5, 40(sp) +8000b688: 23 22 e1 02 sw a4, 36(sp) +8000b68c: 03 27 81 01 lw a4, 24(sp) +8000b690: e3 98 07 16 bnez a5, 2416 +8000b694: 83 46 0d 00 lbu a3, 0(s10) +8000b698: 6f f0 1f df j -528 +8000b69c: 83 46 0d 00 lbu a3, 0(s10) +8000b6a0: 93 ed 0d 02 ori s11, s11, 32 +8000b6a4: 6f f0 5f de j -540 +8000b6a8: 93 ed 0d 01 ori s11, s11, 16 +8000b6ac: 93 f7 0d 02 andi a5, s11, 32 +8000b6b0: 63 82 07 1e beqz a5, 484 +8000b6b4: 83 27 c1 00 lw a5, 12(sp) +8000b6b8: 93 89 77 00 addi s3, a5, 7 +8000b6bc: 93 f9 89 ff andi s3, s3, -8 +8000b6c0: 83 a6 49 00 lw a3, 4(s3) +8000b6c4: 03 ac 09 00 lw s8, 0(s3) +8000b6c8: 93 87 89 00 addi a5, s3, 8 +8000b6cc: 23 26 f1 00 sw a5, 12(sp) +8000b6d0: 13 8e 06 00 mv t3, a3 +8000b6d4: 63 c8 06 1e bltz a3, 496 +8000b6d8: 93 06 f0 ff addi a3, zero, -1 +8000b6dc: 13 89 0d 00 mv s2, s11 +8000b6e0: 63 88 dc 00 beq s9, a3, 16 +8000b6e4: b3 66 cc 01 or a3, s8, t3 +8000b6e8: 13 f9 fd f7 andi s2, s11, -129 +8000b6ec: 63 84 06 7a beqz a3, 1960 +8000b6f0: e3 1c 0e 00 bnez t3, 2072 +8000b6f4: 93 06 90 00 addi a3, zero, 9 +8000b6f8: e3 e8 86 01 bltu a3, s8, 2064 +8000b6fc: 93 07 0c 03 addi a5, s8, 48 +8000b700: a3 07 f1 0e sb a5, 239(sp) +8000b704: 93 0d 09 00 mv s11, s2 +8000b708: 13 0c 10 00 addi s8, zero, 1 +8000b70c: 93 09 f1 0e addi s3, sp, 239 +8000b710: 6f 00 c0 06 j 108 +8000b714: 93 ed 0d 01 ori s11, s11, 16 +8000b718: 93 f7 0d 02 andi a5, s11, 32 +8000b71c: 63 86 07 14 beqz a5, 332 +8000b720: 83 27 c1 00 lw a5, 12(sp) +8000b724: 93 89 77 00 addi s3, a5, 7 +8000b728: 93 f9 89 ff andi s3, s3, -8 +8000b72c: 03 ac 09 00 lw s8, 0(s3) +8000b730: 03 ae 49 00 lw t3, 4(s3) +8000b734: 93 87 89 00 addi a5, s3, 8 +8000b738: 23 26 f1 00 sw a5, 12(sp) +8000b73c: 13 f9 fd bf andi s2, s11, -1025 +8000b740: 93 06 00 00 mv a3, zero +8000b744: a3 0d 01 02 sb zero, 59(sp) +8000b748: 13 06 f0 ff addi a2, zero, -1 +8000b74c: 63 80 cc 1a beq s9, a2, 416 +8000b750: 33 66 cc 01 or a2, s8, t3 +8000b754: 93 7d f9 f7 andi s11, s2, -129 +8000b758: 63 14 06 5e bnez a2, 1512 +8000b75c: 63 98 0c 3e bnez s9, 1008 +8000b760: 63 9e 06 72 bnez a3, 1852 +8000b764: 13 7c 19 00 andi s8, s2, 1 +8000b768: 93 09 01 0f addi s3, sp, 240 +8000b76c: 63 08 0c 00 beqz s8, 16 +8000b770: 93 07 00 03 addi a5, zero, 48 +8000b774: a3 07 f1 0e sb a5, 239(sp) +8000b778: 93 09 f1 0e addi s3, sp, 239 +8000b77c: 13 89 0c 00 mv s2, s9 +8000b780: 63 d4 8c 01 bge s9, s8, 8 +8000b784: 13 09 0c 00 mv s2, s8 +8000b788: 83 47 b1 03 lbu a5, 59(sp) +8000b78c: b3 37 f0 00 snez a5, a5 +8000b790: 33 09 f9 00 add s2, s2, a5 +8000b794: 6f f0 1f d6 j -672 +8000b798: 33 09 a4 41 sub s2, s0, s10 +8000b79c: e3 14 a4 c9 bne s0, s10, -888 +8000b7a0: 83 47 04 00 lbu a5, 0(s0) +8000b7a4: 6f f0 df cb j -836 +8000b7a8: 13 06 01 04 addi a2, sp, 64 +8000b7ac: 93 05 0a 00 mv a1, s4 +8000b7b0: 13 05 0b 00 mv a0, s6 +8000b7b4: ef f0 df 9e jal -1556 +8000b7b8: e3 18 05 e4 bnez a0, -432 +8000b7bc: 13 87 0a 00 mv a4, s5 +8000b7c0: 6f f0 1f c9 j -880 +8000b7c4: 93 06 00 01 addi a3, zero, 16 +8000b7c8: 03 27 41 04 lw a4, 68(sp) +8000b7cc: 63 d0 86 07 bge a3, s8, 96 +8000b7d0: 93 0c 00 01 addi s9, zero, 16 +8000b7d4: 93 09 70 00 addi s3, zero, 7 +8000b7d8: 6f 00 c0 00 j 12 +8000b7dc: 13 0c 0c ff addi s8, s8, -16 +8000b7e0: 63 d6 8c 05 bge s9, s8, 76 +8000b7e4: 93 87 07 01 addi a5, a5, 16 +8000b7e8: 13 07 17 00 addi a4, a4, 1 +8000b7ec: 23 a0 75 01 sw s7, 0(a1) +8000b7f0: 23 a2 95 01 sw s9, 4(a1) +8000b7f4: 23 24 f1 04 sw a5, 72(sp) +8000b7f8: 23 22 e1 04 sw a4, 68(sp) +8000b7fc: 93 85 85 00 addi a1, a1, 8 +8000b800: e3 de e9 fc bge s3, a4, -36 +8000b804: 13 06 01 04 addi a2, sp, 64 +8000b808: 93 05 0a 00 mv a1, s4 +8000b80c: 13 05 0b 00 mv a0, s6 +8000b810: ef f0 1f 99 jal -1648 +8000b814: e3 1a 05 de bnez a0, -524 +8000b818: 13 0c 0c ff addi s8, s8, -16 +8000b81c: 83 27 81 04 lw a5, 72(sp) +8000b820: 03 27 41 04 lw a4, 68(sp) +8000b824: 93 85 0a 00 mv a1, s5 +8000b828: e3 ce 8c fb blt s9, s8, -68 +8000b82c: b3 87 87 01 add a5, a5, s8 +8000b830: 13 07 17 00 addi a4, a4, 1 +8000b834: 23 a0 75 01 sw s7, 0(a1) +8000b838: 23 a2 85 01 sw s8, 4(a1) +8000b83c: 23 24 f1 04 sw a5, 72(sp) +8000b840: 23 22 e1 04 sw a4, 68(sp) +8000b844: 93 06 70 00 addi a3, zero, 7 +8000b848: e3 d8 e6 d8 bge a3, a4, -624 +8000b84c: 13 06 01 04 addi a2, sp, 64 +8000b850: 93 05 0a 00 mv a1, s4 +8000b854: 13 05 0b 00 mv a0, s6 +8000b858: ef f0 9f 94 jal -1720 +8000b85c: e3 16 05 da bnez a0, -596 +8000b860: 83 27 81 04 lw a5, 72(sp) +8000b864: 6f f0 5f d7 j -652 +8000b868: 03 26 c1 00 lw a2, 12(sp) +8000b86c: 93 f7 0d 01 andi a5, s11, 16 +8000b870: 93 06 46 00 addi a3, a2, 4 +8000b874: 63 92 07 7e bnez a5, 2020 +8000b878: 93 f7 0d 04 andi a5, s11, 64 +8000b87c: e3 8c 07 18 beqz a5, 2456 +8000b880: 83 27 c1 00 lw a5, 12(sp) +8000b884: 13 0e 00 00 mv t3, zero +8000b888: 23 26 d1 00 sw a3, 12(sp) +8000b88c: 03 dc 07 00 lhu s8, 0(a5) +8000b890: 6f f0 df ea j -340 +8000b894: 03 26 c1 00 lw a2, 12(sp) +8000b898: 93 f7 0d 01 andi a5, s11, 16 +8000b89c: 93 06 46 00 addi a3, a2, 4 +8000b8a0: 63 98 07 78 bnez a5, 1936 +8000b8a4: 93 f7 0d 04 andi a5, s11, 64 +8000b8a8: e3 86 07 14 beqz a5, 2380 +8000b8ac: 83 27 c1 00 lw a5, 12(sp) +8000b8b0: 23 26 d1 00 sw a3, 12(sp) +8000b8b4: 03 9c 07 00 lh s8, 0(a5) +8000b8b8: 13 5e fc 41 srai t3, s8, 31 +8000b8bc: 93 06 0e 00 mv a3, t3 +8000b8c0: e3 dc 06 e0 bgez a3, -488 +8000b8c4: b3 36 80 01 snez a3, s8 +8000b8c8: 33 0e c0 41 neg t3, t3 +8000b8cc: 33 0e de 40 sub t3, t3, a3 +8000b8d0: 93 06 d0 02 addi a3, zero, 45 +8000b8d4: a3 0d d1 02 sb a3, 59(sp) +8000b8d8: 13 06 f0 ff addi a2, zero, -1 +8000b8dc: 33 0c 80 41 neg s8, s8 +8000b8e0: 13 89 0d 00 mv s2, s11 +8000b8e4: 93 06 10 00 addi a3, zero, 1 +8000b8e8: e3 94 cc e6 bne s9, a2, -408 +8000b8ec: 13 06 10 00 addi a2, zero, 1 +8000b8f0: e3 80 c6 e0 beq a3, a2, -512 +8000b8f4: 13 06 20 00 addi a2, zero, 2 +8000b8f8: 63 84 c6 26 beq a3, a2, 616 +8000b8fc: 93 09 01 0f addi s3, sp, 240 +8000b900: 13 16 de 01 slli a2, t3, 29 +8000b904: 93 76 7c 00 andi a3, s8, 7 +8000b908: 93 57 3c 00 srli a5, s8, 3 +8000b90c: 93 86 06 03 addi a3, a3, 48 +8000b910: 33 6c f6 00 or s8, a2, a5 +8000b914: 13 5e 3e 00 srli t3, t3, 3 +8000b918: a3 8f d9 fe sb a3, -1(s3) +8000b91c: 33 66 cc 01 or a2, s8, t3 +8000b920: 93 85 09 00 mv a1, s3 +8000b924: 93 89 f9 ff addi s3, s3, -1 +8000b928: e3 1c 06 fc bnez a2, -40 +8000b92c: 93 77 19 00 andi a5, s2, 1 +8000b930: 63 82 07 26 beqz a5, 612 +8000b934: 93 07 00 03 addi a5, zero, 48 +8000b938: 63 8e f6 24 beq a3, a5, 604 +8000b93c: 93 85 e5 ff addi a1, a1, -2 +8000b940: a3 8f f9 fe sb a5, -1(s3) +8000b944: 93 07 01 0f addi a5, sp, 240 +8000b948: 33 8c b7 40 sub s8, a5, a1 +8000b94c: 93 0d 09 00 mv s11, s2 +8000b950: 93 89 05 00 mv s3, a1 +8000b954: 6f f0 9f e2 j -472 +8000b958: 83 27 c1 00 lw a5, 12(sp) +8000b95c: a3 0d 01 02 sb zero, 59(sp) +8000b960: 83 a9 07 00 lw s3, 0(a5) +8000b964: 93 86 47 00 addi a3, a5, 4 +8000b968: e3 86 09 04 beqz s3, 2124 +8000b96c: 93 07 f0 ff addi a5, zero, -1 +8000b970: 63 88 fc 78 beq s9, a5, 1936 +8000b974: 13 86 0c 00 mv a2, s9 +8000b978: 93 05 00 00 mv a1, zero +8000b97c: 13 85 09 00 mv a0, s3 +8000b980: 23 2c d1 00 sw a3, 24(sp) +8000b984: 23 26 e1 00 sw a4, 12(sp) +8000b988: ef e0 0f a1 jal -7664 +8000b98c: 03 27 c1 00 lw a4, 12(sp) +8000b990: 83 26 81 01 lw a3, 24(sp) +8000b994: e3 04 05 14 beqz a0, 2376 +8000b998: 33 0c 35 41 sub s8, a0, s3 +8000b99c: 23 26 d1 00 sw a3, 12(sp) +8000b9a0: 93 0c 00 00 mv s9, zero +8000b9a4: 6f f0 9f dd j -552 +8000b9a8: 83 26 c1 00 lw a3, 12(sp) +8000b9ac: a3 0d 01 02 sb zero, 59(sp) +8000b9b0: 13 09 10 00 addi s2, zero, 1 +8000b9b4: 83 a7 06 00 lw a5, 0(a3) +8000b9b8: 93 86 46 00 addi a3, a3, 4 +8000b9bc: 23 26 d1 00 sw a3, 12(sp) +8000b9c0: 23 06 f1 08 sb a5, 140(sp) +8000b9c4: 13 0c 10 00 addi s8, zero, 1 +8000b9c8: 93 09 c1 08 addi s3, sp, 140 +8000b9cc: 6f f0 5f b2 j -1244 +8000b9d0: 83 27 c1 00 lw a5, 12(sp) +8000b9d4: 13 e9 2d 00 ori s2, s11, 2 +8000b9d8: b7 86 ff ff lui a3, 1048568 +8000b9dc: 03 ac 07 00 lw s8, 0(a5) +8000b9e0: b7 5d 01 80 lui s11, 524309 +8000b9e4: 93 87 47 00 addi a5, a5, 4 +8000b9e8: 93 c6 06 83 xori a3, a3, -2000 +8000b9ec: 23 26 f1 00 sw a5, 12(sp) +8000b9f0: 93 87 8d 5a addi a5, s11, 1448 +8000b9f4: 23 1e d1 02 sh a3, 60(sp) +8000b9f8: 13 0e 00 00 mv t3, zero +8000b9fc: 23 28 f1 00 sw a5, 16(sp) +8000ba00: 93 06 20 00 addi a3, zero, 2 +8000ba04: 6f f0 1f d4 j -704 +8000ba08: 03 26 c1 00 lw a2, 12(sp) +8000ba0c: 93 f7 0d 02 andi a5, s11, 32 +8000ba10: 83 26 06 00 lw a3, 0(a2) +8000ba14: 13 06 46 00 addi a2, a2, 4 +8000ba18: 23 26 c1 00 sw a2, 12(sp) +8000ba1c: 63 90 07 60 bnez a5, 1536 +8000ba20: 93 f7 0d 01 andi a5, s11, 16 +8000ba24: 63 92 07 78 bnez a5, 1924 +8000ba28: 93 f7 0d 04 andi a5, s11, 64 +8000ba2c: e3 98 07 08 bnez a5, 2192 +8000ba30: 93 f8 0d 20 andi a7, s11, 512 +8000ba34: 63 8a 08 76 beqz a7, 1908 +8000ba38: 83 27 81 00 lw a5, 8(sp) +8000ba3c: 23 80 f6 00 sb a5, 0(a3) +8000ba40: 6f f0 df 9b j -1604 +8000ba44: 83 46 0d 00 lbu a3, 0(s10) +8000ba48: 93 ed 0d 08 ori s11, s11, 128 +8000ba4c: 6f f0 df a3 j -1476 +8000ba50: 83 46 0d 00 lbu a3, 0(s10) +8000ba54: 93 05 1d 00 addi a1, s10, 1 +8000ba58: e3 8a 36 0b beq a3, s3, 2228 +8000ba5c: 93 87 06 fd addi a5, a3, -48 +8000ba60: 13 8d 05 00 mv s10, a1 +8000ba64: 93 0c 00 00 mv s9, zero +8000ba68: e3 62 fc a2 bltu s8, a5, -1500 +8000ba6c: 83 46 0d 00 lbu a3, 0(s10) +8000ba70: 93 95 2c 00 slli a1, s9, 2 +8000ba74: 33 83 95 01 add t1, a1, s9 +8000ba78: 13 13 13 00 slli t1, t1, 1 +8000ba7c: b3 0c f3 00 add s9, t1, a5 +8000ba80: 93 87 06 fd addi a5, a3, -48 +8000ba84: 13 0d 1d 00 addi s10, s10, 1 +8000ba88: e3 72 fc fe bgeu s8, a5, -28 +8000ba8c: 6f f0 1f a0 j -1536 +8000ba90: 83 46 0d 00 lbu a3, 0(s10) +8000ba94: 93 ed 4d 00 ori s11, s11, 4 +8000ba98: 6f f0 1f 9f j -1552 +8000ba9c: 93 07 b0 02 addi a5, zero, 43 +8000baa0: 83 46 0d 00 lbu a3, 0(s10) +8000baa4: a3 0d f1 02 sb a5, 59(sp) +8000baa8: 6f f0 1f 9e j -1568 +8000baac: 83 27 c1 00 lw a5, 12(sp) +8000bab0: 83 46 0d 00 lbu a3, 0(s10) +8000bab4: 03 a4 07 00 lw s0, 0(a5) +8000bab8: 93 87 47 00 addi a5, a5, 4 +8000babc: 23 26 f1 00 sw a5, 12(sp) +8000bac0: e3 54 04 9c bgez s0, -1592 +8000bac4: 33 04 80 40 neg s0, s0 +8000bac8: 93 ed 4d 00 ori s11, s11, 4 +8000bacc: 6f f0 df 9b j -1604 +8000bad0: 83 46 0d 00 lbu a3, 0(s10) +8000bad4: 93 ed 1d 00 ori s11, s11, 1 +8000bad8: 6f f0 1f 9b j -1616 +8000badc: 83 47 b1 03 lbu a5, 59(sp) +8000bae0: 83 46 0d 00 lbu a3, 0(s10) +8000bae4: e3 92 07 9a bnez a5, -1628 +8000bae8: 93 07 00 02 addi a5, zero, 32 +8000baec: a3 0d f1 02 sb a5, 59(sp) +8000baf0: 6f f0 9f 99 j -1640 +8000baf4: 83 46 0d 00 lbu a3, 0(s10) +8000baf8: 93 07 c0 06 addi a5, zero, 108 +8000bafc: 63 88 f6 66 beq a3, a5, 1648 +8000bb00: 93 ed 0d 01 ori s11, s11, 16 +8000bb04: 6f f0 5f 98 j -1660 +8000bb08: 83 46 0d 00 lbu a3, 0(s10) +8000bb0c: 93 07 80 06 addi a5, zero, 104 +8000bb10: 63 86 f6 64 beq a3, a5, 1612 +8000bb14: 93 ed 0d 04 ori s11, s11, 64 +8000bb18: 6f f0 1f 97 j -1680 +8000bb1c: 13 e9 0d 01 ori s2, s11, 16 +8000bb20: 93 77 09 02 andi a5, s2, 32 +8000bb24: 63 84 07 38 beqz a5, 904 +8000bb28: 83 27 c1 00 lw a5, 12(sp) +8000bb2c: 93 06 10 00 addi a3, zero, 1 +8000bb30: 93 89 77 00 addi s3, a5, 7 +8000bb34: 93 f9 89 ff andi s3, s3, -8 +8000bb38: 93 87 89 00 addi a5, s3, 8 +8000bb3c: 03 ac 09 00 lw s8, 0(s3) +8000bb40: 03 ae 49 00 lw t3, 4(s3) +8000bb44: 23 26 f1 00 sw a5, 12(sp) +8000bb48: 6f f0 df bf j -1028 +8000bb4c: 13 06 10 00 addi a2, zero, 1 +8000bb50: 63 8e c6 78 beq a3, a2, 1948 +8000bb54: 13 06 20 00 addi a2, zero, 2 +8000bb58: 13 89 0d 00 mv s2, s11 +8000bb5c: e3 90 c6 da bne a3, a2, -608 +8000bb60: 93 09 01 0f addi s3, sp, 240 +8000bb64: 83 27 01 01 lw a5, 16(sp) +8000bb68: 93 76 fc 00 andi a3, s8, 15 +8000bb6c: 93 89 f9 ff addi s3, s3, -1 +8000bb70: b3 86 d7 00 add a3, a5, a3 +8000bb74: 03 c6 06 00 lbu a2, 0(a3) +8000bb78: 93 57 4c 00 srli a5, s8, 4 +8000bb7c: 93 16 ce 01 slli a3, t3, 28 +8000bb80: 33 ec f6 00 or s8, a3, a5 +8000bb84: 13 5e 4e 00 srli t3, t3, 4 +8000bb88: 23 80 c9 00 sb a2, 0(s3) +8000bb8c: b3 66 cc 01 or a3, s8, t3 +8000bb90: e3 9a 06 fc bnez a3, -44 +8000bb94: 93 07 01 0f addi a5, sp, 240 +8000bb98: 33 8c 37 41 sub s8, a5, s3 +8000bb9c: 93 0d 09 00 mv s11, s2 +8000bba0: 6f f0 df bd j -1060 +8000bba4: b3 06 24 41 sub a3, s0, s2 +8000bba8: e3 5e d0 9e blez a3, -1540 +8000bbac: 13 0e 00 01 addi t3, zero, 16 +8000bbb0: 63 52 de 74 bge t3, a3, 1860 +8000bbb4: 13 0f 70 00 addi t5, zero, 7 +8000bbb8: 6f 00 c0 00 j 12 +8000bbbc: 93 86 06 ff addi a3, a3, -16 +8000bbc0: 63 5e de 04 bge t3, a3, 92 +8000bbc4: 93 87 07 01 addi a5, a5, 16 +8000bbc8: 13 06 16 00 addi a2, a2, 1 +8000bbcc: 23 20 97 00 sw s1, 0(a4) +8000bbd0: 23 22 c7 01 sw t3, 4(a4) +8000bbd4: 23 24 f1 04 sw a5, 72(sp) +8000bbd8: 23 22 c1 04 sw a2, 68(sp) +8000bbdc: 13 07 87 00 addi a4, a4, 8 +8000bbe0: e3 5e cf fc bge t5, a2, -36 +8000bbe4: 13 06 01 04 addi a2, sp, 64 +8000bbe8: 93 05 0a 00 mv a1, s4 +8000bbec: 13 05 0b 00 mv a0, s6 +8000bbf0: 23 2c d1 00 sw a3, 24(sp) +8000bbf4: ef f0 cf da jal -2644 +8000bbf8: e3 18 05 a0 bnez a0, -1520 +8000bbfc: 83 26 81 01 lw a3, 24(sp) +8000bc00: 13 0e 00 01 addi t3, zero, 16 +8000bc04: 83 27 81 04 lw a5, 72(sp) +8000bc08: 93 86 06 ff addi a3, a3, -16 +8000bc0c: 03 26 41 04 lw a2, 68(sp) +8000bc10: 13 87 0a 00 mv a4, s5 +8000bc14: 13 0f 70 00 addi t5, zero, 7 +8000bc18: e3 46 de fa blt t3, a3, -84 +8000bc1c: 13 06 16 00 addi a2, a2, 1 +8000bc20: 13 0e 87 00 addi t3, a4, 8 +8000bc24: b3 87 d7 00 add a5, a5, a3 +8000bc28: 23 20 97 00 sw s1, 0(a4) +8000bc2c: 23 22 d7 00 sw a3, 4(a4) +8000bc30: 23 24 f1 04 sw a5, 72(sp) +8000bc34: 23 22 c1 04 sw a2, 68(sp) +8000bc38: 13 07 70 00 addi a4, zero, 7 +8000bc3c: 63 40 c7 54 blt a4, a2, 1344 +8000bc40: b3 8c 8c 41 sub s9, s9, s8 +8000bc44: 13 05 16 00 addi a0, a2, 1 +8000bc48: 93 05 8e 00 addi a1, t3, 8 +8000bc4c: 13 07 0e 00 mv a4, t3 +8000bc50: e3 5e 90 95 blez s9, -1700 +8000bc54: 13 03 00 01 addi t1, zero, 16 +8000bc58: 63 5c 93 5f bge t1, s9, 1528 +8000bc5c: 13 0e 70 00 addi t3, zero, 7 +8000bc60: 6f 00 c0 00 j 12 +8000bc64: 93 8c 0c ff addi s9, s9, -16 +8000bc68: 63 5a 93 05 bge t1, s9, 84 +8000bc6c: 93 87 07 01 addi a5, a5, 16 +8000bc70: 13 06 16 00 addi a2, a2, 1 +8000bc74: 23 20 97 00 sw s1, 0(a4) +8000bc78: 23 22 67 00 sw t1, 4(a4) +8000bc7c: 23 24 f1 04 sw a5, 72(sp) +8000bc80: 23 22 c1 04 sw a2, 68(sp) +8000bc84: 13 07 87 00 addi a4, a4, 8 +8000bc88: e3 5e ce fc bge t3, a2, -36 +8000bc8c: 13 06 01 04 addi a2, sp, 64 +8000bc90: 93 05 0a 00 mv a1, s4 +8000bc94: 13 05 0b 00 mv a0, s6 +8000bc98: ef f0 8f d0 jal -2808 +8000bc9c: e3 16 05 96 bnez a0, -1684 +8000bca0: 13 03 00 01 addi t1, zero, 16 +8000bca4: 93 8c 0c ff addi s9, s9, -16 +8000bca8: 83 27 81 04 lw a5, 72(sp) +8000bcac: 03 26 41 04 lw a2, 68(sp) +8000bcb0: 13 87 0a 00 mv a4, s5 +8000bcb4: 13 0e 70 00 addi t3, zero, 7 +8000bcb8: e3 4a 93 fb blt t1, s9, -76 +8000bcbc: 13 05 16 00 addi a0, a2, 1 +8000bcc0: 13 06 87 00 addi a2, a4, 8 +8000bcc4: b3 87 97 01 add a5, a5, s9 +8000bcc8: 23 20 97 00 sw s1, 0(a4) +8000bccc: 23 22 97 01 sw s9, 4(a4) +8000bcd0: 23 24 f1 04 sw a5, 72(sp) +8000bcd4: 23 22 a1 04 sw a0, 68(sp) +8000bcd8: 13 07 70 00 addi a4, zero, 7 +8000bcdc: 63 40 a7 20 blt a4, a0, 512 +8000bce0: 13 07 06 00 mv a4, a2 +8000bce4: 13 05 15 00 addi a0, a0, 1 +8000bce8: b3 07 fc 00 add a5, s8, a5 +8000bcec: 23 20 37 01 sw s3, 0(a4) +8000bcf0: 23 22 87 01 sw s8, 4(a4) +8000bcf4: 23 24 f1 04 sw a5, 72(sp) +8000bcf8: 23 22 a1 04 sw a0, 68(sp) +8000bcfc: 13 07 70 00 addi a4, zero, 7 +8000bd00: 93 05 86 00 addi a1, a2, 8 +8000bd04: e3 52 a7 8c bge a4, a0, -1852 +8000bd08: 13 06 01 04 addi a2, sp, 64 +8000bd0c: 93 05 0a 00 mv a1, s4 +8000bd10: 13 05 0b 00 mv a0, s6 +8000bd14: ef f0 cf c8 jal -2932 +8000bd18: e3 18 05 8e bnez a0, -1808 +8000bd1c: 83 27 81 04 lw a5, 72(sp) +8000bd20: 93 85 0a 00 mv a1, s5 +8000bd24: 6f f0 5f 8a j -1884 +8000bd28: 13 06 01 04 addi a2, sp, 64 +8000bd2c: 93 05 0a 00 mv a1, s4 +8000bd30: 13 05 0b 00 mv a0, s6 +8000bd34: ef f0 cf c6 jal -2964 +8000bd38: e3 0c 05 8a beqz a0, -1864 +8000bd3c: 6f f0 df 8c j -1844 +8000bd40: 13 89 0d 00 mv s2, s11 +8000bd44: 6f f0 9f ba j -1112 +8000bd48: 93 05 00 01 addi a1, zero, 16 +8000bd4c: 63 d0 d5 08 bge a1, a3, 128 +8000bd50: 93 0f 00 01 addi t6, zero, 16 +8000bd54: 93 02 70 00 addi t0, zero, 7 +8000bd58: 6f 00 c0 00 j 12 +8000bd5c: 93 86 06 ff addi a3, a3, -16 +8000bd60: 63 d6 df 06 bge t6, a3, 108 +8000bd64: 93 87 07 01 addi a5, a5, 16 +8000bd68: 13 06 16 00 addi a2, a2, 1 +8000bd6c: 23 20 77 01 sw s7, 0(a4) +8000bd70: 23 22 f7 01 sw t6, 4(a4) +8000bd74: 23 24 f1 04 sw a5, 72(sp) +8000bd78: 23 22 c1 04 sw a2, 68(sp) +8000bd7c: 13 07 87 00 addi a4, a4, 8 +8000bd80: e3 de c2 fc bge t0, a2, -36 +8000bd84: 13 06 01 04 addi a2, sp, 64 +8000bd88: 93 05 0a 00 mv a1, s4 +8000bd8c: 13 05 0b 00 mv a0, s6 +8000bd90: 23 20 d1 02 sw a3, 32(sp) +8000bd94: 23 2e c1 01 sw t3, 28(sp) +8000bd98: 23 2c e1 01 sw t5, 24(sp) +8000bd9c: ef f0 4f c0 jal -3068 +8000bda0: e3 14 05 86 bnez a0, -1944 +8000bda4: 83 26 01 02 lw a3, 32(sp) +8000bda8: 93 0f 00 01 addi t6, zero, 16 +8000bdac: 83 27 81 04 lw a5, 72(sp) +8000bdb0: 93 86 06 ff addi a3, a3, -16 +8000bdb4: 03 26 41 04 lw a2, 68(sp) +8000bdb8: 03 2e c1 01 lw t3, 28(sp) +8000bdbc: 03 2f 81 01 lw t5, 24(sp) +8000bdc0: 13 87 0a 00 mv a4, s5 +8000bdc4: 93 02 70 00 addi t0, zero, 7 +8000bdc8: e3 ce df f8 blt t6, a3, -100 +8000bdcc: b3 87 d7 00 add a5, a5, a3 +8000bdd0: 13 06 16 00 addi a2, a2, 1 +8000bdd4: 23 22 d7 00 sw a3, 4(a4) +8000bdd8: 23 20 77 01 sw s7, 0(a4) +8000bddc: 23 24 f1 04 sw a5, 72(sp) +8000bde0: 23 22 c1 04 sw a2, 68(sp) +8000bde4: 93 06 70 00 addi a3, zero, 7 +8000bde8: 13 07 87 00 addi a4, a4, 8 +8000bdec: 63 d6 c6 f2 bge a3, a2, -2260 +8000bdf0: 13 06 01 04 addi a2, sp, 64 +8000bdf4: 93 05 0a 00 mv a1, s4 +8000bdf8: 13 05 0b 00 mv a0, s6 +8000bdfc: 23 2e c1 01 sw t3, 28(sp) +8000be00: 23 2c e1 01 sw t5, 24(sp) +8000be04: ef f0 cf b9 jal -3172 +8000be08: e3 10 05 80 bnez a0, -2048 +8000be0c: 83 27 81 04 lw a5, 72(sp) +8000be10: 03 26 41 04 lw a2, 68(sp) +8000be14: 03 2e c1 01 lw t3, 28(sp) +8000be18: 03 2f 81 01 lw t5, 24(sp) +8000be1c: 13 87 0a 00 mv a4, s5 +8000be20: 6f f0 8f ef j -2312 +8000be24: 13 06 01 04 addi a2, sp, 64 +8000be28: 93 05 0a 00 mv a1, s4 +8000be2c: 13 05 0b 00 mv a0, s6 +8000be30: 23 2e c1 01 sw t3, 28(sp) +8000be34: 23 2c e1 01 sw t5, 24(sp) +8000be38: ef f0 8f b6 jal -3224 +8000be3c: 63 16 05 fc bnez a0, -2100 +8000be40: 03 26 41 04 lw a2, 68(sp) +8000be44: 83 27 81 04 lw a5, 72(sp) +8000be48: 03 2e c1 01 lw t3, 28(sp) +8000be4c: 03 2f 81 01 lw t5, 24(sp) +8000be50: 93 05 41 05 addi a1, sp, 84 +8000be54: 13 05 16 00 addi a0, a2, 1 +8000be58: 13 87 0a 00 mv a4, s5 +8000be5c: 6f f0 8f f0 j -2296 +8000be60: 13 06 01 04 addi a2, sp, 64 +8000be64: 93 05 0a 00 mv a1, s4 +8000be68: 13 05 0b 00 mv a0, s6 +8000be6c: 23 2c c1 01 sw t3, 24(sp) +8000be70: ef f0 0f b3 jal -3280 +8000be74: 63 1a 05 f8 bnez a0, -2156 +8000be78: 03 26 41 04 lw a2, 68(sp) +8000be7c: 83 27 81 04 lw a5, 72(sp) +8000be80: 03 2e 81 01 lw t3, 24(sp) +8000be84: 93 05 41 05 addi a1, sp, 84 +8000be88: 13 05 16 00 addi a0, a2, 1 +8000be8c: 13 87 0a 00 mv a4, s5 +8000be90: 6f f0 cf f0 j -2292 +8000be94: e3 94 0c 86 bnez s9, -1944 +8000be98: 93 0d 09 00 mv s11, s2 +8000be9c: 93 0c 00 00 mv s9, zero +8000bea0: 13 0c 00 00 mv s8, zero +8000bea4: 93 09 01 0f addi s3, sp, 240 +8000bea8: 6f f0 5f 8d j -1836 +8000beac: 03 26 c1 00 lw a2, 12(sp) +8000beb0: 93 77 09 01 andi a5, s2, 16 +8000beb4: 93 06 46 00 addi a3, a2, 4 +8000beb8: 63 96 07 18 bnez a5, 396 +8000bebc: 93 77 09 04 andi a5, s2, 64 +8000bec0: 63 88 07 36 beqz a5, 880 +8000bec4: 83 27 c1 00 lw a5, 12(sp) +8000bec8: 13 0e 00 00 mv t3, zero +8000becc: 23 26 d1 00 sw a3, 12(sp) +8000bed0: 03 dc 07 00 lhu s8, 0(a5) +8000bed4: 93 06 10 00 addi a3, zero, 1 +8000bed8: 6f f0 df 86 j -1940 +8000bedc: 13 06 01 04 addi a2, sp, 64 +8000bee0: 93 05 0a 00 mv a1, s4 +8000bee4: 13 05 0b 00 mv a0, s6 +8000bee8: ef f0 8f ab jal -3400 +8000beec: 63 1e 05 f0 bnez a0, -2276 +8000bef0: 03 25 41 04 lw a0, 68(sp) +8000bef4: 83 27 81 04 lw a5, 72(sp) +8000bef8: 93 05 41 05 addi a1, sp, 84 +8000befc: 13 05 15 00 addi a0, a0, 1 +8000bf00: 13 87 0a 00 mv a4, s5 +8000bf04: 6f f0 8f ea j -2392 +8000bf08: 93 77 09 40 andi a5, s2, 1024 +8000bf0c: 23 20 f1 02 sw a5, 32(sp) +8000bf10: 93 0d 00 00 mv s11, zero +8000bf14: 93 09 01 0f addi s3, sp, 240 +8000bf18: 6f 00 40 03 j 52 +8000bf1c: 93 05 0e 00 mv a1, t3 +8000bf20: 13 06 a0 00 addi a2, zero, 10 +8000bf24: 93 06 00 00 mv a3, zero +8000bf28: 13 05 0c 00 mv a0, s8 +8000bf2c: 23 2e e1 00 sw a4, 28(sp) +8000bf30: 23 2c c1 01 sw t3, 24(sp) +8000bf34: ef 40 80 07 jal 16504 +8000bf38: 03 2e 81 01 lw t3, 24(sp) +8000bf3c: 03 27 c1 01 lw a4, 28(sp) +8000bf40: 63 0c 0e 30 beqz t3, 792 +8000bf44: 13 0c 05 00 mv s8, a0 +8000bf48: 13 8e 05 00 mv t3, a1 +8000bf4c: 93 05 0e 00 mv a1, t3 +8000bf50: 13 06 a0 00 addi a2, zero, 10 +8000bf54: 93 06 00 00 mv a3, zero +8000bf58: 13 05 0c 00 mv a0, s8 +8000bf5c: 23 2e e1 00 sw a4, 28(sp) +8000bf60: 23 2c c1 01 sw t3, 24(sp) +8000bf64: ef 40 c0 47 jal 17532 +8000bf68: 83 27 01 02 lw a5, 32(sp) +8000bf6c: 13 05 05 03 addi a0, a0, 48 +8000bf70: a3 8f a9 fe sb a0, -1(s3) +8000bf74: 03 2e 81 01 lw t3, 24(sp) +8000bf78: 03 27 c1 01 lw a4, 28(sp) +8000bf7c: 93 89 f9 ff addi s3, s3, -1 +8000bf80: 93 8d 1d 00 addi s11, s11, 1 +8000bf84: e3 8c 07 f8 beqz a5, -104 +8000bf88: 83 27 41 02 lw a5, 36(sp) +8000bf8c: 83 c6 07 00 lbu a3, 0(a5) +8000bf90: e3 96 b6 f9 bne a3, s11, -116 +8000bf94: 93 07 f0 0f addi a5, zero, 255 +8000bf98: e3 82 fd f8 beq s11, a5, -124 +8000bf9c: 63 16 0e 00 bnez t3, 12 +8000bfa0: 93 07 90 00 addi a5, zero, 9 +8000bfa4: e3 f8 87 bf bgeu a5, s8, -1040 +8000bfa8: 83 27 81 02 lw a5, 40(sp) +8000bfac: 83 25 c1 02 lw a1, 44(sp) +8000bfb0: 23 2e c1 01 sw t3, 28(sp) +8000bfb4: b3 89 f9 40 sub s3, s3, a5 +8000bfb8: 13 86 07 00 mv a2, a5 +8000bfbc: 13 85 09 00 mv a0, s3 +8000bfc0: 23 2c e1 00 sw a4, 24(sp) +8000bfc4: ef f0 4f 93 jal -3788 +8000bfc8: 03 27 41 02 lw a4, 36(sp) +8000bfcc: 03 2e c1 01 lw t3, 28(sp) +8000bfd0: 13 06 a0 00 addi a2, zero, 10 +8000bfd4: 83 45 17 00 lbu a1, 1(a4) +8000bfd8: 93 06 00 00 mv a3, zero +8000bfdc: 13 05 0c 00 mv a0, s8 +8000bfe0: b3 37 b0 00 snez a5, a1 +8000bfe4: b3 07 f7 00 add a5, a4, a5 +8000bfe8: 93 05 0e 00 mv a1, t3 +8000bfec: 23 22 f1 02 sw a5, 36(sp) +8000bff0: ef 30 d0 7b jal 16316 +8000bff4: 03 27 81 01 lw a4, 24(sp) +8000bff8: 93 0d 00 00 mv s11, zero +8000bffc: 6f f0 9f f4 j -184 +8000c000: 83 27 41 02 lw a5, 36(sp) +8000c004: 83 46 0d 00 lbu a3, 0(s10) +8000c008: 63 80 07 c8 beqz a5, -2944 +8000c00c: 83 c7 07 00 lbu a5, 0(a5) +8000c010: 63 8c 07 c6 beqz a5, -2952 +8000c014: 93 ed 0d 40 ori s11, s11, 1024 +8000c018: 6f f0 0f c7 j -2960 +8000c01c: 03 26 81 00 lw a2, 8(sp) +8000c020: 93 57 f6 41 srai a5, a2, 31 +8000c024: 23 a0 c6 00 sw a2, 0(a3) +8000c028: 23 a2 f6 00 sw a5, 4(a3) +8000c02c: 6f f0 0f bd j -3120 +8000c030: 03 2c 06 00 lw s8, 0(a2) +8000c034: 23 26 d1 00 sw a3, 12(sp) +8000c038: 13 5e fc 41 srai t3, s8, 31 +8000c03c: 93 06 0e 00 mv a3, t3 +8000c040: 6f f0 4f e9 j -2412 +8000c044: 23 26 d1 00 sw a3, 12(sp) +8000c048: 03 2c 06 00 lw s8, 0(a2) +8000c04c: 13 0e 00 00 mv t3, zero +8000c050: 93 06 10 00 addi a3, zero, 1 +8000c054: 6f f0 0f ef j -2320 +8000c058: 03 2c 06 00 lw s8, 0(a2) +8000c05c: 13 0e 00 00 mv t3, zero +8000c060: 23 26 d1 00 sw a3, 12(sp) +8000c064: 6f f0 8f ed j -2344 +8000c068: 13 89 0d 00 mv s2, s11 +8000c06c: 6f f0 5f ab j -1356 +8000c070: b7 57 01 80 lui a5, 524309 +8000c074: 93 87 c7 5b addi a5, a5, 1468 +8000c078: 23 28 f1 00 sw a5, 16(sp) +8000c07c: 93 f7 0d 02 andi a5, s11, 32 +8000c080: 63 80 07 06 beqz a5, 96 +8000c084: 83 27 c1 00 lw a5, 12(sp) +8000c088: 93 89 77 00 addi s3, a5, 7 +8000c08c: 93 f9 89 ff andi s3, s3, -8 +8000c090: 03 ac 09 00 lw s8, 0(s3) +8000c094: 03 ae 49 00 lw t3, 4(s3) +8000c098: 93 87 89 00 addi a5, s3, 8 +8000c09c: 23 26 f1 00 sw a5, 12(sp) +8000c0a0: 13 f6 1d 00 andi a2, s11, 1 +8000c0a4: 63 0e 06 00 beqz a2, 28 +8000c0a8: 33 66 cc 01 or a2, s8, t3 +8000c0ac: 63 0a 06 00 beqz a2, 20 +8000c0b0: 13 06 00 03 addi a2, zero, 48 +8000c0b4: 23 0e c1 02 sb a2, 60(sp) +8000c0b8: a3 0e d1 02 sb a3, 61(sp) +8000c0bc: 93 ed 2d 00 ori s11, s11, 2 +8000c0c0: 13 f9 fd bf andi s2, s11, -1025 +8000c0c4: 93 06 20 00 addi a3, zero, 2 +8000c0c8: 6f f0 cf e7 j -2436 +8000c0cc: b7 57 01 80 lui a5, 524309 +8000c0d0: 93 87 87 5a addi a5, a5, 1448 +8000c0d4: 23 28 f1 00 sw a5, 16(sp) +8000c0d8: 93 f7 0d 02 andi a5, s11, 32 +8000c0dc: e3 94 07 fa bnez a5, -88 +8000c0e0: 83 25 c1 00 lw a1, 12(sp) +8000c0e4: 93 f7 0d 01 andi a5, s11, 16 +8000c0e8: 13 86 45 00 addi a2, a1, 4 +8000c0ec: 63 8a 07 04 beqz a5, 84 +8000c0f0: 03 ac 05 00 lw s8, 0(a1) +8000c0f4: 13 0e 00 00 mv t3, zero +8000c0f8: 23 26 c1 00 sw a2, 12(sp) +8000c0fc: 6f f0 5f fa j -92 +8000c100: 13 85 09 00 mv a0, s3 +8000c104: 23 2c e1 00 sw a4, 24(sp) +8000c108: 23 26 d1 00 sw a3, 12(sp) +8000c10c: ef e0 1f f6 jal -4256 +8000c110: 03 27 81 01 lw a4, 24(sp) +8000c114: 13 0c 05 00 mv s8, a0 +8000c118: 93 0c 00 00 mv s9, zero +8000c11c: 6f f0 0f e6 j -2464 +8000c120: 93 05 00 04 addi a1, zero, 64 +8000c124: ef d0 cf ab jal -11588 +8000c128: 23 20 aa 00 sw a0, 0(s4) +8000c12c: 23 28 aa 00 sw a0, 16(s4) +8000c130: 63 00 05 20 beqz a0, 512 +8000c134: 93 07 00 04 addi a5, zero, 64 +8000c138: 23 2a fa 00 sw a5, 20(s4) +8000c13c: 6f f0 cf a7 j -3460 +8000c140: 93 f7 0d 04 andi a5, s11, 64 +8000c144: 63 8a 07 08 beqz a5, 148 +8000c148: 83 27 c1 00 lw a5, 12(sp) +8000c14c: 13 0e 00 00 mv t3, zero +8000c150: 23 26 c1 00 sw a2, 12(sp) +8000c154: 03 dc 07 00 lhu s8, 0(a5) +8000c158: 6f f0 9f f4 j -184 +8000c15c: 83 46 1d 00 lbu a3, 1(s10) +8000c160: 93 ed 0d 20 ori s11, s11, 512 +8000c164: 13 0d 1d 00 addi s10, s10, 1 +8000c168: 6f f0 0f b2 j -3296 +8000c16c: 83 46 1d 00 lbu a3, 1(s10) +8000c170: 93 ed 0d 02 ori s11, s11, 32 +8000c174: 13 0d 1d 00 addi s10, s10, 1 +8000c178: 6f f0 0f b1 j -3312 +8000c17c: 13 06 01 04 addi a2, sp, 64 +8000c180: 93 05 0a 00 mv a1, s4 +8000c184: 13 05 0b 00 mv a0, s6 +8000c188: ef f0 8f 81 jal -4072 +8000c18c: 63 1e 05 c6 bnez a0, -2948 +8000c190: 03 26 41 04 lw a2, 68(sp) +8000c194: 83 27 81 04 lw a5, 72(sp) +8000c198: 93 05 41 05 addi a1, sp, 84 +8000c19c: 13 05 16 00 addi a0, a2, 1 +8000c1a0: 13 87 0a 00 mv a4, s5 +8000c1a4: 6f f0 0f c0 j -3072 +8000c1a8: 83 27 81 00 lw a5, 8(sp) +8000c1ac: 23 a0 f6 00 sw a5, 0(a3) +8000c1b0: 6f f0 cf a4 j -3508 +8000c1b4: 93 07 60 00 addi a5, zero, 6 +8000c1b8: 13 8c 0c 00 mv s8, s9 +8000c1bc: 63 f4 97 01 bgeu a5, s9, 8 +8000c1c0: 13 0c 60 00 addi s8, zero, 6 +8000c1c4: b7 5e 01 80 lui t4, 524309 +8000c1c8: 13 09 0c 00 mv s2, s8 +8000c1cc: 23 26 d1 00 sw a3, 12(sp) +8000c1d0: 93 89 0e 5d addi s3, t4, 1488 +8000c1d4: 6f f0 cf b1 j -3300 +8000c1d8: 93 f7 0d 20 andi a5, s11, 512 +8000c1dc: 63 86 07 0c beqz a5, 204 +8000c1e0: 83 27 c1 00 lw a5, 12(sp) +8000c1e4: 13 0e 00 00 mv t3, zero +8000c1e8: 23 26 c1 00 sw a2, 12(sp) +8000c1ec: 03 cc 07 00 lbu s8, 0(a5) +8000c1f0: 6f f0 1f eb j -336 +8000c1f4: 93 f7 0d 20 andi a5, s11, 512 +8000c1f8: 63 8c 07 08 beqz a5, 152 +8000c1fc: 83 27 c1 00 lw a5, 12(sp) +8000c200: 23 26 d1 00 sw a3, 12(sp) +8000c204: 03 8c 07 00 lb s8, 0(a5) +8000c208: 13 5e fc 41 srai t3, s8, 31 +8000c20c: 93 06 0e 00 mv a3, t3 +8000c210: 6f f0 4f cc j -2876 +8000c214: 93 f7 0d 20 andi a5, s11, 512 +8000c218: 63 82 07 06 beqz a5, 100 +8000c21c: 83 27 c1 00 lw a5, 12(sp) +8000c220: 13 0e 00 00 mv t3, zero +8000c224: 23 26 d1 00 sw a3, 12(sp) +8000c228: 03 cc 07 00 lbu s8, 0(a5) +8000c22c: 6f f0 0f d1 j -2800 +8000c230: 93 77 09 20 andi a5, s2, 512 +8000c234: 63 88 07 02 beqz a5, 48 +8000c238: 83 27 c1 00 lw a5, 12(sp) +8000c23c: 13 0e 00 00 mv t3, zero +8000c240: 23 26 d1 00 sw a3, 12(sp) +8000c244: 03 cc 07 00 lbu s8, 0(a5) +8000c248: 93 06 10 00 addi a3, zero, 1 +8000c24c: 6f f0 8f cf j -2824 +8000c250: 13 86 05 00 mv a2, a1 +8000c254: 6f f0 1f a7 j -1424 +8000c258: 93 07 90 00 addi a5, zero, 9 +8000c25c: e3 e4 87 cf bltu a5, s8, -792 +8000c260: 6f f0 5f 93 j -1740 +8000c264: 83 27 c1 00 lw a5, 12(sp) +8000c268: 13 0e 00 00 mv t3, zero +8000c26c: 23 26 d1 00 sw a3, 12(sp) +8000c270: 03 ac 07 00 lw s8, 0(a5) +8000c274: 93 06 10 00 addi a3, zero, 1 +8000c278: 6f f0 cf cc j -2868 +8000c27c: 83 27 c1 00 lw a5, 12(sp) +8000c280: 13 0e 00 00 mv t3, zero +8000c284: 23 26 d1 00 sw a3, 12(sp) +8000c288: 03 ac 07 00 lw s8, 0(a5) +8000c28c: 6f f0 0f cb j -2896 +8000c290: 83 27 c1 00 lw a5, 12(sp) +8000c294: 23 26 d1 00 sw a3, 12(sp) +8000c298: 03 ac 07 00 lw s8, 0(a5) +8000c29c: 13 5e fc 41 srai t3, s8, 31 +8000c2a0: 93 06 0e 00 mv a3, t3 +8000c2a4: 6f f0 0f c3 j -3024 +8000c2a8: 83 27 c1 00 lw a5, 12(sp) +8000c2ac: 13 0e 00 00 mv t3, zero +8000c2b0: 23 26 c1 00 sw a2, 12(sp) +8000c2b4: 03 ac 07 00 lw s8, 0(a5) +8000c2b8: 6f f0 9f de j -536 +8000c2bc: 83 27 81 00 lw a5, 8(sp) +8000c2c0: 23 90 f6 00 sh a5, 0(a3) +8000c2c4: 6f f0 8f 93 j -3784 +8000c2c8: 13 06 01 04 addi a2, sp, 64 +8000c2cc: 93 05 0a 00 mv a1, s4 +8000c2d0: 13 05 0b 00 mv a0, s6 +8000c2d4: ef e0 df ec jal -4404 +8000c2d8: 6f f0 0f b3 j -3280 +8000c2dc: 13 8c 0c 00 mv s8, s9 +8000c2e0: 23 26 d1 00 sw a3, 12(sp) +8000c2e4: 93 0c 00 00 mv s9, zero +8000c2e8: 6f f0 4f c9 j -2924 +8000c2ec: 13 89 0d 00 mv s2, s11 +8000c2f0: 6f f0 cf c0 j -3060 +8000c2f4: 13 8e 05 00 mv t3, a1 +8000c2f8: 13 06 05 00 mv a2, a0 +8000c2fc: 6f f0 9f 92 j -1752 +8000c300: 93 07 f0 ff addi a5, zero, -1 +8000c304: 23 24 f1 00 sw a5, 8(sp) +8000c308: 6f f0 cf b0 j -3316 +8000c30c: 83 27 c1 00 lw a5, 12(sp) +8000c310: 83 ac 07 00 lw s9, 0(a5) +8000c314: 93 87 47 00 addi a5, a5, 4 +8000c318: 63 d4 0c 00 bgez s9, 8 +8000c31c: 93 0c f0 ff addi s9, zero, -1 +8000c320: 83 46 1d 00 lbu a3, 1(s10) +8000c324: 23 26 f1 00 sw a5, 12(sp) +8000c328: 13 8d 05 00 mv s10, a1 +8000c32c: 6f f0 cf 95 j -3748 +8000c330: 93 07 c0 00 addi a5, zero, 12 +8000c334: 23 20 fb 00 sw a5, 0(s6) +8000c338: 93 07 f0 ff addi a5, zero, -1 +8000c33c: 23 24 f1 00 sw a5, 8(sp) +8000c340: 6f f0 4f ad j -3372 + +8000c344 __assert_func: +8000c344: b7 87 01 80 lui a5, 524312 +8000c348: 03 a7 c7 b9 lw a4, -1124(a5) +8000c34c: 13 01 01 ff addi sp, sp, -16 +8000c350: 93 87 06 00 mv a5, a3 +8000c354: 13 08 06 00 mv a6, a2 +8000c358: 23 26 11 00 sw ra, 12(sp) +8000c35c: 83 28 c7 00 lw a7, 12(a4) +8000c360: 93 06 05 00 mv a3, a0 +8000c364: 13 87 05 00 mv a4, a1 +8000c368: 13 86 07 00 mv a2, a5 +8000c36c: 63 00 08 02 beqz a6, 32 +8000c370: b7 67 01 80 lui a5, 524310 +8000c374: 93 87 47 d0 addi a5, a5, -764 +8000c378: b7 65 01 80 lui a1, 524310 +8000c37c: 93 85 45 d1 addi a1, a1, -748 +8000c380: 13 85 08 00 mv a0, a7 +8000c384: ef 00 40 11 jal 276 +8000c388: ef 20 40 12 jal 8484 +8000c38c: 37 68 01 80 lui a6, 524310 +8000c390: 93 07 08 d1 addi a5, a6, -752 +8000c394: 13 08 08 d1 addi a6, a6, -752 +8000c398: 6f f0 1f fe j -32 + +8000c39c __assert: +8000c39c: 13 01 01 ff addi sp, sp, -16 +8000c3a0: 93 06 06 00 mv a3, a2 +8000c3a4: 13 06 00 00 mv a2, zero +8000c3a8: 23 26 11 00 sw ra, 12(sp) +8000c3ac: ef f0 9f f9 jal -104 + +8000c3b0 _calloc_r: +8000c3b0: b3 85 c5 02 mul a1, a1, a2 +8000c3b4: 13 01 01 ff addi sp, sp, -16 +8000c3b8: 23 24 81 00 sw s0, 8(sp) +8000c3bc: 23 26 11 00 sw ra, 12(sp) +8000c3c0: ef d0 0f 82 jal -12256 +8000c3c4: 13 04 05 00 mv s0, a0 +8000c3c8: 63 08 05 02 beqz a0, 48 +8000c3cc: 03 26 c5 ff lw a2, -4(a0) +8000c3d0: 13 07 40 02 addi a4, zero, 36 +8000c3d4: 13 76 c6 ff andi a2, a2, -4 +8000c3d8: 13 06 c6 ff addi a2, a2, -4 +8000c3dc: 63 60 c7 06 bltu a4, a2, 96 +8000c3e0: 93 06 30 01 addi a3, zero, 19 +8000c3e4: 93 07 05 00 mv a5, a0 +8000c3e8: 63 e2 c6 02 bltu a3, a2, 36 +8000c3ec: 23 a0 07 00 sw zero, 0(a5) +8000c3f0: 23 a2 07 00 sw zero, 4(a5) +8000c3f4: 23 a4 07 00 sw zero, 8(a5) +8000c3f8: 83 20 c1 00 lw ra, 12(sp) +8000c3fc: 13 05 04 00 mv a0, s0 +8000c400: 03 24 81 00 lw s0, 8(sp) +8000c404: 13 01 01 01 addi sp, sp, 16 +8000c408: 67 80 00 00 ret +8000c40c: 23 20 05 00 sw zero, 0(a0) +8000c410: 23 22 05 00 sw zero, 4(a0) +8000c414: 93 07 b0 01 addi a5, zero, 27 +8000c418: 63 f0 c7 04 bgeu a5, a2, 64 +8000c41c: 23 24 05 00 sw zero, 8(a0) +8000c420: 23 26 05 00 sw zero, 12(a0) +8000c424: 93 07 05 01 addi a5, a0, 16 +8000c428: e3 12 e6 fc bne a2, a4, -60 +8000c42c: 23 28 05 00 sw zero, 16(a0) +8000c430: 93 07 85 01 addi a5, a0, 24 +8000c434: 23 2a 05 00 sw zero, 20(a0) +8000c438: 6f f0 5f fb j -76 +8000c43c: 93 05 00 00 mv a1, zero +8000c440: ef 70 8f 86 jal -36760 +8000c444: 83 20 c1 00 lw ra, 12(sp) +8000c448: 13 05 04 00 mv a0, s0 +8000c44c: 03 24 81 00 lw s0, 8(sp) +8000c450: 13 01 01 01 addi sp, sp, 16 +8000c454: 67 80 00 00 ret +8000c458: 93 07 85 00 addi a5, a0, 8 +8000c45c: 6f f0 1f f9 j -112 + +8000c460 _fiprintf_r: +8000c460: 13 01 01 fc addi sp, sp, -64 +8000c464: 13 03 c1 02 addi t1, sp, 44 +8000c468: 23 26 d1 02 sw a3, 44(sp) +8000c46c: 93 06 03 00 mv a3, t1 +8000c470: 23 2e 11 00 sw ra, 28(sp) +8000c474: 23 28 e1 02 sw a4, 48(sp) +8000c478: 23 2a f1 02 sw a5, 52(sp) +8000c47c: 23 2c 01 03 sw a6, 56(sp) +8000c480: 23 2e 11 03 sw a7, 60(sp) +8000c484: 23 26 61 00 sw t1, 12(sp) +8000c488: ef 00 d0 3a jal 2988 +8000c48c: 83 20 c1 01 lw ra, 28(sp) +8000c490: 13 01 01 04 addi sp, sp, 64 +8000c494: 67 80 00 00 ret + +8000c498 fiprintf: +8000c498: 13 0e 05 00 mv t3, a0 +8000c49c: 37 85 01 80 lui a0, 524312 +8000c4a0: 13 01 01 fc addi sp, sp, -64 +8000c4a4: 03 25 c5 b9 lw a0, -1124(a0) +8000c4a8: 13 03 81 02 addi t1, sp, 40 +8000c4ac: 23 24 c1 02 sw a2, 40(sp) +8000c4b0: 23 26 d1 02 sw a3, 44(sp) +8000c4b4: 13 86 05 00 mv a2, a1 +8000c4b8: 93 06 03 00 mv a3, t1 +8000c4bc: 93 05 0e 00 mv a1, t3 +8000c4c0: 23 2e 11 00 sw ra, 28(sp) +8000c4c4: 23 28 e1 02 sw a4, 48(sp) +8000c4c8: 23 2a f1 02 sw a5, 52(sp) +8000c4cc: 23 2c 01 03 sw a6, 56(sp) +8000c4d0: 23 2e 11 03 sw a7, 60(sp) +8000c4d4: 23 26 61 00 sw t1, 12(sp) +8000c4d8: ef 00 d0 35 jal 2908 +8000c4dc: 83 20 c1 01 lw ra, 28(sp) +8000c4e0: 13 01 01 04 addi sp, sp, 64 +8000c4e4: 67 80 00 00 ret + +8000c4e8 _setlocale_r: +8000c4e8: 13 01 01 ff addi sp, sp, -16 +8000c4ec: 23 26 11 00 sw ra, 12(sp) +8000c4f0: 23 24 81 00 sw s0, 8(sp) +8000c4f4: 23 22 91 00 sw s1, 4(sp) +8000c4f8: 63 0c 06 02 beqz a2, 56 +8000c4fc: b7 65 01 80 lui a1, 524310 +8000c500: 93 85 85 d4 addi a1, a1, -696 +8000c504: 13 05 06 00 mv a0, a2 +8000c508: 13 04 06 00 mv s0, a2 +8000c50c: ef 00 50 0a jal 2212 +8000c510: b7 64 01 80 lui s1, 524310 +8000c514: 63 12 05 02 bnez a0, 36 +8000c518: 13 85 44 d4 addi a0, s1, -700 +8000c51c: 83 20 c1 00 lw ra, 12(sp) +8000c520: 03 24 81 00 lw s0, 8(sp) +8000c524: 83 24 41 00 lw s1, 4(sp) +8000c528: 13 01 01 01 addi sp, sp, 16 +8000c52c: 67 80 00 00 ret +8000c530: b7 64 01 80 lui s1, 524310 +8000c534: 6f f0 5f fe j -28 +8000c538: 93 85 44 d4 addi a1, s1, -700 +8000c53c: 13 05 04 00 mv a0, s0 +8000c540: ef 00 10 07 jal 2160 +8000c544: e3 0a 05 fc beqz a0, -44 +8000c548: b7 65 01 80 lui a1, 524310 +8000c54c: 93 85 05 d1 addi a1, a1, -752 +8000c550: 13 05 04 00 mv a0, s0 +8000c554: ef 00 d0 05 jal 2140 +8000c558: e3 00 05 fc beqz a0, -64 +8000c55c: 13 05 00 00 mv a0, zero +8000c560: 6f f0 df fb j -68 + +8000c564 __locale_mb_cur_max: +8000c564: b7 87 01 80 lui a5, 524312 +8000c568: 03 c5 07 b3 lbu a0, -1232(a5) +8000c56c: 67 80 00 00 ret + +8000c570 setlocale: +8000c570: 37 87 01 80 lui a4, 524312 +8000c574: 93 07 05 00 mv a5, a0 +8000c578: 03 25 c7 b9 lw a0, -1124(a4) +8000c57c: 13 86 05 00 mv a2, a1 +8000c580: 93 85 07 00 mv a1, a5 +8000c584: 6f f0 5f f6 j -156 + +8000c588 _mbtowc_r: +8000c588: b7 87 01 80 lui a5, 524312 +8000c58c: 03 a3 c7 ae lw t1, -1300(a5) +8000c590: 67 00 03 00 jr t1 + +8000c594 __ascii_mbtowc: +8000c594: 63 80 05 02 beqz a1, 32 +8000c598: 63 02 06 04 beqz a2, 68 +8000c59c: 63 88 06 04 beqz a3, 80 +8000c5a0: 83 47 06 00 lbu a5, 0(a2) +8000c5a4: 23 a0 f5 00 sw a5, 0(a1) +8000c5a8: 03 45 06 00 lbu a0, 0(a2) +8000c5ac: 33 35 a0 00 snez a0, a0 +8000c5b0: 67 80 00 00 ret +8000c5b4: 13 01 01 ff addi sp, sp, -16 +8000c5b8: 93 05 c1 00 addi a1, sp, 12 +8000c5bc: 63 04 06 02 beqz a2, 40 +8000c5c0: 63 8a 06 02 beqz a3, 52 +8000c5c4: 83 47 06 00 lbu a5, 0(a2) +8000c5c8: 23 a0 f5 00 sw a5, 0(a1) +8000c5cc: 03 45 06 00 lbu a0, 0(a2) +8000c5d0: 33 35 a0 00 snez a0, a0 +8000c5d4: 13 01 01 01 addi sp, sp, 16 +8000c5d8: 67 80 00 00 ret +8000c5dc: 13 05 00 00 mv a0, zero +8000c5e0: 67 80 00 00 ret +8000c5e4: 13 05 00 00 mv a0, zero +8000c5e8: 6f f0 df fe j -20 +8000c5ec: 13 05 e0 ff addi a0, zero, -2 +8000c5f0: 67 80 00 00 ret +8000c5f4: 13 05 e0 ff addi a0, zero, -2 +8000c5f8: 6f f0 df fd j -36 + +8000c5fc memcpy: +8000c5fc: b3 c7 a5 00 xor a5, a1, a0 +8000c600: 93 f7 37 00 andi a5, a5, 3 +8000c604: b3 08 c5 00 add a7, a0, a2 +8000c608: 63 92 07 06 bnez a5, 100 +8000c60c: 93 07 30 00 addi a5, zero, 3 +8000c610: 63 fe c7 04 bgeu a5, a2, 92 +8000c614: 93 77 35 00 andi a5, a0, 3 +8000c618: 13 07 05 00 mv a4, a0 +8000c61c: 63 98 07 06 bnez a5, 112 +8000c620: 13 f6 c8 ff andi a2, a7, -4 +8000c624: 93 07 06 fe addi a5, a2, -32 +8000c628: 63 6c f7 08 bltu a4, a5, 152 +8000c62c: 63 7c c7 02 bgeu a4, a2, 56 +8000c630: 93 86 05 00 mv a3, a1 +8000c634: 93 07 07 00 mv a5, a4 +8000c638: 03 a8 06 00 lw a6, 0(a3) +8000c63c: 93 87 47 00 addi a5, a5, 4 +8000c640: 93 86 46 00 addi a3, a3, 4 +8000c644: 23 ae 07 ff sw a6, -4(a5) +8000c648: e3 e8 c7 fe bltu a5, a2, -16 +8000c64c: 93 07 f6 ff addi a5, a2, -1 +8000c650: b3 87 e7 40 sub a5, a5, a4 +8000c654: 93 f7 c7 ff andi a5, a5, -4 +8000c658: 93 87 47 00 addi a5, a5, 4 +8000c65c: 33 07 f7 00 add a4, a4, a5 +8000c660: b3 85 f5 00 add a1, a1, a5 +8000c664: 63 68 17 01 bltu a4, a7, 16 +8000c668: 67 80 00 00 ret +8000c66c: 13 07 05 00 mv a4, a0 +8000c670: e3 7c 15 ff bgeu a0, a7, -8 +8000c674: 83 c7 05 00 lbu a5, 0(a1) +8000c678: 13 07 17 00 addi a4, a4, 1 +8000c67c: 93 85 15 00 addi a1, a1, 1 +8000c680: a3 0f f7 fe sb a5, -1(a4) +8000c684: e3 68 17 ff bltu a4, a7, -16 +8000c688: 67 80 00 00 ret +8000c68c: 83 c6 05 00 lbu a3, 0(a1) +8000c690: 13 07 17 00 addi a4, a4, 1 +8000c694: 93 77 37 00 andi a5, a4, 3 +8000c698: a3 0f d7 fe sb a3, -1(a4) +8000c69c: 93 85 15 00 addi a1, a1, 1 +8000c6a0: e3 80 07 f8 beqz a5, -128 +8000c6a4: 83 c6 05 00 lbu a3, 0(a1) +8000c6a8: 13 07 17 00 addi a4, a4, 1 +8000c6ac: 93 77 37 00 andi a5, a4, 3 +8000c6b0: a3 0f d7 fe sb a3, -1(a4) +8000c6b4: 93 85 15 00 addi a1, a1, 1 +8000c6b8: e3 9a 07 fc bnez a5, -44 +8000c6bc: 6f f0 5f f6 j -156 +8000c6c0: 83 a6 45 00 lw a3, 4(a1) +8000c6c4: 83 a2 05 00 lw t0, 0(a1) +8000c6c8: 83 af 85 00 lw t6, 8(a1) +8000c6cc: 03 af c5 00 lw t5, 12(a1) +8000c6d0: 83 ae 05 01 lw t4, 16(a1) +8000c6d4: 03 ae 45 01 lw t3, 20(a1) +8000c6d8: 03 a3 85 01 lw t1, 24(a1) +8000c6dc: 03 a8 c5 01 lw a6, 28(a1) +8000c6e0: 23 22 d7 00 sw a3, 4(a4) +8000c6e4: 83 a6 05 02 lw a3, 32(a1) +8000c6e8: 23 20 57 00 sw t0, 0(a4) +8000c6ec: 23 24 f7 01 sw t6, 8(a4) +8000c6f0: 23 26 e7 01 sw t5, 12(a4) +8000c6f4: 23 28 d7 01 sw t4, 16(a4) +8000c6f8: 23 2a c7 01 sw t3, 20(a4) +8000c6fc: 23 2c 67 00 sw t1, 24(a4) +8000c700: 23 2e 07 01 sw a6, 28(a4) +8000c704: 23 20 d7 02 sw a3, 32(a4) +8000c708: 13 07 47 02 addi a4, a4, 36 +8000c70c: 93 85 45 02 addi a1, a1, 36 +8000c710: e3 68 f7 fa bltu a4, a5, -80 +8000c714: 6f f0 9f f1 j -232 + +8000c718 memmove: +8000c718: 63 f6 a5 02 bgeu a1, a0, 44 +8000c71c: b3 87 c5 00 add a5, a1, a2 +8000c720: 63 72 f5 02 bgeu a0, a5, 36 +8000c724: 33 07 c5 00 add a4, a0, a2 +8000c728: 63 0a 06 0e beqz a2, 244 +8000c72c: 83 c6 f7 ff lbu a3, -1(a5) +8000c730: 93 87 f7 ff addi a5, a5, -1 +8000c734: 13 07 f7 ff addi a4, a4, -1 +8000c738: 23 00 d7 00 sb a3, 0(a4) +8000c73c: e3 98 f5 fe bne a1, a5, -16 +8000c740: 67 80 00 00 ret +8000c744: 93 07 f0 00 addi a5, zero, 15 +8000c748: 63 e8 c7 02 bltu a5, a2, 48 +8000c74c: 93 07 05 00 mv a5, a0 +8000c750: 93 06 f6 ff addi a3, a2, -1 +8000c754: 63 0c 06 0c beqz a2, 216 +8000c758: 93 86 16 00 addi a3, a3, 1 +8000c75c: b3 86 d7 00 add a3, a5, a3 +8000c760: 03 c7 05 00 lbu a4, 0(a1) +8000c764: 93 87 17 00 addi a5, a5, 1 +8000c768: 93 85 15 00 addi a1, a1, 1 +8000c76c: a3 8f e7 fe sb a4, -1(a5) +8000c770: e3 98 d7 fe bne a5, a3, -16 +8000c774: 67 80 00 00 ret +8000c778: b3 e7 a5 00 or a5, a1, a0 +8000c77c: 93 f7 37 00 andi a5, a5, 3 +8000c780: 63 90 07 0a bnez a5, 160 +8000c784: 93 08 06 ff addi a7, a2, -16 +8000c788: 93 f8 08 ff andi a7, a7, -16 +8000c78c: 93 88 08 01 addi a7, a7, 16 +8000c790: 33 08 15 01 add a6, a0, a7 +8000c794: 13 87 05 00 mv a4, a1 +8000c798: 93 07 05 00 mv a5, a0 +8000c79c: 83 26 07 00 lw a3, 0(a4) +8000c7a0: 13 07 07 01 addi a4, a4, 16 +8000c7a4: 93 87 07 01 addi a5, a5, 16 +8000c7a8: 23 a8 d7 fe sw a3, -16(a5) +8000c7ac: 83 26 47 ff lw a3, -12(a4) +8000c7b0: 23 aa d7 fe sw a3, -12(a5) +8000c7b4: 83 26 87 ff lw a3, -8(a4) +8000c7b8: 23 ac d7 fe sw a3, -8(a5) +8000c7bc: 83 26 c7 ff lw a3, -4(a4) +8000c7c0: 23 ae d7 fe sw a3, -4(a5) +8000c7c4: e3 1c f8 fc bne a6, a5, -40 +8000c7c8: 13 77 c6 00 andi a4, a2, 12 +8000c7cc: b3 85 15 01 add a1, a1, a7 +8000c7d0: 13 78 f6 00 andi a6, a2, 15 +8000c7d4: 63 0e 07 04 beqz a4, 92 +8000c7d8: 13 87 05 00 mv a4, a1 +8000c7dc: 93 88 07 00 mv a7, a5 +8000c7e0: 13 0e 30 00 addi t3, zero, 3 +8000c7e4: 03 23 07 00 lw t1, 0(a4) +8000c7e8: 13 07 47 00 addi a4, a4, 4 +8000c7ec: b3 06 e8 40 sub a3, a6, a4 +8000c7f0: 23 a0 68 00 sw t1, 0(a7) +8000c7f4: b3 86 d5 00 add a3, a1, a3 +8000c7f8: 93 88 48 00 addi a7, a7, 4 +8000c7fc: e3 64 de fe bltu t3, a3, -24 +8000c800: 13 07 c8 ff addi a4, a6, -4 +8000c804: 13 77 c7 ff andi a4, a4, -4 +8000c808: 13 07 47 00 addi a4, a4, 4 +8000c80c: 13 76 36 00 andi a2, a2, 3 +8000c810: b3 87 e7 00 add a5, a5, a4 +8000c814: b3 85 e5 00 add a1, a1, a4 +8000c818: 6f f0 9f f3 j -200 +8000c81c: 67 80 00 00 ret +8000c820: 93 06 f6 ff addi a3, a2, -1 +8000c824: 93 07 05 00 mv a5, a0 +8000c828: 6f f0 1f f3 j -208 +8000c82c: 67 80 00 00 ret +8000c830: 13 06 08 00 mv a2, a6 +8000c834: 6f f0 df f1 j -228 + +8000c838 _realloc_r: +8000c838: 13 01 01 fd addi sp, sp, -48 +8000c83c: 23 20 21 03 sw s2, 32(sp) +8000c840: 23 26 11 02 sw ra, 44(sp) +8000c844: 23 24 81 02 sw s0, 40(sp) +8000c848: 23 22 91 02 sw s1, 36(sp) +8000c84c: 23 2e 31 01 sw s3, 28(sp) +8000c850: 23 2c 41 01 sw s4, 24(sp) +8000c854: 23 2a 51 01 sw s5, 20(sp) +8000c858: 23 28 61 01 sw s6, 16(sp) +8000c85c: 23 26 71 01 sw s7, 12(sp) +8000c860: 23 24 81 01 sw s8, 8(sp) +8000c864: 13 09 06 00 mv s2, a2 +8000c868: 63 84 05 22 beqz a1, 552 +8000c86c: 13 84 05 00 mv s0, a1 +8000c870: 93 09 05 00 mv s3, a0 +8000c874: ef d0 8f bf jal -11272 +8000c878: 93 04 b9 00 addi s1, s2, 11 +8000c87c: 93 07 60 01 addi a5, zero, 22 +8000c880: 63 fe 97 0e bgeu a5, s1, 252 +8000c884: 93 f4 84 ff andi s1, s1, -8 +8000c888: 13 87 04 00 mv a4, s1 +8000c88c: 63 ce 04 0e bltz s1, 252 +8000c890: 63 ec 24 0f bltu s1, s2, 248 +8000c894: 83 27 c4 ff lw a5, -4(s0) +8000c898: 93 0a 84 ff addi s5, s0, -8 +8000c89c: 13 fa c7 ff andi s4, a5, -4 +8000c8a0: 33 8b 4a 01 add s6, s5, s4 +8000c8a4: 63 5c ea 18 bge s4, a4, 408 +8000c8a8: b7 76 01 80 lui a3, 524311 +8000c8ac: 93 8b 06 60 addi s7, a3, 1536 +8000c8b0: 03 a6 8b 00 lw a2, 8(s7) +8000c8b4: 83 26 4b 00 lw a3, 4(s6) +8000c8b8: 63 0e 66 23 beq a2, s6, 572 +8000c8bc: 13 f6 e6 ff andi a2, a3, -2 +8000c8c0: 33 06 cb 00 add a2, s6, a2 +8000c8c4: 03 26 46 00 lw a2, 4(a2) +8000c8c8: 13 76 16 00 andi a2, a2, 1 +8000c8cc: 63 14 06 1a bnez a2, 424 +8000c8d0: 93 f6 c6 ff andi a3, a3, -4 +8000c8d4: 33 06 da 00 add a2, s4, a3 +8000c8d8: 63 5e e6 32 bge a2, a4, 828 +8000c8dc: 93 f7 17 00 andi a5, a5, 1 +8000c8e0: 63 94 07 02 bnez a5, 40 +8000c8e4: 03 2c 84 ff lw s8, -8(s0) +8000c8e8: 33 8c 8a 41 sub s8, s5, s8 +8000c8ec: 83 27 4c 00 lw a5, 4(s8) +8000c8f0: 93 f7 c7 ff andi a5, a5, -4 +8000c8f4: b3 86 d7 00 add a3, a5, a3 +8000c8f8: b3 8b 46 01 add s7, a3, s4 +8000c8fc: 63 da eb 34 bge s7, a4, 852 +8000c900: b3 0b fa 00 add s7, s4, a5 +8000c904: 63 d2 eb 0c bge s7, a4, 196 +8000c908: 93 05 09 00 mv a1, s2 +8000c90c: 13 85 09 00 mv a0, s3 +8000c910: ef c0 1f ad jal -13616 +8000c914: 13 09 05 00 mv s2, a0 +8000c918: 63 0c 05 04 beqz a0, 88 +8000c91c: 83 27 c4 ff lw a5, -4(s0) +8000c920: 13 07 85 ff addi a4, a0, -8 +8000c924: 93 f7 e7 ff andi a5, a5, -2 +8000c928: b3 87 fa 00 add a5, s5, a5 +8000c92c: 63 82 e7 30 beq a5, a4, 772 +8000c930: 13 06 ca ff addi a2, s4, -4 +8000c934: 93 07 40 02 addi a5, zero, 36 +8000c938: 63 e6 c7 30 bltu a5, a2, 780 +8000c93c: 13 07 30 01 addi a4, zero, 19 +8000c940: 83 26 04 00 lw a3, 0(s0) +8000c944: 63 6c c7 26 bltu a4, a2, 632 +8000c948: 93 07 05 00 mv a5, a0 +8000c94c: 13 07 04 00 mv a4, s0 +8000c950: 23 a0 d7 00 sw a3, 0(a5) +8000c954: 83 26 47 00 lw a3, 4(a4) +8000c958: 23 a2 d7 00 sw a3, 4(a5) +8000c95c: 03 27 87 00 lw a4, 8(a4) +8000c960: 23 a4 e7 00 sw a4, 8(a5) +8000c964: 93 05 04 00 mv a1, s0 +8000c968: 13 85 09 00 mv a0, s3 +8000c96c: ef 90 1f ba jal -25696 +8000c970: 13 85 09 00 mv a0, s3 +8000c974: ef d0 cf af jal -11524 +8000c978: 6f 00 c0 01 j 28 +8000c97c: 93 04 00 01 addi s1, zero, 16 +8000c980: 13 07 00 01 addi a4, zero, 16 +8000c984: e3 f8 24 f1 bgeu s1, s2, -240 +8000c988: 93 07 c0 00 addi a5, zero, 12 +8000c98c: 23 a0 f9 00 sw a5, 0(s3) +8000c990: 13 09 00 00 mv s2, zero +8000c994: 83 20 c1 02 lw ra, 44(sp) +8000c998: 03 24 81 02 lw s0, 40(sp) +8000c99c: 83 24 41 02 lw s1, 36(sp) +8000c9a0: 83 29 c1 01 lw s3, 28(sp) +8000c9a4: 03 2a 81 01 lw s4, 24(sp) +8000c9a8: 83 2a 41 01 lw s5, 20(sp) +8000c9ac: 03 2b 01 01 lw s6, 16(sp) +8000c9b0: 83 2b c1 00 lw s7, 12(sp) +8000c9b4: 03 2c 81 00 lw s8, 8(sp) +8000c9b8: 13 05 09 00 mv a0, s2 +8000c9bc: 03 29 01 02 lw s2, 32(sp) +8000c9c0: 13 01 01 03 addi sp, sp, 48 +8000c9c4: 67 80 00 00 ret +8000c9c8: 83 27 cc 00 lw a5, 12(s8) +8000c9cc: 03 27 8c 00 lw a4, 8(s8) +8000c9d0: 13 06 ca ff addi a2, s4, -4 +8000c9d4: 93 06 40 02 addi a3, zero, 36 +8000c9d8: 23 26 f7 00 sw a5, 12(a4) +8000c9dc: 23 a4 e7 00 sw a4, 8(a5) +8000c9e0: 13 09 8c 00 addi s2, s8, 8 +8000c9e4: 33 0b 7c 01 add s6, s8, s7 +8000c9e8: 63 e4 c6 2e bltu a3, a2, 744 +8000c9ec: 93 05 30 01 addi a1, zero, 19 +8000c9f0: 03 27 04 00 lw a4, 0(s0) +8000c9f4: 93 07 09 00 mv a5, s2 +8000c9f8: 63 f2 c5 02 bgeu a1, a2, 36 +8000c9fc: 23 24 ec 00 sw a4, 8(s8) +8000ca00: 03 27 44 00 lw a4, 4(s0) +8000ca04: 93 07 b0 01 addi a5, zero, 27 +8000ca08: 23 26 ec 00 sw a4, 12(s8) +8000ca0c: 63 e2 c7 30 bltu a5, a2, 772 +8000ca10: 03 27 84 00 lw a4, 8(s0) +8000ca14: 93 07 0c 01 addi a5, s8, 16 +8000ca18: 13 04 84 00 addi s0, s0, 8 +8000ca1c: 23 a0 e7 00 sw a4, 0(a5) +8000ca20: 03 27 44 00 lw a4, 4(s0) +8000ca24: 13 8a 0b 00 mv s4, s7 +8000ca28: 93 0a 0c 00 mv s5, s8 +8000ca2c: 23 a2 e7 00 sw a4, 4(a5) +8000ca30: 03 27 84 00 lw a4, 8(s0) +8000ca34: 13 04 09 00 mv s0, s2 +8000ca38: 23 a4 e7 00 sw a4, 8(a5) +8000ca3c: 83 a7 4a 00 lw a5, 4(s5) +8000ca40: 33 07 9a 40 sub a4, s4, s1 +8000ca44: 93 06 f0 00 addi a3, zero, 15 +8000ca48: 93 f7 17 00 andi a5, a5, 1 +8000ca4c: 63 ec e6 06 bltu a3, a4, 120 +8000ca50: b3 67 fa 00 or a5, s4, a5 +8000ca54: 23 a2 fa 00 sw a5, 4(s5) +8000ca58: 83 27 4b 00 lw a5, 4(s6) +8000ca5c: 93 e7 17 00 ori a5, a5, 1 +8000ca60: 23 22 fb 00 sw a5, 4(s6) +8000ca64: 13 85 09 00 mv a0, s3 +8000ca68: ef d0 8f a0 jal -11768 +8000ca6c: 13 09 04 00 mv s2, s0 +8000ca70: 6f f0 5f f2 j -220 +8000ca74: 93 f7 17 00 andi a5, a5, 1 +8000ca78: e3 98 07 e8 bnez a5, -368 +8000ca7c: 03 2c 84 ff lw s8, -8(s0) +8000ca80: 33 8c 8a 41 sub s8, s5, s8 +8000ca84: 83 27 4c 00 lw a5, 4(s8) +8000ca88: 93 f7 c7 ff andi a5, a5, -4 +8000ca8c: 6f f0 5f e7 j -396 +8000ca90: 03 24 81 02 lw s0, 40(sp) +8000ca94: 83 20 c1 02 lw ra, 44(sp) +8000ca98: 83 24 41 02 lw s1, 36(sp) +8000ca9c: 03 29 01 02 lw s2, 32(sp) +8000caa0: 83 29 c1 01 lw s3, 28(sp) +8000caa4: 03 2a 81 01 lw s4, 24(sp) +8000caa8: 83 2a 41 01 lw s5, 20(sp) +8000caac: 03 2b 01 01 lw s6, 16(sp) +8000cab0: 83 2b c1 00 lw s7, 12(sp) +8000cab4: 03 2c 81 00 lw s8, 8(sp) +8000cab8: 93 05 06 00 mv a1, a2 +8000cabc: 13 01 01 03 addi sp, sp, 48 +8000cac0: 6f c0 1f 92 j -14048 +8000cac4: b3 e7 97 00 or a5, a5, s1 +8000cac8: 23 a2 fa 00 sw a5, 4(s5) +8000cacc: b3 85 9a 00 add a1, s5, s1 +8000cad0: 13 67 17 00 ori a4, a4, 1 +8000cad4: 23 a2 e5 00 sw a4, 4(a1) +8000cad8: 83 27 4b 00 lw a5, 4(s6) +8000cadc: 93 85 85 00 addi a1, a1, 8 +8000cae0: 13 85 09 00 mv a0, s3 +8000cae4: 93 e7 17 00 ori a5, a5, 1 +8000cae8: 23 22 fb 00 sw a5, 4(s6) +8000caec: ef 90 1f a2 jal -26080 +8000caf0: 6f f0 5f f7 j -140 +8000caf4: 93 f6 c6 ff andi a3, a3, -4 +8000caf8: 33 06 da 00 add a2, s4, a3 +8000cafc: 93 85 04 01 addi a1, s1, 16 +8000cb00: 63 50 b6 0e bge a2, a1, 224 +8000cb04: 93 f7 17 00 andi a5, a5, 1 +8000cb08: e3 90 07 e0 bnez a5, -512 +8000cb0c: 03 2c 84 ff lw s8, -8(s0) +8000cb10: 33 8c 8a 41 sub s8, s5, s8 +8000cb14: 83 27 4c 00 lw a5, 4(s8) +8000cb18: 93 f7 c7 ff andi a5, a5, -4 +8000cb1c: b3 86 d7 00 add a3, a5, a3 +8000cb20: 33 8b 46 01 add s6, a3, s4 +8000cb24: e3 4e bb dc blt s6, a1, -548 +8000cb28: 83 27 cc 00 lw a5, 12(s8) +8000cb2c: 03 27 8c 00 lw a4, 8(s8) +8000cb30: 13 06 ca ff addi a2, s4, -4 +8000cb34: 93 06 40 02 addi a3, zero, 36 +8000cb38: 23 26 f7 00 sw a5, 12(a4) +8000cb3c: 23 a4 e7 00 sw a4, 8(a5) +8000cb40: 13 09 8c 00 addi s2, s8, 8 +8000cb44: 63 ee c6 20 bltu a3, a2, 540 +8000cb48: 93 05 30 01 addi a1, zero, 19 +8000cb4c: 03 27 04 00 lw a4, 0(s0) +8000cb50: 93 07 09 00 mv a5, s2 +8000cb54: 63 f2 c5 02 bgeu a1, a2, 36 +8000cb58: 23 24 ec 00 sw a4, 8(s8) +8000cb5c: 03 27 44 00 lw a4, 4(s0) +8000cb60: 93 07 b0 01 addi a5, zero, 27 +8000cb64: 23 26 ec 00 sw a4, 12(s8) +8000cb68: 63 e4 c7 20 bltu a5, a2, 520 +8000cb6c: 03 27 84 00 lw a4, 8(s0) +8000cb70: 93 07 0c 01 addi a5, s8, 16 +8000cb74: 13 04 84 00 addi s0, s0, 8 +8000cb78: 23 a0 e7 00 sw a4, 0(a5) +8000cb7c: 03 27 44 00 lw a4, 4(s0) +8000cb80: 23 a2 e7 00 sw a4, 4(a5) +8000cb84: 03 27 84 00 lw a4, 8(s0) +8000cb88: 23 a4 e7 00 sw a4, 8(a5) +8000cb8c: 33 07 9c 00 add a4, s8, s1 +8000cb90: b3 07 9b 40 sub a5, s6, s1 +8000cb94: 23 a4 eb 00 sw a4, 8(s7) +8000cb98: 93 e7 17 00 ori a5, a5, 1 +8000cb9c: 23 22 f7 00 sw a5, 4(a4) +8000cba0: 83 27 4c 00 lw a5, 4(s8) +8000cba4: 13 85 09 00 mv a0, s3 +8000cba8: 93 f7 17 00 andi a5, a5, 1 +8000cbac: b3 e4 97 00 or s1, a5, s1 +8000cbb0: 23 22 9c 00 sw s1, 4(s8) +8000cbb4: ef d0 cf 8b jal -12100 +8000cbb8: 6f f0 df dd j -548 +8000cbbc: 23 20 d5 00 sw a3, 0(a0) +8000cbc0: 83 26 44 00 lw a3, 4(s0) +8000cbc4: 13 07 b0 01 addi a4, zero, 27 +8000cbc8: 23 22 d5 00 sw a3, 4(a0) +8000cbcc: 63 60 c7 12 bltu a4, a2, 288 +8000cbd0: 83 26 84 00 lw a3, 8(s0) +8000cbd4: 13 07 84 00 addi a4, s0, 8 +8000cbd8: 93 07 85 00 addi a5, a0, 8 +8000cbdc: 6f f0 5f d7 j -652 +8000cbe0: b3 8a 9a 00 add s5, s5, s1 +8000cbe4: b3 07 96 40 sub a5, a2, s1 +8000cbe8: 23 a4 5b 01 sw s5, 8(s7) +8000cbec: 93 e7 17 00 ori a5, a5, 1 +8000cbf0: 23 a2 fa 00 sw a5, 4(s5) +8000cbf4: 83 27 c4 ff lw a5, -4(s0) +8000cbf8: 13 85 09 00 mv a0, s3 +8000cbfc: 13 09 04 00 mv s2, s0 +8000cc00: 93 f7 17 00 andi a5, a5, 1 +8000cc04: b3 e4 97 00 or s1, a5, s1 +8000cc08: 23 2e 94 fe sw s1, -4(s0) +8000cc0c: ef d0 4f 86 jal -12188 +8000cc10: 6f f0 5f d8 j -636 +8000cc14: 83 27 cb 00 lw a5, 12(s6) +8000cc18: 03 27 8b 00 lw a4, 8(s6) +8000cc1c: 13 0a 06 00 mv s4, a2 +8000cc20: 33 8b ca 00 add s6, s5, a2 +8000cc24: 23 26 f7 00 sw a5, 12(a4) +8000cc28: 23 a4 e7 00 sw a4, 8(a5) +8000cc2c: 6f f0 1f e1 j -496 +8000cc30: 83 27 c5 ff lw a5, -4(a0) +8000cc34: 93 f7 c7 ff andi a5, a5, -4 +8000cc38: 33 0a fa 00 add s4, s4, a5 +8000cc3c: 33 8b 4a 01 add s6, s5, s4 +8000cc40: 6f f0 df df j -516 +8000cc44: 93 05 04 00 mv a1, s0 +8000cc48: ef f0 1f ad jal -1328 +8000cc4c: 6f f0 9f d1 j -744 +8000cc50: 83 27 cb 00 lw a5, 12(s6) +8000cc54: 03 27 8b 00 lw a4, 8(s6) +8000cc58: 13 06 ca ff addi a2, s4, -4 +8000cc5c: 93 06 40 02 addi a3, zero, 36 +8000cc60: 23 26 f7 00 sw a5, 12(a4) +8000cc64: 23 a4 e7 00 sw a4, 8(a5) +8000cc68: 03 27 8c 00 lw a4, 8(s8) +8000cc6c: 83 27 cc 00 lw a5, 12(s8) +8000cc70: 13 09 8c 00 addi s2, s8, 8 +8000cc74: 33 0b 7c 01 add s6, s8, s7 +8000cc78: 23 26 f7 00 sw a5, 12(a4) +8000cc7c: 23 a4 e7 00 sw a4, 8(a5) +8000cc80: 63 e8 c6 04 bltu a3, a2, 80 +8000cc84: 93 06 30 01 addi a3, zero, 19 +8000cc88: 03 27 04 00 lw a4, 0(s0) +8000cc8c: 93 07 09 00 mv a5, s2 +8000cc90: e3 f6 c6 d8 bgeu a3, a2, -628 +8000cc94: 23 24 ec 00 sw a4, 8(s8) +8000cc98: 03 27 44 00 lw a4, 4(s0) +8000cc9c: 93 07 b0 01 addi a5, zero, 27 +8000cca0: 23 26 ec 00 sw a4, 12(s8) +8000cca4: 03 27 84 00 lw a4, 8(s0) +8000cca8: e3 f6 c7 d6 bgeu a5, a2, -660 +8000ccac: 23 28 ec 00 sw a4, 16(s8) +8000ccb0: 03 27 c4 00 lw a4, 12(s0) +8000ccb4: 93 07 40 02 addi a5, zero, 36 +8000ccb8: 23 2a ec 00 sw a4, 20(s8) +8000ccbc: 03 27 04 01 lw a4, 16(s0) +8000ccc0: 63 04 f6 06 beq a2, a5, 104 +8000ccc4: 93 07 8c 01 addi a5, s8, 24 +8000ccc8: 13 04 04 01 addi s0, s0, 16 +8000cccc: 6f f0 1f d5 j -688 +8000ccd0: 93 05 04 00 mv a1, s0 +8000ccd4: 13 05 09 00 mv a0, s2 +8000ccd8: ef f0 1f a4 jal -1472 +8000ccdc: 13 04 09 00 mv s0, s2 +8000cce0: 13 8a 0b 00 mv s4, s7 +8000cce4: 93 0a 0c 00 mv s5, s8 +8000cce8: 6f f0 5f d5 j -684 +8000ccec: 03 27 84 00 lw a4, 8(s0) +8000ccf0: 23 24 e5 00 sw a4, 8(a0) +8000ccf4: 03 27 c4 00 lw a4, 12(s0) +8000ccf8: 23 26 e5 00 sw a4, 12(a0) +8000ccfc: 83 26 04 01 lw a3, 16(s0) +8000cd00: 63 02 f6 04 beq a2, a5, 68 +8000cd04: 13 07 04 01 addi a4, s0, 16 +8000cd08: 93 07 05 01 addi a5, a0, 16 +8000cd0c: 6f f0 5f c4 j -956 +8000cd10: 83 27 84 00 lw a5, 8(s0) +8000cd14: 23 28 fc 00 sw a5, 16(s8) +8000cd18: 83 27 c4 00 lw a5, 12(s0) +8000cd1c: 23 2a fc 00 sw a5, 20(s8) +8000cd20: 03 27 04 01 lw a4, 16(s0) +8000cd24: e3 10 d6 fa bne a2, a3, -96 +8000cd28: 23 2c ec 00 sw a4, 24(s8) +8000cd2c: 03 27 44 01 lw a4, 20(s0) +8000cd30: 93 07 0c 02 addi a5, s8, 32 +8000cd34: 13 04 84 01 addi s0, s0, 24 +8000cd38: 23 2e ec 00 sw a4, 28(s8) +8000cd3c: 03 27 04 00 lw a4, 0(s0) +8000cd40: 6f f0 df cd j -804 +8000cd44: 23 28 d5 00 sw a3, 16(a0) +8000cd48: 83 26 44 01 lw a3, 20(s0) +8000cd4c: 13 07 84 01 addi a4, s0, 24 +8000cd50: 93 07 85 01 addi a5, a0, 24 +8000cd54: 23 2a d5 00 sw a3, 20(a0) +8000cd58: 83 26 84 01 lw a3, 24(s0) +8000cd5c: 6f f0 5f bf j -1036 +8000cd60: 93 05 04 00 mv a1, s0 +8000cd64: 13 05 09 00 mv a0, s2 +8000cd68: ef f0 1f 9b jal -1616 +8000cd6c: 6f f0 1f e2 j -480 +8000cd70: 83 27 84 00 lw a5, 8(s0) +8000cd74: 23 28 fc 00 sw a5, 16(s8) +8000cd78: 83 27 c4 00 lw a5, 12(s0) +8000cd7c: 23 2a fc 00 sw a5, 20(s8) +8000cd80: 03 27 04 01 lw a4, 16(s0) +8000cd84: 63 08 d6 00 beq a2, a3, 16 +8000cd88: 93 07 8c 01 addi a5, s8, 24 +8000cd8c: 13 04 04 01 addi s0, s0, 16 +8000cd90: 6f f0 9f de j -536 +8000cd94: 23 2c ec 00 sw a4, 24(s8) +8000cd98: 03 27 44 01 lw a4, 20(s0) +8000cd9c: 93 07 0c 02 addi a5, s8, 32 +8000cda0: 13 04 84 01 addi s0, s0, 24 +8000cda4: 23 2e ec 00 sw a4, 28(s8) +8000cda8: 03 27 04 00 lw a4, 0(s0) +8000cdac: 6f f0 df dc j -564 + +8000cdb0 strcmp: +8000cdb0: 33 67 b5 00 or a4, a0, a1 +8000cdb4: 93 03 f0 ff addi t2, zero, -1 +8000cdb8: 13 77 37 00 andi a4, a4, 3 +8000cdbc: 63 10 07 10 bnez a4, 256 +8000cdc0: b7 87 7f 7f lui a5, 522232 +8000cdc4: 93 87 f7 f7 addi a5, a5, -129 +8000cdc8: 03 26 05 00 lw a2, 0(a0) +8000cdcc: 83 a6 05 00 lw a3, 0(a1) +8000cdd0: b3 72 f6 00 and t0, a2, a5 +8000cdd4: 33 63 f6 00 or t1, a2, a5 +8000cdd8: b3 82 f2 00 add t0, t0, a5 +8000cddc: b3 e2 62 00 or t0, t0, t1 +8000cde0: 63 92 72 10 bne t0, t2, 260 +8000cde4: 63 16 d6 08 bne a2, a3, 140 +8000cde8: 03 26 45 00 lw a2, 4(a0) +8000cdec: 83 a6 45 00 lw a3, 4(a1) +8000cdf0: b3 72 f6 00 and t0, a2, a5 +8000cdf4: 33 63 f6 00 or t1, a2, a5 +8000cdf8: b3 82 f2 00 add t0, t0, a5 +8000cdfc: b3 e2 62 00 or t0, t0, t1 +8000ce00: 63 9e 72 0c bne t0, t2, 220 +8000ce04: 63 16 d6 06 bne a2, a3, 108 +8000ce08: 03 26 85 00 lw a2, 8(a0) +8000ce0c: 83 a6 85 00 lw a3, 8(a1) +8000ce10: b3 72 f6 00 and t0, a2, a5 +8000ce14: 33 63 f6 00 or t1, a2, a5 +8000ce18: b3 82 f2 00 add t0, t0, a5 +8000ce1c: b3 e2 62 00 or t0, t0, t1 +8000ce20: 63 98 72 0c bne t0, t2, 208 +8000ce24: 63 16 d6 04 bne a2, a3, 76 +8000ce28: 03 26 c5 00 lw a2, 12(a0) +8000ce2c: 83 a6 c5 00 lw a3, 12(a1) +8000ce30: b3 72 f6 00 and t0, a2, a5 +8000ce34: 33 63 f6 00 or t1, a2, a5 +8000ce38: b3 82 f2 00 add t0, t0, a5 +8000ce3c: b3 e2 62 00 or t0, t0, t1 +8000ce40: 63 92 72 0c bne t0, t2, 196 +8000ce44: 63 16 d6 02 bne a2, a3, 44 +8000ce48: 03 26 05 01 lw a2, 16(a0) +8000ce4c: 83 a6 05 01 lw a3, 16(a1) +8000ce50: b3 72 f6 00 and t0, a2, a5 +8000ce54: 33 63 f6 00 or t1, a2, a5 +8000ce58: b3 82 f2 00 add t0, t0, a5 +8000ce5c: b3 e2 62 00 or t0, t0, t1 +8000ce60: 63 9c 72 0a bne t0, t2, 184 +8000ce64: 13 05 45 01 addi a0, a0, 20 +8000ce68: 93 85 45 01 addi a1, a1, 20 +8000ce6c: e3 0e d6 f4 beq a2, a3, -164 +8000ce70: 13 17 06 01 slli a4, a2, 16 +8000ce74: 93 97 06 01 slli a5, a3, 16 +8000ce78: 63 1e f7 00 bne a4, a5, 28 +8000ce7c: 13 57 06 01 srli a4, a2, 16 +8000ce80: 93 d7 06 01 srli a5, a3, 16 +8000ce84: 33 05 f7 40 sub a0, a4, a5 +8000ce88: 93 75 f5 0f andi a1, a0, 255 +8000ce8c: 63 90 05 02 bnez a1, 32 +8000ce90: 67 80 00 00 ret +8000ce94: 13 57 07 01 srli a4, a4, 16 +8000ce98: 93 d7 07 01 srli a5, a5, 16 +8000ce9c: 33 05 f7 40 sub a0, a4, a5 +8000cea0: 93 75 f5 0f andi a1, a0, 255 +8000cea4: 63 94 05 00 bnez a1, 8 +8000cea8: 67 80 00 00 ret +8000ceac: 13 77 f7 0f andi a4, a4, 255 +8000ceb0: 93 f7 f7 0f andi a5, a5, 255 +8000ceb4: 33 05 f7 40 sub a0, a4, a5 +8000ceb8: 67 80 00 00 ret +8000cebc: 03 46 05 00 lbu a2, 0(a0) +8000cec0: 83 c6 05 00 lbu a3, 0(a1) +8000cec4: 13 05 15 00 addi a0, a0, 1 +8000cec8: 93 85 15 00 addi a1, a1, 1 +8000cecc: 63 14 d6 00 bne a2, a3, 8 +8000ced0: e3 16 06 fe bnez a2, -20 +8000ced4: 33 05 d6 40 sub a0, a2, a3 +8000ced8: 67 80 00 00 ret +8000cedc: 13 05 45 00 addi a0, a0, 4 +8000cee0: 93 85 45 00 addi a1, a1, 4 +8000cee4: e3 1c d6 fc bne a2, a3, -40 +8000cee8: 13 05 00 00 mv a0, zero +8000ceec: 67 80 00 00 ret +8000cef0: 13 05 85 00 addi a0, a0, 8 +8000cef4: 93 85 85 00 addi a1, a1, 8 +8000cef8: e3 12 d6 fc bne a2, a3, -60 +8000cefc: 13 05 00 00 mv a0, zero +8000cf00: 67 80 00 00 ret +8000cf04: 13 05 c5 00 addi a0, a0, 12 +8000cf08: 93 85 c5 00 addi a1, a1, 12 +8000cf0c: e3 18 d6 fa bne a2, a3, -80 +8000cf10: 13 05 00 00 mv a0, zero +8000cf14: 67 80 00 00 ret +8000cf18: 13 05 05 01 addi a0, a0, 16 +8000cf1c: 93 85 05 01 addi a1, a1, 16 +8000cf20: e3 1e d6 f8 bne a2, a3, -100 +8000cf24: 13 05 00 00 mv a0, zero +8000cf28: 67 80 00 00 ret + +8000cf2c __sprint_r.part.0: +8000cf2c: 83 a7 45 06 lw a5, 100(a1) +8000cf30: 13 01 01 fd addi sp, sp, -48 +8000cf34: 23 28 61 01 sw s6, 16(sp) +8000cf38: 23 26 11 02 sw ra, 44(sp) +8000cf3c: 23 24 81 02 sw s0, 40(sp) +8000cf40: 23 22 91 02 sw s1, 36(sp) +8000cf44: 23 20 21 03 sw s2, 32(sp) +8000cf48: 23 2e 31 01 sw s3, 28(sp) +8000cf4c: 23 2c 41 01 sw s4, 24(sp) +8000cf50: 23 2a 51 01 sw s5, 20(sp) +8000cf54: 23 26 71 01 sw s7, 12(sp) +8000cf58: 23 24 81 01 sw s8, 8(sp) +8000cf5c: 13 97 27 01 slli a4, a5, 18 +8000cf60: 13 0b 06 00 mv s6, a2 +8000cf64: 63 58 07 0a bgez a4, 176 +8000cf68: 83 27 86 00 lw a5, 8(a2) +8000cf6c: 83 2b 06 00 lw s7, 0(a2) +8000cf70: 13 89 05 00 mv s2, a1 +8000cf74: 93 09 05 00 mv s3, a0 +8000cf78: 93 0a f0 ff addi s5, zero, -1 +8000cf7c: 63 88 07 08 beqz a5, 144 +8000cf80: 03 ac 4b 00 lw s8, 4(s7) +8000cf84: 03 a4 0b 00 lw s0, 0(s7) +8000cf88: 13 5a 2c 00 srli s4, s8, 2 +8000cf8c: 63 06 0a 06 beqz s4, 108 +8000cf90: 93 04 00 00 mv s1, zero +8000cf94: 6f 00 c0 00 j 12 +8000cf98: 13 04 44 00 addi s0, s0, 4 +8000cf9c: 63 0c 9a 04 beq s4, s1, 88 +8000cfa0: 83 25 04 00 lw a1, 0(s0) +8000cfa4: 13 06 09 00 mv a2, s2 +8000cfa8: 13 85 09 00 mv a0, s3 +8000cfac: ef 10 50 49 jal 7316 +8000cfb0: 93 84 14 00 addi s1, s1, 1 +8000cfb4: e3 12 55 ff bne a0, s5, -28 +8000cfb8: 13 05 f0 ff addi a0, zero, -1 +8000cfbc: 83 20 c1 02 lw ra, 44(sp) +8000cfc0: 03 24 81 02 lw s0, 40(sp) +8000cfc4: 23 24 0b 00 sw zero, 8(s6) +8000cfc8: 23 22 0b 00 sw zero, 4(s6) +8000cfcc: 83 24 41 02 lw s1, 36(sp) +8000cfd0: 03 29 01 02 lw s2, 32(sp) +8000cfd4: 83 29 c1 01 lw s3, 28(sp) +8000cfd8: 03 2a 81 01 lw s4, 24(sp) +8000cfdc: 83 2a 41 01 lw s5, 20(sp) +8000cfe0: 03 2b 01 01 lw s6, 16(sp) +8000cfe4: 83 2b c1 00 lw s7, 12(sp) +8000cfe8: 03 2c 81 00 lw s8, 8(sp) +8000cfec: 13 01 01 03 addi sp, sp, 48 +8000cff0: 67 80 00 00 ret +8000cff4: 83 27 8b 00 lw a5, 8(s6) +8000cff8: 13 7c cc ff andi s8, s8, -4 +8000cffc: b3 87 87 41 sub a5, a5, s8 +8000d000: 23 24 fb 00 sw a5, 8(s6) +8000d004: 93 8b 8b 00 addi s7, s7, 8 +8000d008: e3 9c 07 f6 bnez a5, -136 +8000d00c: 13 05 00 00 mv a0, zero +8000d010: 6f f0 df fa j -84 +8000d014: ef 10 90 4d jal 7384 +8000d018: 6f f0 5f fa j -92 + +8000d01c __sprint_r: +8000d01c: 03 27 86 00 lw a4, 8(a2) +8000d020: 63 04 07 00 beqz a4, 8 +8000d024: 6f f0 9f f0 j -248 +8000d028: 23 22 06 00 sw zero, 4(a2) +8000d02c: 13 05 00 00 mv a0, zero +8000d030: 67 80 00 00 ret + +8000d034 _vfiprintf_r: +8000d034: 13 01 01 ed addi sp, sp, -304 +8000d038: 23 2e 31 11 sw s3, 284(sp) +8000d03c: 23 2a 51 11 sw s5, 276(sp) +8000d040: 23 20 a1 11 sw s10, 256(sp) +8000d044: 23 26 11 12 sw ra, 300(sp) +8000d048: 23 24 81 12 sw s0, 296(sp) +8000d04c: 23 22 91 12 sw s1, 292(sp) +8000d050: 23 20 21 13 sw s2, 288(sp) +8000d054: 23 2c 41 11 sw s4, 280(sp) +8000d058: 23 28 61 11 sw s6, 272(sp) +8000d05c: 23 26 71 11 sw s7, 268(sp) +8000d060: 23 24 81 11 sw s8, 264(sp) +8000d064: 23 22 91 11 sw s9, 260(sp) +8000d068: 23 2e b1 0f sw s11, 252(sp) +8000d06c: 23 26 d1 00 sw a3, 12(sp) +8000d070: 93 0a 05 00 mv s5, a0 +8000d074: 93 89 05 00 mv s3, a1 +8000d078: 13 0d 06 00 mv s10, a2 +8000d07c: 63 06 05 00 beqz a0, 12 +8000d080: 83 27 85 03 lw a5, 56(a0) +8000d084: 63 88 07 6a beqz a5, 1712 +8000d088: 03 97 c9 00 lh a4, 12(s3) +8000d08c: 93 17 07 01 slli a5, a4, 16 +8000d090: 93 16 27 01 slli a3, a4, 18 +8000d094: 93 d7 07 01 srli a5, a5, 16 +8000d098: 63 ca 06 02 bltz a3, 52 +8000d09c: b7 27 00 00 lui a5, 2 +8000d0a0: 83 a6 49 06 lw a3, 100(s3) +8000d0a4: b3 67 f7 00 or a5, a4, a5 +8000d0a8: 93 97 07 01 slli a5, a5, 16 +8000d0ac: 37 e7 ff ff lui a4, 1048574 +8000d0b0: 93 d7 07 41 srai a5, a5, 16 +8000d0b4: 13 07 f7 ff addi a4, a4, -1 +8000d0b8: 33 f7 e6 00 and a4, a3, a4 +8000d0bc: 23 96 f9 00 sh a5, 12(s3) +8000d0c0: 93 97 07 01 slli a5, a5, 16 +8000d0c4: 23 a2 e9 06 sw a4, 100(s3) +8000d0c8: 93 d7 07 01 srli a5, a5, 16 +8000d0cc: 13 f7 87 00 andi a4, a5, 8 +8000d0d0: 63 04 07 3e beqz a4, 1000 +8000d0d4: 03 a7 09 01 lw a4, 16(s3) +8000d0d8: 63 00 07 3e beqz a4, 992 +8000d0dc: 93 f7 a7 01 andi a5, a5, 26 +8000d0e0: 13 07 a0 00 addi a4, zero, 10 +8000d0e4: 63 8a e7 3e beq a5, a4, 1012 +8000d0e8: b7 67 01 80 lui a5, 524310 +8000d0ec: 93 04 c1 04 addi s1, sp, 76 +8000d0f0: 93 87 47 d5 addi a5, a5, -684 +8000d0f4: b7 6b 01 80 lui s7, 524310 +8000d0f8: 37 69 01 80 lui s2, 524310 +8000d0fc: 23 20 91 04 sw s1, 64(sp) +8000d100: 23 24 01 04 sw zero, 72(sp) +8000d104: 23 22 01 04 sw zero, 68(sp) +8000d108: 13 87 04 00 mv a4, s1 +8000d10c: 23 28 01 00 sw zero, 16(sp) +8000d110: 23 22 01 02 sw zero, 36(sp) +8000d114: 23 24 01 02 sw zero, 40(sp) +8000d118: 23 26 01 02 sw zero, 44(sp) +8000d11c: 23 24 01 00 sw zero, 8(sp) +8000d120: 23 2a f1 00 sw a5, 20(sp) +8000d124: 93 8b 0b ec addi s7, s7, -320 +8000d128: 13 09 09 ed addi s2, s2, -304 +8000d12c: 83 47 0d 00 lbu a5, 0(s10) +8000d130: 63 8e 07 24 beqz a5, 604 +8000d134: 13 04 0d 00 mv s0, s10 +8000d138: 93 06 50 02 addi a3, zero, 37 +8000d13c: 63 86 d7 42 beq a5, a3, 1068 +8000d140: 83 47 14 00 lbu a5, 1(s0) +8000d144: 13 04 14 00 addi s0, s0, 1 +8000d148: e3 9a 07 fe bnez a5, -12 +8000d14c: 33 0a a4 41 sub s4, s0, s10 +8000d150: 63 0e a4 23 beq s0, s10, 572 +8000d154: 83 26 81 04 lw a3, 72(sp) +8000d158: 83 27 41 04 lw a5, 68(sp) +8000d15c: 23 20 a7 01 sw s10, 0(a4) +8000d160: b3 06 da 00 add a3, s4, a3 +8000d164: 93 87 17 00 addi a5, a5, 1 +8000d168: 23 22 47 01 sw s4, 4(a4) +8000d16c: 23 24 d1 04 sw a3, 72(sp) +8000d170: 23 22 f1 04 sw a5, 68(sp) +8000d174: 13 06 70 00 addi a2, zero, 7 +8000d178: 13 07 87 00 addi a4, a4, 8 +8000d17c: 63 50 f6 02 bge a2, a5, 32 +8000d180: e3 84 06 36 beqz a3, 2920 +8000d184: 13 06 01 04 addi a2, sp, 64 +8000d188: 93 85 09 00 mv a1, s3 +8000d18c: 13 85 0a 00 mv a0, s5 +8000d190: ef f0 df d9 jal -612 +8000d194: 63 10 05 20 bnez a0, 512 +8000d198: 13 87 04 00 mv a4, s1 +8000d19c: 83 26 81 00 lw a3, 8(sp) +8000d1a0: 83 47 04 00 lbu a5, 0(s0) +8000d1a4: b3 86 46 01 add a3, a3, s4 +8000d1a8: 23 24 d1 00 sw a3, 8(sp) +8000d1ac: 63 80 07 1e beqz a5, 480 +8000d1b0: 83 46 14 00 lbu a3, 1(s0) +8000d1b4: 13 0d 14 00 addi s10, s0, 1 +8000d1b8: a3 0d 01 02 sb zero, 59(sp) +8000d1bc: 93 0c f0 ff addi s9, zero, -1 +8000d1c0: 13 04 00 00 mv s0, zero +8000d1c4: 93 0d 00 00 mv s11, zero +8000d1c8: 13 0a a0 05 addi s4, zero, 90 +8000d1cc: 13 0c 90 00 addi s8, zero, 9 +8000d1d0: 13 0b a0 02 addi s6, zero, 42 +8000d1d4: 13 0d 1d 00 addi s10, s10, 1 +8000d1d8: 93 87 06 fe addi a5, a3, -32 +8000d1dc: 63 64 fa 04 bltu s4, a5, 72 +8000d1e0: 03 26 41 01 lw a2, 20(sp) +8000d1e4: 93 97 27 00 slli a5, a5, 2 +8000d1e8: b3 87 c7 00 add a5, a5, a2 +8000d1ec: 83 a7 07 00 lw a5, 0(a5) +8000d1f0: 67 80 07 00 jr a5 +8000d1f4: 13 04 00 00 mv s0, zero +8000d1f8: 93 87 06 fd addi a5, a3, -48 +8000d1fc: 83 46 0d 00 lbu a3, 0(s10) +8000d200: 93 15 24 00 slli a1, s0, 2 +8000d204: 33 84 85 00 add s0, a1, s0 +8000d208: 13 14 14 00 slli s0, s0, 1 +8000d20c: 33 84 87 00 add s0, a5, s0 +8000d210: 93 87 06 fd addi a5, a3, -48 +8000d214: 13 0d 1d 00 addi s10, s10, 1 +8000d218: e3 72 fc fe bgeu s8, a5, -28 +8000d21c: 93 87 06 fe addi a5, a3, -32 +8000d220: e3 70 fa fc bgeu s4, a5, -64 +8000d224: 63 84 06 16 beqz a3, 360 +8000d228: 23 06 d1 08 sb a3, 140(sp) +8000d22c: a3 0d 01 02 sb zero, 59(sp) +8000d230: 13 0a 10 00 addi s4, zero, 1 +8000d234: 13 0c 10 00 addi s8, zero, 1 +8000d238: 13 0b c1 08 addi s6, sp, 140 +8000d23c: 93 0c 00 00 mv s9, zero +8000d240: 93 ff 2d 00 andi t6, s11, 2 +8000d244: 63 84 0f 00 beqz t6, 8 +8000d248: 13 0a 2a 00 addi s4, s4, 2 +8000d24c: 83 26 41 04 lw a3, 68(sp) +8000d250: 13 ff 4d 08 andi t5, s11, 132 +8000d254: 83 27 81 04 lw a5, 72(sp) +8000d258: 13 86 16 00 addi a2, a3, 1 +8000d25c: 93 05 06 00 mv a1, a2 +8000d260: 63 16 0f 00 bnez t5, 12 +8000d264: 33 08 44 41 sub a6, s0, s4 +8000d268: e3 44 00 17 bgtz a6, 2408 +8000d26c: 03 45 b1 03 lbu a0, 59(sp) +8000d270: 13 06 87 00 addi a2, a4, 8 +8000d274: 63 0c 05 02 beqz a0, 56 +8000d278: 93 06 b1 03 addi a3, sp, 59 +8000d27c: 23 20 d7 00 sw a3, 0(a4) +8000d280: 93 87 17 00 addi a5, a5, 1 +8000d284: 93 06 10 00 addi a3, zero, 1 +8000d288: 23 22 d7 00 sw a3, 4(a4) +8000d28c: 23 24 f1 04 sw a5, 72(sp) +8000d290: 23 22 b1 04 sw a1, 68(sp) +8000d294: 13 07 70 00 addi a4, zero, 7 +8000d298: e3 42 b7 0c blt a4, a1, 2244 +8000d29c: 93 86 05 00 mv a3, a1 +8000d2a0: 13 07 06 00 mv a4, a2 +8000d2a4: 93 85 15 00 addi a1, a1, 1 +8000d2a8: 13 06 86 00 addi a2, a2, 8 +8000d2ac: 63 8e 0f 04 beqz t6, 92 +8000d2b0: 93 06 c1 03 addi a3, sp, 60 +8000d2b4: 23 20 d7 00 sw a3, 0(a4) +8000d2b8: 93 87 27 00 addi a5, a5, 2 +8000d2bc: 93 06 20 00 addi a3, zero, 2 +8000d2c0: 23 22 d7 00 sw a3, 4(a4) +8000d2c4: 23 24 f1 04 sw a5, 72(sp) +8000d2c8: 23 22 b1 04 sw a1, 68(sp) +8000d2cc: 13 07 70 00 addi a4, zero, 7 +8000d2d0: e3 52 b7 0e bge a4, a1, 2276 +8000d2d4: e3 84 07 26 beqz a5, 2664 +8000d2d8: 13 06 01 04 addi a2, sp, 64 +8000d2dc: 93 85 09 00 mv a1, s3 +8000d2e0: 13 85 0a 00 mv a0, s5 +8000d2e4: 23 2c e1 01 sw t5, 24(sp) +8000d2e8: ef f0 5f c4 jal -956 +8000d2ec: 63 14 05 0a bnez a0, 168 +8000d2f0: 83 26 41 04 lw a3, 68(sp) +8000d2f4: 83 27 81 04 lw a5, 72(sp) +8000d2f8: 03 2f 81 01 lw t5, 24(sp) +8000d2fc: 13 06 41 05 addi a2, sp, 84 +8000d300: 93 85 16 00 addi a1, a3, 1 +8000d304: 13 87 04 00 mv a4, s1 +8000d308: 13 05 00 08 addi a0, zero, 128 +8000d30c: 63 06 af 68 beq t5, a0, 1676 +8000d310: b3 8c 8c 41 sub s9, s9, s8 +8000d314: 63 42 90 77 bgtz s9, 1892 +8000d318: b3 07 fc 00 add a5, s8, a5 +8000d31c: 23 20 67 01 sw s6, 0(a4) +8000d320: 23 22 87 01 sw s8, 4(a4) +8000d324: 23 24 f1 04 sw a5, 72(sp) +8000d328: 23 22 b1 04 sw a1, 68(sp) +8000d32c: 13 07 70 00 addi a4, zero, 7 +8000d330: 63 52 b7 02 bge a4, a1, 36 +8000d334: 63 82 07 24 beqz a5, 580 +8000d338: 13 06 01 04 addi a2, sp, 64 +8000d33c: 93 85 09 00 mv a1, s3 +8000d340: 13 85 0a 00 mv a0, s5 +8000d344: ef f0 9f be jal -1048 +8000d348: 63 16 05 04 bnez a0, 76 +8000d34c: 83 27 81 04 lw a5, 72(sp) +8000d350: 13 86 04 00 mv a2, s1 +8000d354: 93 fe 4d 00 andi t4, s11, 4 +8000d358: 63 86 0e 00 beqz t4, 12 +8000d35c: 33 0c 44 41 sub s8, s0, s4 +8000d360: 63 48 80 23 bgtz s8, 560 +8000d364: 63 54 44 01 bge s0, s4, 8 +8000d368: 13 04 0a 00 mv s0, s4 +8000d36c: 03 27 81 00 lw a4, 8(sp) +8000d370: 33 07 87 00 add a4, a4, s0 +8000d374: 23 24 e1 00 sw a4, 8(sp) +8000d378: 63 9e 07 7a bnez a5, 1980 +8000d37c: 83 47 0d 00 lbu a5, 0(s10) +8000d380: 23 22 01 04 sw zero, 68(sp) +8000d384: 13 87 04 00 mv a4, s1 +8000d388: e3 96 07 da bnez a5, -596 +8000d38c: 83 27 81 04 lw a5, 72(sp) +8000d390: e3 96 07 62 bnez a5, 3628 +8000d394: 83 d7 c9 00 lhu a5, 12(s3) +8000d398: 93 f7 07 04 andi a5, a5, 64 +8000d39c: e3 9e 07 64 bnez a5, 3676 +8000d3a0: 83 20 c1 12 lw ra, 300(sp) +8000d3a4: 03 24 81 12 lw s0, 296(sp) +8000d3a8: 03 25 81 00 lw a0, 8(sp) +8000d3ac: 83 24 41 12 lw s1, 292(sp) +8000d3b0: 03 29 01 12 lw s2, 288(sp) +8000d3b4: 83 29 c1 11 lw s3, 284(sp) +8000d3b8: 03 2a 81 11 lw s4, 280(sp) +8000d3bc: 83 2a 41 11 lw s5, 276(sp) +8000d3c0: 03 2b 01 11 lw s6, 272(sp) +8000d3c4: 83 2b c1 10 lw s7, 268(sp) +8000d3c8: 03 2c 81 10 lw s8, 264(sp) +8000d3cc: 83 2c 41 10 lw s9, 260(sp) +8000d3d0: 03 2d 01 10 lw s10, 256(sp) +8000d3d4: 83 2d c1 0f lw s11, 252(sp) +8000d3d8: 13 01 01 13 addi sp, sp, 304 +8000d3dc: 67 80 00 00 ret +8000d3e0: 13 85 0a 00 mv a0, s5 +8000d3e4: 23 2c e1 00 sw a4, 24(sp) +8000d3e8: ef b0 1f fe jal -16416 +8000d3ec: 83 27 45 00 lw a5, 4(a0) +8000d3f0: 13 85 07 00 mv a0, a5 +8000d3f4: 23 26 f1 02 sw a5, 44(sp) +8000d3f8: ef d0 5f c7 jal -9100 +8000d3fc: 93 07 05 00 mv a5, a0 +8000d400: 13 85 0a 00 mv a0, s5 +8000d404: 23 24 f1 02 sw a5, 40(sp) +8000d408: ef b0 1f fc jal -16448 +8000d40c: 03 27 85 00 lw a4, 8(a0) +8000d410: 83 27 81 02 lw a5, 40(sp) +8000d414: 23 22 e1 02 sw a4, 36(sp) +8000d418: 03 27 81 01 lw a4, 24(sp) +8000d41c: e3 98 07 2a bnez a5, 2736 +8000d420: 83 46 0d 00 lbu a3, 0(s10) +8000d424: 6f f0 1f db j -592 +8000d428: 83 46 0d 00 lbu a3, 0(s10) +8000d42c: 93 ed 0d 02 ori s11, s11, 32 +8000d430: 6f f0 5f da j -604 +8000d434: 93 ed 0d 01 ori s11, s11, 16 +8000d438: 93 f7 0d 02 andi a5, s11, 32 +8000d43c: 63 8a 07 22 beqz a5, 564 +8000d440: 83 27 c1 00 lw a5, 12(sp) +8000d444: 13 8b 77 00 addi s6, a5, 7 +8000d448: 13 7b 8b ff andi s6, s6, -8 +8000d44c: 83 26 4b 00 lw a3, 4(s6) +8000d450: 03 2c 0b 00 lw s8, 0(s6) +8000d454: 93 07 8b 00 addi a5, s6, 8 +8000d458: 23 26 f1 00 sw a5, 12(sp) +8000d45c: 13 88 06 00 mv a6, a3 +8000d460: 63 c0 06 24 bltz a3, 576 +8000d464: 93 06 f0 ff addi a3, zero, -1 +8000d468: 13 8a 0d 00 mv s4, s11 +8000d46c: 63 88 dc 00 beq s9, a3, 16 +8000d470: b3 66 0c 01 or a3, s8, a6 +8000d474: 13 fa fd f7 andi s4, s11, -129 +8000d478: e3 8e 06 06 beqz a3, 2172 +8000d47c: e3 18 08 12 bnez a6, 2352 +8000d480: 93 06 90 00 addi a3, zero, 9 +8000d484: e3 e4 86 13 bltu a3, s8, 2344 +8000d488: 93 07 0c 03 addi a5, s8, 48 +8000d48c: a3 07 f1 0e sb a5, 239(sp) +8000d490: 93 0d 0a 00 mv s11, s4 +8000d494: 13 0c 10 00 addi s8, zero, 1 +8000d498: 13 0b f1 0e addi s6, sp, 239 +8000d49c: 13 8a 0c 00 mv s4, s9 +8000d4a0: 63 d4 8c 01 bge s9, s8, 8 +8000d4a4: 13 0a 0c 00 mv s4, s8 +8000d4a8: 83 47 b1 03 lbu a5, 59(sp) +8000d4ac: b3 37 f0 00 snez a5, a5 +8000d4b0: 33 0a fa 00 add s4, s4, a5 +8000d4b4: 6f f0 df d8 j -628 +8000d4b8: 93 85 09 00 mv a1, s3 +8000d4bc: 13 85 0a 00 mv a0, s5 +8000d4c0: ef 00 d0 68 jal 3724 +8000d4c4: e3 1a 05 52 bnez a0, 3380 +8000d4c8: 83 d7 c9 00 lhu a5, 12(s3) +8000d4cc: 13 07 a0 00 addi a4, zero, 10 +8000d4d0: 93 f7 a7 01 andi a5, a5, 26 +8000d4d4: e3 9a e7 c0 bne a5, a4, -1004 +8000d4d8: 83 97 e9 00 lh a5, 14(s3) +8000d4dc: e3 c6 07 c0 bltz a5, -1012 +8000d4e0: 83 26 c1 00 lw a3, 12(sp) +8000d4e4: 13 06 0d 00 mv a2, s10 +8000d4e8: 93 85 09 00 mv a1, s3 +8000d4ec: 13 85 0a 00 mv a0, s5 +8000d4f0: ef 00 10 56 jal 3424 +8000d4f4: 23 24 a1 00 sw a0, 8(sp) +8000d4f8: 6f f0 9f ea j -344 +8000d4fc: 93 ed 0d 01 ori s11, s11, 16 +8000d500: 93 f7 0d 02 andi a5, s11, 32 +8000d504: 63 80 07 14 beqz a5, 320 +8000d508: 83 27 c1 00 lw a5, 12(sp) +8000d50c: 13 8b 77 00 addi s6, a5, 7 +8000d510: 13 7b 8b ff andi s6, s6, -8 +8000d514: 03 2c 0b 00 lw s8, 0(s6) +8000d518: 03 28 4b 00 lw a6, 4(s6) +8000d51c: 93 07 8b 00 addi a5, s6, 8 +8000d520: 23 26 f1 00 sw a5, 12(sp) +8000d524: 13 fa fd bf andi s4, s11, -1025 +8000d528: 93 06 00 00 mv a3, zero +8000d52c: a3 0d 01 02 sb zero, 59(sp) +8000d530: 13 06 f0 ff addi a2, zero, -1 +8000d534: 63 8a cc 18 beq s9, a2, 404 +8000d538: 33 66 0c 01 or a2, s8, a6 +8000d53c: 93 7d fa f7 andi s11, s4, -129 +8000d540: 63 14 06 68 bnez a2, 1672 +8000d544: 63 96 0c 3e bnez s9, 1004 +8000d548: 63 9a 06 7a bnez a3, 1972 +8000d54c: 13 7c 1a 00 andi s8, s4, 1 +8000d550: 13 0b 01 0f addi s6, sp, 240 +8000d554: e3 04 0c f4 beqz s8, -184 +8000d558: 93 07 00 03 addi a5, zero, 48 +8000d55c: a3 07 f1 0e sb a5, 239(sp) +8000d560: 13 0b f1 0e addi s6, sp, 239 +8000d564: 6f f0 9f f3 j -200 +8000d568: 33 0a a4 41 sub s4, s0, s10 +8000d56c: e3 14 a4 bf bne s0, s10, -1048 +8000d570: 83 47 04 00 lbu a5, 0(s0) +8000d574: 6f f0 9f c3 j -968 +8000d578: 23 22 01 04 sw zero, 68(sp) +8000d57c: 93 fe 4d 00 andi t4, s11, 4 +8000d580: 63 80 0e 72 beqz t4, 1824 +8000d584: 33 0c 44 41 sub s8, s0, s4 +8000d588: 63 5c 80 71 blez s8, 1816 +8000d58c: 13 86 04 00 mv a2, s1 +8000d590: 13 07 00 01 addi a4, zero, 16 +8000d594: 83 26 41 04 lw a3, 68(sp) +8000d598: e3 58 87 45 bge a4, s8, 3152 +8000d59c: 93 0c 00 01 addi s9, zero, 16 +8000d5a0: 13 0b 70 00 addi s6, zero, 7 +8000d5a4: 6f 00 80 01 j 24 +8000d5a8: 93 85 26 00 addi a1, a3, 2 +8000d5ac: 13 06 86 00 addi a2, a2, 8 +8000d5b0: 93 06 07 00 mv a3, a4 +8000d5b4: 13 0c 0c ff addi s8, s8, -16 +8000d5b8: 63 d8 8c 05 bge s9, s8, 80 +8000d5bc: 93 87 07 01 addi a5, a5, 16 +8000d5c0: 13 87 16 00 addi a4, a3, 1 +8000d5c4: 23 20 76 01 sw s7, 0(a2) +8000d5c8: 23 22 96 01 sw s9, 4(a2) +8000d5cc: 23 24 f1 04 sw a5, 72(sp) +8000d5d0: 23 22 e1 04 sw a4, 68(sp) +8000d5d4: e3 5a eb fc bge s6, a4, -44 +8000d5d8: 63 88 07 3a beqz a5, 944 +8000d5dc: 13 06 01 04 addi a2, sp, 64 +8000d5e0: 93 85 09 00 mv a1, s3 +8000d5e4: 13 85 0a 00 mv a0, s5 +8000d5e8: ef f0 5f 94 jal -1724 +8000d5ec: e3 14 05 da bnez a0, -600 +8000d5f0: 83 26 41 04 lw a3, 68(sp) +8000d5f4: 13 0c 0c ff addi s8, s8, -16 +8000d5f8: 83 27 81 04 lw a5, 72(sp) +8000d5fc: 13 86 04 00 mv a2, s1 +8000d600: 93 85 16 00 addi a1, a3, 1 +8000d604: e3 cc 8c fb blt s9, s8, -72 +8000d608: b3 87 87 01 add a5, a5, s8 +8000d60c: 23 20 76 01 sw s7, 0(a2) +8000d610: 23 22 86 01 sw s8, 4(a2) +8000d614: 23 24 f1 04 sw a5, 72(sp) +8000d618: 23 22 b1 04 sw a1, 68(sp) +8000d61c: 13 07 70 00 addi a4, zero, 7 +8000d620: e3 52 b7 d4 bge a4, a1, -700 +8000d624: 63 8e 07 66 beqz a5, 1660 +8000d628: 13 06 01 04 addi a2, sp, 64 +8000d62c: 93 85 09 00 mv a1, s3 +8000d630: 13 85 0a 00 mv a0, s5 +8000d634: ef f0 9f 8f jal -1800 +8000d638: e3 1e 05 d4 bnez a0, -676 +8000d63c: 83 27 81 04 lw a5, 72(sp) +8000d640: 6f f0 5f d2 j -732 +8000d644: 03 26 c1 00 lw a2, 12(sp) +8000d648: 93 f7 0d 01 andi a5, s11, 16 +8000d64c: 93 06 46 00 addi a3, a2, 4 +8000d650: e3 90 07 0c bnez a5, 2240 +8000d654: 93 f7 0d 04 andi a5, s11, 64 +8000d658: e3 8e 07 24 beqz a5, 2652 +8000d65c: 83 27 c1 00 lw a5, 12(sp) +8000d660: 13 08 00 00 mv a6, zero +8000d664: 23 26 d1 00 sw a3, 12(sp) +8000d668: 03 dc 07 00 lhu s8, 0(a5) +8000d66c: 6f f0 9f eb j -328 +8000d670: 03 26 c1 00 lw a2, 12(sp) +8000d674: 93 f7 0d 01 andi a5, s11, 16 +8000d678: 93 06 46 00 addi a3, a2, 4 +8000d67c: e3 90 07 08 bnez a5, 2176 +8000d680: 93 f7 0d 04 andi a5, s11, 64 +8000d684: e3 88 07 20 beqz a5, 2576 +8000d688: 83 27 c1 00 lw a5, 12(sp) +8000d68c: 23 26 d1 00 sw a3, 12(sp) +8000d690: 03 9c 07 00 lh s8, 0(a5) +8000d694: 13 58 fc 41 srai a6, s8, 31 +8000d698: 93 06 08 00 mv a3, a6 +8000d69c: e3 d4 06 dc bgez a3, -568 +8000d6a0: b3 36 80 01 snez a3, s8 +8000d6a4: 33 08 00 41 neg a6, a6 +8000d6a8: 33 08 d8 40 sub a6, a6, a3 +8000d6ac: 93 06 d0 02 addi a3, zero, 45 +8000d6b0: a3 0d d1 02 sb a3, 59(sp) +8000d6b4: 13 06 f0 ff addi a2, zero, -1 +8000d6b8: 33 0c 80 41 neg s8, s8 +8000d6bc: 13 8a 0d 00 mv s4, s11 +8000d6c0: 93 06 10 00 addi a3, zero, 1 +8000d6c4: e3 9a cc e6 bne s9, a2, -396 +8000d6c8: 13 06 10 00 addi a2, zero, 1 +8000d6cc: e3 88 c6 da beq a3, a2, -592 +8000d6d0: 13 06 20 00 addi a2, zero, 2 +8000d6d4: 63 88 c6 26 beq a3, a2, 624 +8000d6d8: 13 0b 01 0f addi s6, sp, 240 +8000d6dc: 13 16 d8 01 slli a2, a6, 29 +8000d6e0: 93 76 7c 00 andi a3, s8, 7 +8000d6e4: 93 57 3c 00 srli a5, s8, 3 +8000d6e8: 93 86 06 03 addi a3, a3, 48 +8000d6ec: 33 6c f6 00 or s8, a2, a5 +8000d6f0: 13 58 38 00 srli a6, a6, 3 +8000d6f4: a3 0f db fe sb a3, -1(s6) +8000d6f8: 33 66 0c 01 or a2, s8, a6 +8000d6fc: 93 05 0b 00 mv a1, s6 +8000d700: 13 0b fb ff addi s6, s6, -1 +8000d704: e3 1c 06 fc bnez a2, -40 +8000d708: 93 77 1a 00 andi a5, s4, 1 +8000d70c: 63 86 07 26 beqz a5, 620 +8000d710: 93 07 00 03 addi a5, zero, 48 +8000d714: 63 82 f6 26 beq a3, a5, 612 +8000d718: 93 85 e5 ff addi a1, a1, -2 +8000d71c: a3 0f fb fe sb a5, -1(s6) +8000d720: 93 07 01 0f addi a5, sp, 240 +8000d724: 33 8c b7 40 sub s8, a5, a1 +8000d728: 93 0d 0a 00 mv s11, s4 +8000d72c: 13 8b 05 00 mv s6, a1 +8000d730: 6f f0 df d6 j -660 +8000d734: ef 10 80 39 jal 5016 +8000d738: 6f f0 1f 95 j -1712 +8000d73c: 83 27 c1 00 lw a5, 12(sp) +8000d740: a3 0d 01 02 sb zero, 59(sp) +8000d744: 03 ab 07 00 lw s6, 0(a5) +8000d748: 93 86 47 00 addi a3, a5, 4 +8000d74c: e3 04 0b 12 beqz s6, 2344 +8000d750: 93 07 f0 ff addi a5, zero, -1 +8000d754: e3 8c fc 06 beq s9, a5, 2168 +8000d758: 13 86 0c 00 mv a2, s9 +8000d75c: 93 05 00 00 mv a1, zero +8000d760: 13 05 0b 00 mv a0, s6 +8000d764: 23 2c d1 00 sw a3, 24(sp) +8000d768: 23 26 e1 00 sw a4, 12(sp) +8000d76c: ef c0 cf c2 jal -15316 +8000d770: 03 27 c1 00 lw a4, 12(sp) +8000d774: 83 26 81 01 lw a3, 24(sp) +8000d778: e3 0c 05 24 beqz a0, 2648 +8000d77c: 33 0c 65 41 sub s8, a0, s6 +8000d780: 23 26 d1 00 sw a3, 12(sp) +8000d784: 93 0c 00 00 mv s9, zero +8000d788: 6f f0 5f d1 j -748 +8000d78c: 83 26 c1 00 lw a3, 12(sp) +8000d790: a3 0d 01 02 sb zero, 59(sp) +8000d794: 13 0a 10 00 addi s4, zero, 1 +8000d798: 83 a7 06 00 lw a5, 0(a3) +8000d79c: 93 86 46 00 addi a3, a3, 4 +8000d7a0: 23 26 d1 00 sw a3, 12(sp) +8000d7a4: 23 06 f1 08 sb a5, 140(sp) +8000d7a8: 13 0c 10 00 addi s8, zero, 1 +8000d7ac: 13 0b c1 08 addi s6, sp, 140 +8000d7b0: 6f f0 df a8 j -1396 +8000d7b4: 83 46 0d 00 lbu a3, 0(s10) +8000d7b8: 93 07 c0 06 addi a5, zero, 108 +8000d7bc: e3 8e f6 08 beq a3, a5, 2204 +8000d7c0: 93 ed 0d 01 ori s11, s11, 16 +8000d7c4: 6f f0 1f a1 j -1520 +8000d7c8: 83 46 0d 00 lbu a3, 0(s10) +8000d7cc: 93 07 80 06 addi a5, zero, 104 +8000d7d0: e3 8c f6 06 beq a3, a5, 2168 +8000d7d4: 93 ed 0d 04 ori s11, s11, 64 +8000d7d8: 6f f0 df 9f j -1540 +8000d7dc: 13 ea 0d 01 ori s4, s11, 16 +8000d7e0: 93 77 0a 02 andi a5, s4, 32 +8000d7e4: 63 84 07 52 beqz a5, 1320 +8000d7e8: 83 27 c1 00 lw a5, 12(sp) +8000d7ec: 93 06 10 00 addi a3, zero, 1 +8000d7f0: 13 8b 77 00 addi s6, a5, 7 +8000d7f4: 13 7b 8b ff andi s6, s6, -8 +8000d7f8: 93 07 8b 00 addi a5, s6, 8 +8000d7fc: 03 2c 0b 00 lw s8, 0(s6) +8000d800: 03 28 4b 00 lw a6, 4(s6) +8000d804: 23 26 f1 00 sw a5, 12(sp) +8000d808: 6f f0 5f d2 j -732 +8000d80c: 83 46 0d 00 lbu a3, 0(s10) +8000d810: 93 ed 0d 08 ori s11, s11, 128 +8000d814: 6f f0 1f 9c j -1600 +8000d818: 83 27 c1 00 lw a5, 12(sp) +8000d81c: 13 ea 2d 00 ori s4, s11, 2 +8000d820: b7 86 ff ff lui a3, 1048568 +8000d824: 03 ac 07 00 lw s8, 0(a5) +8000d828: b7 5d 01 80 lui s11, 524309 +8000d82c: 93 87 47 00 addi a5, a5, 4 +8000d830: 93 c6 06 83 xori a3, a3, -2000 +8000d834: 23 26 f1 00 sw a5, 12(sp) +8000d838: 93 87 8d 5a addi a5, s11, 1448 +8000d83c: 23 1e d1 02 sh a3, 60(sp) +8000d840: 13 08 00 00 mv a6, zero +8000d844: 23 28 f1 00 sw a5, 16(sp) +8000d848: 93 06 20 00 addi a3, zero, 2 +8000d84c: 6f f0 1f ce j -800 +8000d850: 03 26 c1 00 lw a2, 12(sp) +8000d854: 93 f7 0d 02 andi a5, s11, 32 +8000d858: 83 26 06 00 lw a3, 0(a2) +8000d85c: 13 06 46 00 addi a2, a2, 4 +8000d860: 23 26 c1 00 sw a2, 12(sp) +8000d864: 63 92 07 68 bnez a5, 1668 +8000d868: 93 f7 0d 01 andi a5, s11, 16 +8000d86c: 63 9e 07 7e bnez a5, 2044 +8000d870: 93 f7 0d 04 andi a5, s11, 64 +8000d874: e3 92 07 0e bnez a5, 2276 +8000d878: 93 fe 0d 20 andi t4, s11, 512 +8000d87c: 63 86 0e 7e beqz t4, 2028 +8000d880: 83 27 81 00 lw a5, 8(sp) +8000d884: 23 80 f6 00 sb a5, 0(a3) +8000d888: 6f f0 5f 8a j -1884 +8000d88c: 83 27 c1 00 lw a5, 12(sp) +8000d890: 83 46 0d 00 lbu a3, 0(s10) +8000d894: 03 a4 07 00 lw s0, 0(a5) +8000d898: 93 87 47 00 addi a5, a5, 4 +8000d89c: 23 26 f1 00 sw a5, 12(sp) +8000d8a0: e3 5a 04 92 bgez s0, -1740 +8000d8a4: 33 04 80 40 neg s0, s0 +8000d8a8: 93 ed 4d 00 ori s11, s11, 4 +8000d8ac: 6f f0 9f 92 j -1752 +8000d8b0: 83 46 0d 00 lbu a3, 0(s10) +8000d8b4: 93 ed 1d 00 ori s11, s11, 1 +8000d8b8: 6f f0 df 91 j -1764 +8000d8bc: 83 47 b1 03 lbu a5, 59(sp) +8000d8c0: 83 46 0d 00 lbu a3, 0(s10) +8000d8c4: e3 98 07 90 bnez a5, -1776 +8000d8c8: 93 07 00 02 addi a5, zero, 32 +8000d8cc: a3 0d f1 02 sb a5, 59(sp) +8000d8d0: 6f f0 5f 90 j -1788 +8000d8d4: 83 46 0d 00 lbu a3, 0(s10) +8000d8d8: 93 ed 4d 00 ori s11, s11, 4 +8000d8dc: 6f f0 9f 8f j -1800 +8000d8e0: 93 07 b0 02 addi a5, zero, 43 +8000d8e4: 83 46 0d 00 lbu a3, 0(s10) +8000d8e8: a3 0d f1 02 sb a5, 59(sp) +8000d8ec: 6f f0 9f 8e j -1816 +8000d8f0: 83 46 0d 00 lbu a3, 0(s10) +8000d8f4: 93 05 1d 00 addi a1, s10, 1 +8000d8f8: e3 8c 66 11 beq a3, s6, 2328 +8000d8fc: 93 87 06 fd addi a5, a3, -48 +8000d900: 13 8d 05 00 mv s10, a1 +8000d904: 93 0c 00 00 mv s9, zero +8000d908: e3 68 fc 8c bltu s8, a5, -1840 +8000d90c: 83 46 0d 00 lbu a3, 0(s10) +8000d910: 13 98 2c 00 slli a6, s9, 2 +8000d914: 33 08 98 01 add a6, a6, s9 +8000d918: 13 18 18 00 slli a6, a6, 1 +8000d91c: b3 0c f8 00 add s9, a6, a5 +8000d920: 93 87 06 fd addi a5, a3, -48 +8000d924: 13 0d 1d 00 addi s10, s10, 1 +8000d928: e3 72 fc fe bgeu s8, a5, -28 +8000d92c: 6f f0 df 8a j -1876 +8000d930: 13 06 10 00 addi a2, zero, 1 +8000d934: e3 8e c6 0a beq a3, a2, 2236 +8000d938: 13 06 20 00 addi a2, zero, 2 +8000d93c: 13 8a 0d 00 mv s4, s11 +8000d940: e3 9c c6 d8 bne a3, a2, -616 +8000d944: 13 0b 01 0f addi s6, sp, 240 +8000d948: 83 27 01 01 lw a5, 16(sp) +8000d94c: 93 76 fc 00 andi a3, s8, 15 +8000d950: 13 0b fb ff addi s6, s6, -1 +8000d954: b3 86 d7 00 add a3, a5, a3 +8000d958: 03 c6 06 00 lbu a2, 0(a3) +8000d95c: 93 57 4c 00 srli a5, s8, 4 +8000d960: 93 16 c8 01 slli a3, a6, 28 +8000d964: 33 ec f6 00 or s8, a3, a5 +8000d968: 13 58 48 00 srli a6, a6, 4 +8000d96c: 23 00 cb 00 sb a2, 0(s6) +8000d970: b3 66 0c 01 or a3, s8, a6 +8000d974: e3 9a 06 fc bnez a3, -44 +8000d978: 93 07 01 0f addi a5, sp, 240 +8000d97c: 33 8c 67 41 sub s8, a5, s6 +8000d980: 93 0d 0a 00 mv s11, s4 +8000d984: 6f f0 9f b1 j -1256 +8000d988: 93 05 10 00 addi a1, zero, 1 +8000d98c: 93 06 00 00 mv a3, zero +8000d990: 13 86 04 00 mv a2, s1 +8000d994: 6f f0 1f c2 j -992 +8000d998: 33 08 44 41 sub a6, s0, s4 +8000d99c: e3 5a 00 97 blez a6, -1676 +8000d9a0: 13 05 00 01 addi a0, zero, 16 +8000d9a4: e3 50 05 07 bge a0, a6, 2144 +8000d9a8: 13 0f 00 01 addi t5, zero, 16 +8000d9ac: 93 0f 70 00 addi t6, zero, 7 +8000d9b0: 6f 00 80 01 j 24 +8000d9b4: 13 85 26 00 addi a0, a3, 2 +8000d9b8: 13 07 87 00 addi a4, a4, 8 +8000d9bc: 93 06 06 00 mv a3, a2 +8000d9c0: 13 08 08 ff addi a6, a6, -16 +8000d9c4: 63 50 0f 07 bge t5, a6, 96 +8000d9c8: 93 87 07 01 addi a5, a5, 16 +8000d9cc: 13 86 16 00 addi a2, a3, 1 +8000d9d0: 23 20 27 01 sw s2, 0(a4) +8000d9d4: 23 22 e7 01 sw t5, 4(a4) +8000d9d8: 23 24 f1 04 sw a5, 72(sp) +8000d9dc: 23 22 c1 04 sw a2, 68(sp) +8000d9e0: e3 da cf fc bge t6, a2, -44 +8000d9e4: 63 84 07 16 beqz a5, 360 +8000d9e8: 13 06 01 04 addi a2, sp, 64 +8000d9ec: 93 85 09 00 mv a1, s3 +8000d9f0: 13 85 0a 00 mv a0, s5 +8000d9f4: 23 2c 01 01 sw a6, 24(sp) +8000d9f8: ef f0 4f d3 jal -2764 +8000d9fc: e3 1c 05 98 bnez a0, -1640 +8000da00: 03 28 81 01 lw a6, 24(sp) +8000da04: 83 26 41 04 lw a3, 68(sp) +8000da08: 13 0f 00 01 addi t5, zero, 16 +8000da0c: 13 08 08 ff addi a6, a6, -16 +8000da10: 83 27 81 04 lw a5, 72(sp) +8000da14: 13 87 04 00 mv a4, s1 +8000da18: 13 85 16 00 addi a0, a3, 1 +8000da1c: 93 0f 70 00 addi t6, zero, 7 +8000da20: e3 44 0f fb blt t5, a6, -88 +8000da24: 13 0f 87 00 addi t5, a4, 8 +8000da28: b3 87 07 01 add a5, a5, a6 +8000da2c: 23 20 27 01 sw s2, 0(a4) +8000da30: 23 22 07 01 sw a6, 4(a4) +8000da34: 23 24 f1 04 sw a5, 72(sp) +8000da38: 23 22 a1 04 sw a0, 68(sp) +8000da3c: 13 07 70 00 addi a4, zero, 7 +8000da40: 63 52 a7 46 bge a4, a0, 1124 +8000da44: 63 8e 07 6c beqz a5, 1756 +8000da48: 13 06 01 04 addi a2, sp, 64 +8000da4c: 93 85 09 00 mv a1, s3 +8000da50: 13 85 0a 00 mv a0, s5 +8000da54: ef f0 8f cd jal -2856 +8000da58: e3 1e 05 92 bnez a0, -1732 +8000da5c: 83 26 41 04 lw a3, 68(sp) +8000da60: b3 8c 8c 41 sub s9, s9, s8 +8000da64: 83 27 81 04 lw a5, 72(sp) +8000da68: 13 06 41 05 addi a2, sp, 84 +8000da6c: 93 85 16 00 addi a1, a3, 1 +8000da70: 13 87 04 00 mv a4, s1 +8000da74: e3 52 90 8b blez s9, -1884 +8000da78: 13 05 00 01 addi a0, zero, 16 +8000da7c: 63 58 95 69 bge a0, s9, 1680 +8000da80: 13 03 00 01 addi t1, zero, 16 +8000da84: 13 0f 70 00 addi t5, zero, 7 +8000da88: 6f 00 80 01 j 24 +8000da8c: 93 85 26 00 addi a1, a3, 2 +8000da90: 13 07 87 00 addi a4, a4, 8 +8000da94: 93 06 06 00 mv a3, a2 +8000da98: 93 8c 0c ff addi s9, s9, -16 +8000da9c: 63 5c 93 05 bge t1, s9, 88 +8000daa0: 93 87 07 01 addi a5, a5, 16 +8000daa4: 13 86 16 00 addi a2, a3, 1 +8000daa8: 23 20 27 01 sw s2, 0(a4) +8000daac: 23 22 67 00 sw t1, 4(a4) +8000dab0: 23 24 f1 04 sw a5, 72(sp) +8000dab4: 23 22 c1 04 sw a2, 68(sp) +8000dab8: e3 5a cf fc bge t5, a2, -44 +8000dabc: 63 84 07 06 beqz a5, 104 +8000dac0: 13 06 01 04 addi a2, sp, 64 +8000dac4: 93 85 09 00 mv a1, s3 +8000dac8: 13 85 0a 00 mv a0, s5 +8000dacc: ef f0 0f c6 jal -2976 +8000dad0: e3 12 05 8c bnez a0, -1852 +8000dad4: 83 26 41 04 lw a3, 68(sp) +8000dad8: 13 03 00 01 addi t1, zero, 16 +8000dadc: 93 8c 0c ff addi s9, s9, -16 +8000dae0: 83 27 81 04 lw a5, 72(sp) +8000dae4: 13 87 04 00 mv a4, s1 +8000dae8: 93 85 16 00 addi a1, a3, 1 +8000daec: 13 0f 70 00 addi t5, zero, 7 +8000daf0: e3 48 93 fb blt t1, s9, -80 +8000daf4: 93 06 87 00 addi a3, a4, 8 +8000daf8: b3 87 97 01 add a5, a5, s9 +8000dafc: 23 20 27 01 sw s2, 0(a4) +8000db00: 23 22 97 01 sw s9, 4(a4) +8000db04: 23 24 f1 04 sw a5, 72(sp) +8000db08: 23 22 b1 04 sw a1, 68(sp) +8000db0c: 13 07 70 00 addi a4, zero, 7 +8000db10: 63 44 b7 1a blt a4, a1, 424 +8000db14: 93 85 15 00 addi a1, a1, 1 +8000db18: 13 86 86 00 addi a2, a3, 8 +8000db1c: 13 87 06 00 mv a4, a3 +8000db20: 6f f0 8f ff j -2056 +8000db24: 93 05 10 00 addi a1, zero, 1 +8000db28: 93 06 00 00 mv a3, zero +8000db2c: 13 87 04 00 mv a4, s1 +8000db30: 6f f0 9f f6 j -152 +8000db34: 13 06 01 04 addi a2, sp, 64 +8000db38: 93 85 09 00 mv a1, s3 +8000db3c: 13 85 0a 00 mv a0, s5 +8000db40: ef f0 cf be jal -3092 +8000db44: e3 0c 05 82 beqz a0, -1992 +8000db48: 6f f0 df 84 j -1972 +8000db4c: 13 05 10 00 addi a0, zero, 1 +8000db50: 93 06 00 00 mv a3, zero +8000db54: 13 87 04 00 mv a4, s1 +8000db58: 6f f0 9f e6 j -408 +8000db5c: 63 8a 07 1e beqz a5, 500 +8000db60: 13 06 01 04 addi a2, sp, 64 +8000db64: 93 85 09 00 mv a1, s3 +8000db68: 13 85 0a 00 mv a0, s5 +8000db6c: 23 2e e1 01 sw t5, 28(sp) +8000db70: 23 2c f1 01 sw t6, 24(sp) +8000db74: ef f0 8f bb jal -3144 +8000db78: e3 1e 05 80 bnez a0, -2020 +8000db7c: 83 26 41 04 lw a3, 68(sp) +8000db80: 83 27 81 04 lw a5, 72(sp) +8000db84: 03 2f c1 01 lw t5, 28(sp) +8000db88: 83 2f 81 01 lw t6, 24(sp) +8000db8c: 13 06 41 05 addi a2, sp, 84 +8000db90: 93 85 16 00 addi a1, a3, 1 +8000db94: 13 87 04 00 mv a4, s1 +8000db98: 6f f0 4f f1 j -2284 +8000db9c: 93 07 c1 03 addi a5, sp, 60 +8000dba0: 23 26 f1 04 sw a5, 76(sp) +8000dba4: 93 07 20 00 addi a5, zero, 2 +8000dba8: 23 28 f1 04 sw a5, 80(sp) +8000dbac: 93 05 10 00 addi a1, zero, 1 +8000dbb0: 13 06 41 05 addi a2, sp, 84 +8000dbb4: 93 86 05 00 mv a3, a1 +8000dbb8: 13 07 06 00 mv a4, a2 +8000dbbc: 93 85 16 00 addi a1, a3, 1 +8000dbc0: 13 06 87 00 addi a2, a4, 8 +8000dbc4: 6f f0 4f f4 j -2236 +8000dbc8: 13 8a 0d 00 mv s4, s11 +8000dbcc: 6f f0 df af j -1284 +8000dbd0: 93 05 00 01 addi a1, zero, 16 +8000dbd4: 63 d6 05 61 bge a1, a6, 1548 +8000dbd8: 93 02 00 01 addi t0, zero, 16 +8000dbdc: 93 03 70 00 addi t2, zero, 7 +8000dbe0: 6f 00 c0 01 j 28 +8000dbe4: 13 85 26 00 addi a0, a3, 2 +8000dbe8: 13 07 87 00 addi a4, a4, 8 +8000dbec: 93 06 06 00 mv a3, a2 +8000dbf0: 13 08 08 ff addi a6, a6, -16 +8000dbf4: 63 d8 02 07 bge t0, a6, 112 +8000dbf8: 13 86 16 00 addi a2, a3, 1 +8000dbfc: 93 87 07 01 addi a5, a5, 16 +8000dc00: 23 20 77 01 sw s7, 0(a4) +8000dc04: 23 22 57 00 sw t0, 4(a4) +8000dc08: 23 24 f1 04 sw a5, 72(sp) +8000dc0c: 23 22 c1 04 sw a2, 68(sp) +8000dc10: e3 da c3 fc bge t2, a2, -44 +8000dc14: 63 8e 07 06 beqz a5, 124 +8000dc18: 13 06 01 04 addi a2, sp, 64 +8000dc1c: 93 85 09 00 mv a1, s3 +8000dc20: 13 85 0a 00 mv a0, s5 +8000dc24: 23 20 01 03 sw a6, 32(sp) +8000dc28: 23 2e e1 01 sw t5, 28(sp) +8000dc2c: 23 2c f1 01 sw t6, 24(sp) +8000dc30: ef f0 cf af jal -3332 +8000dc34: 63 10 05 f6 bnez a0, -2208 +8000dc38: 03 28 01 02 lw a6, 32(sp) +8000dc3c: 83 26 41 04 lw a3, 68(sp) +8000dc40: 93 02 00 01 addi t0, zero, 16 +8000dc44: 13 08 08 ff addi a6, a6, -16 +8000dc48: 83 27 81 04 lw a5, 72(sp) +8000dc4c: 03 2f c1 01 lw t5, 28(sp) +8000dc50: 83 2f 81 01 lw t6, 24(sp) +8000dc54: 13 87 04 00 mv a4, s1 +8000dc58: 13 85 16 00 addi a0, a3, 1 +8000dc5c: 93 03 70 00 addi t2, zero, 7 +8000dc60: e3 cc 02 f9 blt t0, a6, -104 +8000dc64: b3 87 07 01 add a5, a5, a6 +8000dc68: 23 20 77 01 sw s7, 0(a4) +8000dc6c: 23 22 07 01 sw a6, 4(a4) +8000dc70: 23 24 f1 04 sw a5, 72(sp) +8000dc74: 23 22 a1 04 sw a0, 68(sp) +8000dc78: 93 06 70 00 addi a3, zero, 7 +8000dc7c: 63 ca a6 0e blt a3, a0, 244 +8000dc80: 13 07 87 00 addi a4, a4, 8 +8000dc84: 93 05 15 00 addi a1, a0, 1 +8000dc88: 93 06 05 00 mv a3, a0 +8000dc8c: 6f f0 0f de j -2592 +8000dc90: 93 06 00 00 mv a3, zero +8000dc94: 13 05 10 00 addi a0, zero, 1 +8000dc98: 13 87 04 00 mv a4, s1 +8000dc9c: 6f f0 5f f5 j -172 +8000dca0: 63 54 44 01 bge s0, s4, 8 +8000dca4: 13 04 0a 00 mv s0, s4 +8000dca8: 83 27 81 00 lw a5, 8(sp) +8000dcac: b3 87 87 00 add a5, a5, s0 +8000dcb0: 23 24 f1 00 sw a5, 8(sp) +8000dcb4: 6f f0 8f ec j -2360 +8000dcb8: 63 8a 07 34 beqz a5, 852 +8000dcbc: 13 06 01 04 addi a2, sp, 64 +8000dcc0: 93 85 09 00 mv a1, s3 +8000dcc4: 13 85 0a 00 mv a0, s5 +8000dcc8: ef f0 4f a6 jal -3484 +8000dccc: 63 14 05 ec bnez a0, -2360 +8000dcd0: 83 25 41 04 lw a1, 68(sp) +8000dcd4: 83 27 81 04 lw a5, 72(sp) +8000dcd8: 13 06 41 05 addi a2, sp, 84 +8000dcdc: 93 85 15 00 addi a1, a1, 1 +8000dce0: 13 87 04 00 mv a4, s1 +8000dce4: 6f f0 4f e3 j -2508 +8000dce8: 23 22 01 04 sw zero, 68(sp) +8000dcec: 13 87 04 00 mv a4, s1 +8000dcf0: 6f f0 cf ca j -2900 +8000dcf4: 63 9a 0c f8 bnez s9, -2156 +8000dcf8: 93 0d 0a 00 mv s11, s4 +8000dcfc: 93 0c 00 00 mv s9, zero +8000dd00: 13 0c 00 00 mv s8, zero +8000dd04: 13 0b 01 0f addi s6, sp, 240 +8000dd08: 6f f0 4f f9 j -2156 +8000dd0c: 03 26 c1 00 lw a2, 12(sp) +8000dd10: 93 77 0a 01 andi a5, s4, 16 +8000dd14: 93 06 46 00 addi a3, a2, 4 +8000dd18: 63 90 07 1a bnez a5, 416 +8000dd1c: 93 77 0a 04 andi a5, s4, 64 +8000dd20: 63 86 07 3c beqz a5, 972 +8000dd24: 83 27 c1 00 lw a5, 12(sp) +8000dd28: 13 08 00 00 mv a6, zero +8000dd2c: 23 26 d1 00 sw a3, 12(sp) +8000dd30: 03 dc 07 00 lhu s8, 0(a5) +8000dd34: 93 06 10 00 addi a3, zero, 1 +8000dd38: 6f f0 4f ff j -2060 +8000dd3c: 13 06 41 05 addi a2, sp, 84 +8000dd40: 93 05 10 00 addi a1, zero, 1 +8000dd44: 93 06 00 00 mv a3, zero +8000dd48: 13 87 04 00 mv a4, s1 +8000dd4c: 6f f0 cf db j -2628 +8000dd50: 63 88 0f 1c beqz t6, 464 +8000dd54: 93 07 c1 03 addi a5, sp, 60 +8000dd58: 23 26 f1 04 sw a5, 76(sp) +8000dd5c: 93 07 20 00 addi a5, zero, 2 +8000dd60: 23 28 f1 04 sw a5, 80(sp) +8000dd64: 93 06 10 00 addi a3, zero, 1 +8000dd68: 13 07 41 05 addi a4, sp, 84 +8000dd6c: 6f f0 1f e5 j -432 +8000dd70: 63 8e 07 26 beqz a5, 636 +8000dd74: 13 06 01 04 addi a2, sp, 64 +8000dd78: 93 85 09 00 mv a1, s3 +8000dd7c: 13 85 0a 00 mv a0, s5 +8000dd80: 23 2e e1 01 sw t5, 28(sp) +8000dd84: 23 2c f1 01 sw t6, 24(sp) +8000dd88: ef f0 4f 9a jal -3676 +8000dd8c: 63 14 05 e0 bnez a0, -2552 +8000dd90: 83 26 41 04 lw a3, 68(sp) +8000dd94: 83 27 81 04 lw a5, 72(sp) +8000dd98: 03 2f c1 01 lw t5, 28(sp) +8000dd9c: 83 2f 81 01 lw t6, 24(sp) +8000dda0: 13 87 04 00 mv a4, s1 +8000dda4: 93 85 16 00 addi a1, a3, 1 +8000dda8: 6f f0 4f cc j -2876 +8000ddac: 93 77 0a 40 andi a5, s4, 1024 +8000ddb0: 23 20 f1 02 sw a5, 32(sp) +8000ddb4: 93 0d 00 00 mv s11, zero +8000ddb8: 13 0b 01 0f addi s6, sp, 240 +8000ddbc: 6f 00 40 03 j 52 +8000ddc0: 93 05 08 00 mv a1, a6 +8000ddc4: 13 06 a0 00 addi a2, zero, 10 +8000ddc8: 93 06 00 00 mv a3, zero +8000ddcc: 13 05 0c 00 mv a0, s8 +8000ddd0: 23 2e e1 00 sw a4, 28(sp) +8000ddd4: 23 2c 01 01 sw a6, 24(sp) +8000ddd8: ef 20 40 1d jal 8660 +8000dddc: 03 28 81 01 lw a6, 24(sp) +8000dde0: 03 27 c1 01 lw a4, 28(sp) +8000dde4: 63 08 08 32 beqz a6, 816 +8000dde8: 13 0c 05 00 mv s8, a0 +8000ddec: 13 88 05 00 mv a6, a1 +8000ddf0: 93 05 08 00 mv a1, a6 +8000ddf4: 13 06 a0 00 addi a2, zero, 10 +8000ddf8: 93 06 00 00 mv a3, zero +8000ddfc: 13 05 0c 00 mv a0, s8 +8000de00: 23 2e e1 00 sw a4, 28(sp) +8000de04: 23 2c 01 01 sw a6, 24(sp) +8000de08: ef 20 80 5d jal 9688 +8000de0c: 83 27 01 02 lw a5, 32(sp) +8000de10: 13 05 05 03 addi a0, a0, 48 +8000de14: a3 0f ab fe sb a0, -1(s6) +8000de18: 03 28 81 01 lw a6, 24(sp) +8000de1c: 03 27 c1 01 lw a4, 28(sp) +8000de20: 13 0b fb ff addi s6, s6, -1 +8000de24: 93 8d 1d 00 addi s11, s11, 1 +8000de28: e3 8c 07 f8 beqz a5, -104 +8000de2c: 83 27 41 02 lw a5, 36(sp) +8000de30: 83 c6 07 00 lbu a3, 0(a5) +8000de34: e3 96 b6 f9 bne a3, s11, -116 +8000de38: 93 07 f0 0f addi a5, zero, 255 +8000de3c: e3 82 fd f8 beq s11, a5, -124 +8000de40: 63 16 08 00 bnez a6, 12 +8000de44: 93 07 90 00 addi a5, zero, 9 +8000de48: e3 f8 87 b3 bgeu a5, s8, -1232 +8000de4c: 83 27 81 02 lw a5, 40(sp) +8000de50: 83 25 c1 02 lw a1, 44(sp) +8000de54: 23 2e 01 01 sw a6, 28(sp) +8000de58: 33 0b fb 40 sub s6, s6, a5 +8000de5c: 13 86 07 00 mv a2, a5 +8000de60: 13 05 0b 00 mv a0, s6 +8000de64: 23 2c e1 00 sw a4, 24(sp) +8000de68: ef d0 0f a9 jal -11632 +8000de6c: 03 27 41 02 lw a4, 36(sp) +8000de70: 03 28 c1 01 lw a6, 28(sp) +8000de74: 13 06 a0 00 addi a2, zero, 10 +8000de78: 83 45 17 00 lbu a1, 1(a4) +8000de7c: 93 06 00 00 mv a3, zero +8000de80: 13 05 0c 00 mv a0, s8 +8000de84: b3 37 b0 00 snez a5, a1 +8000de88: b3 07 f7 00 add a5, a4, a5 +8000de8c: 93 05 08 00 mv a1, a6 +8000de90: 23 22 f1 02 sw a5, 36(sp) +8000de94: ef 20 80 11 jal 8472 +8000de98: 03 27 81 01 lw a4, 24(sp) +8000de9c: 93 0d 00 00 mv s11, zero +8000dea0: 6f f0 9f f4 j -184 +8000dea4: 93 05 15 00 addi a1, a0, 1 +8000dea8: 13 06 8f 00 addi a2, t5, 8 +8000deac: 93 06 05 00 mv a3, a0 +8000deb0: 13 07 0f 00 mv a4, t5 +8000deb4: 6f f0 cf c5 j -2980 +8000deb8: 23 26 d1 00 sw a3, 12(sp) +8000debc: 03 2c 06 00 lw s8, 0(a2) +8000dec0: 13 08 00 00 mv a6, zero +8000dec4: 93 06 10 00 addi a3, zero, 1 +8000dec8: 6f f0 4f e6 j -2460 +8000decc: 83 27 41 02 lw a5, 36(sp) +8000ded0: 83 46 0d 00 lbu a3, 0(s10) +8000ded4: 63 80 07 b0 beqz a5, -3328 +8000ded8: 83 c7 07 00 lbu a5, 0(a5) +8000dedc: 63 8c 07 ae beqz a5, -3336 +8000dee0: 93 ed 0d 40 ori s11, s11, 1024 +8000dee4: 6f f0 0f af j -3344 +8000dee8: 03 26 81 00 lw a2, 8(sp) +8000deec: 93 57 f6 41 srai a5, a2, 31 +8000def0: 23 a0 c6 00 sw a2, 0(a3) +8000def4: 23 a2 f6 00 sw a5, 4(a3) +8000def8: 6f f0 4f a3 j -3532 +8000defc: 03 2c 06 00 lw s8, 0(a2) +8000df00: 23 26 d1 00 sw a3, 12(sp) +8000df04: 13 58 fc 41 srai a6, s8, 31 +8000df08: 93 06 08 00 mv a3, a6 +8000df0c: 6f f0 4f d5 j -2732 +8000df10: 03 2c 06 00 lw s8, 0(a2) +8000df14: 13 08 00 00 mv a6, zero +8000df18: 23 26 d1 00 sw a3, 12(sp) +8000df1c: 6f f0 8f e0 j -2552 +8000df20: 93 06 00 00 mv a3, zero +8000df24: 13 06 41 05 addi a2, sp, 84 +8000df28: 93 05 10 00 addi a1, zero, 1 +8000df2c: 13 87 04 00 mv a4, s1 +8000df30: 6f f0 8f bd j -3112 +8000df34: b7 57 01 80 lui a5, 524309 +8000df38: 93 87 c7 5b addi a5, a5, 1468 +8000df3c: 23 28 f1 00 sw a5, 16(sp) +8000df40: 93 f7 0d 02 andi a5, s11, 32 +8000df44: 63 84 07 06 beqz a5, 104 +8000df48: 83 27 c1 00 lw a5, 12(sp) +8000df4c: 13 8b 77 00 addi s6, a5, 7 +8000df50: 13 7b 8b ff andi s6, s6, -8 +8000df54: 03 2c 0b 00 lw s8, 0(s6) +8000df58: 03 28 4b 00 lw a6, 4(s6) +8000df5c: 93 07 8b 00 addi a5, s6, 8 +8000df60: 23 26 f1 00 sw a5, 12(sp) +8000df64: 13 f6 1d 00 andi a2, s11, 1 +8000df68: 63 0e 06 00 beqz a2, 28 +8000df6c: 33 66 0c 01 or a2, s8, a6 +8000df70: 63 0a 06 00 beqz a2, 20 +8000df74: 13 06 00 03 addi a2, zero, 48 +8000df78: 23 0e c1 02 sb a2, 60(sp) +8000df7c: a3 0e d1 02 sb a3, 61(sp) +8000df80: 93 ed 2d 00 ori s11, s11, 2 +8000df84: 13 fa fd bf andi s4, s11, -1025 +8000df88: 93 06 20 00 addi a3, zero, 2 +8000df8c: 6f f0 0f da j -2656 +8000df90: 13 8a 0d 00 mv s4, s11 +8000df94: 6f f0 df 84 j -1972 +8000df98: b7 57 01 80 lui a5, 524309 +8000df9c: 93 87 87 5a addi a5, a5, 1448 +8000dfa0: 23 28 f1 00 sw a5, 16(sp) +8000dfa4: 93 f7 0d 02 andi a5, s11, 32 +8000dfa8: e3 90 07 fa bnez a5, -96 +8000dfac: 83 25 c1 00 lw a1, 12(sp) +8000dfb0: 93 f7 0d 01 andi a5, s11, 16 +8000dfb4: 13 86 45 00 addi a2, a1, 4 +8000dfb8: 63 8a 07 06 beqz a5, 116 +8000dfbc: 03 ac 05 00 lw s8, 0(a1) +8000dfc0: 13 08 00 00 mv a6, zero +8000dfc4: 23 26 c1 00 sw a2, 12(sp) +8000dfc8: 6f f0 df f9 j -100 +8000dfcc: 13 05 0b 00 mv a0, s6 +8000dfd0: 23 2c e1 00 sw a4, 24(sp) +8000dfd4: 23 26 d1 00 sw a3, 12(sp) +8000dfd8: ef d0 4f 89 jal -12140 +8000dfdc: 03 27 81 01 lw a4, 24(sp) +8000dfe0: 13 0c 05 00 mv s8, a0 +8000dfe4: 93 0c 00 00 mv s9, zero +8000dfe8: 6f f0 4f cb j -2892 +8000dfec: 03 47 b1 03 lbu a4, 59(sp) +8000dff0: 63 16 07 14 bnez a4, 332 +8000dff4: e3 94 0f ba bnez t6, -1112 +8000dff8: 93 06 00 00 mv a3, zero +8000dffc: 93 05 10 00 addi a1, zero, 1 +8000e000: 13 06 41 05 addi a2, sp, 84 +8000e004: 13 87 04 00 mv a4, s1 +8000e008: 6f f0 0f b0 j -3328 +8000e00c: 13 07 10 00 addi a4, zero, 1 +8000e010: 93 07 0c 00 mv a5, s8 +8000e014: 23 26 61 05 sw s6, 76(sp) +8000e018: 23 28 81 05 sw s8, 80(sp) +8000e01c: 23 24 81 05 sw s8, 72(sp) +8000e020: 23 22 e1 04 sw a4, 68(sp) +8000e024: 13 06 41 05 addi a2, sp, 84 +8000e028: 6f f0 cf b2 j -3284 +8000e02c: 93 f7 0d 04 andi a5, s11, 64 +8000e030: 63 80 07 0a beqz a5, 160 +8000e034: 83 27 c1 00 lw a5, 12(sp) +8000e038: 13 08 00 00 mv a6, zero +8000e03c: 23 26 c1 00 sw a2, 12(sp) +8000e040: 03 dc 07 00 lhu s8, 0(a5) +8000e044: 6f f0 1f f2 j -224 +8000e048: 83 46 1d 00 lbu a3, 1(s10) +8000e04c: 93 ed 0d 20 ori s11, s11, 512 +8000e050: 13 0d 1d 00 addi s10, s10, 1 +8000e054: 6f f0 0f 98 j -3712 +8000e058: 83 46 1d 00 lbu a3, 1(s10) +8000e05c: 93 ed 0d 02 ori s11, s11, 32 +8000e060: 13 0d 1d 00 addi s10, s10, 1 +8000e064: 6f f0 0f 97 j -3728 +8000e068: 83 27 81 00 lw a5, 8(sp) +8000e06c: 23 a0 f6 00 sw a5, 0(a3) +8000e070: 6f f0 cf 8b j -3908 +8000e074: 93 07 60 00 addi a5, zero, 6 +8000e078: 13 8c 0c 00 mv s8, s9 +8000e07c: 63 ec 97 0b bltu a5, s9, 184 +8000e080: b7 58 01 80 lui a7, 524309 +8000e084: 13 0a 0c 00 mv s4, s8 +8000e088: 23 26 d1 00 sw a3, 12(sp) +8000e08c: 13 8b 08 5d addi s6, a7, 1488 +8000e090: 6f f0 cf 9a j -3668 +8000e094: 93 f7 0d 20 andi a5, s11, 512 +8000e098: 63 86 07 10 beqz a5, 268 +8000e09c: 83 27 c1 00 lw a5, 12(sp) +8000e0a0: 23 26 d1 00 sw a3, 12(sp) +8000e0a4: 03 8c 07 00 lb s8, 0(a5) +8000e0a8: 13 58 fc 41 srai a6, s8, 31 +8000e0ac: 93 06 08 00 mv a3, a6 +8000e0b0: 6f f0 0f bb j -3152 +8000e0b4: 93 f7 0d 20 andi a5, s11, 512 +8000e0b8: 63 8c 07 0c beqz a5, 216 +8000e0bc: 83 27 c1 00 lw a5, 12(sp) +8000e0c0: 13 08 00 00 mv a6, zero +8000e0c4: 23 26 d1 00 sw a3, 12(sp) +8000e0c8: 03 cc 07 00 lbu s8, 0(a5) +8000e0cc: 6f f0 8f c5 j -2984 +8000e0d0: 93 f7 0d 20 andi a5, s11, 512 +8000e0d4: 63 84 07 0a beqz a5, 168 +8000e0d8: 83 27 c1 00 lw a5, 12(sp) +8000e0dc: 13 08 00 00 mv a6, zero +8000e0e0: 23 26 c1 00 sw a2, 12(sp) +8000e0e4: 03 cc 07 00 lbu s8, 0(a5) +8000e0e8: 6f f0 df e7 j -388 +8000e0ec: 93 77 0a 20 andi a5, s4, 512 +8000e0f0: 63 8a 07 06 beqz a5, 116 +8000e0f4: 83 27 c1 00 lw a5, 12(sp) +8000e0f8: 13 08 00 00 mv a6, zero +8000e0fc: 23 26 d1 00 sw a3, 12(sp) +8000e100: 03 cc 07 00 lbu s8, 0(a5) +8000e104: 93 06 10 00 addi a3, zero, 1 +8000e108: 6f f0 4f c2 j -3036 +8000e10c: 93 06 06 00 mv a3, a2 +8000e110: 6f f0 9f 9e j -1560 +8000e114: 93 07 90 00 addi a5, zero, 9 +8000e118: e3 e8 87 cd bltu a5, s8, -816 +8000e11c: 6f f0 df 85 j -1956 +8000e120: 13 06 41 05 addi a2, sp, 84 +8000e124: 93 05 10 00 addi a1, zero, 1 +8000e128: 93 06 00 00 mv a3, zero +8000e12c: 13 87 04 00 mv a4, s1 +8000e130: 6f f0 0f 9e j -3616 +8000e134: 13 0c 60 00 addi s8, zero, 6 +8000e138: 6f f0 9f f4 j -184 +8000e13c: 93 07 b1 03 addi a5, sp, 59 +8000e140: 23 26 f1 04 sw a5, 76(sp) +8000e144: 93 07 10 00 addi a5, zero, 1 +8000e148: 23 28 f1 04 sw a5, 80(sp) +8000e14c: 93 05 10 00 addi a1, zero, 1 +8000e150: 13 06 41 05 addi a2, sp, 84 +8000e154: 6f f0 8f 94 j -3768 +8000e158: 83 27 81 00 lw a5, 8(sp) +8000e15c: 23 90 f6 00 sh a5, 0(a3) +8000e160: 6f e0 df fc j -4148 +8000e164: 83 27 c1 00 lw a5, 12(sp) +8000e168: 13 08 00 00 mv a6, zero +8000e16c: 23 26 d1 00 sw a3, 12(sp) +8000e170: 03 ac 07 00 lw s8, 0(a5) +8000e174: 93 06 10 00 addi a3, zero, 1 +8000e178: 6f f0 4f bb j -3148 +8000e17c: 83 27 c1 00 lw a5, 12(sp) +8000e180: 13 08 00 00 mv a6, zero +8000e184: 23 26 c1 00 sw a2, 12(sp) +8000e188: 03 ac 07 00 lw s8, 0(a5) +8000e18c: 6f f0 9f dd j -552 +8000e190: 83 27 c1 00 lw a5, 12(sp) +8000e194: 13 08 00 00 mv a6, zero +8000e198: 23 26 d1 00 sw a3, 12(sp) +8000e19c: 03 ac 07 00 lw s8, 0(a5) +8000e1a0: 6f f0 4f b8 j -3196 +8000e1a4: 83 27 c1 00 lw a5, 12(sp) +8000e1a8: 23 26 d1 00 sw a3, 12(sp) +8000e1ac: 03 ac 07 00 lw s8, 0(a5) +8000e1b0: 13 58 fc 41 srai a6, s8, 31 +8000e1b4: 93 06 08 00 mv a3, a6 +8000e1b8: 6f f0 8f aa j -3416 +8000e1bc: 13 06 01 04 addi a2, sp, 64 +8000e1c0: 93 85 09 00 mv a1, s3 +8000e1c4: 13 85 0a 00 mv a0, s5 +8000e1c8: ef e0 5f d6 jal -4764 +8000e1cc: 6f f0 8f 9c j -3640 +8000e1d0: 13 8c 0c 00 mv s8, s9 +8000e1d4: 23 26 d1 00 sw a3, 12(sp) +8000e1d8: 93 0c 00 00 mv s9, zero +8000e1dc: 6f f0 0f ac j -3392 +8000e1e0: 13 05 06 00 mv a0, a2 +8000e1e4: 6f f0 1f a8 j -1408 +8000e1e8: 93 85 16 00 addi a1, a3, 1 +8000e1ec: 6f f0 cf c1 j -3044 +8000e1f0: 13 8a 0d 00 mv s4, s11 +8000e1f4: 6f f0 4f a9 j -3436 +8000e1f8: 93 07 f0 ff addi a5, zero, -1 +8000e1fc: 23 24 f1 00 sw a5, 8(sp) +8000e200: 6f f0 0f 9a j -3680 +8000e204: 13 0f 06 00 mv t5, a2 +8000e208: 13 85 05 00 mv a0, a1 +8000e20c: 6f f0 df 81 j -2020 +8000e210: 83 27 c1 00 lw a5, 12(sp) +8000e214: 83 ac 07 00 lw s9, 0(a5) +8000e218: 93 87 47 00 addi a5, a5, 4 +8000e21c: 63 d4 0c 00 bgez s9, 8 +8000e220: 93 0c f0 ff addi s9, zero, -1 +8000e224: 83 46 1d 00 lbu a3, 1(s10) +8000e228: 23 26 f1 00 sw a5, 12(sp) +8000e22c: 13 8d 05 00 mv s10, a1 +8000e230: 6f e0 5f fa j -4188 + +8000e234 vfiprintf: +8000e234: 37 87 01 80 lui a4, 524312 +8000e238: 93 07 05 00 mv a5, a0 +8000e23c: 03 25 c7 b9 lw a0, -1124(a4) +8000e240: 93 06 06 00 mv a3, a2 +8000e244: 13 86 05 00 mv a2, a1 +8000e248: 93 85 07 00 mv a1, a5 +8000e24c: 6f e0 9f de j -4632 + +8000e250 __sbprintf: +8000e250: 83 d7 c5 00 lhu a5, 12(a1) +8000e254: 03 ae 45 06 lw t3, 100(a1) +8000e258: 03 d3 e5 00 lhu t1, 14(a1) +8000e25c: 83 a8 c5 01 lw a7, 28(a1) +8000e260: 03 a8 45 02 lw a6, 36(a1) +8000e264: 13 01 01 b8 addi sp, sp, -1152 +8000e268: 93 f7 d7 ff andi a5, a5, -3 +8000e26c: 13 07 00 40 addi a4, zero, 1024 +8000e270: 23 2c 81 46 sw s0, 1144(sp) +8000e274: 23 1a f1 00 sh a5, 20(sp) +8000e278: 13 84 05 00 mv s0, a1 +8000e27c: 93 07 01 07 addi a5, sp, 112 +8000e280: 93 05 81 00 addi a1, sp, 8 +8000e284: 23 2a 91 46 sw s1, 1140(sp) +8000e288: 23 28 21 47 sw s2, 1136(sp) +8000e28c: 23 2e 11 46 sw ra, 1148(sp) +8000e290: 13 09 05 00 mv s2, a0 +8000e294: 23 26 c1 07 sw t3, 108(sp) +8000e298: 23 1b 61 00 sh t1, 22(sp) +8000e29c: 23 22 11 03 sw a7, 36(sp) +8000e2a0: 23 26 01 03 sw a6, 44(sp) +8000e2a4: 23 24 f1 00 sw a5, 8(sp) +8000e2a8: 23 2c f1 00 sw a5, 24(sp) +8000e2ac: 23 28 e1 00 sw a4, 16(sp) +8000e2b0: 23 2e e1 00 sw a4, 28(sp) +8000e2b4: 23 20 01 02 sw zero, 32(sp) +8000e2b8: ef e0 df d7 jal -4740 +8000e2bc: 93 04 05 00 mv s1, a0 +8000e2c0: 63 5c 05 02 bgez a0, 56 +8000e2c4: 83 57 41 01 lhu a5, 20(sp) +8000e2c8: 93 f7 07 04 andi a5, a5, 64 +8000e2cc: 63 88 07 00 beqz a5, 16 +8000e2d0: 83 57 c4 00 lhu a5, 12(s0) +8000e2d4: 93 e7 07 04 ori a5, a5, 64 +8000e2d8: 23 16 f4 00 sh a5, 12(s0) +8000e2dc: 83 20 c1 47 lw ra, 1148(sp) +8000e2e0: 03 24 81 47 lw s0, 1144(sp) +8000e2e4: 03 29 01 47 lw s2, 1136(sp) +8000e2e8: 13 85 04 00 mv a0, s1 +8000e2ec: 83 24 41 47 lw s1, 1140(sp) +8000e2f0: 13 01 01 48 addi sp, sp, 1152 +8000e2f4: 67 80 00 00 ret +8000e2f8: 93 05 81 00 addi a1, sp, 8 +8000e2fc: 13 05 09 00 mv a0, s2 +8000e300: ef 00 00 42 jal 1056 +8000e304: e3 00 05 fc beqz a0, -64 +8000e308: 93 04 f0 ff addi s1, zero, -1 +8000e30c: 6f f0 9f fb j -72 + +8000e310 _wctomb_r: +8000e310: b7 87 01 80 lui a5, 524312 +8000e314: 03 a3 87 ae lw t1, -1304(a5) +8000e318: 67 00 03 00 jr t1 + +8000e31c __ascii_wctomb: +8000e31c: 63 84 05 02 beqz a1, 40 +8000e320: 93 07 f0 0f addi a5, zero, 255 +8000e324: 63 e8 c7 00 bltu a5, a2, 16 +8000e328: 23 80 c5 00 sb a2, 0(a1) +8000e32c: 13 05 10 00 addi a0, zero, 1 +8000e330: 67 80 00 00 ret +8000e334: 93 07 a0 08 addi a5, zero, 138 +8000e338: 23 20 f5 00 sw a5, 0(a0) +8000e33c: 13 05 f0 ff addi a0, zero, -1 +8000e340: 67 80 00 00 ret +8000e344: 13 05 00 00 mv a0, zero +8000e348: 67 80 00 00 ret + +8000e34c __swsetup_r: +8000e34c: b7 87 01 80 lui a5, 524312 +8000e350: 83 a7 c7 b9 lw a5, -1124(a5) +8000e354: 13 01 01 ff addi sp, sp, -16 +8000e358: 23 24 81 00 sw s0, 8(sp) +8000e35c: 23 22 91 00 sw s1, 4(sp) +8000e360: 23 26 11 00 sw ra, 12(sp) +8000e364: 93 04 05 00 mv s1, a0 +8000e368: 13 84 05 00 mv s0, a1 +8000e36c: 63 86 07 00 beqz a5, 12 +8000e370: 03 a7 87 03 lw a4, 56(a5) +8000e374: 63 00 07 0e beqz a4, 224 +8000e378: 03 17 c4 00 lh a4, 12(s0) +8000e37c: 93 17 07 01 slli a5, a4, 16 +8000e380: 93 76 87 00 andi a3, a4, 8 +8000e384: 93 d7 07 01 srli a5, a5, 16 +8000e388: 63 80 06 04 beqz a3, 64 +8000e38c: 83 26 04 01 lw a3, 16(s0) +8000e390: 63 80 06 06 beqz a3, 96 +8000e394: 13 f6 17 00 andi a2, a5, 1 +8000e398: 63 04 06 08 beqz a2, 136 +8000e39c: 03 26 44 01 lw a2, 20(s0) +8000e3a0: 23 24 04 00 sw zero, 8(s0) +8000e3a4: 13 05 00 00 mv a0, zero +8000e3a8: 33 06 c0 40 neg a2, a2 +8000e3ac: 23 2c c4 00 sw a2, 24(s0) +8000e3b0: 63 86 06 08 beqz a3, 140 +8000e3b4: 83 20 c1 00 lw ra, 12(sp) +8000e3b8: 03 24 81 00 lw s0, 8(sp) +8000e3bc: 83 24 41 00 lw s1, 4(sp) +8000e3c0: 13 01 01 01 addi sp, sp, 16 +8000e3c4: 67 80 00 00 ret +8000e3c8: 93 f6 07 01 andi a3, a5, 16 +8000e3cc: 63 84 06 0c beqz a3, 200 +8000e3d0: 93 f7 47 00 andi a5, a5, 4 +8000e3d4: 63 96 07 08 bnez a5, 140 +8000e3d8: 83 26 04 01 lw a3, 16(s0) +8000e3dc: 13 67 87 00 ori a4, a4, 8 +8000e3e0: 93 17 07 01 slli a5, a4, 16 +8000e3e4: 23 16 e4 00 sh a4, 12(s0) +8000e3e8: 93 d7 07 01 srli a5, a5, 16 +8000e3ec: e3 94 06 fa bnez a3, -88 +8000e3f0: 13 f6 07 28 andi a2, a5, 640 +8000e3f4: 93 05 00 20 addi a1, zero, 512 +8000e3f8: e3 0e b6 f8 beq a2, a1, -100 +8000e3fc: 93 05 04 00 mv a1, s0 +8000e400: 13 85 04 00 mv a0, s1 +8000e404: ef 00 90 7b jal 4024 +8000e408: 03 17 c4 00 lh a4, 12(s0) +8000e40c: 83 26 04 01 lw a3, 16(s0) +8000e410: 93 17 07 01 slli a5, a4, 16 +8000e414: 93 d7 07 01 srli a5, a5, 16 +8000e418: 13 f6 17 00 andi a2, a5, 1 +8000e41c: e3 10 06 f8 bnez a2, -128 +8000e420: 13 f6 27 00 andi a2, a5, 2 +8000e424: 93 05 00 00 mv a1, zero +8000e428: 63 14 06 00 bnez a2, 8 +8000e42c: 83 25 44 01 lw a1, 20(s0) +8000e430: 23 24 b4 00 sw a1, 8(s0) +8000e434: 13 05 00 00 mv a0, zero +8000e438: e3 9e 06 f6 bnez a3, -132 +8000e43c: 93 f7 07 08 andi a5, a5, 128 +8000e440: e3 8a 07 f6 beqz a5, -140 +8000e444: 13 67 07 04 ori a4, a4, 64 +8000e448: 23 16 e4 00 sh a4, 12(s0) +8000e44c: 13 05 f0 ff addi a0, zero, -1 +8000e450: 6f f0 5f f6 j -156 +8000e454: 13 85 07 00 mv a0, a5 +8000e458: ef 00 40 67 jal 1652 +8000e45c: 6f f0 df f1 j -228 +8000e460: 83 25 04 03 lw a1, 48(s0) +8000e464: 63 8e 05 00 beqz a1, 28 +8000e468: 93 07 04 04 addi a5, s0, 64 +8000e46c: 63 88 f5 00 beq a1, a5, 16 +8000e470: 13 85 04 00 mv a0, s1 +8000e474: ef 80 8f 89 jal -32616 +8000e478: 03 17 c4 00 lh a4, 12(s0) +8000e47c: 23 28 04 02 sw zero, 48(s0) +8000e480: 83 26 04 01 lw a3, 16(s0) +8000e484: 13 77 b7 fd andi a4, a4, -37 +8000e488: 23 22 04 00 sw zero, 4(s0) +8000e48c: 23 20 d4 00 sw a3, 0(s0) +8000e490: 6f f0 df f4 j -180 +8000e494: 93 07 90 00 addi a5, zero, 9 +8000e498: 23 a0 f4 00 sw a5, 0(s1) +8000e49c: 13 67 07 04 ori a4, a4, 64 +8000e4a0: 23 16 e4 00 sh a4, 12(s0) +8000e4a4: 13 05 f0 ff addi a0, zero, -1 +8000e4a8: 6f f0 df f0 j -244 + +8000e4ac abort: +8000e4ac: 13 01 01 ff addi sp, sp, -16 +8000e4b0: 13 05 60 00 addi a0, zero, 6 +8000e4b4: 23 26 11 00 sw ra, 12(sp) +8000e4b8: ef 10 40 2a jal 4772 +8000e4bc: 13 05 10 00 addi a0, zero, 1 +8000e4c0: ef 40 0f fe jal -47136 + +8000e4c4 __sflush_r: +8000e4c4: 83 97 c5 00 lh a5, 12(a1) +8000e4c8: 13 01 01 fe addi sp, sp, -32 +8000e4cc: 23 2c 81 00 sw s0, 24(sp) +8000e4d0: 23 26 31 01 sw s3, 12(sp) +8000e4d4: 23 2e 11 00 sw ra, 28(sp) +8000e4d8: 23 2a 91 00 sw s1, 20(sp) +8000e4dc: 23 28 21 01 sw s2, 16(sp) +8000e4e0: 93 f6 87 00 andi a3, a5, 8 +8000e4e4: 13 84 05 00 mv s0, a1 +8000e4e8: 93 09 05 00 mv s3, a0 +8000e4ec: 63 9a 06 10 bnez a3, 276 +8000e4f0: 37 17 00 00 lui a4, 1 +8000e4f4: 13 07 07 80 addi a4, a4, -2048 +8000e4f8: 83 a6 45 00 lw a3, 4(a1) +8000e4fc: b3 e7 e7 00 or a5, a5, a4 +8000e500: 23 96 f5 00 sh a5, 12(a1) +8000e504: 63 54 d0 18 blez a3, 392 +8000e508: 03 27 84 02 lw a4, 40(s0) +8000e50c: 63 0a 07 0c beqz a4, 212 +8000e510: 83 a4 09 00 lw s1, 0(s3) +8000e514: 93 96 07 01 slli a3, a5, 16 +8000e518: 23 a0 09 00 sw zero, 0(s3) +8000e51c: 13 96 37 01 slli a2, a5, 19 +8000e520: 83 25 c4 01 lw a1, 28(s0) +8000e524: 93 d6 06 01 srli a3, a3, 16 +8000e528: 63 48 06 16 bltz a2, 368 +8000e52c: 93 06 10 00 addi a3, zero, 1 +8000e530: 13 06 00 00 mv a2, zero +8000e534: 13 85 09 00 mv a0, s3 +8000e538: e7 00 07 00 jalr a4 +8000e53c: 93 07 f0 ff addi a5, zero, -1 +8000e540: 63 0c f5 18 beq a0, a5, 408 +8000e544: 83 56 c4 00 lhu a3, 12(s0) +8000e548: 03 27 84 02 lw a4, 40(s0) +8000e54c: 83 25 c4 01 lw a1, 28(s0) +8000e550: 93 f6 46 00 andi a3, a3, 4 +8000e554: 63 8e 06 00 beqz a3, 28 +8000e558: 83 26 44 00 lw a3, 4(s0) +8000e55c: 83 27 04 03 lw a5, 48(s0) +8000e560: 33 05 d5 40 sub a0, a0, a3 +8000e564: 63 86 07 00 beqz a5, 12 +8000e568: 83 27 c4 03 lw a5, 60(s0) +8000e56c: 33 05 f5 40 sub a0, a0, a5 +8000e570: 13 06 05 00 mv a2, a0 +8000e574: 93 06 00 00 mv a3, zero +8000e578: 13 85 09 00 mv a0, s3 +8000e57c: e7 00 07 00 jalr a4 +8000e580: 93 07 f0 ff addi a5, zero, -1 +8000e584: 63 1e f5 10 bne a0, a5, 284 +8000e588: 03 a7 09 00 lw a4, 0(s3) +8000e58c: 83 17 c4 00 lh a5, 12(s0) +8000e590: 63 08 07 16 beqz a4, 368 +8000e594: 93 06 d0 01 addi a3, zero, 29 +8000e598: 63 06 d7 00 beq a4, a3, 12 +8000e59c: 93 06 60 01 addi a3, zero, 22 +8000e5a0: 63 14 d7 0c bne a4, a3, 200 +8000e5a4: 83 26 04 01 lw a3, 16(s0) +8000e5a8: 37 f7 ff ff lui a4, 1048575 +8000e5ac: 13 07 f7 7f addi a4, a4, 2047 +8000e5b0: b3 f7 e7 00 and a5, a5, a4 +8000e5b4: 23 16 f4 00 sh a5, 12(s0) +8000e5b8: 23 22 04 00 sw zero, 4(s0) +8000e5bc: 23 20 d4 00 sw a3, 0(s0) +8000e5c0: 83 25 04 03 lw a1, 48(s0) +8000e5c4: 23 a0 99 00 sw s1, 0(s3) +8000e5c8: 63 8c 05 00 beqz a1, 24 +8000e5cc: 93 07 04 04 addi a5, s0, 64 +8000e5d0: 63 86 f5 00 beq a1, a5, 12 +8000e5d4: 13 85 09 00 mv a0, s3 +8000e5d8: ef 70 5f f3 jal -32972 +8000e5dc: 23 28 04 02 sw zero, 48(s0) +8000e5e0: 13 05 00 00 mv a0, zero +8000e5e4: 83 20 c1 01 lw ra, 28(sp) +8000e5e8: 03 24 81 01 lw s0, 24(sp) +8000e5ec: 83 24 41 01 lw s1, 20(sp) +8000e5f0: 03 29 01 01 lw s2, 16(sp) +8000e5f4: 83 29 c1 00 lw s3, 12(sp) +8000e5f8: 13 01 01 02 addi sp, sp, 32 +8000e5fc: 67 80 00 00 ret +8000e600: 03 a9 05 01 lw s2, 16(a1) +8000e604: e3 0e 09 fc beqz s2, -36 +8000e608: 83 a4 05 00 lw s1, 0(a1) +8000e60c: 13 97 07 01 slli a4, a5, 16 +8000e610: 13 57 07 01 srli a4, a4, 16 +8000e614: 13 77 37 00 andi a4, a4, 3 +8000e618: 23 a0 25 01 sw s2, 0(a1) +8000e61c: b3 84 24 41 sub s1, s1, s2 +8000e620: 93 07 00 00 mv a5, zero +8000e624: 63 14 07 00 bnez a4, 8 +8000e628: 83 a7 45 01 lw a5, 20(a1) +8000e62c: 23 24 f4 00 sw a5, 8(s0) +8000e630: 63 48 90 00 bgtz s1, 16 +8000e634: 6f f0 df fa j -84 +8000e638: 33 09 a9 00 add s2, s2, a0 +8000e63c: e3 52 90 fa blez s1, -92 +8000e640: 83 27 44 02 lw a5, 36(s0) +8000e644: 83 25 c4 01 lw a1, 28(s0) +8000e648: 93 86 04 00 mv a3, s1 +8000e64c: 13 06 09 00 mv a2, s2 +8000e650: 13 85 09 00 mv a0, s3 +8000e654: e7 80 07 00 jalr a5 +8000e658: b3 84 a4 40 sub s1, s1, a0 +8000e65c: e3 4e a0 fc bgtz a0, -36 +8000e660: 83 57 c4 00 lhu a5, 12(s0) +8000e664: 13 05 f0 ff addi a0, zero, -1 +8000e668: 93 e7 07 04 ori a5, a5, 64 +8000e66c: 83 20 c1 01 lw ra, 28(sp) +8000e670: 23 16 f4 00 sh a5, 12(s0) +8000e674: 03 24 81 01 lw s0, 24(sp) +8000e678: 83 24 41 01 lw s1, 20(sp) +8000e67c: 03 29 01 01 lw s2, 16(sp) +8000e680: 83 29 c1 00 lw s3, 12(sp) +8000e684: 13 01 01 02 addi sp, sp, 32 +8000e688: 67 80 00 00 ret +8000e68c: 03 a7 c5 03 lw a4, 60(a1) +8000e690: e3 4c e0 e6 bgtz a4, -392 +8000e694: 6f f0 df f4 j -180 +8000e698: 03 25 04 05 lw a0, 80(s0) +8000e69c: 6f f0 5f eb j -332 +8000e6a0: 83 57 c4 00 lhu a5, 12(s0) +8000e6a4: 37 f7 ff ff lui a4, 1048575 +8000e6a8: 13 07 f7 7f addi a4, a4, 2047 +8000e6ac: b3 f7 e7 00 and a5, a5, a4 +8000e6b0: 83 26 04 01 lw a3, 16(s0) +8000e6b4: 93 97 07 01 slli a5, a5, 16 +8000e6b8: 93 d7 07 41 srai a5, a5, 16 +8000e6bc: 23 16 f4 00 sh a5, 12(s0) +8000e6c0: 23 22 04 00 sw zero, 4(s0) +8000e6c4: 23 20 d4 00 sw a3, 0(s0) +8000e6c8: 13 97 37 01 slli a4, a5, 19 +8000e6cc: e3 5a 07 ee bgez a4, -268 +8000e6d0: 23 28 a4 04 sw a0, 80(s0) +8000e6d4: 6f f0 df ee j -276 +8000e6d8: 83 a7 09 00 lw a5, 0(s3) +8000e6dc: e3 84 07 e6 beqz a5, -408 +8000e6e0: 13 07 d0 01 addi a4, zero, 29 +8000e6e4: 63 88 e7 02 beq a5, a4, 48 +8000e6e8: 13 07 60 01 addi a4, zero, 22 +8000e6ec: 63 84 e7 02 beq a5, a4, 40 +8000e6f0: 83 57 c4 00 lhu a5, 12(s0) +8000e6f4: 93 e7 07 04 ori a5, a5, 64 +8000e6f8: 23 16 f4 00 sh a5, 12(s0) +8000e6fc: 6f f0 9f ee j -280 +8000e700: 37 f7 ff ff lui a4, 1048575 +8000e704: 13 07 f7 7f addi a4, a4, 2047 +8000e708: 83 26 04 01 lw a3, 16(s0) +8000e70c: b3 f7 e7 00 and a5, a5, a4 +8000e710: 6f f0 df fa j -84 +8000e714: 23 a0 99 00 sw s1, 0(s3) +8000e718: 13 05 00 00 mv a0, zero +8000e71c: 6f f0 9f ec j -312 + +8000e720 _fflush_r: +8000e720: 13 01 01 fe addi sp, sp, -32 +8000e724: 23 2c 81 00 sw s0, 24(sp) +8000e728: 23 2e 11 00 sw ra, 28(sp) +8000e72c: 13 04 05 00 mv s0, a0 +8000e730: 63 06 05 00 beqz a0, 12 +8000e734: 83 27 85 03 lw a5, 56(a0) +8000e738: 63 80 07 02 beqz a5, 32 +8000e73c: 83 97 c5 00 lh a5, 12(a1) +8000e740: 63 96 07 02 bnez a5, 44 +8000e744: 83 20 c1 01 lw ra, 28(sp) +8000e748: 03 24 81 01 lw s0, 24(sp) +8000e74c: 13 05 00 00 mv a0, zero +8000e750: 13 01 01 02 addi sp, sp, 32 +8000e754: 67 80 00 00 ret +8000e758: 23 26 b1 00 sw a1, 12(sp) +8000e75c: ef 00 00 37 jal 880 +8000e760: 83 25 c1 00 lw a1, 12(sp) +8000e764: 83 97 c5 00 lh a5, 12(a1) +8000e768: e3 8e 07 fc beqz a5, -36 +8000e76c: 13 05 04 00 mv a0, s0 +8000e770: 03 24 81 01 lw s0, 24(sp) +8000e774: 83 20 c1 01 lw ra, 28(sp) +8000e778: 13 01 01 02 addi sp, sp, 32 +8000e77c: 6f f0 9f d4 j -696 + +8000e780 fflush: +8000e780: 93 05 05 00 mv a1, a0 +8000e784: 63 08 05 00 beqz a0, 16 +8000e788: b7 87 01 80 lui a5, 524312 +8000e78c: 03 a5 c7 b9 lw a0, -1124(a5) +8000e790: 6f f0 1f f9 j -112 +8000e794: b7 87 01 80 lui a5, 524312 +8000e798: 03 a5 07 b9 lw a0, -1136(a5) +8000e79c: b7 e5 00 80 lui a1, 524302 +8000e7a0: 93 85 05 72 addi a1, a1, 1824 +8000e7a4: 6f 00 50 29 j 2708 + +8000e7a8 __fp_lock: +8000e7a8: 13 05 00 00 mv a0, zero +8000e7ac: 67 80 00 00 ret + +8000e7b0 _cleanup_r: +8000e7b0: b7 05 01 80 lui a1, 524304 +8000e7b4: 93 85 c5 ce addi a1, a1, -788 +8000e7b8: 6f 00 10 28 j 2688 + +8000e7bc __sinit.part.0: +8000e7bc: 13 01 01 fe addi sp, sp, -32 +8000e7c0: b7 e7 00 80 lui a5, 524302 +8000e7c4: 23 2e 11 00 sw ra, 28(sp) +8000e7c8: 23 2c 81 00 sw s0, 24(sp) +8000e7cc: 23 2a 91 00 sw s1, 20(sp) +8000e7d0: 23 28 21 01 sw s2, 16(sp) +8000e7d4: 23 26 31 01 sw s3, 12(sp) +8000e7d8: 23 24 41 01 sw s4, 8(sp) +8000e7dc: 23 22 51 01 sw s5, 4(sp) +8000e7e0: 23 20 61 01 sw s6, 0(sp) +8000e7e4: 03 24 45 00 lw s0, 4(a0) +8000e7e8: 93 87 07 7b addi a5, a5, 1968 +8000e7ec: 23 2e f5 02 sw a5, 60(a0) +8000e7f0: 13 07 c5 2e addi a4, a0, 748 +8000e7f4: 93 07 30 00 addi a5, zero, 3 +8000e7f8: 23 24 e5 2e sw a4, 744(a0) +8000e7fc: 23 22 f5 2e sw a5, 740(a0) +8000e800: 23 20 05 2e sw zero, 736(a0) +8000e804: 93 07 40 00 addi a5, zero, 4 +8000e808: 13 09 05 00 mv s2, a0 +8000e80c: 23 26 f4 00 sw a5, 12(s0) +8000e810: 13 06 80 00 addi a2, zero, 8 +8000e814: 93 05 00 00 mv a1, zero +8000e818: 23 22 04 06 sw zero, 100(s0) +8000e81c: 23 20 04 00 sw zero, 0(s0) +8000e820: 23 22 04 00 sw zero, 4(s0) +8000e824: 23 24 04 00 sw zero, 8(s0) +8000e828: 23 28 04 00 sw zero, 16(s0) +8000e82c: 23 2a 04 00 sw zero, 20(s0) +8000e830: 23 2c 04 00 sw zero, 24(s0) +8000e834: 13 05 c4 05 addi a0, s0, 92 +8000e838: ef 40 1f c7 jal -45968 +8000e83c: 37 0b 01 80 lui s6, 524304 +8000e840: 83 24 89 00 lw s1, 8(s2) +8000e844: b7 0a 01 80 lui s5, 524304 +8000e848: 37 0a 01 80 lui s4, 524304 +8000e84c: b7 09 01 80 lui s3, 524304 +8000e850: 13 0b cb 81 addi s6, s6, -2020 +8000e854: 93 8a 0a 88 addi s5, s5, -1920 +8000e858: 13 0a 8a 90 addi s4, s4, -1784 +8000e85c: 93 89 09 97 addi s3, s3, -1680 +8000e860: b7 07 01 00 lui a5, 16 +8000e864: 23 20 64 03 sw s6, 32(s0) +8000e868: 23 22 54 03 sw s5, 36(s0) +8000e86c: 23 24 44 03 sw s4, 40(s0) +8000e870: 23 26 34 03 sw s3, 44(s0) +8000e874: 23 2e 84 00 sw s0, 28(s0) +8000e878: 93 87 97 00 addi a5, a5, 9 +8000e87c: 23 a6 f4 00 sw a5, 12(s1) +8000e880: 13 06 80 00 addi a2, zero, 8 +8000e884: 93 05 00 00 mv a1, zero +8000e888: 23 a2 04 06 sw zero, 100(s1) +8000e88c: 23 a0 04 00 sw zero, 0(s1) +8000e890: 23 a2 04 00 sw zero, 4(s1) +8000e894: 23 a4 04 00 sw zero, 8(s1) +8000e898: 23 a8 04 00 sw zero, 16(s1) +8000e89c: 23 aa 04 00 sw zero, 20(s1) +8000e8a0: 23 ac 04 00 sw zero, 24(s1) +8000e8a4: 13 85 c4 05 addi a0, s1, 92 +8000e8a8: ef 40 1f c0 jal -46080 +8000e8ac: 03 24 c9 00 lw s0, 12(s2) +8000e8b0: b7 07 02 00 lui a5, 32 +8000e8b4: 23 a0 64 03 sw s6, 32(s1) +8000e8b8: 23 a2 54 03 sw s5, 36(s1) +8000e8bc: 23 a4 44 03 sw s4, 40(s1) +8000e8c0: 23 a6 34 03 sw s3, 44(s1) +8000e8c4: 23 ae 94 00 sw s1, 28(s1) +8000e8c8: 93 87 27 01 addi a5, a5, 18 +8000e8cc: 23 26 f4 00 sw a5, 12(s0) +8000e8d0: 23 22 04 06 sw zero, 100(s0) +8000e8d4: 23 20 04 00 sw zero, 0(s0) +8000e8d8: 23 22 04 00 sw zero, 4(s0) +8000e8dc: 23 24 04 00 sw zero, 8(s0) +8000e8e0: 23 28 04 00 sw zero, 16(s0) +8000e8e4: 23 2a 04 00 sw zero, 20(s0) +8000e8e8: 23 2c 04 00 sw zero, 24(s0) +8000e8ec: 13 05 c4 05 addi a0, s0, 92 +8000e8f0: 13 06 80 00 addi a2, zero, 8 +8000e8f4: 93 05 00 00 mv a1, zero +8000e8f8: ef 40 1f bb jal -46160 +8000e8fc: 83 20 c1 01 lw ra, 28(sp) +8000e900: 23 20 64 03 sw s6, 32(s0) +8000e904: 23 22 54 03 sw s5, 36(s0) +8000e908: 23 24 44 03 sw s4, 40(s0) +8000e90c: 23 26 34 03 sw s3, 44(s0) +8000e910: 23 2e 84 00 sw s0, 28(s0) +8000e914: 03 24 81 01 lw s0, 24(sp) +8000e918: 93 07 10 00 addi a5, zero, 1 +8000e91c: 23 2c f9 02 sw a5, 56(s2) +8000e920: 83 24 41 01 lw s1, 20(sp) +8000e924: 03 29 01 01 lw s2, 16(sp) +8000e928: 83 29 c1 00 lw s3, 12(sp) +8000e92c: 03 2a 81 00 lw s4, 8(sp) +8000e930: 83 2a 41 00 lw s5, 4(sp) +8000e934: 03 2b 01 00 lw s6, 0(sp) +8000e938: 13 01 01 02 addi sp, sp, 32 +8000e93c: 67 80 00 00 ret + +8000e940 __fp_unlock: +8000e940: 13 05 00 00 mv a0, zero +8000e944: 67 80 00 00 ret + +8000e948 __sfmoreglue: +8000e948: 13 01 01 ff addi sp, sp, -16 +8000e94c: 23 22 91 00 sw s1, 4(sp) +8000e950: 13 06 80 06 addi a2, zero, 104 +8000e954: 93 84 f5 ff addi s1, a1, -1 +8000e958: b3 84 c4 02 mul s1, s1, a2 +8000e95c: 23 20 21 01 sw s2, 0(sp) +8000e960: 13 89 05 00 mv s2, a1 +8000e964: 23 24 81 00 sw s0, 8(sp) +8000e968: 23 26 11 00 sw ra, 12(sp) +8000e96c: 93 85 44 07 addi a1, s1, 116 +8000e970: ef a0 1f a7 jal -21904 +8000e974: 13 04 05 00 mv s0, a0 +8000e978: 63 00 05 02 beqz a0, 32 +8000e97c: 13 05 c5 00 addi a0, a0, 12 +8000e980: 23 20 04 00 sw zero, 0(s0) +8000e984: 23 22 24 01 sw s2, 4(s0) +8000e988: 23 24 a4 00 sw a0, 8(s0) +8000e98c: 13 86 84 06 addi a2, s1, 104 +8000e990: 93 05 00 00 mv a1, zero +8000e994: ef 40 5f b1 jal -46316 +8000e998: 83 20 c1 00 lw ra, 12(sp) +8000e99c: 13 05 04 00 mv a0, s0 +8000e9a0: 03 24 81 00 lw s0, 8(sp) +8000e9a4: 83 24 41 00 lw s1, 4(sp) +8000e9a8: 03 29 01 00 lw s2, 0(sp) +8000e9ac: 13 01 01 01 addi sp, sp, 16 +8000e9b0: 67 80 00 00 ret + +8000e9b4 __sfp: +8000e9b4: 13 01 01 fe addi sp, sp, -32 +8000e9b8: b7 87 01 80 lui a5, 524312 +8000e9bc: 23 28 21 01 sw s2, 16(sp) +8000e9c0: 03 a9 07 b9 lw s2, -1136(a5) +8000e9c4: 23 26 31 01 sw s3, 12(sp) +8000e9c8: 23 2e 11 00 sw ra, 28(sp) +8000e9cc: 83 27 89 03 lw a5, 56(s2) +8000e9d0: 23 2c 81 00 sw s0, 24(sp) +8000e9d4: 23 2a 91 00 sw s1, 20(sp) +8000e9d8: 93 09 05 00 mv s3, a0 +8000e9dc: 63 86 07 0a beqz a5, 172 +8000e9e0: 13 09 09 2e addi s2, s2, 736 +8000e9e4: 93 04 f0 ff addi s1, zero, -1 +8000e9e8: 83 27 49 00 lw a5, 4(s2) +8000e9ec: 03 24 89 00 lw s0, 8(s2) +8000e9f0: 93 87 f7 ff addi a5, a5, -1 +8000e9f4: 63 d8 07 00 bgez a5, 16 +8000e9f8: 6f 00 00 08 j 128 +8000e9fc: 13 04 84 06 addi s0, s0, 104 +8000ea00: 63 8c 97 06 beq a5, s1, 120 +8000ea04: 03 17 c4 00 lh a4, 12(s0) +8000ea08: 93 87 f7 ff addi a5, a5, -1 +8000ea0c: e3 18 07 fe bnez a4, -16 +8000ea10: b7 07 ff ff lui a5, 1048560 +8000ea14: 93 87 17 00 addi a5, a5, 1 +8000ea18: 23 22 04 06 sw zero, 100(s0) +8000ea1c: 23 20 04 00 sw zero, 0(s0) +8000ea20: 23 22 04 00 sw zero, 4(s0) +8000ea24: 23 24 04 00 sw zero, 8(s0) +8000ea28: 23 26 f4 00 sw a5, 12(s0) +8000ea2c: 23 28 04 00 sw zero, 16(s0) +8000ea30: 23 2a 04 00 sw zero, 20(s0) +8000ea34: 23 2c 04 00 sw zero, 24(s0) +8000ea38: 13 06 80 00 addi a2, zero, 8 +8000ea3c: 93 05 00 00 mv a1, zero +8000ea40: 13 05 c4 05 addi a0, s0, 92 +8000ea44: ef 40 5f a6 jal -46492 +8000ea48: 23 28 04 02 sw zero, 48(s0) +8000ea4c: 23 2a 04 02 sw zero, 52(s0) +8000ea50: 23 22 04 04 sw zero, 68(s0) +8000ea54: 23 24 04 04 sw zero, 72(s0) +8000ea58: 83 20 c1 01 lw ra, 28(sp) +8000ea5c: 13 05 04 00 mv a0, s0 +8000ea60: 03 24 81 01 lw s0, 24(sp) +8000ea64: 83 24 41 01 lw s1, 20(sp) +8000ea68: 03 29 01 01 lw s2, 16(sp) +8000ea6c: 83 29 c1 00 lw s3, 12(sp) +8000ea70: 13 01 01 02 addi sp, sp, 32 +8000ea74: 67 80 00 00 ret +8000ea78: 03 24 09 00 lw s0, 0(s2) +8000ea7c: 63 0c 04 00 beqz s0, 24 +8000ea80: 13 09 04 00 mv s2, s0 +8000ea84: 6f f0 5f f6 j -156 +8000ea88: 13 05 09 00 mv a0, s2 +8000ea8c: ef f0 1f d3 jal -720 +8000ea90: 6f f0 1f f5 j -176 +8000ea94: 93 05 40 00 addi a1, zero, 4 +8000ea98: 13 85 09 00 mv a0, s3 +8000ea9c: ef f0 df ea jal -340 +8000eaa0: 23 20 a9 00 sw a0, 0(s2) +8000eaa4: 13 04 05 00 mv s0, a0 +8000eaa8: e3 1c 05 fc bnez a0, -40 +8000eaac: 93 07 c0 00 addi a5, zero, 12 +8000eab0: 23 a0 f9 00 sw a5, 0(s3) +8000eab4: 6f f0 5f fa j -92 + +8000eab8 _cleanup: +8000eab8: b7 87 01 80 lui a5, 524312 +8000eabc: 03 a5 07 b9 lw a0, -1136(a5) +8000eac0: b7 05 01 80 lui a1, 524304 +8000eac4: 93 85 c5 ce addi a1, a1, -788 +8000eac8: 6f 00 00 77 j 1904 + +8000eacc __sinit: +8000eacc: 83 27 85 03 lw a5, 56(a0) +8000ead0: 63 84 07 00 beqz a5, 8 +8000ead4: 67 80 00 00 ret +8000ead8: 6f f0 5f ce j -796 + +8000eadc __sfp_lock_acquire: +8000eadc: 67 80 00 00 ret + +8000eae0 __sfp_lock_release: +8000eae0: 67 80 00 00 ret + +8000eae4 __sinit_lock_acquire: +8000eae4: 67 80 00 00 ret + +8000eae8 __sinit_lock_release: +8000eae8: 67 80 00 00 ret + +8000eaec __fp_lock_all: +8000eaec: b7 87 01 80 lui a5, 524312 +8000eaf0: 03 a5 c7 b9 lw a0, -1124(a5) +8000eaf4: b7 e5 00 80 lui a1, 524302 +8000eaf8: 93 85 85 7a addi a1, a1, 1960 +8000eafc: 6f 00 80 69 j 1688 + +8000eb00 __fp_unlock_all: +8000eb00: b7 87 01 80 lui a5, 524312 +8000eb04: 03 a5 c7 b9 lw a0, -1124(a5) +8000eb08: b7 f5 00 80 lui a1, 524303 +8000eb0c: 93 85 05 94 addi a1, a1, -1728 +8000eb10: 6f 00 40 68 j 1668 + +8000eb14 __fputwc: +8000eb14: 13 01 01 fd addi sp, sp, -48 +8000eb18: 23 24 81 02 sw s0, 40(sp) +8000eb1c: 23 2e 31 01 sw s3, 28(sp) +8000eb20: 23 28 61 01 sw s6, 16(sp) +8000eb24: 23 26 11 02 sw ra, 44(sp) +8000eb28: 23 22 91 02 sw s1, 36(sp) +8000eb2c: 23 20 21 03 sw s2, 32(sp) +8000eb30: 23 2c 41 01 sw s4, 24(sp) +8000eb34: 23 2a 51 01 sw s5, 20(sp) +8000eb38: 13 0b 05 00 mv s6, a0 +8000eb3c: 93 89 05 00 mv s3, a1 +8000eb40: 13 04 06 00 mv s0, a2 +8000eb44: ef d0 1f a2 jal -9696 +8000eb48: 93 07 10 00 addi a5, zero, 1 +8000eb4c: 63 10 f5 02 bne a0, a5, 32 +8000eb50: 93 87 f9 ff addi a5, s3, -1 +8000eb54: 13 07 e0 0f addi a4, zero, 254 +8000eb58: 63 6a f7 00 bltu a4, a5, 20 +8000eb5c: 13 f7 f9 0f andi a4, s3, 255 +8000eb60: 23 06 e1 00 sb a4, 12(sp) +8000eb64: 13 09 10 00 addi s2, zero, 1 +8000eb68: 6f 00 c0 02 j 44 +8000eb6c: 93 06 c4 05 addi a3, s0, 92 +8000eb70: 13 86 09 00 mv a2, s3 +8000eb74: 93 05 c1 00 addi a1, sp, 12 +8000eb78: 13 05 0b 00 mv a0, s6 +8000eb7c: ef 00 90 79 jal 3992 +8000eb80: 93 07 f0 ff addi a5, zero, -1 +8000eb84: 13 09 05 00 mv s2, a0 +8000eb88: 63 04 f5 0a beq a0, a5, 168 +8000eb8c: 63 0e 05 08 beqz a0, 156 +8000eb90: 03 47 c1 00 lbu a4, 12(sp) +8000eb94: 93 04 00 00 mv s1, zero +8000eb98: 13 0a f0 ff addi s4, zero, -1 +8000eb9c: 93 0a a0 00 addi s5, zero, 10 +8000eba0: 6f 00 80 02 j 40 +8000eba4: 83 27 04 00 lw a5, 0(s0) +8000eba8: 93 86 17 00 addi a3, a5, 1 +8000ebac: 23 20 d4 00 sw a3, 0(s0) +8000ebb0: 23 80 e7 00 sb a4, 0(a5) +8000ebb4: 93 84 14 00 addi s1, s1, 1 +8000ebb8: 93 07 c1 00 addi a5, sp, 12 +8000ebbc: b3 87 97 00 add a5, a5, s1 +8000ebc0: 63 f4 24 07 bgeu s1, s2, 104 +8000ebc4: 03 c7 07 00 lbu a4, 0(a5) +8000ebc8: 83 27 84 00 lw a5, 8(s0) +8000ebcc: 93 87 f7 ff addi a5, a5, -1 +8000ebd0: 23 24 f4 00 sw a5, 8(s0) +8000ebd4: e3 d8 07 fc bgez a5, -48 +8000ebd8: 83 26 84 01 lw a3, 24(s0) +8000ebdc: 93 05 07 00 mv a1, a4 +8000ebe0: 13 06 04 00 mv a2, s0 +8000ebe4: 13 05 0b 00 mv a0, s6 +8000ebe8: 63 c4 d7 00 blt a5, a3, 8 +8000ebec: e3 1c 57 fb bne a4, s5, -72 +8000ebf0: ef 00 90 58 jal 3464 +8000ebf4: e3 10 45 fd bne a0, s4, -64 +8000ebf8: 13 09 f0 ff addi s2, zero, -1 +8000ebfc: 83 20 c1 02 lw ra, 44(sp) +8000ec00: 03 24 81 02 lw s0, 40(sp) +8000ec04: 83 24 41 02 lw s1, 36(sp) +8000ec08: 83 29 c1 01 lw s3, 28(sp) +8000ec0c: 03 2a 81 01 lw s4, 24(sp) +8000ec10: 83 2a 41 01 lw s5, 20(sp) +8000ec14: 03 2b 01 01 lw s6, 16(sp) +8000ec18: 13 05 09 00 mv a0, s2 +8000ec1c: 03 29 01 02 lw s2, 32(sp) +8000ec20: 13 01 01 03 addi sp, sp, 48 +8000ec24: 67 80 00 00 ret +8000ec28: 13 89 09 00 mv s2, s3 +8000ec2c: 6f f0 1f fd j -48 +8000ec30: 83 57 c4 00 lhu a5, 12(s0) +8000ec34: 93 e7 07 04 ori a5, a5, 64 +8000ec38: 23 16 f4 00 sh a5, 12(s0) +8000ec3c: 6f f0 1f fc j -64 + +8000ec40 _fputwc_r: +8000ec40: 83 17 c6 00 lh a5, 12(a2) +8000ec44: 13 97 27 01 slli a4, a5, 18 +8000ec48: 63 40 07 02 bltz a4, 32 +8000ec4c: 03 27 46 06 lw a4, 100(a2) +8000ec50: b7 26 00 00 lui a3, 2 +8000ec54: b3 e7 d7 00 or a5, a5, a3 +8000ec58: b7 26 00 00 lui a3, 2 +8000ec5c: 33 67 d7 00 or a4, a4, a3 +8000ec60: 23 16 f6 00 sh a5, 12(a2) +8000ec64: 23 22 e6 06 sw a4, 100(a2) +8000ec68: 6f f0 df ea j -340 + +8000ec6c fputwc: +8000ec6c: 13 01 01 fe addi sp, sp, -32 +8000ec70: b7 87 01 80 lui a5, 524312 +8000ec74: 23 2c 81 00 sw s0, 24(sp) +8000ec78: 03 a4 c7 b9 lw s0, -1124(a5) +8000ec7c: 23 2e 11 00 sw ra, 28(sp) +8000ec80: 13 86 05 00 mv a2, a1 +8000ec84: 93 05 05 00 mv a1, a0 +8000ec88: 63 06 04 00 beqz s0, 12 +8000ec8c: 83 27 84 03 lw a5, 56(s0) +8000ec90: 63 80 07 04 beqz a5, 64 +8000ec94: 83 17 c6 00 lh a5, 12(a2) +8000ec98: 13 97 27 01 slli a4, a5, 18 +8000ec9c: 63 40 07 02 bltz a4, 32 +8000eca0: 03 27 46 06 lw a4, 100(a2) +8000eca4: b7 26 00 00 lui a3, 2 +8000eca8: b3 e7 d7 00 or a5, a5, a3 +8000ecac: b7 26 00 00 lui a3, 2 +8000ecb0: 33 67 d7 00 or a4, a4, a3 +8000ecb4: 23 16 f6 00 sh a5, 12(a2) +8000ecb8: 23 22 e6 06 sw a4, 100(a2) +8000ecbc: 13 05 04 00 mv a0, s0 +8000ecc0: 03 24 81 01 lw s0, 24(sp) +8000ecc4: 83 20 c1 01 lw ra, 28(sp) +8000ecc8: 13 01 01 02 addi sp, sp, 32 +8000eccc: 6f f0 9f e4 j -440 +8000ecd0: 23 24 a1 00 sw a0, 8(sp) +8000ecd4: 13 05 04 00 mv a0, s0 +8000ecd8: 23 26 c1 00 sw a2, 12(sp) +8000ecdc: ef f0 1f df jal -528 +8000ece0: 03 26 c1 00 lw a2, 12(sp) +8000ece4: 83 25 81 00 lw a1, 8(sp) +8000ece8: 6f f0 df fa j -84 + +8000ecec __sfvwrite_r: +8000ecec: 83 27 86 00 lw a5, 8(a2) +8000ecf0: 63 8e 07 32 beqz a5, 828 +8000ecf4: 83 d7 c5 00 lhu a5, 12(a1) +8000ecf8: 13 01 01 fd addi sp, sp, -48 +8000ecfc: 23 24 81 02 sw s0, 40(sp) +8000ed00: 23 2c 41 01 sw s4, 24(sp) +8000ed04: 23 2a 51 01 sw s5, 20(sp) +8000ed08: 23 26 11 02 sw ra, 44(sp) +8000ed0c: 23 22 91 02 sw s1, 36(sp) +8000ed10: 23 20 21 03 sw s2, 32(sp) +8000ed14: 23 2e 31 01 sw s3, 28(sp) +8000ed18: 23 28 61 01 sw s6, 16(sp) +8000ed1c: 23 26 71 01 sw s7, 12(sp) +8000ed20: 23 24 81 01 sw s8, 8(sp) +8000ed24: 23 22 91 01 sw s9, 4(sp) +8000ed28: 23 20 a1 01 sw s10, 0(sp) +8000ed2c: 13 f7 87 00 andi a4, a5, 8 +8000ed30: 13 0a 06 00 mv s4, a2 +8000ed34: 93 0a 05 00 mv s5, a0 +8000ed38: 13 84 05 00 mv s0, a1 +8000ed3c: 63 06 07 08 beqz a4, 140 +8000ed40: 03 a7 05 01 lw a4, 16(a1) +8000ed44: 63 02 07 08 beqz a4, 132 +8000ed48: 13 f7 27 00 andi a4, a5, 2 +8000ed4c: 83 24 0a 00 lw s1, 0(s4) +8000ed50: 63 0c 07 08 beqz a4, 152 +8000ed54: 83 27 44 02 lw a5, 36(s0) +8000ed58: 83 25 c4 01 lw a1, 28(s0) +8000ed5c: 37 0b 00 80 lui s6, 524288 +8000ed60: 93 09 00 00 mv s3, zero +8000ed64: 13 09 00 00 mv s2, zero +8000ed68: 13 4b 0b c0 xori s6, s6, -1024 +8000ed6c: 13 86 09 00 mv a2, s3 +8000ed70: 13 85 0a 00 mv a0, s5 +8000ed74: 63 02 09 04 beqz s2, 68 +8000ed78: 93 06 09 00 mv a3, s2 +8000ed7c: 63 74 2b 01 bgeu s6, s2, 8 +8000ed80: 93 06 0b 00 mv a3, s6 +8000ed84: e7 80 07 00 jalr a5 +8000ed88: 63 58 a0 28 blez a0, 656 +8000ed8c: 83 27 8a 00 lw a5, 8(s4) +8000ed90: b3 89 a9 00 add s3, s3, a0 +8000ed94: 33 09 a9 40 sub s2, s2, a0 +8000ed98: 33 85 a7 40 sub a0, a5, a0 +8000ed9c: 23 24 aa 00 sw a0, 8(s4) +8000eda0: 63 0a 05 20 beqz a0, 532 +8000eda4: 83 27 44 02 lw a5, 36(s0) +8000eda8: 83 25 c4 01 lw a1, 28(s0) +8000edac: 13 86 09 00 mv a2, s3 +8000edb0: 13 85 0a 00 mv a0, s5 +8000edb4: e3 12 09 fc bnez s2, -60 +8000edb8: 83 a9 04 00 lw s3, 0(s1) +8000edbc: 03 a9 44 00 lw s2, 4(s1) +8000edc0: 93 84 84 00 addi s1, s1, 8 +8000edc4: 6f f0 9f fa j -88 +8000edc8: 93 05 04 00 mv a1, s0 +8000edcc: 13 85 0a 00 mv a0, s5 +8000edd0: ef f0 cf d7 jal -2692 +8000edd4: 63 1c 05 3a bnez a0, 952 +8000edd8: 83 57 c4 00 lhu a5, 12(s0) +8000eddc: 83 24 0a 00 lw s1, 0(s4) +8000ede0: 13 f7 27 00 andi a4, a5, 2 +8000ede4: e3 18 07 f6 bnez a4, -144 +8000ede8: 13 f7 17 00 andi a4, a5, 1 +8000edec: 63 14 07 24 bnez a4, 584 +8000edf0: 83 2c 84 00 lw s9, 8(s0) +8000edf4: 03 25 04 00 lw a0, 0(s0) +8000edf8: 37 0b 00 80 lui s6, 524288 +8000edfc: 93 4b eb ff xori s7, s6, -2 +8000ee00: 13 0c 00 00 mv s8, zero +8000ee04: 13 09 00 00 mv s2, zero +8000ee08: 13 4b fb ff not s6, s6 +8000ee0c: 63 0e 09 0e beqz s2, 252 +8000ee10: 13 f7 07 20 andi a4, a5, 512 +8000ee14: 63 0c 07 24 beqz a4, 600 +8000ee18: 13 8d 0c 00 mv s10, s9 +8000ee1c: 63 62 99 2f bltu s2, s9, 740 +8000ee20: 13 f7 07 48 andi a4, a5, 1152 +8000ee24: 63 0a 07 08 beqz a4, 148 +8000ee28: 83 29 44 01 lw s3, 20(s0) +8000ee2c: 83 25 04 01 lw a1, 16(s0) +8000ee30: 13 07 19 00 addi a4, s2, 1 +8000ee34: 93 96 19 00 slli a3, s3, 1 +8000ee38: b3 86 36 01 add a3, a3, s3 +8000ee3c: 93 d9 f6 01 srli s3, a3, 31 +8000ee40: 33 0d b5 40 sub s10, a0, a1 +8000ee44: b3 89 d9 00 add s3, s3, a3 +8000ee48: 93 d9 19 40 srai s3, s3, 1 +8000ee4c: 33 07 a7 01 add a4, a4, s10 +8000ee50: 13 86 09 00 mv a2, s3 +8000ee54: 63 f6 e9 00 bgeu s3, a4, 12 +8000ee58: 93 09 07 00 mv s3, a4 +8000ee5c: 13 06 07 00 mv a2, a4 +8000ee60: 93 f7 07 40 andi a5, a5, 1024 +8000ee64: 63 84 07 2e beqz a5, 744 +8000ee68: 93 05 06 00 mv a1, a2 +8000ee6c: 13 85 0a 00 mv a0, s5 +8000ee70: ef a0 0f d7 jal -23184 +8000ee74: 93 0c 05 00 mv s9, a0 +8000ee78: 63 02 05 30 beqz a0, 772 +8000ee7c: 83 25 04 01 lw a1, 16(s0) +8000ee80: 13 06 0d 00 mv a2, s10 +8000ee84: ef d0 8f f7 jal -10376 +8000ee88: 83 57 c4 00 lhu a5, 12(s0) +8000ee8c: 93 f7 f7 b7 andi a5, a5, -1153 +8000ee90: 93 e7 07 08 ori a5, a5, 128 +8000ee94: 23 16 f4 00 sh a5, 12(s0) +8000ee98: 33 85 ac 01 add a0, s9, s10 +8000ee9c: b3 87 a9 41 sub a5, s3, s10 +8000eea0: 23 28 94 01 sw s9, 16(s0) +8000eea4: 23 20 a4 00 sw a0, 0(s0) +8000eea8: 23 2a 34 01 sw s3, 20(s0) +8000eeac: 93 0c 09 00 mv s9, s2 +8000eeb0: 23 24 f4 00 sw a5, 8(s0) +8000eeb4: 13 0d 09 00 mv s10, s2 +8000eeb8: 13 06 0d 00 mv a2, s10 +8000eebc: 93 05 0c 00 mv a1, s8 +8000eec0: ef d0 9f 85 jal -10152 +8000eec4: 03 27 84 00 lw a4, 8(s0) +8000eec8: 83 27 04 00 lw a5, 0(s0) +8000eecc: 93 09 09 00 mv s3, s2 +8000eed0: b3 0c 97 41 sub s9, a4, s9 +8000eed4: b3 87 a7 01 add a5, a5, s10 +8000eed8: 23 24 94 01 sw s9, 8(s0) +8000eedc: 23 20 f4 00 sw a5, 0(s0) +8000eee0: 13 09 00 00 mv s2, zero +8000eee4: 03 26 8a 00 lw a2, 8(s4) +8000eee8: 33 0c 3c 01 add s8, s8, s3 +8000eeec: b3 09 36 41 sub s3, a2, s3 +8000eef0: 23 24 3a 01 sw s3, 8(s4) +8000eef4: 63 80 09 0c beqz s3, 192 +8000eef8: 83 2c 84 00 lw s9, 8(s0) +8000eefc: 03 25 04 00 lw a0, 0(s0) +8000ef00: 83 57 c4 00 lhu a5, 12(s0) +8000ef04: e3 16 09 f0 bnez s2, -244 +8000ef08: 03 ac 04 00 lw s8, 0(s1) +8000ef0c: 03 a9 44 00 lw s2, 4(s1) +8000ef10: 93 84 84 00 addi s1, s1, 8 +8000ef14: 6f f0 9f ef j -264 +8000ef18: 83 a9 44 00 lw s3, 4(s1) +8000ef1c: 03 ac 04 00 lw s8, 0(s1) +8000ef20: 93 84 84 00 addi s1, s1, 8 +8000ef24: e3 8a 09 fe beqz s3, -12 +8000ef28: 13 86 09 00 mv a2, s3 +8000ef2c: 93 05 a0 00 addi a1, zero, 10 +8000ef30: 13 05 0c 00 mv a0, s8 +8000ef34: ef a0 5f c6 jal -21404 +8000ef38: 63 04 05 12 beqz a0, 296 +8000ef3c: 13 05 15 00 addi a0, a0, 1 +8000ef40: 33 0b 85 41 sub s6, a0, s8 +8000ef44: 93 07 0b 00 mv a5, s6 +8000ef48: 93 8b 09 00 mv s7, s3 +8000ef4c: 63 f4 37 01 bgeu a5, s3, 8 +8000ef50: 93 8b 07 00 mv s7, a5 +8000ef54: 03 25 04 00 lw a0, 0(s0) +8000ef58: 83 27 04 01 lw a5, 16(s0) +8000ef5c: 83 26 44 01 lw a3, 20(s0) +8000ef60: 63 f8 a7 00 bgeu a5, a0, 16 +8000ef64: 03 29 84 00 lw s2, 8(s0) +8000ef68: 33 89 26 01 add s2, a3, s2 +8000ef6c: 63 42 79 09 blt s2, s7, 132 +8000ef70: 63 c8 db 1a blt s7, a3, 432 +8000ef74: 83 27 44 02 lw a5, 36(s0) +8000ef78: 83 25 c4 01 lw a1, 28(s0) +8000ef7c: 13 06 0c 00 mv a2, s8 +8000ef80: 13 85 0a 00 mv a0, s5 +8000ef84: e7 80 07 00 jalr a5 +8000ef88: 13 09 05 00 mv s2, a0 +8000ef8c: 63 56 a0 08 blez a0, 140 +8000ef90: 33 0b 2b 41 sub s6, s6, s2 +8000ef94: 13 05 10 00 addi a0, zero, 1 +8000ef98: 63 0a 0b 16 beqz s6, 372 +8000ef9c: 03 26 8a 00 lw a2, 8(s4) +8000efa0: 33 0c 2c 01 add s8, s8, s2 +8000efa4: b3 89 29 41 sub s3, s3, s2 +8000efa8: 33 09 26 41 sub s2, a2, s2 +8000efac: 23 24 2a 01 sw s2, 8(s4) +8000efb0: 63 1a 09 08 bnez s2, 148 +8000efb4: 13 05 00 00 mv a0, zero +8000efb8: 83 20 c1 02 lw ra, 44(sp) +8000efbc: 03 24 81 02 lw s0, 40(sp) +8000efc0: 83 24 41 02 lw s1, 36(sp) +8000efc4: 03 29 01 02 lw s2, 32(sp) +8000efc8: 83 29 c1 01 lw s3, 28(sp) +8000efcc: 03 2a 81 01 lw s4, 24(sp) +8000efd0: 83 2a 41 01 lw s5, 20(sp) +8000efd4: 03 2b 01 01 lw s6, 16(sp) +8000efd8: 83 2b c1 00 lw s7, 12(sp) +8000efdc: 03 2c 81 00 lw s8, 8(sp) +8000efe0: 83 2c 41 00 lw s9, 4(sp) +8000efe4: 03 2d 01 00 lw s10, 0(sp) +8000efe8: 13 01 01 03 addi sp, sp, 48 +8000efec: 67 80 00 00 ret +8000eff0: 93 05 0c 00 mv a1, s8 +8000eff4: 13 06 09 00 mv a2, s2 +8000eff8: ef d0 0f f2 jal -10464 +8000effc: 83 27 04 00 lw a5, 0(s0) +8000f000: 93 05 04 00 mv a1, s0 +8000f004: 13 85 0a 00 mv a0, s5 +8000f008: b3 87 27 01 add a5, a5, s2 +8000f00c: 23 20 f4 00 sw a5, 0(s0) +8000f010: ef f0 0f f1 jal -2288 +8000f014: e3 0e 05 f6 beqz a0, -132 +8000f018: 83 17 c4 00 lh a5, 12(s0) +8000f01c: 93 e7 07 04 ori a5, a5, 64 +8000f020: 23 16 f4 00 sh a5, 12(s0) +8000f024: 13 05 f0 ff addi a0, zero, -1 +8000f028: 6f f0 1f f9 j -112 +8000f02c: 13 05 00 00 mv a0, zero +8000f030: 67 80 00 00 ret +8000f034: 13 0b 00 00 mv s6, zero +8000f038: 13 05 00 00 mv a0, zero +8000f03c: 13 0c 00 00 mv s8, zero +8000f040: 93 09 00 00 mv s3, zero +8000f044: e3 8a 09 ec beqz s3, -300 +8000f048: e3 1e 05 ee bnez a0, -260 +8000f04c: 13 86 09 00 mv a2, s3 +8000f050: 93 05 a0 00 addi a1, zero, 10 +8000f054: 13 05 0c 00 mv a0, s8 +8000f058: ef a0 1f b4 jal -21696 +8000f05c: e3 10 05 ee bnez a0, -288 +8000f060: 93 87 19 00 addi a5, s3, 1 +8000f064: 13 8b 07 00 mv s6, a5 +8000f068: 6f f0 1f ee j -288 +8000f06c: 83 27 04 01 lw a5, 16(s0) +8000f070: 63 e2 a7 04 bltu a5, a0, 68 +8000f074: 83 27 44 01 lw a5, 20(s0) +8000f078: 63 6e f9 02 bltu s2, a5, 60 +8000f07c: 93 06 09 00 mv a3, s2 +8000f080: 63 f4 2b 01 bgeu s7, s2, 8 +8000f084: 93 06 0b 00 mv a3, s6 +8000f088: b3 c6 f6 02 div a3, a3, a5 +8000f08c: 03 27 44 02 lw a4, 36(s0) +8000f090: 83 25 c4 01 lw a1, 28(s0) +8000f094: 13 06 0c 00 mv a2, s8 +8000f098: 13 85 0a 00 mv a0, s5 +8000f09c: b3 86 f6 02 mul a3, a3, a5 +8000f0a0: e7 00 07 00 jalr a4 +8000f0a4: 93 09 05 00 mv s3, a0 +8000f0a8: e3 58 a0 f6 blez a0, -144 +8000f0ac: 33 09 39 41 sub s2, s2, s3 +8000f0b0: 6f f0 5f e3 j -460 +8000f0b4: 93 89 0c 00 mv s3, s9 +8000f0b8: 63 74 99 01 bgeu s2, s9, 8 +8000f0bc: 93 09 09 00 mv s3, s2 +8000f0c0: 13 86 09 00 mv a2, s3 +8000f0c4: 93 05 0c 00 mv a1, s8 +8000f0c8: ef d0 0f e5 jal -10672 +8000f0cc: 83 27 84 00 lw a5, 8(s0) +8000f0d0: 03 27 04 00 lw a4, 0(s0) +8000f0d4: b3 87 37 41 sub a5, a5, s3 +8000f0d8: 33 07 37 01 add a4, a4, s3 +8000f0dc: 23 24 f4 00 sw a5, 8(s0) +8000f0e0: 23 20 e4 00 sw a4, 0(s0) +8000f0e4: e3 94 07 fc bnez a5, -56 +8000f0e8: 93 05 04 00 mv a1, s0 +8000f0ec: 13 85 0a 00 mv a0, s5 +8000f0f0: ef f0 0f e3 jal -2512 +8000f0f4: e3 12 05 f2 bnez a0, -220 +8000f0f8: 33 09 39 41 sub s2, s2, s3 +8000f0fc: 6f f0 9f de j -536 +8000f100: 93 0c 09 00 mv s9, s2 +8000f104: 13 0d 09 00 mv s10, s2 +8000f108: 6f f0 1f db j -592 +8000f10c: 93 05 04 00 mv a1, s0 +8000f110: 13 85 0a 00 mv a0, s5 +8000f114: ef f0 cf e0 jal -2548 +8000f118: e3 02 05 e8 beqz a0, -380 +8000f11c: 6f f0 df ef j -260 +8000f120: 13 86 0b 00 mv a2, s7 +8000f124: 93 05 0c 00 mv a1, s8 +8000f128: ef d0 0f df jal -10768 +8000f12c: 83 27 84 00 lw a5, 8(s0) +8000f130: 03 26 04 00 lw a2, 0(s0) +8000f134: 13 89 0b 00 mv s2, s7 +8000f138: b3 87 77 41 sub a5, a5, s7 +8000f13c: 33 06 76 01 add a2, a2, s7 +8000f140: 23 24 f4 00 sw a5, 8(s0) +8000f144: 23 20 c4 00 sw a2, 0(s0) +8000f148: 6f f0 9f e4 j -440 +8000f14c: 13 85 0a 00 mv a0, s5 +8000f150: ef d0 8f ee jal -10520 +8000f154: 93 0c 05 00 mv s9, a0 +8000f158: e3 10 05 d4 bnez a0, -704 +8000f15c: 83 25 04 01 lw a1, 16(s0) +8000f160: 13 85 0a 00 mv a0, s5 +8000f164: ef 70 8f ba jal -35928 +8000f168: 83 17 c4 00 lh a5, 12(s0) +8000f16c: 13 07 c0 00 addi a4, zero, 12 +8000f170: 23 a0 ea 00 sw a4, 0(s5) +8000f174: 93 f7 f7 f7 andi a5, a5, -129 +8000f178: 6f f0 5f ea j -348 +8000f17c: 13 07 c0 00 addi a4, zero, 12 +8000f180: 83 17 c4 00 lh a5, 12(s0) +8000f184: 23 a0 ea 00 sw a4, 0(s5) +8000f188: 6f f0 5f e9 j -364 +8000f18c: 13 05 f0 ff addi a0, zero, -1 +8000f190: 6f f0 9f e2 j -472 + +8000f194 _fwalk: +8000f194: 13 01 01 fe addi sp, sp, -32 +8000f198: 23 28 21 01 sw s2, 16(sp) +8000f19c: 23 26 31 01 sw s3, 12(sp) +8000f1a0: 23 24 41 01 sw s4, 8(sp) +8000f1a4: 23 22 51 01 sw s5, 4(sp) +8000f1a8: 23 20 61 01 sw s6, 0(sp) +8000f1ac: 23 2e 11 00 sw ra, 28(sp) +8000f1b0: 23 2c 81 00 sw s0, 24(sp) +8000f1b4: 23 2a 91 00 sw s1, 20(sp) +8000f1b8: 13 8b 05 00 mv s6, a1 +8000f1bc: 93 0a 05 2e addi s5, a0, 736 +8000f1c0: 13 0a 00 00 mv s4, zero +8000f1c4: 93 09 10 00 addi s3, zero, 1 +8000f1c8: 13 09 f0 ff addi s2, zero, -1 +8000f1cc: 83 a4 4a 00 lw s1, 4(s5) +8000f1d0: 03 a4 8a 00 lw s0, 8(s5) +8000f1d4: 93 84 f4 ff addi s1, s1, -1 +8000f1d8: 63 c6 04 02 bltz s1, 44 +8000f1dc: 83 57 c4 00 lhu a5, 12(s0) +8000f1e0: 93 84 f4 ff addi s1, s1, -1 +8000f1e4: 63 fc f9 00 bgeu s3, a5, 24 +8000f1e8: 83 17 e4 00 lh a5, 14(s0) +8000f1ec: 13 05 04 00 mv a0, s0 +8000f1f0: 63 86 27 01 beq a5, s2, 12 +8000f1f4: e7 00 0b 00 jalr s6 +8000f1f8: 33 6a aa 00 or s4, s4, a0 +8000f1fc: 13 04 84 06 addi s0, s0, 104 +8000f200: e3 9e 24 fd bne s1, s2, -36 +8000f204: 83 aa 0a 00 lw s5, 0(s5) +8000f208: e3 92 0a fc bnez s5, -60 +8000f20c: 83 20 c1 01 lw ra, 28(sp) +8000f210: 03 24 81 01 lw s0, 24(sp) +8000f214: 83 24 41 01 lw s1, 20(sp) +8000f218: 03 29 01 01 lw s2, 16(sp) +8000f21c: 83 29 c1 00 lw s3, 12(sp) +8000f220: 83 2a 41 00 lw s5, 4(sp) +8000f224: 03 2b 01 00 lw s6, 0(sp) +8000f228: 13 05 0a 00 mv a0, s4 +8000f22c: 03 2a 81 00 lw s4, 8(sp) +8000f230: 13 01 01 02 addi sp, sp, 32 +8000f234: 67 80 00 00 ret + +8000f238 _fwalk_reent: +8000f238: 13 01 01 fd addi sp, sp, -48 +8000f23c: 23 20 21 03 sw s2, 32(sp) +8000f240: 23 2e 31 01 sw s3, 28(sp) +8000f244: 23 2c 41 01 sw s4, 24(sp) +8000f248: 23 2a 51 01 sw s5, 20(sp) +8000f24c: 23 28 61 01 sw s6, 16(sp) +8000f250: 23 26 71 01 sw s7, 12(sp) +8000f254: 23 26 11 02 sw ra, 44(sp) +8000f258: 23 24 81 02 sw s0, 40(sp) +8000f25c: 23 22 91 02 sw s1, 36(sp) +8000f260: 93 0a 05 00 mv s5, a0 +8000f264: 93 8b 05 00 mv s7, a1 +8000f268: 13 0b 05 2e addi s6, a0, 736 +8000f26c: 13 0a 00 00 mv s4, zero +8000f270: 93 09 10 00 addi s3, zero, 1 +8000f274: 13 09 f0 ff addi s2, zero, -1 +8000f278: 83 24 4b 00 lw s1, 4(s6) +8000f27c: 03 24 8b 00 lw s0, 8(s6) +8000f280: 93 84 f4 ff addi s1, s1, -1 +8000f284: 63 c8 04 02 bltz s1, 48 +8000f288: 83 57 c4 00 lhu a5, 12(s0) +8000f28c: 93 84 f4 ff addi s1, s1, -1 +8000f290: 63 fe f9 00 bgeu s3, a5, 28 +8000f294: 83 17 e4 00 lh a5, 14(s0) +8000f298: 93 05 04 00 mv a1, s0 +8000f29c: 13 85 0a 00 mv a0, s5 +8000f2a0: 63 86 27 01 beq a5, s2, 12 +8000f2a4: e7 80 0b 00 jalr s7 +8000f2a8: 33 6a aa 00 or s4, s4, a0 +8000f2ac: 13 04 84 06 addi s0, s0, 104 +8000f2b0: e3 9c 24 fd bne s1, s2, -40 +8000f2b4: 03 2b 0b 00 lw s6, 0(s6) +8000f2b8: e3 10 0b fc bnez s6, -64 +8000f2bc: 83 20 c1 02 lw ra, 44(sp) +8000f2c0: 03 24 81 02 lw s0, 40(sp) +8000f2c4: 83 24 41 02 lw s1, 36(sp) +8000f2c8: 03 29 01 02 lw s2, 32(sp) +8000f2cc: 83 29 c1 01 lw s3, 28(sp) +8000f2d0: 83 2a 41 01 lw s5, 20(sp) +8000f2d4: 03 2b 01 01 lw s6, 16(sp) +8000f2d8: 83 2b c1 00 lw s7, 12(sp) +8000f2dc: 13 05 0a 00 mv a0, s4 +8000f2e0: 03 2a 81 01 lw s4, 24(sp) +8000f2e4: 13 01 01 03 addi sp, sp, 48 +8000f2e8: 67 80 00 00 ret + +8000f2ec __swhatbuf_r: +8000f2ec: 13 01 01 f9 addi sp, sp, -112 +8000f2f0: 23 24 81 06 sw s0, 104(sp) +8000f2f4: 13 84 05 00 mv s0, a1 +8000f2f8: 83 95 e5 00 lh a1, 14(a1) +8000f2fc: 23 22 91 06 sw s1, 100(sp) +8000f300: 23 20 21 07 sw s2, 96(sp) +8000f304: 23 26 11 06 sw ra, 108(sp) +8000f308: 93 04 06 00 mv s1, a2 +8000f30c: 13 89 06 00 mv s2, a3 +8000f310: 63 ca 05 04 bltz a1, 84 +8000f314: 13 06 81 00 addi a2, sp, 8 +8000f318: ef 00 50 2f jal 2804 +8000f31c: 63 44 05 04 bltz a0, 72 +8000f320: 03 27 c1 00 lw a4, 12(sp) +8000f324: b7 f7 00 00 lui a5, 15 +8000f328: 83 20 c1 06 lw ra, 108(sp) +8000f32c: b3 f7 e7 00 and a5, a5, a4 +8000f330: 37 e7 ff ff lui a4, 1048574 +8000f334: b3 87 e7 00 add a5, a5, a4 +8000f338: 03 24 81 06 lw s0, 104(sp) +8000f33c: 93 b7 17 00 seqz a5, a5 +8000f340: 23 20 f9 00 sw a5, 0(s2) +8000f344: 93 07 00 40 addi a5, zero, 1024 +8000f348: 23 a0 f4 00 sw a5, 0(s1) +8000f34c: 37 15 00 00 lui a0, 1 +8000f350: 83 24 41 06 lw s1, 100(sp) +8000f354: 03 29 01 06 lw s2, 96(sp) +8000f358: 13 05 05 80 addi a0, a0, -2048 +8000f35c: 13 01 01 07 addi sp, sp, 112 +8000f360: 67 80 00 00 ret +8000f364: 83 57 c4 00 lhu a5, 12(s0) +8000f368: 23 20 09 00 sw zero, 0(s2) +8000f36c: 93 f7 07 08 andi a5, a5, 128 +8000f370: 63 84 07 02 beqz a5, 40 +8000f374: 83 20 c1 06 lw ra, 108(sp) +8000f378: 03 24 81 06 lw s0, 104(sp) +8000f37c: 93 07 00 04 addi a5, zero, 64 +8000f380: 23 a0 f4 00 sw a5, 0(s1) +8000f384: 03 29 01 06 lw s2, 96(sp) +8000f388: 83 24 41 06 lw s1, 100(sp) +8000f38c: 13 05 00 00 mv a0, zero +8000f390: 13 01 01 07 addi sp, sp, 112 +8000f394: 67 80 00 00 ret +8000f398: 83 20 c1 06 lw ra, 108(sp) +8000f39c: 03 24 81 06 lw s0, 104(sp) +8000f3a0: 93 07 00 40 addi a5, zero, 1024 +8000f3a4: 23 a0 f4 00 sw a5, 0(s1) +8000f3a8: 03 29 01 06 lw s2, 96(sp) +8000f3ac: 83 24 41 06 lw s1, 100(sp) +8000f3b0: 13 05 00 00 mv a0, zero +8000f3b4: 13 01 01 07 addi sp, sp, 112 +8000f3b8: 67 80 00 00 ret + +8000f3bc __smakebuf_r: +8000f3bc: 83 d7 c5 00 lhu a5, 12(a1) +8000f3c0: 13 01 01 fe addi sp, sp, -32 +8000f3c4: 23 2c 81 00 sw s0, 24(sp) +8000f3c8: 23 2e 11 00 sw ra, 28(sp) +8000f3cc: 23 2a 91 00 sw s1, 20(sp) +8000f3d0: 23 28 21 01 sw s2, 16(sp) +8000f3d4: 93 f7 27 00 andi a5, a5, 2 +8000f3d8: 13 84 05 00 mv s0, a1 +8000f3dc: 63 88 07 02 beqz a5, 48 +8000f3e0: 93 87 35 04 addi a5, a1, 67 +8000f3e4: 23 a0 f5 00 sw a5, 0(a1) +8000f3e8: 23 a8 f5 00 sw a5, 16(a1) +8000f3ec: 93 07 10 00 addi a5, zero, 1 +8000f3f0: 23 aa f5 00 sw a5, 20(a1) +8000f3f4: 83 20 c1 01 lw ra, 28(sp) +8000f3f8: 03 24 81 01 lw s0, 24(sp) +8000f3fc: 83 24 41 01 lw s1, 20(sp) +8000f400: 03 29 01 01 lw s2, 16(sp) +8000f404: 13 01 01 02 addi sp, sp, 32 +8000f408: 67 80 00 00 ret +8000f40c: 93 06 c1 00 addi a3, sp, 12 +8000f410: 13 06 81 00 addi a2, sp, 8 +8000f414: 93 04 05 00 mv s1, a0 +8000f418: ef f0 5f ed jal -300 +8000f41c: 83 25 81 00 lw a1, 8(sp) +8000f420: 13 09 05 00 mv s2, a0 +8000f424: 13 85 04 00 mv a0, s1 +8000f428: ef 90 9f fb jal -24648 +8000f42c: 83 17 c4 00 lh a5, 12(s0) +8000f430: 63 08 05 04 beqz a0, 80 +8000f434: 37 e7 00 80 lui a4, 524302 +8000f438: 13 07 07 7b addi a4, a4, 1968 +8000f43c: 23 ae e4 02 sw a4, 60(s1) +8000f440: 03 27 81 00 lw a4, 8(sp) +8000f444: 83 26 c1 00 lw a3, 12(sp) +8000f448: 93 e7 07 08 ori a5, a5, 128 +8000f44c: 23 16 f4 00 sh a5, 12(s0) +8000f450: 23 20 a4 00 sw a0, 0(s0) +8000f454: 23 28 a4 00 sw a0, 16(s0) +8000f458: 23 2a e4 00 sw a4, 20(s0) +8000f45c: 63 98 06 04 bnez a3, 80 +8000f460: b3 e7 27 01 or a5, a5, s2 +8000f464: 83 20 c1 01 lw ra, 28(sp) +8000f468: 23 16 f4 00 sh a5, 12(s0) +8000f46c: 03 24 81 01 lw s0, 24(sp) +8000f470: 83 24 41 01 lw s1, 20(sp) +8000f474: 03 29 01 01 lw s2, 16(sp) +8000f478: 13 01 01 02 addi sp, sp, 32 +8000f47c: 67 80 00 00 ret +8000f480: 13 f7 07 20 andi a4, a5, 512 +8000f484: e3 18 07 f6 bnez a4, -144 +8000f488: 93 f7 c7 ff andi a5, a5, -4 +8000f48c: 93 e7 27 00 ori a5, a5, 2 +8000f490: 13 07 34 04 addi a4, s0, 67 +8000f494: 23 16 f4 00 sh a5, 12(s0) +8000f498: 93 07 10 00 addi a5, zero, 1 +8000f49c: 23 20 e4 00 sw a4, 0(s0) +8000f4a0: 23 28 e4 00 sw a4, 16(s0) +8000f4a4: 23 2a f4 00 sw a5, 20(s0) +8000f4a8: 6f f0 df f4 j -180 +8000f4ac: 83 15 e4 00 lh a1, 14(s0) +8000f4b0: 13 85 04 00 mv a0, s1 +8000f4b4: ef 00 10 1c jal 2496 +8000f4b8: 63 16 05 00 bnez a0, 12 +8000f4bc: 83 17 c4 00 lh a5, 12(s0) +8000f4c0: 6f f0 1f fa j -96 +8000f4c4: 03 57 c4 00 lhu a4, 12(s0) +8000f4c8: 13 77 c7 ff andi a4, a4, -4 +8000f4cc: 13 67 17 00 ori a4, a4, 1 +8000f4d0: 93 17 07 01 slli a5, a4, 16 +8000f4d4: 93 d7 07 41 srai a5, a5, 16 +8000f4d8: 6f f0 9f f8 j -120 + +8000f4dc _init_signal_r.part.0: +8000f4dc: 13 01 01 ff addi sp, sp, -16 +8000f4e0: 93 05 00 08 addi a1, zero, 128 +8000f4e4: 23 24 81 00 sw s0, 8(sp) +8000f4e8: 23 26 11 00 sw ra, 12(sp) +8000f4ec: 13 04 05 00 mv s0, a0 +8000f4f0: ef 90 1f ef jal -24848 +8000f4f4: 23 2e a4 2c sw a0, 732(s0) +8000f4f8: 63 04 05 02 beqz a0, 40 +8000f4fc: 93 07 05 08 addi a5, a0, 128 +8000f500: 23 20 05 00 sw zero, 0(a0) +8000f504: 13 05 45 00 addi a0, a0, 4 +8000f508: e3 1c f5 fe bne a0, a5, -8 +8000f50c: 13 05 00 00 mv a0, zero +8000f510: 83 20 c1 00 lw ra, 12(sp) +8000f514: 03 24 81 00 lw s0, 8(sp) +8000f518: 13 01 01 01 addi sp, sp, 16 +8000f51c: 67 80 00 00 ret +8000f520: 13 05 f0 ff addi a0, zero, -1 +8000f524: 6f f0 df fe j -20 + +8000f528 _init_signal_r: +8000f528: 83 27 c5 2d lw a5, 732(a0) +8000f52c: 63 86 07 00 beqz a5, 12 +8000f530: 13 05 00 00 mv a0, zero +8000f534: 67 80 00 00 ret +8000f538: 6f f0 5f fa j -92 + +8000f53c _signal_r: +8000f53c: 13 01 01 fe addi sp, sp, -32 +8000f540: 23 2a 91 00 sw s1, 20(sp) +8000f544: 23 2e 11 00 sw ra, 28(sp) +8000f548: 23 2c 81 00 sw s0, 24(sp) +8000f54c: 93 07 f0 01 addi a5, zero, 31 +8000f550: 93 04 05 00 mv s1, a0 +8000f554: 63 ea b7 02 bltu a5, a1, 52 +8000f558: 13 84 05 00 mv s0, a1 +8000f55c: 83 25 c5 2d lw a1, 732(a0) +8000f560: 63 84 05 04 beqz a1, 72 +8000f564: 13 14 24 00 slli s0, s0, 2 +8000f568: 33 84 85 00 add s0, a1, s0 +8000f56c: 03 25 04 00 lw a0, 0(s0) +8000f570: 23 20 c4 00 sw a2, 0(s0) +8000f574: 83 20 c1 01 lw ra, 28(sp) +8000f578: 03 24 81 01 lw s0, 24(sp) +8000f57c: 83 24 41 01 lw s1, 20(sp) +8000f580: 13 01 01 02 addi sp, sp, 32 +8000f584: 67 80 00 00 ret +8000f588: 83 20 c1 01 lw ra, 28(sp) +8000f58c: 03 24 81 01 lw s0, 24(sp) +8000f590: 93 07 60 01 addi a5, zero, 22 +8000f594: 23 20 f5 00 sw a5, 0(a0) +8000f598: 83 24 41 01 lw s1, 20(sp) +8000f59c: 13 05 f0 ff addi a0, zero, -1 +8000f5a0: 13 01 01 02 addi sp, sp, 32 +8000f5a4: 67 80 00 00 ret +8000f5a8: 23 26 c1 00 sw a2, 12(sp) +8000f5ac: ef f0 1f f3 jal -208 +8000f5b0: 93 07 05 00 mv a5, a0 +8000f5b4: 13 05 f0 ff addi a0, zero, -1 +8000f5b8: e3 9e 07 fa bnez a5, -68 +8000f5bc: 83 a5 c4 2d lw a1, 732(s1) +8000f5c0: 03 26 c1 00 lw a2, 12(sp) +8000f5c4: 6f f0 1f fa j -96 + +8000f5c8 _raise_r: +8000f5c8: 13 01 01 ff addi sp, sp, -16 +8000f5cc: 23 22 91 00 sw s1, 4(sp) +8000f5d0: 23 26 11 00 sw ra, 12(sp) +8000f5d4: 23 24 81 00 sw s0, 8(sp) +8000f5d8: 93 07 f0 01 addi a5, zero, 31 +8000f5dc: 93 04 05 00 mv s1, a0 +8000f5e0: 63 ea b7 0a bltu a5, a1, 180 +8000f5e4: 83 27 c5 2d lw a5, 732(a0) +8000f5e8: 13 84 05 00 mv s0, a1 +8000f5ec: 63 84 07 04 beqz a5, 72 +8000f5f0: 13 97 25 00 slli a4, a1, 2 +8000f5f4: b3 87 e7 00 add a5, a5, a4 +8000f5f8: 03 a7 07 00 lw a4, 0(a5) +8000f5fc: 63 0c 07 02 beqz a4, 56 +8000f600: 93 06 10 00 addi a3, zero, 1 +8000f604: 63 0c d7 06 beq a4, a3, 120 +8000f608: 93 06 f0 ff addi a3, zero, -1 +8000f60c: 63 08 d7 04 beq a4, a3, 80 +8000f610: 13 85 05 00 mv a0, a1 +8000f614: 23 a0 07 00 sw zero, 0(a5) +8000f618: e7 00 07 00 jalr a4 +8000f61c: 13 05 00 00 mv a0, zero +8000f620: 83 20 c1 00 lw ra, 12(sp) +8000f624: 03 24 81 00 lw s0, 8(sp) +8000f628: 83 24 41 00 lw s1, 4(sp) +8000f62c: 13 01 01 01 addi sp, sp, 16 +8000f630: 67 80 00 00 ret +8000f634: 13 85 04 00 mv a0, s1 +8000f638: ef 00 00 1e jal 480 +8000f63c: 13 06 04 00 mv a2, s0 +8000f640: 03 24 81 00 lw s0, 8(sp) +8000f644: 83 20 c1 00 lw ra, 12(sp) +8000f648: 93 05 05 00 mv a1, a0 +8000f64c: 13 85 04 00 mv a0, s1 +8000f650: 83 24 41 00 lw s1, 4(sp) +8000f654: 13 01 01 01 addi sp, sp, 16 +8000f658: 6f 00 80 15 j 344 +8000f65c: 83 20 c1 00 lw ra, 12(sp) +8000f660: 03 24 81 00 lw s0, 8(sp) +8000f664: 93 07 60 01 addi a5, zero, 22 +8000f668: 23 20 f5 00 sw a5, 0(a0) +8000f66c: 83 24 41 00 lw s1, 4(sp) +8000f670: 13 05 10 00 addi a0, zero, 1 +8000f674: 13 01 01 01 addi sp, sp, 16 +8000f678: 67 80 00 00 ret +8000f67c: 83 20 c1 00 lw ra, 12(sp) +8000f680: 03 24 81 00 lw s0, 8(sp) +8000f684: 83 24 41 00 lw s1, 4(sp) +8000f688: 13 05 00 00 mv a0, zero +8000f68c: 13 01 01 01 addi sp, sp, 16 +8000f690: 67 80 00 00 ret +8000f694: 93 07 60 01 addi a5, zero, 22 +8000f698: 23 20 f5 00 sw a5, 0(a0) +8000f69c: 13 05 f0 ff addi a0, zero, -1 +8000f6a0: 6f f0 1f f8 j -128 + +8000f6a4 __sigtramp_r: +8000f6a4: 93 07 f0 01 addi a5, zero, 31 +8000f6a8: 63 e6 b7 0a bltu a5, a1, 172 +8000f6ac: 83 27 c5 2d lw a5, 732(a0) +8000f6b0: 13 01 01 fe addi sp, sp, -32 +8000f6b4: 23 2c 91 00 sw s1, 24(sp) +8000f6b8: 23 2e 11 00 sw ra, 28(sp) +8000f6bc: 93 04 05 00 mv s1, a0 +8000f6c0: 63 8c 07 04 beqz a5, 88 +8000f6c4: 13 97 25 00 slli a4, a1, 2 +8000f6c8: b3 87 e7 00 add a5, a5, a4 +8000f6cc: 03 a7 07 00 lw a4, 0(a5) +8000f6d0: 63 0a 07 02 beqz a4, 52 +8000f6d4: 93 06 f0 ff addi a3, zero, -1 +8000f6d8: 63 06 d7 06 beq a4, a3, 108 +8000f6dc: 93 06 10 00 addi a3, zero, 1 +8000f6e0: 63 08 d7 04 beq a4, a3, 80 +8000f6e4: 13 85 05 00 mv a0, a1 +8000f6e8: 23 a0 07 00 sw zero, 0(a5) +8000f6ec: e7 00 07 00 jalr a4 +8000f6f0: 13 05 00 00 mv a0, zero +8000f6f4: 83 20 c1 01 lw ra, 28(sp) +8000f6f8: 83 24 81 01 lw s1, 24(sp) +8000f6fc: 13 01 01 02 addi sp, sp, 32 +8000f700: 67 80 00 00 ret +8000f704: 83 20 c1 01 lw ra, 28(sp) +8000f708: 83 24 81 01 lw s1, 24(sp) +8000f70c: 13 05 10 00 addi a0, zero, 1 +8000f710: 13 01 01 02 addi sp, sp, 32 +8000f714: 67 80 00 00 ret +8000f718: 23 26 b1 00 sw a1, 12(sp) +8000f71c: ef f0 1f dc jal -576 +8000f720: 63 16 05 02 bnez a0, 44 +8000f724: 83 a7 c4 2d lw a5, 732(s1) +8000f728: 83 25 c1 00 lw a1, 12(sp) +8000f72c: 6f f0 9f f9 j -104 +8000f730: 83 20 c1 01 lw ra, 28(sp) +8000f734: 83 24 81 01 lw s1, 24(sp) +8000f738: 13 05 30 00 addi a0, zero, 3 +8000f73c: 13 01 01 02 addi sp, sp, 32 +8000f740: 67 80 00 00 ret +8000f744: 13 05 20 00 addi a0, zero, 2 +8000f748: 6f f0 df fa j -84 +8000f74c: 13 05 f0 ff addi a0, zero, -1 +8000f750: 6f f0 5f fa j -92 +8000f754: 13 05 f0 ff addi a0, zero, -1 +8000f758: 67 80 00 00 ret + +8000f75c raise: +8000f75c: b7 87 01 80 lui a5, 524312 +8000f760: 93 05 05 00 mv a1, a0 +8000f764: 03 a5 c7 b9 lw a0, -1124(a5) +8000f768: 6f f0 1f e6 j -416 + +8000f76c signal: +8000f76c: 37 87 01 80 lui a4, 524312 +8000f770: 93 07 05 00 mv a5, a0 +8000f774: 03 25 c7 b9 lw a0, -1124(a4) +8000f778: 13 86 05 00 mv a2, a1 +8000f77c: 93 85 07 00 mv a1, a5 +8000f780: 6f f0 df db j -580 + +8000f784 _init_signal: +8000f784: b7 87 01 80 lui a5, 524312 +8000f788: 03 a5 c7 b9 lw a0, -1124(a5) +8000f78c: 83 27 c5 2d lw a5, 732(a0) +8000f790: 63 86 07 00 beqz a5, 12 +8000f794: 13 05 00 00 mv a0, zero +8000f798: 67 80 00 00 ret +8000f79c: 6f f0 1f d4 j -704 + +8000f7a0 __sigtramp: +8000f7a0: b7 87 01 80 lui a5, 524312 +8000f7a4: 93 05 05 00 mv a1, a0 +8000f7a8: 03 a5 c7 b9 lw a0, -1124(a5) +8000f7ac: 6f f0 9f ef j -264 + +8000f7b0 _kill_r: +8000f7b0: 13 01 01 ff addi sp, sp, -16 +8000f7b4: 13 87 05 00 mv a4, a1 +8000f7b8: 23 24 81 00 sw s0, 8(sp) +8000f7bc: 23 22 91 00 sw s1, 4(sp) +8000f7c0: 13 04 05 00 mv s0, a0 +8000f7c4: b7 84 01 80 lui s1, 524312 +8000f7c8: 93 05 06 00 mv a1, a2 +8000f7cc: 13 05 07 00 mv a0, a4 +8000f7d0: 23 26 11 00 sw ra, 12(sp) +8000f7d4: 23 ae 04 c4 sw zero, -932(s1) +8000f7d8: ef 30 4f d9 jal -51820 +8000f7dc: 93 07 f0 ff addi a5, zero, -1 +8000f7e0: 63 0c f5 00 beq a0, a5, 24 +8000f7e4: 83 20 c1 00 lw ra, 12(sp) +8000f7e8: 03 24 81 00 lw s0, 8(sp) +8000f7ec: 83 24 41 00 lw s1, 4(sp) +8000f7f0: 13 01 01 01 addi sp, sp, 16 +8000f7f4: 67 80 00 00 ret +8000f7f8: 83 a7 c4 c5 lw a5, -932(s1) +8000f7fc: e3 84 07 fe beqz a5, -24 +8000f800: 83 20 c1 00 lw ra, 12(sp) +8000f804: 23 20 f4 00 sw a5, 0(s0) +8000f808: 03 24 81 00 lw s0, 8(sp) +8000f80c: 83 24 41 00 lw s1, 4(sp) +8000f810: 13 01 01 01 addi sp, sp, 16 +8000f814: 67 80 00 00 ret + +8000f818 _getpid_r: +8000f818: 6f 30 cf d5 j -51876 + +8000f81c __sread: +8000f81c: 13 01 01 ff addi sp, sp, -16 +8000f820: 23 24 81 00 sw s0, 8(sp) +8000f824: 13 84 05 00 mv s0, a1 +8000f828: 83 95 e5 00 lh a1, 14(a1) +8000f82c: 23 26 11 00 sw ra, 12(sp) +8000f830: ef 00 00 71 jal 1808 +8000f834: 63 40 05 02 bltz a0, 32 +8000f838: 83 27 04 05 lw a5, 80(s0) +8000f83c: 83 20 c1 00 lw ra, 12(sp) +8000f840: b3 87 a7 00 add a5, a5, a0 +8000f844: 23 28 f4 04 sw a5, 80(s0) +8000f848: 03 24 81 00 lw s0, 8(sp) +8000f84c: 13 01 01 01 addi sp, sp, 16 +8000f850: 67 80 00 00 ret +8000f854: 83 57 c4 00 lhu a5, 12(s0) +8000f858: 37 f7 ff ff lui a4, 1048575 +8000f85c: 13 07 f7 ff addi a4, a4, -1 +8000f860: b3 f7 e7 00 and a5, a5, a4 +8000f864: 83 20 c1 00 lw ra, 12(sp) +8000f868: 23 16 f4 00 sh a5, 12(s0) +8000f86c: 03 24 81 00 lw s0, 8(sp) +8000f870: 13 01 01 01 addi sp, sp, 16 +8000f874: 67 80 00 00 ret + +8000f878 __seofread: +8000f878: 13 05 00 00 mv a0, zero +8000f87c: 67 80 00 00 ret + +8000f880 __swrite: +8000f880: 83 97 c5 00 lh a5, 12(a1) +8000f884: 13 01 01 fe addi sp, sp, -32 +8000f888: 23 2c 81 00 sw s0, 24(sp) +8000f88c: 23 2a 91 00 sw s1, 20(sp) +8000f890: 23 28 21 01 sw s2, 16(sp) +8000f894: 23 26 31 01 sw s3, 12(sp) +8000f898: 23 2e 11 00 sw ra, 28(sp) +8000f89c: 13 f7 07 10 andi a4, a5, 256 +8000f8a0: 13 84 05 00 mv s0, a1 +8000f8a4: 93 04 05 00 mv s1, a0 +8000f8a8: 83 95 e5 00 lh a1, 14(a1) +8000f8ac: 13 09 06 00 mv s2, a2 +8000f8b0: 93 89 06 00 mv s3, a3 +8000f8b4: 63 1e 07 02 bnez a4, 60 +8000f8b8: 37 f7 ff ff lui a4, 1048575 +8000f8bc: 13 07 f7 ff addi a4, a4, -1 +8000f8c0: b3 f7 e7 00 and a5, a5, a4 +8000f8c4: 23 16 f4 00 sh a5, 12(s0) +8000f8c8: 03 24 81 01 lw s0, 24(sp) +8000f8cc: 83 20 c1 01 lw ra, 28(sp) +8000f8d0: 93 86 09 00 mv a3, s3 +8000f8d4: 13 06 09 00 mv a2, s2 +8000f8d8: 83 29 c1 00 lw s3, 12(sp) +8000f8dc: 03 29 01 01 lw s2, 16(sp) +8000f8e0: 13 85 04 00 mv a0, s1 +8000f8e4: 83 24 41 01 lw s1, 20(sp) +8000f8e8: 13 01 01 02 addi sp, sp, 32 +8000f8ec: 6f 00 40 33 j 820 +8000f8f0: 93 06 20 00 addi a3, zero, 2 +8000f8f4: 13 06 00 00 mv a2, zero +8000f8f8: ef 00 c0 5d jal 1500 +8000f8fc: 83 17 c4 00 lh a5, 12(s0) +8000f900: 83 15 e4 00 lh a1, 14(s0) +8000f904: 6f f0 5f fb j -76 + +8000f908 __sseek: +8000f908: 13 01 01 ff addi sp, sp, -16 +8000f90c: 23 24 81 00 sw s0, 8(sp) +8000f910: 13 84 05 00 mv s0, a1 +8000f914: 83 95 e5 00 lh a1, 14(a1) +8000f918: 23 26 11 00 sw ra, 12(sp) +8000f91c: ef 00 80 5b jal 1464 +8000f920: 93 07 f0 ff addi a5, zero, -1 +8000f924: 63 04 f5 02 beq a0, a5, 40 +8000f928: 83 57 c4 00 lhu a5, 12(s0) +8000f92c: 37 17 00 00 lui a4, 1 +8000f930: 83 20 c1 00 lw ra, 12(sp) +8000f934: b3 e7 e7 00 or a5, a5, a4 +8000f938: 23 28 a4 04 sw a0, 80(s0) +8000f93c: 23 16 f4 00 sh a5, 12(s0) +8000f940: 03 24 81 00 lw s0, 8(sp) +8000f944: 13 01 01 01 addi sp, sp, 16 +8000f948: 67 80 00 00 ret +8000f94c: 83 57 c4 00 lhu a5, 12(s0) +8000f950: 37 f7 ff ff lui a4, 1048575 +8000f954: 13 07 f7 ff addi a4, a4, -1 +8000f958: b3 f7 e7 00 and a5, a5, a4 +8000f95c: 83 20 c1 00 lw ra, 12(sp) +8000f960: 23 16 f4 00 sh a5, 12(s0) +8000f964: 03 24 81 00 lw s0, 8(sp) +8000f968: 13 01 01 01 addi sp, sp, 16 +8000f96c: 67 80 00 00 ret + +8000f970 __sclose: +8000f970: 83 95 e5 00 lh a1, 14(a1) +8000f974: 6f 00 80 31 j 792 + +8000f978 __swbuf_r: +8000f978: 13 01 01 fe addi sp, sp, -32 +8000f97c: 23 2c 81 00 sw s0, 24(sp) +8000f980: 23 2a 91 00 sw s1, 20(sp) +8000f984: 23 28 21 01 sw s2, 16(sp) +8000f988: 23 2e 11 00 sw ra, 28(sp) +8000f98c: 23 26 31 01 sw s3, 12(sp) +8000f990: 13 09 05 00 mv s2, a0 +8000f994: 93 84 05 00 mv s1, a1 +8000f998: 13 04 06 00 mv s0, a2 +8000f99c: 63 06 05 00 beqz a0, 12 +8000f9a0: 83 27 85 03 lw a5, 56(a0) +8000f9a4: 63 88 07 14 beqz a5, 336 +8000f9a8: 03 17 c4 00 lh a4, 12(s0) +8000f9ac: 83 26 84 01 lw a3, 24(s0) +8000f9b0: 93 77 87 00 andi a5, a4, 8 +8000f9b4: 23 24 d4 00 sw a3, 8(s0) +8000f9b8: 93 16 07 01 slli a3, a4, 16 +8000f9bc: 93 d6 06 01 srli a3, a3, 16 +8000f9c0: 63 82 07 08 beqz a5, 132 +8000f9c4: 83 27 04 01 lw a5, 16(s0) +8000f9c8: 63 8e 07 06 beqz a5, 124 +8000f9cc: 13 96 26 01 slli a2, a3, 18 +8000f9d0: 93 f9 f4 0f andi s3, s1, 255 +8000f9d4: 93 f4 f4 0f andi s1, s1, 255 +8000f9d8: 63 5e 06 08 bgez a2, 156 +8000f9dc: 03 27 04 00 lw a4, 0(s0) +8000f9e0: 83 26 44 01 lw a3, 20(s0) +8000f9e4: b3 07 f7 40 sub a5, a4, a5 +8000f9e8: 63 de d7 0a bge a5, a3, 188 +8000f9ec: 83 26 84 00 lw a3, 8(s0) +8000f9f0: 13 06 17 00 addi a2, a4, 1 +8000f9f4: 23 20 c4 00 sw a2, 0(s0) +8000f9f8: 93 86 f6 ff addi a3, a3, -1 +8000f9fc: 23 24 d4 00 sw a3, 8(s0) +8000fa00: 23 00 37 01 sb s3, 0(a4) +8000fa04: 03 27 44 01 lw a4, 20(s0) +8000fa08: 93 87 17 00 addi a5, a5, 1 +8000fa0c: 63 08 f7 0c beq a4, a5, 208 +8000fa10: 83 57 c4 00 lhu a5, 12(s0) +8000fa14: 93 f7 17 00 andi a5, a5, 1 +8000fa18: 63 86 07 00 beqz a5, 12 +8000fa1c: 93 07 a0 00 addi a5, zero, 10 +8000fa20: 63 8e f4 0a beq s1, a5, 188 +8000fa24: 83 20 c1 01 lw ra, 28(sp) +8000fa28: 03 24 81 01 lw s0, 24(sp) +8000fa2c: 03 29 01 01 lw s2, 16(sp) +8000fa30: 83 29 c1 00 lw s3, 12(sp) +8000fa34: 13 85 04 00 mv a0, s1 +8000fa38: 83 24 41 01 lw s1, 20(sp) +8000fa3c: 13 01 01 02 addi sp, sp, 32 +8000fa40: 67 80 00 00 ret +8000fa44: 93 05 04 00 mv a1, s0 +8000fa48: 13 05 09 00 mv a0, s2 +8000fa4c: ef e0 1f 90 jal -5888 +8000fa50: 63 1e 05 08 bnez a0, 156 +8000fa54: 03 17 c4 00 lh a4, 12(s0) +8000fa58: 93 f9 f4 0f andi s3, s1, 255 +8000fa5c: 83 27 04 01 lw a5, 16(s0) +8000fa60: 93 16 07 01 slli a3, a4, 16 +8000fa64: 93 d6 06 01 srli a3, a3, 16 +8000fa68: 13 96 26 01 slli a2, a3, 18 +8000fa6c: 93 f4 f4 0f andi s1, s1, 255 +8000fa70: e3 46 06 f6 bltz a2, -148 +8000fa74: 83 26 44 06 lw a3, 100(s0) +8000fa78: 37 26 00 00 lui a2, 2 +8000fa7c: 33 67 c7 00 or a4, a4, a2 +8000fa80: 37 e6 ff ff lui a2, 1048574 +8000fa84: 13 06 f6 ff addi a2, a2, -1 +8000fa88: b3 f6 c6 00 and a3, a3, a2 +8000fa8c: 23 16 e4 00 sh a4, 12(s0) +8000fa90: 03 27 04 00 lw a4, 0(s0) +8000fa94: 23 22 d4 06 sw a3, 100(s0) +8000fa98: 83 26 44 01 lw a3, 20(s0) +8000fa9c: b3 07 f7 40 sub a5, a4, a5 +8000faa0: e3 c6 d7 f4 blt a5, a3, -180 +8000faa4: 93 05 04 00 mv a1, s0 +8000faa8: 13 05 09 00 mv a0, s2 +8000faac: ef e0 5f c7 jal -5004 +8000fab0: 63 1e 05 02 bnez a0, 60 +8000fab4: 03 27 04 00 lw a4, 0(s0) +8000fab8: 83 26 84 00 lw a3, 8(s0) +8000fabc: 93 07 10 00 addi a5, zero, 1 +8000fac0: 13 06 17 00 addi a2, a4, 1 +8000fac4: 93 86 f6 ff addi a3, a3, -1 +8000fac8: 23 20 c4 00 sw a2, 0(s0) +8000facc: 23 24 d4 00 sw a3, 8(s0) +8000fad0: 23 00 37 01 sb s3, 0(a4) +8000fad4: 03 27 44 01 lw a4, 20(s0) +8000fad8: e3 1c f7 f2 bne a4, a5, -200 +8000fadc: 93 05 04 00 mv a1, s0 +8000fae0: 13 05 09 00 mv a0, s2 +8000fae4: ef e0 df c3 jal -5060 +8000fae8: e3 0e 05 f2 beqz a0, -196 +8000faec: 93 04 f0 ff addi s1, zero, -1 +8000faf0: 6f f0 5f f3 j -204 +8000faf4: ef e0 9f fd jal -4136 +8000faf8: 6f f0 1f eb j -336 + +8000fafc __swbuf: +8000fafc: 37 87 01 80 lui a4, 524312 +8000fb00: 93 07 05 00 mv a5, a0 +8000fb04: 03 25 c7 b9 lw a0, -1124(a4) +8000fb08: 13 86 05 00 mv a2, a1 +8000fb0c: 93 85 07 00 mv a1, a5 +8000fb10: 6f f0 9f e6 j -408 + +8000fb14 _wcrtomb_r: +8000fb14: 13 01 01 fe addi sp, sp, -32 +8000fb18: 23 2c 81 00 sw s0, 24(sp) +8000fb1c: 23 2a 91 00 sw s1, 20(sp) +8000fb20: b7 87 01 80 lui a5, 524312 +8000fb24: 23 2e 11 00 sw ra, 28(sp) +8000fb28: 83 a7 87 ae lw a5, -1304(a5) +8000fb2c: 13 04 05 00 mv s0, a0 +8000fb30: 93 84 06 00 mv s1, a3 +8000fb34: 63 82 05 02 beqz a1, 36 +8000fb38: e7 80 07 00 jalr a5 +8000fb3c: 93 07 f0 ff addi a5, zero, -1 +8000fb40: 63 06 f5 02 beq a0, a5, 44 +8000fb44: 83 20 c1 01 lw ra, 28(sp) +8000fb48: 03 24 81 01 lw s0, 24(sp) +8000fb4c: 83 24 41 01 lw s1, 20(sp) +8000fb50: 13 01 01 02 addi sp, sp, 32 +8000fb54: 67 80 00 00 ret +8000fb58: 13 06 00 00 mv a2, zero +8000fb5c: 93 05 41 00 addi a1, sp, 4 +8000fb60: e7 80 07 00 jalr a5 +8000fb64: 93 07 f0 ff addi a5, zero, -1 +8000fb68: e3 1e f5 fc bne a0, a5, -36 +8000fb6c: 23 a0 04 00 sw zero, 0(s1) +8000fb70: 93 07 a0 08 addi a5, zero, 138 +8000fb74: 83 20 c1 01 lw ra, 28(sp) +8000fb78: 23 20 f4 00 sw a5, 0(s0) +8000fb7c: 03 24 81 01 lw s0, 24(sp) +8000fb80: 83 24 41 01 lw s1, 20(sp) +8000fb84: 13 01 01 02 addi sp, sp, 32 +8000fb88: 67 80 00 00 ret + +8000fb8c wcrtomb: +8000fb8c: 13 01 01 fe addi sp, sp, -32 +8000fb90: b7 87 01 80 lui a5, 524312 +8000fb94: 23 2c 81 00 sw s0, 24(sp) +8000fb98: 23 2a 91 00 sw s1, 20(sp) +8000fb9c: 23 2e 11 00 sw ra, 28(sp) +8000fba0: 83 a4 c7 b9 lw s1, -1124(a5) +8000fba4: b7 87 01 80 lui a5, 524312 +8000fba8: 83 a7 87 ae lw a5, -1304(a5) +8000fbac: 13 04 06 00 mv s0, a2 +8000fbb0: 63 0a 05 02 beqz a0, 52 +8000fbb4: 13 86 05 00 mv a2, a1 +8000fbb8: 93 06 04 00 mv a3, s0 +8000fbbc: 93 05 05 00 mv a1, a0 +8000fbc0: 13 85 04 00 mv a0, s1 +8000fbc4: e7 80 07 00 jalr a5 +8000fbc8: 93 07 f0 ff addi a5, zero, -1 +8000fbcc: 63 0a f5 02 beq a0, a5, 52 +8000fbd0: 83 20 c1 01 lw ra, 28(sp) +8000fbd4: 03 24 81 01 lw s0, 24(sp) +8000fbd8: 83 24 41 01 lw s1, 20(sp) +8000fbdc: 13 01 01 02 addi sp, sp, 32 +8000fbe0: 67 80 00 00 ret +8000fbe4: 93 06 06 00 mv a3, a2 +8000fbe8: 93 05 41 00 addi a1, sp, 4 +8000fbec: 13 06 00 00 mv a2, zero +8000fbf0: 13 85 04 00 mv a0, s1 +8000fbf4: e7 80 07 00 jalr a5 +8000fbf8: 93 07 f0 ff addi a5, zero, -1 +8000fbfc: e3 1a f5 fc bne a0, a5, -44 +8000fc00: 23 20 04 00 sw zero, 0(s0) +8000fc04: 83 20 c1 01 lw ra, 28(sp) +8000fc08: 03 24 81 01 lw s0, 24(sp) +8000fc0c: 93 07 a0 08 addi a5, zero, 138 +8000fc10: 23 a0 f4 00 sw a5, 0(s1) +8000fc14: 83 24 41 01 lw s1, 20(sp) +8000fc18: 13 01 01 02 addi sp, sp, 32 +8000fc1c: 67 80 00 00 ret + +8000fc20 _write_r: +8000fc20: 13 01 01 ff addi sp, sp, -16 +8000fc24: 13 87 05 00 mv a4, a1 +8000fc28: 23 24 81 00 sw s0, 8(sp) +8000fc2c: 23 22 91 00 sw s1, 4(sp) +8000fc30: 93 05 06 00 mv a1, a2 +8000fc34: 13 04 05 00 mv s0, a0 +8000fc38: b7 84 01 80 lui s1, 524312 +8000fc3c: 13 86 06 00 mv a2, a3 +8000fc40: 13 05 07 00 mv a0, a4 +8000fc44: 23 26 11 00 sw ra, 12(sp) +8000fc48: 23 ae 04 c4 sw zero, -932(s1) +8000fc4c: ef 30 0f 8d jal -53040 +8000fc50: 93 07 f0 ff addi a5, zero, -1 +8000fc54: 63 0c f5 00 beq a0, a5, 24 +8000fc58: 83 20 c1 00 lw ra, 12(sp) +8000fc5c: 03 24 81 00 lw s0, 8(sp) +8000fc60: 83 24 41 00 lw s1, 4(sp) +8000fc64: 13 01 01 01 addi sp, sp, 16 +8000fc68: 67 80 00 00 ret +8000fc6c: 83 a7 c4 c5 lw a5, -932(s1) +8000fc70: e3 84 07 fe beqz a5, -24 +8000fc74: 83 20 c1 00 lw ra, 12(sp) +8000fc78: 23 20 f4 00 sw a5, 0(s0) +8000fc7c: 03 24 81 00 lw s0, 8(sp) +8000fc80: 83 24 41 00 lw s1, 4(sp) +8000fc84: 13 01 01 01 addi sp, sp, 16 +8000fc88: 67 80 00 00 ret + +8000fc8c _close_r: +8000fc8c: 13 01 01 ff addi sp, sp, -16 +8000fc90: 23 24 81 00 sw s0, 8(sp) +8000fc94: 23 22 91 00 sw s1, 4(sp) +8000fc98: 13 04 05 00 mv s0, a0 +8000fc9c: b7 84 01 80 lui s1, 524312 +8000fca0: 13 85 05 00 mv a0, a1 +8000fca4: 23 26 11 00 sw ra, 12(sp) +8000fca8: 23 ae 04 c4 sw zero, -932(s1) +8000fcac: ef 30 0f 84 jal -53184 +8000fcb0: 93 07 f0 ff addi a5, zero, -1 +8000fcb4: 63 0c f5 00 beq a0, a5, 24 +8000fcb8: 83 20 c1 00 lw ra, 12(sp) +8000fcbc: 03 24 81 00 lw s0, 8(sp) +8000fcc0: 83 24 41 00 lw s1, 4(sp) +8000fcc4: 13 01 01 01 addi sp, sp, 16 +8000fcc8: 67 80 00 00 ret +8000fccc: 83 a7 c4 c5 lw a5, -932(s1) +8000fcd0: e3 84 07 fe beqz a5, -24 +8000fcd4: 83 20 c1 00 lw ra, 12(sp) +8000fcd8: 23 20 f4 00 sw a5, 0(s0) +8000fcdc: 03 24 81 00 lw s0, 8(sp) +8000fce0: 83 24 41 00 lw s1, 4(sp) +8000fce4: 13 01 01 01 addi sp, sp, 16 +8000fce8: 67 80 00 00 ret + +8000fcec _fclose_r: +8000fcec: 13 01 01 ff addi sp, sp, -16 +8000fcf0: 23 26 11 00 sw ra, 12(sp) +8000fcf4: 23 24 81 00 sw s0, 8(sp) +8000fcf8: 23 22 91 00 sw s1, 4(sp) +8000fcfc: 23 20 21 01 sw s2, 0(sp) +8000fd00: 63 80 05 02 beqz a1, 32 +8000fd04: 13 84 05 00 mv s0, a1 +8000fd08: 93 04 05 00 mv s1, a0 +8000fd0c: 63 06 05 00 beqz a0, 12 +8000fd10: 83 27 85 03 lw a5, 56(a0) +8000fd14: 63 8c 07 0a beqz a5, 184 +8000fd18: 83 17 c4 00 lh a5, 12(s0) +8000fd1c: 63 92 07 02 bnez a5, 36 +8000fd20: 83 20 c1 00 lw ra, 12(sp) +8000fd24: 03 24 81 00 lw s0, 8(sp) +8000fd28: 13 09 00 00 mv s2, zero +8000fd2c: 83 24 41 00 lw s1, 4(sp) +8000fd30: 13 05 09 00 mv a0, s2 +8000fd34: 03 29 01 00 lw s2, 0(sp) +8000fd38: 13 01 01 01 addi sp, sp, 16 +8000fd3c: 67 80 00 00 ret +8000fd40: 93 05 04 00 mv a1, s0 +8000fd44: 13 85 04 00 mv a0, s1 +8000fd48: ef e0 cf f7 jal -6276 +8000fd4c: 83 27 c4 02 lw a5, 44(s0) +8000fd50: 13 09 05 00 mv s2, a0 +8000fd54: 63 8a 07 00 beqz a5, 20 +8000fd58: 83 25 c4 01 lw a1, 28(s0) +8000fd5c: 13 85 04 00 mv a0, s1 +8000fd60: e7 80 07 00 jalr a5 +8000fd64: 63 4c 05 06 bltz a0, 120 +8000fd68: 83 57 c4 00 lhu a5, 12(s0) +8000fd6c: 93 f7 07 08 andi a5, a5, 128 +8000fd70: 63 9e 07 06 bnez a5, 124 +8000fd74: 83 25 04 03 lw a1, 48(s0) +8000fd78: 63 8c 05 00 beqz a1, 24 +8000fd7c: 93 07 04 04 addi a5, s0, 64 +8000fd80: 63 86 f5 00 beq a1, a5, 12 +8000fd84: 13 85 04 00 mv a0, s1 +8000fd88: ef 60 4f f8 jal -39036 +8000fd8c: 23 28 04 02 sw zero, 48(s0) +8000fd90: 83 25 44 04 lw a1, 68(s0) +8000fd94: 63 88 05 00 beqz a1, 16 +8000fd98: 13 85 04 00 mv a0, s1 +8000fd9c: ef 60 0f f7 jal -39056 +8000fda0: 23 22 04 04 sw zero, 68(s0) +8000fda4: ef e0 9f d3 jal -4808 +8000fda8: 23 16 04 00 sh zero, 12(s0) +8000fdac: ef e0 5f d3 jal -4812 +8000fdb0: 83 20 c1 00 lw ra, 12(sp) +8000fdb4: 03 24 81 00 lw s0, 8(sp) +8000fdb8: 83 24 41 00 lw s1, 4(sp) +8000fdbc: 13 05 09 00 mv a0, s2 +8000fdc0: 03 29 01 00 lw s2, 0(sp) +8000fdc4: 13 01 01 01 addi sp, sp, 16 +8000fdc8: 67 80 00 00 ret +8000fdcc: ef e0 1f d0 jal -4864 +8000fdd0: 83 17 c4 00 lh a5, 12(s0) +8000fdd4: e3 86 07 f4 beqz a5, -180 +8000fdd8: 6f f0 9f f6 j -152 +8000fddc: 83 57 c4 00 lhu a5, 12(s0) +8000fde0: 13 09 f0 ff addi s2, zero, -1 +8000fde4: 93 f7 07 08 andi a5, a5, 128 +8000fde8: e3 86 07 f8 beqz a5, -116 +8000fdec: 83 25 04 01 lw a1, 16(s0) +8000fdf0: 13 85 04 00 mv a0, s1 +8000fdf4: ef 60 8f f1 jal -39144 +8000fdf8: 6f f0 df f7 j -132 + +8000fdfc fclose: +8000fdfc: b7 87 01 80 lui a5, 524312 +8000fe00: 93 05 05 00 mv a1, a0 +8000fe04: 03 a5 c7 b9 lw a0, -1124(a5) +8000fe08: 6f f0 5f ee j -284 + +8000fe0c _fstat_r: +8000fe0c: 13 01 01 ff addi sp, sp, -16 +8000fe10: 13 87 05 00 mv a4, a1 +8000fe14: 23 24 81 00 sw s0, 8(sp) +8000fe18: 23 22 91 00 sw s1, 4(sp) +8000fe1c: 13 04 05 00 mv s0, a0 +8000fe20: b7 84 01 80 lui s1, 524312 +8000fe24: 93 05 06 00 mv a1, a2 +8000fe28: 13 05 07 00 mv a0, a4 +8000fe2c: 23 26 11 00 sw ra, 12(sp) +8000fe30: 23 ae 04 c4 sw zero, -932(s1) +8000fe34: ef 20 1f ec jal -53568 +8000fe38: 93 07 f0 ff addi a5, zero, -1 +8000fe3c: 63 0c f5 00 beq a0, a5, 24 +8000fe40: 83 20 c1 00 lw ra, 12(sp) +8000fe44: 03 24 81 00 lw s0, 8(sp) +8000fe48: 83 24 41 00 lw s1, 4(sp) +8000fe4c: 13 01 01 01 addi sp, sp, 16 +8000fe50: 67 80 00 00 ret +8000fe54: 83 a7 c4 c5 lw a5, -932(s1) +8000fe58: e3 84 07 fe beqz a5, -24 +8000fe5c: 83 20 c1 00 lw ra, 12(sp) +8000fe60: 23 20 f4 00 sw a5, 0(s0) +8000fe64: 03 24 81 00 lw s0, 8(sp) +8000fe68: 83 24 41 00 lw s1, 4(sp) +8000fe6c: 13 01 01 01 addi sp, sp, 16 +8000fe70: 67 80 00 00 ret + +8000fe74 _isatty_r: +8000fe74: 13 01 01 ff addi sp, sp, -16 +8000fe78: 23 24 81 00 sw s0, 8(sp) +8000fe7c: 23 22 91 00 sw s1, 4(sp) +8000fe80: 13 04 05 00 mv s0, a0 +8000fe84: b7 84 01 80 lui s1, 524312 +8000fe88: 13 85 05 00 mv a0, a1 +8000fe8c: 23 26 11 00 sw ra, 12(sp) +8000fe90: 23 ae 04 c4 sw zero, -932(s1) +8000fe94: ef 20 9f e6 jal -53656 +8000fe98: 93 07 f0 ff addi a5, zero, -1 +8000fe9c: 63 0c f5 00 beq a0, a5, 24 +8000fea0: 83 20 c1 00 lw ra, 12(sp) +8000fea4: 03 24 81 00 lw s0, 8(sp) +8000fea8: 83 24 41 00 lw s1, 4(sp) +8000feac: 13 01 01 01 addi sp, sp, 16 +8000feb0: 67 80 00 00 ret +8000feb4: 83 a7 c4 c5 lw a5, -932(s1) +8000feb8: e3 84 07 fe beqz a5, -24 +8000febc: 83 20 c1 00 lw ra, 12(sp) +8000fec0: 23 20 f4 00 sw a5, 0(s0) +8000fec4: 03 24 81 00 lw s0, 8(sp) +8000fec8: 83 24 41 00 lw s1, 4(sp) +8000fecc: 13 01 01 01 addi sp, sp, 16 +8000fed0: 67 80 00 00 ret + +8000fed4 _lseek_r: +8000fed4: 13 01 01 ff addi sp, sp, -16 +8000fed8: 13 87 05 00 mv a4, a1 +8000fedc: 23 24 81 00 sw s0, 8(sp) +8000fee0: 23 22 91 00 sw s1, 4(sp) +8000fee4: 93 05 06 00 mv a1, a2 +8000fee8: 13 04 05 00 mv s0, a0 +8000feec: b7 84 01 80 lui s1, 524312 +8000fef0: 13 86 06 00 mv a2, a3 +8000fef4: 13 05 07 00 mv a0, a4 +8000fef8: 23 26 11 00 sw ra, 12(sp) +8000fefc: 23 ae 04 c4 sw zero, -932(s1) +8000ff00: ef 20 5f e0 jal -53756 +8000ff04: 93 07 f0 ff addi a5, zero, -1 +8000ff08: 63 0c f5 00 beq a0, a5, 24 +8000ff0c: 83 20 c1 00 lw ra, 12(sp) +8000ff10: 03 24 81 00 lw s0, 8(sp) +8000ff14: 83 24 41 00 lw s1, 4(sp) +8000ff18: 13 01 01 01 addi sp, sp, 16 +8000ff1c: 67 80 00 00 ret +8000ff20: 83 a7 c4 c5 lw a5, -932(s1) +8000ff24: e3 84 07 fe beqz a5, -24 +8000ff28: 83 20 c1 00 lw ra, 12(sp) +8000ff2c: 23 20 f4 00 sw a5, 0(s0) +8000ff30: 03 24 81 00 lw s0, 8(sp) +8000ff34: 83 24 41 00 lw s1, 4(sp) +8000ff38: 13 01 01 01 addi sp, sp, 16 +8000ff3c: 67 80 00 00 ret + +8000ff40 _read_r: +8000ff40: 13 01 01 ff addi sp, sp, -16 +8000ff44: 13 87 05 00 mv a4, a1 +8000ff48: 23 24 81 00 sw s0, 8(sp) +8000ff4c: 23 22 91 00 sw s1, 4(sp) +8000ff50: 93 05 06 00 mv a1, a2 +8000ff54: 13 04 05 00 mv s0, a0 +8000ff58: b7 84 01 80 lui s1, 524312 +8000ff5c: 13 86 06 00 mv a2, a3 +8000ff60: 13 05 07 00 mv a0, a4 +8000ff64: 23 26 11 00 sw ra, 12(sp) +8000ff68: 23 ae 04 c4 sw zero, -932(s1) +8000ff6c: ef 20 1f da jal -53856 +8000ff70: 93 07 f0 ff addi a5, zero, -1 +8000ff74: 63 0c f5 00 beq a0, a5, 24 +8000ff78: 83 20 c1 00 lw ra, 12(sp) +8000ff7c: 03 24 81 00 lw s0, 8(sp) +8000ff80: 83 24 41 00 lw s1, 4(sp) +8000ff84: 13 01 01 01 addi sp, sp, 16 +8000ff88: 67 80 00 00 ret +8000ff8c: 83 a7 c4 c5 lw a5, -932(s1) +8000ff90: e3 84 07 fe beqz a5, -24 +8000ff94: 83 20 c1 00 lw ra, 12(sp) +8000ff98: 23 20 f4 00 sw a5, 0(s0) +8000ff9c: 03 24 81 00 lw s0, 8(sp) +8000ffa0: 83 24 41 00 lw s1, 4(sp) +8000ffa4: 13 01 01 01 addi sp, sp, 16 +8000ffa8: 67 80 00 00 ret + +8000ffac __udivdi3: +8000ffac: 93 08 05 00 mv a7, a0 +8000ffb0: 93 87 05 00 mv a5, a1 +8000ffb4: 13 08 06 00 mv a6, a2 +8000ffb8: 13 85 06 00 mv a0, a3 +8000ffbc: 13 83 08 00 mv t1, a7 +8000ffc0: 63 94 06 28 bnez a3, 648 +8000ffc4: b7 66 01 80 lui a3, 524310 +8000ffc8: 93 86 86 09 addi a3, a3, 152 +8000ffcc: 63 f6 c5 0e bgeu a1, a2, 236 +8000ffd0: 37 07 01 00 lui a4, 16 +8000ffd4: 63 78 e6 0c bgeu a2, a4, 208 +8000ffd8: 13 07 f0 0f addi a4, zero, 255 +8000ffdc: 33 37 c7 00 sltu a4, a4, a2 +8000ffe0: 13 17 37 00 slli a4, a4, 3 +8000ffe4: 33 55 e6 00 srl a0, a2, a4 +8000ffe8: b3 86 a6 00 add a3, a3, a0 +8000ffec: 83 c6 06 00 lbu a3, 0(a3) +8000fff0: 13 05 00 02 addi a0, zero, 32 +8000fff4: 33 87 e6 00 add a4, a3, a4 +8000fff8: b3 06 e5 40 sub a3, a0, a4 +8000fffc: 63 0c e5 00 beq a0, a4, 24 +80010000: b3 97 d7 00 sll a5, a5, a3 +80010004: 33 d7 e8 00 srl a4, a7, a4 +80010008: 33 18 d6 00 sll a6, a2, a3 +8001000c: b3 65 f7 00 or a1, a4, a5 +80010010: 33 93 d8 00 sll t1, a7, a3 +80010014: 93 58 08 01 srli a7, a6, 16 +80010018: b3 d7 15 03 divu a5, a1, a7 +8001001c: 13 16 08 01 slli a2, a6, 16 +80010020: 13 56 06 01 srli a2, a2, 16 +80010024: 13 57 03 01 srli a4, t1, 16 +80010028: b3 f6 15 03 remu a3, a1, a7 +8001002c: 13 85 07 00 mv a0, a5 +80010030: b3 05 f6 02 mul a1, a2, a5 +80010034: 93 96 06 01 slli a3, a3, 16 +80010038: 33 e7 e6 00 or a4, a3, a4 +8001003c: 63 7e b7 00 bgeu a4, a1, 28 +80010040: 33 07 07 01 add a4, a4, a6 +80010044: 13 85 f7 ff addi a0, a5, -1 +80010048: 63 68 07 01 bltu a4, a6, 16 +8001004c: 63 76 b7 00 bgeu a4, a1, 12 +80010050: 13 85 e7 ff addi a0, a5, -2 +80010054: 33 07 07 01 add a4, a4, a6 +80010058: 33 07 b7 40 sub a4, a4, a1 +8001005c: b3 77 17 03 remu a5, a4, a7 +80010060: 13 13 03 01 slli t1, t1, 16 +80010064: 13 53 03 01 srli t1, t1, 16 +80010068: 33 57 17 03 divu a4, a4, a7 +8001006c: 93 97 07 01 slli a5, a5, 16 +80010070: 33 e3 67 00 or t1, a5, t1 +80010074: b3 06 e6 02 mul a3, a2, a4 +80010078: 13 06 07 00 mv a2, a4 +8001007c: 63 7c d3 00 bgeu t1, a3, 24 +80010080: 33 03 68 00 add t1, a6, t1 +80010084: 13 06 f7 ff addi a2, a4, -1 +80010088: 63 66 03 01 bltu t1, a6, 12 +8001008c: 63 74 d3 00 bgeu t1, a3, 8 +80010090: 13 06 e7 ff addi a2, a4, -2 +80010094: 13 15 05 01 slli a0, a0, 16 +80010098: 33 65 c5 00 or a0, a0, a2 +8001009c: 93 05 00 00 mv a1, zero +800100a0: 6f 00 40 0e j 228 +800100a4: 37 05 00 01 lui a0, 4096 +800100a8: 13 07 00 01 addi a4, zero, 16 +800100ac: e3 6c a6 f2 bltu a2, a0, -200 +800100b0: 13 07 80 01 addi a4, zero, 24 +800100b4: 6f f0 1f f3 j -208 +800100b8: 63 16 06 00 bnez a2, 12 +800100bc: 13 07 10 00 addi a4, zero, 1 +800100c0: 33 58 c7 02 divu a6, a4, a2 +800100c4: 37 07 01 00 lui a4, 16 +800100c8: 63 70 e8 0c bgeu a6, a4, 192 +800100cc: 13 07 f0 0f addi a4, zero, 255 +800100d0: 63 74 07 01 bgeu a4, a6, 8 +800100d4: 13 05 80 00 addi a0, zero, 8 +800100d8: 33 57 a8 00 srl a4, a6, a0 +800100dc: b3 86 e6 00 add a3, a3, a4 +800100e0: 03 c7 06 00 lbu a4, 0(a3) +800100e4: 13 06 00 02 addi a2, zero, 32 +800100e8: 33 07 a7 00 add a4, a4, a0 +800100ec: b3 06 e6 40 sub a3, a2, a4 +800100f0: 63 16 e6 0a bne a2, a4, 172 +800100f4: b3 87 07 41 sub a5, a5, a6 +800100f8: 93 05 10 00 addi a1, zero, 1 +800100fc: 93 58 08 01 srli a7, a6, 16 +80010100: 13 16 08 01 slli a2, a6, 16 +80010104: 13 56 06 01 srli a2, a2, 16 +80010108: 13 57 03 01 srli a4, t1, 16 +8001010c: b3 f6 17 03 remu a3, a5, a7 +80010110: b3 d7 17 03 divu a5, a5, a7 +80010114: 93 96 06 01 slli a3, a3, 16 +80010118: 33 e7 e6 00 or a4, a3, a4 +8001011c: 33 0e f6 02 mul t3, a2, a5 +80010120: 13 85 07 00 mv a0, a5 +80010124: 63 7e c7 01 bgeu a4, t3, 28 +80010128: 33 07 07 01 add a4, a4, a6 +8001012c: 13 85 f7 ff addi a0, a5, -1 +80010130: 63 68 07 01 bltu a4, a6, 16 +80010134: 63 76 c7 01 bgeu a4, t3, 12 +80010138: 13 85 e7 ff addi a0, a5, -2 +8001013c: 33 07 07 01 add a4, a4, a6 +80010140: 33 07 c7 41 sub a4, a4, t3 +80010144: b3 77 17 03 remu a5, a4, a7 +80010148: 13 13 03 01 slli t1, t1, 16 +8001014c: 13 53 03 01 srli t1, t1, 16 +80010150: 33 57 17 03 divu a4, a4, a7 +80010154: 93 97 07 01 slli a5, a5, 16 +80010158: 33 e3 67 00 or t1, a5, t1 +8001015c: b3 06 e6 02 mul a3, a2, a4 +80010160: 13 06 07 00 mv a2, a4 +80010164: 63 7c d3 00 bgeu t1, a3, 24 +80010168: 33 03 68 00 add t1, a6, t1 +8001016c: 13 06 f7 ff addi a2, a4, -1 +80010170: 63 66 03 01 bltu t1, a6, 12 +80010174: 63 74 d3 00 bgeu t1, a3, 8 +80010178: 13 06 e7 ff addi a2, a4, -2 +8001017c: 13 15 05 01 slli a0, a0, 16 +80010180: 33 65 c5 00 or a0, a0, a2 +80010184: 67 80 00 00 ret +80010188: 37 07 00 01 lui a4, 4096 +8001018c: 13 05 00 01 addi a0, zero, 16 +80010190: e3 64 e8 f4 bltu a6, a4, -184 +80010194: 13 05 80 01 addi a0, zero, 24 +80010198: 6f f0 1f f4 j -192 +8001019c: 33 18 d8 00 sll a6, a6, a3 +800101a0: b3 d5 e7 00 srl a1, a5, a4 +800101a4: 33 93 d8 00 sll t1, a7, a3 +800101a8: b3 97 d7 00 sll a5, a5, a3 +800101ac: 33 d7 e8 00 srl a4, a7, a4 +800101b0: 93 58 08 01 srli a7, a6, 16 +800101b4: 33 66 f7 00 or a2, a4, a5 +800101b8: 33 f7 15 03 remu a4, a1, a7 +800101bc: 93 17 08 01 slli a5, a6, 16 +800101c0: 93 d7 07 01 srli a5, a5, 16 +800101c4: 13 55 06 01 srli a0, a2, 16 +800101c8: b3 d5 15 03 divu a1, a1, a7 +800101cc: 13 17 07 01 slli a4, a4, 16 +800101d0: 33 67 a7 00 or a4, a4, a0 +800101d4: b3 86 b7 02 mul a3, a5, a1 +800101d8: 13 85 05 00 mv a0, a1 +800101dc: 63 7e d7 00 bgeu a4, a3, 28 +800101e0: 33 07 07 01 add a4, a4, a6 +800101e4: 13 85 f5 ff addi a0, a1, -1 +800101e8: 63 68 07 01 bltu a4, a6, 16 +800101ec: 63 76 d7 00 bgeu a4, a3, 12 +800101f0: 13 85 e5 ff addi a0, a1, -2 +800101f4: 33 07 07 01 add a4, a4, a6 +800101f8: b3 06 d7 40 sub a3, a4, a3 +800101fc: 33 f7 16 03 remu a4, a3, a7 +80010200: 13 16 06 01 slli a2, a2, 16 +80010204: 13 56 06 01 srli a2, a2, 16 +80010208: b3 d6 16 03 divu a3, a3, a7 +8001020c: 13 17 07 01 slli a4, a4, 16 +80010210: b3 88 d7 02 mul a7, a5, a3 +80010214: b3 67 c7 00 or a5, a4, a2 +80010218: 13 87 06 00 mv a4, a3 +8001021c: 63 fe 17 01 bgeu a5, a7, 28 +80010220: b3 87 07 01 add a5, a5, a6 +80010224: 13 87 f6 ff addi a4, a3, -1 +80010228: 63 e8 07 01 bltu a5, a6, 16 +8001022c: 63 f6 17 01 bgeu a5, a7, 12 +80010230: 13 87 e6 ff addi a4, a3, -2 +80010234: b3 87 07 01 add a5, a5, a6 +80010238: 93 15 05 01 slli a1, a0, 16 +8001023c: b3 87 17 41 sub a5, a5, a7 +80010240: b3 e5 e5 00 or a1, a1, a4 +80010244: 6f f0 9f eb j -328 +80010248: 63 e6 d5 18 bltu a1, a3, 396 +8001024c: 37 07 01 00 lui a4, 16 +80010250: 63 f4 e6 04 bgeu a3, a4, 72 +80010254: 13 07 f0 0f addi a4, zero, 255 +80010258: b3 35 d7 00 sltu a1, a4, a3 +8001025c: 93 95 35 00 slli a1, a1, 3 +80010260: 37 67 01 80 lui a4, 524310 +80010264: 33 d5 b6 00 srl a0, a3, a1 +80010268: 13 07 87 09 addi a4, a4, 152 +8001026c: 33 07 a7 00 add a4, a4, a0 +80010270: 03 47 07 00 lbu a4, 0(a4) +80010274: 13 05 00 02 addi a0, zero, 32 +80010278: 33 07 b7 00 add a4, a4, a1 +8001027c: b3 05 e5 40 sub a1, a0, a4 +80010280: 63 16 e5 02 bne a0, a4, 44 +80010284: 13 05 10 00 addi a0, zero, 1 +80010288: e3 ee f6 ee bltu a3, a5, -260 +8001028c: 33 b5 c8 00 sltu a0, a7, a2 +80010290: 13 45 15 00 xori a0, a0, 1 +80010294: 6f f0 1f ef j -272 +80010298: 37 07 00 01 lui a4, 4096 +8001029c: 93 05 00 01 addi a1, zero, 16 +800102a0: e3 e0 e6 fc bltu a3, a4, -64 +800102a4: 93 05 80 01 addi a1, zero, 24 +800102a8: 6f f0 9f fb j -72 +800102ac: 33 53 e6 00 srl t1, a2, a4 +800102b0: b3 96 b6 00 sll a3, a3, a1 +800102b4: 33 63 d3 00 or t1, t1, a3 +800102b8: 13 55 03 01 srli a0, t1, 16 +800102bc: b3 1e b6 00 sll t4, a2, a1 +800102c0: 33 d6 e7 00 srl a2, a5, a4 +800102c4: b3 76 a6 02 remu a3, a2, a0 +800102c8: b3 97 b7 00 sll a5, a5, a1 +800102cc: 33 d7 e8 00 srl a4, a7, a4 +800102d0: 33 68 f7 00 or a6, a4, a5 +800102d4: 93 17 03 01 slli a5, t1, 16 +800102d8: 93 d7 07 01 srli a5, a5, 16 +800102dc: 13 57 08 01 srli a4, a6, 16 +800102e0: 33 56 a6 02 divu a2, a2, a0 +800102e4: 93 96 06 01 slli a3, a3, 16 +800102e8: 33 e7 e6 00 or a4, a3, a4 +800102ec: 33 8f c7 02 mul t5, a5, a2 +800102f0: 13 0e 06 00 mv t3, a2 +800102f4: 63 7e e7 01 bgeu a4, t5, 28 +800102f8: 33 07 67 00 add a4, a4, t1 +800102fc: 13 0e f6 ff addi t3, a2, -1 +80010300: 63 68 67 00 bltu a4, t1, 16 +80010304: 63 76 e7 01 bgeu a4, t5, 12 +80010308: 13 0e e6 ff addi t3, a2, -2 +8001030c: 33 07 67 00 add a4, a4, t1 +80010310: 33 07 e7 41 sub a4, a4, t5 +80010314: b3 76 a7 02 remu a3, a4, a0 +80010318: 33 57 a7 02 divu a4, a4, a0 +8001031c: 93 96 06 01 slli a3, a3, 16 +80010320: 33 86 e7 02 mul a2, a5, a4 +80010324: 93 17 08 01 slli a5, a6, 16 +80010328: 93 d7 07 01 srli a5, a5, 16 +8001032c: b3 e7 f6 00 or a5, a3, a5 +80010330: 93 06 07 00 mv a3, a4 +80010334: 63 fe c7 00 bgeu a5, a2, 28 +80010338: b3 87 67 00 add a5, a5, t1 +8001033c: 93 06 f7 ff addi a3, a4, -1 +80010340: 63 e8 67 00 bltu a5, t1, 16 +80010344: 63 f6 c7 00 bgeu a5, a2, 12 +80010348: 93 06 e7 ff addi a3, a4, -2 +8001034c: b3 87 67 00 add a5, a5, t1 +80010350: 13 15 0e 01 slli a0, t3, 16 +80010354: 37 0e 01 00 lui t3, 16 +80010358: 33 65 d5 00 or a0, a0, a3 +8001035c: 93 06 fe ff addi a3, t3, -1 +80010360: 33 78 d5 00 and a6, a0, a3 +80010364: b3 87 c7 40 sub a5, a5, a2 +80010368: b3 f6 de 00 and a3, t4, a3 +8001036c: 13 56 05 01 srli a2, a0, 16 +80010370: 93 de 0e 01 srli t4, t4, 16 +80010374: 33 03 d8 02 mul t1, a6, a3 +80010378: b3 06 d6 02 mul a3, a2, a3 +8001037c: 13 57 03 01 srli a4, t1, 16 +80010380: 33 08 d8 03 mul a6, a6, t4 +80010384: 33 08 d8 00 add a6, a6, a3 +80010388: 33 07 07 01 add a4, a4, a6 +8001038c: 33 06 d6 03 mul a2, a2, t4 +80010390: 63 74 d7 00 bgeu a4, a3, 8 +80010394: 33 06 c6 01 add a2, a2, t3 +80010398: 93 56 07 01 srli a3, a4, 16 +8001039c: 33 86 c6 00 add a2, a3, a2 +800103a0: 63 e6 c7 02 bltu a5, a2, 44 +800103a4: e3 9c c7 ce bne a5, a2, -776 +800103a8: b7 07 01 00 lui a5, 16 +800103ac: 93 87 f7 ff addi a5, a5, -1 +800103b0: 33 77 f7 00 and a4, a4, a5 +800103b4: 13 17 07 01 slli a4, a4, 16 +800103b8: 33 73 f3 00 and t1, t1, a5 +800103bc: b3 98 b8 00 sll a7, a7, a1 +800103c0: 33 07 67 00 add a4, a4, t1 +800103c4: 93 05 00 00 mv a1, zero +800103c8: e3 fe e8 da bgeu a7, a4, -580 +800103cc: 13 05 f5 ff addi a0, a0, -1 +800103d0: 6f f0 df cc j -820 +800103d4: 93 05 00 00 mv a1, zero +800103d8: 13 05 00 00 mv a0, zero +800103dc: 6f f0 9f da j -600 + +800103e0 __umoddi3: +800103e0: 93 08 06 00 mv a7, a2 +800103e4: 13 87 06 00 mv a4, a3 +800103e8: 93 07 05 00 mv a5, a0 +800103ec: 13 88 05 00 mv a6, a1 +800103f0: 63 9c 06 22 bnez a3, 568 +800103f4: b7 66 01 80 lui a3, 524310 +800103f8: 93 86 86 09 addi a3, a3, 152 +800103fc: 63 fc c5 0c bgeu a1, a2, 216 +80010400: 37 03 01 00 lui t1, 16 +80010404: 63 7e 66 0a bgeu a2, t1, 188 +80010408: 13 03 f0 0f addi t1, zero, 255 +8001040c: 63 74 c3 00 bgeu t1, a2, 8 +80010410: 13 07 80 00 addi a4, zero, 8 +80010414: 33 53 e6 00 srl t1, a2, a4 +80010418: b3 86 66 00 add a3, a3, t1 +8001041c: 03 ce 06 00 lbu t3, 0(a3) +80010420: 33 0e ee 00 add t3, t3, a4 +80010424: 13 07 00 02 addi a4, zero, 32 +80010428: 33 03 c7 41 sub t1, a4, t3 +8001042c: 63 0c c7 01 beq a4, t3, 24 +80010430: b3 95 65 00 sll a1, a1, t1 +80010434: 33 5e c5 01 srl t3, a0, t3 +80010438: b3 18 66 00 sll a7, a2, t1 +8001043c: 33 68 be 00 or a6, t3, a1 +80010440: b3 17 65 00 sll a5, a0, t1 +80010444: 13 d6 08 01 srli a2, a7, 16 +80010448: 33 77 c8 02 remu a4, a6, a2 +8001044c: 13 95 08 01 slli a0, a7, 16 +80010450: 13 55 05 01 srli a0, a0, 16 +80010454: 93 d6 07 01 srli a3, a5, 16 +80010458: 33 58 c8 02 divu a6, a6, a2 +8001045c: 13 17 07 01 slli a4, a4, 16 +80010460: b3 66 d7 00 or a3, a4, a3 +80010464: 33 08 05 03 mul a6, a0, a6 +80010468: 63 fa 06 01 bgeu a3, a6, 20 +8001046c: b3 86 16 01 add a3, a3, a7 +80010470: 63 e6 16 01 bltu a3, a7, 12 +80010474: 63 f4 06 01 bgeu a3, a6, 8 +80010478: b3 86 16 01 add a3, a3, a7 +8001047c: b3 86 06 41 sub a3, a3, a6 +80010480: 33 f7 c6 02 remu a4, a3, a2 +80010484: 93 97 07 01 slli a5, a5, 16 +80010488: 93 d7 07 01 srli a5, a5, 16 +8001048c: b3 d6 c6 02 divu a3, a3, a2 +80010490: b3 06 d5 02 mul a3, a0, a3 +80010494: 13 15 07 01 slli a0, a4, 16 +80010498: b3 67 f5 00 or a5, a0, a5 +8001049c: 63 fa d7 00 bgeu a5, a3, 20 +800104a0: b3 87 17 01 add a5, a5, a7 +800104a4: 63 e6 17 01 bltu a5, a7, 12 +800104a8: 63 f4 d7 00 bgeu a5, a3, 8 +800104ac: b3 87 17 01 add a5, a5, a7 +800104b0: b3 87 d7 40 sub a5, a5, a3 +800104b4: 33 d5 67 00 srl a0, a5, t1 +800104b8: 93 05 00 00 mv a1, zero +800104bc: 67 80 00 00 ret +800104c0: 37 03 00 01 lui t1, 4096 +800104c4: 13 07 00 01 addi a4, zero, 16 +800104c8: e3 66 66 f4 bltu a2, t1, -180 +800104cc: 13 07 80 01 addi a4, zero, 24 +800104d0: 6f f0 5f f4 j -188 +800104d4: 63 16 06 00 bnez a2, 12 +800104d8: 13 06 10 00 addi a2, zero, 1 +800104dc: b3 58 16 03 divu a7, a2, a7 +800104e0: 37 06 01 00 lui a2, 16 +800104e4: 63 f2 c8 0a bgeu a7, a2, 164 +800104e8: 13 06 f0 0f addi a2, zero, 255 +800104ec: 63 74 16 01 bgeu a2, a7, 8 +800104f0: 13 07 80 00 addi a4, zero, 8 +800104f4: 33 d6 e8 00 srl a2, a7, a4 +800104f8: b3 86 c6 00 add a3, a3, a2 +800104fc: 03 ce 06 00 lbu t3, 0(a3) +80010500: 33 0e ee 00 add t3, t3, a4 +80010504: 13 07 00 02 addi a4, zero, 32 +80010508: 33 03 c7 41 sub t1, a4, t3 +8001050c: 63 18 c7 09 bne a4, t3, 144 +80010510: b3 85 15 41 sub a1, a1, a7 +80010514: 13 d7 08 01 srli a4, a7, 16 +80010518: 13 95 08 01 slli a0, a7, 16 +8001051c: 13 55 05 01 srli a0, a0, 16 +80010520: 13 d6 07 01 srli a2, a5, 16 +80010524: b3 f6 e5 02 remu a3, a1, a4 +80010528: b3 d5 e5 02 divu a1, a1, a4 +8001052c: 93 96 06 01 slli a3, a3, 16 +80010530: b3 e6 c6 00 or a3, a3, a2 +80010534: b3 05 b5 02 mul a1, a0, a1 +80010538: 63 fa b6 00 bgeu a3, a1, 20 +8001053c: b3 86 16 01 add a3, a3, a7 +80010540: 63 e6 16 01 bltu a3, a7, 12 +80010544: 63 f4 b6 00 bgeu a3, a1, 8 +80010548: b3 86 16 01 add a3, a3, a7 +8001054c: b3 85 b6 40 sub a1, a3, a1 +80010550: b3 f6 e5 02 remu a3, a1, a4 +80010554: 93 97 07 01 slli a5, a5, 16 +80010558: 93 d7 07 01 srli a5, a5, 16 +8001055c: b3 d5 e5 02 divu a1, a1, a4 +80010560: b3 05 b5 02 mul a1, a0, a1 +80010564: 13 95 06 01 slli a0, a3, 16 +80010568: b3 67 f5 00 or a5, a0, a5 +8001056c: 63 fa b7 00 bgeu a5, a1, 20 +80010570: b3 87 17 01 add a5, a5, a7 +80010574: 63 e6 17 01 bltu a5, a7, 12 +80010578: 63 f4 b7 00 bgeu a5, a1, 8 +8001057c: b3 87 17 01 add a5, a5, a7 +80010580: b3 87 b7 40 sub a5, a5, a1 +80010584: 6f f0 1f f3 j -208 +80010588: 37 06 00 01 lui a2, 4096 +8001058c: 13 07 00 01 addi a4, zero, 16 +80010590: e3 e2 c8 f6 bltu a7, a2, -156 +80010594: 13 07 80 01 addi a4, zero, 24 +80010598: 6f f0 df f5 j -164 +8001059c: b3 98 68 00 sll a7, a7, t1 +800105a0: 33 d7 c5 01 srl a4, a1, t3 +800105a4: b3 17 65 00 sll a5, a0, t1 +800105a8: 33 5e c5 01 srl t3, a0, t3 +800105ac: 13 d5 08 01 srli a0, a7, 16 +800105b0: b3 76 a7 02 remu a3, a4, a0 +800105b4: b3 95 65 00 sll a1, a1, t1 +800105b8: 33 6e be 00 or t3, t3, a1 +800105bc: 93 95 08 01 slli a1, a7, 16 +800105c0: 93 d5 05 01 srli a1, a1, 16 +800105c4: 13 56 0e 01 srli a2, t3, 16 +800105c8: 33 57 a7 02 divu a4, a4, a0 +800105cc: 93 96 06 01 slli a3, a3, 16 +800105d0: b3 e6 c6 00 or a3, a3, a2 +800105d4: 33 87 e5 02 mul a4, a1, a4 +800105d8: 63 fa e6 00 bgeu a3, a4, 20 +800105dc: b3 86 16 01 add a3, a3, a7 +800105e0: 63 e6 16 01 bltu a3, a7, 12 +800105e4: 63 f4 e6 00 bgeu a3, a4, 8 +800105e8: b3 86 16 01 add a3, a3, a7 +800105ec: 33 86 e6 40 sub a2, a3, a4 +800105f0: b3 76 a6 02 remu a3, a2, a0 +800105f4: 13 1e 0e 01 slli t3, t3, 16 +800105f8: 13 5e 0e 01 srli t3, t3, 16 +800105fc: 33 56 a6 02 divu a2, a2, a0 +80010600: 93 96 06 01 slli a3, a3, 16 +80010604: 33 86 c5 02 mul a2, a1, a2 +80010608: b3 e5 c6 01 or a1, a3, t3 +8001060c: 63 fa c5 00 bgeu a1, a2, 20 +80010610: b3 85 15 01 add a1, a1, a7 +80010614: 63 e6 15 01 bltu a1, a7, 12 +80010618: 63 f4 c5 00 bgeu a1, a2, 8 +8001061c: b3 85 15 01 add a1, a1, a7 +80010620: b3 85 c5 40 sub a1, a1, a2 +80010624: 6f f0 1f ef j -272 +80010628: e3 ea d5 e8 bltu a1, a3, -364 +8001062c: 37 07 01 00 lui a4, 16 +80010630: 63 fc e6 04 bgeu a3, a4, 88 +80010634: 13 0e f0 0f addi t3, zero, 255 +80010638: 33 37 de 00 sltu a4, t3, a3 +8001063c: 13 17 37 00 slli a4, a4, 3 +80010640: b7 68 01 80 lui a7, 524310 +80010644: 33 d3 e6 00 srl t1, a3, a4 +80010648: 93 88 88 09 addi a7, a7, 152 +8001064c: b3 88 68 00 add a7, a7, t1 +80010650: 03 ce 08 00 lbu t3, 0(a7) +80010654: 33 0e ee 00 add t3, t3, a4 +80010658: 13 07 00 02 addi a4, zero, 32 +8001065c: 33 03 c7 41 sub t1, a4, t3 +80010660: 63 1e c7 03 bne a4, t3, 60 +80010664: 63 e4 b6 00 bltu a3, a1, 8 +80010668: 63 6a c5 00 bltu a0, a2, 20 +8001066c: b3 07 c5 40 sub a5, a0, a2 +80010670: b3 85 d5 40 sub a1, a1, a3 +80010674: 33 35 f5 00 sltu a0, a0, a5 +80010678: 33 88 a5 40 sub a6, a1, a0 +8001067c: 13 85 07 00 mv a0, a5 +80010680: 93 05 08 00 mv a1, a6 +80010684: 6f f0 9f e3 j -456 +80010688: b7 08 00 01 lui a7, 4096 +8001068c: 13 07 00 01 addi a4, zero, 16 +80010690: e3 e8 16 fb bltu a3, a7, -80 +80010694: 13 07 80 01 addi a4, zero, 24 +80010698: 6f f0 9f fa j -88 +8001069c: 33 57 c6 01 srl a4, a2, t3 +800106a0: b3 96 66 00 sll a3, a3, t1 +800106a4: 33 6f d7 00 or t5, a4, a3 +800106a8: b3 d7 c5 01 srl a5, a1, t3 +800106ac: 13 57 0f 01 srli a4, t5, 16 +800106b0: b3 f8 e7 02 remu a7, a5, a4 +800106b4: b3 95 65 00 sll a1, a1, t1 +800106b8: 33 58 c5 01 srl a6, a0, t3 +800106bc: 33 68 b8 00 or a6, a6, a1 +800106c0: 93 15 0f 01 slli a1, t5, 16 +800106c4: 93 d5 05 01 srli a1, a1, 16 +800106c8: 93 56 08 01 srli a3, a6, 16 +800106cc: 33 16 66 00 sll a2, a2, t1 +800106d0: 33 15 65 00 sll a0, a0, t1 +800106d4: b3 d7 e7 02 divu a5, a5, a4 +800106d8: 93 98 08 01 slli a7, a7, 16 +800106dc: b3 e6 d8 00 or a3, a7, a3 +800106e0: b3 8e f5 02 mul t4, a1, a5 +800106e4: 93 88 07 00 mv a7, a5 +800106e8: 63 fe d6 01 bgeu a3, t4, 28 +800106ec: b3 86 e6 01 add a3, a3, t5 +800106f0: 93 88 f7 ff addi a7, a5, -1 +800106f4: 63 e8 e6 01 bltu a3, t5, 16 +800106f8: 63 f6 d6 01 bgeu a3, t4, 12 +800106fc: 93 88 e7 ff addi a7, a5, -2 +80010700: b3 86 e6 01 add a3, a3, t5 +80010704: b3 86 d6 41 sub a3, a3, t4 +80010708: b3 fe e6 02 remu t4, a3, a4 +8001070c: 13 18 08 01 slli a6, a6, 16 +80010710: 13 58 08 01 srli a6, a6, 16 +80010714: b3 d6 e6 02 divu a3, a3, a4 +80010718: 93 9e 0e 01 slli t4, t4, 16 +8001071c: b3 ee 0e 01 or t4, t4, a6 +80010720: b3 85 d5 02 mul a1, a1, a3 +80010724: 93 87 06 00 mv a5, a3 +80010728: 63 fe be 00 bgeu t4, a1, 28 +8001072c: b3 8e ee 01 add t4, t4, t5 +80010730: 93 87 f6 ff addi a5, a3, -1 +80010734: 63 e8 ee 01 bltu t4, t5, 16 +80010738: 63 f6 be 00 bgeu t4, a1, 12 +8001073c: 93 87 e6 ff addi a5, a3, -2 +80010740: b3 8e ee 01 add t4, t4, t5 +80010744: b3 85 be 40 sub a1, t4, a1 +80010748: 93 98 08 01 slli a7, a7, 16 +8001074c: b7 0e 01 00 lui t4, 16 +80010750: b3 e8 f8 00 or a7, a7, a5 +80010754: 93 87 fe ff addi a5, t4, -1 +80010758: 33 f8 f8 00 and a6, a7, a5 +8001075c: 93 56 06 01 srli a3, a2, 16 +80010760: 93 d8 08 01 srli a7, a7, 16 +80010764: b3 77 f6 00 and a5, a2, a5 +80010768: 33 07 f8 02 mul a4, a6, a5 +8001076c: b3 87 f8 02 mul a5, a7, a5 +80010770: 33 08 d8 02 mul a6, a6, a3 +80010774: b3 88 d8 02 mul a7, a7, a3 +80010778: 33 08 f8 00 add a6, a6, a5 +8001077c: 93 56 07 01 srli a3, a4, 16 +80010780: b3 86 06 01 add a3, a3, a6 +80010784: 63 f4 f6 00 bgeu a3, a5, 8 +80010788: b3 88 d8 01 add a7, a7, t4 +8001078c: b7 07 01 00 lui a5, 16 +80010790: 93 87 f7 ff addi a5, a5, -1 +80010794: 13 d8 06 01 srli a6, a3, 16 +80010798: b3 f6 f6 00 and a3, a3, a5 +8001079c: 93 96 06 01 slli a3, a3, 16 +800107a0: 33 77 f7 00 and a4, a4, a5 +800107a4: b3 08 18 01 add a7, a6, a7 +800107a8: 33 87 e6 00 add a4, a3, a4 +800107ac: 63 e6 15 01 bltu a1, a7, 12 +800107b0: 63 9e 15 01 bne a1, a7, 28 +800107b4: 63 7c e5 00 bgeu a0, a4, 24 +800107b8: 33 06 c7 40 sub a2, a4, a2 +800107bc: 33 37 c7 00 sltu a4, a4, a2 +800107c0: 33 07 e7 01 add a4, a4, t5 +800107c4: b3 88 e8 40 sub a7, a7, a4 +800107c8: 13 07 06 00 mv a4, a2 +800107cc: 33 07 e5 40 sub a4, a0, a4 +800107d0: 33 35 e5 00 sltu a0, a0, a4 +800107d4: b3 85 15 41 sub a1, a1, a7 +800107d8: b3 85 a5 40 sub a1, a1, a0 +800107dc: b3 97 c5 01 sll a5, a1, t3 +800107e0: 33 57 67 00 srl a4, a4, t1 +800107e4: 33 e5 e7 00 or a0, a5, a4 +800107e8: b3 d5 65 00 srl a1, a1, t1 +800107ec: 6f f0 1f cd j -816 + +800107f0 __divdf3: +800107f0: 13 01 01 fd addi sp, sp, -48 +800107f4: 23 24 81 02 sw s0, 40(sp) +800107f8: 23 2a 51 01 sw s5, 20(sp) +800107fc: 23 24 81 01 sw s8, 8(sp) +80010800: 23 26 11 02 sw ra, 44(sp) +80010804: 23 22 91 02 sw s1, 36(sp) +80010808: 23 20 21 03 sw s2, 32(sp) +8001080c: 23 2e 31 01 sw s3, 28(sp) +80010810: 23 2c 41 01 sw s4, 24(sp) +80010814: 23 28 61 01 sw s6, 16(sp) +80010818: 23 26 71 01 sw s7, 12(sp) +8001081c: 23 22 91 01 sw s9, 4(sp) +80010820: 13 04 05 00 mv s0, a0 +80010824: 13 0c 06 00 mv s8, a2 +80010828: 93 8a 06 00 mv s5, a3 +8001082c: 73 29 20 00 frrm s2 +80010830: 93 d7 45 01 srli a5, a1, 20 +80010834: 93 9b c5 00 slli s7, a1, 12 +80010838: 13 97 57 01 slli a4, a5, 21 +8001083c: 93 db cb 00 srli s7, s7, 12 +80010840: 13 da f5 01 srli s4, a1, 31 +80010844: 63 0c 07 02 beqz a4, 56 +80010848: 13 fb f7 7f andi s6, a5, 2047 +8001084c: 93 07 f0 7f addi a5, zero, 2047 +80010850: 63 08 fb 08 beq s6, a5, 144 +80010854: 13 57 d5 01 srli a4, a0, 29 +80010858: 93 9b 3b 00 slli s7, s7, 3 +8001085c: b3 6b 77 01 or s7, a4, s7 +80010860: b7 07 80 00 lui a5, 2048 +80010864: b3 eb fb 00 or s7, s7, a5 +80010868: 93 19 35 00 slli s3, a0, 3 +8001086c: 13 0b 1b c0 addi s6, s6, -1023 +80010870: 93 0c 00 00 mv s9, zero +80010874: 93 04 00 00 mv s1, zero +80010878: 6f 00 80 08 j 136 +8001087c: b3 e7 ab 00 or a5, s7, a0 +80010880: 63 8e 07 0e beqz a5, 252 +80010884: 63 80 0b 04 beqz s7, 64 +80010888: 13 85 0b 00 mv a0, s7 +8001088c: ef 40 d0 43 jal 19516 +80010890: 13 07 55 ff addi a4, a0, -11 +80010894: 93 07 c0 01 addi a5, zero, 28 +80010898: 63 cc e7 02 blt a5, a4, 56 +8001089c: 93 06 d0 01 addi a3, zero, 29 +800108a0: 93 09 85 ff addi s3, a0, -8 +800108a4: b3 86 e6 40 sub a3, a3, a4 +800108a8: b3 9b 3b 01 sll s7, s7, s3 +800108ac: b3 56 d4 00 srl a3, s0, a3 +800108b0: b3 eb 76 01 or s7, a3, s7 +800108b4: b3 19 34 01 sll s3, s0, s3 +800108b8: 93 05 d0 c0 addi a1, zero, -1011 +800108bc: 33 8b a5 40 sub s6, a1, a0 +800108c0: 6f f0 1f fb j -80 +800108c4: ef 40 50 40 jal 19460 +800108c8: 13 05 05 02 addi a0, a0, 32 +800108cc: 6f f0 5f fc j -60 +800108d0: 93 0b 85 fd addi s7, a0, -40 +800108d4: b3 1b 74 01 sll s7, s0, s7 +800108d8: 93 09 00 00 mv s3, zero +800108dc: 6f f0 df fd j -36 +800108e0: 33 e4 ab 00 or s0, s7, a0 +800108e4: 63 06 04 0a beqz s0, 172 +800108e8: 93 97 cb 00 slli a5, s7, 12 +800108ec: 93 09 05 00 mv s3, a0 +800108f0: 13 0b f0 7f addi s6, zero, 2047 +800108f4: 93 0c 30 00 addi s9, zero, 3 +800108f8: 93 04 00 01 addi s1, zero, 16 +800108fc: e3 cc 07 f6 bltz a5, -136 +80010900: 13 d7 4a 01 srli a4, s5, 20 +80010904: 13 95 ca 00 slli a0, s5, 12 +80010908: 93 16 57 01 slli a3, a4, 21 +8001090c: 93 07 0c 00 mv a5, s8 +80010910: 13 54 c5 00 srli s0, a0, 12 +80010914: 93 75 f7 7f andi a1, a4, 2047 +80010918: 93 da fa 01 srli s5, s5, 31 +8001091c: 63 84 06 08 beqz a3, 136 +80010920: 13 07 f0 7f addi a4, zero, 2047 +80010924: 63 86 e5 0e beq a1, a4, 236 +80010928: 93 57 dc 01 srli a5, s8, 29 +8001092c: 13 15 34 00 slli a0, s0, 3 +80010930: 33 e5 a7 00 or a0, a5, a0 +80010934: 37 04 80 00 lui s0, 2048 +80010938: 33 64 85 00 or s0, a0, s0 +8001093c: 93 17 3c 00 slli a5, s8, 3 +80010940: 13 85 15 c0 addi a0, a1, -1023 +80010944: 13 07 00 00 mv a4, zero +80010948: 93 96 2c 00 slli a3, s9, 2 +8001094c: b3 e6 e6 00 or a3, a3, a4 +80010950: b3 05 ab 40 sub a1, s6, a0 +80010954: 93 86 f6 ff addi a3, a3, -1 +80010958: 13 05 e0 00 addi a0, zero, 14 +8001095c: 33 46 5a 01 xor a2, s4, s5 +80010960: 63 60 d5 10 bltu a0, a3, 256 +80010964: 37 65 01 80 lui a0, 524310 +80010968: 93 96 26 00 slli a3, a3, 2 +8001096c: 13 05 45 fe addi a0, a0, -28 +80010970: b3 86 a6 00 add a3, a3, a0 +80010974: 83 a6 06 00 lw a3, 0(a3) +80010978: 67 80 06 00 jr a3 +8001097c: 93 0b 00 00 mv s7, zero +80010980: 93 09 00 00 mv s3, zero +80010984: 13 0b 00 00 mv s6, zero +80010988: 93 0c 10 00 addi s9, zero, 1 +8001098c: 6f f0 9f ee j -280 +80010990: 93 0b 00 00 mv s7, zero +80010994: 93 09 00 00 mv s3, zero +80010998: 13 0b f0 7f addi s6, zero, 2047 +8001099c: 93 0c 20 00 addi s9, zero, 2 +800109a0: 6f f0 5f ed j -300 +800109a4: b3 67 84 01 or a5, s0, s8 +800109a8: 63 84 07 08 beqz a5, 136 +800109ac: 63 02 04 04 beqz s0, 68 +800109b0: 13 05 04 00 mv a0, s0 +800109b4: ef 40 50 31 jal 19220 +800109b8: 93 05 05 00 mv a1, a0 +800109bc: 93 86 55 ff addi a3, a1, -11 +800109c0: 93 07 c0 01 addi a5, zero, 28 +800109c4: 63 ce d7 02 blt a5, a3, 60 +800109c8: 13 07 d0 01 addi a4, zero, 29 +800109cc: 93 87 85 ff addi a5, a1, -8 +800109d0: 33 07 d7 40 sub a4, a4, a3 +800109d4: 33 15 f4 00 sll a0, s0, a5 +800109d8: 33 57 ec 00 srl a4, s8, a4 +800109dc: 33 64 a7 00 or s0, a4, a0 +800109e0: b3 17 fc 00 sll a5, s8, a5 +800109e4: 13 07 d0 c0 addi a4, zero, -1011 +800109e8: 33 05 b7 40 sub a0, a4, a1 +800109ec: 6f f0 9f f5 j -168 +800109f0: 13 05 0c 00 mv a0, s8 +800109f4: ef 40 50 2d jal 19156 +800109f8: 93 05 05 02 addi a1, a0, 32 +800109fc: 6f f0 1f fc j -64 +80010a00: 13 85 85 fd addi a0, a1, -40 +80010a04: 33 14 ac 00 sll s0, s8, a0 +80010a08: 93 07 00 00 mv a5, zero +80010a0c: 6f f0 9f fd j -40 +80010a10: 33 66 84 01 or a2, s0, s8 +80010a14: 63 08 06 02 beqz a2, 48 +80010a18: 13 17 c4 00 slli a4, s0, 12 +80010a1c: 13 05 f0 7f addi a0, zero, 2047 +80010a20: 63 4c 07 02 bltz a4, 56 +80010a24: 13 07 30 00 addi a4, zero, 3 +80010a28: 93 04 00 01 addi s1, zero, 16 +80010a2c: 6f f0 df f1 j -228 +80010a30: 13 04 00 00 mv s0, zero +80010a34: 93 07 00 00 mv a5, zero +80010a38: 13 05 00 00 mv a0, zero +80010a3c: 13 07 10 00 addi a4, zero, 1 +80010a40: 6f f0 9f f0 j -248 +80010a44: 13 04 00 00 mv s0, zero +80010a48: 93 07 00 00 mv a5, zero +80010a4c: 13 05 f0 7f addi a0, zero, 2047 +80010a50: 13 07 20 00 addi a4, zero, 2 +80010a54: 6f f0 5f ef j -268 +80010a58: 13 07 30 00 addi a4, zero, 3 +80010a5c: 6f f0 df ee j -276 +80010a60: 63 66 74 01 bltu s0, s7, 12 +80010a64: 63 96 8b 2e bne s7, s0, 748 +80010a68: 63 e4 f9 2e bltu s3, a5, 744 +80010a6c: 13 95 fb 01 slli a0, s7, 31 +80010a70: 13 d7 19 00 srli a4, s3, 1 +80010a74: 93 96 f9 01 slli a3, s3, 31 +80010a78: 93 db 1b 00 srli s7, s7, 1 +80010a7c: b3 69 e5 00 or s3, a0, a4 +80010a80: 13 15 84 00 slli a0, s0, 8 +80010a84: 13 d8 87 01 srli a6, a5, 24 +80010a88: 33 68 a8 00 or a6, a6, a0 +80010a8c: 13 55 05 01 srli a0, a0, 16 +80010a90: 33 d3 ab 02 divu t1, s7, a0 +80010a94: 13 1e 08 01 slli t3, a6, 16 +80010a98: 13 5e 0e 01 srli t3, t3, 16 +80010a9c: 93 98 87 00 slli a7, a5, 8 +80010aa0: 93 d7 09 01 srli a5, s3, 16 +80010aa4: b3 fb ab 02 remu s7, s7, a0 +80010aa8: 93 0f 03 00 mv t6, t1 +80010aac: 33 07 6e 02 mul a4, t3, t1 +80010ab0: 93 9b 0b 01 slli s7, s7, 16 +80010ab4: b3 e7 77 01 or a5, a5, s7 +80010ab8: 63 fe e7 00 bgeu a5, a4, 28 +80010abc: b3 87 07 01 add a5, a5, a6 +80010ac0: 93 0f f3 ff addi t6, t1, -1 +80010ac4: 63 e8 07 01 bltu a5, a6, 16 +80010ac8: 63 f6 e7 00 bgeu a5, a4, 12 +80010acc: 93 0f e3 ff addi t6, t1, -2 +80010ad0: b3 87 07 01 add a5, a5, a6 +80010ad4: b3 87 e7 40 sub a5, a5, a4 +80010ad8: b3 de a7 02 divu t4, a5, a0 +80010adc: 93 99 09 01 slli s3, s3, 16 +80010ae0: 93 d9 09 01 srli s3, s3, 16 +80010ae4: b3 f7 a7 02 remu a5, a5, a0 +80010ae8: 13 83 0e 00 mv t1, t4 +80010aec: 33 07 de 03 mul a4, t3, t4 +80010af0: 93 97 07 01 slli a5, a5, 16 +80010af4: b3 e7 f9 00 or a5, s3, a5 +80010af8: 63 fe e7 00 bgeu a5, a4, 28 +80010afc: b3 87 07 01 add a5, a5, a6 +80010b00: 13 83 fe ff addi t1, t4, -1 +80010b04: 63 e8 07 01 bltu a5, a6, 16 +80010b08: 63 f6 e7 00 bgeu a5, a4, 12 +80010b0c: 13 83 ee ff addi t1, t4, -2 +80010b10: b3 87 07 01 add a5, a5, a6 +80010b14: 33 87 e7 40 sub a4, a5, a4 +80010b18: 93 9f 0f 01 slli t6, t6, 16 +80010b1c: b7 07 01 00 lui a5, 16 +80010b20: b3 ef 6f 00 or t6, t6, t1 +80010b24: 13 83 f7 ff addi t1, a5, -1 +80010b28: 33 ff 6f 00 and t5, t6, t1 +80010b2c: 93 d2 0f 01 srli t0, t6, 16 +80010b30: 93 de 08 01 srli t4, a7, 16 +80010b34: 33 f3 68 00 and t1, a7, t1 +80010b38: 33 04 6f 02 mul s0, t5, t1 +80010b3c: b3 89 62 02 mul s3, t0, t1 +80010b40: 33 8f ee 03 mul t5, t4, t5 +80010b44: b3 03 3f 01 add t2, t5, s3 +80010b48: 13 5f 04 01 srli t5, s0, 16 +80010b4c: 33 0f 7f 00 add t5, t5, t2 +80010b50: b3 82 d2 03 mul t0, t0, t4 +80010b54: 63 74 3f 01 bgeu t5, s3, 8 +80010b58: b3 82 f2 00 add t0, t0, a5 +80010b5c: b7 03 01 00 lui t2, 16 +80010b60: 93 57 0f 01 srli a5, t5, 16 +80010b64: 93 83 f3 ff addi t2, t2, -1 +80010b68: b3 82 57 00 add t0, a5, t0 +80010b6c: b3 77 7f 00 and a5, t5, t2 +80010b70: 93 97 07 01 slli a5, a5, 16 +80010b74: 33 74 74 00 and s0, s0, t2 +80010b78: b3 87 87 00 add a5, a5, s0 +80010b7c: 63 68 57 00 bltu a4, t0, 16 +80010b80: 13 84 0f 00 mv s0, t6 +80010b84: 63 14 57 04 bne a4, t0, 72 +80010b88: 63 f2 f6 04 bgeu a3, a5, 68 +80010b8c: b3 86 16 01 add a3, a3, a7 +80010b90: 33 bf 16 01 sltu t5, a3, a7 +80010b94: 33 0f 0f 01 add t5, t5, a6 +80010b98: 33 07 e7 01 add a4, a4, t5 +80010b9c: 13 84 ff ff addi s0, t6, -1 +80010ba0: 63 66 e8 00 bltu a6, a4, 12 +80010ba4: 63 14 e8 02 bne a6, a4, 40 +80010ba8: 63 e2 16 03 bltu a3, a7, 36 +80010bac: 63 66 57 00 bltu a4, t0, 12 +80010bb0: 63 9e e2 00 bne t0, a4, 28 +80010bb4: 63 fc f6 00 bgeu a3, a5, 24 +80010bb8: b3 86 16 01 add a3, a3, a7 +80010bbc: 33 bf 16 01 sltu t5, a3, a7 +80010bc0: 33 0f 0f 01 add t5, t5, a6 +80010bc4: 13 84 ef ff addi s0, t6, -2 +80010bc8: 33 07 e7 01 add a4, a4, t5 +80010bcc: 33 8f f6 40 sub t5, a3, a5 +80010bd0: 33 07 57 40 sub a4, a4, t0 +80010bd4: b3 b6 e6 01 sltu a3, a3, t5 +80010bd8: 33 07 d7 40 sub a4, a4, a3 +80010bdc: 93 07 f0 ff addi a5, zero, -1 +80010be0: 63 04 e8 12 beq a6, a4, 296 +80010be4: b3 52 a7 02 divu t0, a4, a0 +80010be8: 93 57 0f 01 srli a5, t5, 16 +80010bec: 33 77 a7 02 remu a4, a4, a0 +80010bf0: 93 86 02 00 mv a3, t0 +80010bf4: b3 0f 5e 02 mul t6, t3, t0 +80010bf8: 13 17 07 01 slli a4, a4, 16 +80010bfc: 33 e7 e7 00 or a4, a5, a4 +80010c00: 63 7e f7 01 bgeu a4, t6, 28 +80010c04: 33 07 07 01 add a4, a4, a6 +80010c08: 93 86 f2 ff addi a3, t0, -1 +80010c0c: 63 68 07 01 bltu a4, a6, 16 +80010c10: 63 76 f7 01 bgeu a4, t6, 12 +80010c14: 93 86 e2 ff addi a3, t0, -2 +80010c18: 33 07 07 01 add a4, a4, a6 +80010c1c: 33 07 f7 41 sub a4, a4, t6 +80010c20: b3 5f a7 02 divu t6, a4, a0 +80010c24: 93 17 0f 01 slli a5, t5, 16 +80010c28: 93 d7 07 01 srli a5, a5, 16 +80010c2c: 33 77 a7 02 remu a4, a4, a0 +80010c30: 33 0e fe 03 mul t3, t3, t6 +80010c34: 13 17 07 01 slli a4, a4, 16 +80010c38: 33 e7 e7 00 or a4, a5, a4 +80010c3c: 93 87 0f 00 mv a5, t6 +80010c40: 63 7e c7 01 bgeu a4, t3, 28 +80010c44: 33 07 07 01 add a4, a4, a6 +80010c48: 93 87 ff ff addi a5, t6, -1 +80010c4c: 63 68 07 01 bltu a4, a6, 16 +80010c50: 63 76 c7 01 bgeu a4, t3, 12 +80010c54: 93 87 ef ff addi a5, t6, -2 +80010c58: 33 07 07 01 add a4, a4, a6 +80010c5c: 93 96 06 01 slli a3, a3, 16 +80010c60: b3 e6 f6 00 or a3, a3, a5 +80010c64: 93 97 06 01 slli a5, a3, 16 +80010c68: 93 d7 07 01 srli a5, a5, 16 +80010c6c: 33 07 c7 41 sub a4, a4, t3 +80010c70: 13 de 06 01 srli t3, a3, 16 +80010c74: 33 0f f3 02 mul t5, t1, a5 +80010c78: 33 03 6e 02 mul t1, t3, t1 +80010c7c: 33 8e ce 03 mul t3, t4, t3 +80010c80: b3 8e fe 02 mul t4, t4, a5 +80010c84: 93 57 0f 01 srli a5, t5, 16 +80010c88: b3 8e 6e 00 add t4, t4, t1 +80010c8c: b3 87 d7 01 add a5, a5, t4 +80010c90: 63 f6 67 00 bgeu a5, t1, 12 +80010c94: 37 05 01 00 lui a0, 16 +80010c98: 33 0e ae 00 add t3, t3, a0 +80010c9c: 13 d3 07 01 srli t1, a5, 16 +80010ca0: 33 03 c3 01 add t1, t1, t3 +80010ca4: 37 0e 01 00 lui t3, 16 +80010ca8: 13 0e fe ff addi t3, t3, -1 +80010cac: 33 f5 c7 01 and a0, a5, t3 +80010cb0: 13 15 05 01 slli a0, a0, 16 +80010cb4: 33 7f cf 01 and t5, t5, t3 +80010cb8: 33 05 e5 01 add a0, a0, t5 +80010cbc: 63 68 67 00 bltu a4, t1, 16 +80010cc0: 63 14 67 3e bne a4, t1, 1000 +80010cc4: 93 87 06 00 mv a5, a3 +80010cc8: 63 00 05 04 beqz a0, 64 +80010ccc: 33 07 e8 00 add a4, a6, a4 +80010cd0: 93 87 f6 ff addi a5, a3, -1 +80010cd4: 63 64 07 03 bltu a4, a6, 40 +80010cd8: 63 66 67 00 bltu a4, t1, 12 +80010cdc: 63 14 67 3c bne a4, t1, 968 +80010ce0: 63 f0 a8 02 bgeu a7, a0, 32 +80010ce4: 93 87 e6 ff addi a5, a3, -2 +80010ce8: 93 96 18 00 slli a3, a7, 1 +80010cec: b3 b8 16 01 sltu a7, a3, a7 +80010cf0: 33 88 08 01 add a6, a7, a6 +80010cf4: 33 07 07 01 add a4, a4, a6 +80010cf8: 93 88 06 00 mv a7, a3 +80010cfc: 63 14 67 00 bne a4, t1, 8 +80010d00: 63 84 a8 00 beq a7, a0, 8 +80010d04: 93 e7 17 00 ori a5, a5, 1 +80010d08: 13 88 f5 3f addi a6, a1, 1023 +80010d0c: 63 5a 00 19 blez a6, 404 +80010d10: 13 f7 77 00 andi a4, a5, 7 +80010d14: 63 0a 07 0a beqz a4, 180 +80010d18: 13 07 20 00 addi a4, zero, 2 +80010d1c: 93 e4 14 00 ori s1, s1, 1 +80010d20: 63 02 e9 0a beq s2, a4, 164 +80010d24: 13 07 30 00 addi a4, zero, 3 +80010d28: 63 08 e9 08 beq s2, a4, 144 +80010d2c: 63 1e 09 08 bnez s2, 156 +80010d30: 13 f7 f7 00 andi a4, a5, 15 +80010d34: 93 06 40 00 addi a3, zero, 4 +80010d38: 63 08 d7 08 beq a4, a3, 144 +80010d3c: 13 87 47 00 addi a4, a5, 4 +80010d40: b3 37 f7 00 sltu a5, a4, a5 +80010d44: 33 04 f4 00 add s0, s0, a5 +80010d48: 93 07 07 00 mv a5, a4 +80010d4c: 6f 00 c0 07 j 124 +80010d50: 93 85 f5 ff addi a1, a1, -1 +80010d54: 93 06 00 00 mv a3, zero +80010d58: 6f f0 9f d2 j -728 +80010d5c: 13 06 0a 00 mv a2, s4 +80010d60: 13 84 0b 00 mv s0, s7 +80010d64: 93 87 09 00 mv a5, s3 +80010d68: 13 87 0c 00 mv a4, s9 +80010d6c: 93 06 30 00 addi a3, zero, 3 +80010d70: 63 00 d7 32 beq a4, a3, 800 +80010d74: 93 06 10 00 addi a3, zero, 1 +80010d78: 63 06 d7 30 beq a4, a3, 780 +80010d7c: 93 06 20 00 addi a3, zero, 2 +80010d80: e3 14 d7 f8 bne a4, a3, -120 +80010d84: 6f 00 00 01 j 16 +80010d88: 13 86 0a 00 mv a2, s5 +80010d8c: 6f f0 1f fe j -32 +80010d90: 93 e4 84 00 ori s1, s1, 8 +80010d94: 13 05 00 00 mv a0, zero +80010d98: 93 07 00 00 mv a5, zero +80010d9c: 13 07 f0 7f addi a4, zero, 2047 +80010da0: 6f 00 c0 05 j 92 +80010da4: 37 04 08 00 lui s0, 128 +80010da8: 93 07 00 00 mv a5, zero +80010dac: 13 06 00 00 mv a2, zero +80010db0: 13 07 30 00 addi a4, zero, 3 +80010db4: 6f f0 9f fb j -72 +80010db8: 63 18 06 00 bnez a2, 16 +80010dbc: 13 87 87 00 addi a4, a5, 8 +80010dc0: 6f f0 1f f8 j -128 +80010dc4: e3 1c 06 fe bnez a2, -8 +80010dc8: 13 17 74 00 slli a4, s0, 7 +80010dcc: 63 5a 07 00 bgez a4, 20 +80010dd0: 37 07 00 ff lui a4, 1044480 +80010dd4: 13 07 f7 ff addi a4, a4, -1 +80010dd8: 33 74 e4 00 and s0, s0, a4 +80010ddc: 13 88 05 40 addi a6, a1, 1024 +80010de0: 13 07 e0 7f addi a4, zero, 2046 +80010de4: 63 4e 07 07 blt a4, a6, 124 +80010de8: 13 d7 37 00 srli a4, a5, 3 +80010dec: 93 17 d4 01 slli a5, s0, 29 +80010df0: b3 e7 e7 00 or a5, a5, a4 +80010df4: 13 55 34 00 srli a0, s0, 3 +80010df8: 13 07 08 00 mv a4, a6 +80010dfc: 13 17 47 01 slli a4, a4, 20 +80010e00: b7 06 f0 7f lui a3, 524032 +80010e04: 13 15 c5 00 slli a0, a0, 12 +80010e08: 33 77 d7 00 and a4, a4, a3 +80010e0c: 13 55 c5 00 srli a0, a0, 12 +80010e10: 33 65 a7 00 or a0, a4, a0 +80010e14: 13 16 f6 01 slli a2, a2, 31 +80010e18: 33 67 c5 00 or a4, a0, a2 +80010e1c: 93 05 07 00 mv a1, a4 +80010e20: 13 85 07 00 mv a0, a5 +80010e24: 63 84 04 00 beqz s1, 8 +80010e28: 73 a0 14 00 csrs fflags, s1 +80010e2c: 83 20 c1 02 lw ra, 44(sp) +80010e30: 03 24 81 02 lw s0, 40(sp) +80010e34: 83 24 41 02 lw s1, 36(sp) +80010e38: 03 29 01 02 lw s2, 32(sp) +80010e3c: 83 29 c1 01 lw s3, 28(sp) +80010e40: 03 2a 81 01 lw s4, 24(sp) +80010e44: 83 2a 41 01 lw s5, 20(sp) +80010e48: 03 2b 01 01 lw s6, 16(sp) +80010e4c: 83 2b c1 00 lw s7, 12(sp) +80010e50: 03 2c 81 00 lw s8, 8(sp) +80010e54: 83 2c 41 00 lw s9, 4(sp) +80010e58: 13 01 01 03 addi sp, sp, 48 +80010e5c: 67 80 00 00 ret +80010e60: 93 07 20 00 addi a5, zero, 2 +80010e64: 63 0a f9 02 beq s2, a5, 52 +80010e68: 93 07 30 00 addi a5, zero, 3 +80010e6c: 63 0a f9 00 beq s2, a5, 20 +80010e70: 63 1a 09 00 bnez s2, 20 +80010e74: 93 07 00 00 mv a5, zero +80010e78: 13 07 f0 7f addi a4, zero, 2047 +80010e7c: 6f 00 00 01 j 16 +80010e80: e3 0a 06 fe beqz a2, -12 +80010e84: 93 07 f0 ff addi a5, zero, -1 +80010e88: 13 07 e0 7f addi a4, zero, 2046 +80010e8c: 93 e4 54 00 ori s1, s1, 5 +80010e90: 13 85 07 00 mv a0, a5 +80010e94: 6f f0 9f f6 j -152 +80010e98: e3 1e 06 fc bnez a2, -36 +80010e9c: 6f f0 9f fe j -24 +80010ea0: 13 07 10 00 addi a4, zero, 1 +80010ea4: 63 16 08 06 bnez a6, 108 +80010ea8: 93 f6 77 00 andi a3, a5, 7 +80010eac: 13 07 04 00 mv a4, s0 +80010eb0: 63 8a 06 04 beqz a3, 84 +80010eb4: 13 07 20 00 addi a4, zero, 2 +80010eb8: 93 e4 14 00 ori s1, s1, 1 +80010ebc: 63 00 e9 04 beq s2, a4, 64 +80010ec0: 13 07 30 00 addi a4, zero, 3 +80010ec4: 63 04 e9 02 beq s2, a4, 40 +80010ec8: 13 07 04 00 mv a4, s0 +80010ecc: 63 1c 09 02 bnez s2, 56 +80010ed0: 93 f6 f7 00 andi a3, a5, 15 +80010ed4: 13 05 40 00 addi a0, zero, 4 +80010ed8: 63 86 a6 02 beq a3, a0, 44 +80010edc: 13 b7 c7 ff sltiu a4, a5, -4 +80010ee0: 13 47 17 00 xori a4, a4, 1 +80010ee4: 33 07 87 00 add a4, a4, s0 +80010ee8: 6f 00 c0 01 j 28 +80010eec: 13 07 04 00 mv a4, s0 +80010ef0: 63 1a 06 00 bnez a2, 20 +80010ef4: 13 b7 87 ff sltiu a4, a5, -8 +80010ef8: 6f f0 9f fe j -24 +80010efc: 13 07 04 00 mv a4, s0 +80010f00: e3 1a 06 fe bnez a2, -12 +80010f04: 13 57 87 01 srli a4, a4, 24 +80010f08: 13 47 17 00 xori a4, a4, 1 +80010f0c: 13 77 17 00 andi a4, a4, 1 +80010f10: 13 05 10 00 addi a0, zero, 1 +80010f14: 33 05 05 41 sub a0, a0, a6 +80010f18: 93 06 80 03 addi a3, zero, 56 +80010f1c: 63 cc a6 0e blt a3, a0, 248 +80010f20: 93 06 f0 01 addi a3, zero, 31 +80010f24: 63 c2 a6 06 blt a3, a0, 100 +80010f28: 93 85 e5 41 addi a1, a1, 1054 +80010f2c: 33 d8 a7 00 srl a6, a5, a0 +80010f30: b3 16 b4 00 sll a3, s0, a1 +80010f34: b3 97 b7 00 sll a5, a5, a1 +80010f38: b3 e6 06 01 or a3, a3, a6 +80010f3c: b3 37 f0 00 snez a5, a5 +80010f40: b3 e7 f6 00 or a5, a3, a5 +80010f44: 33 55 a4 00 srl a0, s0, a0 +80010f48: 93 f6 77 00 andi a3, a5, 7 +80010f4c: 63 80 06 08 beqz a3, 128 +80010f50: 93 06 20 00 addi a3, zero, 2 +80010f54: 93 e4 14 00 ori s1, s1, 1 +80010f58: 63 08 d9 06 beq s2, a3, 112 +80010f5c: 93 06 30 00 addi a3, zero, 3 +80010f60: 63 0e d9 04 beq s2, a3, 92 +80010f64: 63 14 09 06 bnez s2, 104 +80010f68: 93 f6 f7 00 andi a3, a5, 15 +80010f6c: 93 05 40 00 addi a1, zero, 4 +80010f70: 63 8e b6 04 beq a3, a1, 92 +80010f74: 93 86 47 00 addi a3, a5, 4 +80010f78: b3 b7 f6 00 sltu a5, a3, a5 +80010f7c: 33 05 f5 00 add a0, a0, a5 +80010f80: 93 87 06 00 mv a5, a3 +80010f84: 6f 00 80 04 j 72 +80010f88: 93 06 10 fe addi a3, zero, -31 +80010f8c: b3 86 06 41 sub a3, a3, a6 +80010f90: 93 08 00 02 addi a7, zero, 32 +80010f94: b3 56 d4 00 srl a3, s0, a3 +80010f98: 13 08 00 00 mv a6, zero +80010f9c: 63 06 15 01 beq a0, a7, 12 +80010fa0: 93 85 e5 43 addi a1, a1, 1086 +80010fa4: 33 18 b4 00 sll a6, s0, a1 +80010fa8: b3 67 f8 00 or a5, a6, a5 +80010fac: b3 37 f0 00 snez a5, a5 +80010fb0: b3 e7 f6 00 or a5, a3, a5 +80010fb4: 13 05 00 00 mv a0, zero +80010fb8: 6f f0 1f f9 j -112 +80010fbc: 63 18 06 00 bnez a2, 16 +80010fc0: 93 86 87 00 addi a3, a5, 8 +80010fc4: 6f f0 5f fb j -76 +80010fc8: e3 1c 06 fe bnez a2, -8 +80010fcc: 93 16 85 00 slli a3, a0, 8 +80010fd0: 63 de 06 00 bgez a3, 28 +80010fd4: 93 e4 14 00 ori s1, s1, 1 +80010fd8: 13 05 00 00 mv a0, zero +80010fdc: 93 07 00 00 mv a5, zero +80010fe0: 63 16 07 02 bnez a4, 44 +80010fe4: 13 07 10 00 addi a4, zero, 1 +80010fe8: 6f f0 5f e1 j -492 +80010fec: 93 d6 37 00 srli a3, a5, 3 +80010ff0: 93 17 d5 01 slli a5, a0, 29 +80010ff4: b3 e7 d7 00 or a5, a5, a3 +80010ff8: 13 55 35 00 srli a0, a0, 3 +80010ffc: e3 00 07 e0 beqz a4, -512 +80011000: 13 f7 14 00 andi a4, s1, 1 +80011004: e3 0c 07 de beqz a4, -520 +80011008: 13 07 00 00 mv a4, zero +8001100c: 93 e4 24 00 ori s1, s1, 2 +80011010: 6f f0 df de j -532 +80011014: b3 e7 87 00 or a5, a5, s0 +80011018: 63 84 07 02 beqz a5, 40 +8001101c: 93 07 20 00 addi a5, zero, 2 +80011020: 93 e4 14 00 ori s1, s1, 1 +80011024: 63 0e f9 02 beq s2, a5, 60 +80011028: 93 07 30 00 addi a5, zero, 3 +8001102c: 63 02 f9 02 beq s2, a5, 36 +80011030: 93 07 10 00 addi a5, zero, 1 +80011034: 63 14 09 00 bnez s2, 8 +80011038: 93 07 50 00 addi a5, zero, 5 +8001103c: 93 d7 37 00 srli a5, a5, 3 +80011040: 93 e4 24 00 ori s1, s1, 2 +80011044: 13 05 00 00 mv a0, zero +80011048: 13 07 00 00 mv a4, zero +8001104c: 6f f0 1f db j -592 +80011050: 93 07 90 00 addi a5, zero, 9 +80011054: e3 04 06 fe beqz a2, -24 +80011058: 93 07 10 00 addi a5, zero, 1 +8001105c: 6f f0 1f fe j -32 +80011060: 93 07 90 00 addi a5, zero, 9 +80011064: e3 1c 06 fc bnez a2, -40 +80011068: 6f f0 1f ff j -16 +8001106c: 37 05 08 00 lui a0, 128 +80011070: 93 07 00 00 mv a5, zero +80011074: 13 07 f0 7f addi a4, zero, 2047 +80011078: 13 06 00 00 mv a2, zero +8001107c: 93 04 00 01 addi s1, zero, 16 +80011080: 6f f0 df d7 j -644 +80011084: 13 05 00 00 mv a0, zero +80011088: 93 07 00 00 mv a5, zero +8001108c: 6f f0 df fb j -68 +80011090: 37 05 08 00 lui a0, 128 +80011094: 93 07 00 00 mv a5, zero +80011098: 13 07 f0 7f addi a4, zero, 2047 +8001109c: 13 06 00 00 mv a2, zero +800110a0: 6f f0 df d5 j -676 +800110a4: 93 86 07 00 mv a3, a5 +800110a8: 93 87 06 00 mv a5, a3 +800110ac: 6f f0 9f c5 j -936 + +800110b0 __muldf3: +800110b0: 13 01 01 fd addi sp, sp, -48 +800110b4: 23 24 81 02 sw s0, 40(sp) +800110b8: 23 28 61 01 sw s6, 16(sp) +800110bc: 23 22 91 01 sw s9, 4(sp) +800110c0: 23 26 11 02 sw ra, 44(sp) +800110c4: 23 22 91 02 sw s1, 36(sp) +800110c8: 23 20 21 03 sw s2, 32(sp) +800110cc: 23 2e 31 01 sw s3, 28(sp) +800110d0: 23 2c 41 01 sw s4, 24(sp) +800110d4: 23 2a 51 01 sw s5, 20(sp) +800110d8: 23 26 71 01 sw s7, 12(sp) +800110dc: 23 24 81 01 sw s8, 8(sp) +800110e0: 13 04 05 00 mv s0, a0 +800110e4: 93 0c 06 00 mv s9, a2 +800110e8: 13 8b 06 00 mv s6, a3 +800110ec: 73 29 20 00 frrm s2 +800110f0: 93 d7 45 01 srli a5, a1, 20 +800110f4: 93 99 c5 00 slli s3, a1, 12 +800110f8: 13 97 57 01 slli a4, a5, 21 +800110fc: 93 d9 c9 00 srli s3, s3, 12 +80011100: 93 da f5 01 srli s5, a1, 31 +80011104: 63 0c 07 02 beqz a4, 56 +80011108: 93 fb f7 7f andi s7, a5, 2047 +8001110c: 93 07 f0 7f addi a5, zero, 2047 +80011110: 63 88 fb 08 beq s7, a5, 144 +80011114: 93 57 d5 01 srli a5, a0, 29 +80011118: 93 99 39 00 slli s3, s3, 3 +8001111c: b3 e9 37 01 or s3, a5, s3 +80011120: b7 07 80 00 lui a5, 2048 +80011124: b3 e9 f9 00 or s3, s3, a5 +80011128: 13 1a 35 00 slli s4, a0, 3 +8001112c: 93 8b 1b c0 addi s7, s7, -1023 +80011130: 13 0c 00 00 mv s8, zero +80011134: 93 04 00 00 mv s1, zero +80011138: 6f 00 80 08 j 136 +8001113c: b3 e7 a9 00 or a5, s3, a0 +80011140: 63 80 07 10 beqz a5, 256 +80011144: 63 80 09 04 beqz s3, 64 +80011148: 13 85 09 00 mv a0, s3 +8001114c: ef 40 c0 37 jal 17276 +80011150: 13 07 55 ff addi a4, a0, -11 +80011154: 93 07 c0 01 addi a5, zero, 28 +80011158: 63 cc e7 02 blt a5, a4, 56 +8001115c: 93 07 d0 01 addi a5, zero, 29 +80011160: 13 0a 85 ff addi s4, a0, -8 +80011164: b3 87 e7 40 sub a5, a5, a4 +80011168: b3 99 49 01 sll s3, s3, s4 +8001116c: b3 57 f4 00 srl a5, s0, a5 +80011170: b3 e9 37 01 or s3, a5, s3 +80011174: 33 1a 44 01 sll s4, s0, s4 +80011178: 93 0b d0 c0 addi s7, zero, -1011 +8001117c: b3 8b ab 40 sub s7, s7, a0 +80011180: 6f f0 1f fb j -80 +80011184: ef 40 40 34 jal 17220 +80011188: 13 05 05 02 addi a0, a0, 32 +8001118c: 6f f0 5f fc j -60 +80011190: 93 09 85 fd addi s3, a0, -40 +80011194: b3 19 34 01 sll s3, s0, s3 +80011198: 13 0a 00 00 mv s4, zero +8001119c: 6f f0 df fd j -36 +800111a0: 33 e4 a9 00 or s0, s3, a0 +800111a4: 63 08 04 0a beqz s0, 176 +800111a8: 93 97 c9 00 slli a5, s3, 12 +800111ac: 13 0a 05 00 mv s4, a0 +800111b0: 93 0b f0 7f addi s7, zero, 2047 +800111b4: 13 0c 30 00 addi s8, zero, 3 +800111b8: 93 04 00 01 addi s1, zero, 16 +800111bc: e3 cc 07 f6 bltz a5, -136 +800111c0: 13 57 4b 01 srli a4, s6, 20 +800111c4: 13 14 cb 00 slli s0, s6, 12 +800111c8: 93 16 57 01 slli a3, a4, 21 +800111cc: 93 87 0c 00 mv a5, s9 +800111d0: 13 54 c4 00 srli s0, s0, 12 +800111d4: 13 75 f7 7f andi a0, a4, 2047 +800111d8: 13 5b fb 01 srli s6, s6, 31 +800111dc: 63 86 06 08 beqz a3, 140 +800111e0: 13 07 f0 7f addi a4, zero, 2047 +800111e4: 63 06 e5 0e beq a0, a4, 236 +800111e8: 93 d7 dc 01 srli a5, s9, 29 +800111ec: 13 14 34 00 slli s0, s0, 3 +800111f0: 33 e4 87 00 or s0, a5, s0 +800111f4: b7 07 80 00 lui a5, 2048 +800111f8: 33 64 f4 00 or s0, s0, a5 +800111fc: 13 05 15 c0 addi a0, a0, -1023 +80011200: 93 97 3c 00 slli a5, s9, 3 +80011204: 13 07 00 00 mv a4, zero +80011208: 93 16 2c 00 slli a3, s8, 2 +8001120c: b3 e6 e6 00 or a3, a3, a4 +80011210: b3 8b ab 00 add s7, s7, a0 +80011214: 93 86 f6 ff addi a3, a3, -1 +80011218: 13 06 e0 00 addi a2, zero, 14 +8001121c: b3 c5 6a 01 xor a1, s5, s6 +80011220: 13 85 1b 00 addi a0, s7, 1 +80011224: 63 6a d6 16 bltu a2, a3, 372 +80011228: 37 66 01 80 lui a2, 524310 +8001122c: 93 96 26 00 slli a3, a3, 2 +80011230: 13 06 06 02 addi a2, a2, 32 +80011234: b3 86 c6 00 add a3, a3, a2 +80011238: 83 a6 06 00 lw a3, 0(a3) +8001123c: 67 80 06 00 jr a3 +80011240: 93 09 00 00 mv s3, zero +80011244: 13 0a 00 00 mv s4, zero +80011248: 93 0b 00 00 mv s7, zero +8001124c: 13 0c 10 00 addi s8, zero, 1 +80011250: 6f f0 5f ee j -284 +80011254: 93 09 00 00 mv s3, zero +80011258: 13 0a 00 00 mv s4, zero +8001125c: 93 0b f0 7f addi s7, zero, 2047 +80011260: 13 0c 20 00 addi s8, zero, 2 +80011264: 6f f0 1f ed j -304 +80011268: b3 67 94 01 or a5, s0, s9 +8001126c: 63 82 07 08 beqz a5, 132 +80011270: 63 00 04 04 beqz s0, 64 +80011274: 13 05 04 00 mv a0, s0 +80011278: ef 40 00 25 jal 16976 +8001127c: 93 06 55 ff addi a3, a0, -11 +80011280: 93 07 c0 01 addi a5, zero, 28 +80011284: 63 ce d7 02 blt a5, a3, 60 +80011288: 13 07 d0 01 addi a4, zero, 29 +8001128c: 93 07 85 ff addi a5, a0, -8 +80011290: 33 07 d7 40 sub a4, a4, a3 +80011294: 33 14 f4 00 sll s0, s0, a5 +80011298: 33 d7 ec 00 srl a4, s9, a4 +8001129c: 33 64 87 00 or s0, a4, s0 +800112a0: b3 97 fc 00 sll a5, s9, a5 +800112a4: 13 07 d0 c0 addi a4, zero, -1011 +800112a8: 33 05 a7 40 sub a0, a4, a0 +800112ac: 6f f0 9f f5 j -168 +800112b0: 13 85 0c 00 mv a0, s9 +800112b4: ef 40 40 21 jal 16916 +800112b8: 13 05 05 02 addi a0, a0, 32 +800112bc: 6f f0 1f fc j -64 +800112c0: 13 04 85 fd addi s0, a0, -40 +800112c4: 33 94 8c 00 sll s0, s9, s0 +800112c8: 93 07 00 00 mv a5, zero +800112cc: 6f f0 9f fd j -40 +800112d0: 33 66 94 01 or a2, s0, s9 +800112d4: 63 08 06 02 beqz a2, 48 +800112d8: 13 17 c4 00 slli a4, s0, 12 +800112dc: 13 05 f0 7f addi a0, zero, 2047 +800112e0: 63 4c 07 02 bltz a4, 56 +800112e4: 13 07 30 00 addi a4, zero, 3 +800112e8: 93 04 00 01 addi s1, zero, 16 +800112ec: 6f f0 df f1 j -228 +800112f0: 13 04 00 00 mv s0, zero +800112f4: 93 07 00 00 mv a5, zero +800112f8: 13 05 00 00 mv a0, zero +800112fc: 13 07 10 00 addi a4, zero, 1 +80011300: 6f f0 9f f0 j -248 +80011304: 13 04 00 00 mv s0, zero +80011308: 93 07 00 00 mv a5, zero +8001130c: 13 05 f0 7f addi a0, zero, 2047 +80011310: 13 07 20 00 addi a4, zero, 2 +80011314: 6f f0 5f ef j -268 +80011318: 13 07 30 00 addi a4, zero, 3 +8001131c: 6f f0 df ee j -276 +80011320: 37 04 08 00 lui s0, 128 +80011324: 93 07 00 00 mv a5, zero +80011328: 13 07 f0 7f addi a4, zero, 2047 +8001132c: 93 05 00 00 mv a1, zero +80011330: 93 04 00 01 addi s1, zero, 16 +80011334: 13 17 47 01 slli a4, a4, 20 +80011338: b7 06 f0 7f lui a3, 524032 +8001133c: 13 14 c4 00 slli s0, s0, 12 +80011340: 33 77 d7 00 and a4, a4, a3 +80011344: 13 54 c4 00 srli s0, s0, 12 +80011348: 93 95 f5 01 slli a1, a1, 31 +8001134c: 33 64 87 00 or s0, a4, s0 +80011350: 33 67 b4 00 or a4, s0, a1 +80011354: 13 85 07 00 mv a0, a5 +80011358: 93 05 07 00 mv a1, a4 +8001135c: 63 84 04 00 beqz s1, 8 +80011360: 73 a0 14 00 csrs fflags, s1 +80011364: 83 20 c1 02 lw ra, 44(sp) +80011368: 03 24 81 02 lw s0, 40(sp) +8001136c: 83 24 41 02 lw s1, 36(sp) +80011370: 03 29 01 02 lw s2, 32(sp) +80011374: 83 29 c1 01 lw s3, 28(sp) +80011378: 03 2a 81 01 lw s4, 24(sp) +8001137c: 83 2a 41 01 lw s5, 20(sp) +80011380: 03 2b 01 01 lw s6, 16(sp) +80011384: 83 2b c1 00 lw s7, 12(sp) +80011388: 03 2c 81 00 lw s8, 8(sp) +8001138c: 83 2c 41 00 lw s9, 4(sp) +80011390: 13 01 01 03 addi sp, sp, 48 +80011394: 67 80 00 00 ret +80011398: 37 06 01 00 lui a2, 16 +8001139c: 13 07 f6 ff addi a4, a2, -1 +800113a0: 93 56 0a 01 srli a3, s4, 16 +800113a4: 13 de 07 01 srli t3, a5, 16 +800113a8: 33 7a ea 00 and s4, s4, a4 +800113ac: b3 f7 e7 00 and a5, a5, a4 +800113b0: 33 03 4e 03 mul t1, t3, s4 +800113b4: b3 8e 47 03 mul t4, a5, s4 +800113b8: 33 8f f6 02 mul t5, a3, a5 +800113bc: 33 08 e3 01 add a6, t1, t5 +800113c0: 13 d3 0e 01 srli t1, t4, 16 +800113c4: 33 03 03 01 add t1, t1, a6 +800113c8: b3 88 c6 03 mul a7, a3, t3 +800113cc: 63 74 e3 01 bgeu t1, t5, 8 +800113d0: b3 88 c8 00 add a7, a7, a2 +800113d4: 33 78 e3 00 and a6, t1, a4 +800113d8: b3 fe ee 00 and t4, t4, a4 +800113dc: 13 56 03 01 srli a2, t1, 16 +800113e0: 13 18 08 01 slli a6, a6, 16 +800113e4: 13 53 04 01 srli t1, s0, 16 +800113e8: 33 74 e4 00 and s0, s0, a4 +800113ec: 33 08 d8 01 add a6, a6, t4 +800113f0: 33 0f 8a 02 mul t5, s4, s0 +800113f4: b3 8e 86 02 mul t4, a3, s0 +800113f8: 33 0a 43 03 mul s4, t1, s4 +800113fc: 33 07 da 01 add a4, s4, t4 +80011400: 13 5a 0f 01 srli s4, t5, 16 +80011404: 33 0a ea 00 add s4, s4, a4 +80011408: b3 86 66 02 mul a3, a3, t1 +8001140c: 63 76 da 01 bgeu s4, t4, 12 +80011410: 37 07 01 00 lui a4, 16 +80011414: b3 86 e6 00 add a3, a3, a4 +80011418: 93 5e 0a 01 srli t4, s4, 16 +8001141c: b3 8e de 00 add t4, t4, a3 +80011420: b7 06 01 00 lui a3, 16 +80011424: 93 82 f6 ff addi t0, a3, -1 +80011428: 33 7a 5a 00 and s4, s4, t0 +8001142c: 33 7f 5f 00 and t5, t5, t0 +80011430: 13 d7 09 01 srli a4, s3, 16 +80011434: 13 1a 0a 01 slli s4, s4, 16 +80011438: b3 f9 59 00 and s3, s3, t0 +8001143c: 33 0a ea 01 add s4, s4, t5 +80011440: b3 02 ee 02 mul t0, t3, a4 +80011444: b3 0f 46 01 add t6, a2, s4 +80011448: 33 8f 37 03 mul t5, a5, s3 +8001144c: 33 0e 3e 03 mul t3, t3, s3 +80011450: 13 56 0f 01 srli a2, t5, 16 +80011454: b3 07 f7 02 mul a5, a4, a5 +80011458: 33 0e fe 00 add t3, t3, a5 +8001145c: 33 06 c6 01 add a2, a2, t3 +80011460: 63 74 f6 00 bgeu a2, a5, 8 +80011464: b3 82 d2 00 add t0, t0, a3 +80011468: b7 06 01 00 lui a3, 16 +8001146c: 93 87 f6 ff addi a5, a3, -1 +80011470: 13 5e 06 01 srli t3, a2, 16 +80011474: 33 76 f6 00 and a2, a2, a5 +80011478: 33 7f ff 00 and t5, t5, a5 +8001147c: 13 16 06 01 slli a2, a2, 16 +80011480: b3 87 89 02 mul a5, s3, s0 +80011484: 33 06 e6 01 add a2, a2, t5 +80011488: 33 0e 5e 00 add t3, t3, t0 +8001148c: 33 04 87 02 mul s0, a4, s0 +80011490: 33 0f e3 02 mul t5, t1, a4 +80011494: 13 d7 07 01 srli a4, a5, 16 +80011498: 33 03 33 03 mul t1, t1, s3 +8001149c: 33 03 83 00 add t1, t1, s0 +800114a0: 33 03 67 00 add t1, a4, t1 +800114a4: 63 74 83 00 bgeu t1, s0, 8 +800114a8: 33 0f df 00 add t5, t5, a3 +800114ac: 37 07 01 00 lui a4, 16 +800114b0: 13 07 f7 ff addi a4, a4, -1 +800114b4: b3 76 e3 00 and a3, t1, a4 +800114b8: b3 f7 e7 00 and a5, a5, a4 +800114bc: 93 96 06 01 slli a3, a3, 16 +800114c0: b3 88 f8 01 add a7, a7, t6 +800114c4: b3 86 f6 00 add a3, a3, a5 +800114c8: 33 ba 48 01 sltu s4, a7, s4 +800114cc: b3 86 d6 01 add a3, a3, t4 +800114d0: 33 87 46 01 add a4, a3, s4 +800114d4: b3 88 c8 00 add a7, a7, a2 +800114d8: 33 b6 c8 00 sltu a2, a7, a2 +800114dc: b3 0f c7 01 add t6, a4, t3 +800114e0: b3 82 cf 00 add t0, t6, a2 +800114e4: b3 b6 d6 01 sltu a3, a3, t4 +800114e8: 33 37 47 01 sltu a4, a4, s4 +800114ec: 33 e7 e6 00 or a4, a3, a4 +800114f0: 33 b6 c2 00 sltu a2, t0, a2 +800114f4: 13 53 03 01 srli t1, t1, 16 +800114f8: 33 be cf 01 sltu t3, t6, t3 +800114fc: 33 07 67 00 add a4, a4, t1 +80011500: 33 66 ce 00 or a2, t3, a2 +80011504: 93 97 98 00 slli a5, a7, 9 +80011508: 33 07 c7 00 add a4, a4, a2 +8001150c: 33 07 e7 01 add a4, a4, t5 +80011510: b3 e7 07 01 or a5, a5, a6 +80011514: 13 17 97 00 slli a4, a4, 9 +80011518: b3 37 f0 00 snez a5, a5 +8001151c: 93 d8 78 01 srli a7, a7, 23 +80011520: 13 d4 72 01 srli s0, t0, 23 +80011524: b3 e7 17 01 or a5, a5, a7 +80011528: 93 92 92 00 slli t0, t0, 9 +8001152c: 93 16 77 00 slli a3, a4, 7 +80011530: 33 64 87 00 or s0, a4, s0 +80011534: b3 e7 57 00 or a5, a5, t0 +80011538: 63 d0 06 0a bgez a3, 160 +8001153c: 13 d7 17 00 srli a4, a5, 1 +80011540: 93 f7 17 00 andi a5, a5, 1 +80011544: b3 67 f7 00 or a5, a4, a5 +80011548: 13 17 f4 01 slli a4, s0, 31 +8001154c: b3 e7 e7 00 or a5, a5, a4 +80011550: 13 54 14 00 srli s0, s0, 1 +80011554: 13 08 f5 3f addi a6, a0, 1023 +80011558: 63 58 00 11 blez a6, 272 +8001155c: 13 f7 77 00 andi a4, a5, 7 +80011560: 63 08 07 08 beqz a4, 144 +80011564: 13 07 20 00 addi a4, zero, 2 +80011568: 93 e4 14 00 ori s1, s1, 1 +8001156c: 63 00 e9 08 beq s2, a4, 128 +80011570: 13 07 30 00 addi a4, zero, 3 +80011574: 63 06 e9 06 beq s2, a4, 108 +80011578: 63 1c 09 06 bnez s2, 120 +8001157c: 13 f7 f7 00 andi a4, a5, 15 +80011580: 93 06 40 00 addi a3, zero, 4 +80011584: 63 06 d7 06 beq a4, a3, 108 +80011588: 13 87 47 00 addi a4, a5, 4 +8001158c: b3 37 f7 00 sltu a5, a4, a5 +80011590: 33 04 f4 00 add s0, s0, a5 +80011594: 93 07 07 00 mv a5, a4 +80011598: 6f 00 80 05 j 88 +8001159c: 93 85 0a 00 mv a1, s5 +800115a0: 13 84 09 00 mv s0, s3 +800115a4: 93 07 0a 00 mv a5, s4 +800115a8: 13 07 0c 00 mv a4, s8 +800115ac: 93 06 20 00 addi a3, zero, 2 +800115b0: 63 02 d7 28 beq a4, a3, 644 +800115b4: 93 06 30 00 addi a3, zero, 3 +800115b8: 63 06 d7 28 beq a4, a3, 652 +800115bc: 93 06 10 00 addi a3, zero, 1 +800115c0: e3 1a d7 f8 bne a4, a3, -108 +800115c4: 13 04 00 00 mv s0, zero +800115c8: 93 07 00 00 mv a5, zero +800115cc: 6f 00 40 24 j 580 +800115d0: 93 05 0b 00 mv a1, s6 +800115d4: 6f f0 9f fd j -40 +800115d8: 13 85 0b 00 mv a0, s7 +800115dc: 6f f0 9f f7 j -136 +800115e0: 63 98 05 00 bnez a1, 16 +800115e4: 13 87 87 00 addi a4, a5, 8 +800115e8: 6f f0 5f fa j -92 +800115ec: e3 9c 05 fe bnez a1, -8 +800115f0: 13 17 74 00 slli a4, s0, 7 +800115f4: 63 5a 07 00 bgez a4, 20 +800115f8: 37 07 00 ff lui a4, 1044480 +800115fc: 13 07 f7 ff addi a4, a4, -1 +80011600: 33 74 e4 00 and s0, s0, a4 +80011604: 13 08 05 40 addi a6, a0, 1024 +80011608: 13 07 e0 7f addi a4, zero, 2046 +8001160c: 63 4e 07 01 blt a4, a6, 28 +80011610: 13 d7 37 00 srli a4, a5, 3 +80011614: 93 17 d4 01 slli a5, s0, 29 +80011618: b3 e7 e7 00 or a5, a5, a4 +8001161c: 13 54 34 00 srli s0, s0, 3 +80011620: 13 07 08 00 mv a4, a6 +80011624: 6f f0 1f d1 j -752 +80011628: 93 07 20 00 addi a5, zero, 2 +8001162c: 63 0a f9 02 beq s2, a5, 52 +80011630: 93 07 30 00 addi a5, zero, 3 +80011634: 63 0a f9 00 beq s2, a5, 20 +80011638: 63 1a 09 00 bnez s2, 20 +8001163c: 93 07 00 00 mv a5, zero +80011640: 13 07 f0 7f addi a4, zero, 2047 +80011644: 6f 00 00 01 j 16 +80011648: e3 8a 05 fe beqz a1, -12 +8001164c: 93 07 f0 ff addi a5, zero, -1 +80011650: 13 07 e0 7f addi a4, zero, 2046 +80011654: 93 e4 54 00 ori s1, s1, 5 +80011658: 13 84 07 00 mv s0, a5 +8001165c: 6f f0 9f cd j -808 +80011660: e3 9e 05 fc bnez a1, -36 +80011664: 6f f0 9f fe j -24 +80011668: 13 07 10 00 addi a4, zero, 1 +8001166c: 63 16 08 06 bnez a6, 108 +80011670: 93 f6 77 00 andi a3, a5, 7 +80011674: 13 07 04 00 mv a4, s0 +80011678: 63 8a 06 04 beqz a3, 84 +8001167c: 13 07 20 00 addi a4, zero, 2 +80011680: 93 e4 14 00 ori s1, s1, 1 +80011684: 63 00 e9 04 beq s2, a4, 64 +80011688: 13 07 30 00 addi a4, zero, 3 +8001168c: 63 04 e9 02 beq s2, a4, 40 +80011690: 13 07 04 00 mv a4, s0 +80011694: 63 1c 09 02 bnez s2, 56 +80011698: 93 f6 f7 00 andi a3, a5, 15 +8001169c: 13 06 40 00 addi a2, zero, 4 +800116a0: 63 86 c6 02 beq a3, a2, 44 +800116a4: 13 b7 c7 ff sltiu a4, a5, -4 +800116a8: 13 47 17 00 xori a4, a4, 1 +800116ac: 33 07 87 00 add a4, a4, s0 +800116b0: 6f 00 c0 01 j 28 +800116b4: 13 07 04 00 mv a4, s0 +800116b8: 63 9a 05 00 bnez a1, 20 +800116bc: 13 b7 87 ff sltiu a4, a5, -8 +800116c0: 6f f0 9f fe j -24 +800116c4: 13 07 04 00 mv a4, s0 +800116c8: e3 9a 05 fe bnez a1, -12 +800116cc: 13 57 87 01 srli a4, a4, 24 +800116d0: 13 47 17 00 xori a4, a4, 1 +800116d4: 13 77 17 00 andi a4, a4, 1 +800116d8: 93 06 10 00 addi a3, zero, 1 +800116dc: b3 86 06 41 sub a3, a3, a6 +800116e0: 13 06 80 03 addi a2, zero, 56 +800116e4: 63 4c d6 0e blt a2, a3, 248 +800116e8: 13 06 f0 01 addi a2, zero, 31 +800116ec: 63 42 d6 06 blt a2, a3, 100 +800116f0: 13 05 e5 41 addi a0, a0, 1054 +800116f4: 33 16 a4 00 sll a2, s0, a0 +800116f8: 33 d8 d7 00 srl a6, a5, a3 +800116fc: b3 97 a7 00 sll a5, a5, a0 +80011700: 33 66 06 01 or a2, a2, a6 +80011704: b3 37 f0 00 snez a5, a5 +80011708: b3 67 f6 00 or a5, a2, a5 +8001170c: 33 54 d4 00 srl s0, s0, a3 +80011710: 93 f6 77 00 andi a3, a5, 7 +80011714: 63 80 06 08 beqz a3, 128 +80011718: 93 06 20 00 addi a3, zero, 2 +8001171c: 93 e4 14 00 ori s1, s1, 1 +80011720: 63 08 d9 06 beq s2, a3, 112 +80011724: 93 06 30 00 addi a3, zero, 3 +80011728: 63 0e d9 04 beq s2, a3, 92 +8001172c: 63 14 09 06 bnez s2, 104 +80011730: 93 f6 f7 00 andi a3, a5, 15 +80011734: 13 06 40 00 addi a2, zero, 4 +80011738: 63 8e c6 04 beq a3, a2, 92 +8001173c: 93 86 47 00 addi a3, a5, 4 +80011740: b3 b7 f6 00 sltu a5, a3, a5 +80011744: 33 04 f4 00 add s0, s0, a5 +80011748: 93 87 06 00 mv a5, a3 +8001174c: 6f 00 80 04 j 72 +80011750: 13 06 10 fe addi a2, zero, -31 +80011754: 33 06 06 41 sub a2, a2, a6 +80011758: 93 08 00 02 addi a7, zero, 32 +8001175c: 33 56 c4 00 srl a2, s0, a2 +80011760: 13 08 00 00 mv a6, zero +80011764: 63 86 16 01 beq a3, a7, 12 +80011768: 13 05 e5 43 addi a0, a0, 1086 +8001176c: 33 18 a4 00 sll a6, s0, a0 +80011770: b3 67 f8 00 or a5, a6, a5 +80011774: b3 37 f0 00 snez a5, a5 +80011778: b3 67 f6 00 or a5, a2, a5 +8001177c: 13 04 00 00 mv s0, zero +80011780: 6f f0 1f f9 j -112 +80011784: 63 98 05 00 bnez a1, 16 +80011788: 93 86 87 00 addi a3, a5, 8 +8001178c: 6f f0 5f fb j -76 +80011790: e3 9c 05 fe bnez a1, -8 +80011794: 93 16 84 00 slli a3, s0, 8 +80011798: 63 de 06 00 bgez a3, 28 +8001179c: 93 e4 14 00 ori s1, s1, 1 +800117a0: 13 04 00 00 mv s0, zero +800117a4: 93 07 00 00 mv a5, zero +800117a8: 63 16 07 02 bnez a4, 44 +800117ac: 13 07 10 00 addi a4, zero, 1 +800117b0: 6f f0 5f b8 j -1148 +800117b4: 93 d6 37 00 srli a3, a5, 3 +800117b8: 93 17 d4 01 slli a5, s0, 29 +800117bc: b3 e7 d7 00 or a5, a5, a3 +800117c0: 13 54 34 00 srli s0, s0, 3 +800117c4: e3 08 07 b6 beqz a4, -1168 +800117c8: 13 f7 14 00 andi a4, s1, 1 +800117cc: e3 04 07 b6 beqz a4, -1176 +800117d0: 13 07 00 00 mv a4, zero +800117d4: 93 e4 24 00 ori s1, s1, 2 +800117d8: 6f f0 df b5 j -1188 +800117dc: b3 e7 87 00 or a5, a5, s0 +800117e0: 63 84 07 02 beqz a5, 40 +800117e4: 93 07 20 00 addi a5, zero, 2 +800117e8: 93 e4 14 00 ori s1, s1, 1 +800117ec: 63 0e f9 02 beq s2, a5, 60 +800117f0: 93 07 30 00 addi a5, zero, 3 +800117f4: 63 02 f9 02 beq s2, a5, 36 +800117f8: 93 07 10 00 addi a5, zero, 1 +800117fc: 63 14 09 00 bnez s2, 8 +80011800: 93 07 50 00 addi a5, zero, 5 +80011804: 93 d7 37 00 srli a5, a5, 3 +80011808: 93 e4 24 00 ori s1, s1, 2 +8001180c: 13 04 00 00 mv s0, zero +80011810: 13 07 00 00 mv a4, zero +80011814: 6f f0 1f b2 j -1248 +80011818: 93 07 90 00 addi a5, zero, 9 +8001181c: e3 84 05 fe beqz a1, -24 +80011820: 93 07 10 00 addi a5, zero, 1 +80011824: 6f f0 1f fe j -32 +80011828: 93 07 90 00 addi a5, zero, 9 +8001182c: e3 9c 05 fc bnez a1, -40 +80011830: 6f f0 1f ff j -16 +80011834: 13 04 00 00 mv s0, zero +80011838: 93 07 00 00 mv a5, zero +8001183c: 13 07 f0 7f addi a4, zero, 2047 +80011840: 6f f0 5f af j -1292 +80011844: 37 04 08 00 lui s0, 128 +80011848: 93 07 00 00 mv a5, zero +8001184c: 13 07 f0 7f addi a4, zero, 2047 +80011850: 93 05 00 00 mv a1, zero +80011854: 6f f0 1f ae j -1312 + +80011858 __netf2: +80011858: 83 27 05 00 lw a5, 0(a0) +8001185c: 83 2e 45 00 lw t4, 4(a0) +80011860: 03 2f 85 00 lw t5, 8(a0) +80011864: 83 26 c5 00 lw a3, 12(a0) +80011868: 03 a7 05 00 lw a4, 0(a1) +8001186c: 83 a2 45 00 lw t0, 4(a1) +80011870: 83 af 85 00 lw t6, 8(a1) +80011874: 03 a3 c5 00 lw t1, 12(a1) +80011878: 13 01 01 ff addi sp, sp, -16 +8001187c: 73 26 20 00 frrm a2 +80011880: 37 88 00 00 lui a6, 8 +80011884: 13 d6 06 01 srli a2, a3, 16 +80011888: 13 08 f8 ff addi a6, a6, -1 +8001188c: 13 9e 06 01 slli t3, a3, 16 +80011890: 93 15 03 01 slli a1, t1, 16 +80011894: 93 d8 f6 01 srli a7, a3, 31 +80011898: 33 76 06 01 and a2, a2, a6 +8001189c: 93 56 03 01 srli a3, t1, 16 +800118a0: 13 5e 0e 01 srli t3, t3, 16 +800118a4: 93 d5 05 01 srli a1, a1, 16 +800118a8: b3 f6 06 01 and a3, a3, a6 +800118ac: 13 53 f3 01 srli t1, t1, 31 +800118b0: 63 1e 06 01 bne a2, a6, 28 +800118b4: 33 e8 d7 01 or a6, a5, t4 +800118b8: 33 68 e8 01 or a6, a6, t5 +800118bc: 33 68 c8 01 or a6, a6, t3 +800118c0: 63 12 08 08 bnez a6, 132 +800118c4: 63 9c c6 0a bne a3, a2, 184 +800118c8: 6f 00 80 00 j 8 +800118cc: 63 9a 06 01 bne a3, a6, 20 +800118d0: 33 68 57 00 or a6, a4, t0 +800118d4: 33 68 f8 01 or a6, a6, t6 +800118d8: 33 68 b8 00 or a6, a6, a1 +800118dc: 63 16 08 04 bnez a6, 76 +800118e0: 13 05 10 00 addi a0, zero, 1 +800118e4: 63 96 c6 02 bne a3, a2, 44 +800118e8: 63 94 e7 02 bne a5, a4, 40 +800118ec: 63 92 5e 02 bne t4, t0, 36 +800118f0: 63 10 ff 03 bne t5, t6, 32 +800118f4: 63 1e be 00 bne t3, a1, 28 +800118f8: 63 84 68 02 beq a7, t1, 40 +800118fc: 63 9a 06 00 bnez a3, 20 +80011900: 33 e5 d7 01 or a0, a5, t4 +80011904: 33 65 e5 01 or a0, a0, t5 +80011908: 33 65 c5 01 or a0, a0, t3 +8001190c: 33 35 a0 00 snez a0, a0 +80011910: 13 01 01 01 addi sp, sp, 16 +80011914: 67 80 00 00 ret +80011918: 73 60 18 00 csrsi fflags, 16 +8001191c: 6f 00 00 06 j 96 +80011920: 13 05 00 00 mv a0, zero +80011924: 6f f0 df fe j -20 +80011928: 37 85 00 00 lui a0, 8 +8001192c: 13 05 f5 ff addi a0, a0, -1 +80011930: 63 10 a6 04 bne a2, a0, 64 +80011934: b3 e7 d7 01 or a5, a5, t4 +80011938: b3 e7 e7 01 or a5, a5, t5 +8001193c: b3 e7 c7 01 or a5, a5, t3 +80011940: 63 88 07 02 beqz a5, 48 +80011944: 13 15 0e 01 slli a0, t3, 16 +80011948: 13 55 05 41 srai a0, a0, 16 +8001194c: e3 56 05 fc bgez a0, -52 +80011950: b7 87 00 00 lui a5, 8 +80011954: 93 87 f7 ff addi a5, a5, -1 +80011958: 13 05 10 00 addi a0, zero, 1 +8001195c: e3 9a f6 fa bne a3, a5, -76 +80011960: 33 67 57 00 or a4, a4, t0 +80011964: 33 67 f7 01 or a4, a4, t6 +80011968: 33 67 b7 00 or a4, a4, a1 +8001196c: e3 02 07 fa beqz a4, -92 +80011970: 93 95 05 01 slli a1, a1, 16 +80011974: 93 d5 05 41 srai a1, a1, 16 +80011978: e3 d0 05 fa bgez a1, -96 +8001197c: 13 05 10 00 addi a0, zero, 1 +80011980: 6f f0 1f f9 j -112 + +80011984 __gttf2: +80011984: 83 2f 05 00 lw t6, 0(a0) +80011988: 03 28 45 00 lw a6, 4(a0) +8001198c: 03 2e 85 00 lw t3, 8(a0) +80011990: 83 a2 05 00 lw t0, 0(a1) +80011994: 03 25 c5 00 lw a0, 12(a0) +80011998: 83 a8 45 00 lw a7, 4(a1) +8001199c: 83 ae 85 00 lw t4, 8(a1) +800119a0: 83 a6 c5 00 lw a3, 12(a1) +800119a4: 13 01 01 ff addi sp, sp, -16 +800119a8: f3 27 20 00 frrm a5 +800119ac: b7 87 00 00 lui a5, 8 +800119b0: 13 56 05 01 srli a2, a0, 16 +800119b4: 93 87 f7 ff addi a5, a5, -1 +800119b8: 93 15 05 01 slli a1, a0, 16 +800119bc: 13 93 06 01 slli t1, a3, 16 +800119c0: 13 d7 06 01 srli a4, a3, 16 +800119c4: 33 76 f6 00 and a2, a2, a5 +800119c8: 93 d5 05 01 srli a1, a1, 16 +800119cc: 13 55 f5 01 srli a0, a0, 31 +800119d0: 13 53 03 01 srli t1, t1, 16 +800119d4: 33 77 f7 00 and a4, a4, a5 +800119d8: 93 d6 f6 01 srli a3, a3, 31 +800119dc: 63 10 f6 02 bne a2, a5, 32 +800119e0: b3 e7 0f 01 or a5, t6, a6 +800119e4: b3 e7 c7 01 or a5, a5, t3 +800119e8: b3 e7 b7 00 or a5, a5, a1 +800119ec: 63 84 07 0c beqz a5, 200 +800119f0: 73 60 18 00 csrsi fflags, 16 +800119f4: 13 05 e0 ff addi a0, zero, -2 +800119f8: 6f 00 00 05 j 80 +800119fc: 63 1a f7 00 bne a4, a5, 20 +80011a00: b3 e7 12 01 or a5, t0, a7 +80011a04: b3 e7 d7 01 or a5, a5, t4 +80011a08: b3 e7 67 00 or a5, a5, t1 +80011a0c: e3 92 07 fe bnez a5, -28 +80011a10: 63 14 06 0a bnez a2, 168 +80011a14: b3 e7 0f 01 or a5, t6, a6 +80011a18: b3 e7 c7 01 or a5, a5, t3 +80011a1c: b3 e7 b7 00 or a5, a5, a1 +80011a20: 93 b7 17 00 seqz a5, a5 +80011a24: 63 1a 07 00 bnez a4, 20 +80011a28: 33 ef 12 01 or t5, t0, a7 +80011a2c: 33 6f df 01 or t5, t5, t4 +80011a30: 33 6f 6f 00 or t5, t5, t1 +80011a34: 63 04 0f 06 beqz t5, 104 +80011a38: 63 82 07 08 beqz a5, 132 +80011a3c: 13 05 f0 ff addi a0, zero, -1 +80011a40: 63 84 06 00 beqz a3, 8 +80011a44: 13 85 06 00 mv a0, a3 +80011a48: 13 01 01 01 addi sp, sp, 16 +80011a4c: 67 80 00 00 ret +80011a50: 93 07 00 00 mv a5, zero +80011a54: 6f f0 5f fd j -44 +80011a58: 63 56 e6 00 bge a2, a4, 12 +80011a5c: e3 16 05 fe bnez a0, -20 +80011a60: 6f 00 80 06 j 104 +80011a64: 63 60 b3 06 bltu t1, a1, 96 +80011a68: 63 9e 65 02 bne a1, t1, 60 +80011a6c: 63 ec ce 05 bltu t4, t3, 88 +80011a70: 63 1e de 03 bne t3, t4, 60 +80011a74: 63 e8 08 05 bltu a7, a6, 80 +80011a78: 63 14 18 01 bne a6, a7, 8 +80011a7c: 63 e4 f2 05 bltu t0, t6, 72 +80011a80: e3 6e 18 fd bltu a6, a7, -36 +80011a84: 63 14 18 01 bne a6, a7, 8 +80011a88: e3 ea 5f fc bltu t6, t0, -44 +80011a8c: 13 05 00 00 mv a0, zero +80011a90: 6f f0 9f fb j -72 +80011a94: 13 05 10 00 addi a0, zero, 1 +80011a98: 6f f0 1f fb j -80 +80011a9c: e3 98 07 fe bnez a5, -16 +80011aa0: 6f 00 40 02 j 36 +80011aa4: e3 ec 65 fa bltu a1, t1, -72 +80011aa8: 6f f0 5f fe j -28 +80011aac: e3 68 de fb bltu t3, t4, -80 +80011ab0: 6f f0 df fd j -36 +80011ab4: e3 06 c7 f4 beq a4, a2, -180 +80011ab8: e3 0c 07 f8 beqz a4, -104 +80011abc: 63 94 a6 00 bne a3, a0, 8 +80011ac0: e3 5c c7 f8 bge a4, a2, -104 +80011ac4: e3 08 05 fc beqz a0, -48 +80011ac8: 13 05 f0 ff addi a0, zero, -1 +80011acc: 6f f0 df f7 j -132 + +80011ad0 __lttf2: +80011ad0: 83 2f 05 00 lw t6, 0(a0) +80011ad4: 03 28 45 00 lw a6, 4(a0) +80011ad8: 03 2e 85 00 lw t3, 8(a0) +80011adc: 83 a2 05 00 lw t0, 0(a1) +80011ae0: 03 25 c5 00 lw a0, 12(a0) +80011ae4: 83 a8 45 00 lw a7, 4(a1) +80011ae8: 83 ae 85 00 lw t4, 8(a1) +80011aec: 83 a6 c5 00 lw a3, 12(a1) +80011af0: 13 01 01 ff addi sp, sp, -16 +80011af4: f3 27 20 00 frrm a5 +80011af8: b7 87 00 00 lui a5, 8 +80011afc: 13 56 05 01 srli a2, a0, 16 +80011b00: 93 87 f7 ff addi a5, a5, -1 +80011b04: 93 15 05 01 slli a1, a0, 16 +80011b08: 13 93 06 01 slli t1, a3, 16 +80011b0c: 13 d7 06 01 srli a4, a3, 16 +80011b10: 33 76 f6 00 and a2, a2, a5 +80011b14: 93 d5 05 01 srli a1, a1, 16 +80011b18: 13 55 f5 01 srli a0, a0, 31 +80011b1c: 13 53 03 01 srli t1, t1, 16 +80011b20: 33 77 f7 00 and a4, a4, a5 +80011b24: 93 d6 f6 01 srli a3, a3, 31 +80011b28: 63 10 f6 02 bne a2, a5, 32 +80011b2c: b3 e7 0f 01 or a5, t6, a6 +80011b30: b3 e7 c7 01 or a5, a5, t3 +80011b34: b3 e7 b7 00 or a5, a5, a1 +80011b38: 63 84 07 0c beqz a5, 200 +80011b3c: 73 60 18 00 csrsi fflags, 16 +80011b40: 13 05 20 00 addi a0, zero, 2 +80011b44: 6f 00 00 05 j 80 +80011b48: 63 1a f7 00 bne a4, a5, 20 +80011b4c: b3 e7 12 01 or a5, t0, a7 +80011b50: b3 e7 d7 01 or a5, a5, t4 +80011b54: b3 e7 67 00 or a5, a5, t1 +80011b58: e3 92 07 fe bnez a5, -28 +80011b5c: 63 14 06 0a bnez a2, 168 +80011b60: b3 e7 0f 01 or a5, t6, a6 +80011b64: b3 e7 c7 01 or a5, a5, t3 +80011b68: b3 e7 b7 00 or a5, a5, a1 +80011b6c: 93 b7 17 00 seqz a5, a5 +80011b70: 63 1a 07 00 bnez a4, 20 +80011b74: 33 ef 12 01 or t5, t0, a7 +80011b78: 33 6f df 01 or t5, t5, t4 +80011b7c: 33 6f 6f 00 or t5, t5, t1 +80011b80: 63 04 0f 06 beqz t5, 104 +80011b84: 63 82 07 08 beqz a5, 132 +80011b88: 13 05 f0 ff addi a0, zero, -1 +80011b8c: 63 84 06 00 beqz a3, 8 +80011b90: 13 85 06 00 mv a0, a3 +80011b94: 13 01 01 01 addi sp, sp, 16 +80011b98: 67 80 00 00 ret +80011b9c: 93 07 00 00 mv a5, zero +80011ba0: 6f f0 5f fd j -44 +80011ba4: 63 56 e6 00 bge a2, a4, 12 +80011ba8: e3 16 05 fe bnez a0, -20 +80011bac: 6f 00 80 06 j 104 +80011bb0: 63 60 b3 06 bltu t1, a1, 96 +80011bb4: 63 9e 65 02 bne a1, t1, 60 +80011bb8: 63 ec ce 05 bltu t4, t3, 88 +80011bbc: 63 1e de 03 bne t3, t4, 60 +80011bc0: 63 e8 08 05 bltu a7, a6, 80 +80011bc4: 63 14 18 01 bne a6, a7, 8 +80011bc8: 63 e4 f2 05 bltu t0, t6, 72 +80011bcc: e3 6e 18 fd bltu a6, a7, -36 +80011bd0: 63 14 18 01 bne a6, a7, 8 +80011bd4: e3 ea 5f fc bltu t6, t0, -44 +80011bd8: 13 05 00 00 mv a0, zero +80011bdc: 6f f0 9f fb j -72 +80011be0: 13 05 10 00 addi a0, zero, 1 +80011be4: 6f f0 1f fb j -80 +80011be8: e3 98 07 fe bnez a5, -16 +80011bec: 6f 00 40 02 j 36 +80011bf0: e3 ec 65 fa bltu a1, t1, -72 +80011bf4: 6f f0 5f fe j -28 +80011bf8: e3 68 de fb bltu t3, t4, -80 +80011bfc: 6f f0 df fd j -36 +80011c00: e3 06 c7 f4 beq a4, a2, -180 +80011c04: e3 0c 07 f8 beqz a4, -104 +80011c08: 63 94 a6 00 bne a3, a0, 8 +80011c0c: e3 5c c7 f8 bge a4, a2, -104 +80011c10: e3 08 05 fc beqz a0, -48 +80011c14: 13 05 f0 ff addi a0, zero, -1 +80011c18: 6f f0 df f7 j -132 + +80011c1c __multf3: +80011c1c: 13 01 01 f4 addi sp, sp, -192 +80011c20: 23 28 21 0b sw s2, 176(sp) +80011c24: 23 24 41 0b sw s4, 168(sp) +80011c28: 23 22 51 0b sw s5, 164(sp) +80011c2c: 23 20 61 0b sw s6, 160(sp) +80011c30: 23 2c 81 09 sw s8, 152(sp) +80011c34: 23 2a 91 09 sw s9, 148(sp) +80011c38: 13 09 05 00 mv s2, a0 +80011c3c: 83 a6 05 00 lw a3, 0(a1) +80011c40: 83 a7 45 00 lw a5, 4(a1) +80011c44: 03 a5 85 00 lw a0, 8(a1) +80011c48: 83 aa c5 00 lw s5, 12(a1) +80011c4c: 83 2c 06 00 lw s9, 0(a2) +80011c50: 03 2b 46 00 lw s6, 4(a2) +80011c54: 03 2c 86 00 lw s8, 8(a2) +80011c58: 03 2a c6 00 lw s4, 12(a2) +80011c5c: 23 2e 11 0a sw ra, 188(sp) +80011c60: 23 2c 81 0a sw s0, 184(sp) +80011c64: 23 2a 91 0a sw s1, 180(sp) +80011c68: 23 26 31 0b sw s3, 172(sp) +80011c6c: 23 2e 71 09 sw s7, 156(sp) +80011c70: 23 28 a1 09 sw s10, 144(sp) +80011c74: 23 26 b1 09 sw s11, 140(sp) +80011c78: f3 24 20 00 frrm s1 +80011c7c: 37 86 00 00 lui a2, 8 +80011c80: 13 97 0a 01 slli a4, s5, 16 +80011c84: 93 d9 0a 01 srli s3, s5, 16 +80011c88: 13 57 07 01 srli a4, a4, 16 +80011c8c: 13 06 f6 ff addi a2, a2, -1 +80011c90: 23 26 51 07 sw s5, 108(sp) +80011c94: 23 20 d1 06 sw a3, 96(sp) +80011c98: 23 22 f1 06 sw a5, 100(sp) +80011c9c: 23 24 a1 06 sw a0, 104(sp) +80011ca0: 23 28 d1 02 sw a3, 48(sp) +80011ca4: 23 2a f1 02 sw a5, 52(sp) +80011ca8: 23 2c a1 02 sw a0, 56(sp) +80011cac: 23 2e e1 02 sw a4, 60(sp) +80011cb0: b3 f9 c9 00 and s3, s3, a2 +80011cb4: 93 da fa 01 srli s5, s5, 31 +80011cb8: 63 80 09 06 beqz s3, 96 +80011cbc: 63 8e c9 16 beq s3, a2, 380 +80011cc0: 37 05 01 00 lui a0, 16 +80011cc4: 33 67 a7 00 or a4, a4, a0 +80011cc8: 23 2e e1 02 sw a4, 60(sp) +80011ccc: 13 06 01 03 addi a2, sp, 48 +80011cd0: 93 07 c1 03 addi a5, sp, 60 +80011cd4: 03 a7 07 00 lw a4, 0(a5) +80011cd8: 83 a6 c7 ff lw a3, -4(a5) +80011cdc: 93 87 c7 ff addi a5, a5, -4 +80011ce0: 13 17 37 00 slli a4, a4, 3 +80011ce4: 93 d6 d6 01 srli a3, a3, 29 +80011ce8: 33 67 d7 00 or a4, a4, a3 +80011cec: 23 a2 e7 00 sw a4, 4(a5) +80011cf0: e3 12 f6 fe bne a2, a5, -28 +80011cf4: 83 27 01 03 lw a5, 48(sp) +80011cf8: 37 c5 ff ff lui a0, 1048572 +80011cfc: 13 05 15 00 addi a0, a0, 1 +80011d00: 93 97 37 00 slli a5, a5, 3 +80011d04: 23 28 f1 02 sw a5, 48(sp) +80011d08: b3 89 a9 00 add s3, s3, a0 +80011d0c: 93 0b 00 00 mv s7, zero +80011d10: 13 04 00 00 mv s0, zero +80011d14: 6f 00 80 14 j 328 +80011d18: 33 e6 d7 00 or a2, a5, a3 +80011d1c: 33 66 a6 00 or a2, a2, a0 +80011d20: 33 66 e6 00 or a2, a2, a4 +80011d24: 63 06 06 20 beqz a2, 524 +80011d28: 63 00 07 06 beqz a4, 96 +80011d2c: 13 05 07 00 mv a0, a4 +80011d30: ef 30 80 79 jal 14232 +80011d34: 93 06 45 ff addi a3, a0, -12 +80011d38: 93 d7 56 40 srai a5, a3, 5 +80011d3c: 93 f6 f6 01 andi a3, a3, 31 +80011d40: 63 8e 06 06 beqz a3, 124 +80011d44: 13 07 c0 ff addi a4, zero, -4 +80011d48: 33 87 e7 02 mul a4, a5, a4 +80011d4c: 13 03 01 03 addi t1, sp, 48 +80011d50: 13 08 00 02 addi a6, zero, 32 +80011d54: 93 95 27 00 slli a1, a5, 2 +80011d58: 33 08 d8 40 sub a6, a6, a3 +80011d5c: 13 07 c7 00 addi a4, a4, 12 +80011d60: 33 07 e3 00 add a4, t1, a4 +80011d64: 63 14 e3 08 bne t1, a4, 136 +80011d68: 13 07 01 08 addi a4, sp, 128 +80011d6c: b3 05 b7 00 add a1, a4, a1 +80011d70: 03 27 01 03 lw a4, 48(sp) +80011d74: 93 87 f7 ff addi a5, a5, -1 +80011d78: b3 16 d7 00 sll a3, a4, a3 +80011d7c: 23 a8 d5 fa sw a3, -80(a1) +80011d80: 93 06 f0 ff addi a3, zero, -1 +80011d84: 6f 00 00 0a j 160 +80011d88: 63 08 05 00 beqz a0, 16 +80011d8c: ef 30 c0 73 jal 14140 +80011d90: 13 05 05 02 addi a0, a0, 32 +80011d94: 6f f0 1f fa j -96 +80011d98: 63 8a 07 00 beqz a5, 20 +80011d9c: 13 85 07 00 mv a0, a5 +80011da0: ef 30 80 72 jal 14120 +80011da4: 13 05 05 04 addi a0, a0, 64 +80011da8: 6f f0 df f8 j -116 +80011dac: 13 85 06 00 mv a0, a3 +80011db0: ef 30 80 71 jal 14104 +80011db4: 13 05 05 06 addi a0, a0, 96 +80011db8: 6f f0 df f7 j -132 +80011dbc: 13 06 c0 ff addi a2, zero, -4 +80011dc0: 33 86 c7 02 mul a2, a5, a2 +80011dc4: 13 07 c1 03 addi a4, sp, 60 +80011dc8: 93 06 30 00 addi a3, zero, 3 +80011dcc: b3 05 c7 00 add a1, a4, a2 +80011dd0: 83 a5 05 00 lw a1, 0(a1) +80011dd4: 93 86 f6 ff addi a3, a3, -1 +80011dd8: 13 07 c7 ff addi a4, a4, -4 +80011ddc: 23 22 b7 00 sw a1, 4(a4) +80011de0: e3 d6 f6 fe bge a3, a5, -20 +80011de4: 93 87 f7 ff addi a5, a5, -1 +80011de8: 6f f0 9f f9 j -104 +80011dec: 03 26 c7 ff lw a2, -4(a4) +80011df0: 83 28 07 00 lw a7, 0(a4) +80011df4: 33 0e b7 00 add t3, a4, a1 +80011df8: 33 56 06 01 srl a2, a2, a6 +80011dfc: b3 98 d8 00 sll a7, a7, a3 +80011e00: 33 66 16 01 or a2, a2, a7 +80011e04: 23 20 ce 00 sw a2, 0(t3) +80011e08: 13 07 c7 ff addi a4, a4, -4 +80011e0c: 6f f0 9f f5 j -168 +80011e10: 13 97 27 00 slli a4, a5, 2 +80011e14: 13 06 01 03 addi a2, sp, 48 +80011e18: 33 07 e6 00 add a4, a2, a4 +80011e1c: 23 20 07 00 sw zero, 0(a4) +80011e20: 93 87 f7 ff addi a5, a5, -1 +80011e24: e3 96 d7 fe bne a5, a3, -20 +80011e28: b7 c9 ff ff lui s3, 1048572 +80011e2c: 93 89 19 01 addi s3, s3, 17 +80011e30: b3 89 a9 40 sub s3, s3, a0 +80011e34: 6f f0 9f ed j -296 +80011e38: b3 e7 d7 00 or a5, a5, a3 +80011e3c: b3 e7 a7 00 or a5, a5, a0 +80011e40: b3 e7 e7 00 or a5, a5, a4 +80011e44: 63 8c 07 0e beqz a5, 248 +80011e48: 13 17 07 01 slli a4, a4, 16 +80011e4c: 13 57 07 41 srai a4, a4, 16 +80011e50: 93 0b 30 00 addi s7, zero, 3 +80011e54: 13 04 00 01 addi s0, zero, 16 +80011e58: e3 4c 07 ea bltz a4, -328 +80011e5c: 13 15 0a 01 slli a0, s4, 16 +80011e60: 37 87 00 00 lui a4, 8 +80011e64: 93 57 0a 01 srli a5, s4, 16 +80011e68: 13 55 05 01 srli a0, a0, 16 +80011e6c: 13 07 f7 ff addi a4, a4, -1 +80011e70: 23 26 41 07 sw s4, 108(sp) +80011e74: 23 20 91 07 sw s9, 96(sp) +80011e78: 23 22 61 07 sw s6, 100(sp) +80011e7c: 23 24 81 07 sw s8, 104(sp) +80011e80: 23 20 91 05 sw s9, 64(sp) +80011e84: 23 22 61 05 sw s6, 68(sp) +80011e88: 23 24 81 05 sw s8, 72(sp) +80011e8c: 23 26 a1 04 sw a0, 76(sp) +80011e90: b3 f7 e7 00 and a5, a5, a4 +80011e94: 13 5a fa 01 srli s4, s4, 31 +80011e98: 63 86 07 0a beqz a5, 172 +80011e9c: 63 84 e7 1c beq a5, a4, 456 +80011ea0: 37 07 01 00 lui a4, 16 +80011ea4: 33 65 e5 00 or a0, a0, a4 +80011ea8: 23 26 a1 04 sw a0, 76(sp) +80011eac: 93 05 01 04 addi a1, sp, 64 +80011eb0: 13 07 c1 04 addi a4, sp, 76 +80011eb4: 83 26 07 00 lw a3, 0(a4) +80011eb8: 03 26 c7 ff lw a2, -4(a4) +80011ebc: 13 07 c7 ff addi a4, a4, -4 +80011ec0: 93 96 36 00 slli a3, a3, 3 +80011ec4: 13 56 d6 01 srli a2, a2, 29 +80011ec8: b3 e6 c6 00 or a3, a3, a2 +80011ecc: 23 22 d7 00 sw a3, 4(a4) +80011ed0: e3 92 e5 fe bne a1, a4, -28 +80011ed4: 03 27 01 04 lw a4, 64(sp) +80011ed8: 37 c5 ff ff lui a0, 1048572 +80011edc: 13 05 15 00 addi a0, a0, 1 +80011ee0: 13 17 37 00 slli a4, a4, 3 +80011ee4: 23 20 e1 04 sw a4, 64(sp) +80011ee8: 33 85 a7 00 add a0, a5, a0 +80011eec: 93 06 00 00 mv a3, zero +80011ef0: 33 07 35 01 add a4, a0, s3 +80011ef4: 23 24 e1 00 sw a4, 8(sp) +80011ef8: 13 07 17 00 addi a4, a4, 1 +80011efc: 23 22 e1 00 sw a4, 4(sp) +80011f00: 13 97 2b 00 slli a4, s7, 2 +80011f04: 33 67 d7 00 or a4, a4, a3 +80011f08: 13 07 f7 ff addi a4, a4, -1 +80011f0c: 13 06 e0 00 addi a2, zero, 14 +80011f10: b3 c7 4a 01 xor a5, s5, s4 +80011f14: 63 62 e6 1c bltu a2, a4, 452 +80011f18: 37 66 01 80 lui a2, 524310 +80011f1c: 13 17 27 00 slli a4, a4, 2 +80011f20: 13 06 c6 05 addi a2, a2, 92 +80011f24: 33 07 c7 00 add a4, a4, a2 +80011f28: 03 27 07 00 lw a4, 0(a4) +80011f2c: 67 00 07 00 jr a4 +80011f30: 93 09 00 00 mv s3, zero +80011f34: 93 0b 10 00 addi s7, zero, 1 +80011f38: 6f f0 9f dd j -552 +80011f3c: 93 0b 20 00 addi s7, zero, 2 +80011f40: 6f f0 1f dd j -560 +80011f44: b3 67 9b 01 or a5, s6, s9 +80011f48: b3 e7 87 01 or a5, a5, s8 +80011f4c: b3 e7 a7 00 or a5, a5, a0 +80011f50: 63 80 07 14 beqz a5, 320 +80011f54: 63 0e 05 04 beqz a0, 92 +80011f58: ef 30 00 57 jal 13680 +80011f5c: 93 06 45 ff addi a3, a0, -12 +80011f60: 93 d7 56 40 srai a5, a3, 5 +80011f64: 93 f6 f6 01 andi a3, a3, 31 +80011f68: 63 80 06 08 beqz a3, 128 +80011f6c: 13 07 c0 ff addi a4, zero, -4 +80011f70: 33 87 e7 02 mul a4, a5, a4 +80011f74: 13 03 01 04 addi t1, sp, 64 +80011f78: 13 08 00 02 addi a6, zero, 32 +80011f7c: 93 95 27 00 slli a1, a5, 2 +80011f80: 33 08 d8 40 sub a6, a6, a3 +80011f84: 13 07 c7 00 addi a4, a4, 12 +80011f88: 33 07 e3 00 add a4, t1, a4 +80011f8c: 63 16 e3 08 bne t1, a4, 140 +80011f90: 13 07 01 08 addi a4, sp, 128 +80011f94: b3 05 b7 00 add a1, a4, a1 +80011f98: 03 27 01 04 lw a4, 64(sp) +80011f9c: 93 87 f7 ff addi a5, a5, -1 +80011fa0: b3 16 d7 00 sll a3, a4, a3 +80011fa4: 23 a0 d5 fc sw a3, -64(a1) +80011fa8: 93 06 f0 ff addi a3, zero, -1 +80011fac: 6f 00 40 0a j 164 +80011fb0: 63 0a 0c 00 beqz s8, 20 +80011fb4: 13 05 0c 00 mv a0, s8 +80011fb8: ef 30 00 51 jal 13584 +80011fbc: 13 05 05 02 addi a0, a0, 32 +80011fc0: 6f f0 df f9 j -100 +80011fc4: 63 0a 0b 00 beqz s6, 20 +80011fc8: 13 05 0b 00 mv a0, s6 +80011fcc: ef 30 c0 4f jal 13564 +80011fd0: 13 05 05 04 addi a0, a0, 64 +80011fd4: 6f f0 9f f8 j -120 +80011fd8: 13 85 0c 00 mv a0, s9 +80011fdc: ef 30 c0 4e jal 13548 +80011fe0: 13 05 05 06 addi a0, a0, 96 +80011fe4: 6f f0 9f f7 j -136 +80011fe8: 13 06 c0 ff addi a2, zero, -4 +80011fec: 33 86 c7 02 mul a2, a5, a2 +80011ff0: 13 07 c1 04 addi a4, sp, 76 +80011ff4: 93 06 30 00 addi a3, zero, 3 +80011ff8: b3 05 c7 00 add a1, a4, a2 +80011ffc: 83 a5 05 00 lw a1, 0(a1) +80012000: 93 86 f6 ff addi a3, a3, -1 +80012004: 13 07 c7 ff addi a4, a4, -4 +80012008: 23 22 b7 00 sw a1, 4(a4) +8001200c: e3 d6 f6 fe bge a3, a5, -20 +80012010: 93 87 f7 ff addi a5, a5, -1 +80012014: 6f f0 5f f9 j -108 +80012018: 03 26 c7 ff lw a2, -4(a4) +8001201c: 83 28 07 00 lw a7, 0(a4) +80012020: 33 0e b7 00 add t3, a4, a1 +80012024: 33 56 06 01 srl a2, a2, a6 +80012028: b3 98 d8 00 sll a7, a7, a3 +8001202c: 33 66 16 01 or a2, a2, a7 +80012030: 23 20 ce 00 sw a2, 0(t3) +80012034: 13 07 c7 ff addi a4, a4, -4 +80012038: 6f f0 5f f5 j -172 +8001203c: 13 97 27 00 slli a4, a5, 2 +80012040: 13 06 01 04 addi a2, sp, 64 +80012044: 33 07 e6 00 add a4, a2, a4 +80012048: 23 20 07 00 sw zero, 0(a4) +8001204c: 93 87 f7 ff addi a5, a5, -1 +80012050: e3 96 d7 fe bne a5, a3, -20 +80012054: b7 c7 ff ff lui a5, 1048572 +80012058: 93 87 17 01 addi a5, a5, 17 +8001205c: 33 85 a7 40 sub a0, a5, a0 +80012060: 6f f0 df e8 j -372 +80012064: 33 6b 9b 01 or s6, s6, s9 +80012068: 33 6b 8b 01 or s6, s6, s8 +8001206c: 33 6b ab 00 or s6, s6, a0 +80012070: 63 06 0b 02 beqz s6, 44 +80012074: 13 15 05 01 slli a0, a0, 16 +80012078: 13 55 05 41 srai a0, a0, 16 +8001207c: 63 46 05 02 bltz a0, 44 +80012080: 13 85 07 00 mv a0, a5 +80012084: 93 06 30 00 addi a3, zero, 3 +80012088: 13 04 00 01 addi s0, zero, 16 +8001208c: 6f f0 5f e6 j -412 +80012090: 13 05 00 00 mv a0, zero +80012094: 93 06 10 00 addi a3, zero, 1 +80012098: 6f f0 9f e5 j -424 +8001209c: 13 85 07 00 mv a0, a5 +800120a0: 93 06 20 00 addi a3, zero, 2 +800120a4: 6f f0 df e4 j -436 +800120a8: 13 85 07 00 mv a0, a5 +800120ac: 93 06 30 00 addi a3, zero, 3 +800120b0: 6f f0 1f e4 j -448 +800120b4: 13 04 00 01 addi s0, zero, 16 +800120b8: 37 87 00 00 lui a4, 8 +800120bc: 23 2e e1 04 sw a4, 92(sp) +800120c0: 23 2c 01 04 sw zero, 88(sp) +800120c4: 23 2a 01 04 sw zero, 84(sp) +800120c8: 23 28 01 04 sw zero, 80(sp) +800120cc: 13 07 f7 ff addi a4, a4, -1 +800120d0: 93 07 00 00 mv a5, zero +800120d4: 6f 00 d0 19 j 2460 +800120d8: 83 25 01 03 lw a1, 48(sp) +800120dc: 03 25 01 04 lw a0, 64(sp) +800120e0: b7 08 01 00 lui a7, 16 +800120e4: 13 86 f8 ff addi a2, a7, -1 +800120e8: 93 d3 05 01 srli t2, a1, 16 +800120ec: 13 57 05 01 srli a4, a0, 16 +800120f0: b3 f5 c5 00 and a1, a1, a2 +800120f4: 33 75 c5 00 and a0, a0, a2 +800120f8: b3 06 b7 02 mul a3, a4, a1 +800120fc: 33 0a b5 02 mul s4, a0, a1 +80012100: 33 83 a3 02 mul t1, t2, a0 +80012104: 33 88 66 00 add a6, a3, t1 +80012108: 93 56 0a 01 srli a3, s4, 16 +8001210c: b3 86 06 01 add a3, a3, a6 +80012110: b3 89 e3 02 mul s3, t2, a4 +80012114: 63 f4 66 00 bgeu a3, t1, 8 +80012118: b3 89 19 01 add s3, s3, a7 +8001211c: 03 2e 41 04 lw t3, 68(sp) +80012120: 93 d8 06 01 srli a7, a3, 16 +80012124: b3 f6 c6 00 and a3, a3, a2 +80012128: 33 7a ca 00 and s4, s4, a2 +8001212c: 93 96 06 01 slli a3, a3, 16 +80012130: b3 86 46 01 add a3, a3, s4 +80012134: 93 5f 0e 01 srli t6, t3, 16 +80012138: 33 7e ce 00 and t3, t3, a2 +8001213c: 33 03 be 02 mul t1, t3, a1 +80012140: 23 26 d1 00 sw a3, 12(sp) +80012144: 23 20 d1 06 sw a3, 96(sp) +80012148: 33 86 c3 03 mul a2, t2, t3 +8001214c: b3 86 bf 02 mul a3, t6, a1 +80012150: 33 88 c6 00 add a6, a3, a2 +80012154: 93 56 03 01 srli a3, t1, 16 +80012158: b3 86 06 01 add a3, a3, a6 +8001215c: b3 8b f3 03 mul s7, t2, t6 +80012160: 63 f6 c6 00 bgeu a3, a2, 12 +80012164: 37 06 01 00 lui a2, 16 +80012168: b3 8b cb 00 add s7, s7, a2 +8001216c: 13 d6 06 01 srli a2, a3, 16 +80012170: b7 0e 01 00 lui t4, 16 +80012174: 23 20 c1 00 sw a2, 0(sp) +80012178: 13 86 fe ff addi a2, t4, -1 +8001217c: 33 f8 c6 00 and a6, a3, a2 +80012180: 33 73 c3 00 and t1, t1, a2 +80012184: 13 18 08 01 slli a6, a6, 16 +80012188: 33 08 68 00 add a6, a6, t1 +8001218c: b3 86 08 01 add a3, a7, a6 +80012190: 23 20 d1 02 sw a3, 32(sp) +80012194: 83 26 41 03 lw a3, 52(sp) +80012198: 93 d2 06 01 srli t0, a3, 16 +8001219c: 33 f6 c6 00 and a2, a3, a2 +800121a0: 33 03 a6 02 mul t1, a2, a0 +800121a4: 33 8a a2 02 mul s4, t0, a0 +800121a8: 93 58 03 01 srli a7, t1, 16 +800121ac: b3 06 c7 02 mul a3, a4, a2 +800121b0: b3 86 46 01 add a3, a3, s4 +800121b4: b3 86 d8 00 add a3, a7, a3 +800121b8: 33 0f 57 02 mul t5, a4, t0 +800121bc: 63 f4 46 01 bgeu a3, s4, 8 +800121c0: 33 0f df 01 add t5, t5, t4 +800121c4: 93 d8 06 01 srli a7, a3, 16 +800121c8: 37 0a 01 00 lui s4, 16 +800121cc: b3 88 e8 01 add a7, a7, t5 +800121d0: 93 0e fa ff addi t4, s4, -1 +800121d4: 13 8b 08 00 mv s6, a7 +800121d8: b3 f8 d6 01 and a7, a3, t4 +800121dc: 33 73 d3 01 and t1, t1, t4 +800121e0: 93 98 08 01 slli a7, a7, 16 +800121e4: b3 0e c6 03 mul t4, a2, t3 +800121e8: b3 88 68 00 add a7, a7, t1 +800121ec: b3 86 cf 02 mul a3, t6, a2 +800121f0: 93 da 0e 01 srli s5, t4, 16 +800121f4: 33 83 c2 03 mul t1, t0, t3 +800121f8: b3 86 66 00 add a3, a3, t1 +800121fc: b3 86 da 00 add a3, s5, a3 +80012200: 33 8f 5f 02 mul t5, t6, t0 +80012204: 63 f4 66 00 bgeu a3, t1, 8 +80012208: 33 0f 4f 01 add t5, t5, s4 +8001220c: 13 d3 06 01 srli t1, a3, 16 +80012210: 33 03 e3 01 add t1, t1, t5 +80012214: b7 0a 01 00 lui s5, 16 +80012218: 23 28 61 00 sw t1, 16(sp) +8001221c: 13 83 fa ff addi t1, s5, -1 +80012220: b3 f6 66 00 and a3, a3, t1 +80012224: b3 fe 6e 00 and t4, t4, t1 +80012228: 93 96 06 01 slli a3, a3, 16 +8001222c: b3 8d d6 01 add s11, a3, t4 +80012230: 83 26 81 04 lw a3, 72(sp) +80012234: 33 f3 66 00 and t1, a3, t1 +80012238: 93 de 06 01 srli t4, a3, 16 +8001223c: 33 0a b3 02 mul s4, t1, a1 +80012240: 33 8c 63 02 mul s8, t2, t1 +80012244: 93 5c 0a 01 srli s9, s4, 16 +80012248: 33 8f be 02 mul t5, t4, a1 +8001224c: 33 0f 8f 01 add t5, t5, s8 +80012250: 33 8f ec 01 add t5, s9, t5 +80012254: b3 86 d3 03 mul a3, t2, t4 +80012258: 63 74 8f 01 bgeu t5, s8, 8 +8001225c: b3 86 56 01 add a3, a3, s5 +80012260: 93 5a 0f 01 srli s5, t5, 16 +80012264: b3 86 da 00 add a3, s5, a3 +80012268: 37 0d 01 00 lui s10, 16 +8001226c: 23 2a d1 00 sw a3, 20(sp) +80012270: 93 06 fd ff addi a3, s10, -1 +80012274: 33 7f df 00 and t5, t5, a3 +80012278: 33 7a da 00 and s4, s4, a3 +8001227c: 13 1f 0f 01 slli t5, t5, 16 +80012280: 33 0f 4f 01 add t5, t5, s4 +80012284: 03 2a 81 03 lw s4, 56(sp) +80012288: 23 2c e1 01 sw t5, 24(sp) +8001228c: b3 76 da 00 and a3, s4, a3 +80012290: 13 5f 0a 01 srli t5, s4, 16 +80012294: 33 0a af 02 mul s4, t5, a0 +80012298: b3 8a a6 02 mul s5, a3, a0 +8001229c: b3 0c d7 02 mul s9, a4, a3 +800122a0: b3 8c 4c 01 add s9, s9, s4 +800122a4: 13 da 0a 01 srli s4, s5, 16 +800122a8: 33 0a 9a 01 add s4, s4, s9 +800122ac: b3 0c af 02 mul s9, t5, a0 +800122b0: 33 0c e7 03 mul s8, a4, t5 +800122b4: 63 74 9a 01 bgeu s4, s9, 8 +800122b8: 33 0c ac 01 add s8, s8, s10 +800122bc: 93 5c 0a 01 srli s9, s4, 16 +800122c0: 33 8c 8c 01 add s8, s9, s8 +800122c4: 23 2e 81 01 sw s8, 28(sp) +800122c8: 37 0c 01 00 lui s8, 16 +800122cc: 13 0d fc ff addi s10, s8, -1 +800122d0: 33 7a aa 01 and s4, s4, s10 +800122d4: b3 fa aa 01 and s5, s5, s10 +800122d8: 13 1a 0a 01 slli s4, s4, 16 +800122dc: b3 0c 5a 01 add s9, s4, s5 +800122e0: 03 2a 01 02 lw s4, 32(sp) +800122e4: b3 89 49 01 add s3, s3, s4 +800122e8: 03 2a 01 00 lw s4, 0(sp) +800122ec: 33 b8 09 01 sltu a6, s3, a6 +800122f0: b3 89 19 01 add s3, s3, a7 +800122f4: 33 0a 0a 01 add s4, s4, a6 +800122f8: b3 0b 7a 01 add s7, s4, s7 +800122fc: 33 8c 6b 01 add s8, s7, s6 +80012300: b3 b8 19 01 sltu a7, s3, a7 +80012304: b3 0a 1c 01 add s5, s8, a7 +80012308: b3 b8 1a 01 sltu a7, s5, a7 +8001230c: 33 3c 6c 01 sltu s8, s8, s6 +80012310: b3 68 1c 01 or a7, s8, a7 +80012314: b3 bb 0b 01 sltu s7, s7, a6 +80012318: b3 8b 78 01 add s7, a7, s7 +8001231c: 83 28 81 01 lw a7, 24(sp) +80012320: 33 8a ba 01 add s4, s5, s11 +80012324: b3 3d ba 01 sltu s11, s4, s11 +80012328: 03 28 01 01 lw a6, 16(sp) +8001232c: 33 0a 1a 01 add s4, s4, a7 +80012330: b3 38 1a 01 sltu a7, s4, a7 +80012334: 23 2c 11 01 sw a7, 24(sp) +80012338: 83 28 41 01 lw a7, 20(sp) +8001233c: b3 8b 0b 01 add s7, s7, a6 +80012340: 23 20 31 01 sw s3, 0(sp) +80012344: 23 22 31 07 sw s3, 100(sp) +80012348: 83 29 81 01 lw s3, 24(sp) +8001234c: 33 88 bb 01 add a6, s7, s11 +80012350: b3 08 18 01 add a7, a6, a7 +80012354: b3 8a 38 01 add s5, a7, s3 +80012358: b3 3d b8 01 sltu s11, a6, s11 +8001235c: 83 29 c1 01 lw s3, 28(sp) +80012360: 03 28 41 01 lw a6, 20(sp) +80012364: 33 0a 9a 01 add s4, s4, s9 +80012368: 33 8c 3a 01 add s8, s5, s3 +8001236c: b3 b8 08 01 sltu a7, a7, a6 +80012370: b3 3c 9a 01 sltu s9, s4, s9 +80012374: 03 28 81 01 lw a6, 24(sp) +80012378: b3 09 9c 01 add s3, s8, s9 +8001237c: 13 8b 09 00 mv s6, s3 +80012380: 83 29 01 01 lw s3, 16(sp) +80012384: b3 ba 0a 01 sltu s5, s5, a6 +80012388: 03 28 c1 01 lw a6, 28(sp) +8001238c: b3 bb 3b 01 sltu s7, s7, s3 +80012390: b3 ea 58 01 or s5, a7, s5 +80012394: b3 ed bb 01 or s11, s7, s11 +80012398: 33 3c 0c 01 sltu s8, s8, a6 +8001239c: b3 3c 9b 01 sltu s9, s6, s9 +800123a0: b3 8d 5d 01 add s11, s11, s5 +800123a4: b3 6c 9c 01 or s9, s8, s9 +800123a8: 33 88 9d 01 add a6, s11, s9 +800123ac: 23 2a 01 01 sw a6, 20(sp) +800123b0: 03 28 c1 04 lw a6, 76(sp) +800123b4: 23 24 41 07 sw s4, 104(sp) +800123b8: 93 58 08 01 srli a7, a6, 16 +800123bc: 33 7d a8 01 and s10, a6, s10 +800123c0: 33 08 bd 02 mul a6, s10, a1 +800123c4: b3 8a a3 03 mul s5, t2, s10 +800123c8: 93 5b 08 01 srli s7, a6, 16 +800123cc: b3 85 b8 02 mul a1, a7, a1 +800123d0: b3 85 55 01 add a1, a1, s5 +800123d4: b3 85 bb 00 add a1, s7, a1 +800123d8: b3 83 13 03 mul t2, t2, a7 +800123dc: 63 f6 55 01 bgeu a1, s5, 12 +800123e0: 37 0c 01 00 lui s8, 16 +800123e4: b3 83 83 01 add t2, t2, s8 +800123e8: 93 da 05 01 srli s5, a1, 16 +800123ec: b3 83 7a 00 add t2, s5, t2 +800123f0: 37 0c 01 00 lui s8, 16 +800123f4: 83 2a c1 03 lw s5, 60(sp) +800123f8: 23 2e 71 00 sw t2, 28(sp) +800123fc: 93 03 fc ff addi t2, s8, -1 +80012400: b3 f5 75 00 and a1, a1, t2 +80012404: 33 78 78 00 and a6, a6, t2 +80012408: 93 95 05 01 slli a1, a1, 16 +8001240c: b3 f3 7a 00 and t2, s5, t2 +80012410: b3 85 05 01 add a1, a1, a6 +80012414: 13 d8 0a 01 srli a6, s5, 16 +80012418: b3 0b 07 03 mul s7, a4, a6 +8001241c: b3 8a a3 02 mul s5, t2, a0 +80012420: 33 07 77 02 mul a4, a4, t2 +80012424: 93 dd 0a 01 srli s11, s5, 16 +80012428: 33 05 a8 02 mul a0, a6, a0 +8001242c: 33 07 a7 00 add a4, a4, a0 +80012430: 33 87 ed 00 add a4, s11, a4 +80012434: 63 74 a7 00 bgeu a4, a0, 8 +80012438: b3 8b 8b 01 add s7, s7, s8 +8001243c: 37 0c 01 00 lui s8, 16 +80012440: 93 0d fc ff addi s11, s8, -1 +80012444: 13 55 07 01 srli a0, a4, 16 +80012448: 33 77 b7 01 and a4, a4, s11 +8001244c: 33 05 75 01 add a0, a0, s7 +80012450: 13 17 07 01 slli a4, a4, 16 +80012454: b3 fd ba 01 and s11, s5, s11 +80012458: 23 20 a1 02 sw a0, 32(sp) +8001245c: b3 8a 62 02 mul s5, t0, t1 +80012460: b3 0d b7 01 add s11, a4, s11 +80012464: 33 05 c3 02 mul a0, t1, a2 +80012468: 33 87 ce 02 mul a4, t4, a2 +8001246c: 93 5c 05 01 srli s9, a0, 16 +80012470: 33 07 57 01 add a4, a4, s5 +80012474: 33 87 ec 00 add a4, s9, a4 +80012478: b3 8b d2 03 mul s7, t0, t4 +8001247c: 63 74 57 01 bgeu a4, s5, 8 +80012480: b3 8b 8b 01 add s7, s7, s8 +80012484: 93 5a 07 01 srli s5, a4, 16 +80012488: b3 89 7a 01 add s3, s5, s7 +8001248c: b7 0b 01 00 lui s7, 16 +80012490: 93 8a fb ff addi s5, s7, -1 +80012494: 33 77 57 01 and a4, a4, s5 +80012498: 33 75 55 01 and a0, a0, s5 +8001249c: 13 17 07 01 slli a4, a4, 16 +800124a0: 33 07 a7 00 add a4, a4, a0 +800124a4: b3 0a cf 03 mul s5, t5, t3 +800124a8: 23 28 e1 00 sw a4, 16(sp) +800124ac: 23 22 31 03 sw s3, 36(sp) +800124b0: 33 87 c6 03 mul a4, a3, t3 +800124b4: b3 8c df 02 mul s9, t6, a3 +800124b8: 13 55 07 01 srli a0, a4, 16 +800124bc: b3 8c 5c 01 add s9, s9, s5 +800124c0: 33 05 95 01 add a0, a0, s9 +800124c4: 33 8c ef 03 mul s8, t6, t5 +800124c8: 63 74 55 01 bgeu a0, s5, 8 +800124cc: 33 0c 7c 01 add s8, s8, s7 +800124d0: 93 5a 05 01 srli s5, a0, 16 +800124d4: 33 8c 8a 01 add s8, s5, s8 +800124d8: b7 0a 01 00 lui s5, 16 +800124dc: 93 8a fa ff addi s5, s5, -1 +800124e0: 33 75 55 01 and a0, a0, s5 +800124e4: 13 15 05 01 slli a0, a0, 16 +800124e8: 33 77 57 01 and a4, a4, s5 +800124ec: 33 07 e5 00 add a4, a0, a4 +800124f0: 83 29 c1 01 lw s3, 28(sp) +800124f4: 03 25 41 01 lw a0, 20(sp) +800124f8: b3 0a bb 00 add s5, s6, a1 +800124fc: b3 b5 ba 00 sltu a1, s5, a1 +80012500: b3 0c 35 01 add s9, a0, s3 +80012504: 83 29 01 02 lw s3, 32(sp) +80012508: 33 85 bc 00 add a0, s9, a1 +8001250c: b3 8a ba 01 add s5, s5, s11 +80012510: b3 bd ba 01 sltu s11, s5, s11 +80012514: b3 0b 35 01 add s7, a0, s3 +80012518: b3 89 bb 01 add s3, s7, s11 +8001251c: 23 26 31 03 sw s3, 44(sp) +80012520: 83 29 01 01 lw s3, 16(sp) +80012524: 03 2b 41 02 lw s6, 36(sp) +80012528: b3 35 b5 00 sltu a1, a0, a1 +8001252c: b3 8a 3a 01 add s5, s5, s3 +80012530: b3 b9 3a 01 sltu s3, s5, s3 +80012534: 23 24 31 03 sw s3, 40(sp) +80012538: b3 89 bb 01 add s3, s7, s11 +8001253c: b3 89 69 01 add s3, s3, s6 +80012540: 03 2b 81 02 lw s6, 40(sp) +80012544: 03 25 01 02 lw a0, 32(sp) +80012548: 23 28 31 01 sw s3, 16(sp) +8001254c: b3 8a ea 00 add s5, s5, a4 +80012550: b3 89 69 01 add s3, s3, s6 +80012554: 13 8b 09 00 mv s6, s3 +80012558: 33 b7 ea 00 sltu a4, s5, a4 +8001255c: b3 89 89 01 add s3, s3, s8 +80012560: 23 2a 31 01 sw s3, 20(sp) +80012564: b3 89 e9 00 add s3, s3, a4 +80012568: b3 bb ab 00 sltu s7, s7, a0 +8001256c: 23 2c 31 01 sw s3, 24(sp) +80012570: 03 25 c1 02 lw a0, 44(sp) +80012574: 83 29 c1 01 lw s3, 28(sp) +80012578: 23 26 51 07 sw s5, 108(sp) +8001257c: b3 3d b5 01 sltu s11, a0, s11 +80012580: b3 bc 3c 01 sltu s9, s9, s3 +80012584: 03 25 01 01 lw a0, 16(sp) +80012588: 83 29 41 02 lw s3, 36(sp) +8001258c: b3 ed bb 01 or s11, s7, s11 +80012590: b3 e5 bc 00 or a1, s9, a1 +80012594: b3 3b 35 01 sltu s7, a0, s3 +80012598: 03 25 41 01 lw a0, 20(sp) +8001259c: 83 29 81 02 lw s3, 40(sp) +800125a0: b3 85 b5 01 add a1, a1, s11 +800125a4: 33 3c 85 01 sltu s8, a0, s8 +800125a8: 03 25 81 01 lw a0, 24(sp) +800125ac: b3 3d 3b 01 sltu s11, s6, s3 +800125b0: b3 ed bb 01 or s11, s7, s11 +800125b4: 33 37 e5 00 sltu a4, a0, a4 +800125b8: 33 67 ec 00 or a4, s8, a4 +800125bc: b3 8d b5 01 add s11, a1, s11 +800125c0: 33 85 66 02 mul a0, a3, t1 +800125c4: b3 8d ed 00 add s11, s11, a4 +800125c8: 33 0c 6f 02 mul s8, t5, t1 +800125cc: 93 55 05 01 srli a1, a0, 16 +800125d0: 33 87 de 02 mul a4, t4, a3 +800125d4: 33 07 87 01 add a4, a4, s8 +800125d8: 33 87 e5 00 add a4, a1, a4 +800125dc: b3 8b ee 03 mul s7, t4, t5 +800125e0: 63 76 87 01 bgeu a4, s8, 12 +800125e4: b7 05 01 00 lui a1, 16 +800125e8: b3 8b bb 00 add s7, s7, a1 +800125ec: 93 55 07 01 srli a1, a4, 16 +800125f0: 37 0c 01 00 lui s8, 16 +800125f4: b3 8b 75 01 add s7, a1, s7 +800125f8: 93 05 fc ff addi a1, s8, -1 +800125fc: 33 77 b7 00 and a4, a4, a1 +80012600: b3 75 b5 00 and a1, a0, a1 +80012604: b3 8c a2 03 mul s9, t0, s10 +80012608: 13 17 07 01 slli a4, a4, 16 +8001260c: b3 05 b7 00 add a1, a4, a1 +80012610: 33 05 cd 02 mul a0, s10, a2 +80012614: 33 86 c8 02 mul a2, a7, a2 +80012618: 13 57 05 01 srli a4, a0, 16 +8001261c: 33 06 96 01 add a2, a2, s9 +80012620: 33 07 c7 00 add a4, a4, a2 +80012624: b3 82 12 03 mul t0, t0, a7 +80012628: 63 74 97 01 bgeu a4, s9, 8 +8001262c: b3 82 82 01 add t0, t0, s8 +80012630: 13 56 07 01 srli a2, a4, 16 +80012634: b7 0c 01 00 lui s9, 16 +80012638: b3 02 56 00 add t0, a2, t0 +8001263c: 13 86 fc ff addi a2, s9, -1 +80012640: 33 77 c7 00 and a4, a4, a2 +80012644: 13 17 07 01 slli a4, a4, 16 +80012648: 33 76 c5 00 and a2, a0, a2 +8001264c: 33 8c 0f 03 mul s8, t6, a6 +80012650: 33 06 c7 00 add a2, a4, a2 +80012654: b3 8f 7f 02 mul t6, t6, t2 +80012658: 33 87 c3 03 mul a4, t2, t3 +8001265c: 33 0e c8 03 mul t3, a6, t3 +80012660: 13 55 07 01 srli a0, a4, 16 +80012664: b3 8f cf 01 add t6, t6, t3 +80012668: b3 0f f5 01 add t6, a0, t6 +8001266c: 63 f4 cf 01 bgeu t6, t3, 8 +80012670: 33 0c 9c 01 add s8, s8, s9 +80012674: 13 de 0f 01 srli t3, t6, 16 +80012678: 33 0e 8e 01 add t3, t3, s8 +8001267c: 37 0c 01 00 lui s8, 16 +80012680: 13 05 fc ff addi a0, s8, -1 +80012684: b3 ff af 00 and t6, t6, a0 +80012688: 93 9f 0f 01 slli t6, t6, 16 +8001268c: 33 77 a7 00 and a4, a4, a0 +80012690: b3 0c af 03 mul s9, t5, s10 +80012694: 33 85 ef 00 add a0, t6, a4 +80012698: b3 8f a6 03 mul t6, a3, s10 +8001269c: b3 86 d8 02 mul a3, a7, a3 +800126a0: 13 d7 0f 01 srli a4, t6, 16 +800126a4: b3 86 96 01 add a3, a3, s9 +800126a8: 33 07 d7 00 add a4, a4, a3 +800126ac: 33 0f 1f 03 mul t5, t5, a7 +800126b0: 63 74 97 01 bgeu a4, s9, 8 +800126b4: 33 0f 8f 01 add t5, t5, s8 +800126b8: 93 56 07 01 srli a3, a4, 16 +800126bc: 37 0c 01 00 lui s8, 16 +800126c0: 33 8f e6 01 add t5, a3, t5 +800126c4: 93 06 fc ff addi a3, s8, -1 +800126c8: 33 77 d7 00 and a4, a4, a3 +800126cc: 13 17 07 01 slli a4, a4, 16 +800126d0: b3 f6 df 00 and a3, t6, a3 +800126d4: b3 06 d7 00 add a3, a4, a3 +800126d8: b3 8f 0e 03 mul t6, t4, a6 +800126dc: 33 87 63 02 mul a4, t2, t1 +800126e0: b3 8e 7e 02 mul t4, t4, t2 +800126e4: 93 5c 07 01 srli s9, a4, 16 +800126e8: 33 03 68 02 mul t1, a6, t1 +800126ec: b3 8e 6e 00 add t4, t4, t1 +800126f0: b3 8e dc 01 add t4, s9, t4 +800126f4: 63 f4 6e 00 bgeu t4, t1, 8 +800126f8: b3 8f 8f 01 add t6, t6, s8 +800126fc: 13 d3 0e 01 srli t1, t4, 16 +80012700: b3 0f f3 01 add t6, t1, t6 +80012704: 37 03 01 00 lui t1, 16 +80012708: 83 29 81 01 lw s3, 24(sp) +8001270c: 13 03 f3 ff addi t1, t1, -1 +80012710: b3 fe 6e 00 and t4, t4, t1 +80012714: 33 77 67 00 and a4, a4, t1 +80012718: 93 9e 0e 01 slli t4, t4, 16 +8001271c: b3 8e ee 00 add t4, t4, a4 +80012720: 33 87 b9 00 add a4, s3, a1 +80012724: b3 35 b7 00 sltu a1, a4, a1 +80012728: b3 8d 7d 01 add s11, s11, s7 +8001272c: b3 89 bd 00 add s3, s11, a1 +80012730: 33 07 c7 00 add a4, a4, a2 +80012734: 33 36 c7 00 sltu a2, a4, a2 +80012738: 33 8c 59 00 add s8, s3, t0 +8001273c: 33 07 a7 00 add a4, a4, a0 +80012740: 13 8b 09 00 mv s6, s3 +80012744: b3 09 cc 00 add s3, s8, a2 +80012748: 23 28 e1 06 sw a4, 112(sp) +8001274c: 33 37 a7 00 sltu a4, a4, a0 +80012750: 33 85 c9 01 add a0, s3, t3 +80012754: b3 0c e5 00 add s9, a0, a4 +80012758: 23 28 31 01 sw s3, 16(sp) +8001275c: b3 89 dc 00 add s3, s9, a3 +80012760: b3 b6 d9 00 sltu a3, s3, a3 +80012764: 23 2a 31 01 sw s3, 20(sp) +80012768: 83 29 01 01 lw s3, 16(sp) +8001276c: b3 bb 7d 01 sltu s7, s11, s7 +80012770: b3 35 bb 00 sltu a1, s6, a1 +80012774: 33 b6 c9 00 sltu a2, s3, a2 +80012778: b3 32 5c 00 sltu t0, s8, t0 +8001277c: b3 e2 c2 00 or t0, t0, a2 +80012780: 33 b7 ec 00 sltu a4, s9, a4 +80012784: b3 e5 bb 00 or a1, s7, a1 +80012788: 33 35 c5 01 sltu a0, a0, t3 +8001278c: 33 65 e5 00 or a0, a0, a4 +80012790: b3 85 55 00 add a1, a1, t0 +80012794: b3 85 a5 00 add a1, a1, a0 +80012798: b3 85 e5 01 add a1, a1, t5 +8001279c: 33 86 d5 00 add a2, a1, a3 +800127a0: 33 bf e5 01 sltu t5, a1, t5 +800127a4: 83 25 41 01 lw a1, 20(sp) +800127a8: b3 36 d6 00 sltu a3, a2, a3 +800127ac: b3 66 df 00 or a3, t5, a3 +800127b0: 33 87 d5 01 add a4, a1, t4 +800127b4: b3 85 a3 03 mul a1, t2, s10 +800127b8: 33 0f f6 01 add t5, a2, t6 +800127bc: 23 2a e1 06 sw a4, 116(sp) +800127c0: 33 37 d7 01 sltu a4, a4, t4 +800127c4: 33 06 ef 00 add a2, t5, a4 +800127c8: 33 37 e6 00 sltu a4, a2, a4 +800127cc: 33 3f ff 01 sltu t5, t5, t6 +800127d0: 33 6f ef 00 or t5, t5, a4 +800127d4: 33 0d a8 03 mul s10, a6, s10 +800127d8: 13 d7 05 01 srli a4, a1, 16 +800127dc: b3 83 78 02 mul t2, a7, t2 +800127e0: b3 83 a3 01 add t2, t2, s10 +800127e4: 33 88 08 03 mul a6, a7, a6 +800127e8: b3 08 77 00 add a7, a4, t2 +800127ec: 63 f6 a8 01 bgeu a7, s10, 12 +800127f0: 37 07 01 00 lui a4, 16 +800127f4: 33 08 e8 00 add a6, a6, a4 +800127f8: 33 f7 68 00 and a4, a7, t1 +800127fc: 13 17 07 01 slli a4, a4, 16 +80012800: 33 f3 65 00 and t1, a1, t1 +80012804: 93 d8 08 01 srli a7, a7, 16 +80012808: 33 03 67 00 add t1, a4, t1 +8001280c: b3 88 d8 00 add a7, a7, a3 +80012810: 03 27 c1 00 lw a4, 12(sp) +80012814: 83 26 01 00 lw a3, 0(sp) +80012818: 33 06 66 00 add a2, a2, t1 +8001281c: b3 88 e8 01 add a7, a7, t5 +80012820: 33 33 66 00 sltu t1, a2, t1 +80012824: b3 69 d7 00 or s3, a4, a3 +80012828: b3 88 68 00 add a7, a7, t1 +8001282c: 33 88 08 01 add a6, a7, a6 +80012830: 33 6a 3a 01 or s4, s4, s3 +80012834: 93 9a da 00 slli s5, s5, 13 +80012838: 23 2e 01 07 sw a6, 124(sp) +8001283c: 23 2c c1 06 sw a2, 120(sp) +80012840: 33 ea 4a 01 or s4, s5, s4 +80012844: 13 07 01 06 addi a4, sp, 96 +80012848: 93 05 01 07 addi a1, sp, 112 +8001284c: 83 26 c7 00 lw a3, 12(a4) +80012850: 03 26 07 01 lw a2, 16(a4) +80012854: 13 07 47 00 addi a4, a4, 4 +80012858: 93 d6 36 01 srli a3, a3, 19 +8001285c: 13 16 d6 00 slli a2, a2, 13 +80012860: b3 e6 c6 00 or a3, a3, a2 +80012864: 23 2e d7 fe sw a3, -4(a4) +80012868: e3 92 e5 fe bne a1, a4, -28 +8001286c: 83 26 81 06 lw a3, 104(sp) +80012870: 83 2a 01 06 lw s5, 96(sp) +80012874: 03 27 c1 06 lw a4, 108(sp) +80012878: 23 2c d1 04 sw a3, 88(sp) +8001287c: 83 26 41 06 lw a3, 100(sp) +80012880: 33 3a 40 01 snez s4, s4 +80012884: 33 6a 5a 01 or s4, s4, s5 +80012888: 23 2a d1 04 sw a3, 84(sp) +8001288c: 23 2e e1 04 sw a4, 92(sp) +80012890: 23 28 41 05 sw s4, 80(sp) +80012894: 93 16 b7 00 slli a3, a4, 11 +80012898: 63 d4 06 14 bgez a3, 328 +8001289c: 13 1a fa 01 slli s4, s4, 31 +800128a0: 13 07 01 05 addi a4, sp, 80 +800128a4: 93 05 c1 05 addi a1, sp, 92 +800128a8: 83 26 07 00 lw a3, 0(a4) +800128ac: 03 26 47 00 lw a2, 4(a4) +800128b0: 13 07 47 00 addi a4, a4, 4 +800128b4: 93 d6 16 00 srli a3, a3, 1 +800128b8: 13 16 f6 01 slli a2, a2, 31 +800128bc: b3 e6 c6 00 or a3, a3, a2 +800128c0: 23 2e d7 fe sw a3, -4(a4) +800128c4: e3 92 e5 fe bne a1, a4, -28 +800128c8: 03 27 c1 05 lw a4, 92(sp) +800128cc: 33 3a 40 01 snez s4, s4 +800128d0: 13 57 17 00 srli a4, a4, 1 +800128d4: 23 2e e1 04 sw a4, 92(sp) +800128d8: 03 27 01 05 lw a4, 80(sp) +800128dc: 33 6a 47 01 or s4, a4, s4 +800128e0: 23 28 41 05 sw s4, 80(sp) +800128e4: 03 27 41 00 lw a4, 4(sp) +800128e8: b7 46 00 00 lui a3, 4 +800128ec: 93 86 f6 ff addi a3, a3, -1 +800128f0: b3 06 d7 00 add a3, a4, a3 +800128f4: 63 50 d0 26 blez a3, 608 +800128f8: 03 27 01 05 lw a4, 80(sp) +800128fc: 13 76 77 00 andi a2, a4, 7 +80012900: 63 02 06 10 beqz a2, 260 +80012904: 13 05 20 00 addi a0, zero, 2 +80012908: 03 26 41 05 lw a2, 84(sp) +8001290c: 83 25 c1 05 lw a1, 92(sp) +80012910: 13 64 14 00 ori s0, s0, 1 +80012914: 63 86 a4 0e beq s1, a0, 236 +80012918: 13 05 30 00 addi a0, zero, 3 +8001291c: 63 88 a4 0c beq s1, a0, 208 +80012920: 63 92 04 0e bnez s1, 228 +80012924: 13 75 f7 00 andi a0, a4, 15 +80012928: 13 08 40 00 addi a6, zero, 4 +8001292c: 63 0c 05 0d beq a0, a6, 216 +80012930: 13 07 47 00 addi a4, a4, 4 +80012934: 23 28 e1 04 sw a4, 80(sp) +80012938: 13 37 47 00 sltiu a4, a4, 4 +8001293c: 33 06 c7 00 add a2, a4, a2 +80012940: 33 37 e6 00 sltu a4, a2, a4 +80012944: 23 2a c1 04 sw a2, 84(sp) +80012948: 03 26 81 05 lw a2, 88(sp) +8001294c: 33 06 c7 00 add a2, a4, a2 +80012950: 33 37 e6 00 sltu a4, a2, a4 +80012954: 33 07 b7 00 add a4, a4, a1 +80012958: 23 2c c1 04 sw a2, 88(sp) +8001295c: 23 2e e1 04 sw a4, 92(sp) +80012960: 6f 00 40 0a j 164 +80012964: 93 87 0a 00 mv a5, s5 +80012968: 03 27 01 03 lw a4, 48(sp) +8001296c: 23 28 e1 04 sw a4, 80(sp) +80012970: 03 27 41 03 lw a4, 52(sp) +80012974: 23 2a e1 04 sw a4, 84(sp) +80012978: 03 27 81 03 lw a4, 56(sp) +8001297c: 23 2c e1 04 sw a4, 88(sp) +80012980: 03 27 c1 03 lw a4, 60(sp) +80012984: 23 2e e1 04 sw a4, 92(sp) +80012988: 13 07 20 00 addi a4, zero, 2 +8001298c: 63 86 eb 54 beq s7, a4, 1356 +80012990: 13 07 30 00 addi a4, zero, 3 +80012994: 63 82 eb f2 beq s7, a4, -2268 +80012998: 13 07 10 00 addi a4, zero, 1 +8001299c: e3 94 eb f4 bne s7, a4, -184 +800129a0: 23 2e 01 04 sw zero, 92(sp) +800129a4: 23 2c 01 04 sw zero, 88(sp) +800129a8: 23 2a 01 04 sw zero, 84(sp) +800129ac: 23 28 01 04 sw zero, 80(sp) +800129b0: 6f 00 80 50 j 1288 +800129b4: 93 07 0a 00 mv a5, s4 +800129b8: 03 27 01 04 lw a4, 64(sp) +800129bc: 93 8b 06 00 mv s7, a3 +800129c0: 23 28 e1 04 sw a4, 80(sp) +800129c4: 03 27 41 04 lw a4, 68(sp) +800129c8: 23 2a e1 04 sw a4, 84(sp) +800129cc: 03 27 81 04 lw a4, 72(sp) +800129d0: 23 2c e1 04 sw a4, 88(sp) +800129d4: 03 27 c1 04 lw a4, 76(sp) +800129d8: 23 2e e1 04 sw a4, 92(sp) +800129dc: 6f f0 df fa j -84 +800129e0: 03 27 81 00 lw a4, 8(sp) +800129e4: 23 22 e1 00 sw a4, 4(sp) +800129e8: 6f f0 df ef j -260 +800129ec: 63 9c 07 00 bnez a5, 24 +800129f0: 13 07 87 00 addi a4, a4, 8 +800129f4: 23 28 e1 04 sw a4, 80(sp) +800129f8: 13 37 87 00 sltiu a4, a4, 8 +800129fc: 6f f0 1f f4 j -192 +80012a00: e3 98 07 fe bnez a5, -16 +80012a04: 03 27 c1 05 lw a4, 92(sp) +80012a08: 13 16 b7 00 slli a2, a4, 11 +80012a0c: 63 50 06 02 bgez a2, 32 +80012a10: b7 06 f0 ff lui a3, 1048320 +80012a14: 93 86 f6 ff addi a3, a3, -1 +80012a18: 33 77 d7 00 and a4, a4, a3 +80012a1c: 23 2e e1 04 sw a4, 92(sp) +80012a20: 03 27 41 00 lw a4, 4(sp) +80012a24: b7 46 00 00 lui a3, 4 +80012a28: b3 06 d7 00 add a3, a4, a3 +80012a2c: 13 07 01 05 addi a4, sp, 80 +80012a30: 13 05 c1 05 addi a0, sp, 92 +80012a34: 03 26 07 00 lw a2, 0(a4) +80012a38: 83 25 47 00 lw a1, 4(a4) +80012a3c: 13 07 47 00 addi a4, a4, 4 +80012a40: 13 56 36 00 srli a2, a2, 3 +80012a44: 93 95 d5 01 slli a1, a1, 29 +80012a48: 33 66 b6 00 or a2, a2, a1 +80012a4c: 23 2e c7 fe sw a2, -4(a4) +80012a50: e3 12 e5 fe bne a0, a4, -28 +80012a54: 37 87 00 00 lui a4, 8 +80012a58: 13 07 e7 ff addi a4, a4, -2 +80012a5c: 63 4c d7 08 blt a4, a3, 152 +80012a60: 03 27 c1 05 lw a4, 92(sp) +80012a64: 13 57 37 00 srli a4, a4, 3 +80012a68: 23 2e e1 04 sw a4, 92(sp) +80012a6c: 13 87 06 00 mv a4, a3 +80012a70: 03 25 c1 05 lw a0, 92(sp) +80012a74: 13 17 17 01 slli a4, a4, 17 +80012a78: 93 97 f7 00 slli a5, a5, 15 +80012a7c: 13 57 17 01 srli a4, a4, 17 +80012a80: 33 e7 e7 00 or a4, a5, a4 +80012a84: 23 16 a1 06 sh a0, 108(sp) +80012a88: 23 17 e1 06 sh a4, 110(sp) +80012a8c: 83 25 01 05 lw a1, 80(sp) +80012a90: 03 26 41 05 lw a2, 84(sp) +80012a94: 83 26 81 05 lw a3, 88(sp) +80012a98: 83 27 c1 06 lw a5, 108(sp) +80012a9c: 63 04 04 00 beqz s0, 8 +80012aa0: 73 20 14 00 csrs fflags, s0 +80012aa4: 83 20 c1 0b lw ra, 188(sp) +80012aa8: 03 24 81 0b lw s0, 184(sp) +80012aac: 23 20 b9 00 sw a1, 0(s2) +80012ab0: 23 22 c9 00 sw a2, 4(s2) +80012ab4: 23 24 d9 00 sw a3, 8(s2) +80012ab8: 23 26 f9 00 sw a5, 12(s2) +80012abc: 83 24 41 0b lw s1, 180(sp) +80012ac0: 83 29 c1 0a lw s3, 172(sp) +80012ac4: 03 2a 81 0a lw s4, 168(sp) +80012ac8: 83 2a 41 0a lw s5, 164(sp) +80012acc: 03 2b 01 0a lw s6, 160(sp) +80012ad0: 83 2b c1 09 lw s7, 156(sp) +80012ad4: 03 2c 81 09 lw s8, 152(sp) +80012ad8: 83 2c 41 09 lw s9, 148(sp) +80012adc: 03 2d 01 09 lw s10, 144(sp) +80012ae0: 83 2d c1 08 lw s11, 140(sp) +80012ae4: 13 05 09 00 mv a0, s2 +80012ae8: 03 29 01 0b lw s2, 176(sp) +80012aec: 13 01 01 0c addi sp, sp, 192 +80012af0: 67 80 00 00 ret +80012af4: 13 07 20 00 addi a4, zero, 2 +80012af8: 63 8a e4 04 beq s1, a4, 84 +80012afc: 13 07 30 00 addi a4, zero, 3 +80012b00: 63 84 e4 02 beq s1, a4, 40 +80012b04: 63 94 04 02 bnez s1, 40 +80012b08: 37 87 00 00 lui a4, 8 +80012b0c: 23 2e 01 04 sw zero, 92(sp) +80012b10: 23 2c 01 04 sw zero, 88(sp) +80012b14: 23 2a 01 04 sw zero, 84(sp) +80012b18: 23 28 01 04 sw zero, 80(sp) +80012b1c: 13 07 f7 ff addi a4, a4, -1 +80012b20: 13 64 54 00 ori s0, s0, 5 +80012b24: 6f f0 df f4 j -180 +80012b28: e3 80 07 fe beqz a5, -32 +80012b2c: 13 07 f0 ff addi a4, zero, -1 +80012b30: 23 2e e1 04 sw a4, 92(sp) +80012b34: 23 2c e1 04 sw a4, 88(sp) +80012b38: 23 2a e1 04 sw a4, 84(sp) +80012b3c: 23 28 e1 04 sw a4, 80(sp) +80012b40: 37 87 00 00 lui a4, 8 +80012b44: 13 07 e7 ff addi a4, a4, -2 +80012b48: 6f f0 9f fd j -40 +80012b4c: e3 80 07 fe beqz a5, -32 +80012b50: 6f f0 9f fb j -72 +80012b54: 13 07 10 00 addi a4, zero, 1 +80012b58: 63 90 06 08 bnez a3, 128 +80012b5c: 03 26 01 05 lw a2, 80(sp) +80012b60: 83 25 41 05 lw a1, 84(sp) +80012b64: 03 25 81 05 lw a0, 88(sp) +80012b68: 13 78 76 00 andi a6, a2, 7 +80012b6c: 03 27 c1 05 lw a4, 92(sp) +80012b70: 63 0e 08 04 beqz a6, 92 +80012b74: 13 08 20 00 addi a6, zero, 2 +80012b78: 13 64 14 00 ori s0, s0, 1 +80012b7c: 63 86 04 05 beq s1, a6, 76 +80012b80: 13 08 30 00 addi a6, zero, 3 +80012b84: 63 8a 04 03 beq s1, a6, 52 +80012b88: 63 92 04 04 bnez s1, 68 +80012b8c: 13 78 f6 00 andi a6, a2, 15 +80012b90: 93 08 40 00 addi a7, zero, 4 +80012b94: 63 0c 18 03 beq a6, a7, 56 +80012b98: 13 06 46 00 addi a2, a2, 4 +80012b9c: 13 36 46 00 sltiu a2, a2, 4 +80012ba0: b3 85 c5 00 add a1, a1, a2 +80012ba4: 33 b6 c5 00 sltu a2, a1, a2 +80012ba8: 33 05 c5 00 add a0, a0, a2 +80012bac: 33 36 c5 00 sltu a2, a0, a2 +80012bb0: 33 07 c7 00 add a4, a4, a2 +80012bb4: 6f 00 80 01 j 24 +80012bb8: 63 9a 07 00 bnez a5, 20 +80012bbc: 13 06 86 00 addi a2, a2, 8 +80012bc0: 13 36 86 00 sltiu a2, a2, 8 +80012bc4: 6f f0 df fd j -36 +80012bc8: e3 9a 07 fe bnez a5, -12 +80012bcc: 13 57 47 01 srli a4, a4, 20 +80012bd0: 13 47 17 00 xori a4, a4, 1 +80012bd4: 13 77 17 00 andi a4, a4, 1 +80012bd8: 93 05 10 00 addi a1, zero, 1 +80012bdc: 33 86 d5 40 sub a2, a1, a3 +80012be0: 93 06 40 07 addi a3, zero, 116 +80012be4: 63 cc c6 26 blt a3, a2, 632 +80012be8: 93 58 56 40 srai a7, a2, 5 +80012bec: 93 06 00 00 mv a3, zero +80012bf0: 93 05 00 00 mv a1, zero +80012bf4: 63 98 15 05 bne a1, a7, 80 +80012bf8: 13 76 f6 01 andi a2, a2, 31 +80012bfc: 13 98 28 00 slli a6, a7, 2 +80012c00: 63 10 06 06 bnez a2, 96 +80012c04: 13 05 30 00 addi a0, zero, 3 +80012c08: 13 06 01 05 addi a2, sp, 80 +80012c0c: 93 05 00 00 mv a1, zero +80012c10: 33 05 15 41 sub a0, a0, a7 +80012c14: 33 03 06 01 add t1, a2, a6 +80012c18: 03 23 03 00 lw t1, 0(t1) +80012c1c: 93 85 15 00 addi a1, a1, 1 +80012c20: 13 06 46 00 addi a2, a2, 4 +80012c24: 23 2e 66 fe sw t1, -4(a2) +80012c28: e3 56 b5 fe bge a0, a1, -20 +80012c2c: 93 05 40 00 addi a1, zero, 4 +80012c30: b3 88 15 41 sub a7, a1, a7 +80012c34: 93 05 10 00 addi a1, zero, 1 +80012c38: 63 50 10 09 blez a7, 128 +80012c3c: 93 85 08 00 mv a1, a7 +80012c40: 6f 00 80 07 j 120 +80012c44: 13 95 25 00 slli a0, a1, 2 +80012c48: 13 08 01 05 addi a6, sp, 80 +80012c4c: 33 05 a8 00 add a0, a6, a0 +80012c50: 03 25 05 00 lw a0, 0(a0) +80012c54: 93 85 15 00 addi a1, a1, 1 +80012c58: b3 e6 a6 00 or a3, a3, a0 +80012c5c: 6f f0 9f f9 j -104 +80012c60: 93 05 01 08 addi a1, sp, 128 +80012c64: b3 85 05 01 add a1, a1, a6 +80012c68: 83 a5 05 fd lw a1, -48(a1) +80012c6c: 13 0e 00 02 addi t3, zero, 32 +80012c70: 33 0e ce 40 sub t3, t3, a2 +80012c74: b3 95 c5 01 sll a1, a1, t3 +80012c78: b3 e6 b6 00 or a3, a3, a1 +80012c7c: 13 05 30 00 addi a0, zero, 3 +80012c80: 93 05 01 05 addi a1, sp, 80 +80012c84: 33 88 05 01 add a6, a1, a6 +80012c88: 13 03 00 00 mv t1, zero +80012c8c: 33 05 15 41 sub a0, a0, a7 +80012c90: 13 08 48 00 addi a6, a6, 4 +80012c94: 63 46 a3 02 blt t1, a0, 44 +80012c98: 13 08 01 08 addi a6, sp, 128 +80012c9c: 13 15 25 00 slli a0, a0, 2 +80012ca0: 33 05 a8 00 add a0, a6, a0 +80012ca4: 03 28 c1 05 lw a6, 92(sp) +80012ca8: 93 05 40 00 addi a1, zero, 4 +80012cac: b3 85 15 41 sub a1, a1, a7 +80012cb0: 33 56 c8 00 srl a2, a6, a2 +80012cb4: 23 28 c5 fc sw a2, -48(a0) +80012cb8: 13 05 40 00 addi a0, zero, 4 +80012cbc: 6f 00 40 04 j 68 +80012cc0: 93 1e 23 00 slli t4, t1, 2 +80012cc4: 93 05 01 05 addi a1, sp, 80 +80012cc8: 03 2f 08 00 lw t5, 0(a6) +80012ccc: b3 8e d5 01 add t4, a1, t4 +80012cd0: 83 25 c8 ff lw a1, -4(a6) +80012cd4: 33 1f cf 01 sll t5, t5, t3 +80012cd8: 13 03 13 00 addi t1, t1, 1 +80012cdc: b3 d5 c5 00 srl a1, a1, a2 +80012ce0: b3 e5 e5 01 or a1, a1, t5 +80012ce4: 23 a0 be 00 sw a1, 0(t4) +80012ce8: 6f f0 9f fa j -88 +80012cec: 13 96 25 00 slli a2, a1, 2 +80012cf0: 13 08 01 05 addi a6, sp, 80 +80012cf4: 33 06 c8 00 add a2, a6, a2 +80012cf8: 23 20 06 00 sw zero, 0(a2) +80012cfc: 93 85 15 00 addi a1, a1, 1 +80012d00: e3 96 a5 fe bne a1, a0, -20 +80012d04: 03 26 01 05 lw a2, 80(sp) +80012d08: b3 36 d0 00 snez a3, a3 +80012d0c: b3 e6 c6 00 or a3, a3, a2 +80012d10: 23 28 d1 04 sw a3, 80(sp) +80012d14: 13 f6 76 00 andi a2, a3, 7 +80012d18: 63 0e 06 04 beqz a2, 92 +80012d1c: 13 06 20 00 addi a2, zero, 2 +80012d20: 03 28 c1 05 lw a6, 92(sp) +80012d24: 13 64 14 00 ori s0, s0, 1 +80012d28: 63 88 c4 0a beq s1, a2, 176 +80012d2c: 13 06 30 00 addi a2, zero, 3 +80012d30: 63 88 c4 06 beq s1, a2, 112 +80012d34: 63 90 04 04 bnez s1, 64 +80012d38: 13 f6 f6 00 andi a2, a3, 15 +80012d3c: 63 0c b6 02 beq a2, a1, 56 +80012d40: 03 25 41 05 lw a0, 84(sp) +80012d44: 93 86 46 00 addi a3, a3, 4 +80012d48: 23 28 d1 04 sw a3, 80(sp) +80012d4c: 93 b6 46 00 sltiu a3, a3, 4 +80012d50: 33 85 a6 00 add a0, a3, a0 +80012d54: b3 36 d5 00 sltu a3, a0, a3 +80012d58: 23 2a a1 04 sw a0, 84(sp) +80012d5c: 03 25 81 05 lw a0, 88(sp) +80012d60: 33 85 a6 00 add a0, a3, a0 +80012d64: 23 2c a1 04 sw a0, 88(sp) +80012d68: 33 35 d5 00 sltu a0, a0, a3 +80012d6c: 33 06 05 01 add a2, a0, a6 +80012d70: 23 2e c1 04 sw a2, 92(sp) +80012d74: 83 26 c1 05 lw a3, 92(sp) +80012d78: 13 96 c6 00 slli a2, a3, 12 +80012d7c: 63 5a 06 08 bgez a2, 148 +80012d80: 23 2e 01 04 sw zero, 92(sp) +80012d84: 23 2c 01 04 sw zero, 88(sp) +80012d88: 23 2a 01 04 sw zero, 84(sp) +80012d8c: 23 28 01 04 sw zero, 80(sp) +80012d90: 13 64 14 00 ori s0, s0, 1 +80012d94: 63 10 07 0c bnez a4, 192 +80012d98: 13 07 10 00 addi a4, zero, 1 +80012d9c: 6f f0 5f cd j -812 +80012da0: e3 9a 07 fc bnez a5, -44 +80012da4: 83 25 41 05 lw a1, 84(sp) +80012da8: 93 86 86 00 addi a3, a3, 8 +80012dac: 23 28 d1 04 sw a3, 80(sp) +80012db0: 93 b6 86 00 sltiu a3, a3, 8 +80012db4: b3 85 b6 00 add a1, a3, a1 +80012db8: b3 b6 d5 00 sltu a3, a1, a3 +80012dbc: 23 2a b1 04 sw a1, 84(sp) +80012dc0: 83 25 81 05 lw a1, 88(sp) +80012dc4: b3 85 b6 00 add a1, a3, a1 +80012dc8: 23 2c b1 04 sw a1, 88(sp) +80012dcc: b3 b5 d5 00 sltu a1, a1, a3 +80012dd0: 33 86 05 01 add a2, a1, a6 +80012dd4: 6f f0 df f9 j -100 +80012dd8: e3 8e 07 f8 beqz a5, -100 +80012ddc: 03 26 41 05 lw a2, 84(sp) +80012de0: 93 86 86 00 addi a3, a3, 8 +80012de4: 83 25 81 05 lw a1, 88(sp) +80012de8: 23 28 d1 04 sw a3, 80(sp) +80012dec: 93 b6 86 00 sltiu a3, a3, 8 +80012df0: 33 86 c6 00 add a2, a3, a2 +80012df4: b3 36 d6 00 sltu a3, a2, a3 +80012df8: 23 2a c1 04 sw a2, 84(sp) +80012dfc: 33 86 b6 00 add a2, a3, a1 +80012e00: 23 2c c1 04 sw a2, 88(sp) +80012e04: 33 36 d6 00 sltu a2, a2, a3 +80012e08: 33 06 06 01 add a2, a2, a6 +80012e0c: 6f f0 5f f6 j -156 +80012e10: 93 06 01 05 addi a3, sp, 80 +80012e14: 13 05 c1 05 addi a0, sp, 92 +80012e18: 03 a6 06 00 lw a2, 0(a3) +80012e1c: 83 a5 46 00 lw a1, 4(a3) +80012e20: 93 86 46 00 addi a3, a3, 4 +80012e24: 13 56 36 00 srli a2, a2, 3 +80012e28: 93 95 d5 01 slli a1, a1, 29 +80012e2c: 33 66 b6 00 or a2, a2, a1 +80012e30: 23 ae c6 fe sw a2, -4(a3) +80012e34: e3 12 d5 fe bne a0, a3, -28 +80012e38: 83 26 c1 05 lw a3, 92(sp) +80012e3c: 93 d6 36 00 srli a3, a3, 3 +80012e40: 23 2e d1 04 sw a3, 92(sp) +80012e44: e3 06 07 c2 beqz a4, -980 +80012e48: 13 77 14 00 andi a4, s0, 1 +80012e4c: e3 02 07 c2 beqz a4, -988 +80012e50: 13 07 00 00 mv a4, zero +80012e54: 13 64 24 00 ori s0, s0, 2 +80012e58: 6f f0 9f c1 j -1000 +80012e5c: 83 26 41 05 lw a3, 84(sp) +80012e60: 03 27 01 05 lw a4, 80(sp) +80012e64: 33 67 d7 00 or a4, a4, a3 +80012e68: 83 26 81 05 lw a3, 88(sp) +80012e6c: 33 67 d7 00 or a4, a4, a3 +80012e70: 83 26 c1 05 lw a3, 92(sp) +80012e74: 33 67 d7 00 or a4, a4, a3 +80012e78: 63 0e 07 02 beqz a4, 60 +80012e7c: 23 2e 01 04 sw zero, 92(sp) +80012e80: 23 2c 01 04 sw zero, 88(sp) +80012e84: 23 2a 01 04 sw zero, 84(sp) +80012e88: 23 28 b1 04 sw a1, 80(sp) +80012e8c: 13 07 20 00 addi a4, zero, 2 +80012e90: 13 64 14 00 ori s0, s0, 1 +80012e94: 63 8e e4 02 beq s1, a4, 60 +80012e98: 13 07 30 00 addi a4, zero, 3 +80012e9c: 63 82 e4 02 beq s1, a4, 36 +80012ea0: 13 07 50 00 addi a4, zero, 5 +80012ea4: 63 82 04 02 beqz s1, 36 +80012ea8: 03 27 01 05 lw a4, 80(sp) +80012eac: 13 57 37 00 srli a4, a4, 3 +80012eb0: 23 28 e1 04 sw a4, 80(sp) +80012eb4: 13 64 24 00 ori s0, s0, 2 +80012eb8: 13 07 00 00 mv a4, zero +80012ebc: 6f f0 5f bb j -1100 +80012ec0: e3 94 07 fe bnez a5, -24 +80012ec4: 13 07 90 00 addi a4, zero, 9 +80012ec8: 23 28 e1 04 sw a4, 80(sp) +80012ecc: 6f f0 df fd j -36 +80012ed0: e3 9a 07 fe bnez a5, -12 +80012ed4: 6f f0 5f fd j -44 +80012ed8: 37 87 00 00 lui a4, 8 +80012edc: 23 2e 01 04 sw zero, 92(sp) +80012ee0: 23 2c 01 04 sw zero, 88(sp) +80012ee4: 23 2a 01 04 sw zero, 84(sp) +80012ee8: 23 28 01 04 sw zero, 80(sp) +80012eec: 13 07 f7 ff addi a4, a4, -1 +80012ef0: 6f f0 1f b8 j -1152 + +80012ef4 __subtf3: +80012ef4: 13 01 01 f9 addi sp, sp, -112 +80012ef8: 83 a6 05 00 lw a3, 0(a1) +80012efc: 03 a7 45 00 lw a4, 4(a1) +80012f00: 83 a7 85 00 lw a5, 8(a1) +80012f04: 23 22 91 06 sw s1, 100(sp) +80012f08: 23 20 21 07 sw s2, 96(sp) +80012f0c: 83 a4 c5 00 lw s1, 12(a1) +80012f10: 13 09 05 00 mv s2, a0 +80012f14: 23 26 11 06 sw ra, 108(sp) +80012f18: 23 24 81 06 sw s0, 104(sp) +80012f1c: 23 2e 31 05 sw s3, 92(sp) +80012f20: 23 2c 41 05 sw s4, 88(sp) +80012f24: 23 2a 51 05 sw s5, 84(sp) +80012f28: 23 28 61 05 sw s6, 80(sp) +80012f2c: 23 26 71 05 sw s7, 76(sp) +80012f30: 83 28 06 00 lw a7, 0(a2) +80012f34: 03 25 46 00 lw a0, 4(a2) +80012f38: 83 25 86 00 lw a1, 8(a2) +80012f3c: 83 2e c6 00 lw t4, 12(a2) +80012f40: f3 29 20 00 frrm s3 +80012f44: 23 2c f1 02 sw a5, 56(sp) +80012f48: 23 24 f1 00 sw a5, 8(sp) +80012f4c: 93 97 04 01 slli a5, s1, 16 +80012f50: 13 94 14 00 slli s0, s1, 1 +80012f54: 93 d7 07 01 srli a5, a5, 16 +80012f58: 23 2e 91 02 sw s1, 60(sp) +80012f5c: 23 28 d1 02 sw a3, 48(sp) +80012f60: 23 2a e1 02 sw a4, 52(sp) +80012f64: 23 20 d1 00 sw a3, 0(sp) +80012f68: 23 22 e1 00 sw a4, 4(sp) +80012f6c: 23 26 f1 00 sw a5, 12(sp) +80012f70: 13 54 14 01 srli s0, s0, 17 +80012f74: 93 d4 f4 01 srli s1, s1, 31 +80012f78: 93 0f 01 00 mv t6, sp +80012f7c: 13 08 c1 00 addi a6, sp, 12 +80012f80: 83 27 08 00 lw a5, 0(a6) +80012f84: 03 27 c8 ff lw a4, -4(a6) +80012f88: 13 08 c8 ff addi a6, a6, -4 +80012f8c: 93 97 37 00 slli a5, a5, 3 +80012f90: 13 57 d7 01 srli a4, a4, 29 +80012f94: b3 e7 e7 00 or a5, a5, a4 +80012f98: 23 22 f8 00 sw a5, 4(a6) +80012f9c: e3 92 0f ff bne t6, a6, -28 +80012fa0: 83 26 01 00 lw a3, 0(sp) +80012fa4: 93 97 0e 01 slli a5, t4, 16 +80012fa8: 13 9e 1e 00 slli t3, t4, 1 +80012fac: 93 96 36 00 slli a3, a3, 3 +80012fb0: 93 d7 07 01 srli a5, a5, 16 +80012fb4: 23 2e d1 03 sw t4, 60(sp) +80012fb8: 23 20 d1 00 sw a3, 0(sp) +80012fbc: 23 28 11 03 sw a7, 48(sp) +80012fc0: 23 2a a1 02 sw a0, 52(sp) +80012fc4: 23 2c b1 02 sw a1, 56(sp) +80012fc8: 23 28 11 01 sw a7, 16(sp) +80012fcc: 23 2a a1 00 sw a0, 20(sp) +80012fd0: 23 2c b1 00 sw a1, 24(sp) +80012fd4: 23 2e f1 00 sw a5, 28(sp) +80012fd8: 13 5e 1e 01 srli t3, t3, 17 +80012fdc: 93 de fe 01 srli t4, t4, 31 +80012fe0: 13 0f 01 01 addi t5, sp, 16 +80012fe4: 13 06 c1 01 addi a2, sp, 28 +80012fe8: 83 27 06 00 lw a5, 0(a2) +80012fec: 03 27 c6 ff lw a4, -4(a2) +80012ff0: 13 06 c6 ff addi a2, a2, -4 +80012ff4: 93 97 37 00 slli a5, a5, 3 +80012ff8: 13 57 d7 01 srli a4, a4, 29 +80012ffc: b3 e7 e7 00 or a5, a5, a4 +80013000: 23 22 f6 00 sw a5, 4(a2) +80013004: e3 12 cf fe bne t5, a2, -28 +80013008: 03 27 01 01 lw a4, 16(sp) +8001300c: b7 87 00 00 lui a5, 8 +80013010: 93 87 f7 ff addi a5, a5, -1 +80013014: 13 17 37 00 slli a4, a4, 3 +80013018: 23 28 e1 00 sw a4, 16(sp) +8001301c: 63 10 fe 02 bne t3, a5, 32 +80013020: 83 25 81 01 lw a1, 24(sp) +80013024: 83 27 41 01 lw a5, 20(sp) +80013028: b3 e7 b7 00 or a5, a5, a1 +8001302c: 83 25 c1 01 lw a1, 28(sp) +80013030: b3 e7 b7 00 or a5, a5, a1 +80013034: b3 e7 e7 00 or a5, a5, a4 +80013038: 63 94 07 00 bnez a5, 8 +8001303c: 93 ce 1e 00 xori t4, t4, 1 +80013040: b3 07 c4 41 sub a5, s0, t3 +80013044: e3 9e 9e 3a bne t4, s1, 3004 +80013048: 63 50 f0 3a blez a5, 928 +8001304c: 03 28 41 00 lw a6, 4(sp) +80013050: 83 28 81 00 lw a7, 8(sp) +80013054: 83 25 c1 00 lw a1, 12(sp) +80013058: 63 12 0e 10 bnez t3, 260 +8001305c: 83 2e 41 01 lw t4, 20(sp) +80013060: 03 25 81 01 lw a0, 24(sp) +80013064: 83 2f c1 01 lw t6, 28(sp) +80013068: 33 e3 ae 00 or t1, t4, a0 +8001306c: 33 63 f3 01 or t1, t1, t6 +80013070: 33 63 e3 00 or t1, t1, a4 +80013074: 63 12 03 04 bnez t1, 68 +80013078: 37 87 00 00 lui a4, 8 +8001307c: 13 07 f7 ff addi a4, a4, -1 +80013080: 63 90 e7 02 bne a5, a4, 32 +80013084: 33 67 18 01 or a4, a6, a7 +80013088: 33 67 b7 00 or a4, a4, a1 +8001308c: 33 67 d7 00 or a4, a4, a3 +80013090: 63 08 07 00 beqz a4, 16 +80013094: 13 97 d5 00 slli a4, a1, 13 +80013098: 63 44 07 00 bltz a4, 8 +8001309c: 13 0e 00 01 addi t3, zero, 16 +800130a0: 23 20 d1 02 sw a3, 32(sp) +800130a4: 23 22 01 03 sw a6, 36(sp) +800130a8: 23 24 11 03 sw a7, 40(sp) +800130ac: 23 26 b1 02 sw a1, 44(sp) +800130b0: 13 04 0e 00 mv s0, t3 +800130b4: 6f 00 00 0a j 160 +800130b8: 13 83 f7 ff addi t1, a5, -1 +800130bc: 63 1a 03 04 bnez t1, 84 +800130c0: 33 87 e6 00 add a4, a3, a4 +800130c4: b3 36 d7 00 sltu a3, a4, a3 +800130c8: 33 86 0e 01 add a2, t4, a6 +800130cc: b3 07 d6 00 add a5, a2, a3 +800130d0: b3 b6 d7 00 sltu a3, a5, a3 +800130d4: 33 38 06 01 sltu a6, a2, a6 +800130d8: 33 68 d8 00 or a6, a6, a3 +800130dc: 23 22 f1 02 sw a5, 36(sp) +800130e0: b3 07 15 01 add a5, a0, a7 +800130e4: 23 20 e1 02 sw a4, 32(sp) +800130e8: 33 87 07 01 add a4, a5, a6 +800130ec: 33 38 07 01 sltu a6, a4, a6 +800130f0: b3 b7 17 01 sltu a5, a5, a7 +800130f4: b3 e7 07 01 or a5, a5, a6 +800130f8: b3 85 bf 00 add a1, t6, a1 +800130fc: b3 85 b7 00 add a1, a5, a1 +80013100: 23 24 e1 02 sw a4, 40(sp) +80013104: 23 26 b1 02 sw a1, 44(sp) +80013108: 93 07 10 00 addi a5, zero, 1 +8001310c: 6f 00 00 23 j 560 +80013110: 37 87 00 00 lui a4, 8 +80013114: 13 07 f7 ff addi a4, a4, -1 +80013118: 63 84 e7 00 beq a5, a4, 8 +8001311c: 6f 10 10 00 j 6144 +80013120: 33 67 18 01 or a4, a6, a7 +80013124: 33 67 b7 00 or a4, a4, a1 +80013128: 33 67 d7 00 or a4, a4, a3 +8001312c: 13 04 00 00 mv s0, zero +80013130: 63 0a 07 00 beqz a4, 20 +80013134: 37 04 04 00 lui s0, 64 +80013138: 33 f4 85 00 and s0, a1, s0 +8001313c: 13 34 14 00 seqz s0, s0 +80013140: 13 14 44 00 slli s0, s0, 4 +80013144: 23 20 d1 02 sw a3, 32(sp) +80013148: 23 22 01 03 sw a6, 36(sp) +8001314c: 23 24 11 03 sw a7, 40(sp) +80013150: 23 26 b1 02 sw a1, 44(sp) +80013154: 13 08 00 00 mv a6, zero +80013158: 6f 00 00 74 j 1856 +8001315c: 37 87 00 00 lui a4, 8 +80013160: 13 07 f7 ff addi a4, a4, -1 +80013164: 63 12 e4 04 bne s0, a4, 68 +80013168: b3 67 18 01 or a5, a6, a7 +8001316c: b3 e7 b7 00 or a5, a5, a1 +80013170: b3 e7 d7 00 or a5, a5, a3 +80013174: 13 07 00 00 mv a4, zero +80013178: 63 8a 07 00 beqz a5, 20 +8001317c: 37 07 04 00 lui a4, 64 +80013180: 33 f7 e5 00 and a4, a1, a4 +80013184: 13 37 17 00 seqz a4, a4 +80013188: 13 17 47 00 slli a4, a4, 4 +8001318c: 23 20 d1 02 sw a3, 32(sp) +80013190: 23 22 01 03 sw a6, 36(sp) +80013194: 23 24 11 03 sw a7, 40(sp) +80013198: 23 26 b1 02 sw a1, 44(sp) +8001319c: 93 07 04 00 mv a5, s0 +800131a0: 13 04 07 00 mv s0, a4 +800131a4: 6f f0 1f fb j -80 +800131a8: 03 27 c1 01 lw a4, 28(sp) +800131ac: 37 05 08 00 lui a0, 128 +800131b0: 33 67 a7 00 or a4, a4, a0 +800131b4: 23 2e e1 00 sw a4, 28(sp) +800131b8: 13 07 40 07 addi a4, zero, 116 +800131bc: 63 54 f7 00 bge a4, a5, 8 +800131c0: 6f 10 80 76 j 5992 +800131c4: 13 83 07 00 mv t1, a5 +800131c8: 13 55 53 40 srai a0, t1, 5 +800131cc: 13 0e 00 00 mv t3, zero +800131d0: 93 07 00 00 mv a5, zero +800131d4: 63 96 a7 04 bne a5, a0, 76 +800131d8: 13 73 f3 01 andi t1, t1, 31 +800131dc: 13 17 25 00 slli a4, a0, 2 +800131e0: 63 1c 03 04 bnez t1, 88 +800131e4: 13 03 30 00 addi t1, zero, 3 +800131e8: 93 07 00 00 mv a5, zero +800131ec: 33 03 a3 40 sub t1, t1, a0 +800131f0: b3 0e e6 00 add t4, a2, a4 +800131f4: 83 ae 0e 00 lw t4, 0(t4) +800131f8: 93 87 17 00 addi a5, a5, 1 +800131fc: 13 06 46 00 addi a2, a2, 4 +80013200: 23 2e d6 ff sw t4, -4(a2) +80013204: e3 56 f3 fe bge t1, a5, -20 +80013208: 93 07 40 00 addi a5, zero, 4 +8001320c: 33 85 a7 40 sub a0, a5, a0 +80013210: 93 07 10 00 addi a5, zero, 1 +80013214: 63 5c a0 06 blez a0, 120 +80013218: 93 07 05 00 mv a5, a0 +8001321c: 6f 00 00 07 j 112 +80013220: 13 97 27 00 slli a4, a5, 2 +80013224: 33 07 ef 00 add a4, t5, a4 +80013228: 03 27 07 00 lw a4, 0(a4) +8001322c: 93 87 17 00 addi a5, a5, 1 +80013230: 33 6e ee 00 or t3, t3, a4 +80013234: 6f f0 1f fa j -96 +80013238: 93 07 01 04 addi a5, sp, 64 +8001323c: b3 87 e7 00 add a5, a5, a4 +80013240: 83 a7 07 fd lw a5, -48(a5) +80013244: 93 0f 00 02 addi t6, zero, 32 +80013248: b3 8f 6f 40 sub t6, t6, t1 +8001324c: b3 97 f7 01 sll a5, a5, t6 +80013250: 33 06 ef 00 add a2, t5, a4 +80013254: 13 07 30 00 addi a4, zero, 3 +80013258: 33 6e fe 00 or t3, t3, a5 +8001325c: 93 0e 00 00 mv t4, zero +80013260: 33 07 a7 40 sub a4, a4, a0 +80013264: 13 06 46 00 addi a2, a2, 4 +80013268: 63 c6 ee 02 blt t4, a4, 44 +8001326c: 13 06 01 04 addi a2, sp, 64 +80013270: 13 17 27 00 slli a4, a4, 2 +80013274: 33 07 e6 00 add a4, a2, a4 +80013278: 03 26 c1 01 lw a2, 28(sp) +8001327c: 93 07 40 00 addi a5, zero, 4 +80013280: b3 87 a7 40 sub a5, a5, a0 +80013284: 33 53 66 00 srl t1, a2, t1 +80013288: 23 28 67 fc sw t1, -48(a4) +8001328c: 13 06 40 00 addi a2, zero, 4 +80013290: 6f 00 c0 03 j 60 +80013294: 83 27 c6 ff lw a5, -4(a2) +80013298: 83 23 06 00 lw t2, 0(a2) +8001329c: 93 92 2e 00 slli t0, t4, 2 +800132a0: b3 d7 67 00 srl a5, a5, t1 +800132a4: b3 93 f3 01 sll t2, t2, t6 +800132a8: b3 02 5f 00 add t0, t5, t0 +800132ac: b3 e7 77 00 or a5, a5, t2 +800132b0: 23 a0 f2 00 sw a5, 0(t0) +800132b4: 93 8e 1e 00 addi t4, t4, 1 +800132b8: 6f f0 df fa j -84 +800132bc: 13 97 27 00 slli a4, a5, 2 +800132c0: 33 07 ef 00 add a4, t5, a4 +800132c4: 23 20 07 00 sw zero, 0(a4) +800132c8: 93 87 17 00 addi a5, a5, 1 +800132cc: e3 98 c7 fe bne a5, a2, -16 +800132d0: 03 27 01 01 lw a4, 16(sp) +800132d4: b3 37 c0 01 snez a5, t3 +800132d8: b3 67 f7 00 or a5, a4, a5 +800132dc: 23 28 f1 00 sw a5, 16(sp) +800132e0: 83 27 01 01 lw a5, 16(sp) +800132e4: 03 26 41 01 lw a2, 20(sp) +800132e8: b3 87 f6 00 add a5, a3, a5 +800132ec: b3 b6 d7 00 sltu a3, a5, a3 +800132f0: 33 06 c8 00 add a2, a6, a2 +800132f4: 23 20 f1 02 sw a5, 32(sp) +800132f8: b3 07 d6 00 add a5, a2, a3 +800132fc: b3 b6 d7 00 sltu a3, a5, a3 +80013300: 23 22 f1 02 sw a5, 36(sp) +80013304: 83 27 81 01 lw a5, 24(sp) +80013308: 33 38 06 01 sltu a6, a2, a6 +8001330c: 33 68 d8 00 or a6, a6, a3 +80013310: b3 87 f8 00 add a5, a7, a5 +80013314: 33 87 07 01 add a4, a5, a6 +80013318: b3 b7 17 01 sltu a5, a5, a7 +8001331c: 83 28 c1 01 lw a7, 28(sp) +80013320: 33 38 07 01 sltu a6, a4, a6 +80013324: b3 e7 07 01 or a5, a5, a6 +80013328: b3 85 15 01 add a1, a1, a7 +8001332c: b3 85 b7 00 add a1, a5, a1 +80013330: 23 24 e1 02 sw a4, 40(sp) +80013334: 23 26 b1 02 sw a1, 44(sp) +80013338: 93 07 04 00 mv a5, s0 +8001333c: 03 27 c1 02 lw a4, 44(sp) +80013340: 93 16 c7 00 slli a3, a4, 12 +80013344: 63 c4 06 00 bltz a3, 8 +80013348: 6f 10 40 4d j 5332 +8001334c: b7 06 f8 ff lui a3, 1048448 +80013350: 93 86 f6 ff addi a3, a3, -1 +80013354: 33 77 d7 00 and a4, a4, a3 +80013358: 23 26 e1 02 sw a4, 44(sp) +8001335c: 03 27 01 02 lw a4, 32(sp) +80013360: 93 87 17 00 addi a5, a5, 1 +80013364: 13 05 c1 02 addi a0, sp, 44 +80013368: 93 16 f7 01 slli a3, a4, 31 +8001336c: 13 07 01 02 addi a4, sp, 32 +80013370: 03 26 07 00 lw a2, 0(a4) +80013374: 83 25 47 00 lw a1, 4(a4) +80013378: 13 07 47 00 addi a4, a4, 4 +8001337c: 13 56 16 00 srli a2, a2, 1 +80013380: 93 95 f5 01 slli a1, a1, 31 +80013384: 33 66 b6 00 or a2, a2, a1 +80013388: 23 2e c7 fe sw a2, -4(a4) +8001338c: e3 12 e5 fe bne a0, a4, -28 +80013390: 03 27 c1 02 lw a4, 44(sp) +80013394: 13 57 17 00 srli a4, a4, 1 +80013398: 23 26 e1 02 sw a4, 44(sp) +8001339c: 33 37 d0 00 snez a4, a3 +800133a0: 83 26 01 02 lw a3, 32(sp) +800133a4: 33 e7 e6 00 or a4, a3, a4 +800133a8: 23 20 e1 02 sw a4, 32(sp) +800133ac: 37 87 00 00 lui a4, 8 +800133b0: 13 07 f7 ff addi a4, a4, -1 +800133b4: 63 9a e7 7c bne a5, a4, 2004 +800133b8: e3 80 09 02 beqz s3, 2080 +800133bc: 13 07 30 00 addi a4, zero, 3 +800133c0: e3 98 e9 02 bne s3, a4, 2096 +800133c4: e3 8a 04 00 beqz s1, 2068 +800133c8: 93 07 f0 ff addi a5, zero, -1 +800133cc: 23 26 f1 02 sw a5, 44(sp) +800133d0: 23 24 f1 02 sw a5, 40(sp) +800133d4: 23 22 f1 02 sw a5, 36(sp) +800133d8: 23 20 f1 02 sw a5, 32(sp) +800133dc: b7 87 00 00 lui a5, 8 +800133e0: 93 87 e7 ff addi a5, a5, -2 +800133e4: 6f 00 50 00 j 2052 +800133e8: 03 26 41 01 lw a2, 20(sp) +800133ec: 83 25 81 01 lw a1, 24(sp) +800133f0: 83 28 c1 01 lw a7, 28(sp) +800133f4: 63 8e 07 2e beqz a5, 764 +800133f8: b3 07 8e 40 sub a5, t3, s0 +800133fc: 63 10 04 10 bnez s0, 256 +80013400: 03 23 41 00 lw t1, 4(sp) +80013404: 03 25 81 00 lw a0, 8(sp) +80013408: 03 2f c1 00 lw t5, 12(sp) +8001340c: b3 6e a3 00 or t4, t1, a0 +80013410: b3 ee ee 01 or t4, t4, t5 +80013414: b3 ee de 00 or t4, t4, a3 +80013418: 63 94 0e 04 bnez t4, 72 +8001341c: b7 86 00 00 lui a3, 8 +80013420: 93 86 f6 ff addi a3, a3, -1 +80013424: 63 90 d7 02 bne a5, a3, 32 +80013428: b3 66 b6 00 or a3, a2, a1 +8001342c: b3 e6 16 01 or a3, a3, a7 +80013430: b3 e6 e6 00 or a3, a3, a4 +80013434: 63 88 06 00 beqz a3, 16 +80013438: 93 96 d8 00 slli a3, a7, 13 +8001343c: 63 c4 06 00 bltz a3, 8 +80013440: 13 04 00 01 addi s0, zero, 16 +80013444: 23 20 e1 02 sw a4, 32(sp) +80013448: 23 22 c1 02 sw a2, 36(sp) +8001344c: 23 24 b1 02 sw a1, 40(sp) +80013450: 23 26 11 03 sw a7, 44(sp) +80013454: 13 08 00 00 mv a6, zero +80013458: 63 8e 07 2c beqz a5, 732 +8001345c: 6f 00 c0 43 j 1084 +80013460: 93 8e f7 ff addi t4, a5, -1 +80013464: 63 98 0e 04 bnez t4, 80 +80013468: b3 86 e6 00 add a3, a3, a4 +8001346c: 33 b7 e6 00 sltu a4, a3, a4 +80013470: 33 08 c3 00 add a6, t1, a2 +80013474: b3 07 e8 00 add a5, a6, a4 +80013478: 33 b7 e7 00 sltu a4, a5, a4 +8001347c: 33 36 c8 00 sltu a2, a6, a2 +80013480: 33 66 e6 00 or a2, a2, a4 +80013484: 23 22 f1 02 sw a5, 36(sp) +80013488: b3 07 b5 00 add a5, a0, a1 +8001348c: 33 87 c7 00 add a4, a5, a2 +80013490: 33 36 c7 00 sltu a2, a4, a2 +80013494: b3 b7 b7 00 sltu a5, a5, a1 +80013498: b3 e7 c7 00 or a5, a5, a2 +8001349c: b3 08 1f 01 add a7, t5, a7 +800134a0: b3 88 17 01 add a7, a5, a7 +800134a4: 23 20 d1 02 sw a3, 32(sp) +800134a8: 23 24 e1 02 sw a4, 40(sp) +800134ac: 23 26 11 03 sw a7, 44(sp) +800134b0: 6f f0 9f c5 j -936 +800134b4: b7 86 00 00 lui a3, 8 +800134b8: 93 86 f6 ff addi a3, a3, -1 +800134bc: 63 84 d7 00 beq a5, a3, 8 +800134c0: 6f 10 c0 47 j 5244 +800134c4: b3 66 b6 00 or a3, a2, a1 +800134c8: b3 e6 16 01 or a3, a3, a7 +800134cc: b3 e6 e6 00 or a3, a3, a4 +800134d0: 13 04 00 00 mv s0, zero +800134d4: 63 8a 06 00 beqz a3, 20 +800134d8: 37 04 04 00 lui s0, 64 +800134dc: 33 f4 88 00 and s0, a7, s0 +800134e0: 13 34 14 00 seqz s0, s0 +800134e4: 13 14 44 00 slli s0, s0, 4 +800134e8: 23 20 e1 02 sw a4, 32(sp) +800134ec: 23 22 c1 02 sw a2, 36(sp) +800134f0: 23 24 b1 02 sw a1, 40(sp) +800134f4: 23 26 11 03 sw a7, 44(sp) +800134f8: 6f f0 df c5 j -932 +800134fc: b7 86 00 00 lui a3, 8 +80013500: 93 86 f6 ff addi a3, a3, -1 +80013504: 63 10 de 04 bne t3, a3, 64 +80013508: b3 67 b6 00 or a5, a2, a1 +8001350c: b3 e7 17 01 or a5, a5, a7 +80013510: b3 e7 e7 00 or a5, a5, a4 +80013514: 13 04 00 00 mv s0, zero +80013518: 63 8a 07 00 beqz a5, 20 +8001351c: 37 04 04 00 lui s0, 64 +80013520: 33 f4 88 00 and s0, a7, s0 +80013524: 13 34 14 00 seqz s0, s0 +80013528: 13 14 44 00 slli s0, s0, 4 +8001352c: 23 20 e1 02 sw a4, 32(sp) +80013530: 23 22 c1 02 sw a2, 36(sp) +80013534: 23 24 b1 02 sw a1, 40(sp) +80013538: 23 26 11 03 sw a7, 44(sp) +8001353c: 93 07 0e 00 mv a5, t3 +80013540: 6f f0 5f c1 j -1004 +80013544: 83 26 c1 00 lw a3, 12(sp) +80013548: 37 05 08 00 lui a0, 128 +8001354c: b3 e6 a6 00 or a3, a3, a0 +80013550: 23 26 d1 00 sw a3, 12(sp) +80013554: 93 06 40 07 addi a3, zero, 116 +80013558: 63 d4 f6 00 bge a3, a5, 8 +8001355c: 6f 10 c0 3e j 5100 +80013560: 93 8e 07 00 mv t4, a5 +80013564: 93 07 00 02 addi a5, zero, 32 +80013568: 33 c3 fe 02 div t1, t4, a5 +8001356c: 13 0f 00 00 mv t5, zero +80013570: 93 07 00 00 mv a5, zero +80013574: 63 ca 67 04 blt a5, t1, 84 +80013578: 93 06 03 00 mv a3, t1 +8001357c: 63 54 03 00 bgez t1, 8 +80013580: 93 06 00 00 mv a3, zero +80013584: 93 f7 fe 01 andi a5, t4, 31 +80013588: 13 15 23 00 slli a0, t1, 2 +8001358c: 63 9a 07 04 bnez a5, 84 +80013590: 93 06 30 00 addi a3, zero, 3 +80013594: b3 86 66 40 sub a3, a3, t1 +80013598: b3 0e a8 00 add t4, a6, a0 +8001359c: 83 ae 0e 00 lw t4, 0(t4) +800135a0: 93 87 17 00 addi a5, a5, 1 +800135a4: 13 08 48 00 addi a6, a6, 4 +800135a8: 23 2e d8 ff sw t4, -4(a6) +800135ac: e3 d6 f6 fe bge a3, a5, -20 +800135b0: 93 07 40 00 addi a5, zero, 4 +800135b4: 33 83 67 40 sub t1, a5, t1 +800135b8: 93 07 10 00 addi a5, zero, 1 +800135bc: 63 50 60 08 blez t1, 128 +800135c0: 93 07 03 00 mv a5, t1 +800135c4: 6f 00 80 07 j 120 +800135c8: 93 96 27 00 slli a3, a5, 2 +800135cc: b3 86 df 00 add a3, t6, a3 +800135d0: 83 a6 06 00 lw a3, 0(a3) +800135d4: 93 87 17 00 addi a5, a5, 1 +800135d8: 33 6f df 00 or t5, t5, a3 +800135dc: 6f f0 9f f9 j -104 +800135e0: 93 07 00 02 addi a5, zero, 32 +800135e4: b3 ee fe 02 rem t4, t4, a5 +800135e8: 93 96 26 00 slli a3, a3, 2 +800135ec: 13 08 01 04 addi a6, sp, 64 +800135f0: b3 06 d8 00 add a3, a6, a3 +800135f4: 83 a6 06 fc lw a3, -64(a3) +800135f8: 33 85 af 00 add a0, t6, a0 +800135fc: 93 02 00 00 mv t0, zero +80013600: b3 87 d7 41 sub a5, a5, t4 +80013604: b3 96 f6 00 sll a3, a3, a5 +80013608: 33 6f df 00 or t5, t5, a3 +8001360c: 93 06 30 00 addi a3, zero, 3 +80013610: b3 86 66 40 sub a3, a3, t1 +80013614: 13 05 45 00 addi a0, a0, 4 +80013618: 63 c6 d2 02 blt t0, a3, 44 +8001361c: 13 05 01 04 addi a0, sp, 64 +80013620: 93 96 26 00 slli a3, a3, 2 +80013624: b3 06 d5 00 add a3, a0, a3 +80013628: 03 25 c1 00 lw a0, 12(sp) +8001362c: 93 07 40 00 addi a5, zero, 4 +80013630: b3 87 67 40 sub a5, a5, t1 +80013634: b3 5e d5 01 srl t4, a0, t4 +80013638: 23 a0 d6 fd sw t4, -64(a3) +8001363c: 13 05 30 00 addi a0, zero, 3 +80013640: 6f 00 c0 03 j 60 +80013644: 03 28 c5 ff lw a6, -4(a0) +80013648: 03 24 05 00 lw s0, 0(a0) +8001364c: 93 93 22 00 slli t2, t0, 2 +80013650: 33 58 d8 01 srl a6, a6, t4 +80013654: 33 14 f4 00 sll s0, s0, a5 +80013658: b3 83 7f 00 add t2, t6, t2 +8001365c: 33 68 88 00 or a6, a6, s0 +80013660: 23 a0 03 01 sw a6, 0(t2) +80013664: 93 82 12 00 addi t0, t0, 1 +80013668: 6f f0 df fa j -84 +8001366c: 93 96 27 00 slli a3, a5, 2 +80013670: b3 86 df 00 add a3, t6, a3 +80013674: 23 a0 06 00 sw zero, 0(a3) +80013678: 93 87 17 00 addi a5, a5, 1 +8001367c: e3 58 f5 fe bge a0, a5, -16 +80013680: 83 26 01 00 lw a3, 0(sp) +80013684: b3 37 e0 01 snez a5, t5 +80013688: b3 e7 f6 00 or a5, a3, a5 +8001368c: 23 20 f1 00 sw a5, 0(sp) +80013690: 83 27 01 00 lw a5, 0(sp) +80013694: 83 26 41 00 lw a3, 4(sp) +80013698: b3 07 f7 00 add a5, a4, a5 +8001369c: 33 b7 e7 00 sltu a4, a5, a4 +800136a0: b3 06 d6 00 add a3, a2, a3 +800136a4: 23 20 f1 02 sw a5, 32(sp) +800136a8: b3 87 e6 00 add a5, a3, a4 +800136ac: 33 b7 e7 00 sltu a4, a5, a4 +800136b0: 23 22 f1 02 sw a5, 36(sp) +800136b4: 83 27 81 00 lw a5, 8(sp) +800136b8: 33 b6 c6 00 sltu a2, a3, a2 +800136bc: 33 66 e6 00 or a2, a2, a4 +800136c0: b3 87 f5 00 add a5, a1, a5 +800136c4: 33 87 c7 00 add a4, a5, a2 +800136c8: b3 b7 b7 00 sltu a5, a5, a1 +800136cc: 83 25 c1 00 lw a1, 12(sp) +800136d0: 33 36 c7 00 sltu a2, a4, a2 +800136d4: b3 e7 c7 00 or a5, a5, a2 +800136d8: b3 88 b8 00 add a7, a7, a1 +800136dc: b3 88 17 01 add a7, a5, a7 +800136e0: 23 24 e1 02 sw a4, 40(sp) +800136e4: 23 26 11 03 sw a7, 44(sp) +800136e8: 93 07 0e 00 mv a5, t3 +800136ec: 6f f0 1f c5 j -944 +800136f0: b7 8e 00 00 lui t4, 8 +800136f4: 93 07 14 00 addi a5, s0, 1 +800136f8: 13 88 ee ff addi a6, t4, -2 +800136fc: 33 f8 07 01 and a6, a5, a6 +80013700: 03 2f 41 00 lw t5, 4(sp) +80013704: 83 2f 81 00 lw t6, 8(sp) +80013708: 03 23 c1 00 lw t1, 12(sp) +8001370c: 63 1a 08 3e bnez a6, 1012 +80013710: 33 65 ff 01 or a0, t5, t6 +80013714: 33 65 65 00 or a0, a0, t1 +80013718: 33 65 d5 00 or a0, a0, a3 +8001371c: 63 12 04 30 bnez s0, 772 +80013720: 63 14 05 0e bnez a0, 232 +80013724: 23 20 e1 02 sw a4, 32(sp) +80013728: 23 22 c1 02 sw a2, 36(sp) +8001372c: 23 24 b1 02 sw a1, 40(sp) +80013730: 23 26 11 03 sw a7, 44(sp) +80013734: 83 25 01 02 lw a1, 32(sp) +80013738: 03 26 41 02 lw a2, 36(sp) +8001373c: 83 26 81 02 lw a3, 40(sp) +80013740: 03 27 c1 02 lw a4, 44(sp) +80013744: b3 e7 c5 00 or a5, a1, a2 +80013748: b3 e7 d7 00 or a5, a5, a3 +8001374c: b3 e7 e7 00 or a5, a5, a4 +80013750: 63 94 07 00 bnez a5, 8 +80013754: 6f 10 c0 0f j 4348 +80013758: 23 2a c1 02 sw a2, 52(sp) +8001375c: 23 28 b1 02 sw a1, 48(sp) +80013760: 23 2c d1 02 sw a3, 56(sp) +80013764: 23 2e e1 02 sw a4, 60(sp) +80013768: 13 06 01 03 addi a2, sp, 48 +8001376c: 93 07 c1 03 addi a5, sp, 60 +80013770: 03 a7 07 00 lw a4, 0(a5) +80013774: 83 a6 c7 ff lw a3, -4(a5) +80013778: 93 87 c7 ff addi a5, a5, -4 +8001377c: 13 17 17 00 slli a4, a4, 1 +80013780: 93 d6 f6 01 srli a3, a3, 31 +80013784: 33 67 d7 00 or a4, a4, a3 +80013788: 23 a2 e7 00 sw a4, 4(a5) +8001378c: e3 12 f6 fe bne a2, a5, -28 +80013790: 83 27 01 03 lw a5, 48(sp) +80013794: 93 97 17 00 slli a5, a5, 1 +80013798: 13 f7 77 00 andi a4, a5, 7 +8001379c: 63 14 07 00 bnez a4, 8 +800137a0: 6f 10 80 09 j 4248 +800137a4: 13 07 20 00 addi a4, zero, 2 +800137a8: 83 26 c1 03 lw a3, 60(sp) +800137ac: 13 64 14 00 ori s0, s0, 1 +800137b0: 63 94 e9 00 bne s3, a4, 8 +800137b4: 6f 10 00 08 j 4224 +800137b8: 13 07 30 00 addi a4, zero, 3 +800137bc: 63 94 e9 00 bne s3, a4, 8 +800137c0: 6f 10 40 06 j 4196 +800137c4: 63 84 09 00 beqz s3, 8 +800137c8: 6f 10 00 07 j 4208 +800137cc: 13 f7 f7 00 andi a4, a5, 15 +800137d0: 13 06 40 00 addi a2, zero, 4 +800137d4: 63 14 c7 00 bne a4, a2, 8 +800137d8: 6f 10 00 06 j 4192 +800137dc: 93 87 47 00 addi a5, a5, 4 +800137e0: 93 b7 47 00 sltiu a5, a5, 4 +800137e4: 03 27 41 03 lw a4, 52(sp) +800137e8: 33 87 e7 00 add a4, a5, a4 +800137ec: 33 37 f7 00 sltu a4, a4, a5 +800137f0: 83 27 81 03 lw a5, 56(sp) +800137f4: b3 07 f7 00 add a5, a4, a5 +800137f8: b3 b7 e7 00 sltu a5, a5, a4 +800137fc: b3 87 d7 00 add a5, a5, a3 +80013800: 23 2e f1 02 sw a5, 60(sp) +80013804: 6f 10 40 03 j 4148 +80013808: b3 67 b6 00 or a5, a2, a1 +8001380c: b3 e7 17 01 or a5, a5, a7 +80013810: b3 e7 e7 00 or a5, a5, a4 +80013814: 63 9c 07 00 bnez a5, 24 +80013818: 23 20 d1 02 sw a3, 32(sp) +8001381c: 23 22 e1 03 sw t5, 36(sp) +80013820: 23 24 f1 03 sw t6, 40(sp) +80013824: 23 26 61 02 sw t1, 44(sp) +80013828: 6f f0 df f0 j -244 +8001382c: 33 87 e6 00 add a4, a3, a4 +80013830: b3 07 cf 00 add a5, t5, a2 +80013834: b3 36 d7 00 sltu a3, a4, a3 +80013838: 23 20 e1 02 sw a4, 32(sp) +8001383c: 33 87 d7 00 add a4, a5, a3 +80013840: 33 b6 e7 01 sltu a2, a5, t5 +80013844: b3 36 d7 00 sltu a3, a4, a3 +80013848: b3 66 d6 00 or a3, a2, a3 +8001384c: b3 85 bf 00 add a1, t6, a1 +80013850: 33 86 d5 00 add a2, a1, a3 +80013854: b3 36 d6 00 sltu a3, a2, a3 +80013858: b3 b5 f5 01 sltu a1, a1, t6 +8001385c: b3 e5 d5 00 or a1, a1, a3 +80013860: b3 08 13 01 add a7, t1, a7 +80013864: b3 85 15 01 add a1, a1, a7 +80013868: 23 22 e1 02 sw a4, 36(sp) +8001386c: 23 24 c1 02 sw a2, 40(sp) +80013870: 93 97 c5 00 slli a5, a1, 12 +80013874: 63 c6 07 00 bltz a5, 12 +80013878: 23 26 b1 02 sw a1, 44(sp) +8001387c: 6f f0 9f eb j -328 +80013880: b7 07 f8 ff lui a5, 1048448 +80013884: 93 87 f7 ff addi a5, a5, -1 +80013888: b3 f5 f5 00 and a1, a1, a5 +8001388c: 23 26 b1 02 sw a1, 44(sp) +80013890: 13 08 04 00 mv a6, s0 +80013894: 93 07 10 00 addi a5, zero, 1 +80013898: 03 27 01 02 lw a4, 32(sp) +8001389c: 93 76 77 00 andi a3, a4, 7 +800138a0: 63 80 06 06 beqz a3, 96 +800138a4: 93 06 20 00 addi a3, zero, 2 +800138a8: 03 25 c1 02 lw a0, 44(sp) +800138ac: 13 64 14 00 ori s0, s0, 1 +800138b0: e3 80 d9 7e beq s3, a3, 4064 +800138b4: 93 06 30 00 addi a3, zero, 3 +800138b8: e3 80 d9 7a beq s3, a3, 4000 +800138bc: 63 92 09 04 bnez s3, 68 +800138c0: 93 76 f7 00 andi a3, a4, 15 +800138c4: 13 06 40 00 addi a2, zero, 4 +800138c8: 63 8c c6 02 beq a3, a2, 56 +800138cc: 83 25 41 02 lw a1, 36(sp) +800138d0: 13 07 47 00 addi a4, a4, 4 +800138d4: 23 20 e1 02 sw a4, 32(sp) +800138d8: 13 37 47 00 sltiu a4, a4, 4 +800138dc: b3 05 b7 00 add a1, a4, a1 +800138e0: 33 b7 e5 00 sltu a4, a1, a4 +800138e4: 23 22 b1 02 sw a1, 36(sp) +800138e8: 83 25 81 02 lw a1, 40(sp) +800138ec: b3 05 b7 00 add a1, a4, a1 +800138f0: 23 24 b1 02 sw a1, 40(sp) +800138f4: b3 b5 e5 00 sltu a1, a1, a4 +800138f8: b3 86 a5 00 add a3, a1, a0 +800138fc: 23 26 d1 02 sw a3, 44(sp) +80013900: 63 08 08 00 beqz a6, 16 +80013904: 13 77 14 00 andi a4, s0, 1 +80013908: 63 04 07 00 beqz a4, 8 +8001390c: 13 64 24 00 ori s0, s0, 2 +80013910: 03 27 c1 02 lw a4, 44(sp) +80013914: 93 16 c7 00 slli a3, a4, 12 +80013918: 63 d2 06 02 bgez a3, 36 +8001391c: b7 86 00 00 lui a3, 8 +80013920: 93 87 17 00 addi a5, a5, 1 +80013924: 93 86 f6 ff addi a3, a3, -1 +80013928: e3 80 d7 7a beq a5, a3, 4000 +8001392c: b7 06 f8 ff lui a3, 1048448 +80013930: 93 86 f6 ff addi a3, a3, -1 +80013934: 33 77 d7 00 and a4, a4, a3 +80013938: 23 26 e1 02 sw a4, 44(sp) +8001393c: 13 07 01 02 addi a4, sp, 32 +80013940: 93 05 c1 02 addi a1, sp, 44 +80013944: 83 26 07 00 lw a3, 0(a4) +80013948: 03 26 47 00 lw a2, 4(a4) +8001394c: 13 07 47 00 addi a4, a4, 4 +80013950: 93 d6 36 00 srli a3, a3, 3 +80013954: 13 16 d6 01 slli a2, a2, 29 +80013958: b3 e6 c6 00 or a3, a3, a2 +8001395c: 23 2e d7 fe sw a3, -4(a4) +80013960: e3 92 e5 fe bne a1, a4, -28 +80013964: 03 27 c1 02 lw a4, 44(sp) +80013968: 37 86 00 00 lui a2, 8 +8001396c: 93 56 37 00 srli a3, a4, 3 +80013970: 23 26 d1 02 sw a3, 44(sp) +80013974: 13 07 f6 ff addi a4, a2, -1 +80013978: 63 9a e7 02 bne a5, a4, 52 +8001397c: 83 25 41 02 lw a1, 36(sp) +80013980: 03 27 01 02 lw a4, 32(sp) +80013984: 33 67 b7 00 or a4, a4, a1 +80013988: 83 25 81 02 lw a1, 40(sp) +8001398c: 33 67 b7 00 or a4, a4, a1 +80013990: 33 67 d7 00 or a4, a4, a3 +80013994: 63 0c 07 00 beqz a4, 24 +80013998: 23 26 c1 02 sw a2, 44(sp) +8001399c: 23 24 01 02 sw zero, 40(sp) +800139a0: 23 22 01 02 sw zero, 36(sp) +800139a4: 23 20 01 02 sw zero, 32(sp) +800139a8: 93 04 00 00 mv s1, zero +800139ac: 83 25 c1 02 lw a1, 44(sp) +800139b0: 93 97 17 01 slli a5, a5, 17 +800139b4: 93 d7 17 01 srli a5, a5, 17 +800139b8: 93 94 f4 00 slli s1, s1, 15 +800139bc: b3 e4 f4 00 or s1, s1, a5 +800139c0: 23 1e b1 02 sh a1, 60(sp) +800139c4: 23 1f 91 02 sh s1, 62(sp) +800139c8: 03 26 01 02 lw a2, 32(sp) +800139cc: 83 26 41 02 lw a3, 36(sp) +800139d0: 03 27 81 02 lw a4, 40(sp) +800139d4: 83 27 c1 03 lw a5, 60(sp) +800139d8: 63 04 04 00 beqz s0, 8 +800139dc: 73 20 14 00 csrs fflags, s0 +800139e0: 83 20 c1 06 lw ra, 108(sp) +800139e4: 03 24 81 06 lw s0, 104(sp) +800139e8: 23 20 c9 00 sw a2, 0(s2) +800139ec: 23 22 d9 00 sw a3, 4(s2) +800139f0: 23 24 e9 00 sw a4, 8(s2) +800139f4: 23 26 f9 00 sw a5, 12(s2) +800139f8: 83 24 41 06 lw s1, 100(sp) +800139fc: 83 29 c1 05 lw s3, 92(sp) +80013a00: 03 2a 81 05 lw s4, 88(sp) +80013a04: 83 2a 41 05 lw s5, 84(sp) +80013a08: 03 2b 01 05 lw s6, 80(sp) +80013a0c: 83 2b c1 04 lw s7, 76(sp) +80013a10: 13 05 09 00 mv a0, s2 +80013a14: 03 29 01 06 lw s2, 96(sp) +80013a18: 13 01 01 07 addi sp, sp, 112 +80013a1c: 67 80 00 00 ret +80013a20: 93 8e fe ff addi t4, t4, -1 +80013a24: 63 14 d4 09 bne s0, t4, 136 +80013a28: e3 08 05 76 beqz a0, 3952 +80013a2c: 37 04 04 00 lui s0, 64 +80013a30: 33 74 83 00 and s0, t1, s0 +80013a34: 13 34 14 00 seqz s0, s0 +80013a38: 13 14 44 00 slli s0, s0, 4 +80013a3c: 63 10 de 0b bne t3, t4, 160 +80013a40: b3 67 b6 00 or a5, a2, a1 +80013a44: b3 e7 17 01 or a5, a5, a7 +80013a48: b3 e7 e7 00 or a5, a5, a4 +80013a4c: e3 8e 07 72 beqz a5, 3900 +80013a50: 93 97 d8 00 slli a5, a7, 13 +80013a54: e3 de 07 72 bgez a5, 3900 +80013a58: 63 04 05 06 beqz a0, 104 +80013a5c: b7 87 00 00 lui a5, 8 +80013a60: 23 26 f1 02 sw a5, 44(sp) +80013a64: 23 24 01 02 sw zero, 40(sp) +80013a68: 23 22 01 02 sw zero, 36(sp) +80013a6c: 23 20 01 02 sw zero, 32(sp) +80013a70: 13 06 01 02 addi a2, sp, 32 +80013a74: 93 07 c1 02 addi a5, sp, 44 +80013a78: 03 a7 07 00 lw a4, 0(a5) +80013a7c: 83 a6 c7 ff lw a3, -4(a5) +80013a80: 93 87 c7 ff addi a5, a5, -4 +80013a84: 13 17 37 00 slli a4, a4, 3 +80013a88: 93 d6 d6 01 srli a3, a3, 29 +80013a8c: 33 67 d7 00 or a4, a4, a3 +80013a90: 23 a2 e7 00 sw a4, 4(a5) +80013a94: e3 12 f6 fe bne a2, a5, -28 +80013a98: 83 27 01 02 lw a5, 32(sp) +80013a9c: 93 04 00 00 mv s1, zero +80013aa0: 93 97 37 00 slli a5, a5, 3 +80013aa4: 23 20 f1 02 sw a5, 32(sp) +80013aa8: 6f 00 80 02 j 40 +80013aac: 63 16 de 01 bne t3, t4, 12 +80013ab0: 13 04 00 00 mv s0, zero +80013ab4: 6f f0 df f8 j -116 +80013ab8: 13 04 00 00 mv s0, zero +80013abc: 63 10 05 02 bnez a0, 32 +80013ac0: 23 20 e1 02 sw a4, 32(sp) +80013ac4: 23 22 c1 02 sw a2, 36(sp) +80013ac8: 23 24 b1 02 sw a1, 40(sp) +80013acc: 23 26 11 03 sw a7, 44(sp) +80013ad0: b7 87 00 00 lui a5, 8 +80013ad4: 93 87 f7 ff addi a5, a5, -1 +80013ad8: 6f f0 1f dc j -576 +80013adc: 33 66 b6 00 or a2, a2, a1 +80013ae0: b3 68 16 01 or a7, a2, a7 +80013ae4: 33 e7 e8 00 or a4, a7, a4 +80013ae8: e3 1a 07 f6 bnez a4, -140 +80013aec: 23 20 d1 02 sw a3, 32(sp) +80013af0: 23 22 e1 03 sw t5, 36(sp) +80013af4: 23 24 f1 03 sw t6, 40(sp) +80013af8: 23 26 61 02 sw t1, 44(sp) +80013afc: 6f f0 5f fd j -44 +80013b00: 33 87 e6 00 add a4, a3, a4 +80013b04: b3 36 d7 00 sltu a3, a4, a3 +80013b08: 33 06 cf 00 add a2, t5, a2 +80013b0c: 23 20 e1 02 sw a4, 32(sp) +80013b10: 33 07 d6 00 add a4, a2, a3 +80013b14: b3 36 d7 00 sltu a3, a4, a3 +80013b18: 33 36 e6 01 sltu a2, a2, t5 +80013b1c: b3 66 d6 00 or a3, a2, a3 +80013b20: 33 86 bf 00 add a2, t6, a1 +80013b24: 23 22 e1 02 sw a4, 36(sp) +80013b28: 33 07 d6 00 add a4, a2, a3 +80013b2c: b3 35 f6 01 sltu a1, a2, t6 +80013b30: 33 36 d7 00 sltu a2, a4, a3 +80013b34: 33 e6 c5 00 or a2, a1, a2 +80013b38: b3 08 13 01 add a7, t1, a7 +80013b3c: b3 08 16 01 add a7, a2, a7 +80013b40: 23 24 e1 02 sw a4, 40(sp) +80013b44: 23 26 11 03 sw a7, 44(sp) +80013b48: 13 07 01 02 addi a4, sp, 32 +80013b4c: 93 05 c1 02 addi a1, sp, 44 +80013b50: 83 26 07 00 lw a3, 0(a4) +80013b54: 03 26 47 00 lw a2, 4(a4) +80013b58: 13 07 47 00 addi a4, a4, 4 +80013b5c: 93 d6 16 00 srli a3, a3, 1 +80013b60: 13 16 f6 01 slli a2, a2, 31 +80013b64: b3 e6 c6 00 or a3, a3, a2 +80013b68: 23 2e d7 fe sw a3, -4(a4) +80013b6c: e3 92 e5 fe bne a1, a4, -28 +80013b70: 37 87 00 00 lui a4, 8 +80013b74: 13 07 f7 ff addi a4, a4, -1 +80013b78: 63 8e e7 00 beq a5, a4, 28 +80013b7c: 03 27 c1 02 lw a4, 44(sp) +80013b80: 13 57 17 00 srli a4, a4, 1 +80013b84: 23 26 e1 02 sw a4, 44(sp) +80013b88: 13 08 00 00 mv a6, zero +80013b8c: 13 04 00 00 mv s0, zero +80013b90: 6f f0 9f d0 j -760 +80013b94: 63 82 09 04 beqz s3, 68 +80013b98: 13 07 30 00 addi a4, zero, 3 +80013b9c: 63 98 e9 02 bne s3, a4, 48 +80013ba0: 63 8c 04 02 beqz s1, 56 +80013ba4: 93 07 f0 ff addi a5, zero, -1 +80013ba8: 23 26 f1 02 sw a5, 44(sp) +80013bac: 23 24 f1 02 sw a5, 40(sp) +80013bb0: 23 22 f1 02 sw a5, 36(sp) +80013bb4: 23 20 f1 02 sw a5, 32(sp) +80013bb8: b7 87 00 00 lui a5, 8 +80013bbc: 13 08 00 00 mv a6, zero +80013bc0: 93 87 e7 ff addi a5, a5, -2 +80013bc4: 13 04 50 00 addi s0, zero, 5 +80013bc8: 6f f0 1f cd j -816 +80013bcc: 13 07 20 00 addi a4, zero, 2 +80013bd0: e3 9a e9 fc bne s3, a4, -44 +80013bd4: e3 88 04 fc beqz s1, -48 +80013bd8: 23 26 01 02 sw zero, 44(sp) +80013bdc: 23 24 01 02 sw zero, 40(sp) +80013be0: 23 22 01 02 sw zero, 36(sp) +80013be4: 23 20 01 02 sw zero, 32(sp) +80013be8: 13 08 00 00 mv a6, zero +80013bec: 6f f0 9f fd j -40 +80013bf0: 13 07 20 00 addi a4, zero, 2 +80013bf4: 63 9a e9 fc bne s3, a4, -2092 +80013bf8: 63 88 04 fc beqz s1, -2096 +80013bfc: 6f f0 df fd j -36 +80013c00: 63 54 f0 32 blez a5, 808 +80013c04: 03 25 41 00 lw a0, 4(sp) +80013c08: 03 28 81 00 lw a6, 8(sp) +80013c0c: 83 28 c1 00 lw a7, 12(sp) +80013c10: 63 14 0e 10 bnez t3, 264 +80013c14: 83 2f 41 01 lw t6, 20(sp) +80013c18: 83 2e 81 01 lw t4, 24(sp) +80013c1c: 03 23 c1 01 lw t1, 28(sp) +80013c20: b3 e5 df 01 or a1, t6, t4 +80013c24: b3 e5 65 00 or a1, a1, t1 +80013c28: b3 e5 e5 00 or a1, a1, a4 +80013c2c: 63 90 05 04 bnez a1, 64 +80013c30: 37 87 00 00 lui a4, 8 +80013c34: 13 07 f7 ff addi a4, a4, -1 +80013c38: 63 90 e7 02 bne a5, a4, 32 +80013c3c: 33 67 05 01 or a4, a0, a6 +80013c40: 33 67 17 01 or a4, a4, a7 +80013c44: 33 67 d7 00 or a4, a4, a3 +80013c48: 63 08 07 00 beqz a4, 16 +80013c4c: 13 97 d8 00 slli a4, a7, 13 +80013c50: 63 44 07 00 bltz a4, 8 +80013c54: 13 0e 00 01 addi t3, zero, 16 +80013c58: 23 20 d1 02 sw a3, 32(sp) +80013c5c: 23 22 a1 02 sw a0, 36(sp) +80013c60: 23 24 01 03 sw a6, 40(sp) +80013c64: 23 26 11 03 sw a7, 44(sp) +80013c68: 6f f0 8f c4 j -3000 +80013c6c: 93 85 f7 ff addi a1, a5, -1 +80013c70: 63 94 05 06 bnez a1, 104 +80013c74: 33 87 e6 40 sub a4, a3, a4 +80013c78: b3 07 f5 41 sub a5, a0, t6 +80013c7c: 33 b6 e6 00 sltu a2, a3, a4 +80013c80: 33 3e f5 00 sltu t3, a0, a5 +80013c84: 33 86 c7 40 sub a2, a5, a2 +80013c88: 93 07 00 00 mv a5, zero +80013c8c: 63 f6 e6 00 bgeu a3, a4, 12 +80013c90: 33 85 af 40 sub a0, t6, a0 +80013c94: 93 37 15 00 seqz a5, a0 +80013c98: 33 e5 c7 01 or a0, a5, t3 +80013c9c: b3 07 d8 41 sub a5, a6, t4 +80013ca0: b3 36 f8 00 sltu a3, a6, a5 +80013ca4: b3 87 a7 40 sub a5, a5, a0 +80013ca8: 63 06 05 00 beqz a0, 12 +80013cac: 33 88 0e 41 sub a6, t4, a6 +80013cb0: 93 35 18 00 seqz a1, a6 +80013cb4: b3 88 68 40 sub a7, a7, t1 +80013cb8: b3 e5 d5 00 or a1, a1, a3 +80013cbc: b3 85 b8 40 sub a1, a7, a1 +80013cc0: 23 26 b1 02 sw a1, 44(sp) +80013cc4: 23 24 f1 02 sw a5, 40(sp) +80013cc8: 23 22 c1 02 sw a2, 36(sp) +80013ccc: 23 20 e1 02 sw a4, 32(sp) +80013cd0: 93 07 10 00 addi a5, zero, 1 +80013cd4: 6f 00 00 23 j 560 +80013cd8: 37 87 00 00 lui a4, 8 +80013cdc: 13 07 f7 ff addi a4, a4, -1 +80013ce0: e3 9e e7 46 bne a5, a4, 3196 +80013ce4: 33 67 05 01 or a4, a0, a6 +80013ce8: 33 67 17 01 or a4, a4, a7 +80013cec: 33 67 d7 00 or a4, a4, a3 +80013cf0: 13 04 00 00 mv s0, zero +80013cf4: 63 0a 07 00 beqz a4, 20 +80013cf8: 37 04 04 00 lui s0, 64 +80013cfc: 33 f4 88 00 and s0, a7, s0 +80013d00: 13 34 14 00 seqz s0, s0 +80013d04: 13 14 44 00 slli s0, s0, 4 +80013d08: 23 20 d1 02 sw a3, 32(sp) +80013d0c: 23 22 a1 02 sw a0, 36(sp) +80013d10: 23 24 01 03 sw a6, 40(sp) +80013d14: 6f f0 0f fe j -2080 +80013d18: 37 87 00 00 lui a4, 8 +80013d1c: 13 07 f7 ff addi a4, a4, -1 +80013d20: 63 1e e4 02 bne s0, a4, 60 +80013d24: b3 67 05 01 or a5, a0, a6 +80013d28: b3 e7 17 01 or a5, a5, a7 +80013d2c: b3 e7 d7 00 or a5, a5, a3 +80013d30: 13 07 00 00 mv a4, zero +80013d34: 63 8a 07 00 beqz a5, 20 +80013d38: 37 07 04 00 lui a4, 64 +80013d3c: 33 f7 e8 00 and a4, a7, a4 +80013d40: 13 37 17 00 seqz a4, a4 +80013d44: 13 17 47 00 slli a4, a4, 4 +80013d48: 23 20 d1 02 sw a3, 32(sp) +80013d4c: 23 22 a1 02 sw a0, 36(sp) +80013d50: 23 24 01 03 sw a6, 40(sp) +80013d54: 23 26 11 03 sw a7, 44(sp) +80013d58: 6f f0 4f c4 j -3004 +80013d5c: 03 27 c1 01 lw a4, 28(sp) +80013d60: b7 05 08 00 lui a1, 128 +80013d64: 33 67 b7 00 or a4, a4, a1 +80013d68: 23 2e e1 00 sw a4, 28(sp) +80013d6c: 13 07 40 07 addi a4, zero, 116 +80013d70: e3 4a f7 3e blt a4, a5, 3060 +80013d74: 93 85 07 00 mv a1, a5 +80013d78: 13 d3 55 40 srai t1, a1, 5 +80013d7c: 13 0e 00 00 mv t3, zero +80013d80: 93 07 00 00 mv a5, zero +80013d84: 63 96 67 04 bne a5, t1, 76 +80013d88: 93 f5 f5 01 andi a1, a1, 31 +80013d8c: 13 17 23 00 slli a4, t1, 2 +80013d90: 63 9c 05 04 bnez a1, 88 +80013d94: 93 05 30 00 addi a1, zero, 3 +80013d98: 93 07 00 00 mv a5, zero +80013d9c: b3 85 65 40 sub a1, a1, t1 +80013da0: b3 0e e6 00 add t4, a2, a4 +80013da4: 83 ae 0e 00 lw t4, 0(t4) +80013da8: 93 87 17 00 addi a5, a5, 1 +80013dac: 13 06 46 00 addi a2, a2, 4 +80013db0: 23 2e d6 ff sw t4, -4(a2) +80013db4: e3 d6 f5 fe bge a1, a5, -20 +80013db8: 93 07 40 00 addi a5, zero, 4 +80013dbc: 33 83 67 40 sub t1, a5, t1 +80013dc0: 93 07 10 00 addi a5, zero, 1 +80013dc4: 63 5c 60 06 blez t1, 120 +80013dc8: 93 07 03 00 mv a5, t1 +80013dcc: 6f 00 00 07 j 112 +80013dd0: 13 97 27 00 slli a4, a5, 2 +80013dd4: 33 07 ef 00 add a4, t5, a4 +80013dd8: 03 27 07 00 lw a4, 0(a4) +80013ddc: 93 87 17 00 addi a5, a5, 1 +80013de0: 33 6e ee 00 or t3, t3, a4 +80013de4: 6f f0 1f fa j -96 +80013de8: 93 07 01 04 addi a5, sp, 64 +80013dec: b3 87 e7 00 add a5, a5, a4 +80013df0: 83 a7 07 fd lw a5, -48(a5) +80013df4: 93 0f 00 02 addi t6, zero, 32 +80013df8: b3 8f bf 40 sub t6, t6, a1 +80013dfc: b3 97 f7 01 sll a5, a5, t6 +80013e00: 33 06 ef 00 add a2, t5, a4 +80013e04: 13 07 30 00 addi a4, zero, 3 +80013e08: 33 6e fe 00 or t3, t3, a5 +80013e0c: 93 0e 00 00 mv t4, zero +80013e10: 33 07 67 40 sub a4, a4, t1 +80013e14: 13 06 46 00 addi a2, a2, 4 +80013e18: 63 c6 ee 02 blt t4, a4, 44 +80013e1c: 13 06 01 04 addi a2, sp, 64 +80013e20: 13 17 27 00 slli a4, a4, 2 +80013e24: 33 07 e6 00 add a4, a2, a4 +80013e28: 03 26 c1 01 lw a2, 28(sp) +80013e2c: 93 07 40 00 addi a5, zero, 4 +80013e30: b3 87 67 40 sub a5, a5, t1 +80013e34: b3 55 b6 00 srl a1, a2, a1 +80013e38: 23 28 b7 fc sw a1, -48(a4) +80013e3c: 13 06 40 00 addi a2, zero, 4 +80013e40: 6f 00 c0 03 j 60 +80013e44: 83 27 c6 ff lw a5, -4(a2) +80013e48: 83 23 06 00 lw t2, 0(a2) +80013e4c: 93 92 2e 00 slli t0, t4, 2 +80013e50: b3 d7 b7 00 srl a5, a5, a1 +80013e54: b3 93 f3 01 sll t2, t2, t6 +80013e58: b3 02 5f 00 add t0, t5, t0 +80013e5c: b3 e7 77 00 or a5, a5, t2 +80013e60: 23 a0 f2 00 sw a5, 0(t0) +80013e64: 93 8e 1e 00 addi t4, t4, 1 +80013e68: 6f f0 df fa j -84 +80013e6c: 13 97 27 00 slli a4, a5, 2 +80013e70: 33 07 ef 00 add a4, t5, a4 +80013e74: 23 20 07 00 sw zero, 0(a4) +80013e78: 93 87 17 00 addi a5, a5, 1 +80013e7c: e3 98 c7 fe bne a5, a2, -16 +80013e80: 03 27 01 01 lw a4, 16(sp) +80013e84: b3 37 c0 01 snez a5, t3 +80013e88: b3 67 f7 00 or a5, a4, a5 +80013e8c: 23 28 f1 00 sw a5, 16(sp) +80013e90: 83 27 01 01 lw a5, 16(sp) +80013e94: 83 25 41 01 lw a1, 20(sp) +80013e98: b3 87 f6 40 sub a5, a3, a5 +80013e9c: 33 06 b5 40 sub a2, a0, a1 +80013ea0: 33 b7 f6 00 sltu a4, a3, a5 +80013ea4: 33 33 c5 00 sltu t1, a0, a2 +80013ea8: 33 06 e6 40 sub a2, a2, a4 +80013eac: 13 07 00 00 mv a4, zero +80013eb0: 63 f6 f6 00 bgeu a3, a5, 12 +80013eb4: 33 85 a5 40 sub a0, a1, a0 +80013eb8: 13 37 15 00 seqz a4, a0 +80013ebc: 33 65 67 00 or a0, a4, t1 +80013ec0: 03 23 81 01 lw t1, 24(sp) +80013ec4: 93 05 00 00 mv a1, zero +80013ec8: 33 07 68 40 sub a4, a6, t1 +80013ecc: 33 3e e8 00 sltu t3, a6, a4 +80013ed0: b3 06 a7 40 sub a3, a4, a0 +80013ed4: 63 06 05 00 beqz a0, 12 +80013ed8: 33 08 03 41 sub a6, t1, a6 +80013edc: 93 35 18 00 seqz a1, a6 +80013ee0: 03 27 c1 01 lw a4, 28(sp) +80013ee4: b3 e5 c5 01 or a1, a1, t3 +80013ee8: 23 20 f1 02 sw a5, 32(sp) +80013eec: b3 88 e8 40 sub a7, a7, a4 +80013ef0: b3 88 b8 40 sub a7, a7, a1 +80013ef4: 23 26 11 03 sw a7, 44(sp) +80013ef8: 23 24 d1 02 sw a3, 40(sp) +80013efc: 23 22 c1 02 sw a2, 36(sp) +80013f00: 93 07 04 00 mv a5, s0 +80013f04: 03 27 c1 02 lw a4, 44(sp) +80013f08: 93 16 c7 00 slli a3, a4, 12 +80013f0c: e3 d8 06 10 bgez a3, 2320 +80013f10: b7 06 08 00 lui a3, 128 +80013f14: 93 86 f6 ff addi a3, a3, -1 +80013f18: 33 77 d7 00 and a4, a4, a3 +80013f1c: 23 26 e1 02 sw a4, 44(sp) +80013f20: 13 84 07 00 mv s0, a5 +80013f24: 6f 00 80 66 j 1640 +80013f28: 03 23 41 01 lw t1, 20(sp) +80013f2c: 83 28 81 01 lw a7, 24(sp) +80013f30: 03 2f c1 01 lw t5, 28(sp) +80013f34: 63 8e 07 32 beqz a5, 828 +80013f38: b3 07 8e 40 sub a5, t3, s0 +80013f3c: 63 1a 04 10 bnez s0, 276 +80013f40: 83 22 41 00 lw t0, 4(sp) +80013f44: 83 25 81 00 lw a1, 8(sp) +80013f48: 03 25 c1 00 lw a0, 12(sp) +80013f4c: 33 e6 b2 00 or a2, t0, a1 +80013f50: 33 66 a6 00 or a2, a2, a0 +80013f54: 33 66 d6 00 or a2, a2, a3 +80013f58: 63 12 06 04 bnez a2, 68 +80013f5c: b7 86 00 00 lui a3, 8 +80013f60: 93 86 f6 ff addi a3, a3, -1 +80013f64: 63 90 d7 02 bne a5, a3, 32 +80013f68: b3 66 13 01 or a3, t1, a7 +80013f6c: b3 e6 e6 01 or a3, a3, t5 +80013f70: b3 e6 e6 00 or a3, a3, a4 +80013f74: 63 88 06 00 beqz a3, 16 +80013f78: 93 16 df 00 slli a3, t5, 13 +80013f7c: 63 c4 06 00 bltz a3, 8 +80013f80: 13 04 00 01 addi s0, zero, 16 +80013f84: 23 20 e1 02 sw a4, 32(sp) +80013f88: 23 22 61 02 sw t1, 36(sp) +80013f8c: 23 24 11 03 sw a7, 40(sp) +80013f90: 23 26 e1 03 sw t5, 44(sp) +80013f94: 93 84 0e 00 mv s1, t4 +80013f98: 6f f0 cf cb j -2884 +80013f9c: 13 86 f7 ff addi a2, a5, -1 +80013fa0: 63 14 06 06 bnez a2, 104 +80013fa4: b3 06 d7 40 sub a3, a4, a3 +80013fa8: b3 07 53 40 sub a5, t1, t0 +80013fac: 33 38 d7 00 sltu a6, a4, a3 +80013fb0: 33 3e f3 00 sltu t3, t1, a5 +80013fb4: 33 88 07 41 sub a6, a5, a6 +80013fb8: 93 07 00 00 mv a5, zero +80013fbc: 63 76 d7 00 bgeu a4, a3, 12 +80013fc0: 33 83 62 40 sub t1, t0, t1 +80013fc4: 93 37 13 00 seqz a5, t1 +80013fc8: 33 e3 c7 01 or t1, a5, t3 +80013fcc: b3 87 b8 40 sub a5, a7, a1 +80013fd0: 33 b7 f8 00 sltu a4, a7, a5 +80013fd4: b3 87 67 40 sub a5, a5, t1 +80013fd8: 63 06 03 00 beqz t1, 12 +80013fdc: b3 88 15 41 sub a7, a1, a7 +80013fe0: 13 b6 18 00 seqz a2, a7 +80013fe4: 33 0f af 40 sub t5, t5, a0 +80013fe8: 33 66 e6 00 or a2, a2, a4 +80013fec: 33 0f cf 40 sub t5, t5, a2 +80013ff0: 23 26 e1 03 sw t5, 44(sp) +80013ff4: 23 24 f1 02 sw a5, 40(sp) +80013ff8: 23 22 01 03 sw a6, 36(sp) +80013ffc: 23 20 d1 02 sw a3, 32(sp) +80014000: 93 84 0e 00 mv s1, t4 +80014004: 6f f0 df cc j -820 +80014008: b7 86 00 00 lui a3, 8 +8001400c: 93 86 f6 ff addi a3, a3, -1 +80014010: e3 94 d7 16 bne a5, a3, 2408 +80014014: b3 66 13 01 or a3, t1, a7 +80014018: b3 e6 e6 01 or a3, a3, t5 +8001401c: b3 e6 e6 00 or a3, a3, a4 +80014020: 13 04 00 00 mv s0, zero +80014024: 63 8a 06 00 beqz a3, 20 +80014028: 37 04 04 00 lui s0, 64 +8001402c: 33 74 8f 00 and s0, t5, s0 +80014030: 13 34 14 00 seqz s0, s0 +80014034: 13 14 44 00 slli s0, s0, 4 +80014038: 23 20 e1 02 sw a4, 32(sp) +8001403c: 23 22 61 02 sw t1, 36(sp) +80014040: 23 24 11 03 sw a7, 40(sp) +80014044: 23 26 e1 03 sw t5, 44(sp) +80014048: 93 84 0e 00 mv s1, t4 +8001404c: 6f f0 8f 90 j -3832 +80014050: b7 86 00 00 lui a3, 8 +80014054: 93 86 f6 ff addi a3, a3, -1 +80014058: 63 10 de 04 bne t3, a3, 64 +8001405c: b3 67 13 01 or a5, t1, a7 +80014060: b3 e7 e7 01 or a5, a5, t5 +80014064: b3 e7 e7 00 or a5, a5, a4 +80014068: 13 04 00 00 mv s0, zero +8001406c: 63 8a 07 00 beqz a5, 20 +80014070: 37 04 04 00 lui s0, 64 +80014074: 33 74 8f 00 and s0, t5, s0 +80014078: 13 34 14 00 seqz s0, s0 +8001407c: 13 14 44 00 slli s0, s0, 4 +80014080: 23 20 e1 02 sw a4, 32(sp) +80014084: 23 22 61 02 sw t1, 36(sp) +80014088: 23 24 11 03 sw a7, 40(sp) +8001408c: 23 26 e1 03 sw t5, 44(sp) +80014090: 93 07 0e 00 mv a5, t3 +80014094: 6f f0 5f fb j -76 +80014098: 83 26 c1 00 lw a3, 12(sp) +8001409c: 37 06 08 00 lui a2, 128 +800140a0: b3 e6 c6 00 or a3, a3, a2 +800140a4: 23 26 d1 00 sw a3, 12(sp) +800140a8: 93 06 40 07 addi a3, zero, 116 +800140ac: 63 c8 f6 1a blt a3, a5, 432 +800140b0: 93 06 00 02 addi a3, zero, 32 +800140b4: b3 c2 d7 02 div t0, a5, a3 +800140b8: 93 03 00 00 mv t2, zero +800140bc: 93 06 00 00 mv a3, zero +800140c0: 63 cc 56 04 blt a3, t0, 88 +800140c4: 13 86 02 00 mv a2, t0 +800140c8: 63 d4 02 00 bgez t0, 8 +800140cc: 13 06 00 00 mv a2, zero +800140d0: 93 f6 f7 01 andi a3, a5, 31 +800140d4: 93 95 22 00 slli a1, t0, 2 +800140d8: 63 9c 06 04 bnez a3, 88 +800140dc: 93 06 30 00 addi a3, zero, 3 +800140e0: 93 07 00 00 mv a5, zero +800140e4: b3 86 56 40 sub a3, a3, t0 +800140e8: 33 06 b8 00 add a2, a6, a1 +800140ec: 03 26 06 00 lw a2, 0(a2) +800140f0: 93 87 17 00 addi a5, a5, 1 +800140f4: 13 08 48 00 addi a6, a6, 4 +800140f8: 23 2e c8 fe sw a2, -4(a6) +800140fc: e3 d6 f6 fe bge a3, a5, -20 +80014100: 93 06 40 00 addi a3, zero, 4 +80014104: b3 82 56 40 sub t0, a3, t0 +80014108: 93 06 10 00 addi a3, zero, 1 +8001410c: 63 50 50 08 blez t0, 128 +80014110: 93 86 02 00 mv a3, t0 +80014114: 6f 00 80 07 j 120 +80014118: 13 96 26 00 slli a2, a3, 2 +8001411c: 33 86 cf 00 add a2, t6, a2 +80014120: 03 26 06 00 lw a2, 0(a2) +80014124: 93 86 16 00 addi a3, a3, 1 +80014128: b3 e3 c3 00 or t2, t2, a2 +8001412c: 6f f0 5f f9 j -108 +80014130: 93 06 00 02 addi a3, zero, 32 +80014134: b3 e7 d7 02 rem a5, a5, a3 +80014138: 13 05 01 04 addi a0, sp, 64 +8001413c: 13 16 26 00 slli a2, a2, 2 +80014140: 33 06 c5 00 add a2, a0, a2 +80014144: 03 26 06 fc lw a2, -64(a2) +80014148: b3 85 bf 00 add a1, t6, a1 +8001414c: 13 05 00 00 mv a0, zero +80014150: b3 86 f6 40 sub a3, a3, a5 +80014154: 33 16 d6 00 sll a2, a2, a3 +80014158: b3 e3 c3 00 or t2, t2, a2 +8001415c: 13 06 30 00 addi a2, zero, 3 +80014160: 33 06 56 40 sub a2, a2, t0 +80014164: 93 85 45 00 addi a1, a1, 4 +80014168: 63 46 c5 02 blt a0, a2, 44 +8001416c: 93 05 01 04 addi a1, sp, 64 +80014170: 13 16 26 00 slli a2, a2, 2 +80014174: 33 86 c5 00 add a2, a1, a2 +80014178: 83 25 c1 00 lw a1, 12(sp) +8001417c: 93 06 40 00 addi a3, zero, 4 +80014180: b3 86 56 40 sub a3, a3, t0 +80014184: b3 d7 f5 00 srl a5, a1, a5 +80014188: 23 20 f6 fc sw a5, -64(a2) +8001418c: 13 06 30 00 addi a2, zero, 3 +80014190: 6f 00 c0 03 j 60 +80014194: 03 a8 c5 ff lw a6, -4(a1) +80014198: 83 a4 05 00 lw s1, 0(a1) +8001419c: 13 14 25 00 slli s0, a0, 2 +800141a0: 33 58 f8 00 srl a6, a6, a5 +800141a4: b3 94 d4 00 sll s1, s1, a3 +800141a8: 33 84 8f 00 add s0, t6, s0 +800141ac: 33 68 98 00 or a6, a6, s1 +800141b0: 23 20 04 01 sw a6, 0(s0) +800141b4: 13 05 15 00 addi a0, a0, 1 +800141b8: 6f f0 df fa j -84 +800141bc: 93 97 26 00 slli a5, a3, 2 +800141c0: b3 87 ff 00 add a5, t6, a5 +800141c4: 23 a0 07 00 sw zero, 0(a5) +800141c8: 93 86 16 00 addi a3, a3, 1 +800141cc: e3 58 d6 fe bge a2, a3, -16 +800141d0: 83 26 01 00 lw a3, 0(sp) +800141d4: b3 37 70 00 snez a5, t2 +800141d8: b3 e7 f6 00 or a5, a3, a5 +800141dc: 23 20 f1 00 sw a5, 0(sp) +800141e0: 83 26 01 00 lw a3, 0(sp) +800141e4: 83 25 41 00 lw a1, 4(sp) +800141e8: b3 06 d7 40 sub a3, a4, a3 +800141ec: 33 06 b3 40 sub a2, t1, a1 +800141f0: b3 37 d7 00 sltu a5, a4, a3 +800141f4: 33 35 c3 00 sltu a0, t1, a2 +800141f8: 33 06 f6 40 sub a2, a2, a5 +800141fc: 93 07 00 00 mv a5, zero +80014200: 63 76 d7 00 bgeu a4, a3, 12 +80014204: 33 83 65 40 sub t1, a1, t1 +80014208: 93 37 13 00 seqz a5, t1 +8001420c: 83 25 81 00 lw a1, 8(sp) +80014210: 33 e3 a7 00 or t1, a5, a0 +80014214: 93 07 00 00 mv a5, zero +80014218: 33 87 b8 40 sub a4, a7, a1 +8001421c: 33 b8 e8 00 sltu a6, a7, a4 +80014220: 33 07 67 40 sub a4, a4, t1 +80014224: 63 06 03 00 beqz t1, 12 +80014228: b3 88 15 41 sub a7, a1, a7 +8001422c: 93 b7 18 00 seqz a5, a7 +80014230: 03 25 c1 00 lw a0, 12(sp) +80014234: b3 e7 07 01 or a5, a5, a6 +80014238: 23 24 e1 02 sw a4, 40(sp) +8001423c: 33 0f af 40 sub t5, t5, a0 +80014240: 33 0f ff 40 sub t5, t5, a5 +80014244: 23 26 e1 03 sw t5, 44(sp) +80014248: 23 22 c1 02 sw a2, 36(sp) +8001424c: 23 20 d1 02 sw a3, 32(sp) +80014250: 93 07 0e 00 mv a5, t3 +80014254: 93 84 0e 00 mv s1, t4 +80014258: 6f f0 df ca j -852 +8001425c: 23 26 01 00 sw zero, 12(sp) +80014260: 23 24 01 00 sw zero, 8(sp) +80014264: 23 22 01 00 sw zero, 4(sp) +80014268: 93 07 10 00 addi a5, zero, 1 +8001426c: 6f f0 1f f7 j -144 +80014270: b7 83 00 00 lui t2, 8 +80014274: 13 86 e3 ff addi a2, t2, -2 +80014278: 13 08 14 00 addi a6, s0, 1 +8001427c: 33 78 c8 00 and a6, a6, a2 +80014280: 83 25 81 00 lw a1, 8(sp) +80014284: 03 26 41 00 lw a2, 4(sp) +80014288: 03 25 c1 00 lw a0, 12(sp) +8001428c: 63 14 08 24 bnez a6, 584 +80014290: b3 6f 13 01 or t6, t1, a7 +80014294: b3 62 b6 00 or t0, a2, a1 +80014298: b3 ef ef 01 or t6, t6, t5 +8001429c: b3 e2 a2 00 or t0, t0, a0 +800142a0: b3 ef ef 00 or t6, t6, a4 +800142a4: b3 e2 d2 00 or t0, t0, a3 +800142a8: 63 1c 04 10 bnez s0, 280 +800142ac: 63 94 02 02 bnez t0, 40 +800142b0: 23 20 e1 02 sw a4, 32(sp) +800142b4: 23 22 61 02 sw t1, 36(sp) +800142b8: 23 24 11 03 sw a7, 40(sp) +800142bc: 23 26 e1 03 sw t5, 44(sp) +800142c0: 93 84 0e 00 mv s1, t4 +800142c4: 63 98 0f c6 bnez t6, -2960 +800142c8: 93 84 e9 ff addi s1, s3, -2 +800142cc: 93 b4 14 00 seqz s1, s1 +800142d0: 6f f0 4f c6 j -2972 +800142d4: 63 9c 0f 00 bnez t6, 24 +800142d8: 23 20 d1 02 sw a3, 32(sp) +800142dc: 23 22 c1 02 sw a2, 36(sp) +800142e0: 23 24 b1 02 sw a1, 40(sp) +800142e4: 23 26 a1 02 sw a0, 44(sp) +800142e8: 6f f0 cf c4 j -2996 +800142ec: b3 87 e6 40 sub a5, a3, a4 +800142f0: b3 03 66 40 sub t2, a2, t1 +800142f4: b3 bf f6 00 sltu t6, a3, a5 +800142f8: 33 38 76 00 sltu a6, a2, t2 +800142fc: b3 8f f3 41 sub t6, t2, t6 +80014300: 13 0e 00 00 mv t3, zero +80014304: 63 f4 f6 00 bgeu a3, a5, 8 +80014308: 13 be 13 00 seqz t3, t2 +8001430c: b3 82 15 41 sub t0, a1, a7 +80014310: 33 6e 0e 01 or t3, t3, a6 +80014314: 33 bb 55 00 sltu s6, a1, t0 +80014318: b3 8a c2 41 sub s5, t0, t3 +8001431c: 13 0a 00 00 mv s4, zero +80014320: 63 04 0e 00 beqz t3, 8 +80014324: 13 ba 12 00 seqz s4, t0 +80014328: 33 08 e5 41 sub a6, a0, t5 +8001432c: 33 6a 6a 01 or s4, s4, s6 +80014330: 33 08 48 41 sub a6, a6, s4 +80014334: 23 26 01 03 sw a6, 44(sp) +80014338: 23 24 51 03 sw s5, 40(sp) +8001433c: 23 22 f1 03 sw t6, 36(sp) +80014340: 23 20 f1 02 sw a5, 32(sp) +80014344: 13 1e c8 00 slli t3, a6, 12 +80014348: 63 52 0e 06 bgez t3, 100 +8001434c: b3 06 d7 40 sub a3, a4, a3 +80014350: 33 06 c3 40 sub a2, t1, a2 +80014354: b3 37 d7 00 sltu a5, a4, a3 +80014358: 33 33 c3 00 sltu t1, t1, a2 +8001435c: 33 06 f6 40 sub a2, a2, a5 +80014360: 93 07 00 00 mv a5, zero +80014364: 63 74 d7 00 bgeu a4, a3, 8 +80014368: 93 b7 13 00 seqz a5, t2 +8001436c: b3 85 b8 40 sub a1, a7, a1 +80014370: 33 e3 67 00 or t1, a5, t1 +80014374: b3 b8 b8 00 sltu a7, a7, a1 +80014378: 13 08 00 00 mv a6, zero +8001437c: b3 85 65 40 sub a1, a1, t1 +80014380: 63 04 03 00 beqz t1, 8 +80014384: 13 b8 12 00 seqz a6, t0 +80014388: 33 05 af 40 sub a0, t5, a0 +8001438c: 33 68 18 01 or a6, a6, a7 +80014390: 33 08 05 41 sub a6, a0, a6 +80014394: 23 26 01 03 sw a6, 44(sp) +80014398: 23 24 b1 02 sw a1, 40(sp) +8001439c: 23 22 c1 02 sw a2, 36(sp) +800143a0: 23 20 d1 02 sw a3, 32(sp) +800143a4: 93 84 0e 00 mv s1, t4 +800143a8: 6f f0 cf b8 j -3188 +800143ac: b3 e7 f7 01 or a5, a5, t6 +800143b0: b3 e7 57 01 or a5, a5, s5 +800143b4: b3 e7 07 01 or a5, a5, a6 +800143b8: 63 9e 07 b6 bnez a5, -3204 +800143bc: 6f f0 df f0 j -244 +800143c0: 93 83 f3 ff addi t2, t2, -1 +800143c4: 13 0a 01 02 addi s4, sp, 32 +800143c8: 63 14 74 06 bne s0, t2, 104 +800143cc: 63 84 02 5e beqz t0, 1512 +800143d0: 37 04 04 00 lui s0, 64 +800143d4: 33 74 85 00 and s0, a0, s0 +800143d8: 13 34 14 00 seqz s0, s0 +800143dc: 13 14 44 00 slli s0, s0, 4 +800143e0: 63 1e 7e 0c bne t3, t2, 220 +800143e4: 63 80 0f 5c beqz t6, 1472 +800143e8: 93 17 df 00 slli a5, t5, 13 +800143ec: 63 d0 07 5c bgez a5, 1472 +800143f0: 63 88 02 0a beqz t0, 176 +800143f4: b7 87 00 00 lui a5, 8 +800143f8: 23 26 f1 02 sw a5, 44(sp) +800143fc: 23 24 01 02 sw zero, 40(sp) +80014400: 23 22 01 02 sw zero, 36(sp) +80014404: 23 20 01 02 sw zero, 32(sp) +80014408: 93 07 c1 02 addi a5, sp, 44 +8001440c: 03 a7 07 00 lw a4, 0(a5) +80014410: 83 a6 c7 ff lw a3, -4(a5) +80014414: 93 87 c7 ff addi a5, a5, -4 +80014418: 13 17 37 00 slli a4, a4, 3 +8001441c: 93 d6 d6 01 srli a3, a3, 29 +80014420: 33 67 d7 00 or a4, a4, a3 +80014424: 23 a2 e7 00 sw a4, 4(a5) +80014428: e3 12 fa fe bne s4, a5, -28 +8001442c: 6f f0 cf e6 j -2452 +80014430: 63 16 7e 00 bne t3, t2, 12 +80014434: 13 04 00 00 mv s0, zero +80014438: 6f f0 df fa j -84 +8001443c: 63 9e 02 06 bnez t0, 124 +80014440: 63 9e 0f 04 bnez t6, 92 +80014444: b7 87 00 00 lui a5, 8 +80014448: 23 26 f1 02 sw a5, 44(sp) +8001444c: 23 24 01 02 sw zero, 40(sp) +80014450: 23 22 01 02 sw zero, 36(sp) +80014454: 23 20 01 02 sw zero, 32(sp) +80014458: 93 07 c1 02 addi a5, sp, 44 +8001445c: 03 a7 07 00 lw a4, 0(a5) +80014460: 83 a6 c7 ff lw a3, -4(a5) +80014464: 93 87 c7 ff addi a5, a5, -4 +80014468: 13 17 37 00 slli a4, a4, 3 +8001446c: 93 d6 d6 01 srli a3, a3, 29 +80014470: 33 67 d7 00 or a4, a4, a3 +80014474: 23 a2 e7 00 sw a4, 4(a5) +80014478: e3 12 fa fe bne s4, a5, -28 +8001447c: 83 27 01 02 lw a5, 32(sp) +80014480: 93 04 00 00 mv s1, zero +80014484: 13 04 00 01 addi s0, zero, 16 +80014488: 93 97 37 00 slli a5, a5, 3 +8001448c: 23 20 f1 02 sw a5, 32(sp) +80014490: b7 87 00 00 lui a5, 8 +80014494: 93 87 f7 ff addi a5, a5, -1 +80014498: 6f f0 0f c0 j -3072 +8001449c: 13 04 00 00 mv s0, zero +800144a0: 23 20 e1 02 sw a4, 32(sp) +800144a4: 23 22 61 02 sw t1, 36(sp) +800144a8: 23 24 11 03 sw a7, 40(sp) +800144ac: 23 26 e1 03 sw t5, 44(sp) +800144b0: 93 84 0e 00 mv s1, t4 +800144b4: 6f f0 cf e1 j -2532 +800144b8: 13 04 00 00 mv s0, zero +800144bc: e3 9c 0f f2 bnez t6, -200 +800144c0: 23 20 d1 02 sw a3, 32(sp) +800144c4: 23 22 c1 02 sw a2, 36(sp) +800144c8: 23 24 b1 02 sw a1, 40(sp) +800144cc: 23 26 a1 02 sw a0, 44(sp) +800144d0: 6f f0 0f e0 j -2560 +800144d4: 33 88 e6 40 sub a6, a3, a4 +800144d8: 33 0a 66 40 sub s4, a2, t1 +800144dc: b3 b2 06 01 sltu t0, a3, a6 +800144e0: 33 3e 46 01 sltu t3, a2, s4 +800144e4: b3 02 5a 40 sub t0, s4, t0 +800144e8: 93 0f 00 00 mv t6, zero +800144ec: 63 f4 06 01 bgeu a3, a6, 8 +800144f0: 93 3f 1a 00 seqz t6, s4 +800144f4: b3 83 15 41 sub t2, a1, a7 +800144f8: b3 ef cf 01 or t6, t6, t3 +800144fc: b3 bb 75 00 sltu s7, a1, t2 +80014500: 33 8b f3 41 sub s6, t2, t6 +80014504: 93 0a 00 00 mv s5, zero +80014508: 63 84 0f 00 beqz t6, 8 +8001450c: 93 ba 13 00 seqz s5, t2 +80014510: 33 0e e5 41 sub t3, a0, t5 +80014514: b3 ea 7a 01 or s5, s5, s7 +80014518: 33 0e 5e 41 sub t3, t3, s5 +8001451c: 23 26 c1 03 sw t3, 44(sp) +80014520: 23 24 61 03 sw s6, 40(sp) +80014524: 23 22 51 02 sw t0, 36(sp) +80014528: 23 20 01 03 sw a6, 32(sp) +8001452c: 93 1f ce 00 slli t6, t3, 12 +80014530: 63 d0 0f 0c bgez t6, 192 +80014534: b3 06 d7 40 sub a3, a4, a3 +80014538: 33 06 c3 40 sub a2, t1, a2 +8001453c: 33 38 d7 00 sltu a6, a4, a3 +80014540: 33 33 c3 00 sltu t1, t1, a2 +80014544: 33 06 06 41 sub a2, a2, a6 +80014548: 13 08 00 00 mv a6, zero +8001454c: 63 74 d7 00 bgeu a4, a3, 8 +80014550: 13 38 1a 00 seqz a6, s4 +80014554: b3 85 b8 40 sub a1, a7, a1 +80014558: 33 63 68 00 or t1, a6, t1 +8001455c: b3 b8 b8 00 sltu a7, a7, a1 +80014560: b3 85 65 40 sub a1, a1, t1 +80014564: 63 04 03 00 beqz t1, 8 +80014568: 93 b7 13 00 seqz a5, t2 +8001456c: 33 05 af 40 sub a0, t5, a0 +80014570: b3 e7 17 01 or a5, a5, a7 +80014574: 33 05 f5 40 sub a0, a0, a5 +80014578: 23 26 a1 02 sw a0, 44(sp) +8001457c: 23 24 b1 02 sw a1, 40(sp) +80014580: 23 22 c1 02 sw a2, 36(sp) +80014584: 23 20 d1 02 sw a3, 32(sp) +80014588: 93 84 0e 00 mv s1, t4 +8001458c: 03 25 c1 02 lw a0, 44(sp) +80014590: 63 00 05 08 beqz a0, 128 +80014594: ef 00 50 73 jal 3892 +80014598: 93 07 45 ff addi a5, a0, -12 +8001459c: 13 06 00 02 addi a2, zero, 32 +800145a0: 93 f6 f7 01 andi a3, a5, 31 +800145a4: 33 c7 c7 02 div a4, a5, a2 +800145a8: 63 80 06 0a beqz a3, 160 +800145ac: 93 06 c0 ff addi a3, zero, -4 +800145b0: 13 03 01 02 addi t1, sp, 32 +800145b4: 13 15 27 00 slli a0, a4, 2 +800145b8: 33 e8 c7 02 rem a6, a5, a2 +800145bc: b3 06 d7 02 mul a3, a4, a3 +800145c0: 33 06 06 41 sub a2, a2, a6 +800145c4: 93 86 c6 00 addi a3, a3, 12 +800145c8: b3 06 d3 00 add a3, t1, a3 +800145cc: 63 16 d3 0a bne t1, a3, 172 +800145d0: 93 06 01 04 addi a3, sp, 64 +800145d4: 33 85 a6 00 add a0, a3, a0 +800145d8: 83 26 01 02 lw a3, 32(sp) +800145dc: 13 07 f7 ff addi a4, a4, -1 +800145e0: b3 96 06 01 sll a3, a3, a6 +800145e4: 23 20 d5 fe sw a3, -32(a0) +800145e8: 13 06 f0 ff addi a2, zero, -1 +800145ec: 6f 00 40 0c j 196 +800145f0: 33 68 58 00 or a6, a6, t0 +800145f4: 33 68 68 01 or a6, a6, s6 +800145f8: 33 68 c8 01 or a6, a6, t3 +800145fc: e3 18 08 f8 bnez a6, -112 +80014600: 93 84 e9 ff addi s1, s3, -2 +80014604: 93 b4 14 00 seqz s1, s1 +80014608: 13 04 00 00 mv s0, zero +8001460c: 6f f0 8f 92 j -3800 +80014610: 03 25 81 02 lw a0, 40(sp) +80014614: 63 08 05 00 beqz a0, 16 +80014618: ef 00 10 6b jal 3760 +8001461c: 13 05 05 02 addi a0, a0, 32 +80014620: 6f f0 9f f7 j -136 +80014624: 03 25 41 02 lw a0, 36(sp) +80014628: 63 08 05 00 beqz a0, 16 +8001462c: ef 00 d0 69 jal 3740 +80014630: 13 05 05 04 addi a0, a0, 64 +80014634: 6f f0 5f f6 j -156 +80014638: 03 25 01 02 lw a0, 32(sp) +8001463c: ef 00 d0 68 jal 3724 +80014640: 13 05 05 06 addi a0, a0, 96 +80014644: 6f f0 5f f5 j -172 +80014648: 93 05 c0 ff addi a1, zero, -4 +8001464c: b3 05 b7 02 mul a1, a4, a1 +80014650: 93 06 c1 02 addi a3, sp, 44 +80014654: 13 06 30 00 addi a2, zero, 3 +80014658: 33 85 b6 00 add a0, a3, a1 +8001465c: 03 25 05 00 lw a0, 0(a0) +80014660: 13 06 f6 ff addi a2, a2, -1 +80014664: 93 86 c6 ff addi a3, a3, -4 +80014668: 23 a2 a6 00 sw a0, 4(a3) +8001466c: e3 56 e6 fe bge a2, a4, -20 +80014670: 13 07 f7 ff addi a4, a4, -1 +80014674: 6f f0 5f f7 j -140 +80014678: 83 a5 c6 ff lw a1, -4(a3) +8001467c: 83 a8 06 00 lw a7, 0(a3) +80014680: 33 8e a6 00 add t3, a3, a0 +80014684: b3 d5 c5 00 srl a1, a1, a2 +80014688: b3 98 08 01 sll a7, a7, a6 +8001468c: b3 e5 15 01 or a1, a1, a7 +80014690: 23 20 be 00 sw a1, 0(t3) +80014694: 93 86 c6 ff addi a3, a3, -4 +80014698: 6f f0 5f f3 j -204 +8001469c: 93 16 27 00 slli a3, a4, 2 +800146a0: 93 05 01 02 addi a1, sp, 32 +800146a4: b3 86 d5 00 add a3, a1, a3 +800146a8: 23 a0 06 00 sw zero, 0(a3) +800146ac: 13 07 f7 ff addi a4, a4, -1 +800146b0: e3 16 c7 fe bne a4, a2, -20 +800146b4: 63 c8 87 14 blt a5, s0, 336 +800146b8: b3 87 87 40 sub a5, a5, s0 +800146bc: 13 07 00 02 addi a4, zero, 32 +800146c0: 93 87 17 00 addi a5, a5, 1 +800146c4: 33 c8 e7 02 div a6, a5, a4 +800146c8: 93 08 00 00 mv a7, zero +800146cc: 13 07 00 00 mv a4, zero +800146d0: 63 4c 07 05 blt a4, a6, 88 +800146d4: 93 06 08 00 mv a3, a6 +800146d8: 63 54 08 00 bgez a6, 8 +800146dc: 93 06 00 00 mv a3, zero +800146e0: 13 f7 f7 01 andi a4, a5, 31 +800146e4: 13 16 28 00 slli a2, a6, 2 +800146e8: 63 1e 07 04 bnez a4, 92 +800146ec: 93 06 30 00 addi a3, zero, 3 +800146f0: 93 07 01 02 addi a5, sp, 32 +800146f4: b3 86 06 41 sub a3, a3, a6 +800146f8: b3 85 c7 00 add a1, a5, a2 +800146fc: 83 a5 05 00 lw a1, 0(a1) +80014700: 13 07 17 00 addi a4, a4, 1 +80014704: 93 87 47 00 addi a5, a5, 4 +80014708: 23 ae b7 fe sw a1, -4(a5) +8001470c: e3 d6 e6 fe bge a3, a4, -20 +80014710: 13 07 40 00 addi a4, zero, 4 +80014714: 33 08 07 41 sub a6, a4, a6 +80014718: 13 07 10 00 addi a4, zero, 1 +8001471c: 63 54 00 09 blez a6, 136 +80014720: 13 07 08 00 mv a4, a6 +80014724: 6f 00 00 08 j 128 +80014728: 93 16 27 00 slli a3, a4, 2 +8001472c: 13 06 01 02 addi a2, sp, 32 +80014730: b3 06 d6 00 add a3, a2, a3 +80014734: 83 a6 06 00 lw a3, 0(a3) +80014738: 13 07 17 00 addi a4, a4, 1 +8001473c: b3 e8 d8 00 or a7, a7, a3 +80014740: 6f f0 1f f9 j -112 +80014744: 93 05 00 02 addi a1, zero, 32 +80014748: b3 e7 b7 02 rem a5, a5, a1 +8001474c: 13 07 01 04 addi a4, sp, 64 +80014750: 93 96 26 00 slli a3, a3, 2 +80014754: b3 06 d7 00 add a3, a4, a3 +80014758: 03 a7 06 fe lw a4, -32(a3) +8001475c: 93 06 30 00 addi a3, zero, 3 +80014760: b3 86 06 41 sub a3, a3, a6 +80014764: b3 85 f5 40 sub a1, a1, a5 +80014768: 33 17 b7 00 sll a4, a4, a1 +8001476c: b3 e8 e8 00 or a7, a7, a4 +80014770: 13 07 01 02 addi a4, sp, 32 +80014774: 33 06 c7 00 add a2, a4, a2 +80014778: 13 07 00 00 mv a4, zero +8001477c: 13 06 46 00 addi a2, a2, 4 +80014780: 63 46 d7 02 blt a4, a3, 44 +80014784: 03 24 c1 02 lw s0, 44(sp) +80014788: 93 96 26 00 slli a3, a3, 2 +8001478c: 13 06 01 04 addi a2, sp, 64 +80014790: 13 07 40 00 addi a4, zero, 4 +80014794: b3 06 d6 00 add a3, a2, a3 +80014798: b3 57 f4 00 srl a5, s0, a5 +8001479c: 33 07 07 41 sub a4, a4, a6 +800147a0: 23 a0 f6 fe sw a5, -32(a3) +800147a4: 93 06 30 00 addi a3, zero, 3 +800147a8: 6f 00 40 04 j 68 +800147ac: 13 13 27 00 slli t1, a4, 2 +800147b0: 13 05 01 02 addi a0, sp, 32 +800147b4: 03 2e 06 00 lw t3, 0(a2) +800147b8: 33 03 65 00 add t1, a0, t1 +800147bc: 03 25 c6 ff lw a0, -4(a2) +800147c0: 33 1e be 00 sll t3, t3, a1 +800147c4: 13 07 17 00 addi a4, a4, 1 +800147c8: 33 55 f5 00 srl a0, a0, a5 +800147cc: 33 65 c5 01 or a0, a0, t3 +800147d0: 23 20 a3 00 sw a0, 0(t1) +800147d4: 6f f0 9f fa j -88 +800147d8: 93 17 27 00 slli a5, a4, 2 +800147dc: 13 06 01 02 addi a2, sp, 32 +800147e0: b3 07 f6 00 add a5, a2, a5 +800147e4: 23 a0 07 00 sw zero, 0(a5) +800147e8: 13 07 17 00 addi a4, a4, 1 +800147ec: e3 d6 e6 fe bge a3, a4, -20 +800147f0: 03 27 01 02 lw a4, 32(sp) +800147f4: b3 37 10 01 snez a5, a7 +800147f8: b3 67 f7 00 or a5, a4, a5 +800147fc: 23 20 f1 02 sw a5, 32(sp) +80014800: 6f f0 9f e0 j -504 +80014804: 03 27 c1 02 lw a4, 44(sp) +80014808: b7 06 f8 ff lui a3, 1048448 +8001480c: 93 86 f6 ff addi a3, a3, -1 +80014810: 33 77 d7 00 and a4, a4, a3 +80014814: b3 07 f4 40 sub a5, s0, a5 +80014818: 23 26 e1 02 sw a4, 44(sp) +8001481c: 13 04 00 00 mv s0, zero +80014820: 6f e0 5f c3 j -5068 +80014824: 63 9a 04 00 bnez s1, 20 +80014828: 93 87 87 00 addi a5, a5, 8 +8001482c: 93 b7 87 00 sltiu a5, a5, 8 +80014830: 6f e0 5f fb j -4172 +80014834: e3 9a 04 fe bnez s1, -12 +80014838: 03 28 c1 03 lw a6, 60(sp) +8001483c: 93 07 00 00 mv a5, zero +80014840: 13 58 48 01 srli a6, a6, 20 +80014844: 13 48 18 00 xori a6, a6, 1 +80014848: 13 78 18 00 andi a6, a6, 1 +8001484c: 6f f0 cf 84 j -4020 +80014850: 93 07 00 00 mv a5, zero +80014854: 6f e0 1f 90 j -5888 +80014858: 63 94 04 8a bnez s1, -3928 +8001485c: 03 26 41 02 lw a2, 36(sp) +80014860: 13 07 87 00 addi a4, a4, 8 +80014864: 23 20 e1 02 sw a4, 32(sp) +80014868: 13 37 87 00 sltiu a4, a4, 8 +8001486c: 33 06 c7 00 add a2, a4, a2 +80014870: 33 37 e6 00 sltu a4, a2, a4 +80014874: 23 22 c1 02 sw a2, 36(sp) +80014878: 03 26 81 02 lw a2, 40(sp) +8001487c: 33 06 c7 00 add a2, a4, a2 +80014880: 23 24 c1 02 sw a2, 40(sp) +80014884: 33 36 e6 00 sltu a2, a2, a4 +80014888: b3 06 a6 00 add a3, a2, a0 +8001488c: 6f f0 0f 87 j -3984 +80014890: 63 88 04 86 beqz s1, -3984 +80014894: 83 26 41 02 lw a3, 36(sp) +80014898: 13 07 87 00 addi a4, a4, 8 +8001489c: 03 26 81 02 lw a2, 40(sp) +800148a0: 23 20 e1 02 sw a4, 32(sp) +800148a4: 13 37 87 00 sltiu a4, a4, 8 +800148a8: b3 06 d7 00 add a3, a4, a3 +800148ac: 33 b7 e6 00 sltu a4, a3, a4 +800148b0: 23 22 d1 02 sw a3, 36(sp) +800148b4: b3 06 c7 00 add a3, a4, a2 +800148b8: 23 24 d1 02 sw a3, 40(sp) +800148bc: b3 b6 e6 00 sltu a3, a3, a4 +800148c0: b3 86 a6 00 add a3, a3, a0 +800148c4: 6f f0 8f 83 j -4040 +800148c8: 63 8e 09 02 beqz s3, 60 +800148cc: 13 07 30 00 addi a4, zero, 3 +800148d0: 63 94 e9 02 bne s3, a4, 40 +800148d4: 63 88 04 02 beqz s1, 48 +800148d8: 93 07 f0 ff addi a5, zero, -1 +800148dc: 23 26 f1 02 sw a5, 44(sp) +800148e0: 23 24 f1 02 sw a5, 40(sp) +800148e4: 23 22 f1 02 sw a5, 36(sp) +800148e8: 23 20 f1 02 sw a5, 32(sp) +800148ec: b7 87 00 00 lui a5, 8 +800148f0: 93 87 e7 ff addi a5, a5, -2 +800148f4: 6f 00 00 02 j 32 +800148f8: 13 07 20 00 addi a4, zero, 2 +800148fc: e3 9e e9 fc bne s3, a4, -36 +80014900: e3 8c 04 fc beqz s1, -40 +80014904: 23 26 01 02 sw zero, 44(sp) +80014908: 23 24 01 02 sw zero, 40(sp) +8001490c: 23 22 01 02 sw zero, 36(sp) +80014910: 23 20 01 02 sw zero, 32(sp) +80014914: 13 64 54 00 ori s0, s0, 5 +80014918: 6f f0 4f 82 j -4060 +8001491c: 93 07 40 07 addi a5, zero, 116 +80014920: 63 c4 67 00 blt a5, t1, 8 +80014924: 6f e0 5f 8a j -5980 +80014928: 23 2e 01 00 sw zero, 28(sp) +8001492c: 23 2c 01 00 sw zero, 24(sp) +80014930: 23 2a 01 00 sw zero, 20(sp) +80014934: 93 07 10 00 addi a5, zero, 1 +80014938: 6f e0 5f 9a j -5724 +8001493c: 93 07 40 07 addi a5, zero, 116 +80014940: 63 c4 d7 01 blt a5, t4, 8 +80014944: 6f e0 1f c2 j -5088 +80014948: 23 26 01 00 sw zero, 12(sp) +8001494c: 23 24 01 00 sw zero, 8(sp) +80014950: 23 22 01 00 sw zero, 4(sp) +80014954: 93 07 10 00 addi a5, zero, 1 +80014958: 6f e0 5f d3 j -4812 +8001495c: 93 07 40 07 addi a5, zero, 116 +80014960: 63 dc b7 c0 bge a5, a1, -3048 +80014964: 23 2e 01 00 sw zero, 28(sp) +80014968: 23 2c 01 00 sw zero, 24(sp) +8001496c: 23 2a 01 00 sw zero, 20(sp) +80014970: 93 07 10 00 addi a5, zero, 1 +80014974: 6f f0 8f d1 j -2792 +80014978: 93 07 40 07 addi a5, zero, 116 +8001497c: e3 c0 c7 8e blt a5, a2, -1824 +80014980: 93 07 06 00 mv a5, a2 +80014984: 6f f0 cf f2 j -2260 +80014988: 63 12 05 96 bnez a0, -3740 +8001498c: 6f f0 4f 93 j -3788 +80014990: 13 04 00 01 addi s0, zero, 16 +80014994: 6f f0 4f 8c j -3900 +80014998: 63 0c 8e 90 beq t3, s0, -3816 +8001499c: 13 04 00 00 mv s0, zero +800149a0: 6f f0 0f 92 j -3808 +800149a4: e3 9e 02 b0 bnez t0, -1252 +800149a8: 6f f0 df a9 j -1380 +800149ac: 13 04 00 01 addi s0, zero, 16 +800149b0: 6f f0 1f a4 j -1472 +800149b4: e3 16 8e a8 bne t3, s0, -1396 +800149b8: 6f f0 df a7 j -1412 + +800149bc __fixtfsi: +800149bc: 03 27 05 00 lw a4, 0(a0) +800149c0: 03 23 45 00 lw t1, 4(a0) +800149c4: 03 26 85 00 lw a2, 8(a0) +800149c8: 83 28 c5 00 lw a7, 12(a0) +800149cc: 13 01 01 fe addi sp, sp, -32 +800149d0: f3 27 20 00 frrm a5 +800149d4: 93 97 18 00 slli a5, a7, 1 +800149d8: 93 d5 17 01 srli a1, a5, 17 +800149dc: b7 47 00 00 lui a5, 4 +800149e0: 13 98 08 01 slli a6, a7, 16 +800149e4: 23 20 e1 00 sw a4, 0(sp) +800149e8: 23 22 61 00 sw t1, 4(sp) +800149ec: 23 24 c1 00 sw a2, 8(sp) +800149f0: 23 26 11 01 sw a7, 12(sp) +800149f4: 23 28 e1 00 sw a4, 16(sp) +800149f8: 23 2a 61 00 sw t1, 20(sp) +800149fc: 23 2c c1 00 sw a2, 24(sp) +80014a00: 93 86 e7 ff addi a3, a5, -2 +80014a04: 13 58 08 01 srli a6, a6, 16 +80014a08: 63 c0 b6 02 blt a3, a1, 32 +80014a0c: 63 94 05 14 bnez a1, 328 +80014a10: 33 65 67 00 or a0, a4, t1 +80014a14: 33 65 c5 00 or a0, a0, a2 +80014a18: 33 65 05 01 or a0, a0, a6 +80014a1c: 63 1c 05 12 bnez a0, 312 +80014a20: 13 01 01 02 addi sp, sp, 32 +80014a24: 67 80 00 00 ret +80014a28: 93 d8 f8 01 srli a7, a7, 31 +80014a2c: 13 8e d7 01 addi t3, a5, 29 +80014a30: 93 86 08 00 mv a3, a7 +80014a34: 63 52 be 04 bge t3, a1, 68 +80014a38: 37 05 00 80 lui a0, 524288 +80014a3c: 13 45 f5 ff not a0, a0 +80014a40: 33 85 a8 00 add a0, a7, a0 +80014a44: 63 8e 08 10 beqz a7, 284 +80014a48: 93 87 e7 01 addi a5, a5, 30 +80014a4c: 63 9a f5 10 bne a1, a5, 276 +80014a50: 93 57 16 01 srli a5, a2, 17 +80014a54: 13 18 f8 00 slli a6, a6, 15 +80014a58: 33 e8 07 01 or a6, a5, a6 +80014a5c: 63 12 08 10 bnez a6, 260 +80014a60: 33 67 67 00 or a4, a4, t1 +80014a64: 13 16 f6 00 slli a2, a2, 15 +80014a68: 33 67 e6 00 or a4, a2, a4 +80014a6c: e3 0a 07 fa beqz a4, -76 +80014a70: 73 a0 16 00 csrs fflags, a3 +80014a74: 6f f0 df fa j -84 +80014a78: 13 05 07 00 mv a0, a4 +80014a7c: 93 87 f7 06 addi a5, a5, 111 +80014a80: 37 07 01 00 lui a4, 16 +80014a84: 33 68 e8 00 or a6, a6, a4 +80014a88: b3 87 b7 40 sub a5, a5, a1 +80014a8c: 23 2e 01 01 sw a6, 28(sp) +80014a90: 93 d6 57 40 srai a3, a5, 5 +80014a94: 13 06 01 01 addi a2, sp, 16 +80014a98: 13 03 00 00 mv t1, zero +80014a9c: 13 07 00 00 mv a4, zero +80014aa0: 83 25 06 00 lw a1, 0(a2) +80014aa4: 13 07 17 00 addi a4, a4, 1 +80014aa8: 13 06 46 00 addi a2, a2, 4 +80014aac: 33 63 b3 00 or t1, t1, a1 +80014ab0: e3 98 e6 fe bne a3, a4, -16 +80014ab4: 93 f7 f7 01 andi a5, a5, 31 +80014ab8: 13 96 26 00 slli a2, a3, 2 +80014abc: 63 96 07 02 bnez a5, 44 +80014ac0: 93 07 01 02 addi a5, sp, 32 +80014ac4: 33 86 c7 00 add a2, a5, a2 +80014ac8: 83 27 06 ff lw a5, -16(a2) +80014acc: 23 28 f1 00 sw a5, 16(sp) +80014ad0: 03 25 01 01 lw a0, 16(sp) +80014ad4: 63 84 08 00 beqz a7, 8 +80014ad8: 33 05 a0 40 neg a0, a0 +80014adc: 93 06 10 00 addi a3, zero, 1 +80014ae0: e3 00 03 f4 beqz t1, -192 +80014ae4: 6f f0 df f8 j -116 +80014ae8: 93 05 01 02 addi a1, sp, 32 +80014aec: 33 86 c5 00 add a2, a1, a2 +80014af0: 03 26 06 ff lw a2, -16(a2) +80014af4: 13 07 00 02 addi a4, zero, 32 +80014af8: 33 07 f7 40 sub a4, a4, a5 +80014afc: b3 15 e6 00 sll a1, a2, a4 +80014b00: 33 63 b3 00 or t1, t1, a1 +80014b04: 93 86 e6 ff addi a3, a3, -2 +80014b08: b3 15 e8 00 sll a1, a6, a4 +80014b0c: 33 56 f6 00 srl a2, a2, a5 +80014b10: 13 0e 00 00 mv t3, zero +80014b14: 13 07 00 00 mv a4, zero +80014b18: 93 b6 16 00 seqz a3, a3 +80014b1c: 33 66 b6 00 or a2, a2, a1 +80014b20: 63 42 d7 02 blt a4, a3, 36 +80014b24: 63 04 0e 00 beqz t3, 8 +80014b28: 23 28 a1 00 sw a0, 16(sp) +80014b2c: 13 17 27 00 slli a4, a4, 2 +80014b30: 93 06 01 02 addi a3, sp, 32 +80014b34: 33 87 e6 00 add a4, a3, a4 +80014b38: b3 57 f8 00 srl a5, a6, a5 +80014b3c: 23 28 f7 fe sw a5, -16(a4) +80014b40: 6f f0 1f f9 j -112 +80014b44: 13 05 06 00 mv a0, a2 +80014b48: 13 0e 10 00 addi t3, zero, 1 +80014b4c: 13 07 10 00 addi a4, zero, 1 +80014b50: 6f f0 1f fd j -48 +80014b54: 93 06 10 00 addi a3, zero, 1 +80014b58: 13 05 00 00 mv a0, zero +80014b5c: 6f f0 5f f1 j -236 +80014b60: 93 06 00 01 addi a3, zero, 16 +80014b64: 6f f0 df f0 j -244 + +80014b68 __floatsitf: +80014b68: 13 01 01 fd addi sp, sp, -48 +80014b6c: 23 22 91 02 sw s1, 36(sp) +80014b70: 23 26 11 02 sw ra, 44(sp) +80014b74: 23 24 81 02 sw s0, 40(sp) +80014b78: 23 20 21 03 sw s2, 32(sp) +80014b7c: 93 04 05 00 mv s1, a0 +80014b80: 63 80 05 12 beqz a1, 288 +80014b84: 93 d7 f5 41 srai a5, a1, 31 +80014b88: 33 c4 b7 00 xor s0, a5, a1 +80014b8c: 33 04 f4 40 sub s0, s0, a5 +80014b90: 13 05 04 00 mv a0, s0 +80014b94: 13 d9 f5 01 srli s2, a1, 31 +80014b98: ef 00 10 13 jal 2352 +80014b9c: 37 47 00 00 lui a4, 4 +80014ba0: 13 07 e7 01 addi a4, a4, 30 +80014ba4: 93 07 15 05 addi a5, a0, 81 +80014ba8: b3 05 a7 40 sub a1, a4, a0 +80014bac: 23 28 81 00 sw s0, 16(sp) +80014bb0: 13 d7 57 40 srai a4, a5, 5 +80014bb4: 23 2a 01 00 sw zero, 20(sp) +80014bb8: 23 2c 01 00 sw zero, 24(sp) +80014bbc: 23 2e 01 00 sw zero, 28(sp) +80014bc0: 93 f7 f7 01 andi a5, a5, 31 +80014bc4: 63 8c 07 02 beqz a5, 56 +80014bc8: 93 06 20 00 addi a3, zero, 2 +80014bcc: 63 16 d7 0c bne a4, a3, 204 +80014bd0: 93 06 00 02 addi a3, zero, 32 +80014bd4: b3 86 f6 40 sub a3, a3, a5 +80014bd8: b3 56 d4 00 srl a3, s0, a3 +80014bdc: 23 2e d1 00 sw a3, 28(sp) +80014be0: 93 06 f7 ff addi a3, a4, -1 +80014be4: 13 06 01 02 addi a2, sp, 32 +80014be8: 13 17 27 00 slli a4, a4, 2 +80014bec: 33 07 e6 00 add a4, a2, a4 +80014bf0: b3 17 f4 00 sll a5, s0, a5 +80014bf4: 23 28 f7 fe sw a5, -16(a4) +80014bf8: 6f 00 40 03 j 52 +80014bfc: 93 07 30 00 addi a5, zero, 3 +80014c00: b3 87 e7 40 sub a5, a5, a4 +80014c04: 93 06 01 02 addi a3, sp, 32 +80014c08: 93 97 27 00 slli a5, a5, 2 +80014c0c: b3 87 f6 00 add a5, a3, a5 +80014c10: 83 a7 07 ff lw a5, -16(a5) +80014c14: 93 06 20 00 addi a3, zero, 2 +80014c18: 23 2e f1 00 sw a5, 28(sp) +80014c1c: 93 07 20 00 addi a5, zero, 2 +80014c20: 63 16 f7 00 bne a4, a5, 12 +80014c24: 23 2c 81 00 sw s0, 24(sp) +80014c28: 93 06 10 00 addi a3, zero, 1 +80014c2c: 93 07 f0 ff addi a5, zero, -1 +80014c30: 13 97 26 00 slli a4, a3, 2 +80014c34: 13 06 01 01 addi a2, sp, 16 +80014c38: 33 07 e6 00 add a4, a2, a4 +80014c3c: 23 20 07 00 sw zero, 0(a4) +80014c40: 93 86 f6 ff addi a3, a3, -1 +80014c44: e3 96 f6 fe bne a3, a5, -20 +80014c48: 83 27 c1 01 lw a5, 28(sp) +80014c4c: 83 20 c1 02 lw ra, 44(sp) +80014c50: 03 24 81 02 lw s0, 40(sp) +80014c54: 23 16 f1 00 sh a5, 12(sp) +80014c58: 93 17 f9 00 slli a5, s2, 15 +80014c5c: b3 e5 b7 00 or a1, a5, a1 +80014c60: 83 27 01 01 lw a5, 16(sp) +80014c64: 23 17 b1 00 sh a1, 14(sp) +80014c68: 03 29 01 02 lw s2, 32(sp) +80014c6c: 23 a0 f4 00 sw a5, 0(s1) +80014c70: 83 27 41 01 lw a5, 20(sp) +80014c74: 13 85 04 00 mv a0, s1 +80014c78: 23 a2 f4 00 sw a5, 4(s1) +80014c7c: 83 27 81 01 lw a5, 24(sp) +80014c80: 23 a4 f4 00 sw a5, 8(s1) +80014c84: 83 27 c1 00 lw a5, 12(sp) +80014c88: 23 a6 f4 00 sw a5, 12(s1) +80014c8c: 83 24 41 02 lw s1, 36(sp) +80014c90: 13 01 01 03 addi sp, sp, 48 +80014c94: 67 80 00 00 ret +80014c98: 13 07 30 00 addi a4, zero, 3 +80014c9c: 6f f0 5f f4 j -188 +80014ca0: 23 2e 01 00 sw zero, 28(sp) +80014ca4: 23 2c 01 00 sw zero, 24(sp) +80014ca8: 23 2a 01 00 sw zero, 20(sp) +80014cac: 23 28 01 00 sw zero, 16(sp) +80014cb0: 13 09 00 00 mv s2, zero +80014cb4: 6f f0 5f f9 j -108 + +80014cb8 __extendsfdf2: +80014cb8: 13 01 01 ff addi sp, sp, -16 +80014cbc: d3 07 05 e0 fmv.x.w a5, fa0 +80014cc0: 23 26 11 00 sw ra, 12(sp) +80014cc4: 23 24 81 00 sw s0, 8(sp) +80014cc8: 23 22 91 00 sw s1, 4(sp) +80014ccc: 23 20 21 01 sw s2, 0(sp) +80014cd0: 73 27 20 00 frrm a4 +80014cd4: 13 d5 77 01 srli a0, a5, 23 +80014cd8: 13 75 f5 0f andi a0, a0, 255 +80014cdc: 13 09 15 00 addi s2, a0, 1 +80014ce0: 13 94 97 00 slli s0, a5, 9 +80014ce4: 13 79 e9 0f andi s2, s2, 254 +80014ce8: 13 54 94 00 srli s0, s0, 9 +80014cec: 93 d4 f7 01 srli s1, a5, 31 +80014cf0: 63 0a 09 04 beqz s2, 84 +80014cf4: 93 57 34 00 srli a5, s0, 3 +80014cf8: 13 05 05 38 addi a0, a0, 896 +80014cfc: 13 14 d4 01 slli s0, s0, 29 +80014d00: 13 09 00 00 mv s2, zero +80014d04: 93 97 c7 00 slli a5, a5, 12 +80014d08: 13 15 45 01 slli a0, a0, 20 +80014d0c: 93 d7 c7 00 srli a5, a5, 12 +80014d10: b3 67 f5 00 or a5, a0, a5 +80014d14: 93 94 f4 01 slli s1, s1, 31 +80014d18: 33 e7 97 00 or a4, a5, s1 +80014d1c: 13 05 04 00 mv a0, s0 +80014d20: 93 05 07 00 mv a1, a4 +80014d24: 63 04 09 00 beqz s2, 8 +80014d28: 73 20 19 00 csrs fflags, s2 +80014d2c: 83 20 c1 00 lw ra, 12(sp) +80014d30: 03 24 81 00 lw s0, 8(sp) +80014d34: 83 24 41 00 lw s1, 4(sp) +80014d38: 03 29 01 00 lw s2, 0(sp) +80014d3c: 13 01 01 01 addi sp, sp, 16 +80014d40: 67 80 00 00 ret +80014d44: 63 14 05 04 bnez a0, 72 +80014d48: 63 08 04 06 beqz s0, 112 +80014d4c: 13 05 04 00 mv a0, s0 +80014d50: ef 00 80 77 jal 1912 +80014d54: 93 07 a0 00 addi a5, zero, 10 +80014d58: 63 c2 a7 02 blt a5, a0, 36 +80014d5c: 93 07 b0 00 addi a5, zero, 11 +80014d60: b3 87 a7 40 sub a5, a5, a0 +80014d64: 13 07 55 01 addi a4, a0, 21 +80014d68: b3 57 f4 00 srl a5, s0, a5 +80014d6c: 33 14 e4 00 sll s0, s0, a4 +80014d70: 13 07 90 38 addi a4, zero, 905 +80014d74: 33 05 a7 40 sub a0, a4, a0 +80014d78: 6f f0 df f8 j -116 +80014d7c: 93 07 55 ff addi a5, a0, -11 +80014d80: b3 17 f4 00 sll a5, s0, a5 +80014d84: 13 04 00 00 mv s0, zero +80014d88: 6f f0 9f fe j -24 +80014d8c: 93 07 00 00 mv a5, zero +80014d90: 63 00 04 02 beqz s0, 32 +80014d94: 93 17 94 00 slli a5, s0, 9 +80014d98: 63 c4 07 00 bltz a5, 8 +80014d9c: 13 09 00 01 addi s2, zero, 16 +80014da0: 93 57 34 00 srli a5, s0, 3 +80014da4: 37 07 08 00 lui a4, 128 +80014da8: 13 14 d4 01 slli s0, s0, 29 +80014dac: b3 e7 e7 00 or a5, a5, a4 +80014db0: 13 05 f0 7f addi a0, zero, 2047 +80014db4: 6f f0 1f f5 j -176 +80014db8: 93 07 00 00 mv a5, zero +80014dbc: 13 05 00 00 mv a0, zero +80014dc0: 6f f0 5f f4 j -188 + +80014dc4 __extenddftf2: +80014dc4: 13 01 01 fc addi sp, sp, -64 +80014dc8: 23 2a 91 02 sw s1, 52(sp) +80014dcc: 23 26 31 03 sw s3, 44(sp) +80014dd0: 23 2e 11 02 sw ra, 60(sp) +80014dd4: 23 2c 81 02 sw s0, 56(sp) +80014dd8: 23 28 21 03 sw s2, 48(sp) +80014ddc: 93 09 05 00 mv s3, a0 +80014de0: 93 84 05 00 mv s1, a1 +80014de4: f3 27 20 00 frrm a5 +80014de8: 13 59 46 01 srli s2, a2, 20 +80014dec: 93 17 c6 00 slli a5, a2, 12 +80014df0: 13 79 f9 7f andi s2, s2, 2047 +80014df4: 93 d7 c7 00 srli a5, a5, 12 +80014df8: 93 06 19 00 addi a3, s2, 1 +80014dfc: 23 28 b1 00 sw a1, 16(sp) +80014e00: 23 2a f1 00 sw a5, 20(sp) +80014e04: 23 2e 01 00 sw zero, 28(sp) +80014e08: 23 2c 01 00 sw zero, 24(sp) +80014e0c: 93 f6 e6 7f andi a3, a3, 2046 +80014e10: 13 54 f6 01 srli s0, a2, 31 +80014e14: 63 8a 06 08 beqz a3, 148 +80014e18: 93 d6 47 00 srli a3, a5, 4 +80014e1c: 37 47 00 00 lui a4, 4 +80014e20: 93 97 c7 01 slli a5, a5, 28 +80014e24: 13 d5 45 00 srli a0, a1, 4 +80014e28: 13 07 07 c0 addi a4, a4, -1024 +80014e2c: b3 e7 a7 00 or a5, a5, a0 +80014e30: 93 94 c5 01 slli s1, a1, 28 +80014e34: 33 07 e9 00 add a4, s2, a4 +80014e38: 23 2e d1 00 sw a3, 28(sp) +80014e3c: 23 2c f1 00 sw a5, 24(sp) +80014e40: 23 2a 91 00 sw s1, 20(sp) +80014e44: 23 28 01 00 sw zero, 16(sp) +80014e48: 13 09 00 00 mv s2, zero +80014e4c: 83 27 c1 01 lw a5, 28(sp) +80014e50: 13 14 f4 00 slli s0, s0, 15 +80014e54: 33 67 e4 00 or a4, s0, a4 +80014e58: 23 16 f1 00 sh a5, 12(sp) +80014e5c: 23 17 e1 00 sh a4, 14(sp) +80014e60: 83 25 01 01 lw a1, 16(sp) +80014e64: 03 26 41 01 lw a2, 20(sp) +80014e68: 83 26 81 01 lw a3, 24(sp) +80014e6c: 83 27 c1 00 lw a5, 12(sp) +80014e70: 63 04 09 00 beqz s2, 8 +80014e74: 73 20 19 00 csrs fflags, s2 +80014e78: 83 20 c1 03 lw ra, 60(sp) +80014e7c: 03 24 81 03 lw s0, 56(sp) +80014e80: 23 a0 b9 00 sw a1, 0(s3) +80014e84: 23 a2 c9 00 sw a2, 4(s3) +80014e88: 23 a4 d9 00 sw a3, 8(s3) +80014e8c: 23 a6 f9 00 sw a5, 12(s3) +80014e90: 83 24 41 03 lw s1, 52(sp) +80014e94: 03 29 01 03 lw s2, 48(sp) +80014e98: 13 85 09 00 mv a0, s3 +80014e9c: 83 29 c1 02 lw s3, 44(sp) +80014ea0: 13 01 01 04 addi sp, sp, 64 +80014ea4: 67 80 00 00 ret +80014ea8: 33 e5 b7 00 or a0, a5, a1 +80014eac: 63 16 09 0e bnez s2, 236 +80014eb0: 13 07 00 00 mv a4, zero +80014eb4: e3 0c 05 f8 beqz a0, -104 +80014eb8: 63 8c 07 04 beqz a5, 88 +80014ebc: 13 85 07 00 mv a0, a5 +80014ec0: ef 00 80 60 jal 1544 +80014ec4: 93 05 15 03 addi a1, a0, 49 +80014ec8: 93 d7 55 40 srai a5, a1, 5 +80014ecc: 93 f5 f5 01 andi a1, a1, 31 +80014ed0: 63 86 05 04 beqz a1, 76 +80014ed4: 93 06 c0 ff addi a3, zero, -4 +80014ed8: b3 86 d7 02 mul a3, a5, a3 +80014edc: 13 03 01 01 addi t1, sp, 16 +80014ee0: 13 08 00 02 addi a6, zero, 32 +80014ee4: 13 96 27 00 slli a2, a5, 2 +80014ee8: 33 08 b8 40 sub a6, a6, a1 +80014eec: 93 86 c6 00 addi a3, a3, 12 +80014ef0: b3 06 d3 00 add a3, t1, a3 +80014ef4: 63 10 d3 08 bne t1, a3, 128 +80014ef8: 13 07 01 02 addi a4, sp, 32 +80014efc: 33 06 c7 00 add a2, a4, a2 +80014f00: b3 95 b4 00 sll a1, s1, a1 +80014f04: 93 87 f7 ff addi a5, a5, -1 +80014f08: 23 28 b6 fe sw a1, -16(a2) +80014f0c: 6f 00 c0 03 j 60 +80014f10: ef 00 80 5b jal 1464 +80014f14: 13 05 05 02 addi a0, a0, 32 +80014f18: 6f f0 df fa j -84 +80014f1c: 13 06 c0 ff addi a2, zero, -4 +80014f20: 33 86 c7 02 mul a2, a5, a2 +80014f24: 13 07 c1 01 addi a4, sp, 28 +80014f28: 93 06 30 00 addi a3, zero, 3 +80014f2c: b3 05 c7 00 add a1, a4, a2 +80014f30: 83 a5 05 00 lw a1, 0(a1) +80014f34: 93 86 f6 ff addi a3, a3, -1 +80014f38: 13 07 c7 ff addi a4, a4, -4 +80014f3c: 23 22 b7 00 sw a1, 4(a4) +80014f40: e3 d6 f6 fe bge a3, a5, -20 +80014f44: 93 87 f7 ff addi a5, a5, -1 +80014f48: 93 06 f0 ff addi a3, zero, -1 +80014f4c: 13 97 27 00 slli a4, a5, 2 +80014f50: 13 06 01 01 addi a2, sp, 16 +80014f54: 33 07 e6 00 add a4, a2, a4 +80014f58: 23 20 07 00 sw zero, 0(a4) +80014f5c: 93 87 f7 ff addi a5, a5, -1 +80014f60: e3 96 d7 fe bne a5, a3, -20 +80014f64: 37 47 00 00 lui a4, 4 +80014f68: 13 07 c7 c0 addi a4, a4, -1012 +80014f6c: 33 07 a7 40 sub a4, a4, a0 +80014f70: 6f f0 df ed j -292 +80014f74: 03 a7 c6 ff lw a4, -4(a3) +80014f78: 83 a8 06 00 lw a7, 0(a3) +80014f7c: 33 8e c6 00 add t3, a3, a2 +80014f80: 33 57 07 01 srl a4, a4, a6 +80014f84: b3 98 b8 00 sll a7, a7, a1 +80014f88: 33 67 17 01 or a4, a4, a7 +80014f8c: 23 20 ee 00 sw a4, 0(t3) +80014f90: 93 86 c6 ff addi a3, a3, -4 +80014f94: 6f f0 1f f6 j -160 +80014f98: 63 04 05 04 beqz a0, 72 +80014f9c: 13 d7 37 01 srli a4, a5, 19 +80014fa0: 63 14 07 00 bnez a4, 8 +80014fa4: 93 06 00 01 addi a3, zero, 16 +80014fa8: 13 97 c7 01 slli a4, a5, 28 +80014fac: 13 d6 44 00 srli a2, s1, 4 +80014fb0: 33 67 c7 00 or a4, a4, a2 +80014fb4: 23 2c e1 00 sw a4, 24(sp) +80014fb8: 93 d7 47 00 srli a5, a5, 4 +80014fbc: 37 87 00 00 lui a4, 8 +80014fc0: 93 94 c4 01 slli s1, s1, 28 +80014fc4: b3 e7 e7 00 or a5, a5, a4 +80014fc8: 23 2a 91 00 sw s1, 20(sp) +80014fcc: 23 28 01 00 sw zero, 16(sp) +80014fd0: 23 2e f1 00 sw a5, 28(sp) +80014fd4: 13 89 06 00 mv s2, a3 +80014fd8: 13 07 f7 ff addi a4, a4, -1 +80014fdc: 6f f0 1f e7 j -400 +80014fe0: 13 09 00 00 mv s2, zero +80014fe4: 37 87 00 00 lui a4, 8 +80014fe8: 6f f0 1f ff j -16 + +80014fec __trunctfdf2: +80014fec: 13 01 01 fe addi sp, sp, -32 +80014ff0: 83 26 05 00 lw a3, 0(a0) +80014ff4: 03 27 45 00 lw a4, 4(a0) +80014ff8: 83 27 85 00 lw a5, 8(a0) +80014ffc: 03 26 c5 00 lw a2, 12(a0) +80015000: f3 25 20 00 frrm a1 +80015004: 23 24 f1 00 sw a5, 8(sp) +80015008: 23 2c f1 00 sw a5, 24(sp) +8001500c: 93 17 06 01 slli a5, a2, 16 +80015010: 93 18 16 00 slli a7, a2, 1 +80015014: 23 26 c1 00 sw a2, 12(sp) +80015018: 93 d7 07 01 srli a5, a5, 16 +8001501c: 13 56 f6 01 srli a2, a2, 31 +80015020: 23 20 d1 00 sw a3, 0(sp) +80015024: 23 28 d1 00 sw a3, 16(sp) +80015028: 23 22 e1 00 sw a4, 4(sp) +8001502c: 23 2a e1 00 sw a4, 20(sp) +80015030: 23 2e f1 00 sw a5, 28(sp) +80015034: 13 de 18 01 srli t3, a7, 17 +80015038: 13 05 06 00 mv a0, a2 +8001503c: 13 0f 01 01 addi t5, sp, 16 +80015040: 93 06 c1 01 addi a3, sp, 28 +80015044: 83 a7 06 00 lw a5, 0(a3) +80015048: 03 a7 c6 ff lw a4, -4(a3) +8001504c: 93 86 c6 ff addi a3, a3, -4 +80015050: 93 97 37 00 slli a5, a5, 3 +80015054: 13 57 d7 01 srli a4, a4, 29 +80015058: b3 e7 e7 00 or a5, a5, a4 +8001505c: 23 a2 f6 00 sw a5, 4(a3) +80015060: e3 12 df fe bne t5, a3, -28 +80015064: 83 27 01 01 lw a5, 16(sp) +80015068: b7 8f 00 00 lui t6, 8 +8001506c: 13 07 1e 00 addi a4, t3, 1 +80015070: 93 9e 37 00 slli t4, a5, 3 +80015074: 93 87 ef ff addi a5, t6, -2 +80015078: 23 28 d1 01 sw t4, 16(sp) +8001507c: 33 77 f7 00 and a4, a4, a5 +80015080: 63 00 07 2c beqz a4, 704 +80015084: b7 c8 ff ff lui a7, 1048572 +80015088: 93 88 08 40 addi a7, a7, 1024 +8001508c: b3 08 1e 01 add a7, t3, a7 +80015090: 93 07 e0 7f addi a5, zero, 2046 +80015094: 63 d2 17 11 bge a5, a7, 260 +80015098: 63 84 05 06 beqz a1, 104 +8001509c: 93 07 30 00 addi a5, zero, 3 +800150a0: 63 9a f5 04 bne a1, a5, 84 +800150a4: 63 0e 06 04 beqz a2, 92 +800150a8: 93 08 e0 7f addi a7, zero, 2046 +800150ac: 93 07 f0 ff addi a5, zero, -1 +800150b0: 13 03 f0 ff addi t1, zero, -1 +800150b4: 13 07 00 00 mv a4, zero +800150b8: 93 0e 50 00 addi t4, zero, 5 +800150bc: 93 06 20 00 addi a3, zero, 2 +800150c0: 93 ee 1e 00 ori t4, t4, 1 +800150c4: 63 8e d5 3a beq a1, a3, 956 +800150c8: 93 06 30 00 addi a3, zero, 3 +800150cc: 63 84 d5 3a beq a1, a3, 936 +800150d0: 63 9a 05 3a bnez a1, 948 +800150d4: 93 f6 f7 00 andi a3, a5, 15 +800150d8: 13 08 40 00 addi a6, zero, 4 +800150dc: 63 84 06 3b beq a3, a6, 936 +800150e0: 93 86 47 00 addi a3, a5, 4 +800150e4: b3 b7 f6 00 sltu a5, a3, a5 +800150e8: 33 03 f3 00 add t1, t1, a5 +800150ec: 93 87 06 00 mv a5, a3 +800150f0: 6f 00 40 39 j 916 +800150f4: 93 07 20 00 addi a5, zero, 2 +800150f8: e3 98 f5 fa bne a1, a5, -80 +800150fc: e3 06 06 fa beqz a2, -84 +80015100: 93 08 f0 7f addi a7, zero, 2047 +80015104: 93 07 00 00 mv a5, zero +80015108: 13 03 00 00 mv t1, zero +8001510c: 93 0e 50 00 addi t4, zero, 5 +80015110: 13 17 83 00 slli a4, t1, 8 +80015114: 63 5e 07 00 bgez a4, 28 +80015118: 93 88 18 00 addi a7, a7, 1 +8001511c: 13 07 f0 7f addi a4, zero, 2047 +80015120: 63 88 e8 36 beq a7, a4, 880 +80015124: 37 07 80 ff lui a4, 1046528 +80015128: 13 07 f7 ff addi a4, a4, -1 +8001512c: 33 73 e3 00 and t1, t1, a4 +80015130: 13 d7 37 00 srli a4, a5, 3 +80015134: 93 17 d3 01 slli a5, t1, 29 +80015138: b3 e7 e7 00 or a5, a5, a4 +8001513c: 13 07 f0 7f addi a4, zero, 2047 +80015140: 93 56 33 00 srli a3, t1, 3 +80015144: 63 9e e8 00 bne a7, a4, 28 +80015148: b3 e7 d7 00 or a5, a5, a3 +8001514c: 93 06 00 00 mv a3, zero +80015150: 63 88 07 00 beqz a5, 16 +80015154: b7 06 08 00 lui a3, 128 +80015158: 93 07 00 00 mv a5, zero +8001515c: 13 05 00 00 mv a0, zero +80015160: 37 07 f0 7f lui a4, 524032 +80015164: 93 98 48 01 slli a7, a7, 20 +80015168: 93 96 c6 00 slli a3, a3, 12 +8001516c: b3 f8 e8 00 and a7, a7, a4 +80015170: 93 d6 c6 00 srli a3, a3, 12 +80015174: 13 15 f5 01 slli a0, a0, 31 +80015178: b3 e6 d8 00 or a3, a7, a3 +8001517c: 33 e7 a6 00 or a4, a3, a0 +80015180: 93 05 07 00 mv a1, a4 +80015184: 13 85 07 00 mv a0, a5 +80015188: 63 84 0e 00 beqz t4, 8 +8001518c: 73 a0 1e 00 csrs fflags, t4 +80015190: 13 01 01 02 addi sp, sp, 32 +80015194: 67 80 00 00 ret +80015198: 63 54 10 07 blez a7, 104 +8001519c: 03 28 81 01 lw a6, 24(sp) +800151a0: 83 26 c1 01 lw a3, 28(sp) +800151a4: 03 27 41 01 lw a4, 20(sp) +800151a8: 93 57 c8 01 srli a5, a6, 28 +800151ac: 93 96 46 00 slli a3, a3, 4 +800151b0: b3 e6 f6 00 or a3, a3, a5 +800151b4: 93 17 47 00 slli a5, a4, 4 +800151b8: b3 e7 d7 01 or a5, a5, t4 +800151bc: 13 57 c7 01 srli a4, a4, 28 +800151c0: 13 18 48 00 slli a6, a6, 4 +800151c4: b3 37 f0 00 snez a5, a5 +800151c8: 33 67 07 01 or a4, a4, a6 +800151cc: b3 e7 e7 00 or a5, a5, a4 +800151d0: 23 2a d1 00 sw a3, 20(sp) +800151d4: 23 28 f1 00 sw a5, 16(sp) +800151d8: 83 27 01 01 lw a5, 16(sp) +800151dc: 03 23 41 01 lw t1, 20(sp) +800151e0: 63 82 08 18 beqz a7, 388 +800151e4: 13 07 00 00 mv a4, zero +800151e8: 93 0e 00 00 mv t4, zero +800151ec: 93 f6 77 00 andi a3, a5, 7 +800151f0: e3 96 06 ec bnez a3, -308 +800151f4: e3 0e 07 f0 beqz a4, -228 +800151f8: 13 f7 1e 00 andi a4, t4, 1 +800151fc: 6f 00 80 28 j 648 +80015200: 93 07 c0 fc addi a5, zero, -52 +80015204: 63 dc f8 00 bge a7, a5, 24 +80015208: 23 2a 01 00 sw zero, 20(sp) +8001520c: 93 07 10 00 addi a5, zero, 1 +80015210: 23 28 f1 00 sw a5, 16(sp) +80015214: 93 08 00 00 mv a7, zero +80015218: 6f f0 1f fc j -64 +8001521c: 83 27 c1 01 lw a5, 28(sp) +80015220: 37 07 08 00 lui a4, 128 +80015224: 93 0f 00 00 mv t6, zero +80015228: b3 62 f7 00 or t0, a4, a5 +8001522c: 93 07 d0 03 addi a5, zero, 61 +80015230: b3 88 17 41 sub a7, a5, a7 +80015234: 23 2e 51 00 sw t0, 28(sp) +80015238: 13 d3 58 40 srai t1, a7, 5 +8001523c: 13 07 0f 00 mv a4, t5 +80015240: 93 07 00 00 mv a5, zero +80015244: 03 28 07 00 lw a6, 0(a4) +80015248: 93 87 17 00 addi a5, a5, 1 +8001524c: 13 07 47 00 addi a4, a4, 4 +80015250: b3 ef 0f 01 or t6, t6, a6 +80015254: e3 18 f3 fe bne t1, a5, -16 +80015258: 13 f7 f8 01 andi a4, a7, 31 +8001525c: 13 18 23 00 slli a6, t1, 2 +80015260: 63 10 07 04 bnez a4, 64 +80015264: 13 07 30 00 addi a4, zero, 3 +80015268: 93 07 00 00 mv a5, zero +8001526c: 33 07 67 40 sub a4, a4, t1 +80015270: b3 88 06 01 add a7, a3, a6 +80015274: 83 a8 08 00 lw a7, 0(a7) +80015278: 93 87 17 00 addi a5, a5, 1 +8001527c: 93 86 46 00 addi a3, a3, 4 +80015280: 23 ae 16 ff sw a7, -4(a3) +80015284: e3 56 f7 fe bge a4, a5, -20 +80015288: 13 07 40 00 addi a4, zero, 4 +8001528c: 33 03 67 40 sub t1, a4, t1 +80015290: 93 07 10 00 addi a5, zero, 1 +80015294: 63 5e 60 04 blez t1, 92 +80015298: 93 07 03 00 mv a5, t1 +8001529c: 6f 00 40 05 j 84 +800152a0: 93 07 01 02 addi a5, sp, 32 +800152a4: b3 87 07 01 add a5, a5, a6 +800152a8: 83 a7 07 ff lw a5, -16(a5) +800152ac: 93 0e 00 02 addi t4, zero, 32 +800152b0: b3 8e ee 40 sub t4, t4, a4 +800152b4: b3 97 d7 01 sll a5, a5, t4 +800152b8: 93 06 30 00 addi a3, zero, 3 +800152bc: b3 ef ff 00 or t6, t6, a5 +800152c0: 33 08 0f 01 add a6, t5, a6 +800152c4: 13 0e 00 00 mv t3, zero +800152c8: b3 86 66 40 sub a3, a3, t1 +800152cc: 13 08 48 00 addi a6, a6, 4 +800152d0: 63 44 de 04 blt t3, a3, 72 +800152d4: 93 96 26 00 slli a3, a3, 2 +800152d8: 13 08 01 02 addi a6, sp, 32 +800152dc: 93 07 40 00 addi a5, zero, 4 +800152e0: b3 06 d8 00 add a3, a6, a3 +800152e4: 33 d7 e2 00 srl a4, t0, a4 +800152e8: b3 87 67 40 sub a5, a5, t1 +800152ec: 23 a8 e6 fe sw a4, -16(a3) +800152f0: 93 06 40 00 addi a3, zero, 4 +800152f4: 13 97 27 00 slli a4, a5, 2 +800152f8: 33 07 ef 00 add a4, t5, a4 +800152fc: 23 20 07 00 sw zero, 0(a4) +80015300: 93 87 17 00 addi a5, a5, 1 +80015304: e3 98 d7 fe bne a5, a3, -16 +80015308: 03 27 01 01 lw a4, 16(sp) +8001530c: b3 37 f0 01 snez a5, t6 +80015310: b3 67 f7 00 or a5, a4, a5 +80015314: 6f f0 df ef j -260 +80015318: 83 28 c8 ff lw a7, -4(a6) +8001531c: 83 23 08 00 lw t2, 0(a6) +80015320: 93 17 2e 00 slli a5, t3, 2 +80015324: b3 d8 e8 00 srl a7, a7, a4 +80015328: b3 93 d3 01 sll t2, t2, t4 +8001532c: b3 07 ff 00 add a5, t5, a5 +80015330: b3 e8 78 00 or a7, a7, t2 +80015334: 23 a0 17 01 sw a7, 0(a5) +80015338: 13 0e 1e 00 addi t3, t3, 1 +8001533c: 6f f0 1f f9 j -112 +80015340: 83 28 41 01 lw a7, 20(sp) +80015344: 03 28 81 01 lw a6, 24(sp) +80015348: 03 2f c1 01 lw t5, 28(sp) +8001534c: b3 66 18 01 or a3, a6, a7 +80015350: b3 e6 e6 01 or a3, a3, t5 +80015354: 33 e3 d6 01 or t1, a3, t4 +80015358: 63 1a 0e 06 bnez t3, 116 +8001535c: b3 37 60 00 snez a5, t1 +80015360: 13 03 00 00 mv t1, zero +80015364: 33 67 f3 00 or a4, t1, a5 +80015368: 63 0c 07 0e beqz a4, 248 +8001536c: 93 d6 f7 01 srli a3, a5, 31 +80015370: 13 17 13 00 slli a4, t1, 1 +80015374: 33 07 d7 00 add a4, a4, a3 +80015378: 93 96 17 00 slli a3, a5, 1 +8001537c: 13 f8 76 00 andi a6, a3, 7 +80015380: 93 0e 00 00 mv t4, zero +80015384: 63 0a 08 02 beqz a6, 52 +80015388: 13 08 20 00 addi a6, zero, 2 +8001538c: 63 84 05 0b beq a1, a6, 168 +80015390: 13 08 30 00 addi a6, zero, 3 +80015394: 63 82 05 09 beq a1, a6, 132 +80015398: 93 0e 10 00 addi t4, zero, 1 +8001539c: 63 9e 05 00 bnez a1, 28 +800153a0: 13 f8 f6 00 andi a6, a3, 15 +800153a4: 93 08 40 00 addi a7, zero, 4 +800153a8: 63 08 18 01 beq a6, a7, 16 +800153ac: 93 b6 c6 ff sltiu a3, a3, -4 +800153b0: 93 c6 16 00 xori a3, a3, 1 +800153b4: 33 07 d7 00 add a4, a4, a3 +800153b8: 13 57 87 01 srli a4, a4, 24 +800153bc: 13 47 17 00 xori a4, a4, 1 +800153c0: 13 77 17 00 andi a4, a4, 1 +800153c4: 93 08 00 00 mv a7, zero +800153c8: 6f f0 5f e2 j -476 +800153cc: 63 02 03 08 beqz t1, 132 +800153d0: 93 8f ff ff addi t6, t6, -1 +800153d4: 93 0e 00 00 mv t4, zero +800153d8: 63 1a fe 01 bne t3, t6, 20 +800153dc: b7 0e 04 00 lui t4, 64 +800153e0: b3 7e df 01 and t4, t5, t4 +800153e4: 93 be 1e 00 seqz t4, t4 +800153e8: 93 9e 4e 00 slli t4, t4, 4 +800153ec: 93 d7 c8 01 srli a5, a7, 28 +800153f0: 13 1f 4f 00 slli t5, t5, 4 +800153f4: 93 18 48 00 slli a7, a6, 4 +800153f8: 13 58 c8 01 srli a6, a6, 28 +800153fc: b3 e7 17 01 or a5, a5, a7 +80015400: 33 68 e8 01 or a6, a6, t5 +80015404: b7 06 40 00 lui a3, 1024 +80015408: 93 f7 87 ff andi a5, a5, -8 +8001540c: 33 63 d8 00 or t1, a6, a3 +80015410: 93 08 f0 7f addi a7, zero, 2047 +80015414: 6f f0 9f dd j -552 +80015418: 93 0e 06 00 mv t4, a2 +8001541c: e3 1e 06 f8 bnez a2, -100 +80015420: 93 b6 86 ff sltiu a3, a3, -8 +80015424: 93 c6 16 00 xori a3, a3, 1 +80015428: 33 07 d7 00 add a4, a4, a3 +8001542c: 93 0e 10 00 addi t4, zero, 1 +80015430: 6f f0 9f f8 j -120 +80015434: 93 0e 10 00 addi t4, zero, 1 +80015438: e3 00 06 f8 beqz a2, -128 +8001543c: 93 b6 86 ff sltiu a3, a3, -8 +80015440: 93 c6 16 00 xori a3, a3, 1 +80015444: 33 07 d7 00 add a4, a4, a3 +80015448: 93 0e 06 00 mv t4, a2 +8001544c: 6f f0 df f6 j -148 +80015450: 93 07 00 00 mv a5, zero +80015454: 93 0e 00 00 mv t4, zero +80015458: 93 08 f0 7f addi a7, zero, 2047 +8001545c: 6f f0 5f cb j -844 +80015460: 93 07 00 00 mv a5, zero +80015464: 13 03 00 00 mv t1, zero +80015468: 93 08 00 00 mv a7, zero +8001546c: 93 0e 00 00 mv t4, zero +80015470: 6f f0 1f ca j -864 +80015474: 63 18 06 00 bnez a2, 16 +80015478: 93 86 87 00 addi a3, a5, 8 +8001547c: 6f f0 9f c6 j -920 +80015480: e3 1c 06 fe bnez a2, -8 +80015484: e3 06 07 c8 beqz a4, -884 +80015488: 93 ee 2e 00 ori t4, t4, 2 +8001548c: 6f f0 5f c8 j -892 +80015490: 93 07 00 00 mv a5, zero +80015494: 63 84 05 02 beqz a1, 40 +80015498: 13 07 30 00 addi a4, zero, 3 +8001549c: 63 9a e5 00 bne a1, a4, 20 +800154a0: 63 0e 06 00 beqz a2, 28 +800154a4: 93 07 f0 ff addi a5, zero, -1 +800154a8: 93 08 e0 7f addi a7, zero, 2046 +800154ac: 6f 00 00 01 j 16 +800154b0: 13 07 20 00 addi a4, zero, 2 +800154b4: e3 98 e5 fe bne a1, a4, -16 +800154b8: e3 06 06 fe beqz a2, -20 +800154bc: 93 ee 5e 00 ori t4, t4, 5 +800154c0: 13 83 07 00 mv t1, a5 +800154c4: 6f f0 df c6 j -916 + +800154c8 __clzsi2: +800154c8: b7 07 01 00 lui a5, 16 +800154cc: 63 7a f5 02 bgeu a0, a5, 52 +800154d0: 93 07 f0 0f addi a5, zero, 255 +800154d4: b3 b7 a7 00 sltu a5, a5, a0 +800154d8: 93 97 37 00 slli a5, a5, 3 +800154dc: 37 67 01 80 lui a4, 524310 +800154e0: 93 06 00 02 addi a3, zero, 32 +800154e4: b3 86 f6 40 sub a3, a3, a5 +800154e8: 33 55 f5 00 srl a0, a0, a5 +800154ec: 93 07 87 09 addi a5, a4, 152 +800154f0: 33 85 a7 00 add a0, a5, a0 +800154f4: 03 45 05 00 lbu a0, 0(a0) +800154f8: 33 85 a6 40 sub a0, a3, a0 +800154fc: 67 80 00 00 ret +80015500: 37 07 00 01 lui a4, 4096 +80015504: 93 07 00 01 addi a5, zero, 16 +80015508: e3 6a e5 fc bltu a0, a4, -44 +8001550c: 93 07 80 01 addi a5, zero, 24 +80015510: 6f f0 df fc j -52 + +Disassembly of section .rodata: + +80015518 .rodata: +80015518: 50 72 +8001551a: 69 6e +8001551c: 74 20 +8001551e: 54 65 +80015520: 73 74 21 20 csrrci s0, 514, 2 +80015524: 76 61 +80015526: 6c 75 +80015528: 65 5b +8001552a: 25 64 +8001552c: 5d 3d +8001552e: 25 64 +80015530: 0a 00 +80015532: 69 6e +80015534: 66 00 +80015536: 49 4e +80015538: 46 00 +8001553a: 6e 61 +8001553c: 6e 00 +8001553e: 4e 41 +80015540: 4e 00 +80015542: 20 70 +80015544: 72 69 +80015546: 6e 74 +80015548: 66 20 +8001554a: 66 6f +8001554c: 72 6d +8001554e: 61 74 +80015550: 20 73 +80015552: 74 72 +80015554: 69 6e +80015556: 67 20 65 72 +8001555a: 72 6f +8001555c: 72 3a +8001555e: 20 30 +80015560: 78 00 +80015562: 25 25 +80015564: 25 73 +80015566: 25 73 +80015568: 25 73 +8001556a: 25 73 +8001556c: 25 73 +8001556e: 25 2e +80015570: 30 64 +80015572: 25 73 +80015574: 25 2e +80015576: 30 64 +80015578: 25 63 +8001557a: 00 2d +8001557c: 00 2b +8001557e: 00 20 +80015580: 00 23 +80015582: 00 30 +80015584: 00 2e +80015586: 00 00 +80015588: 3a 55 +8001558a: 01 80 +8001558c: 3e 55 +8001558e: 01 80 +80015590: 32 55 +80015592: 01 80 +80015594: 36 55 +80015596: 01 80 +80015598: 49 4e +8001559a: 46 00 +8001559c: 69 6e +8001559e: 66 00 +800155a0: 4e 41 +800155a2: 4e 00 +800155a4: 6e 61 +800155a6: 6e 00 +800155a8: 30 31 +800155aa: 32 33 +800155ac: 34 35 +800155ae: 36 37 +800155b0: 38 39 +800155b2: 61 62 +800155b4: 63 64 65 66 bltu a0, t1, 1640 +800155b8: 00 00 +800155ba: 00 00 +800155bc: 30 31 +800155be: 32 33 +800155c0: 34 35 +800155c2: 36 37 +800155c4: 38 39 +800155c6: 41 42 +800155c8: 43 44 45 46 +800155cc: 00 00 +800155ce: 00 00 +800155d0: 28 6e +800155d2: 75 6c +800155d4: 6c 29 +800155d6: 00 00 +800155d8: 30 00 +800155da: 00 00 +800155dc: 00 44 +800155de: 00 80 +800155e0: ec 38 +800155e2: 00 80 +800155e4: ec 38 +800155e6: 00 80 +800155e8: f4 43 +800155ea: 00 80 +800155ec: ec 38 +800155ee: 00 80 +800155f0: ec 38 +800155f2: 00 80 +800155f4: ec 38 +800155f6: 00 80 +800155f8: 90 3a +800155fa: 00 80 +800155fc: ec 38 +800155fe: 00 80 +80015600: ec 38 +80015602: 00 80 +80015604: d0 43 +80015606: 00 80 +80015608: 70 43 +8001560a: 00 80 +8001560c: ec 38 +8001560e: 00 80 +80015610: 64 43 +80015612: 00 80 +80015614: 8c 43 +80015616: 00 80 +80015618: ec 38 +8001561a: 00 80 +8001561c: 80 43 +8001561e: 00 80 +80015620: bc 38 +80015622: 00 80 +80015624: bc 38 +80015626: 00 80 +80015628: bc 38 +8001562a: 00 80 +8001562c: bc 38 +8001562e: 00 80 +80015630: bc 38 +80015632: 00 80 +80015634: bc 38 +80015636: 00 80 +80015638: bc 38 +8001563a: 00 80 +8001563c: bc 38 +8001563e: 00 80 +80015640: bc 38 +80015642: 00 80 +80015644: ec 38 +80015646: 00 80 +80015648: ec 38 +8001564a: 00 80 +8001564c: ec 38 +8001564e: 00 80 +80015650: ec 38 +80015652: 00 80 +80015654: ec 38 +80015656: 00 80 +80015658: ec 38 +8001565a: 00 80 +8001565c: ec 38 +8001565e: 00 80 +80015660: 10 3c +80015662: 00 80 +80015664: ec 38 +80015666: 00 80 +80015668: 18 43 +8001566a: 00 80 +8001566c: f0 3a +8001566e: 00 80 +80015670: 10 3c +80015672: 00 80 +80015674: 10 3c +80015676: 00 80 +80015678: 10 3c +8001567a: 00 80 +8001567c: ec 38 +8001567e: 00 80 +80015680: ec 38 +80015682: 00 80 +80015684: ec 38 +80015686: 00 80 +80015688: ec 38 +8001568a: 00 80 +8001568c: 84 44 +8001568e: 00 80 +80015690: ec 38 +80015692: 00 80 +80015694: ec 38 +80015696: 00 80 +80015698: 78 3b +8001569a: 00 80 +8001569c: ec 38 +8001569e: 00 80 +800156a0: ec 38 +800156a2: 00 80 +800156a4: ec 38 +800156a6: 00 80 +800156a8: 90 42 +800156aa: 00 80 +800156ac: ec 38 +800156ae: 00 80 +800156b0: 18 44 +800156b2: 00 80 +800156b4: ec 38 +800156b6: 00 80 +800156b8: ec 38 +800156ba: 00 80 +800156bc: 74 4d +800156be: 00 80 +800156c0: ec 38 +800156c2: 00 80 +800156c4: ec 38 +800156c6: 00 80 +800156c8: ec 38 +800156ca: 00 80 +800156cc: ec 38 +800156ce: 00 80 +800156d0: ec 38 +800156d2: 00 80 +800156d4: ec 38 +800156d6: 00 80 +800156d8: ec 38 +800156da: 00 80 +800156dc: ec 38 +800156de: 00 80 +800156e0: 10 3c +800156e2: 00 80 +800156e4: ec 38 +800156e6: 00 80 +800156e8: 18 43 +800156ea: 00 80 +800156ec: f4 3a +800156ee: 00 80 +800156f0: 10 3c +800156f2: 00 80 +800156f4: 10 3c +800156f6: 00 80 +800156f8: 10 3c +800156fa: 00 80 +800156fc: a4 44 +800156fe: 00 80 +80015700: f4 3a +80015702: 00 80 +80015704: e4 3a +80015706: 00 80 +80015708: ec 38 +8001570a: 00 80 +8001570c: 90 44 +8001570e: 00 80 +80015710: ec 38 +80015712: 00 80 +80015714: b8 44 +80015716: 00 80 +80015718: 7c 3b +8001571a: 00 80 +8001571c: 48 44 +8001571e: 00 80 +80015720: e4 3a +80015722: 00 80 +80015724: ec 38 +80015726: 00 80 +80015728: 90 42 +8001572a: 00 80 +8001572c: dc 3a +8001572e: 00 80 +80015730: d0 4c +80015732: 00 80 +80015734: ec 38 +80015736: 00 80 +80015738: ec 38 +8001573a: 00 80 +8001573c: d8 4c +8001573e: 00 80 +80015740: ec 38 +80015742: 00 80 +80015744: dc 3a +80015746: 00 80 + +80015748 blanks.4470: +80015748: 20 20 +8001574a: 20 20 +8001574c: 20 20 +8001574e: 20 20 +80015750: 20 20 +80015752: 20 20 +80015754: 20 20 +80015756: 20 20 + +80015758 zeroes.4471: +80015758: 30 30 +8001575a: 30 30 +8001575c: 30 30 +8001575e: 30 30 +80015760: 30 30 +80015762: 30 30 +80015764: 30 30 +80015766: 30 30 +80015768: 20 4e +8001576a: 61 4e +8001576c: 20 00 +8001576e: 00 00 +80015770: 20 2d +80015772: 49 6e +80015774: 66 69 +80015776: 6e 69 +80015778: 74 79 +8001577a: 20 00 +8001577c: 20 49 +8001577e: 6e 66 +80015780: 69 6e +80015782: 69 74 +80015784: 79 20 +80015786: 00 00 +80015788: 4e 61 +8001578a: 4e 00 +8001578c: 45 25 +8001578e: 64 00 + +80015790 ezero: + ... + +800157a4 eone: + ... +800157b4: 00 80 +800157b6: ff 3f 76 65 + +800157b8 etens: +800157b8: 76 65 +800157ba: 92 4a +800157bc: 4a 80 +800157be: 3f 15 4c c9 +800157c2: 9a 97 +800157c4: 20 8a +800157c6: 02 52 +800157c8: 60 c4 +800157ca: 25 75 +800157cc: 32 6a +800157ce: 52 ce +800157d0: 9a 32 +800157d2: ce 28 +800157d4: 4d a7 +800157d6: e4 5d +800157d8: 3d c5 +800157da: 5d 3b +800157dc: 8b 9e 92 5a +800157e0: 6c 52 +800157e2: ce 50 +800157e4: 8b f1 28 3d +800157e8: 0d 65 +800157ea: 17 0c 75 81 auipc s8, 530256 +800157ee: 86 75 +800157f0: 76 c9 +800157f2: 48 4d +800157f4: 66 9c +800157f6: f8 58 +800157f8: 50 bc +800157fa: 54 5c +800157fc: 65 cc +800157fe: c6 91 +80015800: 0e a6 +80015802: ae a0 +80015804: 19 e3 +80015806: a3 46 1e 85 +8001580a: b7 ea fe 98 lui s5, 626670 +8001580e: 1b 90 bb dd +80015812: 8d de +80015814: f9 9d +80015816: fb eb 7e aa +8001581a: 51 43 +8001581c: 35 02 +8001581e: 37 01 b1 36 lui sp, 224016 +80015822: 6c 33 +80015824: 6f c6 df 8c jal a2, -14132 +80015828: e9 80 +8001582a: c9 47 +8001582c: ba 93 +8001582e: a8 41 +80015830: f8 50 +80015832: fb 25 6b c7 +80015836: 71 6b +80015838: bf 3c d5 a6 +8001583c: cf ff 49 1f +80015840: 78 c2 +80015842: d3 40 00 00 fadd.s ft1, ft0, ft0, rmm +80015846: 00 00 +80015848: 00 00 +8001584a: 00 00 +8001584c: 20 f0 +8001584e: 9d b5 +80015850: 70 2b +80015852: a8 ad +80015854: c5 9d +80015856: 69 40 + ... +80015864: 00 04 +80015866: bf c9 1b 8e +8001586a: 34 40 + ... +80015878: 00 00 +8001587a: 00 20 +8001587c: bc be +8001587e: 19 40 + ... +80015890: 40 9c +80015892: 0c 40 + ... +800158a4: 00 c8 +800158a6: 05 40 + ... +800158b8: 00 a0 +800158ba: 02 40 + +800158bc emtens: +800158bc: 30 20 +800158be: fc cf +800158c0: c3 a1 23 81 fmadd.s ft3, ft7, fs2, fa6, rdn +800158c4: e3 2d de 9f +800158c8: ce d2 +800158ca: c8 04 +800158cc: dd a6 +800158ce: d8 0a +800158d0: 64 82 +800158d2: cb d2 ea f2 +800158d6: d4 12 +800158d8: 25 49 +800158da: e4 2d +800158dc: 36 34 +800158de: 4f 53 ae ce +800158e2: 6b 25 3f f5 vx_tex a0, t5, s3, t5, rdn +800158e6: 98 f6 +800158e8: d3 6b 58 01 +800158ec: a6 87 +800158ee: bd c0 +800158f0: 57 da a5 82 +800158f4: a6 a2 +800158f6: b5 32 +800158f8: 31 e7 +800158fa: d4 04 +800158fc: f2 e3 +800158fe: 32 d3 +80015900: 32 71 +80015902: 1c d2 +80015904: 23 db 32 ee +80015908: 49 90 +8001590a: 5a 39 +8001590c: 3e a2 +8001590e: 08 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+8001598e: 2b 65 19 e2 +80015992: 58 17 +80015994: b7 d1 f1 3f lui gp, 261917 +80015998: 0a d7 +8001599a: a3 70 3d 0a +8001599e: d7 a3 70 3d +800159a2: 0a d7 +800159a4: a3 70 3d 0a +800159a8: d7 a3 f8 3f +800159ac: cd cc +800159ae: cc cc +800159b0: cc cc +800159b2: cc cc +800159b4: cc cc +800159b6: cc cc +800159b8: cc cc +800159ba: cc cc +800159bc: cc cc +800159be: fb 3f ff ff + +800159c0 bmask: +800159c0: ff ff fe ff +800159c4: fc ff +800159c6: f8 ff +800159c8: f0 ff +800159ca: e0 ff +800159cc: c0 ff +800159ce: 80 ff +800159d0: 00 ff +800159d2: 00 fe +800159d4: 00 fc +800159d6: 00 f8 +800159d8: 00 f0 +800159da: 00 e0 +800159dc: 00 c0 +800159de: 00 80 +800159e0: 00 00 +800159e2: 00 00 +800159e4: 42 61 +800159e6: 6c 6c +800159e8: 6f 63 20 73 jal t1, 26418 +800159ec: 75 63 +800159ee: 63 65 65 64 bltu a0, t1, 1610 +800159f2: 65 64 +800159f4: 00 00 +800159f6: 00 00 +800159f8: 2f 68 6f 6d +800159fc: 65 2f +800159fe: 62 6c +80015a00: 61 69 +80015a02: 73 65 2f 64 csrrsi a0, 1602, 30 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07 +800160dc: 07 07 07 07 +800160e0: 07 07 07 07 +800160e4: 07 07 07 07 +800160e8: 07 07 07 07 +800160ec: 07 07 07 07 +800160f0: 07 07 07 07 +800160f4: 07 07 07 07 +800160f8: 07 07 07 07 +800160fc: 07 07 07 07 +80016100: 07 07 07 07 +80016104: 07 07 07 07 +80016108: 07 07 07 07 +8001610c: 07 07 07 07 +80016110: 07 07 07 07 +80016114: 07 07 07 07 +80016118: 08 08 +8001611a: 08 08 +8001611c: 08 08 +8001611e: 08 08 +80016120: 08 08 +80016122: 08 08 +80016124: 08 08 +80016126: 08 08 +80016128: 08 08 +8001612a: 08 08 +8001612c: 08 08 +8001612e: 08 08 +80016130: 08 08 +80016132: 08 08 +80016134: 08 08 +80016136: 08 08 +80016138: 08 08 +8001613a: 08 08 +8001613c: 08 08 +8001613e: 08 08 +80016140: 08 08 +80016142: 08 08 +80016144: 08 08 +80016146: 08 08 +80016148: 08 08 +8001614a: 08 08 +8001614c: 08 08 +8001614e: 08 08 +80016150: 08 08 +80016152: 08 08 +80016154: 08 08 +80016156: 08 08 +80016158: 08 08 +8001615a: 08 08 +8001615c: 08 08 +8001615e: 08 08 +80016160: 08 08 +80016162: 08 08 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.init_array: + +800171d4 __preinit_array_start: +800171d4: 50 00 +800171d6: 00 80 + +Disassembly of section .data: + +800171d8 impure_data: +800171d8: 00 00 +800171da: 00 00 +800171dc: c4 74 +800171de: 01 80 +800171e0: 2c 75 +800171e2: 01 80 +800171e4: 94 75 +800171e6: 01 80 + ... +80017280: 01 00 +80017282: 00 00 +80017284: 00 00 +80017286: 00 00 +80017288: 0e 33 +8001728a: cd ab +8001728c: 34 12 +8001728e: 6d e6 +80017290: ec de +80017292: 05 00 +80017294: 0b 00 00 00 + ... + +80017600 __malloc_av_: + ... +80017608: 00 76 +8001760a: 01 80 +8001760c: 00 76 +8001760e: 01 80 +80017610: 08 76 +80017612: 01 80 +80017614: 08 76 +80017616: 01 80 +80017618: 10 76 +8001761a: 01 80 +8001761c: 10 76 +8001761e: 01 80 +80017620: 18 76 +80017622: 01 80 +80017624: 18 76 +80017626: 01 80 +80017628: 20 76 +8001762a: 01 80 +8001762c: 20 76 +8001762e: 01 80 +80017630: 28 76 +80017632: 01 80 +80017634: 28 76 +80017636: 01 80 +80017638: 30 76 +8001763a: 01 80 +8001763c: 30 76 +8001763e: 01 80 +80017640: 38 76 +80017642: 01 80 +80017644: 38 76 +80017646: 01 80 +80017648: 40 76 +8001764a: 01 80 +8001764c: 40 76 +8001764e: 01 80 +80017650: 48 76 +80017652: 01 80 +80017654: 48 76 +80017656: 01 80 +80017658: 50 76 +8001765a: 01 80 +8001765c: 50 76 +8001765e: 01 80 +80017660: 58 76 +80017662: 01 80 +80017664: 58 76 +80017666: 01 80 +80017668: 60 76 +8001766a: 01 80 +8001766c: 60 76 +8001766e: 01 80 +80017670: 68 76 +80017672: 01 80 +80017674: 68 76 +80017676: 01 80 +80017678: 70 76 +8001767a: 01 80 +8001767c: 70 76 +8001767e: 01 80 +80017680: 78 76 +80017682: 01 80 +80017684: 78 76 +80017686: 01 80 +80017688: 80 76 +8001768a: 01 80 +8001768c: 80 76 +8001768e: 01 80 +80017690: 88 76 +80017692: 01 80 +80017694: 88 76 +80017696: 01 80 +80017698: 90 76 +8001769a: 01 80 +8001769c: 90 76 +8001769e: 01 80 +800176a0: 98 76 +800176a2: 01 80 +800176a4: 98 76 +800176a6: 01 80 +800176a8: a0 76 +800176aa: 01 80 +800176ac: a0 76 +800176ae: 01 80 +800176b0: a8 76 +800176b2: 01 80 +800176b4: a8 76 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80 +800179ec: e0 79 +800179ee: 01 80 +800179f0: e8 79 +800179f2: 01 80 +800179f4: e8 79 +800179f6: 01 80 +800179f8: f0 79 +800179fa: 01 80 +800179fc: f0 79 +800179fe: 01 80 +80017a00: f8 79 +80017a02: 01 80 +80017a04: f8 79 +80017a06: 01 80 + +80017a08 __global_locale: +80017a08: 43 00 00 00 fmadd.s ft0, ft0, ft0, ft0, rne + ... +80017a28: 43 00 00 00 fmadd.s ft0, ft0, ft0, ft0, rne + ... +80017a48: 43 00 00 00 fmadd.s ft0, ft0, ft0, ft0, rne + ... +80017a68: 43 00 00 00 fmadd.s ft0, ft0, ft0, ft0, rne + ... +80017a88: 43 00 00 00 fmadd.s ft0, ft0, ft0, ft0, rne + ... +80017aa8: 43 00 00 00 fmadd.s ft0, ft0, ft0, ft0, rne + ... +80017ac8: 43 00 00 00 fmadd.s ft0, ft0, ft0, ft0, rne + ... +80017ae8: 1c e3 +80017aea: 00 80 +80017aec: 94 c5 +80017aee: 00 80 +80017af0: 00 00 +80017af2: 00 00 +80017af4: e0 5e +80017af6: 01 80 +80017af8: 50 5d +80017afa: 01 80 +80017afc: 10 5d +80017afe: 01 80 +80017b00: 10 5d +80017b02: 01 80 +80017b04: 10 5d +80017b06: 01 80 +80017b08: 10 5d +80017b0a: 01 80 +80017b0c: 10 5d +80017b0e: 01 80 +80017b10: 10 5d +80017b12: 01 80 +80017b14: 10 5d +80017b16: 01 80 +80017b18: 10 5d +80017b1a: 01 80 +80017b1c: 10 5d +80017b1e: 01 80 +80017b20: ff ff ff ff +80017b24: ff ff ff ff +80017b28: ff ff ff ff +80017b2c: ff ff 00 00 +80017b30: 01 00 +80017b32: 41 53 +80017b34: 43 49 49 00 fmadd.s fs2, fs2, ft4, ft0, rmm + ... +80017b50: 00 00 +80017b52: 41 53 +80017b54: 43 49 49 00 fmadd.s fs2, fs2, ft4, ft0, rmm + ... + +Disassembly of section .sdata: + +80017b78 __SDATA_BEGIN__: +80017b78: 00 00 +80017b7a: 00 00 +80017b7c: 00 00 +80017b7e: f0 3f +80017b80: 00 00 +80017b82: 00 00 +80017b84: 00 00 +80017b86: 24 40 +80017b88: 00 00 +80017b8a: 00 00 +80017b8c: 00 00 +80017b8e: 50 43 + +80017b90 _global_impure_ptr: +80017b90: d8 71 +80017b92: 01 80 +80017b94: 00 00 +80017b96: 80 ff +80017b98: 00 00 +80017b9a: 80 7f + +80017b9c _impure_ptr: +80017b9c: d8 71 +80017b9e: 01 80 + +80017ba0 __malloc_sbrk_base: +80017ba0: ff ff ff ff + +80017ba4 __malloc_trim_threshold: +80017ba4: 00 00 +80017ba6: 02 00 + +Disassembly of section .sbss: + +80017ba8 __malloc_max_total_mem: +... + +80017bac __malloc_max_sbrked_mem: +... + +80017bb0 __malloc_top_pad: +... + +Disassembly of section .bss: + +80017bb4 __malloc_current_mallinfo: +... + +80017bdc g_wspawn_args: +... + +80017c5c errno: +... + +Disassembly of section .comment: + +00000000 .comment: + 0: 63 6c 61 6e bltu sp, t1, 1784 + 4: 67 20 76 65 + 8: 72 73 + a: 69 6f + c: 6e 20 + e: 31 30 + 10: 2e 30 + 12: 2e 31 + 14: 20 28 + 16: 68 74 + 18: 74 70 + 1a: 73 3a 2f 2f csrrc s4, 754, t5 + 1e: 67 69 74 68 + 22: 75 62 + 24: 2e 63 + 26: 6f 6d 2f 6c jal s10, 1009346 + 2a: 6c 76 + 2c: 6d 2f + 2e: 6c 6c + 30: 76 6d + 32: 2d 70 + 34: 72 6f + 36: 6a 65 + 38: 63 74 2e 67 bgeu t3, s2, 1640 + 3c: 69 74 + 3e: 20 32 + 40: 61 32 + 42: 33 65 66 61 + 46: 63 33 35 32 + 4a: 66 39 + 4c: 31 39 + 4e: 65 62 + 50: 64 31 + 52: 65 63 + 54: 31 62 + 56: 65 34 + 58: 35 31 + 5a: 34 36 + 5c: 64 36 + 5e: 61 39 + 60: 66 61 + 62: 32 31 + 64: 62 35 + 66: 33 29 00 47 + 6a: 43 43 3a 20 fmadd.s ft6, fs4, ft3, ft4, rmm + 6e: 28 47 + 70: 4e 55 + 72: 29 20 + 74: 39 2e + 76: 32 2e + 78: 30 00 + +Disassembly of section .riscv.attributes: + +00000000 .riscv.attributes: + 0: 41 25 + 2: 00 00 + 4: 00 72 + 6: 69 73 + 8: 63 76 00 01 bgeu zero, a6, 12 + c: 1b 00 00 00 + 10: 04 10 + 12: 05 72 + 14: 76 33 + 16: 32 69 + 18: 32 70 + 1a: 30 5f + 1c: 6d 32 + 1e: 70 30 + 20: 5f 66 32 70 + 24: 30 00 + +Disassembly of section .debug_aranges: + +00000000 .debug_aranges: + 0: 1c 00 + 2: 00 00 + 4: 02 00 + 6: 00 00 + 8: 00 00 + a: 04 00 + c: 00 00 + e: 00 00 + 10: ac ff + 12: 00 80 + 14: 34 04 + ... + 1e: 00 00 + 20: 1c 00 + 22: 00 00 + 24: 02 00 + 26: 45 12 + 28: 00 00 + 2a: 04 00 + 2c: 00 00 + 2e: 00 00 + 30: e0 03 + 32: 01 80 + 34: 10 04 + ... + 3e: 00 00 + 40: 1c 00 + 42: 00 00 + 44: 02 00 + 46: e6 24 + 48: 00 00 + 4a: 04 00 + 4c: 00 00 + 4e: 00 00 + 50: f0 07 + 52: 01 80 + 54: c0 08 + ... + 5e: 00 00 + 60: 1c 00 + 62: 00 00 + 64: 02 00 + 66: 55 2c + 68: 00 00 + 6a: 04 00 + 6c: 00 00 + 6e: 00 00 + 70: b0 10 + 72: 01 80 + 74: a8 07 + ... + 7e: 00 00 + 80: 1c 00 + 82: 00 00 + 84: 02 00 + 86: f0 33 + 88: 00 00 + 8a: 04 00 + 8c: 00 00 + 8e: 00 00 + 90: 58 18 + 92: 01 80 + 94: 2c 01 + ... + 9e: 00 00 + a0: 1c 00 + a2: 00 00 + a4: 02 00 + a6: a0 36 + a8: 00 00 + aa: 04 00 + ac: 00 00 + ae: 00 00 + b0: 84 19 + b2: 01 80 + b4: 4c 01 + ... + be: 00 00 + c0: 1c 00 + c2: 00 00 + c4: 02 00 + c6: 38 39 + c8: 00 00 + ca: 04 00 + cc: 00 00 + ce: 00 00 + d0: d0 1a + d2: 01 80 + d4: 4c 01 + ... + de: 00 00 + e0: 1c 00 + e2: 00 00 + e4: 02 00 + e6: d0 3b + e8: 00 00 + ea: 04 00 + ec: 00 00 + ee: 00 00 + f0: 1c 1c + f2: 01 80 + f4: d8 12 + ... + fe: 00 00 + 100: 1c 00 + 102: 00 00 + 104: 02 00 + 106: e7 4e 00 00 + 10a: 04 00 + 10c: 00 00 + 10e: 00 00 + 110: f4 2e + 112: 01 80 + 114: c8 1a + ... + 11e: 00 00 + 120: 1c 00 + 122: 00 00 + 124: 02 00 + 126: 4b 5d 00 00 + 12a: 04 00 + 12c: 00 00 + 12e: 00 00 + 130: bc 49 + 132: 01 80 + 134: ac 01 + ... + 13e: 00 00 + 140: 1c 00 + 142: 00 00 + 144: 02 00 + 146: 1f 60 00 00 + 14a: 04 00 + 14c: 00 00 + 14e: 00 00 + 150: 68 4b + 152: 01 80 + 154: 50 01 + ... + 15e: 00 00 + 160: 1c 00 + 162: 00 00 + 164: 02 00 + 166: dd 63 + 168: 00 00 + 16a: 04 00 + 16c: 00 00 + 16e: 00 00 + 170: b8 4c + 172: 01 80 + 174: 0c 01 + ... + 17e: 00 00 + 180: 1c 00 + 182: 00 00 + 184: 02 00 + 186: 8c 66 + 188: 00 00 + 18a: 04 00 + 18c: 00 00 + 18e: 00 00 + 190: c4 4d + 192: 01 80 + 194: 28 02 + ... + 19e: 00 00 + 1a0: 1c 00 + 1a2: 00 00 + 1a4: 02 00 + 1a6: 8d 6a + 1a8: 00 00 + 1aa: 04 00 + 1ac: 00 00 + 1ae: 00 00 + 1b0: ec 4f + 1b2: 01 80 + 1b4: dc 04 + ... + 1be: 00 00 + 1c0: 14 00 + 1c2: 00 00 + 1c4: 02 00 + 1c6: 0f 70 00 00 + 1ca: 04 00 + ... + 1d8: 1c 00 + 1da: 00 00 + 1dc: 02 00 + 1de: 79 7b + 1e0: 00 00 + 1e2: 04 00 + 1e4: 00 00 + 1e6: 00 00 + 1e8: c8 54 + 1ea: 01 80 + 1ec: 4c 00 + ... + 1f6: 00 00 + +Disassembly of section .debug_info: + +00000000 .debug_info: + 0: 41 12 + 2: 00 00 + 4: 04 00 + 6: 00 00 + 8: 00 00 + a: 04 01 + c: ec 04 + e: 00 00 + 10: 0c 6d + 12: 04 00 + 14: 00 d5 + 16: 01 00 + 18: 00 ac + 1a: ff 00 80 34 + 1e: 04 00 + 20: 00 00 + 22: 00 00 + 24: 00 02 + 26: 08 07 + 28: ca 02 + 2a: 00 00 + 2c: 02 04 + 2e: 07 d4 02 00 + 32: 00 03 + 34: 04 05 + 36: 69 6e + 38: 74 00 + 3a: 02 08 + 3c: 05 f1 + 3e: 03 00 00 02 lb zero, 32(zero) + 42: 10 04 + 44: c0 00 + 46: 00 00 + 48: 02 01 + 4a: 06 ad + 4c: 06 00 + 4e: 00 02 + 50: 01 08 + 52: ab 06 00 00 + 56: 02 02 + 58: 05 00 + 5a: 00 00 + 5c: 00 02 + 5e: 02 07 + 60: ea 02 + 62: 00 00 + 64: 02 04 + 66: 05 f6 + 68: 03 00 00 02 lb zero, 32(zero) + 6c: 04 07 + 6e: cf 02 00 00 fnmadd.s ft5, ft0, ft0, ft0, rne + 72: 04 4a + 74: 03 00 00 02 lb zero, 32(zero) + 78: 5e 01 + 7a: 17 2c 00 00 auipc s8, 2 + 7e: 00 05 + 80: 25 04 + 82: 00 00 + 84: 03 2e 0e 64 lw t3, 1600(t3) + 88: 00 00 + 8a: 00 05 + 8c: 33 06 00 00 add a2, zero, zero + 90: 03 74 0e 64 + 94: 00 00 + 96: 00 05 + 98: 15 07 + 9a: 00 00 + 9c: 03 93 17 33 lh t1, 817(a5) + a0: 00 00 + a2: 00 06 + a4: 04 03 + a6: a5 03 + a8: c5 00 + aa: 00 00 + ac: 07 31 03 00 + b0: 00 03 + b2: a7 0c 72 00 + b6: 00 00 + b8: 07 9c 02 00 + bc: 00 03 + be: a8 13 + c0: c5 00 + c2: 00 00 + c4: 00 08 + c6: 4f 00 00 00 fnmadd.s ft0, ft0, ft0, ft0, rne + ca: d5 00 + cc: 00 00 + ce: 09 2c + d0: 00 00 + d2: 00 03 + d4: 00 0a + d6: 08 03 + d8: a2 09 + da: f9 00 + dc: 00 00 + de: 0b 9b 03 00 + e2: 00 03 + e4: a4 07 + e6: 33 00 00 00 add zero, zero, zero + ea: 00 0b + ec: 25 06 + ee: 00 00 + f0: 03 a9 05 a3 lw s2, -1488(a1) + f4: 00 00 + f6: 00 04 + f8: 00 05 + fa: 4a 04 + fc: 00 00 + fe: 03 aa 03 d5 lw s4, -688(t2) + 102: 00 00 + 104: 00 0c + 106: 04 05 + 108: be 06 + 10a: 00 00 + 10c: 04 16 + 10e: 19 6b + 110: 00 00 + 112: 00 05 + 114: 55 04 + 116: 00 00 + 118: 05 0c + 11a: 0d 33 + 11c: 00 00 + 11e: 00 05 + 120: cb 04 00 00 fnmsub.s fs1, ft0, ft0, ft0, rne + 124: 04 23 + 126: 1b 13 01 00 + 12a: 00 0d + 12c: d4 03 + 12e: 00 00 + 130: 18 04 + 132: 34 08 + 134: 85 01 + 136: 00 00 + 138: 0b d5 07 00 + 13c: 00 04 + 13e: 36 13 + 140: 85 01 + 142: 00 00 + 144: 00 0e + 146: 5f 6b 00 04 + 14a: 37 07 33 00 lui a4, 816 + 14e: 00 00 + 150: 04 0b + 152: 02 06 + 154: 00 00 + 156: 04 37 + 158: 0b 33 00 00 + 15c: 00 08 + 15e: 0b 40 02 00 + 162: 00 04 + 164: 37 14 33 00 lui s0, 817 + 168: 00 00 + 16a: 0c 0b + 16c: 6b 01 00 00 vx_tex sp, zero, zero, zero, rne + 170: 04 37 + 172: 1b 33 00 00 + 176: 00 10 + 178: 0e 5f + 17a: 78 00 + 17c: 04 38 + 17e: 0b 8b 01 00 + 182: 00 14 + 184: 00 0f + 186: 04 2b + 188: 01 00 + 18a: 00 08 + 18c: 07 01 00 00 + 190: 9b 01 00 00 + 194: 09 2c + 196: 00 00 + 198: 00 00 + 19a: 00 0d + 19c: 7f 02 00 00 + 1a0: 24 04 + 1a2: 3c 08 + 1a4: 1e 02 + 1a6: 00 00 + 1a8: 0b f8 00 00 + 1ac: 00 04 + 1ae: 3e 09 + 1b0: 33 00 00 00 add zero, zero, zero + 1b4: 00 0b + 1b6: 73 07 00 00 + 1ba: 04 3f + 1bc: 09 33 + 1be: 00 00 + 1c0: 00 04 + 1c2: 0b 14 01 00 + 1c6: 00 04 + 1c8: 40 09 + 1ca: 33 00 00 00 add zero, zero, zero + 1ce: 08 0b + 1d0: c6 07 + 1d2: 00 00 + 1d4: 04 41 + 1d6: 09 33 + 1d8: 00 00 + 1da: 00 0c + 1dc: 0b ff 03 00 + 1e0: 00 04 + 1e2: 42 09 + 1e4: 33 00 00 00 add zero, zero, zero + 1e8: 10 0b + 1ea: 91 03 + 1ec: 00 00 + 1ee: 04 43 + 1f0: 09 33 + 1f2: 00 00 + 1f4: 00 14 + 1f6: 0b fe 06 00 + 1fa: 00 04 + 1fc: 44 09 + 1fe: 33 00 00 00 add zero, zero, zero + 202: 18 0b + 204: d4 04 + 206: 00 00 + 208: 04 45 + 20a: 09 33 + 20c: 00 00 + 20e: 00 1c + 210: 0b 59 07 00 + 214: 00 04 + 216: 46 09 + 218: 33 00 00 00 add zero, zero, zero + 21c: 20 00 + 21e: 10 31 + 220: 01 00 + 222: 00 08 + 224: 01 04 + 226: 4f 08 63 02 + 22a: 00 00 + 22c: 0b 33 02 00 + 230: 00 04 + 232: 50 0a + 234: 63 02 00 00 beqz zero, 4 + 238: 00 0b + 23a: a7 04 00 00 + 23e: 04 51 + 240: 09 63 + 242: 02 00 + 244: 00 80 + 246: 11 a2 + 248: 06 00 + 24a: 00 04 + 24c: 53 0a 07 01 fadd.s fs4, fa4, fa6, rne + 250: 00 00 + 252: 00 01 + 254: 11 63 + 256: 01 00 + 258: 00 04 + 25a: 56 0a + 25c: 07 01 00 00 + 260: 04 01 + 262: 00 08 + 264: 05 01 + 266: 00 00 + 268: 73 02 00 00 + 26c: 09 2c + 26e: 00 00 + 270: 00 1f + 272: 00 10 + 274: 08 04 + 276: 00 00 + 278: 90 01 + 27a: 04 62 + 27c: 08 b6 + 27e: 02 00 + 280: 00 0b + 282: d5 07 + 284: 00 00 + 286: 04 63 + 288: 12 b6 + 28a: 02 00 + 28c: 00 00 + 28e: 0b e9 05 00 + 292: 00 04 + 294: 64 06 + 296: 33 00 00 00 add zero, zero, zero + 29a: 04 0b + 29c: 3b 02 00 00 + 2a0: 04 66 + 2a2: 09 bc + 2a4: 02 00 + 2a6: 00 08 + 2a8: 0b 31 01 00 + 2ac: 00 04 + 2ae: 67 1e 1e 02 + 2b2: 00 00 + 2b4: 88 00 + 2b6: 0f 04 73 02 + 2ba: 00 00 + 2bc: 08 cc + 2be: 02 00 + 2c0: 00 cc + 2c2: 02 00 + 2c4: 00 09 + 2c6: 2c 00 + 2c8: 00 00 + 2ca: 1f 00 0f 04 + 2ce: d2 02 + 2d0: 00 00 + 2d2: 12 0d + 2d4: bf 07 00 00 + 2d8: 08 04 + 2da: 7a 08 + 2dc: fb 02 00 00 + 2e0: 0b 0e 01 00 + 2e4: 00 04 + 2e6: 7b 11 fb 02 + 2ea: 00 00 + 2ec: 00 0b + 2ee: 1c 00 + 2f0: 00 00 + 2f2: 04 7c + 2f4: 06 33 + 2f6: 00 00 + 2f8: 00 04 + 2fa: 00 0f + 2fc: 04 4f + 2fe: 00 00 + 300: 00 0d + 302: c5 05 + 304: 00 00 + 306: 68 04 + 308: ba 08 + 30a: 44 04 + 30c: 00 00 + 30e: 0e 5f + 310: 70 00 + 312: 04 bb + 314: 12 fb + 316: 02 00 + 318: 00 00 + 31a: 0e 5f + 31c: 72 00 + 31e: 04 bc + 320: 07 33 00 00 + 324: 00 04 + 326: 0e 5f + 328: 77 00 04 bd + 32c: 07 33 00 00 + 330: 00 08 + 332: 0b 5c 01 00 + 336: 00 04 + 338: be 09 + 33a: 56 00 + 33c: 00 00 + 33e: 0c 0b + 340: ab 02 00 00 + 344: 04 bf + 346: 09 56 + 348: 00 00 + 34a: 00 0e + 34c: 0e 5f + 34e: 62 66 + 350: 00 04 + 352: c0 11 + 354: d3 02 00 00 fadd.s ft5, ft0, ft0, rne + 358: 10 0b + 35a: a8 00 + 35c: 00 00 + 35e: 04 c1 + 360: 07 33 00 00 + 364: 00 18 + 366: 0b 3f 01 00 + 36a: 00 04 + 36c: c8 0a + 36e: 05 01 + 370: 00 00 + 372: 1c 0b + 374: 67 04 00 00 jalr s0, zero + 378: 04 ca + 37a: 1d c8 + 37c: 05 00 + 37e: 00 20 + 380: 0b 8a 03 00 + 384: 00 04 + 386: cc 1d + 388: f7 05 00 00 + 38c: 24 0b + 38e: 2d 06 + 390: 00 00 + 392: 04 cf + 394: 0d 1b + 396: 06 00 + 398: 00 28 + 39a: 0b 01 01 00 + 39e: 00 04 + 3a0: d0 09 + 3a2: 35 06 + 3a4: 00 00 + 3a6: 2c 0e + 3a8: 5f 75 62 00 + 3ac: 04 d3 + 3ae: 11 d3 + 3b0: 02 00 + 3b2: 00 30 + 3b4: 0e 5f + 3b6: 75 70 + 3b8: 00 04 + 3ba: d4 12 + 3bc: fb 02 00 00 + 3c0: 38 0e + 3c2: 5f 75 72 00 + 3c6: 04 d5 + 3c8: 07 33 00 00 + 3cc: 00 3c + 3ce: 0b 08 01 00 + 3d2: 00 04 + 3d4: d8 11 + 3d6: 3b 06 00 00 + 3da: 40 0b + 3dc: 41 07 + 3de: 00 00 + 3e0: 04 d9 + 3e2: 11 4b + 3e4: 06 00 + 3e6: 00 43 + 3e8: 0e 5f + 3ea: 6c 62 + 3ec: 00 04 + 3ee: dc 11 + 3f0: d3 02 00 00 fadd.s ft5, ft0, ft0, rne + 3f4: 44 0b + 3f6: 44 06 + 3f8: 00 00 + 3fa: 04 df + 3fc: 07 33 00 00 + 400: 00 4c + 402: 0b cc 03 00 + 406: 00 04 + 408: e0 0a + 40a: 7f 00 00 00 + 40e: 50 0b + 410: 5b 00 00 00 + 414: 04 e3 + 416: 12 62 + 418: 04 00 + 41a: 00 54 + 41c: 0b 51 03 00 + 420: 00 04 + 422: e7 0c 1f 01 jalr s9, 17(t5) + 426: 00 00 + 428: 58 0b + 42a: 93 02 00 00 mv t0, zero + 42e: 04 e9 + 430: 0e f9 + 432: 00 00 + 434: 00 5c + 436: 0b de 04 00 + 43a: 00 04 + 43c: ea 09 + 43e: 33 00 00 00 add zero, zero, zero + 442: 64 00 + 444: 13 97 00 00 slli a4, ra, 0 + 448: 00 62 + 44a: 04 00 + 44c: 00 14 + 44e: 62 04 + 450: 00 00 + 452: 14 05 + 454: 01 00 + 456: 00 14 + 458: b6 05 + 45a: 00 00 + 45c: 14 33 + 45e: 00 00 + 460: 00 00 + 462: 0f 04 6d 04 + 466: 00 00 + 468: 15 62 + 46a: 04 00 + 46c: 00 16 + 46e: 0a 06 + 470: 00 00 + 472: 28 04 + 474: 04 65 + 476: 02 08 + 478: b6 05 + 47a: 00 00 + 47c: 17 c4 04 00 auipc s0, 76 + 480: 00 04 + 482: 67 02 07 33 jalr tp, 816(a4) + 486: 00 00 + 488: 00 00 + 48a: 17 0e 07 00 auipc t3, 112 + 48e: 00 04 + 490: 6c 02 + 492: 0b a7 06 00 + 496: 00 04 + 498: 17 f6 06 00 auipc a2, 111 + 49c: 00 04 + 49e: 6c 02 + 4a0: 14 a7 + 4a2: 06 00 + 4a4: 00 08 + 4a6: 17 46 02 00 auipc a2, 36 + 4aa: 00 04 + 4ac: 6c 02 + 4ae: 1e a7 + 4b0: 06 00 + 4b2: 00 0c + 4b4: 17 e4 05 00 auipc s0, 94 + 4b8: 00 04 + 4ba: 6e 02 + 4bc: 08 33 + 4be: 00 00 + 4c0: 00 10 + 4c2: 17 2a 00 00 auipc s4, 2 + 4c6: 00 04 + 4c8: 6f 02 08 a7 jal tp, -523664 + 4cc: 08 00 + 4ce: 00 14 + 4d0: 17 66 02 00 auipc a2, 38 + 4d4: 00 04 + 4d6: 72 02 + 4d8: 07 33 00 00 + 4dc: 00 30 + 4de: 17 af 07 00 auipc t5, 122 + 4e2: 00 04 + 4e4: 73 02 16 bc + 4e8: 08 00 + 4ea: 00 34 + 4ec: 17 1a 04 00 auipc s4, 65 + 4f0: 00 04 + 4f2: 75 02 + 4f4: 07 33 00 00 + 4f8: 00 38 + 4fa: 17 f8 05 00 auipc a6, 95 + 4fe: 00 04 + 500: 77 02 0a cd + 504: 08 00 + 506: 00 3c + 508: 17 29 03 00 auipc s2, 50 + 50c: 00 04 + 50e: 7a 02 + 510: 13 85 01 00 mv a0, gp + 514: 00 40 + 516: 17 77 01 00 auipc a4, 23 + 51a: 00 04 + 51c: 7b 02 07 33 + 520: 00 00 + 522: 00 44 + 524: 17 aa 07 00 auipc s4, 122 + 528: 00 04 + 52a: 7c 02 + 52c: 13 85 01 00 mv a0, gp + 530: 00 48 + 532: 17 36 04 00 auipc a2, 67 + 536: 00 04 + 538: 7d 02 + 53a: 14 d3 + 53c: 08 00 + 53e: 00 4c + 540: 17 a3 02 00 auipc t1, 42 + 544: 00 04 + 546: 80 02 + 548: 07 33 00 00 + 54c: 00 50 + 54e: 17 ae 01 00 auipc t3, 26 + 552: 00 04 + 554: 81 02 + 556: 09 b6 + 558: 05 00 + 55a: 00 54 + 55c: 17 bd 04 00 auipc s10, 75 + 560: 00 04 + 562: a4 02 + 564: 07 82 08 00 + 568: 00 58 + 56a: 18 08 + 56c: 04 00 + 56e: 00 04 + 570: a8 02 + 572: 13 b6 02 00 sltiu a2, t0, 0 + 576: 00 48 + 578: 01 18 + 57a: 07 03 00 00 + 57e: 04 a9 + 580: 02 12 + 582: 73 02 00 00 + 586: 4c 01 + 588: 18 28 + 58a: 07 00 00 04 + 58e: ad 02 + 590: 0c e4 + 592: 08 00 + 594: 00 dc + 596: 02 18 + 598: 47 01 00 00 fmsub.s ft2, ft0, ft0, ft0, rne + 59c: 04 b2 + 59e: 02 10 + 5a0: 68 06 + 5a2: 00 00 + 5a4: e0 02 + 5a6: 18 2c + 5a8: 01 00 + 5aa: 00 04 + 5ac: b4 02 + 5ae: 0a f0 + 5b0: 08 00 + 5b2: 00 ec + 5b4: 02 00 + 5b6: 0f 04 bc 05 + 5ba: 00 00 + 5bc: 02 01 + 5be: 08 b4 + 5c0: 06 00 + 5c2: 00 15 + 5c4: bc 05 + 5c6: 00 00 + 5c8: 0f 04 44 04 + 5cc: 00 00 + 5ce: 13 97 00 00 slli a4, ra, 0 + 5d2: 00 ec + 5d4: 05 00 + 5d6: 00 14 + 5d8: 62 04 + 5da: 00 00 + 5dc: 14 05 + 5de: 01 00 + 5e0: 00 14 + 5e2: ec 05 + 5e4: 00 00 + 5e6: 14 33 + 5e8: 00 00 + 5ea: 00 00 + 5ec: 0f 04 c3 05 + 5f0: 00 00 + 5f2: 15 ec + 5f4: 05 00 + 5f6: 00 0f + 5f8: 04 ce + 5fa: 05 00 + 5fc: 00 13 + 5fe: 8b 00 00 00 + 602: 1b 06 00 00 + 606: 14 62 + 608: 04 00 + 60a: 00 14 + 60c: 05 01 + 60e: 00 00 + 610: 14 8b + 612: 00 00 + 614: 00 14 + 616: 33 00 00 00 add zero, zero, zero + 61a: 00 0f + 61c: 04 fd + 61e: 05 00 + 620: 00 13 + 622: 33 00 00 00 add zero, zero, zero + 626: 35 06 + 628: 00 00 + 62a: 14 62 + 62c: 04 00 + 62e: 00 14 + 630: 05 01 + 632: 00 00 + 634: 00 0f + 636: 04 21 + 638: 06 00 + 63a: 00 08 + 63c: 4f 00 00 00 fnmadd.s ft0, ft0, ft0, ft0, rne + 640: 4b 06 00 00 fnmsub.s fa2, ft0, ft0, ft0, rne + 644: 09 2c + 646: 00 00 + 648: 00 02 + 64a: 00 08 + 64c: 4f 00 00 00 fnmadd.s ft0, ft0, ft0, ft0, rne + 650: 5b 06 00 00 + 654: 09 2c + 656: 00 00 + 658: 00 00 + 65a: 00 04 + 65c: 70 01 + 65e: 00 00 + 660: 04 24 + 662: 01 1a + 664: 01 03 + 666: 00 00 + 668: 19 08 + 66a: 07 00 00 0c + 66e: 04 28 + 670: 01 08 + 672: a1 06 + 674: 00 00 + 676: 17 d5 07 00 auipc a0, 125 + 67a: 00 04 + 67c: 2a 01 + 67e: 11 a1 + 680: 06 00 + 682: 00 00 + 684: 17 c3 02 00 auipc t1, 44 + 688: 00 04 + 68a: 2b 01 07 33 + 68e: 00 00 + 690: 00 04 + 692: 17 e6 04 00 auipc a2, 78 + 696: 00 04 + 698: 2c 01 + 69a: 0b a7 06 00 + 69e: 00 08 + 6a0: 00 0f + 6a2: 04 68 + 6a4: 06 00 + 6a6: 00 0f + 6a8: 04 5b + 6aa: 06 00 + 6ac: 00 19 + 6ae: 22 00 + 6b0: 00 00 + 6b2: 0e 04 + 6b4: 44 01 + 6b6: 08 e6 + 6b8: 06 00 + 6ba: 00 17 + 6bc: 72 06 + 6be: 00 00 + 6c0: 04 45 + 6c2: 01 12 + 6c4: e6 06 + 6c6: 00 00 + 6c8: 00 17 + 6ca: 67 03 00 00 jalr t1, zero + 6ce: 04 46 + 6d0: 01 12 + 6d2: e6 06 + 6d4: 00 00 + 6d6: 06 17 + 6d8: b9 06 + 6da: 00 00 + 6dc: 04 47 + 6de: 01 12 + 6e0: 5d 00 + 6e2: 00 00 + 6e4: 0c 00 + 6e6: 08 5d + 6e8: 00 00 + 6ea: 00 f6 + 6ec: 06 00 + 6ee: 00 09 + 6f0: 2c 00 + 6f2: 00 00 + 6f4: 02 00 + 6f6: 1a d0 + 6f8: 04 85 + 6fa: 02 07 + 6fc: 0b 08 00 00 + 700: 17 a3 03 00 auipc t1, 58 + 704: 00 04 + 706: 87 02 18 2c + 70a: 00 00 + 70c: 00 00 + 70e: 17 8e 06 00 auipc t3, 104 + 712: 00 04 + 714: 88 02 + 716: 12 b6 + 718: 05 00 + 71a: 00 04 + 71c: 17 1c 03 00 auipc s8, 49 + 720: 00 04 + 722: 89 02 + 724: 10 0b + 726: 08 00 + 728: 00 08 + 72a: 17 64 07 00 auipc s0, 118 + 72e: 00 04 + 730: 8a 02 + 732: 17 9b 01 00 auipc s6, 25 + 736: 00 24 + 738: 17 4e 02 00 auipc t3, 36 + 73c: 00 04 + 73e: 8b 02 0f 33 + 742: 00 00 + 744: 00 48 + 746: 17 d0 07 00 auipc zero, 125 + 74a: 00 04 + 74c: 8c 02 + 74e: 2c 25 + 750: 00 00 + 752: 00 50 + 754: 17 7c 07 00 auipc s8, 119 + 758: 00 04 + 75a: 8d 02 + 75c: 1a ad + 75e: 06 00 + 760: 00 58 + 762: 17 d7 05 00 auipc a4, 93 + 766: 00 04 + 768: 8e 02 + 76a: 16 f9 + 76c: 00 00 + 76e: 00 68 + 770: 17 9c 07 00 auipc s8, 121 + 774: 00 04 + 776: 8f 02 16 f9 + 77a: 00 00 + 77c: 00 70 + 77e: 17 1e 01 00 auipc t3, 17 + 782: 00 04 + 784: 90 02 + 786: 16 f9 + 788: 00 00 + 78a: 00 78 + 78c: 17 1e 07 00 auipc t3, 113 + 790: 00 04 + 792: 91 02 + 794: 10 1b + 796: 08 00 + 798: 00 80 + 79a: 17 10 03 00 auipc zero, 49 + 79e: 00 04 + 7a0: 92 02 + 7a2: 10 2b + 7a4: 08 00 + 7a6: 00 88 + 7a8: 17 4e 00 00 auipc t3, 4 + 7ac: 00 04 + 7ae: 93 02 0f 33 addi t0, t5, 816 + 7b2: 00 00 + 7b4: 00 a0 + 7b6: 17 c7 01 00 auipc a4, 28 + 7ba: 00 04 + 7bc: 94 02 + 7be: 16 f9 + 7c0: 00 00 + 7c2: 00 a4 + 7c4: 17 e1 00 00 auipc sp, 14 + 7c8: 00 04 + 7ca: 95 02 + 7cc: 16 f9 + 7ce: 00 00 + 7d0: 00 ac + 7d2: 17 b6 01 00 auipc a2, 27 + 7d6: 00 04 + 7d8: 96 02 + 7da: 16 f9 + 7dc: 00 00 + 7de: 00 b4 + 7e0: 17 61 00 00 auipc sp, 6 + 7e4: 00 04 + 7e6: 97 02 16 f9 auipc t0, 1020256 + 7ea: 00 00 + 7ec: 00 bc + 7ee: 17 8d 00 00 auipc s10, 8 + 7f2: 00 04 + 7f4: 98 02 + 7f6: 16 f9 + 7f8: 00 00 + 7fa: 00 c4 + 7fc: 17 c2 04 00 auipc tp, 76 + 800: 00 04 + 802: 99 02 + 804: 08 33 + 806: 00 00 + 808: 00 cc + 80a: 00 08 + 80c: bc 05 + 80e: 00 00 + 810: 1b 08 00 00 + 814: 09 2c + 816: 00 00 + 818: 00 19 + 81a: 00 08 + 81c: bc 05 + 81e: 00 00 + 820: 2b 08 00 00 + 824: 09 2c + 826: 00 00 + 828: 00 07 + 82a: 00 08 + 82c: bc 05 + 82e: 00 00 + 830: 3b 08 00 00 + 834: 09 2c + 836: 00 00 + 838: 00 17 + 83a: 00 1a + 83c: f0 04 + 83e: 9e 02 + 840: 07 62 08 00 + 844: 00 17 + 846: dc 03 + 848: 00 00 + 84a: 04 a1 + 84c: 02 1b + 84e: 62 08 + 850: 00 00 + 852: 00 17 + 854: 5d 02 + 856: 00 00 + 858: 04 a2 + 85a: 02 18 + 85c: 72 08 + 85e: 00 00 + 860: 78 00 + 862: 08 fb + 864: 02 00 + 866: 00 72 + 868: 08 00 + 86a: 00 09 + 86c: 2c 00 + 86e: 00 00 + 870: 1d 00 + 872: 08 2c + 874: 00 00 + 876: 00 82 + 878: 08 00 + 87a: 00 09 + 87c: 2c 00 + 87e: 00 00 + 880: 1d 00 + 882: 1b f0 04 83 + 886: 02 03 + 888: a7 08 00 00 + 88c: 1c 0a + 88e: 06 00 + 890: 00 04 + 892: 9a 02 + 894: 0b f6 06 00 + 898: 00 1c + 89a: 47 07 00 00 fmsub.s fa4, ft0, ft0, ft0, rne + 89e: 04 a3 + 8a0: 02 0b + 8a2: 3b 08 00 00 + 8a6: 00 08 + 8a8: bc 05 + 8aa: 00 00 + 8ac: b7 08 00 00 lui a7, 0 + 8b0: 09 2c + 8b2: 00 00 + 8b4: 00 18 + 8b6: 00 1d + 8b8: d6 00 + 8ba: 00 00 + 8bc: 0f 04 b7 08 + 8c0: 00 00 + 8c2: 1e cd + 8c4: 08 00 + 8c6: 00 14 + 8c8: 62 04 + 8ca: 00 00 + 8cc: 00 0f + 8ce: 04 c2 + 8d0: 08 00 + 8d2: 00 0f + 8d4: 04 85 + 8d6: 01 00 + 8d8: 00 1e + 8da: e4 08 + 8dc: 00 00 + 8de: 14 33 + 8e0: 00 00 + 8e2: 00 00 + 8e4: 0f 04 ea 08 + 8e8: 00 00 + 8ea: 0f 04 d9 08 + 8ee: 00 00 + 8f0: 08 5b + 8f2: 06 00 + 8f4: 00 00 + 8f6: 09 00 + 8f8: 00 09 + 8fa: 2c 00 + 8fc: 00 00 + 8fe: 02 00 + 900: 1f e2 06 00 + 904: 00 04 + 906: 33 03 17 62 + 90a: 04 00 + 90c: 00 1f + 90e: db 06 00 00 + 912: 04 34 + 914: 03 1d 68 04 lh s10, 70(a6) + 918: 00 00 + 91a: 08 f2 + 91c: 05 00 + 91e: 00 25 + 920: 09 00 + 922: 00 20 + 924: 00 15 + 926: 1a 09 + 928: 00 00 + 92a: 21 a1 + 92c: 01 00 + 92e: 00 06 + 930: 14 24 + 932: 25 09 + 934: 00 00 + 936: 21 cd + 938: 05 00 + 93a: 00 06 + 93c: 15 15 + 93e: 33 00 00 00 add zero, zero, zero + 942: 0f 04 48 09 + 946: 00 00 + 948: 13 33 00 00 sltiu t1, zero, 0 + 94c: 00 5c + 94e: 09 00 + 950: 00 14 + 952: 5c 09 + 954: 00 00 + 956: 14 5c + 958: 09 00 + 95a: 00 00 + 95c: 0f 04 62 09 + 960: 00 00 + 962: 22 21 + 964: 10 04 + 966: 00 00 + 968: 07 67 0e b6 + 96c: 05 00 + 96e: 00 21 + 970: 42 03 + 972: 00 00 + 974: 08 10 + 976: 0f 7b 09 00 + 97a: 00 0f + 97c: 04 b6 + 97e: 05 00 + 980: 00 21 + 982: 13 04 00 00 mv s0, zero + 986: 08 fc + 988: 0e b6 + 98a: 05 00 + 98c: 00 21 + 98e: b1 00 + 990: 00 00 + 992: 08 fd + 994: 0c 33 + 996: 00 00 + 998: 00 21 + 99a: 78 06 + 99c: 00 00 + 99e: 08 fd + 9a0: 14 33 + 9a2: 00 00 + 9a4: 00 21 + 9a6: 8b 07 00 00 + 9aa: 08 fd + 9ac: 1c 33 + 9ae: 00 00 + 9b0: 00 21 + 9b2: 81 03 + 9b4: 00 00 + 9b6: 08 ff + 9b8: 0c 33 + 9ba: 00 00 + 9bc: 00 21 + 9be: 40 04 + 9c0: 00 00 + 9c2: 09 9a + 9c4: 16 64 + 9c6: 00 00 + 9c8: 00 21 + 9ca: 35 00 + 9cc: 00 00 + 9ce: 09 9b + 9d0: 15 33 + 9d2: 00 00 + 9d4: 00 08 + 9d6: b6 05 + 9d8: 00 00 + 9da: e5 09 + 9dc: 00 00 + 9de: 09 2c + 9e0: 00 00 + 9e2: 00 01 + 9e4: 00 21 + 9e6: f0 00 + 9e8: 00 00 + 9ea: 09 9e + 9ec: 17 d5 09 00 auipc a0, 157 + 9f0: 00 05 + 9f2: b1 02 + 9f4: 00 00 + 9f6: 0a 2a + 9f8: 16 2c + 9fa: 00 00 + 9fc: 00 05 + 9fe: bb 05 00 00 + a02: 0a 2f + a04: 15 09 + a06: 0a 00 + a08: 00 0f + a0a: 04 0f + a0c: 0a 00 + a0e: 00 13 + a10: f1 09 + a12: 00 00 + a14: 1e 0a + a16: 00 00 + a18: 14 5c + a1a: 09 00 + a1c: 00 00 + a1e: 05 db + a20: 07 00 00 0a + a24: 36 0f + a26: 42 09 + a28: 00 00 + a2a: 21 0a + a2c: 00 00 + a2e: 00 0a + a30: bb 12 fd 09 + a34: 00 00 + a36: 21 c6 + a38: 06 00 + a3a: 00 0a + a3c: be 10 + a3e: 1e 0a + a40: 00 00 + a42: 23 84 02 00 sb zero, 8(t0) + a46: 00 07 + a48: 04 2c + a4a: 00 00 + a4c: 00 0b + a4e: 18 06 + a50: 7f 0a 00 00 + a54: 24 9d + a56: 04 00 + a58: 00 00 + a5a: 24 5c + a5c: 03 00 00 01 lb zero, 16(zero) + a60: 24 37 + a62: 03 00 00 02 lb zero, 32(zero) + a66: 24 b0 + a68: 03 00 00 03 lb zero, 48(zero) + a6c: 24 94 + a6e: 04 00 + a70: 00 04 + a72: 24 92 + a74: 07 00 00 05 + a78: 24 81 + a7a: 07 00 00 06 + a7e: 00 21 + a80: cc 00 + a82: 00 00 + a84: 0b 21 1c 42 + a88: 0a 00 + a8a: 00 23 + a8c: bb 03 00 00 + a90: 07 04 2c 00 + a94: 00 00 + a96: 0b 23 06 b0 + a9a: 0a 00 + a9c: 00 24 + a9e: b1 05 + aa0: 00 00 + aa2: 00 24 + aa4: b3 04 00 00 add s1, zero, zero + aa8: 01 24 + aaa: 9b 06 00 00 + aae: 02 00 + ab0: 21 4f + ab2: 01 00 + ab4: 00 0b + ab6: 28 1e + ab8: 8b 0a 00 00 + abc: 23 70 00 00 + ac0: 00 07 + ac2: 04 2c + ac4: 00 00 + ac6: 00 0b + ac8: 2b 06 db 0a + acc: 00 00 + ace: 24 4d + ad0: 06 00 + ad2: 00 00 + ad4: 24 3b + ad6: 06 00 + ad8: 00 01 + ada: 00 21 + adc: 89 01 + ade: 00 00 + ae0: 0b 2f 2a bc + ae4: 0a 00 + ae6: 00 21 + ae8: 72 03 + aea: 00 00 + aec: 0c 29 + aee: 1a 25 + af0: 09 00 + af2: 00 21 + af4: 62 06 + af6: 00 00 + af8: 0c 38 + afa: 1a 25 + afc: 09 00 + afe: 00 05 + b00: b7 07 00 00 lui a5, 0 + b04: 0d 7b + b06: 16 4f + b08: 00 00 + b0a: 00 15 + b0c: ff 0a 00 00 + b10: 05 82 + b12: 01 00 + b14: 00 0d + b16: 80 0f + b18: 33 00 00 00 add zero, zero, zero + b1c: 05 81 + b1e: 01 00 + b20: 00 0d + b22: 81 16 + b24: 2c 00 + b26: 00 00 + b28: 05 ef + b2a: 06 00 + b2c: 00 0d + b2e: 84 0f + b30: 3a 00 + b32: 00 00 + b34: 05 ee + b36: 06 00 + b38: 00 0d + b3a: 85 16 + b3c: 25 00 + b3e: 00 00 + b40: 02 04 + b42: 04 eb + b44: 03 00 00 02 lb zero, 32(zero) + b48: 08 03 + b4a: e3 03 00 00 beqz zero, 2054 + b4e: 02 08 + b50: 04 c5 + b52: 00 00 + b54: 00 02 + b56: 10 03 + b58: 3f 00 00 00 + b5c: 02 20 + b5e: 03 b8 00 00 + b62: 00 19 + b64: e1 02 + b66: 00 00 + b68: 08 0d + b6a: ed 01 + b6c: 0a 8e + b6e: 0b 00 00 25 + b72: 6c 6f + b74: 77 00 0d ed + b78: 01 1a + b7a: 10 0b + b7c: 00 00 + b7e: 00 17 + b80: 7f 06 00 00 + b84: 0d ed + b86: 01 1f + b88: 10 0b + b8a: 00 00 + b8c: 04 00 + b8e: 1b 08 0d f4 + b92: 01 09 + b94: b0 0b + b96: 00 00 + b98: 26 73 + b9a: 00 0d + b9c: f6 01 + b9e: 13 63 0b 00 ori t1, s6, 0 + ba2: 00 26 + ba4: 6c 6c + ba6: 00 0d + ba8: f7 01 0a 28 + bac: 0b 00 00 00 + bb0: 04 bb + bb2: 02 00 + bb4: 00 0d + bb6: f8 01 + bb8: 03 8e 0b 00 lb t3, 0(s7) + bbc: 00 15 + bbe: b0 0b + bc0: 00 00 + bc2: 08 0b + bc4: 0b 00 00 d2 + bc8: 0b 00 00 09 + bcc: 2c 00 + bce: 00 00 + bd0: ff 00 15 c2 + bd4: 0b 00 00 1f + bd8: 32 07 + bda: 00 00 + bdc: 0d fc + bde: 01 16 + be0: d2 0b + be2: 00 00 + be4: 1f fd 02 00 + be8: 00 0d + bea: 02 02 + bec: 16 d2 + bee: 0b 00 00 27 + bf2: ee 05 + bf4: 00 00 + bf6: 01 26 + bf8: 05 01 + bfa: 34 0b + bfc: 00 00 + bfe: ac ff + c00: 00 80 + c02: 34 04 + c04: 00 00 + c06: 01 9c + c08: cd 0e + c0a: 00 00 + c0c: 28 6e + c0e: 00 01 + c10: 26 05 + c12: 14 34 + c14: 0b 00 00 00 + c18: 00 00 + c1a: 00 28 + c1c: 64 00 + c1e: 01 26 + c20: 05 1f + c22: 34 0b + c24: 00 00 + c26: 28 00 + c28: 00 00 + c2a: 29 cd + c2c: 0e 00 + c2e: 00 b0 + c30: ff 00 80 00 + c34: 00 00 + c36: 00 01 + c38: 28 05 + c3a: 0a 2a + c3c: f5 0e + c3e: 00 00 + c40: c0 00 + c42: 00 00 + c44: 2a ea + c46: 0e 00 + c48: 00 e0 + c4a: 00 00 + c4c: 00 2a + c4e: df 0e 00 00 + c52: 98 01 + c54: 00 00 + c56: 2b 00 00 00 + c5a: 00 2c + c5c: 01 0f + c5e: 00 00 + c60: 2c 0d + c62: 0f 00 00 2c + c66: 19 0f + c68: 00 00 + c6a: 2d 25 + c6c: 0f 00 00 70 + c70: 02 00 + c72: 00 2d + c74: 31 0f + c76: 00 00 + c78: 16 03 + c7a: 00 00 + c7c: 2d 3d + c7e: 0f 00 00 a2 + c82: 03 00 00 2d lb zero, 720(zero) + c86: 49 0f + c88: 00 00 + c8a: 12 04 + c8c: 00 00 + c8e: 2d 55 + c90: 0f 00 00 bf + c94: 04 00 + c96: 00 2d + c98: 61 0f + c9a: 00 00 + c9c: dd 04 + c9e: 00 00 + ca0: 2d 6d + ca2: 0f 00 00 fb + ca6: 04 00 + ca8: 00 2d + caa: 79 0f + cac: 00 00 + cae: 25 05 + cb0: 00 00 + cb2: 2d 84 + cb4: 0f 00 00 43 + cb8: 05 00 + cba: 00 2c + cbc: 90 0f + cbe: 00 00 + cc0: 2e 9c + cc2: 0f 00 00 28 + cc6: 00 00 + cc8: 00 e0 + cca: 0c 00 + ccc: 00 2d + cce: a1 0f + cd0: 00 00 + cd2: 82 05 + cd4: 00 00 + cd6: 2d ae + cd8: 0f 00 00 be + cdc: 05 00 + cde: 00 00 + ce0: 2f bc 0f 00 + ce4: 00 14 + ce6: 00 01 + ce8: 80 88 + cea: 00 00 + cec: 00 31 + cee: 0d 00 + cf0: 00 2d + cf2: c1 0f + cf4: 00 00 + cf6: d1 05 + cf8: 00 00 + cfa: 2d ce + cfc: 0f 00 00 e4 + d00: 05 00 + d02: 00 2d + d04: db 0f 00 00 + d08: 08 06 + d0a: 00 00 + d0c: 2d e8 + d0e: 0f 00 00 26 + d12: 06 00 + d14: 00 2d + d16: f5 0f + d18: 00 00 + d1a: 44 06 + d1c: 00 00 + d1e: 2d 02 + d20: 10 00 + d22: 00 7f + d24: 06 00 + d26: 00 2d + d28: 0f 10 00 00 fence.i + d2c: 9d 06 + d2e: 00 00 + d30: 00 2e + d32: 32 11 + d34: 00 00 + d36: 40 00 + d38: 00 00 + d3a: f0 0d + d3c: 00 00 + d3e: 2d 33 + d40: 11 00 + d42: 00 bb + d44: 06 00 + d46: 00 2d + d48: 3f 11 00 00 + d4c: ce 06 + d4e: 00 00 + d50: 2e 4b + d52: 11 00 + d54: 00 58 + d56: 00 00 + d58: 00 9d + d5a: 0d 00 + d5c: 00 2d + d5e: 50 11 + d60: 00 00 + d62: 0f 07 00 00 + d66: 2d 5d + d68: 11 00 + d6a: 00 31 + d6c: 07 00 00 2d + d70: 6a 11 + d72: 00 00 + d74: 55 07 + d76: 00 00 + d78: 2d 77 + d7a: 11 00 + d7c: 00 73 + d7e: 07 00 00 2d + d82: 84 11 + d84: 00 00 + d86: 91 07 + d88: 00 00 + d8a: 2d 91 + d8c: 11 00 + d8e: 00 cc + d90: 07 00 00 2d + d94: 9e 11 + d96: 00 00 + d98: f5 07 + d9a: 00 00 + d9c: 00 30 + d9e: ac 11 + da0: 00 00 + da2: 88 00 + da4: 00 00 + da6: 2d b1 + da8: 11 00 + daa: 00 27 + dac: 08 00 + dae: 00 2d + db0: be 11 + db2: 00 00 + db4: 3a 08 + db6: 00 00 + db8: 2d cb + dba: 11 00 + dbc: 00 8d + dbe: 08 00 + dc0: 00 2d + dc2: d8 11 + dc4: 00 00 + dc6: a0 08 + dc8: 00 00 + dca: 2d e5 + dcc: 11 00 + dce: 00 b3 + dd0: 08 00 + dd2: 00 2d + dd4: f2 11 + dd6: 00 00 + dd8: 06 09 + dda: 00 00 + ddc: 2d ff + dde: 11 00 + de0: 00 19 + de2: 09 00 + de4: 00 2d + de6: 0c 12 + de8: 00 00 + dea: 4a 09 + dec: 00 00 + dee: 00 00 + df0: 2e 1d + df2: 10 00 + df4: 00 b8 + df6: 00 00 + df8: 00 10 + dfa: 0e 00 + dfc: 00 2d + dfe: 22 10 + e00: 00 00 + e02: 5d 09 + e04: 00 00 + e06: 2d 2f + e08: 10 00 + e0a: 00 99 + e0c: 09 00 + e0e: 00 00 + e10: 2f 9e 10 00 + e14: 00 fc + e16: 00 01 + e18: 80 88 + e1a: 00 00 + e1c: 00 61 + e1e: 0e 00 + e20: 00 2d + e22: a3 10 00 00 sh zero, 1(zero) + e26: b7 09 00 00 lui s3, 0 + e2a: 2d b0 + e2c: 10 00 + e2e: 00 ca + e30: 09 00 + e32: 00 2d + e34: bd 10 + e36: 00 00 + e38: ee 09 + e3a: 00 00 + e3c: 2d ca + e3e: 10 00 + e40: 00 0c + e42: 0a 00 + e44: 00 2d + e46: d7 10 00 00 + e4a: 2a 0a + e4c: 00 00 + e4e: 2d e4 + e50: 10 00 + e52: 00 65 + e54: 0a 00 + e56: 00 2d + e58: f1 10 + e5a: 00 00 + e5c: 83 0a 00 00 lb s5, 0(zero) + e60: 00 2e + e62: 3d 10 + e64: 00 00 + e66: d0 00 + e68: 00 00 + e6a: ae 0e + e6c: 00 00 + e6e: 2d 42 + e70: 10 00 + e72: 00 a1 + e74: 0a 00 + e76: 00 2d + e78: 4f 10 00 00 fnmadd.s ft0, ft0, ft0, ft0, rtz + e7c: c3 0a 00 00 fmadd.s fs5, ft0, ft0, ft0, rne + e80: 2d 5c + e82: 10 00 + e84: 00 e7 + e86: 0a 00 + e88: 00 2d + e8a: 69 10 + e8c: 00 00 + e8e: 05 0b + e90: 00 00 + e92: 2d 76 + e94: 10 00 + e96: 00 23 + e98: 0b 00 00 2d + e9c: 83 10 00 00 lh ra, 0(zero) + ea0: 57 0b 00 00 + ea4: 2d 90 + ea6: 10 00 + ea8: 00 80 + eaa: 0b 00 00 00 + eae: 30 ff + eb0: 10 00 + eb2: 00 e8 + eb4: 00 00 + eb6: 00 2d + eb8: 04 11 + eba: 00 00 + ebc: ae 0b + ebe: 00 00 + ec0: 2d 11 + ec2: 11 00 + ec4: 00 e2 + ec6: 0b 00 00 00 + eca: 00 00 + ecc: 00 31 + ece: 55 06 + ed0: 00 00 + ed2: 01 f7 + ed4: 03 01 34 0b lb sp, 179(s0) + ed8: 00 00 + eda: 03 3e 12 00 + ede: 00 32 + ee0: 6e 00 + ee2: 01 f7 + ee4: 03 17 34 0b lh a4, 179(s0) + ee8: 00 00 + eea: 32 64 + eec: 00 01 + eee: f7 03 22 34 + ef2: 0b 00 00 32 + ef6: 72 70 + ef8: 00 01 + efa: f7 03 2e 3e + efe: 12 00 + f00: 00 33 + f02: 6e 6e + f04: 00 01 + f06: f9 03 + f08: 11 bd + f0a: 0b 00 00 33 + f0e: 64 64 + f10: 00 01 + f12: fa 03 + f14: 11 bd + f16: 0b 00 00 33 + f1a: 72 72 + f1c: 00 01 + f1e: fb 03 0b b0 + f22: 0b 00 00 33 + f26: 64 30 + f28: 00 01 + f2a: fc 03 + f2c: 0a 1c + f2e: 0b 00 00 33 + f32: 64 31 + f34: 00 01 + f36: fc 03 + f38: 0e 1c + f3a: 0b 00 00 33 + f3e: 6e 30 + f40: 00 01 + f42: fc 03 + f44: 12 1c + f46: 0b 00 00 33 + f4a: 6e 31 + f4c: 00 01 + f4e: fc 03 + f50: 16 1c + f52: 0b 00 00 33 + f56: 6e 32 + f58: 00 01 + f5a: fc 03 + f5c: 1a 1c + f5e: 0b 00 00 33 + f62: 71 30 + f64: 00 01 + f66: fd 03 + f68: 0a 1c + f6a: 0b 00 00 33 + f6e: 71 31 + f70: 00 01 + f72: fd 03 + f74: 0e 1c + f76: 0b 00 00 33 + f7a: 62 00 + f7c: 01 fe + f7e: 03 0a 1c 0b lb s4, 177(s8) + f82: 00 00 + f84: 33 62 6d 00 or tp, s10, t1 + f88: 01 fe + f8a: 03 0d 1c 0b lb s10, 177(s8) + f8e: 00 00 + f90: 33 77 77 00 and a4, a4, t2 + f94: 01 c7 + f96: 04 11 + f98: bd 0b + f9a: 00 00 + f9c: 34 bc + f9e: 0f 00 00 35 + fa2: d6 06 + fa4: 00 00 + fa6: 01 2e + fa8: 04 04 + faa: 1c 0b + fac: 00 00 + fae: 33 5f 5f 61 + fb2: 00 01 + fb4: 2e 04 + fb6: 04 1c + fb8: 0b 00 00 00 + fbc: 34 1d + fbe: 10 00 + fc0: 00 35 + fc2: a3 00 00 00 sb zero, 1(zero) + fc6: 01 3a + fc8: 04 04 + fca: 1c 0b + fcc: 00 00 + fce: 35 9e + fd0: 00 00 + fd2: 00 01 + fd4: 3a 04 + fd6: 04 1c + fd8: 0b 00 00 35 + fdc: 89 06 + fde: 00 00 + fe0: 01 3a + fe2: 04 04 + fe4: 1c 0b + fe6: 00 00 + fe8: 35 84 + fea: 06 00 + fec: 00 01 + fee: 3a 04 + ff0: 04 1c + ff2: 0b 00 00 35 + ff6: 54 07 + ff8: 00 00 + ffa: 01 3a + ffc: 04 04 + ffe: 1c 0b + 1000: 00 00 + 1002: 35 4f + 1004: 07 00 00 01 + 1008: 3a 04 + 100a: 04 1c + 100c: 0b 00 00 33 + 1010: 5f 5f 6d 00 + 1014: 01 3a + 1016: 04 04 + 1018: 1c 0b + 101a: 00 00 + 101c: 00 34 + 101e: 3d 10 + 1020: 00 00 + 1022: 35 d6 + 1024: 06 00 + 1026: 00 01 + 1028: 46 04 + 102a: 04 1c + 102c: 0b 00 00 33 + 1030: 5f 5f 61 00 + 1034: 01 46 + 1036: 04 04 + 1038: 1c 0b + 103a: 00 00 + 103c: 00 34 + 103e: 9e 10 + 1040: 00 00 + 1042: 35 a3 + 1044: 00 00 + 1046: 00 01 + 1048: 5f 04 08 1c + 104c: 0b 00 00 35 + 1050: 9e 00 + 1052: 00 00 + 1054: 01 5f + 1056: 04 08 + 1058: 1c 0b + 105a: 00 00 + 105c: 35 89 + 105e: 06 00 + 1060: 00 01 + 1062: 5f 04 08 1c + 1066: 0b 00 00 35 + 106a: 84 06 + 106c: 00 00 + 106e: 01 5f + 1070: 04 08 + 1072: 1c 0b + 1074: 00 00 + 1076: 35 54 + 1078: 07 00 00 01 + 107c: 5f 04 08 1c + 1080: 0b 00 00 35 + 1084: 4f 07 00 00 fnmadd.s fa4, ft0, ft0, ft0, rne + 1088: 01 5f + 108a: 04 08 + 108c: 1c 0b + 108e: 00 00 + 1090: 33 5f 5f 6d + 1094: 00 01 + 1096: 5f 04 08 1c + 109a: 0b 00 00 00 + 109e: 34 ff + 10a0: 10 00 + 10a2: 00 35 + 10a4: a3 00 00 00 sb zero, 1(zero) + 10a8: 01 64 + 10aa: 04 04 + 10ac: 1c 0b + 10ae: 00 00 + 10b0: 35 9e + 10b2: 00 00 + 10b4: 00 01 + 10b6: 64 04 + 10b8: 04 1c + 10ba: 0b 00 00 35 + 10be: 89 06 + 10c0: 00 00 + 10c2: 01 64 + 10c4: 04 04 + 10c6: 1c 0b + 10c8: 00 00 + 10ca: 35 84 + 10cc: 06 00 + 10ce: 00 01 + 10d0: 64 04 + 10d2: 04 1c + 10d4: 0b 00 00 35 + 10d8: 54 07 + 10da: 00 00 + 10dc: 01 64 + 10de: 04 04 + 10e0: 1c 0b + 10e2: 00 00 + 10e4: 35 4f + 10e6: 07 00 00 01 + 10ea: 64 04 + 10ec: 04 1c + 10ee: 0b 00 00 33 + 10f2: 5f 5f 6d 00 + 10f6: 01 64 + 10f8: 04 04 + 10fa: 1c 0b + 10fc: 00 00 + 10fe: 00 34 + 1100: 1f 11 00 00 + 1104: 35 d6 + 1106: 06 00 + 1108: 00 01 + 110a: 87 04 04 1c + 110e: 0b 00 00 33 + 1112: 5f 5f 61 00 + 1116: 01 87 + 1118: 04 04 + 111a: 1c 0b + 111c: 00 00 + 111e: 00 34 + 1120: 32 11 + 1122: 00 00 + 1124: 33 5f 5f 78 + 1128: 00 01 + 112a: 95 04 + 112c: 05 1c + 112e: 0b 00 00 00 + 1132: 36 33 + 1134: 6d 31 + 1136: 00 01 + 1138: a5 04 + 113a: 0f 1c 0b 00 + 113e: 00 33 + 1140: 6d 30 + 1142: 00 01 + 1144: a5 04 + 1146: 13 1c 0b 00 slli s8, s6, 0 + 114a: 00 34 + 114c: ac 11 + 114e: 00 00 + 1150: 35 a3 + 1152: 00 00 + 1154: 00 01 + 1156: b0 04 + 1158: 08 1c + 115a: 0b 00 00 35 + 115e: 9e 00 + 1160: 00 00 + 1162: 01 b0 + 1164: 04 08 + 1166: 1c 0b + 1168: 00 00 + 116a: 35 89 + 116c: 06 00 + 116e: 00 01 + 1170: b0 04 + 1172: 08 1c + 1174: 0b 00 00 35 + 1178: 84 06 + 117a: 00 00 + 117c: 01 b0 + 117e: 04 08 + 1180: 1c 0b + 1182: 00 00 + 1184: 35 54 + 1186: 07 00 00 01 + 118a: b0 04 + 118c: 08 1c + 118e: 0b 00 00 35 + 1192: 4f 07 00 00 fnmadd.s fa4, ft0, ft0, ft0, rne + 1196: 01 b0 + 1198: 04 08 + 119a: 1c 0b + 119c: 00 00 + 119e: 33 5f 5f 6d + 11a2: 00 01 + 11a4: b0 04 + 11a6: 08 1c + 11a8: 0b 00 00 00 + 11ac: 34 1a + 11ae: 12 00 + 11b0: 00 35 + 11b2: 11 06 + 11b4: 00 00 + 11b6: 01 b1 + 11b8: 04 08 + 11ba: 1c 0b + 11bc: 00 00 + 11be: 35 16 + 11c0: 06 00 + 11c2: 00 01 + 11c4: b1 04 + 11c6: 08 1c + 11c8: 0b 00 00 35 + 11cc: 1b 06 00 00 + 11d0: 01 b1 + 11d2: 04 08 + 11d4: 1c 0b + 11d6: 00 00 + 11d8: 35 20 + 11da: 06 00 + 11dc: 00 01 + 11de: b1 04 + 11e0: 08 1c + 11e2: 0b 00 00 35 + 11e6: 6d 03 + 11e8: 00 00 + 11ea: 01 b1 + 11ec: 04 08 + 11ee: 1c 0b + 11f0: 00 00 + 11f2: 35 31 + 11f4: 04 00 + 11f6: 00 01 + 11f8: b1 04 + 11fa: 08 1c + 11fc: 0b 00 00 35 + 1200: 57 03 00 00 + 1204: 01 b1 + 1206: 04 08 + 1208: 1c 0b + 120a: 00 00 + 120c: 35 2c + 120e: 04 00 + 1210: 00 01 + 1212: b1 04 + 1214: 08 1c + 1216: 0b 00 00 00 + 121a: 34 2d + 121c: 12 00 + 121e: 00 33 + 1220: 5f 5f 78 00 + 1224: 01 b6 + 1226: 04 05 + 1228: 1c 0b + 122a: 00 00 + 122c: 00 36 + 122e: 33 5f 5f 78 + 1232: 00 01 + 1234: be 04 + 1236: 05 1c + 1238: 0b 00 00 00 + 123c: 00 00 + 123e: 0f 04 34 0b + 1242: 00 00 + 1244: 00 9d + 1246: 12 00 + 1248: 00 04 + 124a: 00 cc + 124c: 02 00 + 124e: 00 04 + 1250: 01 ec + 1252: 04 00 + 1254: 00 0c + 1256: 6d 04 + 1258: 00 00 + 125a: d5 01 + 125c: 00 00 + 125e: e0 03 + 1260: 01 80 + 1262: 10 04 + 1264: 00 00 + 1266: 23 09 00 00 sb zero, 18(zero) + 126a: 02 08 + 126c: 07 ca 02 00 + 1270: 00 03 + 1272: 04 05 + 1274: 69 6e + 1276: 74 00 + 1278: 02 04 + 127a: 07 d4 02 00 + 127e: 00 02 + 1280: 08 05 + 1282: f1 03 + 1284: 00 00 + 1286: 02 10 + 1288: 04 c0 + 128a: 00 00 + 128c: 00 02 + 128e: 01 06 + 1290: ad 06 + 1292: 00 00 + 1294: 02 01 + 1296: 08 ab + 1298: 06 00 + 129a: 00 02 + 129c: 02 05 + 129e: 00 00 + 12a0: 00 00 + 12a2: 02 02 + 12a4: 07 ea 02 00 + 12a8: 00 02 + 12aa: 04 05 + 12ac: f6 03 + 12ae: 00 00 + 12b0: 02 04 + 12b2: 07 cf 02 00 + 12b6: 00 04 + 12b8: 4a 03 + 12ba: 00 00 + 12bc: 02 5e + 12be: 01 17 + 12c0: 33 00 00 00 add zero, zero, zero + 12c4: 05 25 + 12c6: 04 00 + 12c8: 00 03 + 12ca: 2e 0e + 12cc: 64 00 + 12ce: 00 00 + 12d0: 05 33 + 12d2: 06 00 + 12d4: 00 03 + 12d6: 74 0e + 12d8: 64 00 + 12da: 00 00 + 12dc: 05 15 + 12de: 07 00 00 03 + 12e2: 93 17 2c 00 slli a5, s8, 2 + 12e6: 00 00 + 12e8: 06 04 + 12ea: 03 a5 03 c5 lw a0, -944(t2) + 12ee: 00 00 + 12f0: 00 07 + 12f2: 31 03 + 12f4: 00 00 + 12f6: 03 a7 0c 72 lw a4, 1824(s9) + 12fa: 00 00 + 12fc: 00 07 + 12fe: 9c 02 + 1300: 00 00 + 1302: 03 a8 13 c5 lw a6, -943(t2) + 1306: 00 00 + 1308: 00 00 + 130a: 08 4f + 130c: 00 00 + 130e: 00 d5 + 1310: 00 00 + 1312: 00 09 + 1314: 33 00 00 00 add zero, zero, zero + 1318: 03 00 0a 08 lb zero, 128(s4) + 131c: 03 a2 09 f9 lw tp, -112(s3) + 1320: 00 00 + 1322: 00 0b + 1324: 9b 03 00 00 + 1328: 03 a4 07 2c lw s0, 704(a5) + 132c: 00 00 + 132e: 00 00 + 1330: 0b 25 06 00 + 1334: 00 03 + 1336: a9 05 + 1338: a3 00 00 00 sb zero, 1(zero) + 133c: 04 00 + 133e: 05 4a + 1340: 04 00 + 1342: 00 03 + 1344: aa 03 + 1346: d5 00 + 1348: 00 00 + 134a: 0c 04 + 134c: 05 be + 134e: 06 00 + 1350: 00 04 + 1352: 16 19 + 1354: 6b 00 00 00 vx_tmc zero + 1358: 05 55 + 135a: 04 00 + 135c: 00 05 + 135e: 0c 0d + 1360: 2c 00 + 1362: 00 00 + 1364: 05 cb + 1366: 04 00 + 1368: 00 04 + 136a: 23 1b 13 01 sh a7, 22(t1) + 136e: 00 00 + 1370: 0d d4 + 1372: 03 00 00 18 lb zero, 384(zero) + 1376: 04 34 + 1378: 08 85 + 137a: 01 00 + 137c: 00 0b + 137e: d5 07 + 1380: 00 00 + 1382: 04 36 + 1384: 13 85 01 00 mv a0, gp + 1388: 00 00 + 138a: 0e 5f + 138c: 6b 00 04 37 vx_tex zero, s0, a6, t1, rne + 1390: 07 2c 00 00 flw fs8, 0(zero) + 1394: 00 04 + 1396: 0b 02 06 00 + 139a: 00 04 + 139c: 37 0b 2c 00 lui s6, 704 + 13a0: 00 00 + 13a2: 08 0b + 13a4: 40 02 + 13a6: 00 00 + 13a8: 04 37 + 13aa: 14 2c + 13ac: 00 00 + 13ae: 00 0c + 13b0: 0b 6b 01 00 + 13b4: 00 04 + 13b6: 37 1b 2c 00 lui s6, 705 + 13ba: 00 00 + 13bc: 10 0e + 13be: 5f 78 00 04 + 13c2: 38 0b + 13c4: 8b 01 00 00 + 13c8: 14 00 + 13ca: 0f 04 2b 01 + 13ce: 00 00 + 13d0: 08 07 + 13d2: 01 00 + 13d4: 00 9b + 13d6: 01 00 + 13d8: 00 09 + 13da: 33 00 00 00 add zero, zero, zero + 13de: 00 00 + 13e0: 0d 7f + 13e2: 02 00 + 13e4: 00 24 + 13e6: 04 3c + 13e8: 08 1e + 13ea: 02 00 + 13ec: 00 0b + 13ee: f8 00 + 13f0: 00 00 + 13f2: 04 3e + 13f4: 09 2c + 13f6: 00 00 + 13f8: 00 00 + 13fa: 0b 73 07 00 + 13fe: 00 04 + 1400: 3f 09 2c 00 + 1404: 00 00 + 1406: 04 0b + 1408: 14 01 + 140a: 00 00 + 140c: 04 40 + 140e: 09 2c + 1410: 00 00 + 1412: 00 08 + 1414: 0b c6 07 00 + 1418: 00 04 + 141a: 41 09 + 141c: 2c 00 + 141e: 00 00 + 1420: 0c 0b + 1422: ff 03 00 00 + 1426: 04 42 + 1428: 09 2c + 142a: 00 00 + 142c: 00 10 + 142e: 0b 91 03 00 + 1432: 00 04 + 1434: 43 09 2c 00 fmadd.s fs2, fs8, ft2, ft0, rne + 1438: 00 00 + 143a: 14 0b + 143c: fe 06 + 143e: 00 00 + 1440: 04 44 + 1442: 09 2c + 1444: 00 00 + 1446: 00 18 + 1448: 0b d4 04 00 + 144c: 00 04 + 144e: 45 09 + 1450: 2c 00 + 1452: 00 00 + 1454: 1c 0b + 1456: 59 07 + 1458: 00 00 + 145a: 04 46 + 145c: 09 2c + 145e: 00 00 + 1460: 00 20 + 1462: 00 10 + 1464: 31 01 + 1466: 00 00 + 1468: 08 01 + 146a: 04 4f + 146c: 08 63 + 146e: 02 00 + 1470: 00 0b + 1472: 33 02 00 00 add tp, zero, zero + 1476: 04 50 + 1478: 0a 63 + 147a: 02 00 + 147c: 00 00 + 147e: 0b a7 04 00 + 1482: 00 04 + 1484: 51 09 + 1486: 63 02 00 00 beqz zero, 4 + 148a: 80 11 + 148c: a2 06 + 148e: 00 00 + 1490: 04 53 + 1492: 0a 07 + 1494: 01 00 + 1496: 00 00 + 1498: 01 11 + 149a: 63 01 00 00 beqz zero, 2 + 149e: 04 56 + 14a0: 0a 07 + 14a2: 01 00 + 14a4: 00 04 + 14a6: 01 00 + 14a8: 08 05 + 14aa: 01 00 + 14ac: 00 73 + 14ae: 02 00 + 14b0: 00 09 + 14b2: 33 00 00 00 add zero, zero, zero + 14b6: 1f 00 10 08 + 14ba: 04 00 + 14bc: 00 90 + 14be: 01 04 + 14c0: 62 08 + 14c2: b6 02 + 14c4: 00 00 + 14c6: 0b d5 07 00 + 14ca: 00 04 + 14cc: 63 12 b6 02 bne a2, a1, 36 + 14d0: 00 00 + 14d2: 00 0b + 14d4: e9 05 + 14d6: 00 00 + 14d8: 04 64 + 14da: 06 2c + 14dc: 00 00 + 14de: 00 04 + 14e0: 0b 3b 02 00 + 14e4: 00 04 + 14e6: 66 09 + 14e8: bc 02 + 14ea: 00 00 + 14ec: 08 0b + 14ee: 31 01 + 14f0: 00 00 + 14f2: 04 67 + 14f4: 1e 1e + 14f6: 02 00 + 14f8: 00 88 + 14fa: 00 0f + 14fc: 04 73 + 14fe: 02 00 + 1500: 00 08 + 1502: cc 02 + 1504: 00 00 + 1506: cc 02 + 1508: 00 00 + 150a: 09 33 + 150c: 00 00 + 150e: 00 1f + 1510: 00 0f + 1512: 04 d2 + 1514: 02 00 + 1516: 00 12 + 1518: 0d bf + 151a: 07 00 00 08 + 151e: 04 7a + 1520: 08 fb + 1522: 02 00 + 1524: 00 0b + 1526: 0e 01 + 1528: 00 00 + 152a: 04 7b + 152c: 11 fb + 152e: 02 00 + 1530: 00 00 + 1532: 0b 1c 00 00 + 1536: 00 04 + 1538: 7c 06 + 153a: 2c 00 + 153c: 00 00 + 153e: 04 00 + 1540: 0f 04 4f 00 + 1544: 00 00 + 1546: 0d c5 + 1548: 05 00 + 154a: 00 68 + 154c: 04 ba + 154e: 08 44 + 1550: 04 00 + 1552: 00 0e + 1554: 5f 70 00 04 + 1558: bb 12 fb 02 + 155c: 00 00 + 155e: 00 0e + 1560: 5f 72 00 04 + 1564: bc 07 + 1566: 2c 00 + 1568: 00 00 + 156a: 04 0e + 156c: 5f 77 00 04 + 1570: bd 07 + 1572: 2c 00 + 1574: 00 00 + 1576: 08 0b + 1578: 5c 01 + 157a: 00 00 + 157c: 04 be + 157e: 09 56 + 1580: 00 00 + 1582: 00 0c + 1584: 0b ab 02 00 + 1588: 00 04 + 158a: bf 09 56 00 + 158e: 00 00 + 1590: 0e 0e + 1592: 5f 62 66 00 + 1596: 04 c0 + 1598: 11 d3 + 159a: 02 00 + 159c: 00 10 + 159e: 0b a8 00 00 + 15a2: 00 04 + 15a4: c1 07 + 15a6: 2c 00 + 15a8: 00 00 + 15aa: 18 0b + 15ac: 3f 01 00 00 + 15b0: 04 c8 + 15b2: 0a 05 + 15b4: 01 00 + 15b6: 00 1c + 15b8: 0b 67 04 00 + 15bc: 00 04 + 15be: ca 1d + 15c0: c8 05 + 15c2: 00 00 + 15c4: 20 0b + 15c6: 8a 03 + 15c8: 00 00 + 15ca: 04 cc + 15cc: 1d f7 + 15ce: 05 00 + 15d0: 00 24 + 15d2: 0b 2d 06 00 + 15d6: 00 04 + 15d8: cf 0d 1b 06 + 15dc: 00 00 + 15de: 28 0b + 15e0: 01 01 + 15e2: 00 00 + 15e4: 04 d0 + 15e6: 09 35 + 15e8: 06 00 + 15ea: 00 2c + 15ec: 0e 5f + 15ee: 75 62 + 15f0: 00 04 + 15f2: d3 11 d3 02 + 15f6: 00 00 + 15f8: 30 0e + 15fa: 5f 75 70 00 + 15fe: 04 d4 + 1600: 12 fb + 1602: 02 00 + 1604: 00 38 + 1606: 0e 5f + 1608: 75 72 + 160a: 00 04 + 160c: d5 07 + 160e: 2c 00 + 1610: 00 00 + 1612: 3c 0b + 1614: 08 01 + 1616: 00 00 + 1618: 04 d8 + 161a: 11 3b + 161c: 06 00 + 161e: 00 40 + 1620: 0b 41 07 00 + 1624: 00 04 + 1626: d9 11 + 1628: 4b 06 00 00 fnmsub.s fa2, ft0, ft0, ft0, rne + 162c: 43 0e 5f 6c + 1630: 62 00 + 1632: 04 dc + 1634: 11 d3 + 1636: 02 00 + 1638: 00 44 + 163a: 0b 44 06 00 + 163e: 00 04 + 1640: df 07 2c 00 + 1644: 00 00 + 1646: 4c 0b + 1648: cc 03 + 164a: 00 00 + 164c: 04 e0 + 164e: 0a 7f + 1650: 00 00 + 1652: 00 50 + 1654: 0b 5b 00 00 + 1658: 00 04 + 165a: e3 12 62 04 bne tp, t1, 2116 + 165e: 00 00 + 1660: 54 0b + 1662: 51 03 + 1664: 00 00 + 1666: 04 e7 + 1668: 0c 1f + 166a: 01 00 + 166c: 00 58 + 166e: 0b 93 02 00 + 1672: 00 04 + 1674: e9 0e + 1676: f9 00 + 1678: 00 00 + 167a: 5c 0b + 167c: de 04 + 167e: 00 00 + 1680: 04 ea + 1682: 09 2c + 1684: 00 00 + 1686: 00 64 + 1688: 00 13 + 168a: 97 00 00 00 auipc ra, 0 + 168e: 62 04 + 1690: 00 00 + 1692: 14 62 + 1694: 04 00 + 1696: 00 14 + 1698: 05 01 + 169a: 00 00 + 169c: 14 b6 + 169e: 05 00 + 16a0: 00 14 + 16a2: 2c 00 + 16a4: 00 00 + 16a6: 00 0f + 16a8: 04 6d + 16aa: 04 00 + 16ac: 00 15 + 16ae: 62 04 + 16b0: 00 00 + 16b2: 16 0a + 16b4: 06 00 + 16b6: 00 28 + 16b8: 04 04 + 16ba: 65 02 + 16bc: 08 b6 + 16be: 05 00 + 16c0: 00 17 + 16c2: c4 04 + 16c4: 00 00 + 16c6: 04 67 + 16c8: 02 07 + 16ca: 2c 00 + 16cc: 00 00 + 16ce: 00 17 + 16d0: 0e 07 + 16d2: 00 00 + 16d4: 04 6c + 16d6: 02 0b + 16d8: a7 06 00 00 + 16dc: 04 17 + 16de: f6 06 + 16e0: 00 00 + 16e2: 04 6c + 16e4: 02 14 + 16e6: a7 06 00 00 + 16ea: 08 17 + 16ec: 46 02 + 16ee: 00 00 + 16f0: 04 6c + 16f2: 02 1e + 16f4: a7 06 00 00 + 16f8: 0c 17 + 16fa: e4 05 + 16fc: 00 00 + 16fe: 04 6e + 1700: 02 08 + 1702: 2c 00 + 1704: 00 00 + 1706: 10 17 + 1708: 2a 00 + 170a: 00 00 + 170c: 04 6f + 170e: 02 08 + 1710: a7 08 00 00 + 1714: 14 17 + 1716: 66 02 + 1718: 00 00 + 171a: 04 72 + 171c: 02 07 + 171e: 2c 00 + 1720: 00 00 + 1722: 30 17 + 1724: af 07 00 00 + 1728: 04 73 + 172a: 02 16 + 172c: bc 08 + 172e: 00 00 + 1730: 34 17 + 1732: 1a 04 + 1734: 00 00 + 1736: 04 75 + 1738: 02 07 + 173a: 2c 00 + 173c: 00 00 + 173e: 38 17 + 1740: f8 05 + 1742: 00 00 + 1744: 04 77 + 1746: 02 0a + 1748: cd 08 + 174a: 00 00 + 174c: 3c 17 + 174e: 29 03 + 1750: 00 00 + 1752: 04 7a + 1754: 02 13 + 1756: 85 01 + 1758: 00 00 + 175a: 40 17 + 175c: 77 01 00 00 + 1760: 04 7b + 1762: 02 07 + 1764: 2c 00 + 1766: 00 00 + 1768: 44 17 + 176a: aa 07 + 176c: 00 00 + 176e: 04 7c + 1770: 02 13 + 1772: 85 01 + 1774: 00 00 + 1776: 48 17 + 1778: 36 04 + 177a: 00 00 + 177c: 04 7d + 177e: 02 14 + 1780: d3 08 00 00 fadd.s fa7, ft0, ft0, rne + 1784: 4c 17 + 1786: a3 02 00 00 sb zero, 5(zero) + 178a: 04 80 + 178c: 02 07 + 178e: 2c 00 + 1790: 00 00 + 1792: 50 17 + 1794: ae 01 + 1796: 00 00 + 1798: 04 81 + 179a: 02 09 + 179c: b6 05 + 179e: 00 00 + 17a0: 54 17 + 17a2: bd 04 + 17a4: 00 00 + 17a6: 04 a4 + 17a8: 02 07 + 17aa: 82 08 + 17ac: 00 00 + 17ae: 58 18 + 17b0: 08 04 + 17b2: 00 00 + 17b4: 04 a8 + 17b6: 02 13 + 17b8: b6 02 + 17ba: 00 00 + 17bc: 48 01 + 17be: 18 07 + 17c0: 03 00 00 04 lb zero, 64(zero) + 17c4: a9 02 + 17c6: 12 73 + 17c8: 02 00 + 17ca: 00 4c + 17cc: 01 18 + 17ce: 28 07 + 17d0: 00 00 + 17d2: 04 ad + 17d4: 02 0c + 17d6: e4 08 + 17d8: 00 00 + 17da: dc 02 + 17dc: 18 47 + 17de: 01 00 + 17e0: 00 04 + 17e2: b2 02 + 17e4: 10 68 + 17e6: 06 00 + 17e8: 00 e0 + 17ea: 02 18 + 17ec: 2c 01 + 17ee: 00 00 + 17f0: 04 b4 + 17f2: 02 0a + 17f4: f0 08 + 17f6: 00 00 + 17f8: ec 02 + 17fa: 00 0f + 17fc: 04 bc + 17fe: 05 00 + 1800: 00 02 + 1802: 01 08 + 1804: b4 06 + 1806: 00 00 + 1808: 15 bc + 180a: 05 00 + 180c: 00 0f + 180e: 04 44 + 1810: 04 00 + 1812: 00 13 + 1814: 97 00 00 00 auipc ra, 0 + 1818: ec 05 + 181a: 00 00 + 181c: 14 62 + 181e: 04 00 + 1820: 00 14 + 1822: 05 01 + 1824: 00 00 + 1826: 14 ec + 1828: 05 00 + 182a: 00 14 + 182c: 2c 00 + 182e: 00 00 + 1830: 00 0f + 1832: 04 c3 + 1834: 05 00 + 1836: 00 15 + 1838: ec 05 + 183a: 00 00 + 183c: 0f 04 ce 05 + 1840: 00 00 + 1842: 13 8b 00 00 mv s6, ra + 1846: 00 1b + 1848: 06 00 + 184a: 00 14 + 184c: 62 04 + 184e: 00 00 + 1850: 14 05 + 1852: 01 00 + 1854: 00 14 + 1856: 8b 00 00 00 + 185a: 14 2c + 185c: 00 00 + 185e: 00 00 + 1860: 0f 04 fd 05 + 1864: 00 00 + 1866: 13 2c 00 00 slti s8, zero, 0 + 186a: 00 35 + 186c: 06 00 + 186e: 00 14 + 1870: 62 04 + 1872: 00 00 + 1874: 14 05 + 1876: 01 00 + 1878: 00 00 + 187a: 0f 04 21 06 + 187e: 00 00 + 1880: 08 4f + 1882: 00 00 + 1884: 00 4b + 1886: 06 00 + 1888: 00 09 + 188a: 33 00 00 00 add zero, zero, zero + 188e: 02 00 + 1890: 08 4f + 1892: 00 00 + 1894: 00 5b + 1896: 06 00 + 1898: 00 09 + 189a: 33 00 00 00 add zero, zero, zero + 189e: 00 00 + 18a0: 04 70 + 18a2: 01 00 + 18a4: 00 04 + 18a6: 24 01 + 18a8: 1a 01 + 18aa: 03 00 00 19 lb zero, 400(zero) + 18ae: 08 07 + 18b0: 00 00 + 18b2: 0c 04 + 18b4: 28 01 + 18b6: 08 a1 + 18b8: 06 00 + 18ba: 00 17 + 18bc: d5 07 + 18be: 00 00 + 18c0: 04 2a + 18c2: 01 11 + 18c4: a1 06 + 18c6: 00 00 + 18c8: 00 17 + 18ca: c3 02 00 00 fmadd.s ft5, ft0, ft0, ft0, rne + 18ce: 04 2b + 18d0: 01 07 + 18d2: 2c 00 + 18d4: 00 00 + 18d6: 04 17 + 18d8: e6 04 + 18da: 00 00 + 18dc: 04 2c + 18de: 01 0b + 18e0: a7 06 00 00 + 18e4: 08 00 + 18e6: 0f 04 68 06 + 18ea: 00 00 + 18ec: 0f 04 5b 06 + 18f0: 00 00 + 18f2: 19 22 + 18f4: 00 00 + 18f6: 00 0e + 18f8: 04 44 + 18fa: 01 08 + 18fc: e6 06 + 18fe: 00 00 + 1900: 17 72 06 00 auipc tp, 103 + 1904: 00 04 + 1906: 45 01 + 1908: 12 e6 + 190a: 06 00 + 190c: 00 00 + 190e: 17 67 03 00 auipc a4, 54 + 1912: 00 04 + 1914: 46 01 + 1916: 12 e6 + 1918: 06 00 + 191a: 00 06 + 191c: 17 b9 06 00 auipc s2, 107 + 1920: 00 04 + 1922: 47 01 12 5d + 1926: 00 00 + 1928: 00 0c + 192a: 00 08 + 192c: 5d 00 + 192e: 00 00 + 1930: f6 06 + 1932: 00 00 + 1934: 09 33 + 1936: 00 00 + 1938: 00 02 + 193a: 00 1a + 193c: d0 04 + 193e: 85 02 + 1940: 07 0b 08 00 + 1944: 00 17 + 1946: a3 03 00 00 sb zero, 7(zero) + 194a: 04 87 + 194c: 02 18 + 194e: 33 00 00 00 add zero, zero, zero + 1952: 00 17 + 1954: 8e 06 + 1956: 00 00 + 1958: 04 88 + 195a: 02 12 + 195c: b6 05 + 195e: 00 00 + 1960: 04 17 + 1962: 1c 03 + 1964: 00 00 + 1966: 04 89 + 1968: 02 10 + 196a: 0b 08 00 00 + 196e: 08 17 + 1970: 64 07 + 1972: 00 00 + 1974: 04 8a + 1976: 02 17 + 1978: 9b 01 00 00 + 197c: 24 17 + 197e: 4e 02 + 1980: 00 00 + 1982: 04 8b + 1984: 02 0f + 1986: 2c 00 + 1988: 00 00 + 198a: 48 17 + 198c: d0 07 + 198e: 00 00 + 1990: 04 8c + 1992: 02 2c + 1994: 25 00 + 1996: 00 00 + 1998: 50 17 + 199a: 7c 07 + 199c: 00 00 + 199e: 04 8d + 19a0: 02 1a + 19a2: ad 06 + 19a4: 00 00 + 19a6: 58 17 + 19a8: d7 05 00 00 + 19ac: 04 8e + 19ae: 02 16 + 19b0: f9 00 + 19b2: 00 00 + 19b4: 68 17 + 19b6: 9c 07 + 19b8: 00 00 + 19ba: 04 8f + 19bc: 02 16 + 19be: f9 00 + 19c0: 00 00 + 19c2: 70 17 + 19c4: 1e 01 + 19c6: 00 00 + 19c8: 04 90 + 19ca: 02 16 + 19cc: f9 00 + 19ce: 00 00 + 19d0: 78 17 + 19d2: 1e 07 + 19d4: 00 00 + 19d6: 04 91 + 19d8: 02 10 + 19da: 1b 08 00 00 + 19de: 80 17 + 19e0: 10 03 + 19e2: 00 00 + 19e4: 04 92 + 19e6: 02 10 + 19e8: 2b 08 00 00 + 19ec: 88 17 + 19ee: 4e 00 + 19f0: 00 00 + 19f2: 04 93 + 19f4: 02 0f + 19f6: 2c 00 + 19f8: 00 00 + 19fa: a0 17 + 19fc: c7 01 00 00 fmsub.s ft3, ft0, ft0, ft0, rne + 1a00: 04 94 + 1a02: 02 16 + 1a04: f9 00 + 1a06: 00 00 + 1a08: a4 17 + 1a0a: e1 00 + 1a0c: 00 00 + 1a0e: 04 95 + 1a10: 02 16 + 1a12: f9 00 + 1a14: 00 00 + 1a16: ac 17 + 1a18: b6 01 + 1a1a: 00 00 + 1a1c: 04 96 + 1a1e: 02 16 + 1a20: f9 00 + 1a22: 00 00 + 1a24: b4 17 + 1a26: 61 00 + 1a28: 00 00 + 1a2a: 04 97 + 1a2c: 02 16 + 1a2e: f9 00 + 1a30: 00 00 + 1a32: bc 17 + 1a34: 8d 00 + 1a36: 00 00 + 1a38: 04 98 + 1a3a: 02 16 + 1a3c: f9 00 + 1a3e: 00 00 + 1a40: c4 17 + 1a42: c2 04 + 1a44: 00 00 + 1a46: 04 99 + 1a48: 02 08 + 1a4a: 2c 00 + 1a4c: 00 00 + 1a4e: cc 00 + 1a50: 08 bc + 1a52: 05 00 + 1a54: 00 1b + 1a56: 08 00 + 1a58: 00 09 + 1a5a: 33 00 00 00 add zero, zero, zero + 1a5e: 19 00 + 1a60: 08 bc + 1a62: 05 00 + 1a64: 00 2b + 1a66: 08 00 + 1a68: 00 09 + 1a6a: 33 00 00 00 add zero, zero, zero + 1a6e: 07 00 08 bc + 1a72: 05 00 + 1a74: 00 3b + 1a76: 08 00 + 1a78: 00 09 + 1a7a: 33 00 00 00 add zero, zero, zero + 1a7e: 17 00 1a f0 auipc zero, 983456 + 1a82: 04 9e + 1a84: 02 07 + 1a86: 62 08 + 1a88: 00 00 + 1a8a: 17 dc 03 00 auipc s8, 61 + 1a8e: 00 04 + 1a90: a1 02 + 1a92: 1b 62 08 00 + 1a96: 00 00 + 1a98: 17 5d 02 00 auipc s10, 37 + 1a9c: 00 04 + 1a9e: a2 02 + 1aa0: 18 72 + 1aa2: 08 00 + 1aa4: 00 78 + 1aa6: 00 08 + 1aa8: fb 02 00 00 + 1aac: 72 08 + 1aae: 00 00 + 1ab0: 09 33 + 1ab2: 00 00 + 1ab4: 00 1d + 1ab6: 00 08 + 1ab8: 33 00 00 00 add zero, zero, zero + 1abc: 82 08 + 1abe: 00 00 + 1ac0: 09 33 + 1ac2: 00 00 + 1ac4: 00 1d + 1ac6: 00 1b + 1ac8: f0 04 + 1aca: 83 02 03 a7 lb t0, -1424(t1) + 1ace: 08 00 + 1ad0: 00 1c + 1ad2: 0a 06 + 1ad4: 00 00 + 1ad6: 04 9a + 1ad8: 02 0b + 1ada: f6 06 + 1adc: 00 00 + 1ade: 1c 47 + 1ae0: 07 00 00 04 + 1ae4: a3 02 0b 3b sb a6, 933(s6) + 1ae8: 08 00 + 1aea: 00 00 + 1aec: 08 bc + 1aee: 05 00 + 1af0: 00 b7 + 1af2: 08 00 + 1af4: 00 09 + 1af6: 33 00 00 00 add zero, zero, zero + 1afa: 18 00 + 1afc: 1d d6 + 1afe: 00 00 + 1b00: 00 0f + 1b02: 04 b7 + 1b04: 08 00 + 1b06: 00 1e + 1b08: cd 08 + 1b0a: 00 00 + 1b0c: 14 62 + 1b0e: 04 00 + 1b10: 00 00 + 1b12: 0f 04 c2 08 + 1b16: 00 00 + 1b18: 0f 04 85 01 + 1b1c: 00 00 + 1b1e: 1e e4 + 1b20: 08 00 + 1b22: 00 14 + 1b24: 2c 00 + 1b26: 00 00 + 1b28: 00 0f + 1b2a: 04 ea + 1b2c: 08 00 + 1b2e: 00 0f + 1b30: 04 d9 + 1b32: 08 00 + 1b34: 00 08 + 1b36: 5b 06 00 00 + 1b3a: 00 09 + 1b3c: 00 00 + 1b3e: 09 33 + 1b40: 00 00 + 1b42: 00 02 + 1b44: 00 1f + 1b46: e2 06 + 1b48: 00 00 + 1b4a: 04 33 + 1b4c: 03 17 62 04 lh a4, 70(tp) + 1b50: 00 00 + 1b52: 1f db 06 00 + 1b56: 00 04 + 1b58: 34 03 + 1b5a: 1d 68 + 1b5c: 04 00 + 1b5e: 00 08 + 1b60: f2 05 + 1b62: 00 00 + 1b64: 25 09 + 1b66: 00 00 + 1b68: 20 00 + 1b6a: 15 1a + 1b6c: 09 00 + 1b6e: 00 21 + 1b70: a1 01 + 1b72: 00 00 + 1b74: 06 14 + 1b76: 24 25 + 1b78: 09 00 + 1b7a: 00 21 + 1b7c: cd 05 + 1b7e: 00 00 + 1b80: 06 15 + 1b82: 15 2c + 1b84: 00 00 + 1b86: 00 0f + 1b88: 04 48 + 1b8a: 09 00 + 1b8c: 00 13 + 1b8e: 2c 00 + 1b90: 00 00 + 1b92: 5c 09 + 1b94: 00 00 + 1b96: 14 5c + 1b98: 09 00 + 1b9a: 00 14 + 1b9c: 5c 09 + 1b9e: 00 00 + 1ba0: 00 0f + 1ba2: 04 62 + 1ba4: 09 00 + 1ba6: 00 22 + 1ba8: 21 10 + 1baa: 04 00 + 1bac: 00 07 + 1bae: 67 0e b6 05 jalr t3, 91(a2) + 1bb2: 00 00 + 1bb4: 21 42 + 1bb6: 03 00 00 08 lb zero, 128(zero) + 1bba: 10 0f + 1bbc: 7b 09 00 00 + 1bc0: 0f 04 b6 05 + 1bc4: 00 00 + 1bc6: 21 13 + 1bc8: 04 00 + 1bca: 00 08 + 1bcc: fc 0e + 1bce: b6 05 + 1bd0: 00 00 + 1bd2: 21 b1 + 1bd4: 00 00 + 1bd6: 00 08 + 1bd8: fd 0c + 1bda: 2c 00 + 1bdc: 00 00 + 1bde: 21 78 + 1be0: 06 00 + 1be2: 00 08 + 1be4: fd 14 + 1be6: 2c 00 + 1be8: 00 00 + 1bea: 21 8b + 1bec: 07 00 00 08 + 1bf0: fd 1c + 1bf2: 2c 00 + 1bf4: 00 00 + 1bf6: 21 81 + 1bf8: 03 00 00 08 lb zero, 128(zero) + 1bfc: ff 0c 2c 00 + 1c00: 00 00 + 1c02: 21 40 + 1c04: 04 00 + 1c06: 00 09 + 1c08: 9a 16 + 1c0a: 64 00 + 1c0c: 00 00 + 1c0e: 21 35 + 1c10: 00 00 + 1c12: 00 09 + 1c14: 9b 15 2c 00 + 1c18: 00 00 + 1c1a: 08 b6 + 1c1c: 05 00 + 1c1e: 00 e5 + 1c20: 09 00 + 1c22: 00 09 + 1c24: 33 00 00 00 add zero, zero, zero + 1c28: 01 00 + 1c2a: 21 f0 + 1c2c: 00 00 + 1c2e: 00 09 + 1c30: 9e 17 + 1c32: d5 09 + 1c34: 00 00 + 1c36: 05 b1 + 1c38: 02 00 + 1c3a: 00 0a + 1c3c: 2a 16 + 1c3e: 33 00 00 00 add zero, zero, zero + 1c42: 05 bb + 1c44: 05 00 + 1c46: 00 0a + 1c48: 2f 15 09 0a + 1c4c: 00 00 + 1c4e: 0f 04 0f 0a + 1c52: 00 00 + 1c54: 13 f1 09 00 andi sp, s3, 0 + 1c58: 00 1e + 1c5a: 0a 00 + 1c5c: 00 14 + 1c5e: 5c 09 + 1c60: 00 00 + 1c62: 00 05 + 1c64: db 07 00 00 + 1c68: 0a 36 + 1c6a: 0f 42 09 00 + 1c6e: 00 21 + 1c70: 0a 00 + 1c72: 00 00 + 1c74: 0a bb + 1c76: 12 fd + 1c78: 09 00 + 1c7a: 00 21 + 1c7c: c6 06 + 1c7e: 00 00 + 1c80: 0a be + 1c82: 10 1e + 1c84: 0a 00 + 1c86: 00 23 + 1c88: 84 02 + 1c8a: 00 00 + 1c8c: 07 04 33 00 + 1c90: 00 00 + 1c92: 0b 18 06 7f + 1c96: 0a 00 + 1c98: 00 24 + 1c9a: 9d 04 + 1c9c: 00 00 + 1c9e: 00 24 + 1ca0: 5c 03 + 1ca2: 00 00 + 1ca4: 01 24 + 1ca6: 37 03 00 00 lui t1, 0 + 1caa: 02 24 + 1cac: b0 03 + 1cae: 00 00 + 1cb0: 03 24 94 04 lw s0, 73(s0) + 1cb4: 00 00 + 1cb6: 04 24 + 1cb8: 92 07 + 1cba: 00 00 + 1cbc: 05 24 + 1cbe: 81 07 + 1cc0: 00 00 + 1cc2: 06 00 + 1cc4: 21 cc + 1cc6: 00 00 + 1cc8: 00 0b + 1cca: 21 1c + 1ccc: 42 0a + 1cce: 00 00 + 1cd0: 23 bb 03 00 + 1cd4: 00 07 + 1cd6: 04 33 + 1cd8: 00 00 + 1cda: 00 0b + 1cdc: 23 06 b0 0a sb a1, 172(zero) + 1ce0: 00 00 + 1ce2: 24 b1 + 1ce4: 05 00 + 1ce6: 00 00 + 1ce8: 24 b3 + 1cea: 04 00 + 1cec: 00 01 + 1cee: 24 9b + 1cf0: 06 00 + 1cf2: 00 02 + 1cf4: 00 21 + 1cf6: 4f 01 00 00 fnmadd.s ft2, ft0, ft0, ft0, rne + 1cfa: 0b 28 1e 8b + 1cfe: 0a 00 + 1d00: 00 23 + 1d02: 70 00 + 1d04: 00 00 + 1d06: 07 04 33 00 + 1d0a: 00 00 + 1d0c: 0b 2b 06 db + 1d10: 0a 00 + 1d12: 00 24 + 1d14: 4d 06 + 1d16: 00 00 + 1d18: 00 24 + 1d1a: 3b 06 00 00 + 1d1e: 01 00 + 1d20: 21 89 + 1d22: 01 00 + 1d24: 00 0b + 1d26: 2f 2a bc 0a + 1d2a: 00 00 + 1d2c: 21 72 + 1d2e: 03 00 00 0c lb zero, 192(zero) + 1d32: 29 1a + 1d34: 25 09 + 1d36: 00 00 + 1d38: 21 62 + 1d3a: 06 00 + 1d3c: 00 0c + 1d3e: 38 1a + 1d40: 25 09 + 1d42: 00 00 + 1d44: 05 b7 + 1d46: 07 00 00 0d + 1d4a: 7b 16 4f 00 + 1d4e: 00 00 + 1d50: 15 ff + 1d52: 0a 00 + 1d54: 00 05 + 1d56: 82 01 + 1d58: 00 00 + 1d5a: 0d 80 + 1d5c: 0f 2c 00 00 + 1d60: 00 05 + 1d62: 81 01 + 1d64: 00 00 + 1d66: 0d 81 + 1d68: 16 33 + 1d6a: 00 00 + 1d6c: 00 05 + 1d6e: ef 06 00 00 jal a3, 0 + 1d72: 0d 84 + 1d74: 0f 3a 00 00 + 1d78: 00 05 + 1d7a: ee 06 + 1d7c: 00 00 + 1d7e: 0d 85 + 1d80: 16 25 + 1d82: 00 00 + 1d84: 00 02 + 1d86: 04 04 + 1d88: eb 03 00 00 vx_tex t2, zero, zero, zero, rne + 1d8c: 02 08 + 1d8e: 03 e3 03 00 + 1d92: 00 02 + 1d94: 08 04 + 1d96: c5 00 + 1d98: 00 00 + 1d9a: 02 10 + 1d9c: 03 3f 00 00 + 1da0: 00 02 + 1da2: 20 03 + 1da4: b8 00 + 1da6: 00 00 + 1da8: 19 e1 + 1daa: 02 00 + 1dac: 00 08 + 1dae: 0d ed + 1db0: 01 0a + 1db2: 8e 0b + 1db4: 00 00 + 1db6: 25 6c + 1db8: 6f 77 00 0d jal a4, 28880 + 1dbc: ed 01 + 1dbe: 1a 10 + 1dc0: 0b 00 00 00 + 1dc4: 17 7f 06 00 auipc t5, 103 + 1dc8: 00 0d + 1dca: ed 01 + 1dcc: 1f 10 0b 00 + 1dd0: 00 04 + 1dd2: 00 1b + 1dd4: 08 0d + 1dd6: f4 01 + 1dd8: 09 b0 + 1dda: 0b 00 00 26 + 1dde: 73 00 0d f6 + 1de2: 01 13 + 1de4: 63 0b 00 00 beqz zero, 22 + 1de8: 26 6c + 1dea: 6c 00 + 1dec: 0d f7 + 1dee: 01 0a + 1df0: 28 0b + 1df2: 00 00 + 1df4: 00 04 + 1df6: bb 02 00 00 + 1dfa: 0d f8 + 1dfc: 01 03 + 1dfe: 8e 0b + 1e00: 00 00 + 1e02: 15 b0 + 1e04: 0b 00 00 08 + 1e08: 0b 0b 00 00 + 1e0c: d2 0b + 1e0e: 00 00 + 1e10: 09 33 + 1e12: 00 00 + 1e14: 00 ff + 1e16: 00 15 + 1e18: c2 0b + 1e1a: 00 00 + 1e1c: 1f 32 07 00 + 1e20: 00 0d + 1e22: fc 01 + 1e24: 16 d2 + 1e26: 0b 00 00 1f + 1e2a: fd 02 + 1e2c: 00 00 + 1e2e: 0d 02 + 1e30: 02 16 + 1e32: d2 0b + 1e34: 00 00 + 1e36: 27 e3 07 00 + 1e3a: 00 01 + 1e3c: 1a 05 + 1e3e: 01 34 + 1e40: 0b 00 00 e0 + 1e44: 03 01 80 10 lb sp, 264(zero) + 1e48: 04 00 + 1e4a: 00 01 + 1e4c: 9c 29 + 1e4e: 0f 00 00 28 + 1e52: 75 00 + 1e54: 01 1a + 1e56: 05 14 + 1e58: 34 0b + 1e5a: 00 00 + 1e5c: f5 0b + 1e5e: 00 00 + 1e60: 28 76 + 1e62: 00 01 + 1e64: 1a 05 + 1e66: 1f 34 0b 00 + 1e6a: 00 9d + 1e6c: 0c 00 + 1e6e: 00 29 + 1e70: 77 00 01 1c + 1e74: 05 0b + 1e76: 34 0b + 1e78: 00 00 + 1e7a: 05 0d + 1e7c: 00 00 + 1e7e: 2a 29 + 1e80: 0f 00 00 e0 + 1e84: 03 01 80 00 lb sp, 8(zero) + 1e88: 01 00 + 1e8a: 00 01 + 1e8c: 1e 05 + 1e8e: 0a 2b + 1e90: 51 0f + 1e92: 00 00 + 1e94: 2d 0d + 1e96: 00 00 + 1e98: 2b 46 0f 00 + 1e9c: 00 55 + 1e9e: 0d 00 + 1ea0: 00 2b + 1ea2: 3b 0f 00 00 + 1ea6: bd 0d + 1ea8: 00 00 + 1eaa: 2c 00 + 1eac: 01 00 + 1eae: 00 2d + 1eb0: 5d 0f + 1eb2: 00 00 + 1eb4: 2d 69 + 1eb6: 0f 00 00 2d + 1eba: 75 0f + 1ebc: 00 00 + 1ebe: 2e 81 + 1ec0: 0f 00 00 45 + 1ec4: 0e 00 + 1ec6: 00 2e + 1ec8: 8d 0f + 1eca: 00 00 + 1ecc: 84 0e + 1ece: 00 00 + 1ed0: 2e 99 + 1ed2: 0f 00 00 d9 + 1ed6: 0e 00 + 1ed8: 00 2e + 1eda: a5 0f + 1edc: 00 00 + 1ede: 4f 0f 00 00 fnmadd.s ft10, ft0, ft0, ft0, rne + 1ee2: 2e b1 + 1ee4: 0f 00 00 e6 + 1ee8: 0f 00 00 2e + 1eec: bd 0f + 1eee: 00 00 + 1ef0: 04 10 + 1ef2: 00 00 + 1ef4: 2e c9 + 1ef6: 0f 00 00 23 + 1efa: 10 00 + 1efc: 00 2e + 1efe: d5 0f + 1f00: 00 00 + 1f02: 43 10 00 00 fmadd.s ft0, ft0, ft0, ft0, rtz + 1f06: 2e e0 + 1f08: 0f 00 00 61 + 1f0c: 10 00 + 1f0e: 00 2d + 1f10: ec 0f + 1f12: 00 00 + 1f14: 2f f8 0f 00 + 1f18: 00 18 + 1f1a: 01 00 + 1f1c: 00 ef + 1f1e: 0c 00 + 1f20: 00 2e + 1f22: fd 0f + 1f24: 00 00 + 1f26: a0 10 + 1f28: 00 00 + 1f2a: 2e 0a + 1f2c: 10 00 + 1f2e: 00 be + 1f30: 10 00 + 1f32: 00 00 + 1f34: 30 18 + 1f36: 10 00 + 1f38: 00 44 + 1f3a: 04 01 + 1f3c: 80 70 + 1f3e: 00 00 + 1f40: 00 3c + 1f42: 0d 00 + 1f44: 00 2e + 1f46: 1d 10 + 1f48: 00 00 + 1f4a: d1 10 + 1f4c: 00 00 + 1f4e: 2e 2a + 1f50: 10 00 + 1f52: 00 e4 + 1f54: 10 00 + 1f56: 00 2d + 1f58: 37 10 00 00 lui zero, 1 + 1f5c: 2e 44 + 1f5e: 10 00 + 1f60: 00 08 + 1f62: 11 00 + 1f64: 00 2e + 1f66: 51 10 + 1f68: 00 00 + 1f6a: 1b 11 00 00 + 1f6e: 2e 5e + 1f70: 10 00 + 1f72: 00 39 + 1f74: 11 00 + 1f76: 00 2e + 1f78: 6b 10 00 00 vx_wspawn zero, zero + 1f7c: 57 11 00 00 + 1f80: 00 2f + 1f82: 79 10 + 1f84: 00 00 + 1f86: 30 01 + 1f88: 00 00 + 1f8a: 5c 0d + 1f8c: 00 00 + 1f8e: 2e 7e + 1f90: 10 00 + 1f92: 00 75 + 1f94: 11 00 + 1f96: 00 2e + 1f98: 8b 10 00 00 + 1f9c: 93 11 00 00 slli gp, zero, 0 + 1fa0: 00 30 + 1fa2: fa 10 + 1fa4: 00 00 + 1fa6: 14 05 + 1fa8: 01 80 + 1faa: 74 00 + 1fac: 00 00 + 1fae: ad 0d + 1fb0: 00 00 + 1fb2: 2e ff + 1fb4: 10 00 + 1fb6: 00 a6 + 1fb8: 11 00 + 1fba: 00 2e + 1fbc: 0c 11 + 1fbe: 00 00 + 1fc0: b9 11 + 1fc2: 00 00 + 1fc4: 2e 19 + 1fc6: 11 00 + 1fc8: 00 dd + 1fca: 11 00 + 1fcc: 00 2e + 1fce: 26 11 + 1fd0: 00 00 + 1fd2: f0 11 + 1fd4: 00 00 + 1fd6: 2e 33 + 1fd8: 11 00 + 1fda: 00 03 + 1fdc: 12 00 + 1fde: 00 2e + 1fe0: 40 11 + 1fe2: 00 00 + 1fe4: 2c 12 + 1fe6: 00 00 + 1fe8: 2e 4d + 1fea: 11 00 + 1fec: 00 4a + 1fee: 12 00 + 1ff0: 00 00 + 1ff2: 2f 99 10 00 + 1ff6: 00 48 + 1ff8: 01 00 + 1ffa: 00 fa + 1ffc: 0d 00 + 1ffe: 00 2e + 2000: 9e 10 + 2002: 00 00 + 2004: 68 12 + 2006: 00 00 + 2008: 2e ab + 200a: 10 00 + 200c: 00 7b + 200e: 12 00 + 2010: 00 2e + 2012: b8 10 + 2014: 00 00 + 2016: 9f 12 00 00 + 201a: 2e c5 + 201c: 10 00 + 201e: 00 b2 + 2020: 12 00 + 2022: 00 2e + 2024: d2 10 + 2026: 00 00 + 2028: c5 12 + 202a: 00 00 + 202c: 2e df + 202e: 10 00 + 2030: 00 ee + 2032: 12 00 + 2034: 00 2e + 2036: ec 10 + 2038: 00 00 + 203a: 0c 13 + 203c: 00 00 + 203e: 00 2f + 2040: 5b 11 00 00 + 2044: 60 01 + 2046: 00 00 + 2048: 1a 0e + 204a: 00 00 + 204c: 2e 60 + 204e: 11 00 + 2050: 00 2a + 2052: 13 00 00 2e addi zero, zero, 736 + 2056: 6d 11 + 2058: 00 00 + 205a: 3d 13 + 205c: 00 00 + 205e: 00 30 + 2060: 7b 11 00 00 + 2064: 6c 06 + 2066: 01 80 + 2068: 10 00 + 206a: 00 00 + 206c: 35 0e + 206e: 00 00 + 2070: 2e 80 + 2072: 11 00 + 2074: 00 50 + 2076: 13 00 00 00 nop + 207a: 31 8e + 207c: 11 00 + 207e: 00 9c + 2080: 06 01 + 2082: 80 54 + 2084: 01 00 + 2086: 00 32 + 2088: 8f 11 00 00 + 208c: 01 61 + 208e: 2e 9b + 2090: 11 00 + 2092: 00 63 + 2094: 13 00 00 2f addi zero, zero, 752 + 2098: a7 11 00 00 + 209c: 78 01 + 209e: 00 00 + 20a0: 9f 0e 00 00 + 20a4: 2e ac + 20a6: 11 00 + 20a8: 00 8c + 20aa: 13 00 00 2e addi zero, zero, 736 + 20ae: b9 11 + 20b0: 00 00 + 20b2: ae 13 + 20b4: 00 00 + 20b6: 2e c6 + 20b8: 11 00 + 20ba: 00 d2 + 20bc: 13 00 00 2e addi zero, zero, 736 + 20c0: d3 11 00 00 fadd.s ft3, ft0, ft0, rtz + 20c4: f0 13 + 20c6: 00 00 + 20c8: 2e e0 + 20ca: 11 00 + 20cc: 00 0e + 20ce: 14 00 + 20d0: 00 2e + 20d2: ed 11 + 20d4: 00 00 + 20d6: 37 14 00 00 lui s0, 1 + 20da: 2e fa + 20dc: 11 00 + 20de: 00 6b + 20e0: 14 00 + 20e2: 00 00 + 20e4: 2f 08 12 00 + 20e8: 00 a0 + 20ea: 01 00 + 20ec: 00 f3 + 20ee: 0e 00 + 20f0: 00 2e + 20f2: 0d 12 + 20f4: 00 00 + 20f6: ad 14 + 20f8: 00 00 + 20fa: 2e 1a + 20fc: 12 00 + 20fe: 00 c0 + 2100: 14 00 + 2102: 00 2e + 2104: 27 12 00 00 + 2108: d3 14 00 00 fadd.s fs1, ft0, ft0, rtz + 210c: 2e 34 + 210e: 12 00 + 2110: 00 e6 + 2112: 14 00 + 2114: 00 2e + 2116: 41 12 + 2118: 00 00 + 211a: f9 14 + 211c: 00 00 + 211e: 2e 4e + 2120: 12 00 + 2122: 00 0c + 2124: 15 00 + 2126: 00 2e + 2128: 5b 12 00 00 + 212c: 3f 15 00 00 + 2130: 32 68 + 2132: 12 00 + 2134: 00 01 + 2136: 5d 00 + 2138: 30 76 + 213a: 12 00 + 213c: 00 b8 + 213e: 07 01 80 14 + 2142: 00 00 + 2144: 00 0e + 2146: 0f 00 00 2e + 214a: 7b 12 00 00 + 214e: 52 15 + 2150: 00 00 + 2152: 00 31 + 2154: 89 12 + 2156: 00 00 + 2158: cc 07 + 215a: 01 80 + 215c: 10 00 + 215e: 00 00 + 2160: 2e 8a + 2162: 12 00 + 2164: 00 65 + 2166: 15 00 + 2168: 00 00 + 216a: 00 00 + 216c: 00 00 + 216e: 33 55 06 00 srl a0, a2, zero + 2172: 00 01 + 2174: f7 03 01 34 + 2178: 0b 00 00 03 + 217c: 9a 12 + 217e: 00 00 + 2180: 34 6e + 2182: 00 01 + 2184: f7 03 17 34 + 2188: 0b 00 00 34 + 218c: 64 00 + 218e: 01 f7 + 2190: 03 22 34 0b lw tp, 179(s0) + 2194: 00 00 + 2196: 34 72 + 2198: 70 00 + 219a: 01 f7 + 219c: 03 2e 9a 12 lw t3, 297(s4) + 21a0: 00 00 + 21a2: 35 6e + 21a4: 6e 00 + 21a6: 01 f9 + 21a8: 03 11 bd 0b lh sp, 187(s10) + 21ac: 00 00 + 21ae: 35 64 + 21b0: 64 00 + 21b2: 01 fa + 21b4: 03 11 bd 0b lh sp, 187(s10) + 21b8: 00 00 + 21ba: 35 72 + 21bc: 72 00 + 21be: 01 fb + 21c0: 03 0b b0 0b lb s6, 187(zero) + 21c4: 00 00 + 21c6: 35 64 + 21c8: 30 00 + 21ca: 01 fc + 21cc: 03 0a 1c 0b lb s4, 177(s8) + 21d0: 00 00 + 21d2: 35 64 + 21d4: 31 00 + 21d6: 01 fc + 21d8: 03 0e 1c 0b lb t3, 177(s8) + 21dc: 00 00 + 21de: 35 6e + 21e0: 30 00 + 21e2: 01 fc + 21e4: 03 12 1c 0b lh tp, 177(s8) + 21e8: 00 00 + 21ea: 35 6e + 21ec: 31 00 + 21ee: 01 fc + 21f0: 03 16 1c 0b lh a2, 177(s8) + 21f4: 00 00 + 21f6: 35 6e + 21f8: 32 00 + 21fa: 01 fc + 21fc: 03 1a 1c 0b lh s4, 177(s8) + 2200: 00 00 + 2202: 35 71 + 2204: 30 00 + 2206: 01 fd + 2208: 03 0a 1c 0b lb s4, 177(s8) + 220c: 00 00 + 220e: 35 71 + 2210: 31 00 + 2212: 01 fd + 2214: 03 0e 1c 0b lb t3, 177(s8) + 2218: 00 00 + 221a: 35 62 + 221c: 00 01 + 221e: fe 03 + 2220: 0a 1c + 2222: 0b 00 00 35 + 2226: 62 6d + 2228: 00 01 + 222a: fe 03 + 222c: 0d 1c + 222e: 0b 00 00 35 + 2232: 77 77 00 01 + 2236: c7 04 11 bd + 223a: 0b 00 00 36 + 223e: 18 10 + 2240: 00 00 + 2242: 37 d6 06 00 lui a2, 109 + 2246: 00 01 + 2248: 2e 04 + 224a: 04 1c + 224c: 0b 00 00 35 + 2250: 5f 5f 61 00 + 2254: 01 2e + 2256: 04 04 + 2258: 1c 0b + 225a: 00 00 + 225c: 00 36 + 225e: 79 10 + 2260: 00 00 + 2262: 37 a3 00 00 lui t1, 10 + 2266: 00 01 + 2268: 3a 04 + 226a: 04 1c + 226c: 0b 00 00 37 + 2270: 9e 00 + 2272: 00 00 + 2274: 01 3a + 2276: 04 04 + 2278: 1c 0b + 227a: 00 00 + 227c: 37 89 06 00 lui s2, 104 + 2280: 00 01 + 2282: 3a 04 + 2284: 04 1c + 2286: 0b 00 00 37 + 228a: 84 06 + 228c: 00 00 + 228e: 01 3a + 2290: 04 04 + 2292: 1c 0b + 2294: 00 00 + 2296: 37 54 07 00 lui s0, 117 + 229a: 00 01 + 229c: 3a 04 + 229e: 04 1c + 22a0: 0b 00 00 37 + 22a4: 4f 07 00 00 fnmadd.s fa4, ft0, ft0, ft0, rne + 22a8: 01 3a + 22aa: 04 04 + 22ac: 1c 0b + 22ae: 00 00 + 22b0: 35 5f + 22b2: 5f 6d 00 01 + 22b6: 3a 04 + 22b8: 04 1c + 22ba: 0b 00 00 00 + 22be: 36 99 + 22c0: 10 00 + 22c2: 00 37 + 22c4: d6 06 + 22c6: 00 00 + 22c8: 01 46 + 22ca: 04 04 + 22cc: 1c 0b + 22ce: 00 00 + 22d0: 35 5f + 22d2: 5f 61 00 01 + 22d6: 46 04 + 22d8: 04 1c + 22da: 0b 00 00 00 + 22de: 36 fa + 22e0: 10 00 + 22e2: 00 37 + 22e4: a3 00 00 00 sb zero, 1(zero) + 22e8: 01 5f + 22ea: 04 08 + 22ec: 1c 0b + 22ee: 00 00 + 22f0: 37 9e 00 00 lui t3, 9 + 22f4: 00 01 + 22f6: 5f 04 08 1c + 22fa: 0b 00 00 37 + 22fe: 89 06 + 2300: 00 00 + 2302: 01 5f + 2304: 04 08 + 2306: 1c 0b + 2308: 00 00 + 230a: 37 84 06 00 lui s0, 104 + 230e: 00 01 + 2310: 5f 04 08 1c + 2314: 0b 00 00 37 + 2318: 54 07 + 231a: 00 00 + 231c: 01 5f + 231e: 04 08 + 2320: 1c 0b + 2322: 00 00 + 2324: 37 4f 07 00 lui t5, 116 + 2328: 00 01 + 232a: 5f 04 08 1c + 232e: 0b 00 00 35 + 2332: 5f 5f 6d 00 + 2336: 01 5f + 2338: 04 08 + 233a: 1c 0b + 233c: 00 00 + 233e: 00 36 + 2340: 5b 11 00 00 + 2344: 37 a3 00 00 lui t1, 10 + 2348: 00 01 + 234a: 64 04 + 234c: 04 1c + 234e: 0b 00 00 37 + 2352: 9e 00 + 2354: 00 00 + 2356: 01 64 + 2358: 04 04 + 235a: 1c 0b + 235c: 00 00 + 235e: 37 89 06 00 lui s2, 104 + 2362: 00 01 + 2364: 64 04 + 2366: 04 1c + 2368: 0b 00 00 37 + 236c: 84 06 + 236e: 00 00 + 2370: 01 64 + 2372: 04 04 + 2374: 1c 0b + 2376: 00 00 + 2378: 37 54 07 00 lui s0, 117 + 237c: 00 01 + 237e: 64 04 + 2380: 04 1c + 2382: 0b 00 00 37 + 2386: 4f 07 00 00 fnmadd.s fa4, ft0, ft0, ft0, rne + 238a: 01 64 + 238c: 04 04 + 238e: 1c 0b + 2390: 00 00 + 2392: 35 5f + 2394: 5f 6d 00 01 + 2398: 64 04 + 239a: 04 1c + 239c: 0b 00 00 00 + 23a0: 36 7b + 23a2: 11 00 + 23a4: 00 37 + 23a6: d6 06 + 23a8: 00 00 + 23aa: 01 87 + 23ac: 04 04 + 23ae: 1c 0b + 23b0: 00 00 + 23b2: 35 5f + 23b4: 5f 61 00 01 + 23b8: 87 04 04 1c + 23bc: 0b 00 00 00 + 23c0: 36 8e + 23c2: 11 00 + 23c4: 00 35 + 23c6: 5f 5f 78 00 + 23ca: 01 95 + 23cc: 04 05 + 23ce: 1c 0b + 23d0: 00 00 + 23d2: 00 38 + 23d4: 35 6d + 23d6: 31 00 + 23d8: 01 a5 + 23da: 04 0f + 23dc: 1c 0b + 23de: 00 00 + 23e0: 35 6d + 23e2: 30 00 + 23e4: 01 a5 + 23e6: 04 13 + 23e8: 1c 0b + 23ea: 00 00 + 23ec: 36 08 + 23ee: 12 00 + 23f0: 00 37 + 23f2: a3 00 00 00 sb zero, 1(zero) + 23f6: 01 b0 + 23f8: 04 08 + 23fa: 1c 0b + 23fc: 00 00 + 23fe: 37 9e 00 00 lui t3, 9 + 2402: 00 01 + 2404: b0 04 + 2406: 08 1c + 2408: 0b 00 00 37 + 240c: 89 06 + 240e: 00 00 + 2410: 01 b0 + 2412: 04 08 + 2414: 1c 0b + 2416: 00 00 + 2418: 37 84 06 00 lui s0, 104 + 241c: 00 01 + 241e: b0 04 + 2420: 08 1c + 2422: 0b 00 00 37 + 2426: 54 07 + 2428: 00 00 + 242a: 01 b0 + 242c: 04 08 + 242e: 1c 0b + 2430: 00 00 + 2432: 37 4f 07 00 lui t5, 116 + 2436: 00 01 + 2438: b0 04 + 243a: 08 1c + 243c: 0b 00 00 35 + 2440: 5f 5f 6d 00 + 2444: 01 b0 + 2446: 04 08 + 2448: 1c 0b + 244a: 00 00 + 244c: 00 36 + 244e: 76 12 + 2450: 00 00 + 2452: 37 11 06 00 lui sp, 97 + 2456: 00 01 + 2458: b1 04 + 245a: 08 1c + 245c: 0b 00 00 37 + 2460: 16 06 + 2462: 00 00 + 2464: 01 b1 + 2466: 04 08 + 2468: 1c 0b + 246a: 00 00 + 246c: 37 1b 06 00 lui s6, 97 + 2470: 00 01 + 2472: b1 04 + 2474: 08 1c + 2476: 0b 00 00 37 + 247a: 20 06 + 247c: 00 00 + 247e: 01 b1 + 2480: 04 08 + 2482: 1c 0b + 2484: 00 00 + 2486: 37 6d 03 00 lui s10, 54 + 248a: 00 01 + 248c: b1 04 + 248e: 08 1c + 2490: 0b 00 00 37 + 2494: 31 04 + 2496: 00 00 + 2498: 01 b1 + 249a: 04 08 + 249c: 1c 0b + 249e: 00 00 + 24a0: 37 57 03 00 lui a4, 53 + 24a4: 00 01 + 24a6: b1 04 + 24a8: 08 1c + 24aa: 0b 00 00 37 + 24ae: 2c 04 + 24b0: 00 00 + 24b2: 01 b1 + 24b4: 04 08 + 24b6: 1c 0b + 24b8: 00 00 + 24ba: 00 36 + 24bc: 89 12 + 24be: 00 00 + 24c0: 35 5f + 24c2: 5f 78 00 01 + 24c6: b6 04 + 24c8: 05 1c + 24ca: 0b 00 00 00 + 24ce: 38 35 + 24d0: 5f 5f 78 00 + 24d4: 01 be + 24d6: 04 05 + 24d8: 1c 0b + 24da: 00 00 + 24dc: 00 00 + 24de: 00 0f + 24e0: 04 34 + 24e2: 0b 00 00 00 + 24e6: 6b 07 00 00 vx_tex a4, zero, zero, zero, rne + 24ea: 04 00 + 24ec: b4 05 + 24ee: 00 00 + 24f0: 04 01 + 24f2: c8 09 + 24f4: 00 00 + 24f6: 0c 9a + 24f8: 09 00 + 24fa: 00 d5 + 24fc: 01 00 + 24fe: 00 f0 + 2500: 07 01 80 c0 + 2504: 08 00 + 2506: 00 e4 + 2508: 12 00 + 250a: 00 02 + 250c: 08 04 + 250e: c5 00 + 2510: 00 00 + 2512: 03 04 05 69 lb s0, 1680(a0) + 2516: 6e 74 + 2518: 00 02 + 251a: 01 06 + 251c: ad 06 + 251e: 00 00 + 2520: 02 08 + 2522: 05 f1 + 2524: 03 00 00 04 lb zero, 64(zero) + 2528: b7 07 00 00 lui a5, 0 + 252c: 02 4a + 252e: 01 16 + 2530: 53 00 00 00 fadd.s ft0, ft0, ft0, rne + 2534: 05 41 + 2536: 00 00 + 2538: 00 02 + 253a: 01 08 + 253c: ab 06 00 00 + 2540: 02 04 + 2542: 07 d4 02 00 + 2546: 00 02 + 2548: 08 07 + 254a: ca 02 + 254c: 00 00 + 254e: 04 3f + 2550: 08 00 + 2552: 00 02 + 2554: 4e 01 + 2556: 16 75 + 2558: 00 00 + 255a: 00 02 + 255c: 02 07 + 255e: ea 02 + 2560: 00 00 + 2562: 06 4e + 2564: 00 00 + 2566: 00 8c + 2568: 00 00 + 256a: 00 07 + 256c: 5a 00 + 256e: 00 00 + 2570: ff 00 05 7c + 2574: 00 00 + 2576: 00 08 + 2578: fd 02 + 257a: 00 00 + 257c: 04 3c + 257e: 16 8c + 2580: 00 00 + 2582: 00 09 + 2584: 7f 08 00 00 + 2588: 03 48 0f 25 lbu a6, 592(t5) + 258c: 00 00 + 258e: 00 0a + 2590: 08 03 + 2592: 4f 03 f3 00 fnmadd.s ft6, ft6, fa5, ft0, rne + 2596: 00 00 + 2598: 0b 60 08 00 + 259c: 00 03 + 259e: 57 0e 5a 00 + 25a2: 00 00 + 25a4: 04 20 + 25a6: 00 00 + 25a8: 0b 66 08 00 + 25ac: 00 03 + 25ae: 58 0e + 25b0: 5a 00 + 25b2: 00 00 + 25b4: 04 14 + 25b6: 0c 04 + 25b8: 0c 65 + 25ba: 78 70 + 25bc: 00 03 + 25be: 59 0e + 25c0: 5a 00 + 25c2: 00 00 + 25c4: 04 0b + 25c6: 01 04 + 25c8: 0b 41 02 00 + 25cc: 00 03 + 25ce: 5a 0e + 25d0: 5a 00 + 25d2: 00 00 + 25d4: 04 01 + 25d6: 00 04 + 25d8: 00 0d + 25da: 6a 0a + 25dc: 00 00 + 25de: 08 03 + 25e0: 4c 07 + 25e2: 19 01 + 25e4: 00 00 + 25e6: 0e 66 + 25e8: 6c 74 + 25ea: 00 03 + 25ec: 4e 0a + 25ee: 9d 00 + 25f0: 00 00 + 25f2: 0f 8d 0a 00 + 25f6: 00 03 + 25f8: 5c 05 + 25fa: a9 00 + 25fc: 00 00 + 25fe: 00 10 + 2600: 36 08 + 2602: 00 00 + 2604: 01 23 + 2606: 01 9d + 2608: 00 00 + 260a: 00 f0 + 260c: 07 01 80 c0 + 2610: 08 00 + 2612: 00 01 + 2614: 9c 60 + 2616: 07 00 00 11 + 261a: 61 00 + 261c: 01 23 + 261e: 12 9d + 2620: 00 00 + 2622: 00 78 + 2624: 15 00 + 2626: 00 11 + 2628: 62 00 + 262a: 01 23 + 262c: 1c 9d + 262e: 00 00 + 2630: 00 20 + 2632: 16 00 + 2634: 00 12 + 2636: f2 08 + 2638: 00 00 + 263a: 01 25 + 263c: 03 2c 00 00 lw s8, 0(zero) + 2640: 00 c8 + 2642: 16 00 + 2644: 00 12 + 2646: 92 0a + 2648: 00 00 + 264a: 01 25 + 264c: 03 2c 00 00 lw s8, 0(zero) + 2650: 00 39 + 2652: 17 00 00 13 auipc zero, 77824 + 2656: 41 5f + 2658: 63 00 01 26 beqz sp, 608 + 265c: 03 60 07 00 + 2660: 00 57 + 2662: 17 00 00 13 auipc zero, 77824 + 2666: 41 5f + 2668: 73 00 01 26 + 266c: 03 60 07 00 + 2670: 00 98 + 2672: 17 00 00 13 auipc zero, 77824 + 2676: 41 5f + 2678: 65 00 + 267a: 01 26 + 267c: 03 60 07 00 + 2680: 00 c0 + 2682: 17 00 00 12 auipc zero, 73728 + 2686: 8b 09 00 00 + 268a: 01 26 + 268c: 03 67 07 00 + 2690: 00 75 + 2692: 18 00 + 2694: 00 12 + 2696: ed 08 + 2698: 00 00 + 269a: 01 26 + 269c: 03 67 07 00 + 26a0: 00 18 + 26a2: 19 00 + 26a4: 00 13 + 26a6: 42 5f + 26a8: 63 00 01 27 beq sp, a6, 608 + 26ac: 03 60 07 00 + 26b0: 00 cb + 26b2: 19 00 + 26b4: 00 13 + 26b6: 42 5f + 26b8: 73 00 01 27 + 26bc: 03 60 07 00 + 26c0: 00 39 + 26c2: 1a 00 + 26c4: 00 13 + 26c6: 42 5f + 26c8: 65 00 + 26ca: 01 27 + 26cc: 03 60 07 00 + 26d0: 00 71 + 26d2: 1a 00 + 26d4: 00 12 + 26d6: 90 09 + 26d8: 00 00 + 26da: 01 27 + 26dc: 03 67 07 00 + 26e0: 00 c8 + 26e2: 1a 00 + 26e4: 00 12 + 26e6: 95 09 + 26e8: 00 00 + 26ea: 01 27 + 26ec: 03 67 07 00 + 26f0: 00 a2 + 26f2: 1b 00 00 13 + 26f6: 52 5f + 26f8: 63 00 01 28 beqz sp, 640 + 26fc: 03 60 07 00 + 2700: 00 52 + 2702: 1c 00 + 2704: 00 13 + 2706: 52 5f + 2708: 73 00 01 28 + 270c: 03 60 07 00 + 2710: 00 aa + 2712: 1c 00 + 2714: 00 13 + 2716: 52 5f + 2718: 65 00 + 271a: 01 28 + 271c: 03 60 07 00 + 2720: 00 7c + 2722: 1d 00 + 2724: 00 12 + 2726: d3 08 00 00 fadd.s fa7, ft0, ft0, rne + 272a: 01 28 + 272c: 03 67 07 00 + 2730: 00 22 + 2732: 1e 00 + 2734: 00 12 + 2736: 97 0a 00 00 auipc s5, 0 + 273a: 01 28 + 273c: 03 67 07 00 + 2740: 00 7b + 2742: 1f 00 00 14 + 2746: 72 00 + 2748: 01 29 + 274a: 0a 9d + 274c: 00 00 + 274e: 00 15 + 2750: b8 01 + 2752: 00 00 + 2754: 7f 02 00 00 + 2758: 16 d8 + 275a: 08 00 + 275c: 00 01 + 275e: 2c 03 + 2760: f3 00 00 00 + 2764: 00 15 + 2766: d8 01 + 2768: 00 00 + 276a: 99 02 + 276c: 00 00 + 276e: 12 86 + 2770: 08 00 + 2772: 00 01 + 2774: 2c 03 + 2776: 60 07 + 2778: 00 00 + 277a: 90 20 + 277c: 00 00 + 277e: 00 15 + 2780: f0 01 + 2782: 00 00 + 2784: af 02 00 00 + 2788: 16 d8 + 278a: 08 00 + 278c: 00 01 + 278e: 2d 03 + 2790: f3 00 00 00 + 2794: 00 15 + 2796: 10 02 + 2798: 00 00 + 279a: c9 02 + 279c: 00 00 + 279e: 12 86 + 27a0: 08 00 + 27a2: 00 01 + 27a4: 2d 03 + 27a6: 60 07 + 27a8: 00 00 + 27aa: c4 20 + 27ac: 00 00 + 27ae: 00 15 + 27b0: 28 02 + 27b2: 00 00 + 27b4: d5 05 + 27b6: 00 00 + 27b8: 12 29 + 27ba: 09 00 + 27bc: 00 01 + 27be: 2e 03 + 27c0: 67 07 00 00 jalr a4, zero + 27c4: 03 21 00 00 lw sp, 0(zero) + 27c8: 12 10 + 27ca: 09 00 + 27cc: 00 01 + 27ce: 2e 03 + 27d0: 67 07 00 00 jalr a4, zero + 27d4: 30 21 + 27d6: 00 00 + 27d8: 12 f7 + 27da: 08 00 + 27dc: 00 01 + 27de: 2e 03 + 27e0: 67 07 00 00 jalr a4, zero + 27e4: 5e 21 + 27e6: 00 00 + 27e8: 12 ba + 27ea: 08 00 + 27ec: 00 01 + 27ee: 2e 03 + 27f0: 67 07 00 00 jalr a4, zero + 27f4: 7d 21 + 27f6: 00 00 + 27f8: 12 a1 + 27fa: 08 00 + 27fc: 00 01 + 27fe: 2e 03 + 2800: 67 07 00 00 jalr a4, zero + 2804: d2 21 + 2806: 00 00 + 2808: 12 47 + 280a: 08 00 + 280c: 00 01 + 280e: 2e 03 + 2810: 67 07 00 00 jalr a4, zero + 2814: 3e 22 + 2816: 00 00 + 2818: 12 1d + 281a: 08 00 + 281c: 00 01 + 281e: 2e 03 + 2820: 67 07 00 00 jalr a4, zero + 2824: 67 22 00 00 + 2828: 15 48 + 282a: 02 00 + 282c: 00 bc + 282e: 03 00 00 12 lb zero, 288(zero) + 2832: a3 00 00 00 sb zero, 1(zero) + 2836: 01 2e + 2838: 03 67 07 00 + 283c: 00 c2 + 283e: 22 00 + 2840: 00 12 + 2842: 9e 00 + 2844: 00 00 + 2846: 01 2e + 2848: 03 67 07 00 + 284c: 00 d5 + 284e: 22 00 + 2850: 00 12 + 2852: 89 06 + 2854: 00 00 + 2856: 01 2e + 2858: 03 67 07 00 + 285c: 00 0a + 285e: 23 00 00 12 sb zero, 288(zero) + 2862: 84 06 + 2864: 00 00 + 2866: 01 2e + 2868: 03 67 07 00 + 286c: 00 28 + 286e: 23 00 00 12 sb zero, 288(zero) + 2872: 54 07 + 2874: 00 00 + 2876: 01 2e + 2878: 03 67 07 00 + 287c: 00 46 + 287e: 23 00 00 12 sb zero, 288(zero) + 2882: 4f 07 00 00 fnmadd.s fa4, ft0, ft0, ft0, rne + 2886: 01 2e + 2888: 03 67 07 00 + 288c: 00 91 + 288e: 23 00 00 13 sb a6, 288(zero) + 2892: 5f 5f 6d 00 + 2896: 01 2e + 2898: 03 67 07 00 + 289c: 00 d5 + 289e: 23 00 00 00 sb zero, 0(zero) + 28a2: 17 24 0b 01 auipc s0, 4274 + 28a6: 80 58 + 28a8: 00 00 + 28aa: 00 4a + 28ac: 04 00 + 28ae: 00 12 + 28b0: 11 06 + 28b2: 00 00 + 28b4: 01 2e + 28b6: 03 67 07 00 + 28ba: 00 f8 + 28bc: 23 00 00 12 sb zero, 288(zero) + 28c0: 16 06 + 28c2: 00 00 + 28c4: 01 2e + 28c6: 03 67 07 00 + 28ca: 00 44 + 28cc: 24 00 + 28ce: 00 12 + 28d0: 1b 06 00 00 + 28d4: 01 2e + 28d6: 03 67 07 00 + 28da: 00 a6 + 28dc: 24 00 + 28de: 00 12 + 28e0: 20 06 + 28e2: 00 00 + 28e4: 01 2e + 28e6: 03 67 07 00 + 28ea: 00 c4 + 28ec: 24 00 + 28ee: 00 12 + 28f0: 6d 03 + 28f2: 00 00 + 28f4: 01 2e + 28f6: 03 68 00 00 + 28fa: 00 d7 + 28fc: 24 00 + 28fe: 00 12 + 2900: 31 04 + 2902: 00 00 + 2904: 01 2e + 2906: 03 68 00 00 + 290a: 00 ea + 290c: 24 00 + 290e: 00 12 + 2910: 57 03 00 00 + 2914: 01 2e + 2916: 03 68 00 00 + 291a: 00 08 + 291c: 25 00 + 291e: 00 12 + 2920: 2c 04 + 2922: 00 00 + 2924: 01 2e + 2926: 03 68 00 00 + 292a: 00 48 + 292c: 25 00 + 292e: 00 00 + 2930: 15 68 + 2932: 02 00 + 2934: 00 64 + 2936: 04 00 + 2938: 00 13 + 293a: 5f 5f 78 00 + 293e: 01 2e + 2940: 03 67 07 00 + 2944: 00 79 + 2946: 25 00 + 2948: 00 00 + 294a: 15 80 + 294c: 02 00 + 294e: 00 7e + 2950: 04 00 + 2952: 00 13 + 2954: 5f 5f 78 00 + 2958: 01 2e + 295a: 03 67 07 00 + 295e: 00 8c + 2960: 25 00 + 2962: 00 00 + 2964: 17 cc 0b 01 auipc s8, 4284 + 2968: 80 10 + 296a: 00 00 + 296c: 00 9c + 296e: 04 00 + 2970: 00 13 + 2972: 5f 5f 78 00 + 2976: 01 2e + 2978: 03 67 07 00 + 297c: 00 9f + 297e: 25 00 + 2980: 00 00 + 2982: 15 98 + 2984: 02 00 + 2986: 00 16 + 2988: 05 00 + 298a: 00 12 + 298c: a3 00 00 00 sb zero, 1(zero) + 2990: 01 2e + 2992: 03 67 07 00 + 2996: 00 b2 + 2998: 25 00 + 299a: 00 12 + 299c: 9e 00 + 299e: 00 00 + 29a0: 01 2e + 29a2: 03 67 07 00 + 29a6: 00 c5 + 29a8: 25 00 + 29aa: 00 12 + 29ac: 89 06 + 29ae: 00 00 + 29b0: 01 2e + 29b2: 03 67 07 00 + 29b6: 00 fa + 29b8: 25 00 + 29ba: 00 12 + 29bc: 84 06 + 29be: 00 00 + 29c0: 01 2e + 29c2: 03 67 07 00 + 29c6: 00 18 + 29c8: 26 00 + 29ca: 00 12 + 29cc: 54 07 + 29ce: 00 00 + 29d0: 01 2e + 29d2: 03 67 07 00 + 29d6: 00 36 + 29d8: 26 00 + 29da: 00 12 + 29dc: 4f 07 00 00 fnmadd.s fa4, ft0, ft0, ft0, rne + 29e0: 01 2e + 29e2: 03 67 07 00 + 29e6: 00 6f + 29e8: 26 00 + 29ea: 00 13 + 29ec: 5f 5f 6d 00 + 29f0: 01 2e + 29f2: 03 67 07 00 + 29f6: 00 a8 + 29f8: 26 00 + 29fa: 00 00 + 29fc: 17 70 0c 01 auipc zero, 4295 + 2a00: 80 4c + 2a02: 00 00 + 2a04: 00 a4 + 2a06: 05 00 + 2a08: 00 12 + 2a0a: 11 06 + 2a0c: 00 00 + 2a0e: 01 2e + 2a10: 03 67 07 00 + 2a14: 00 fe + 2a16: 26 00 + 2a18: 00 12 + 2a1a: 16 06 + 2a1c: 00 00 + 2a1e: 01 2e + 2a20: 03 67 07 00 + 2a24: 00 56 + 2a26: 27 00 00 12 + 2a2a: 1b 06 00 00 + 2a2e: 01 2e + 2a30: 03 67 07 00 + 2a34: 00 f3 + 2a36: 27 00 00 12 + 2a3a: 20 06 + 2a3c: 00 00 + 2a3e: 01 2e + 2a40: 03 67 07 00 + 2a44: 00 45 + 2a46: 28 00 + 2a48: 00 12 + 2a4a: 6d 03 + 2a4c: 00 00 + 2a4e: 01 2e + 2a50: 03 68 00 00 + 2a54: 00 58 + 2a56: 28 00 + 2a58: 00 12 + 2a5a: 31 04 + 2a5c: 00 00 + 2a5e: 01 2e + 2a60: 03 68 00 00 + 2a64: 00 83 + 2a66: 28 00 + 2a68: 00 12 + 2a6a: 57 03 00 00 + 2a6e: 01 2e + 2a70: 03 68 00 00 + 2a74: 00 a1 + 2a76: 28 00 + 2a78: 00 12 + 2a7a: 2c 04 + 2a7c: 00 00 + 2a7e: 01 2e + 2a80: 03 68 00 00 + 2a84: 00 e1 + 2a86: 28 00 + 2a88: 00 00 + 2a8a: 15 b0 + 2a8c: 02 00 + 2a8e: 00 be + 2a90: 05 00 + 2a92: 00 13 + 2a94: 5f 5f 78 00 + 2a98: 01 2e + 2a9a: 03 67 07 00 + 2a9e: 00 12 + 2aa0: 29 00 + 2aa2: 00 00 + 2aa4: 18 c8 + 2aa6: 02 00 + 2aa8: 00 13 + 2aaa: 5f 5f 78 00 + 2aae: 01 2e + 2ab0: 03 67 07 00 + 2ab4: 00 30 + 2ab6: 29 00 + 2ab8: 00 00 + 2aba: 00 17 + 2abc: 3c 0d + 2abe: 01 80 + 2ac0: 04 00 + 2ac2: 00 00 + 2ac4: ef 05 00 00 jal a1, 0 + 2ac8: 14 5f + 2aca: 5f 78 00 01 + 2ace: 2f 03 67 07 + 2ad2: 00 00 + 2ad4: 00 19 + 2ad6: 01 06 + 2ad8: 00 00 + 2ada: 14 5f + 2adc: 5f 78 00 01 + 2ae0: 2f 03 67 07 + 2ae4: 00 00 + 2ae6: 00 15 + 2ae8: e0 02 + 2aea: 00 00 + 2aec: 1b 06 00 00 + 2af0: 13 5f 5f 78 + 2af4: 00 01 + 2af6: 2f 03 67 07 + 2afa: 00 00 + 2afc: 43 29 00 00 fmadd.s fs2, ft0, ft0, ft0, rdn + 2b00: 00 15 + 2b02: 10 03 + 2b04: 00 00 + 2b06: 4d 07 + 2b08: 00 00 + 2b0a: 12 59 + 2b0c: 09 00 + 2b0e: 00 01 + 2b10: 2f 03 2c 00 + 2b14: 00 00 + 2b16: 56 29 + 2b18: 00 00 + 2b1a: 17 a8 0e 01 auipc a6, 4330 + 2b1e: 80 68 + 2b20: 00 00 + 2b22: 00 d0 + 2b24: 06 00 + 2b26: 00 16 + 2b28: 74 09 + 2b2a: 00 00 + 2b2c: 01 2f + 2b2e: 03 60 07 00 + 2b32: 00 16 + 2b34: 42 09 + 2b36: 00 00 + 2b38: 01 2f + 2b3a: 03 60 07 00 + 2b3e: 00 12 + 2b40: 76 0a + 2b42: 00 00 + 2b44: 01 2f + 2b46: 03 60 07 00 + 2b4a: 00 9c + 2b4c: 29 00 + 2b4e: 00 12 + 2b50: ed 07 + 2b52: 00 00 + 2b54: 01 2f + 2b56: 03 67 07 00 + 2b5a: 00 b0 + 2b5c: 29 00 + 2b5e: 00 12 + 2b60: 05 08 + 2b62: 00 00 + 2b64: 01 2f + 2b66: 03 67 07 00 + 2b6a: 00 ce + 2b6c: 29 00 + 2b6e: 00 17 + 2b70: dc 0e + 2b72: 01 80 + 2b74: 04 00 + 2b76: 00 00 + 2b78: a7 06 00 00 + 2b7c: 13 5f 5f 78 + 2b80: 00 01 + 2b82: 2f 03 67 07 + 2b86: 00 00 + 2b88: 02 2a + 2b8a: 00 00 + 2b8c: 00 19 + 2b8e: b9 06 + 2b90: 00 00 + 2b92: 14 5f + 2b94: 5f 78 00 01 + 2b98: 2f 03 67 07 + 2b9c: 00 00 + 2b9e: 00 18 + 2ba0: 28 03 + 2ba2: 00 00 + 2ba4: 13 5f 5f 78 + 2ba8: 00 01 + 2baa: 2f 03 67 07 + 2bae: 00 00 + 2bb0: 17 2a 00 00 auipc s4, 2 + 2bb4: 00 00 + 2bb6: 17 74 0f 01 auipc s0, 4343 + 2bba: 80 04 + 2bbc: 00 00 + 2bbe: 00 ea + 2bc0: 06 00 + 2bc2: 00 14 + 2bc4: 5f 5f 78 00 + 2bc8: 01 2f + 2bca: 03 67 07 00 + 2bce: 00 00 + 2bd0: 19 fc + 2bd2: 06 00 + 2bd4: 00 14 + 2bd6: 5f 5f 78 00 + 2bda: 01 2f + 2bdc: 03 67 07 00 + 2be0: 00 00 + 2be2: 15 40 + 2be4: 03 00 00 16 lb zero, 352(zero) + 2be8: 07 00 00 13 + 2bec: 5f 5f 78 00 + 2bf0: 01 2f + 2bf2: 03 67 07 00 + 2bf6: 00 2c + 2bf8: 2a 00 + 2bfa: 00 00 + 2bfc: 19 28 + 2bfe: 07 00 00 14 + 2c02: 5f 5f 78 00 + 2c06: 01 2f + 2c08: 03 67 07 00 + 2c0c: 00 00 + 2c0e: 15 58 + 2c10: 03 00 00 3e lb zero, 992(zero) + 2c14: 07 00 00 14 + 2c18: 5f 5f 78 00 + 2c1c: 01 2f + 2c1e: 03 67 07 00 + 2c22: 00 00 + 2c24: 1a 14 + 2c26: 5f 5f 78 00 + 2c2a: 01 2f + 2c2c: 03 67 07 00 + 2c30: 00 00 + 2c32: 00 18 + 2c34: f8 02 + 2c36: 00 00 + 2c38: 16 6c + 2c3a: 08 00 + 2c3c: 00 01 + 2c3e: 2f 03 f3 00 + 2c42: 00 00 + 2c44: 00 00 + 2c46: 02 04 + 2c48: 05 f6 + 2c4a: 03 00 00 02 lb zero, 32(zero) + 2c4e: 04 07 + 2c50: cf 02 00 00 fnmadd.s ft5, ft0, ft0, ft0, rne + 2c54: 00 97 + 2c56: 07 00 00 04 + 2c5a: 00 2a + 2c5c: 07 00 00 04 + 2c60: 01 c8 + 2c62: 09 00 + 2c64: 00 0c + 2c66: 92 0b + 2c68: 00 00 + 2c6a: d5 01 + 2c6c: 00 00 + 2c6e: b0 10 + 2c70: 01 80 + 2c72: a8 07 + 2c74: 00 00 + 2c76: 31 25 + 2c78: 00 00 + 2c7a: 02 08 + 2c7c: 04 c5 + 2c7e: 00 00 + 2c80: 00 03 + 2c82: 04 05 + 2c84: 69 6e + 2c86: 74 00 + 2c88: 02 01 + 2c8a: 06 ad + 2c8c: 06 00 + 2c8e: 00 02 + 2c90: 08 05 + 2c92: f1 03 + 2c94: 00 00 + 2c96: 04 b7 + 2c98: 07 00 00 02 + 2c9c: 4a 01 + 2c9e: 16 53 + 2ca0: 00 00 + 2ca2: 00 05 + 2ca4: 41 00 + 2ca6: 00 00 + 2ca8: 02 01 + 2caa: 08 ab + 2cac: 06 00 + 2cae: 00 02 + 2cb0: 04 07 + 2cb2: d4 02 + 2cb4: 00 00 + 2cb6: 02 08 + 2cb8: 07 ca 02 00 + 2cbc: 00 04 + 2cbe: 3f 08 00 00 + 2cc2: 02 4e + 2cc4: 01 16 + 2cc6: 75 00 + 2cc8: 00 00 + 2cca: 02 02 + 2ccc: 07 ea 02 00 + 2cd0: 00 06 + 2cd2: 4e 00 + 2cd4: 00 00 + 2cd6: 8c 00 + 2cd8: 00 00 + 2cda: 07 5a 00 00 + 2cde: 00 ff + 2ce0: 00 05 + 2ce2: 7c 00 + 2ce4: 00 00 + 2ce6: 08 fd + 2ce8: 02 00 + 2cea: 00 04 + 2cec: 3c 16 + 2cee: 8c 00 + 2cf0: 00 00 + 2cf2: 09 7f + 2cf4: 08 00 + 2cf6: 00 03 + 2cf8: 48 0f + 2cfa: 25 00 + 2cfc: 00 00 + 2cfe: 0a 08 + 2d00: 03 4f 03 f3 lbu t5, -208(t1) + 2d04: 00 00 + 2d06: 00 0b + 2d08: 60 08 + 2d0a: 00 00 + 2d0c: 03 57 0e 5a lhu a4, 1440(t3) + 2d10: 00 00 + 2d12: 00 04 + 2d14: 20 00 + 2d16: 00 0b + 2d18: 66 08 + 2d1a: 00 00 + 2d1c: 03 58 0e 5a lhu a6, 1440(t3) + 2d20: 00 00 + 2d22: 00 04 + 2d24: 14 0c + 2d26: 04 0c + 2d28: 65 78 + 2d2a: 70 00 + 2d2c: 03 59 0e 5a lhu s2, 1440(t3) + 2d30: 00 00 + 2d32: 00 04 + 2d34: 0b 01 04 0b + 2d38: 41 02 + 2d3a: 00 00 + 2d3c: 03 5a 0e 5a lhu s4, 1440(t3) + 2d40: 00 00 + 2d42: 00 04 + 2d44: 01 00 + 2d46: 04 00 + 2d48: 0d 6a + 2d4a: 0a 00 + 2d4c: 00 08 + 2d4e: 03 4c 07 19 lbu s8, 400(a4) + 2d52: 01 00 + 2d54: 00 0e + 2d56: 66 6c + 2d58: 74 00 + 2d5a: 03 4e 0a 9d lbu t3, -1584(s4) + 2d5e: 00 00 + 2d60: 00 0f + 2d62: 8d 0a + 2d64: 00 00 + 2d66: 03 5c 05 a9 lhu s8, -1392(a0) + 2d6a: 00 00 + 2d6c: 00 00 + 2d6e: 10 26 + 2d70: 0b 00 00 01 + 2d74: 23 01 9d 00 sb s1, 2(s10) + 2d78: 00 00 + 2d7a: b0 10 + 2d7c: 01 80 + 2d7e: a8 07 + 2d80: 00 00 + 2d82: 01 9c + 2d84: 80 07 + 2d86: 00 00 + 2d88: 11 61 + 2d8a: 00 01 + 2d8c: 23 12 9d 00 sh s1, 4(s10) + 2d90: 00 00 + 2d92: 3f 2a 00 00 + 2d96: 11 62 + 2d98: 00 01 + 2d9a: 23 1c 9d 00 sh s1, 24(s10) + 2d9e: 00 00 + 2da0: e7 2a 00 00 + 2da4: 12 f2 + 2da6: 08 00 + 2da8: 00 01 + 2daa: 25 03 + 2dac: 2c 00 + 2dae: 00 00 + 2db0: 8f 2b 00 00 + 2db4: 12 92 + 2db6: 0a 00 + 2db8: 00 01 + 2dba: 25 03 + 2dbc: 2c 00 + 2dbe: 00 00 + 2dc0: f5 2b + 2dc2: 00 00 + 2dc4: 13 41 5f 63 xori sp, t5, 1589 + 2dc8: 00 01 + 2dca: 26 03 + 2dcc: 80 07 + 2dce: 00 00 + 2dd0: 13 2c 00 00 slti s8, zero, 0 + 2dd4: 13 41 5f 73 xori sp, t5, 1845 + 2dd8: 00 01 + 2dda: 26 03 + 2ddc: 80 07 + 2dde: 00 00 + 2de0: 54 2c + 2de2: 00 00 + 2de4: 13 41 5f 65 xori sp, t5, 1621 + 2de8: 00 01 + 2dea: 26 03 + 2dec: 80 07 + 2dee: 00 00 + 2df0: 7c 2c + 2df2: 00 00 + 2df4: 12 8b + 2df6: 09 00 + 2df8: 00 01 + 2dfa: 26 03 + 2dfc: 87 07 00 00 + 2e00: 26 2d + 2e02: 00 00 + 2e04: 12 ed + 2e06: 08 00 + 2e08: 00 01 + 2e0a: 26 03 + 2e0c: 87 07 00 00 + 2e10: d4 2d + 2e12: 00 00 + 2e14: 13 42 5f 63 xori tp, t5, 1589 + 2e18: 00 01 + 2e1a: 27 03 80 07 + 2e1e: 00 00 + 2e20: 92 2e + 2e22: 00 00 + 2e24: 13 42 5f 73 xori tp, t5, 1845 + 2e28: 00 01 + 2e2a: 27 03 80 07 + 2e2e: 00 00 + 2e30: f5 2e + 2e32: 00 00 + 2e34: 13 42 5f 65 xori tp, t5, 1621 + 2e38: 00 01 + 2e3a: 27 03 80 07 + 2e3e: 00 00 + 2e40: 2d 2f + 2e42: 00 00 + 2e44: 12 90 + 2e46: 09 00 + 2e48: 00 01 + 2e4a: 27 03 87 07 + 2e4e: 00 00 + 2e50: eb 2f 00 00 vx_tex t6, zero, zero, zero, rdn + 2e54: 12 95 + 2e56: 09 00 + 2e58: 00 01 + 2e5a: 27 03 87 07 + 2e5e: 00 00 + 2e60: a4 30 + 2e62: 00 00 + 2e64: 13 52 5f 63 + 2e68: 00 01 + 2e6a: 28 03 + 2e6c: 80 07 + 2e6e: 00 00 + 2e70: 2b 31 00 00 + 2e74: 13 52 5f 73 + 2e78: 00 01 + 2e7a: 28 03 + 2e7c: 80 07 + 2e7e: 00 00 + 2e80: 61 31 + 2e82: 00 00 + 2e84: 13 52 5f 65 + 2e88: 00 01 + 2e8a: 28 03 + 2e8c: 80 07 + 2e8e: 00 00 + 2e90: f7 31 00 00 + 2e94: 12 d3 + 2e96: 08 00 + 2e98: 00 01 + 2e9a: 28 03 + 2e9c: 87 07 00 00 + 2ea0: aa 32 + 2ea2: 00 00 + 2ea4: 12 97 + 2ea6: 0a 00 + 2ea8: 00 01 + 2eaa: 28 03 + 2eac: 87 07 00 00 + 2eb0: d7 33 00 00 + 2eb4: 14 72 + 2eb6: 00 01 + 2eb8: 29 0a + 2eba: 9d 00 + 2ebc: 00 00 + 2ebe: 15 70 + 2ec0: 03 00 00 7f lb zero, 2032(zero) + 2ec4: 02 00 + 2ec6: 00 16 + 2ec8: d8 08 + 2eca: 00 00 + 2ecc: 01 2c + 2ece: 03 f3 00 00 + 2ed2: 00 00 + 2ed4: 15 90 + 2ed6: 03 00 00 99 lb zero, -1648(zero) + 2eda: 02 00 + 2edc: 00 12 + 2ede: 86 08 + 2ee0: 00 00 + 2ee2: 01 2c + 2ee4: 03 80 07 00 lb zero, 0(a5) + 2ee8: 00 9f + 2eea: 34 00 + 2eec: 00 00 + 2eee: 15 a8 + 2ef0: 03 00 00 af lb zero, -1296(zero) + 2ef4: 02 00 + 2ef6: 00 16 + 2ef8: d8 08 + 2efa: 00 00 + 2efc: 01 2d + 2efe: 03 f3 00 00 + 2f02: 00 00 + 2f04: 15 c8 + 2f06: 03 00 00 c9 lb zero, -880(zero) + 2f0a: 02 00 + 2f0c: 00 12 + 2f0e: 86 08 + 2f10: 00 00 + 2f12: 01 2d + 2f14: 03 80 07 00 lb zero, 0(a5) + 2f18: 00 d3 + 2f1a: 34 00 + 2f1c: 00 00 + 2f1e: 15 e0 + 2f20: 03 00 00 f1 lb zero, -240(zero) + 2f24: 05 00 + 2f26: 00 16 + 2f28: 7a 0b + 2f2a: 00 00 + 2f2c: 01 2e + 2f2e: 03 8e 07 00 lb t3, 0(a5) + 2f32: 00 15 + 2f34: f8 03 + 2f36: 00 00 + 2f38: 88 05 + 2f3a: 00 00 + 2f3c: 12 c0 + 2f3e: 0b 00 00 01 + 2f42: 2e 03 + 2f44: 87 07 00 00 + 2f48: 07 35 00 00 + 2f4c: 12 dc + 2f4e: 0b 00 00 01 + 2f52: 2e 03 + 2f54: 87 07 00 00 + 2f58: 1a 35 + 2f5a: 00 00 + 2f5c: 12 2f + 2f5e: 0b 00 00 01 + 2f62: 2e 03 + 2f64: 87 07 00 00 + 2f68: 38 35 + 2f6a: 00 00 + 2f6c: 12 4b + 2f6e: 0b 00 00 01 + 2f72: 2e 03 + 2f74: 87 07 00 00 + 2f78: 4b 35 00 00 fnmsub.s fa0, ft0, ft0, ft0, rup + 2f7c: 15 18 + 2f7e: 04 00 + 2f80: 00 b1 + 2f82: 03 00 00 12 lb zero, 288(zero) + 2f86: 11 06 + 2f88: 00 00 + 2f8a: 01 2e + 2f8c: 03 87 07 00 lb a4, 0(a5) + 2f90: 00 5e + 2f92: 35 00 + 2f94: 00 12 + 2f96: 16 06 + 2f98: 00 00 + 2f9a: 01 2e + 2f9c: 03 87 07 00 lb a4, 0(a5) + 2fa0: 00 81 + 2fa2: 35 00 + 2fa4: 00 12 + 2fa6: 1b 06 00 00 + 2faa: 01 2e + 2fac: 03 87 07 00 lb a4, 0(a5) + 2fb0: 00 e8 + 2fb2: 35 00 + 2fb4: 00 12 + 2fb6: 20 06 + 2fb8: 00 00 + 2fba: 01 2e + 2fbc: 03 87 07 00 lb a4, 0(a5) + 2fc0: 00 0b + 2fc2: 36 00 + 2fc4: 00 12 + 2fc6: 6d 03 + 2fc8: 00 00 + 2fca: 01 2e + 2fcc: 03 68 00 00 + 2fd0: 00 1e + 2fd2: 36 00 + 2fd4: 00 12 + 2fd6: 31 04 + 2fd8: 00 00 + 2fda: 01 2e + 2fdc: 03 68 00 00 + 2fe0: 00 31 + 2fe2: 36 00 + 2fe4: 00 12 + 2fe6: 57 03 00 00 + 2fea: 01 2e + 2fec: 03 68 00 00 + 2ff0: 00 44 + 2ff2: 36 00 + 2ff4: 00 12 + 2ff6: 2c 04 + 2ff8: 00 00 + 2ffa: 01 2e + 2ffc: 03 68 00 00 + 3000: 00 57 + 3002: 36 00 + 3004: 00 00 + 3006: 15 30 + 3008: 04 00 + 300a: 00 33 + 300c: 04 00 + 300e: 00 12 + 3010: 11 06 + 3012: 00 00 + 3014: 01 2e + 3016: 03 87 07 00 lb a4, 0(a5) + 301a: 00 6a + 301c: 36 00 + 301e: 00 12 + 3020: 16 06 + 3022: 00 00 + 3024: 01 2e + 3026: 03 87 07 00 lb a4, 0(a5) + 302a: 00 7d + 302c: 36 00 + 302e: 00 12 + 3030: 1b 06 00 00 + 3034: 01 2e + 3036: 03 87 07 00 lb a4, 0(a5) + 303a: 00 ab + 303c: 36 00 + 303e: 00 12 + 3040: 20 06 + 3042: 00 00 + 3044: 01 2e + 3046: 03 87 07 00 lb a4, 0(a5) + 304a: 00 be + 304c: 36 00 + 304e: 00 16 + 3050: 6d 03 + 3052: 00 00 + 3054: 01 2e + 3056: 03 68 00 00 + 305a: 00 16 + 305c: 31 04 + 305e: 00 00 + 3060: 01 2e + 3062: 03 68 00 00 + 3066: 00 12 + 3068: 57 03 00 00 + 306c: 01 2e + 306e: 03 68 00 00 + 3072: 00 d1 + 3074: 36 00 + 3076: 00 12 + 3078: 2c 04 + 307a: 00 00 + 307c: 01 2e + 307e: 03 68 00 00 + 3082: 00 e4 + 3084: 36 00 + 3086: 00 00 + 3088: 15 50 + 308a: 04 00 + 308c: 00 b5 + 308e: 04 00 + 3090: 00 12 + 3092: 11 06 + 3094: 00 00 + 3096: 01 2e + 3098: 03 87 07 00 lb a4, 0(a5) + 309c: 00 f7 + 309e: 36 00 + 30a0: 00 12 + 30a2: 16 06 + 30a4: 00 00 + 30a6: 01 2e + 30a8: 03 87 07 00 lb a4, 0(a5) + 30ac: 00 0a + 30ae: 37 00 00 12 lui zero, 73728 + 30b2: 1b 06 00 00 + 30b6: 01 2e + 30b8: 03 87 07 00 lb a4, 0(a5) + 30bc: 00 38 + 30be: 37 00 00 12 lui zero, 73728 + 30c2: 20 06 + 30c4: 00 00 + 30c6: 01 2e + 30c8: 03 87 07 00 lb a4, 0(a5) + 30cc: 00 4b + 30ce: 37 00 00 16 lui zero, 90112 + 30d2: 6d 03 + 30d4: 00 00 + 30d6: 01 2e + 30d8: 03 68 00 00 + 30dc: 00 16 + 30de: 31 04 + 30e0: 00 00 + 30e2: 01 2e + 30e4: 03 68 00 00 + 30e8: 00 12 + 30ea: 57 03 00 00 + 30ee: 01 2e + 30f0: 03 68 00 00 + 30f4: 00 5e + 30f6: 37 00 00 12 lui zero, 73728 + 30fa: 2c 04 + 30fc: 00 00 + 30fe: 01 2e + 3100: 03 68 00 00 + 3104: 00 71 + 3106: 37 00 00 00 lui zero, 0 + 310a: 15 78 + 310c: 04 00 + 310e: 00 37 + 3110: 05 00 + 3112: 00 12 + 3114: 11 06 + 3116: 00 00 + 3118: 01 2e + 311a: 03 87 07 00 lb a4, 0(a5) + 311e: 00 84 + 3120: 37 00 00 12 lui zero, 73728 + 3124: 16 06 + 3126: 00 00 + 3128: 01 2e + 312a: 03 87 07 00 lb a4, 0(a5) + 312e: 00 97 + 3130: 37 00 00 12 lui zero, 73728 + 3134: 1b 06 00 00 + 3138: 01 2e + 313a: 03 87 07 00 lb a4, 0(a5) + 313e: 00 c5 + 3140: 37 00 00 12 lui zero, 73728 + 3144: 20 06 + 3146: 00 00 + 3148: 01 2e + 314a: 03 87 07 00 lb a4, 0(a5) + 314e: 00 d8 + 3150: 37 00 00 16 lui zero, 90112 + 3154: 6d 03 + 3156: 00 00 + 3158: 01 2e + 315a: 03 68 00 00 + 315e: 00 16 + 3160: 31 04 + 3162: 00 00 + 3164: 01 2e + 3166: 03 68 00 00 + 316a: 00 12 + 316c: 57 03 00 00 + 3170: 01 2e + 3172: 03 68 00 00 + 3176: 00 f6 + 3178: 37 00 00 12 lui zero, 73728 + 317c: 2c 04 + 317e: 00 00 + 3180: 01 2e + 3182: 03 68 00 00 + 3186: 00 09 + 3188: 38 00 + 318a: 00 00 + 318c: 15 a8 + 318e: 04 00 + 3190: 00 61 + 3192: 05 00 + 3194: 00 12 + 3196: b2 0a + 3198: 00 00 + 319a: 01 2e + 319c: 03 87 07 00 lb a4, 0(a5) + 31a0: 00 1c + 31a2: 38 00 + 31a4: 00 12 + 31a6: 67 0b 00 00 jalr s6, zero + 31aa: 01 2e + 31ac: 03 87 07 00 lb a4, 0(a5) + 31b0: 00 3a + 31b2: 38 00 + 31b4: 00 00 + 31b6: 17 d0 04 00 auipc zero, 77 + 31ba: 00 12 + 31bc: b2 0a + 31be: 00 00 + 31c0: 01 2e + 31c2: 03 87 07 00 lb a4, 0(a5) + 31c6: 00 11 + 31c8: 39 00 + 31ca: 00 12 + 31cc: 67 0b 00 00 jalr s6, zero + 31d0: 01 2e + 31d2: 03 87 07 00 lb a4, 0(a5) + 31d6: 00 24 + 31d8: 39 00 + 31da: 00 00 + 31dc: 00 17 + 31de: f8 04 + 31e0: 00 00 + 31e2: 16 9c + 31e4: 0a 00 + 31e6: 00 01 + 31e8: 2e 03 + 31ea: 2c 00 + 31ec: 00 00 + 31ee: 17 20 05 00 auipc zero, 82 + 31f2: 00 12 + 31f4: 13 0b 00 00 mv s6, zero + 31f8: 01 2e + 31fa: 03 80 07 00 lb zero, 0(a5) + 31fe: 00 70 + 3200: 39 00 + 3202: 00 12 + 3204: c5 0a + 3206: 00 00 + 3208: 01 2e + 320a: 03 80 07 00 lb zero, 0(a5) + 320e: 00 90 + 3210: 39 00 + 3212: 00 12 + 3214: ec 0a + 3216: 00 00 + 3218: 01 2e + 321a: 03 80 07 00 lb zero, 0(a5) + 321e: 00 b0 + 3220: 39 00 + 3222: 00 12 + 3224: da 0a + 3226: 00 00 + 3228: 01 2e + 322a: 03 80 07 00 lb zero, 0(a5) + 322e: 00 d0 + 3230: 39 00 + 3232: 00 12 + 3234: 01 0b + 3236: 00 00 + 3238: 01 2e + 323a: 03 87 07 00 lb a4, 0(a5) + 323e: 00 e4 + 3240: 39 00 + 3242: 00 00 + 3244: 00 00 + 3246: 18 88 + 3248: 15 01 + 324a: 80 04 + 324c: 00 00 + 324e: 00 0b + 3250: 06 00 + 3252: 00 14 + 3254: 5f 5f 78 00 + 3258: 01 2f + 325a: 03 87 07 00 lb a4, 0(a5) + 325e: 00 00 + 3260: 19 1d + 3262: 06 00 + 3264: 00 14 + 3266: 5f 5f 78 00 + 326a: 01 2f + 326c: 03 87 07 00 lb a4, 0(a5) + 3270: 00 00 + 3272: 15 50 + 3274: 05 00 + 3276: 00 37 + 3278: 06 00 + 327a: 00 13 + 327c: 5f 5f 78 00 + 3280: 01 2f + 3282: 03 87 07 00 lb a4, 0(a5) + 3286: 00 1b + 3288: 3a 00 + 328a: 00 00 + 328c: 15 68 + 328e: 05 00 + 3290: 00 69 + 3292: 07 00 00 12 + 3296: 59 09 + 3298: 00 00 + 329a: 01 2f + 329c: 03 2c 00 00 lw s8, 0(zero) + 32a0: 00 2e + 32a2: 3a 00 + 32a4: 00 18 + 32a6: 70 16 + 32a8: 01 80 + 32aa: 68 00 + 32ac: 00 00 + 32ae: ec 06 + 32b0: 00 00 + 32b2: 16 74 + 32b4: 09 00 + 32b6: 00 01 + 32b8: 2f 03 80 07 + 32bc: 00 00 + 32be: 16 42 + 32c0: 09 00 + 32c2: 00 01 + 32c4: 2f 03 80 07 + 32c8: 00 00 + 32ca: 12 76 + 32cc: 0a 00 + 32ce: 00 01 + 32d0: 2f 03 80 07 + 32d4: 00 00 + 32d6: 74 3a + 32d8: 00 00 + 32da: 12 ed + 32dc: 07 00 00 01 + 32e0: 2f 03 87 07 + 32e4: 00 00 + 32e6: 88 3a + 32e8: 00 00 + 32ea: 12 05 + 32ec: 08 00 + 32ee: 00 01 + 32f0: 2f 03 87 07 + 32f4: 00 00 + 32f6: a6 3a + 32f8: 00 00 + 32fa: 18 a4 + 32fc: 16 01 + 32fe: 80 04 + 3300: 00 00 + 3302: 00 c3 + 3304: 06 00 + 3306: 00 13 + 3308: 5f 5f 78 00 + 330c: 01 2f + 330e: 03 87 07 00 lb a4, 0(a5) + 3312: 00 da + 3314: 3a 00 + 3316: 00 00 + 3318: 19 d5 + 331a: 06 00 + 331c: 00 14 + 331e: 5f 5f 78 00 + 3322: 01 2f + 3324: 03 87 07 00 lb a4, 0(a5) + 3328: 00 00 + 332a: 17 80 05 00 auipc zero, 88 + 332e: 00 13 + 3330: 5f 5f 78 00 + 3334: 01 2f + 3336: 03 87 07 00 lb a4, 0(a5) + 333a: 00 ef + 333c: 3a 00 + 333e: 00 00 + 3340: 00 18 + 3342: 3c 17 + 3344: 01 80 + 3346: 04 00 + 3348: 00 00 + 334a: 06 07 + 334c: 00 00 + 334e: 14 5f + 3350: 5f 78 00 01 + 3354: 2f 03 87 07 + 3358: 00 00 + 335a: 00 19 + 335c: 18 07 + 335e: 00 00 + 3360: 14 5f + 3362: 5f 78 00 01 + 3366: 2f 03 87 07 + 336a: 00 00 + 336c: 00 15 + 336e: 98 05 + 3370: 00 00 + 3372: 32 07 + 3374: 00 00 + 3376: 13 5f 5f 78 + 337a: 00 01 + 337c: 2f 03 87 07 + 3380: 00 00 + 3382: 04 3b + 3384: 00 00 + 3386: 00 19 + 3388: 44 07 + 338a: 00 00 + 338c: 14 5f + 338e: 5f 78 00 01 + 3392: 2f 03 87 07 + 3396: 00 00 + 3398: 00 15 + 339a: b0 05 + 339c: 00 00 + 339e: 5a 07 + 33a0: 00 00 + 33a2: 14 5f + 33a4: 5f 78 00 01 + 33a8: 2f 03 87 07 + 33ac: 00 00 + 33ae: 00 1a + 33b0: 14 5f + 33b2: 5f 78 00 01 + 33b6: 2f 03 87 07 + 33ba: 00 00 + 33bc: 00 00 + 33be: 1b 34 13 01 + 33c2: 80 28 + 33c4: 00 00 + 33c6: 00 16 + 33c8: 6c 08 + 33ca: 00 00 + 33cc: 01 2f + 33ce: 03 f3 00 00 + 33d2: 00 00 + 33d4: 00 02 + 33d6: 04 05 + 33d8: f6 03 + 33da: 00 00 + 33dc: 02 04 + 33de: 07 cf 02 00 + 33e2: 00 1c + 33e4: 87 07 00 00 + 33e8: 07 5a 00 00 + 33ec: 00 03 + 33ee: 00 00 + 33f0: ac 02 + 33f2: 00 00 + 33f4: 04 00 + 33f6: b0 08 + 33f8: 00 00 + 33fa: 04 01 + 33fc: c8 09 + 33fe: 00 00 + 3400: 0c 0d + 3402: 0c 00 + 3404: 00 d5 + 3406: 01 00 + 3408: 00 58 + 340a: 18 01 + 340c: 80 2c + 340e: 01 00 + 3410: 00 8e + 3412: 35 00 + 3414: 00 02 + 3416: 4d 0c + 3418: 00 00 + 341a: 02 50 + 341c: 0d 31 + 341e: 00 00 + 3420: 00 03 + 3422: 04 05 + 3424: 69 6e + 3426: 74 00 + 3428: 04 01 + 342a: 06 ad + 342c: 06 00 + 342e: 00 04 + 3430: 08 05 + 3432: f1 03 + 3434: 00 00 + 3436: 05 b7 + 3438: 07 00 00 03 + 343c: 4a 01 + 343e: 16 58 + 3440: 00 00 + 3442: 00 06 + 3444: 46 00 + 3446: 00 00 + 3448: 04 01 + 344a: 08 ab + 344c: 06 00 + 344e: 00 04 + 3450: 04 07 + 3452: d4 02 + 3454: 00 00 + 3456: 04 08 + 3458: 07 ca 02 00 + 345c: 00 04 + 345e: 02 07 + 3460: ea 02 + 3462: 00 00 + 3464: 07 53 00 00 + 3468: 00 84 + 346a: 00 00 + 346c: 00 08 + 346e: 5f 00 00 00 + 3472: ff 00 06 74 + 3476: 00 00 + 3478: 00 09 + 347a: fd 02 + 347c: 00 00 + 347e: 05 3c + 3480: 16 84 + 3482: 00 00 + 3484: 00 02 + 3486: 46 0c + 3488: 00 00 + 348a: 04 48 + 348c: 0f a1 00 00 + 3490: 00 04 + 3492: 10 04 + 3494: c0 00 + 3496: 00 00 + 3498: 0a 10 + 349a: 04 4f + 349c: 03 12 01 00 lh tp, 0(sp) + 34a0: 00 0b + 34a2: 60 08 + 34a4: 00 00 + 34a6: 04 59 + 34a8: 13 12 01 00 slli tp, sp, 0 + 34ac: 00 04 + 34ae: 20 00 + 34b0: 00 0b + 34b2: 66 08 + 34b4: 00 00 + 34b6: 04 5a + 34b8: 13 12 01 00 slli tp, sp, 0 + 34bc: 00 04 + 34be: 20 00 + 34c0: 04 0b + 34c2: 3a 0c + 34c4: 00 00 + 34c6: 04 5b + 34c8: 13 12 01 00 slli tp, sp, 0 + 34cc: 00 04 + 34ce: 20 00 + 34d0: 08 0b + 34d2: 40 0c + 34d4: 00 00 + 34d6: 04 5c + 34d8: 13 12 01 00 slli tp, sp, 0 + 34dc: 00 04 + 34de: 10 10 + 34e0: 0c 0c + 34e2: 65 78 + 34e4: 70 00 + 34e6: 04 5d + 34e8: 0e 5f + 34ea: 00 00 + 34ec: 00 04 + 34ee: 0f 01 0c 0b + 34f2: 41 02 + 34f4: 00 00 + 34f6: 04 5e + 34f8: 0e 5f + 34fa: 00 00 + 34fc: 00 04 + 34fe: 01 00 + 3500: 0c 00 + 3502: 04 04 + 3504: 07 cf 02 00 + 3508: 00 0d + 350a: 74 0c + 350c: 00 00 + 350e: 10 04 + 3510: 4c 07 + 3512: 3f 01 00 00 + 3516: 0e 66 + 3518: 6c 74 + 351a: 00 04 + 351c: 4e 0a + 351e: 95 00 + 3520: 00 00 + 3522: 0f 8d 0a 00 + 3526: 00 04 + 3528: 60 05 + 352a: a8 00 + 352c: 00 00 + 352e: 00 10 + 3530: 6c 0c + 3532: 00 00 + 3534: 01 23 + 3536: 01 25 + 3538: 00 00 + 353a: 00 58 + 353c: 18 01 + 353e: 80 2c + 3540: 01 00 + 3542: 00 01 + 3544: 9c 9c + 3546: 02 00 + 3548: 00 11 + 354a: 61 00 + 354c: 01 23 + 354e: 11 95 + 3550: 00 00 + 3552: 00 11 + 3554: 62 00 + 3556: 01 23 + 3558: 1b 95 00 00 + 355c: 00 12 + 355e: f2 08 + 3560: 00 00 + 3562: 01 25 + 3564: 03 31 00 00 + 3568: 00 17 + 356a: 3b 00 00 13 + 356e: 92 0a + 3570: 00 00 + 3572: 01 25 + 3574: 03 31 00 00 + 3578: 00 14 + 357a: 41 5f + 357c: 63 00 01 26 beqz sp, 608 + 3580: 03 9c 02 00 lh s8, 0(t0) + 3584: 00 15 + 3586: 41 5f + 3588: 73 00 01 26 + 358c: 03 9c 02 00 lh s8, 0(t0) + 3590: 00 06 + 3592: 81 00 + 3594: 08 ff + 3596: 1a 9f + 3598: 15 41 + 359a: 5f 65 00 01 + 359e: 26 03 + 35a0: 9c 02 + 35a2: 00 00 + 35a4: 01 5c + 35a6: 16 41 + 35a8: 5f 66 00 01 + 35ac: 26 03 + 35ae: a3 02 00 00 sb zero, 5(zero) + 35b2: 37 3b 00 00 lui s6, 3 + 35b6: 14 42 + 35b8: 5f 63 00 01 + 35bc: 27 03 9c 02 + 35c0: 00 00 + 35c2: 15 42 + 35c4: 5f 73 00 01 + 35c8: 27 03 9c 02 + 35cc: 00 00 + 35ce: 06 76 + 35d0: 00 08 + 35d2: ff 1a 9f 15 + 35d6: 42 5f + 35d8: 65 00 + 35da: 01 27 + 35dc: 03 9c 02 00 lh s8, 0(t0) + 35e0: 00 01 + 35e2: 5d 16 + 35e4: 42 5f + 35e6: 66 00 + 35e8: 01 27 + 35ea: 03 a3 02 00 lw t1, 0(t0) + 35ee: 00 aa + 35f0: 3b 00 00 16 + 35f4: 72 00 + 35f6: 01 28 + 35f8: 0b 25 00 00 + 35fc: 00 30 + 35fe: 3c 00 + 3600: 00 17 + 3602: c8 05 + 3604: 00 00 + 3606: 2a 02 + 3608: 00 00 + 360a: 18 f8 + 360c: 0b 00 00 01 + 3610: 2b 03 19 01 + 3614: 00 00 + 3616: 02 91 + 3618: 70 00 + 361a: 17 e0 05 00 auipc zero, 94 + 361e: 00 43 + 3620: 02 00 + 3622: 00 18 + 3624: f8 0b + 3626: 00 00 + 3628: 01 2c + 362a: 03 19 01 00 lh s2, 0(sp) + 362e: 00 02 + 3630: 91 70 + 3632: 00 19 + 3634: 55 02 + 3636: 00 00 + 3638: 13 5b 0c 00 srli s6, s8, 0 + 363c: 00 01 + 363e: 2d 03 + 3640: 31 00 + 3642: 00 00 + 3644: 00 19 + 3646: 67 02 00 00 jalr tp, zero + 364a: 13 5b 0c 00 srli s6, s8, 0 + 364e: 00 01 + 3650: 2d 03 + 3652: 31 00 + 3654: 00 00 + 3656: 00 1a + 3658: 28 19 + 365a: 01 80 + 365c: 28 00 + 365e: 00 00 + 3660: 85 02 + 3662: 00 00 + 3664: 12 5b + 3666: 0c 00 + 3668: 00 01 + 366a: 2d 03 + 366c: 31 00 + 366e: 00 00 + 3670: 44 3c + 3672: 00 00 + 3674: 00 1b + 3676: f8 05 + 3678: 00 00 + 367a: 12 5b + 367c: 0c 00 + 367e: 00 01 + 3680: 2d 03 + 3682: 31 00 + 3684: 00 00 + 3686: 58 3c + 3688: 00 00 + 368a: 00 00 + 368c: 04 04 + 368e: 05 f6 + 3690: 03 00 00 1c lb zero, 448(zero) + 3694: 12 01 + 3696: 00 00 + 3698: 08 5f + 369a: 00 00 + 369c: 00 03 + 369e: 00 00 + 36a0: 94 02 + 36a2: 00 00 + 36a4: 04 00 + 36a6: 48 0a + 36a8: 00 00 + 36aa: 04 01 + 36ac: c8 09 + 36ae: 00 00 + 36b0: 0c 88 + 36b2: 0c 00 + 36b4: 00 d5 + 36b6: 01 00 + 36b8: 00 84 + 36ba: 19 01 + 36bc: 80 4c + 36be: 01 00 + 36c0: 00 ba + 36c2: 38 00 + 36c4: 00 02 + 36c6: 4d 0c + 36c8: 00 00 + 36ca: 02 50 + 36cc: 0d 31 + 36ce: 00 00 + 36d0: 00 03 + 36d2: 04 05 + 36d4: 69 6e + 36d6: 74 00 + 36d8: 04 01 + 36da: 06 ad + 36dc: 06 00 + 36de: 00 04 + 36e0: 08 05 + 36e2: f1 03 + 36e4: 00 00 + 36e6: 05 b7 + 36e8: 07 00 00 03 + 36ec: 4a 01 + 36ee: 16 58 + 36f0: 00 00 + 36f2: 00 06 + 36f4: 46 00 + 36f6: 00 00 + 36f8: 04 01 + 36fa: 08 ab + 36fc: 06 00 + 36fe: 00 04 + 3700: 04 07 + 3702: d4 02 + 3704: 00 00 + 3706: 04 08 + 3708: 07 ca 02 00 + 370c: 00 04 + 370e: 02 07 + 3710: ea 02 + 3712: 00 00 + 3714: 07 53 00 00 + 3718: 00 84 + 371a: 00 00 + 371c: 00 08 + 371e: 5f 00 00 00 + 3722: ff 00 06 74 + 3726: 00 00 + 3728: 00 09 + 372a: fd 02 + 372c: 00 00 + 372e: 05 3c + 3730: 16 84 + 3732: 00 00 + 3734: 00 02 + 3736: 46 0c + 3738: 00 00 + 373a: 04 48 + 373c: 0f a1 00 00 + 3740: 00 04 + 3742: 10 04 + 3744: c0 00 + 3746: 00 00 + 3748: 0a 10 + 374a: 04 4f + 374c: 03 12 01 00 lh tp, 0(sp) + 3750: 00 0b + 3752: 60 08 + 3754: 00 00 + 3756: 04 59 + 3758: 13 12 01 00 slli tp, sp, 0 + 375c: 00 04 + 375e: 20 00 + 3760: 00 0b + 3762: 66 08 + 3764: 00 00 + 3766: 04 5a + 3768: 13 12 01 00 slli tp, sp, 0 + 376c: 00 04 + 376e: 20 00 + 3770: 04 0b + 3772: 3a 0c + 3774: 00 00 + 3776: 04 5b + 3778: 13 12 01 00 slli tp, sp, 0 + 377c: 00 04 + 377e: 20 00 + 3780: 08 0b + 3782: 40 0c + 3784: 00 00 + 3786: 04 5c + 3788: 13 12 01 00 slli tp, sp, 0 + 378c: 00 04 + 378e: 10 10 + 3790: 0c 0c + 3792: 65 78 + 3794: 70 00 + 3796: 04 5d + 3798: 0e 5f + 379a: 00 00 + 379c: 00 04 + 379e: 0f 01 0c 0b + 37a2: 41 02 + 37a4: 00 00 + 37a6: 04 5e + 37a8: 0e 5f + 37aa: 00 00 + 37ac: 00 04 + 37ae: 01 00 + 37b0: 0c 00 + 37b2: 04 04 + 37b4: 07 cf 02 00 + 37b8: 00 0d + 37ba: 74 0c + 37bc: 00 00 + 37be: 10 04 + 37c0: 4c 07 + 37c2: 3f 01 00 00 + 37c6: 0e 66 + 37c8: 6c 74 + 37ca: 00 04 + 37cc: 4e 0a + 37ce: 95 00 + 37d0: 00 00 + 37d2: 0f 8d 0a 00 + 37d6: 00 04 + 37d8: 60 05 + 37da: a8 00 + 37dc: 00 00 + 37de: 00 10 + 37e0: 80 0c + 37e2: 00 00 + 37e4: 01 23 + 37e6: 01 25 + 37e8: 00 00 + 37ea: 00 84 + 37ec: 19 01 + 37ee: 80 4c + 37f0: 01 00 + 37f2: 00 01 + 37f4: 9c 84 + 37f6: 02 00 + 37f8: 00 11 + 37fa: 61 00 + 37fc: 01 23 + 37fe: 11 95 + 3800: 00 00 + 3802: 00 11 + 3804: 62 00 + 3806: 01 23 + 3808: 1b 95 00 00 + 380c: 00 12 + 380e: f2 08 + 3810: 00 00 + 3812: 01 25 + 3814: 03 31 00 00 + 3818: 00 6c + 381a: 3c 00 + 381c: 00 13 + 381e: 92 0a + 3820: 00 00 + 3822: 01 25 + 3824: 03 31 00 00 + 3828: 00 14 + 382a: 41 5f + 382c: 63 00 01 26 beqz sp, 608 + 3830: 03 84 02 00 lb s0, 0(t0) + 3834: 00 15 + 3836: 41 5f + 3838: 73 00 01 26 + 383c: 03 84 02 00 lb s0, 0(t0) + 3840: 00 98 + 3842: 3c 00 + 3844: 00 16 + 3846: 41 5f + 3848: 65 00 + 384a: 01 26 + 384c: 03 84 02 00 lb s0, 0(t0) + 3850: 00 01 + 3852: 5c 15 + 3854: 41 5f + 3856: 66 00 + 3858: 01 26 + 385a: 03 8b 02 00 lb s6, 0(t0) + 385e: 00 d7 + 3860: 3c 00 + 3862: 00 14 + 3864: 42 5f + 3866: 63 00 01 27 beq sp, a6, 608 + 386a: 03 84 02 00 lb s0, 0(t0) + 386e: 00 16 + 3870: 42 5f + 3872: 73 00 01 27 + 3876: 03 84 02 00 lb s0, 0(t0) + 387a: 00 01 + 387c: 5d 16 + 387e: 42 5f + 3880: 65 00 + 3882: 01 27 + 3884: 03 84 02 00 lb s0, 0(t0) + 3888: 00 01 + 388a: 5e 15 + 388c: 42 5f + 388e: 66 00 + 3890: 01 27 + 3892: 03 8b 02 00 lb s6, 0(t0) + 3896: 00 0a + 3898: 3d 00 + 389a: 00 16 + 389c: 72 00 + 389e: 01 28 + 38a0: 0b 25 00 00 + 38a4: 00 01 + 38a6: 5a 17 + 38a8: 10 06 + 38aa: 00 00 + 38ac: 20 02 + 38ae: 00 00 + 38b0: 18 f8 + 38b2: 0b 00 00 01 + 38b6: 2b 03 19 01 + 38ba: 00 00 + 38bc: 02 91 + 38be: 70 00 + 38c0: 17 28 06 00 auipc a6, 98 + 38c4: 00 39 + 38c6: 02 00 + 38c8: 00 18 + 38ca: f8 0b + 38cc: 00 00 + 38ce: 01 2c + 38d0: 03 19 01 00 lh s2, 0(sp) + 38d4: 00 02 + 38d6: 91 70 + 38d8: 00 19 + 38da: 4b 02 00 00 fnmsub.s ft4, ft0, ft0, ft0, rne + 38de: 13 5b 0c 00 srli s6, s8, 0 + 38e2: 00 01 + 38e4: 2d 03 + 38e6: 31 00 + 38e8: 00 00 + 38ea: 00 19 + 38ec: 5d 02 + 38ee: 00 00 + 38f0: 13 5b 0c 00 srli s6, s8, 0 + 38f4: 00 01 + 38f6: 2d 03 + 38f8: 31 00 + 38fa: 00 00 + 38fc: 00 1a + 38fe: 40 06 + 3900: 00 00 + 3902: 12 b5 + 3904: 0c 00 + 3906: 00 01 + 3908: 2d 03 + 390a: 31 00 + 390c: 00 00 + 390e: 3d 3d + 3910: 00 00 + 3912: 12 c7 + 3914: 0c 00 + 3916: 00 01 + 3918: 2d 03 + 391a: 31 00 + 391c: 00 00 + 391e: 68 3d + 3920: 00 00 + 3922: 00 00 + 3924: 04 04 + 3926: 05 f6 + 3928: 03 00 00 1b lb zero, 432(zero) + 392c: 12 01 + 392e: 00 00 + 3930: 08 5f + 3932: 00 00 + 3934: 00 03 + 3936: 00 00 + 3938: 94 02 + 393a: 00 00 + 393c: 04 00 + 393e: d5 0b + 3940: 00 00 + 3942: 04 01 + 3944: c8 09 + 3946: 00 00 + 3948: 0c e1 + 394a: 0c 00 + 394c: 00 d5 + 394e: 01 00 + 3950: 00 d0 + 3952: 1a 01 + 3954: 80 4c + 3956: 01 00 + 3958: 00 52 + 395a: 3c 00 + 395c: 00 02 + 395e: 4d 0c + 3960: 00 00 + 3962: 02 50 + 3964: 0d 31 + 3966: 00 00 + 3968: 00 03 + 396a: 04 05 + 396c: 69 6e + 396e: 74 00 + 3970: 04 01 + 3972: 06 ad + 3974: 06 00 + 3976: 00 04 + 3978: 08 05 + 397a: f1 03 + 397c: 00 00 + 397e: 05 b7 + 3980: 07 00 00 03 + 3984: 4a 01 + 3986: 16 58 + 3988: 00 00 + 398a: 00 06 + 398c: 46 00 + 398e: 00 00 + 3990: 04 01 + 3992: 08 ab + 3994: 06 00 + 3996: 00 04 + 3998: 04 07 + 399a: d4 02 + 399c: 00 00 + 399e: 04 08 + 39a0: 07 ca 02 00 + 39a4: 00 04 + 39a6: 02 07 + 39a8: ea 02 + 39aa: 00 00 + 39ac: 07 53 00 00 + 39b0: 00 84 + 39b2: 00 00 + 39b4: 00 08 + 39b6: 5f 00 00 00 + 39ba: ff 00 06 74 + 39be: 00 00 + 39c0: 00 09 + 39c2: fd 02 + 39c4: 00 00 + 39c6: 05 3c + 39c8: 16 84 + 39ca: 00 00 + 39cc: 00 02 + 39ce: 46 0c + 39d0: 00 00 + 39d2: 04 48 + 39d4: 0f a1 00 00 + 39d8: 00 04 + 39da: 10 04 + 39dc: c0 00 + 39de: 00 00 + 39e0: 0a 10 + 39e2: 04 4f + 39e4: 03 12 01 00 lh tp, 0(sp) + 39e8: 00 0b + 39ea: 60 08 + 39ec: 00 00 + 39ee: 04 59 + 39f0: 13 12 01 00 slli tp, sp, 0 + 39f4: 00 04 + 39f6: 20 00 + 39f8: 00 0b + 39fa: 66 08 + 39fc: 00 00 + 39fe: 04 5a + 3a00: 13 12 01 00 slli tp, sp, 0 + 3a04: 00 04 + 3a06: 20 00 + 3a08: 04 0b + 3a0a: 3a 0c + 3a0c: 00 00 + 3a0e: 04 5b + 3a10: 13 12 01 00 slli tp, sp, 0 + 3a14: 00 04 + 3a16: 20 00 + 3a18: 08 0b + 3a1a: 40 0c + 3a1c: 00 00 + 3a1e: 04 5c + 3a20: 13 12 01 00 slli tp, sp, 0 + 3a24: 00 04 + 3a26: 10 10 + 3a28: 0c 0c + 3a2a: 65 78 + 3a2c: 70 00 + 3a2e: 04 5d + 3a30: 0e 5f + 3a32: 00 00 + 3a34: 00 04 + 3a36: 0f 01 0c 0b + 3a3a: 41 02 + 3a3c: 00 00 + 3a3e: 04 5e + 3a40: 0e 5f + 3a42: 00 00 + 3a44: 00 04 + 3a46: 01 00 + 3a48: 0c 00 + 3a4a: 04 04 + 3a4c: 07 cf 02 00 + 3a50: 00 0d + 3a52: 74 0c + 3a54: 00 00 + 3a56: 10 04 + 3a58: 4c 07 + 3a5a: 3f 01 00 00 + 3a5e: 0e 66 + 3a60: 6c 74 + 3a62: 00 04 + 3a64: 4e 0a + 3a66: 95 00 + 3a68: 00 00 + 3a6a: 0f 8d 0a 00 + 3a6e: 00 04 + 3a70: 60 05 + 3a72: a8 00 + 3a74: 00 00 + 3a76: 00 10 + 3a78: d9 0c + 3a7a: 00 00 + 3a7c: 01 23 + 3a7e: 01 25 + 3a80: 00 00 + 3a82: 00 d0 + 3a84: 1a 01 + 3a86: 80 4c + 3a88: 01 00 + 3a8a: 00 01 + 3a8c: 9c 84 + 3a8e: 02 00 + 3a90: 00 11 + 3a92: 61 00 + 3a94: 01 23 + 3a96: 11 95 + 3a98: 00 00 + 3a9a: 00 11 + 3a9c: 62 00 + 3a9e: 01 23 + 3aa0: 1b 95 00 00 + 3aa4: 00 12 + 3aa6: f2 08 + 3aa8: 00 00 + 3aaa: 01 25 + 3aac: 03 31 00 00 + 3ab0: 00 ac + 3ab2: 3d 00 + 3ab4: 00 13 + 3ab6: 92 0a + 3ab8: 00 00 + 3aba: 01 25 + 3abc: 03 31 00 00 + 3ac0: 00 14 + 3ac2: 41 5f + 3ac4: 63 00 01 26 beqz sp, 608 + 3ac8: 03 84 02 00 lb s0, 0(t0) + 3acc: 00 15 + 3ace: 41 5f + 3ad0: 73 00 01 26 + 3ad4: 03 84 02 00 lb s0, 0(t0) + 3ad8: 00 d8 + 3ada: 3d 00 + 3adc: 00 16 + 3ade: 41 5f + 3ae0: 65 00 + 3ae2: 01 26 + 3ae4: 03 84 02 00 lb s0, 0(t0) + 3ae8: 00 01 + 3aea: 5c 15 + 3aec: 41 5f + 3aee: 66 00 + 3af0: 01 26 + 3af2: 03 8b 02 00 lb s6, 0(t0) + 3af6: 00 17 + 3af8: 3e 00 + 3afa: 00 14 + 3afc: 42 5f + 3afe: 63 00 01 27 beq sp, a6, 608 + 3b02: 03 84 02 00 lb s0, 0(t0) + 3b06: 00 16 + 3b08: 42 5f + 3b0a: 73 00 01 27 + 3b0e: 03 84 02 00 lb s0, 0(t0) + 3b12: 00 01 + 3b14: 5d 16 + 3b16: 42 5f + 3b18: 65 00 + 3b1a: 01 27 + 3b1c: 03 84 02 00 lb s0, 0(t0) + 3b20: 00 01 + 3b22: 5e 15 + 3b24: 42 5f + 3b26: 66 00 + 3b28: 01 27 + 3b2a: 03 8b 02 00 lb s6, 0(t0) + 3b2e: 00 4a + 3b30: 3e 00 + 3b32: 00 16 + 3b34: 72 00 + 3b36: 01 28 + 3b38: 0b 25 00 00 + 3b3c: 00 01 + 3b3e: 5a 17 + 3b40: 60 06 + 3b42: 00 00 + 3b44: 20 02 + 3b46: 00 00 + 3b48: 18 f8 + 3b4a: 0b 00 00 01 + 3b4e: 2b 03 19 01 + 3b52: 00 00 + 3b54: 02 91 + 3b56: 70 00 + 3b58: 17 78 06 00 auipc a6, 103 + 3b5c: 00 39 + 3b5e: 02 00 + 3b60: 00 18 + 3b62: f8 0b + 3b64: 00 00 + 3b66: 01 2c + 3b68: 03 19 01 00 lh s2, 0(sp) + 3b6c: 00 02 + 3b6e: 91 70 + 3b70: 00 19 + 3b72: 4b 02 00 00 fnmsub.s ft4, ft0, ft0, ft0, rne + 3b76: 13 5b 0c 00 srli s6, s8, 0 + 3b7a: 00 01 + 3b7c: 2d 03 + 3b7e: 31 00 + 3b80: 00 00 + 3b82: 00 19 + 3b84: 5d 02 + 3b86: 00 00 + 3b88: 13 5b 0c 00 srli s6, s8, 0 + 3b8c: 00 01 + 3b8e: 2d 03 + 3b90: 31 00 + 3b92: 00 00 + 3b94: 00 1a + 3b96: 90 06 + 3b98: 00 00 + 3b9a: 12 b5 + 3b9c: 0c 00 + 3b9e: 00 01 + 3ba0: 2d 03 + 3ba2: 31 00 + 3ba4: 00 00 + 3ba6: 7d 3e + 3ba8: 00 00 + 3baa: 12 c7 + 3bac: 0c 00 + 3bae: 00 01 + 3bb0: 2d 03 + 3bb2: 31 00 + 3bb4: 00 00 + 3bb6: a8 3e + 3bb8: 00 00 + 3bba: 00 00 + 3bbc: 04 04 + 3bbe: 05 f6 + 3bc0: 03 00 00 1b lb zero, 432(zero) + 3bc4: 12 01 + 3bc6: 00 00 + 3bc8: 08 5f + 3bca: 00 00 + 3bcc: 00 03 + 3bce: 00 00 + 3bd0: 13 13 00 00 slli t1, zero, 0 + 3bd4: 04 00 + 3bd6: 62 0d + 3bd8: 00 00 + 3bda: 04 01 + 3bdc: c8 09 + 3bde: 00 00 + 3be0: 0c 08 + 3be2: 0f 00 00 d5 + 3be6: 01 00 + 3be8: 00 1c + 3bea: 1c 01 + 3bec: 80 d8 + 3bee: 12 00 + 3bf0: 00 ea + 3bf2: 3f 00 00 02 + 3bf6: 04 05 + 3bf8: 69 6e + 3bfa: 74 00 + 3bfc: 03 01 06 ad lb sp, -1328(a2) + 3c00: 06 00 + 3c02: 00 03 + 3c04: 08 05 + 3c06: f1 03 + 3c08: 00 00 + 3c0a: 04 b7 + 3c0c: 07 00 00 02 + 3c10: 4a 01 + 3c12: 16 4c + 3c14: 00 00 + 3c16: 00 05 + 3c18: 3a 00 + 3c1a: 00 00 + 3c1c: 03 01 08 ab lb sp, -1360(a6) + 3c20: 06 00 + 3c22: 00 03 + 3c24: 04 07 + 3c26: d4 02 + 3c28: 00 00 + 3c2a: 03 08 07 ca lb a6, -864(a4) + 3c2e: 02 00 + 3c30: 00 04 + 3c32: 3f 08 00 00 + 3c36: 02 4e + 3c38: 01 16 + 3c3a: 6e 00 + 3c3c: 00 00 + 3c3e: 03 02 07 ea lb tp, -352(a4) + 3c42: 02 00 + 3c44: 00 06 + 3c46: 47 00 00 00 fmsub.s ft0, ft0, ft0, ft0, rne + 3c4a: 85 00 + 3c4c: 00 00 + 3c4e: 07 53 00 00 + 3c52: 00 ff + 3c54: 00 05 + 3c56: 75 00 + 3c58: 00 00 + 3c5a: 08 fd + 3c5c: 02 00 + 3c5e: 00 04 + 3c60: 3c 16 + 3c62: 85 00 + 3c64: 00 00 + 3c66: 09 46 + 3c68: 0c 00 + 3c6a: 00 03 + 3c6c: 48 0f + 3c6e: a2 00 + 3c70: 00 00 + 3c72: 03 10 04 c0 lh zero, -1024(s0) + 3c76: 00 00 + 3c78: 00 0a + 3c7a: 10 03 + 3c7c: 4f 03 13 01 fnmadd.s ft6, ft6, fa7, ft0, rne + 3c80: 00 00 + 3c82: 0b 60 08 00 + 3c86: 00 03 + 3c88: 59 13 + 3c8a: 13 01 00 00 mv sp, zero + 3c8e: 04 20 + 3c90: 00 00 + 3c92: 0b 66 08 00 + 3c96: 00 03 + 3c98: 5a 13 + 3c9a: 13 01 00 00 mv sp, zero + 3c9e: 04 20 + 3ca0: 00 04 + 3ca2: 0b 3a 0c 00 + 3ca6: 00 03 + 3ca8: 5b 13 13 01 + 3cac: 00 00 + 3cae: 04 20 + 3cb0: 00 08 + 3cb2: 0b 40 0c 00 + 3cb6: 00 03 + 3cb8: 5c 13 + 3cba: 13 01 00 00 mv sp, zero + 3cbe: 04 10 + 3cc0: 10 0c + 3cc2: 0c 65 + 3cc4: 78 70 + 3cc6: 00 03 + 3cc8: 5d 0e + 3cca: 53 00 00 00 fadd.s ft0, ft0, ft0, rne + 3cce: 04 0f + 3cd0: 01 0c + 3cd2: 0b 41 02 00 + 3cd6: 00 03 + 3cd8: 5e 0e + 3cda: 53 00 00 00 fadd.s ft0, ft0, ft0, rne + 3cde: 04 01 + 3ce0: 00 0c + 3ce2: 00 03 + 3ce4: 04 07 + 3ce6: cf 02 00 00 fnmadd.s ft5, ft0, ft0, ft0, rne + 3cea: 0d 74 + 3cec: 0c 00 + 3cee: 00 10 + 3cf0: 03 4c 07 40 lbu s8, 1024(a4) + 3cf4: 01 00 + 3cf6: 00 0e + 3cf8: 66 6c + 3cfa: 74 00 + 3cfc: 03 4e 0a 96 lbu t3, -1696(s4) + 3d00: 00 00 + 3d02: 00 0f + 3d04: 8d 0a + 3d06: 00 00 + 3d08: 03 60 05 a9 + 3d0c: 00 00 + 3d0e: 00 00 + 3d10: 10 7a + 3d12: 0d 00 + 3d14: 00 01 + 3d16: 23 01 96 00 sb s1, 2(a2) + 3d1a: 00 00 + 3d1c: 1c 1c + 3d1e: 01 80 + 3d20: d8 12 + 3d22: 00 00 + 3d24: 01 9c + 3d26: f3 12 00 00 csrrw t0, ustatus, zero + 3d2a: 11 61 + 3d2c: 00 01 + 3d2e: 23 12 96 00 sh s1, 4(a2) + 3d32: 00 00 + 3d34: 11 62 + 3d36: 00 01 + 3d38: 23 1c 96 00 sh s1, 24(a2) + 3d3c: 00 00 + 3d3e: 12 f2 + 3d40: 08 00 + 3d42: 00 01 + 3d44: 25 03 + 3d46: 25 00 + 3d48: 00 00 + 3d4a: ec 3e + 3d4c: 00 00 + 3d4e: 12 92 + 3d50: 0a 00 + 3d52: 00 01 + 3d54: 25 03 + 3d56: 25 00 + 3d58: 00 00 + 3d5a: 52 3f + 3d5c: 00 00 + 3d5e: 13 41 5f 63 xori sp, t5, 1589 + 3d62: 00 01 + 3d64: 26 03 + 3d66: f3 12 00 00 csrrw t0, ustatus, zero + 3d6a: 70 3f + 3d6c: 00 00 + 3d6e: 13 41 5f 73 xori sp, t5, 1845 + 3d72: 00 01 + 3d74: 26 03 + 3d76: f3 12 00 00 csrrw t0, ustatus, zero + 3d7a: c7 3f 00 00 fmsub.s ft11, ft0, ft0, ft0, rup + 3d7e: 13 41 5f 65 xori sp, t5, 1621 + 3d82: 00 01 + 3d84: 26 03 + 3d86: f3 12 00 00 csrrw t0, ustatus, zero + 3d8a: ff 3f 00 00 + 3d8e: 14 41 + 3d90: 5f 66 00 01 + 3d94: 26 03 + 3d96: fa 12 + 3d98: 00 00 + 3d9a: 03 91 f0 7e lh sp, 2031(ra) + 3d9e: 13 42 5f 63 xori tp, t5, 1589 + 3da2: 00 01 + 3da4: 27 03 f3 12 + 3da8: 00 00 + 3daa: bd 40 + 3dac: 00 00 + 3dae: 13 42 5f 73 xori tp, t5, 1845 + 3db2: 00 01 + 3db4: 27 03 f3 12 + 3db8: 00 00 + 3dba: 15 41 + 3dbc: 00 00 + 3dbe: 13 42 5f 65 xori tp, t5, 1621 + 3dc2: 00 01 + 3dc4: 27 03 f3 12 + 3dc8: 00 00 + 3dca: 6e 41 + 3dcc: 00 00 + 3dce: 14 42 + 3dd0: 5f 66 00 01 + 3dd4: 27 03 fa 12 + 3dd8: 00 00 + 3dda: 03 91 80 7f lh sp, 2040(ra) + 3dde: 13 52 5f 63 + 3de2: 00 01 + 3de4: 28 03 + 3de6: f3 12 00 00 csrrw t0, ustatus, zero + 3dea: 9e 42 + 3dec: 00 00 + 3dee: 13 52 5f 73 + 3df2: 00 01 + 3df4: 28 03 + 3df6: f3 12 00 00 csrrw t0, ustatus, zero + 3dfa: eb 42 00 00 vx_tex t0, zero, zero, zero, rmm + 3dfe: 13 52 5f 65 + 3e02: 00 01 + 3e04: 28 03 + 3e06: f3 12 00 00 csrrw t0, ustatus, zero + 3e0a: 2b 43 00 00 + 3e0e: 14 52 + 3e10: 5f 66 00 01 + 3e14: 28 03 + 3e16: fa 12 + 3e18: 00 00 + 3e1a: 03 91 90 7f lh sp, 2041(ra) + 3e1e: 13 72 00 01 andi tp, zero, 16 + 3e22: 29 0a + 3e24: 96 00 + 3e26: 00 00 + 3e28: e3 44 00 00 bltz zero, 2056 + 3e2c: 15 b0 + 3e2e: 06 00 + 3e30: 00 76 + 3e32: 02 00 + 3e34: 00 16 + 3e36: f8 0b + 3e38: 00 00 + 3e3a: 01 2c + 3e3c: 03 1a 01 00 lh s4, 0(sp) + 3e40: 00 03 + 3e42: 91 a0 + 3e44: 7f 00 15 c8 + 3e48: 06 00 + 3e4a: 00 c0 + 3e4c: 02 00 + 3e4e: 00 12 + 3e50: 81 0f + 3e52: 00 00 + 3e54: 01 2c + 3e56: 03 f3 12 00 + 3e5a: 00 01 + 3e5c: 45 00 + 3e5e: 00 12 + 3e60: bc 0d + 3e62: 00 00 + 3e64: 01 2c + 3e66: 03 f3 12 00 + 3e6a: 00 15 + 3e6c: 45 00 + 3e6e: 00 12 + 3e70: a8 0d + 3e72: 00 00 + 3e74: 01 2c + 3e76: 03 f3 12 00 + 3e7a: 00 29 + 3e7c: 45 00 + 3e7e: 00 12 + 3e80: 0e 0e + 3e82: 00 00 + 3e84: 01 2c + 3e86: 03 f3 12 00 + 3e8a: 00 3d + 3e8c: 45 00 + 3e8e: 00 00 + 3e90: 15 e0 + 3e92: 06 00 + 3e94: 00 20 + 3e96: 03 00 00 12 lb zero, 288(zero) + 3e9a: 86 08 + 3e9c: 00 00 + 3e9e: 01 2c + 3ea0: 03 f3 12 00 + 3ea4: 00 5e + 3ea6: 45 00 + 3ea8: 00 17 + 3eaa: f8 06 + 3eac: 00 00 + 3eae: 12 81 + 3eb0: 0f 00 00 01 fence w, unknown + 3eb4: 2c 03 + 3eb6: f3 12 00 00 csrrw t0, ustatus, zero + 3eba: a1 45 + 3ebc: 00 00 + 3ebe: 12 bc + 3ec0: 0d 00 + 3ec2: 00 01 + 3ec4: 2c 03 + 3ec6: f3 12 00 00 csrrw t0, ustatus, zero + 3eca: dd 45 + 3ecc: 00 00 + 3ece: 12 a8 + 3ed0: 0d 00 + 3ed2: 00 01 + 3ed4: 2c 03 + 3ed6: f3 12 00 00 csrrw t0, ustatus, zero + 3eda: 29 46 + 3edc: 00 00 + 3ede: 12 0e + 3ee0: 0e 00 + 3ee2: 00 01 + 3ee4: 2c 03 + 3ee6: f3 12 00 00 csrrw t0, ustatus, zero + 3eea: 8a 46 + 3eec: 00 00 + 3eee: 00 00 + 3ef0: 15 10 + 3ef2: 07 00 00 3a + 3ef6: 03 00 00 16 lb zero, 352(zero) + 3efa: f8 0b + 3efc: 00 00 + 3efe: 01 2d + 3f00: 03 1a 01 00 lh s4, 0(sp) + 3f04: 00 03 + 3f06: 91 a0 + 3f08: 7f 00 15 28 + 3f0c: 07 00 00 84 + 3f10: 03 00 00 12 lb zero, 288(zero) + 3f14: 81 0f + 3f16: 00 00 + 3f18: 01 2d + 3f1a: 03 f3 12 00 + 3f1e: 00 cb + 3f20: 46 00 + 3f22: 00 12 + 3f24: bc 0d + 3f26: 00 00 + 3f28: 01 2d + 3f2a: 03 f3 12 00 + 3f2e: 00 df + 3f30: 46 00 + 3f32: 00 12 + 3f34: a8 0d + 3f36: 00 00 + 3f38: 01 2d + 3f3a: 03 f3 12 00 + 3f3e: 00 f3 + 3f40: 46 00 + 3f42: 00 12 + 3f44: 0e 0e + 3f46: 00 00 + 3f48: 01 2d + 3f4a: 03 f3 12 00 + 3f4e: 00 07 + 3f50: 47 00 00 00 fmsub.s ft0, ft0, ft0, ft0, rne + 3f54: 15 40 + 3f56: 07 00 00 e4 + 3f5a: 03 00 00 12 lb zero, 288(zero) + 3f5e: 86 08 + 3f60: 00 00 + 3f62: 01 2d + 3f64: 03 f3 12 00 + 3f68: 00 28 + 3f6a: 47 00 00 17 + 3f6e: 58 07 + 3f70: 00 00 + 3f72: 12 81 + 3f74: 0f 00 00 01 fence w, unknown + 3f78: 2d 03 + 3f7a: f3 12 00 00 csrrw t0, ustatus, zero + 3f7e: 6b 47 00 00 vx_tex a4, zero, zero, zero, rmm + 3f82: 12 bc + 3f84: 0d 00 + 3f86: 00 01 + 3f88: 2d 03 + 3f8a: f3 12 00 00 csrrw t0, ustatus, zero + 3f8e: a7 47 00 00 + 3f92: 12 a8 + 3f94: 0d 00 + 3f96: 00 01 + 3f98: 2d 03 + 3f9a: f3 12 00 00 csrrw t0, ustatus, zero + 3f9e: f3 47 00 00 + 3fa2: 12 0e + 3fa4: 0e 00 + 3fa6: 00 01 + 3fa8: 2d 03 + 3faa: f3 12 00 00 csrrw t0, ustatus, zero + 3fae: 54 48 + 3fb0: 00 00 + 3fb2: 00 00 + 3fb4: 18 d8 + 3fb6: 20 01 + 3fb8: 80 bc + 3fba: 07 00 00 dc + 3fbe: 0f 00 00 16 + 3fc2: 0e 0d + 3fc4: 00 00 + 3fc6: 01 2e + 3fc8: 03 0a 13 00 lb s4, 1(t1) + 3fcc: 00 03 + 3fce: 91 a0 + 3fd0: 7f 15 70 07 + 3fd4: 00 00 + 3fd6: 85 0f + 3fd8: 00 00 + 3fda: 12 a5 + 3fdc: 0e 00 + 3fde: 00 01 + 3fe0: 2e 03 + 3fe2: 13 01 00 00 mv sp, zero + 3fe6: 95 48 + 3fe8: 00 00 + 3fea: 12 c1 + 3fec: 0e 00 + 3fee: 00 01 + 3ff0: 2e 03 + 3ff2: 13 01 00 00 mv sp, zero + 3ff6: 45 4d + 3ff8: 00 00 + 3ffa: 12 26 + 3ffc: 0d 00 + 3ffe: 00 01 + 4000: 2e 03 + 4002: 13 01 00 00 mv sp, zero + 4006: ca 4d + 4008: 00 00 + 400a: 12 42 + 400c: 0d 00 + 400e: 00 01 + 4010: 2e 03 + 4012: 13 01 00 00 mv sp, zero + 4016: 98 52 + 4018: 00 00 + 401a: 12 d0 + 401c: 0d 00 + 401e: 00 01 + 4020: 2e 03 + 4022: 13 01 00 00 mv sp, zero + 4026: d9 52 + 4028: 00 00 + 402a: 12 5e + 402c: 0d 00 + 402e: 00 01 + 4030: 2e 03 + 4032: 13 01 00 00 mv sp, zero + 4036: 2e 57 + 4038: 00 00 + 403a: 12 5b + 403c: 0e 00 + 403e: 00 01 + 4040: 2e 03 + 4042: 13 01 00 00 mv sp, zero + 4046: 7c 57 + 4048: 00 00 + 404a: 12 77 + 404c: 0e 00 + 404e: 00 01 + 4050: 2e 03 + 4052: 13 01 00 00 mv sp, zero + 4056: 91 5d + 4058: 00 00 + 405a: 12 36 + 405c: 0f 00 00 01 fence w, unknown + 4060: 2e 03 + 4062: 13 01 00 00 mv sp, zero + 4066: c7 5d 00 00 + 406a: 12 52 + 406c: 0f 00 00 01 fence w, unknown + 4070: 2e 03 + 4072: 13 01 00 00 mv sp, zero + 4076: e1 61 + 4078: 00 00 + 407a: 15 98 + 407c: 07 00 00 34 + 4080: 05 00 + 4082: 00 12 + 4084: 11 06 + 4086: 00 00 + 4088: 01 2e + 408a: 03 13 01 00 lh t1, 0(sp) + 408e: 00 17 + 4090: 62 00 + 4092: 00 12 + 4094: 16 06 + 4096: 00 00 + 4098: 01 2e + 409a: 03 13 01 00 lh t1, 0(sp) + 409e: 00 d0 + 40a0: 63 00 00 12 beqz zero, 288 + 40a4: 1b 06 00 00 + 40a8: 01 2e + 40aa: 03 13 01 00 lh t1, 0(sp) + 40ae: 00 19 + 40b0: 68 00 + 40b2: 00 12 + 40b4: 20 06 + 40b6: 00 00 + 40b8: 01 2e + 40ba: 03 13 01 00 lh t1, 0(sp) + 40be: 00 80 + 40c0: 69 00 + 40c2: 00 12 + 40c4: 6d 03 + 40c6: 00 00 + 40c8: 01 2e + 40ca: 03 61 00 00 + 40ce: 00 93 + 40d0: 69 00 + 40d2: 00 12 + 40d4: 31 04 + 40d6: 00 00 + 40d8: 01 2e + 40da: 03 61 00 00 + 40de: 00 c0 + 40e0: 69 00 + 40e2: 00 12 + 40e4: 57 03 00 00 + 40e8: 01 2e + 40ea: 03 61 00 00 + 40ee: 00 ed + 40f0: 69 00 + 40f2: 00 12 + 40f4: 2c 04 + 40f6: 00 00 + 40f8: 01 2e + 40fa: 03 61 00 00 + 40fe: 00 1a + 4100: 6a 00 + 4102: 00 00 + 4104: 15 b8 + 4106: 07 00 00 ba + 410a: 05 00 + 410c: 00 12 + 410e: 11 06 + 4110: 00 00 + 4112: 01 2e + 4114: 03 13 01 00 lh t1, 0(sp) + 4118: 00 47 + 411a: 6a 00 + 411c: 00 12 + 411e: 16 06 + 4120: 00 00 + 4122: 01 2e + 4124: 03 13 01 00 lh t1, 0(sp) + 4128: 00 e0 + 412a: 6b 00 00 12 vx_tex zero, zero, zero, sp, rne + 412e: 1b 06 00 00 + 4132: 01 2e + 4134: 03 13 01 00 lh t1, 0(sp) + 4138: 00 ba + 413a: 6f 00 00 12 j 288 + 413e: 20 06 + 4140: 00 00 + 4142: 01 2e + 4144: 03 13 01 00 lh t1, 0(sp) + 4148: 00 89 + 414a: 70 00 + 414c: 00 12 + 414e: 6d 03 + 4150: 00 00 + 4152: 01 2e + 4154: 03 61 00 00 + 4158: 00 9c + 415a: 70 00 + 415c: 00 19 + 415e: 31 04 + 4160: 00 00 + 4162: 01 2e + 4164: 03 61 00 00 + 4168: 00 12 + 416a: 57 03 00 00 + 416e: 01 2e + 4170: 03 61 00 00 + 4174: 00 be + 4176: 70 00 + 4178: 00 12 + 417a: 2c 04 + 417c: 00 00 + 417e: 01 2e + 4180: 03 61 00 00 + 4184: 00 eb + 4186: 70 00 + 4188: 00 00 + 418a: 15 d8 + 418c: 07 00 00 44 + 4190: 06 00 + 4192: 00 12 + 4194: 11 06 + 4196: 00 00 + 4198: 01 2e + 419a: 03 13 01 00 lh t1, 0(sp) + 419e: 00 18 + 41a0: 71 00 + 41a2: 00 12 + 41a4: 16 06 + 41a6: 00 00 + 41a8: 01 2e + 41aa: 03 13 01 00 lh t1, 0(sp) + 41ae: 00 75 + 41b0: 72 00 + 41b2: 00 12 + 41b4: 1b 06 00 00 + 41b8: 01 2e + 41ba: 03 13 01 00 lh t1, 0(sp) + 41be: 00 d3 + 41c0: 75 00 + 41c2: 00 12 + 41c4: 20 06 + 41c6: 00 00 + 41c8: 01 2e + 41ca: 03 13 01 00 lh t1, 0(sp) + 41ce: 00 27 + 41d0: 77 00 00 12 + 41d4: 6d 03 + 41d6: 00 00 + 41d8: 01 2e + 41da: 03 61 00 00 + 41de: 00 3a + 41e0: 77 00 00 12 + 41e4: 31 04 + 41e6: 00 00 + 41e8: 01 2e + 41ea: 03 61 00 00 + 41ee: 00 67 + 41f0: 77 00 00 12 + 41f4: 57 03 00 00 + 41f8: 01 2e + 41fa: 03 61 00 00 + 41fe: 00 89 + 4200: 77 00 00 12 + 4204: 2c 04 + 4206: 00 00 + 4208: 01 2e + 420a: 03 61 00 00 + 420e: 00 b6 + 4210: 77 00 00 00 + 4214: 15 f0 + 4216: 07 00 00 c8 + 421a: 06 00 + 421c: 00 12 + 421e: 11 06 + 4220: 00 00 + 4222: 01 2e + 4224: 03 13 01 00 lh t1, 0(sp) + 4228: 00 e3 + 422a: 77 00 00 12 + 422e: 16 06 + 4230: 00 00 + 4232: 01 2e + 4234: 03 13 01 00 lh t1, 0(sp) + 4238: 00 d0 + 423a: 78 00 + 423c: 00 16 + 423e: 1b 06 00 00 + 4242: 01 2e + 4244: 03 13 01 00 lh t1, 0(sp) + 4248: 00 01 + 424a: 56 12 + 424c: 20 06 + 424e: 00 00 + 4250: 01 2e + 4252: 03 13 01 00 lh t1, 0(sp) + 4256: 00 5b + 4258: 7b 00 00 12 + 425c: 6d 03 + 425e: 00 00 + 4260: 01 2e + 4262: 03 61 00 00 + 4266: 00 6e + 4268: 7b 00 00 19 + 426c: 31 04 + 426e: 00 00 + 4270: 01 2e + 4272: 03 61 00 00 + 4276: 00 12 + 4278: 57 03 00 00 + 427c: 01 2e + 427e: 03 61 00 00 + 4282: 00 90 + 4284: 7b 00 00 12 + 4288: 2c 04 + 428a: 00 00 + 428c: 01 2e + 428e: 03 61 00 00 + 4292: 00 bd + 4294: 7b 00 00 00 + 4298: 15 08 + 429a: 08 00 + 429c: 00 52 + 429e: 07 00 00 12 + 42a2: 11 06 + 42a4: 00 00 + 42a6: 01 2e + 42a8: 03 13 01 00 lh t1, 0(sp) + 42ac: 00 ea + 42ae: 7b 00 00 12 + 42b2: 16 06 + 42b4: 00 00 + 42b6: 01 2e + 42b8: 03 13 01 00 lh t1, 0(sp) + 42bc: 00 79 + 42be: 7d 00 + 42c0: 00 12 + 42c2: 1b 06 00 00 + 42c6: 01 2e + 42c8: 03 13 01 00 lh t1, 0(sp) + 42cc: 00 68 + 42ce: 81 00 + 42d0: 00 12 + 42d2: 20 06 + 42d4: 00 00 + 42d6: 01 2e + 42d8: 03 13 01 00 lh t1, 0(sp) + 42dc: 00 05 + 42de: 82 00 + 42e0: 00 12 + 42e2: 6d 03 + 42e4: 00 00 + 42e6: 01 2e + 42e8: 03 61 00 00 + 42ec: 00 18 + 42ee: 82 00 + 42f0: 00 12 + 42f2: 31 04 + 42f4: 00 00 + 42f6: 01 2e + 42f8: 03 61 00 00 + 42fc: 00 3a + 42fe: 82 00 + 4300: 00 12 + 4302: 57 03 00 00 + 4306: 01 2e + 4308: 03 61 00 00 + 430c: 00 67 + 430e: 82 00 + 4310: 00 12 + 4312: 2c 04 + 4314: 00 00 + 4316: 01 2e + 4318: 03 61 00 00 + 431c: 00 94 + 431e: 82 00 + 4320: 00 00 + 4322: 15 20 + 4324: 08 00 + 4326: 00 dc + 4328: 07 00 00 12 + 432c: 11 06 + 432e: 00 00 + 4330: 01 2e + 4332: 03 13 01 00 lh t1, 0(sp) + 4336: 00 c1 + 4338: 82 00 + 433a: 00 12 + 433c: 16 06 + 433e: 00 00 + 4340: 01 2e + 4342: 03 13 01 00 lh t1, 0(sp) + 4346: 00 0f + 4348: 84 00 + 434a: 00 12 + 434c: 1b 06 00 00 + 4350: 01 2e + 4352: 03 13 01 00 lh t1, 0(sp) + 4356: 00 5e + 4358: 87 00 00 12 + 435c: 20 06 + 435e: 00 00 + 4360: 01 2e + 4362: 03 13 01 00 lh t1, 0(sp) + 4366: 00 c1 + 4368: 88 00 + 436a: 00 12 + 436c: 6d 03 + 436e: 00 00 + 4370: 01 2e + 4372: 03 61 00 00 + 4376: 00 d4 + 4378: 88 00 + 437a: 00 12 + 437c: 31 04 + 437e: 00 00 + 4380: 01 2e + 4382: 03 61 00 00 + 4386: 00 01 + 4388: 89 00 + 438a: 00 12 + 438c: 57 03 00 00 + 4390: 01 2e + 4392: 03 61 00 00 + 4396: 00 23 + 4398: 89 00 + 439a: 00 12 + 439c: 2c 04 + 439e: 00 00 + 43a0: 01 2e + 43a2: 03 61 00 00 + 43a6: 00 50 + 43a8: 89 00 + 43aa: 00 00 + 43ac: 15 38 + 43ae: 08 00 + 43b0: 00 06 + 43b2: 08 00 + 43b4: 00 12 + 43b6: b2 0a + 43b8: 00 00 + 43ba: 01 2e + 43bc: 03 13 01 00 lh t1, 0(sp) + 43c0: 00 7d + 43c2: 89 00 + 43c4: 00 12 + 43c6: 67 0b 00 00 jalr s6, zero + 43ca: 01 2e + 43cc: 03 13 01 00 lh t1, 0(sp) + 43d0: 00 90 + 43d2: 89 00 + 43d4: 00 00 + 43d6: 15 58 + 43d8: 08 00 + 43da: 00 28 + 43dc: 08 00 + 43de: 00 19 + 43e0: b2 0a + 43e2: 00 00 + 43e4: 01 2e + 43e6: 03 13 01 00 lh t1, 0(sp) + 43ea: 00 19 + 43ec: 67 0b 00 00 jalr s6, zero + 43f0: 01 2e + 43f2: 03 13 01 00 lh t1, 0(sp) + 43f6: 00 00 + 43f8: 15 d8 + 43fa: 08 00 + 43fc: 00 52 + 43fe: 08 00 + 4400: 00 12 + 4402: b2 0a + 4404: 00 00 + 4406: 01 2e + 4408: 03 13 01 00 lh t1, 0(sp) + 440c: 00 bf + 440e: 89 00 + 4410: 00 12 + 4412: 67 0b 00 00 jalr s6, zero + 4416: 01 2e + 4418: 03 13 01 00 lh t1, 0(sp) + 441c: 00 d2 + 441e: 89 00 + 4420: 00 00 + 4422: 15 80 + 4424: 08 00 + 4426: 00 7c + 4428: 08 00 + 442a: 00 12 + 442c: b2 0a + 442e: 00 00 + 4430: 01 2e + 4432: 03 13 01 00 lh t1, 0(sp) + 4436: 00 20 + 4438: 8a 00 + 443a: 00 12 + 443c: 67 0b 00 00 jalr s6, zero + 4440: 01 2e + 4442: 03 13 01 00 lh t1, 0(sp) + 4446: 00 40 + 4448: 8a 00 + 444a: 00 00 + 444c: 15 20 + 444e: 09 00 + 4450: 00 9e + 4452: 08 00 + 4454: 00 19 + 4456: b2 0a + 4458: 00 00 + 445a: 01 2e + 445c: 03 13 01 00 lh t1, 0(sp) + 4460: 00 19 + 4462: 67 0b 00 00 jalr s6, zero + 4466: 01 2e + 4468: 03 13 01 00 lh t1, 0(sp) + 446c: 00 00 + 446e: 15 70 + 4470: 09 00 + 4472: 00 28 + 4474: 09 00 + 4476: 00 12 + 4478: 11 06 + 447a: 00 00 + 447c: 01 2e + 447e: 03 13 01 00 lh t1, 0(sp) + 4482: 00 bd + 4484: 8a 00 + 4486: 00 12 + 4488: 16 06 + 448a: 00 00 + 448c: 01 2e + 448e: 03 13 01 00 lh t1, 0(sp) + 4492: 00 f6 + 4494: 8b 00 00 12 + 4498: 1b 06 00 00 + 449c: 01 2e + 449e: 03 13 01 00 lh t1, 0(sp) + 44a2: 00 04 + 44a4: 8f 00 00 12 + 44a8: 20 06 + 44aa: 00 00 + 44ac: 01 2e + 44ae: 03 13 01 00 lh t1, 0(sp) + 44b2: 00 78 + 44b4: 8f 00 00 12 + 44b8: 6d 03 + 44ba: 00 00 + 44bc: 01 2e + 44be: 03 61 00 00 + 44c2: 00 8b + 44c4: 8f 00 00 12 + 44c8: 31 04 + 44ca: 00 00 + 44cc: 01 2e + 44ce: 03 61 00 00 + 44d2: 00 ad + 44d4: 8f 00 00 12 + 44d8: 57 03 00 00 + 44dc: 01 2e + 44de: 03 61 00 00 + 44e2: 00 da + 44e4: 8f 00 00 12 + 44e8: 2c 04 + 44ea: 00 00 + 44ec: 01 2e + 44ee: 03 61 00 00 + 44f2: 00 07 + 44f4: 90 00 + 44f6: 00 00 + 44f8: 15 90 + 44fa: 09 00 + 44fc: 00 b2 + 44fe: 09 00 + 4500: 00 12 + 4502: 11 06 + 4504: 00 00 + 4506: 01 2e + 4508: 03 13 01 00 lh t1, 0(sp) + 450c: 00 34 + 450e: 90 00 + 4510: 00 12 + 4512: 16 06 + 4514: 00 00 + 4516: 01 2e + 4518: 03 13 01 00 lh t1, 0(sp) + 451c: 00 6d + 451e: 91 00 + 4520: 00 12 + 4522: 1b 06 00 00 + 4526: 01 2e + 4528: 03 13 01 00 lh t1, 0(sp) + 452c: 00 67 + 452e: 94 00 + 4530: 00 12 + 4532: 20 06 + 4534: 00 00 + 4536: 01 2e + 4538: 03 13 01 00 lh t1, 0(sp) + 453c: 00 9b + 453e: 95 00 + 4540: 00 12 + 4542: 6d 03 + 4544: 00 00 + 4546: 01 2e + 4548: 03 61 00 00 + 454c: 00 ae + 454e: 95 00 + 4550: 00 12 + 4552: 31 04 + 4554: 00 00 + 4556: 01 2e + 4558: 03 61 00 00 + 455c: 00 db + 455e: 95 00 + 4560: 00 12 + 4562: 57 03 00 00 + 4566: 01 2e + 4568: 03 61 00 00 + 456c: 00 fd + 456e: 95 00 + 4570: 00 12 + 4572: 2c 04 + 4574: 00 00 + 4576: 01 2e + 4578: 03 61 00 00 + 457c: 00 2a + 457e: 96 00 + 4580: 00 00 + 4582: 15 b0 + 4584: 09 00 + 4586: 00 3a + 4588: 0a 00 + 458a: 00 12 + 458c: 11 06 + 458e: 00 00 + 4590: 01 2e + 4592: 03 13 01 00 lh t1, 0(sp) + 4596: 00 57 + 4598: 96 00 + 459a: 00 12 + 459c: 16 06 + 459e: 00 00 + 45a0: 01 2e + 45a2: 03 13 01 00 lh t1, 0(sp) + 45a6: 00 3a + 45a8: 97 00 00 16 auipc ra, 90112 + 45ac: 1b 06 00 00 + 45b0: 01 2e + 45b2: 03 13 01 00 lh t1, 0(sp) + 45b6: 00 01 + 45b8: 65 12 + 45ba: 20 06 + 45bc: 00 00 + 45be: 01 2e + 45c0: 03 13 01 00 lh t1, 0(sp) + 45c4: 00 a7 + 45c6: 99 00 + 45c8: 00 12 + 45ca: 6d 03 + 45cc: 00 00 + 45ce: 01 2e + 45d0: 03 61 00 00 + 45d4: 00 ba + 45d6: 99 00 + 45d8: 00 12 + 45da: 31 04 + 45dc: 00 00 + 45de: 01 2e + 45e0: 03 61 00 00 + 45e4: 00 dc + 45e6: 99 00 + 45e8: 00 12 + 45ea: 57 03 00 00 + 45ee: 01 2e + 45f0: 03 61 00 00 + 45f4: 00 fe + 45f6: 99 00 + 45f8: 00 12 + 45fa: 2c 04 + 45fc: 00 00 + 45fe: 01 2e + 4600: 03 61 00 00 + 4604: 00 2b + 4606: 9a 00 + 4608: 00 00 + 460a: 15 d0 + 460c: 09 00 + 460e: 00 be + 4610: 0a 00 + 4612: 00 12 + 4614: 11 06 + 4616: 00 00 + 4618: 01 2e + 461a: 03 13 01 00 lh t1, 0(sp) + 461e: 00 58 + 4620: 9a 00 + 4622: 00 12 + 4624: 16 06 + 4626: 00 00 + 4628: 01 2e + 462a: 03 13 01 00 lh t1, 0(sp) + 462e: 00 26 + 4630: 9b 00 00 16 + 4634: 1b 06 00 00 + 4638: 01 2e + 463a: 03 13 01 00 lh t1, 0(sp) + 463e: 00 01 + 4640: 65 12 + 4642: 20 06 + 4644: 00 00 + 4646: 01 2e + 4648: 03 13 01 00 lh t1, 0(sp) + 464c: 00 75 + 464e: 9d 00 + 4650: 00 12 + 4652: 6d 03 + 4654: 00 00 + 4656: 01 2e + 4658: 03 61 00 00 + 465c: 00 88 + 465e: 9d 00 + 4660: 00 19 + 4662: 31 04 + 4664: 00 00 + 4666: 01 2e + 4668: 03 61 00 00 + 466c: 00 12 + 466e: 57 03 00 00 + 4672: 01 2e + 4674: 03 61 00 00 + 4678: 00 aa + 467a: 9d 00 + 467c: 00 12 + 467e: 2c 04 + 4680: 00 00 + 4682: 01 2e + 4684: 03 61 00 00 + 4688: 00 d7 + 468a: 9d 00 + 468c: 00 00 + 468e: 15 e8 + 4690: 09 00 + 4692: 00 e8 + 4694: 0a 00 + 4696: 00 12 + 4698: b2 0a + 469a: 00 00 + 469c: 01 2e + 469e: 03 13 01 00 lh t1, 0(sp) + 46a2: 00 04 + 46a4: 9e 00 + 46a6: 00 12 + 46a8: 67 0b 00 00 jalr s6, zero + 46ac: 01 2e + 46ae: 03 13 01 00 lh t1, 0(sp) + 46b2: 00 17 + 46b4: 9e 00 + 46b6: 00 00 + 46b8: 15 20 + 46ba: 0a 00 + 46bc: 00 12 + 46be: 0b 00 00 12 + 46c2: b2 0a + 46c4: 00 00 + 46c6: 01 2e + 46c8: 03 13 01 00 lh t1, 0(sp) + 46cc: 00 82 + 46ce: 9e 00 + 46d0: 00 12 + 46d2: 67 0b 00 00 jalr s6, zero + 46d6: 01 2e + 46d8: 03 13 01 00 lh t1, 0(sp) + 46dc: 00 95 + 46de: 9e 00 + 46e0: 00 00 + 46e2: 15 68 + 46e4: 0a 00 + 46e6: 00 3c + 46e8: 0b 00 00 12 + 46ec: b2 0a + 46ee: 00 00 + 46f0: 01 2e + 46f2: 03 13 01 00 lh t1, 0(sp) + 46f6: 00 2d + 46f8: 9f 00 00 12 + 46fc: 67 0b 00 00 jalr s6, zero + 4700: 01 2e + 4702: 03 13 01 00 lh t1, 0(sp) + 4706: 00 5a + 4708: 9f 00 00 00 + 470c: 15 b8 + 470e: 0a 00 + 4710: 00 66 + 4712: 0b 00 00 12 + 4716: b2 0a + 4718: 00 00 + 471a: 01 2e + 471c: 03 13 01 00 lh t1, 0(sp) + 4720: 00 b2 + 4722: a0 00 + 4724: 00 12 + 4726: 67 0b 00 00 jalr s6, zero + 472a: 01 2e + 472c: 03 13 01 00 lh t1, 0(sp) + 4730: 00 d4 + 4732: a4 00 + 4734: 00 00 + 4736: 15 00 + 4738: 0b 00 00 ee + 473c: 0b 00 00 12 + 4740: 11 06 + 4742: 00 00 + 4744: 01 2e + 4746: 03 13 01 00 lh t1, 0(sp) + 474a: 00 09 + 474c: a5 00 + 474e: 00 12 + 4750: 16 06 + 4752: 00 00 + 4754: 01 2e + 4756: 03 13 01 00 lh t1, 0(sp) + 475a: 00 ad + 475c: a5 00 + 475e: 00 16 + 4760: 1b 06 00 00 + 4764: 01 2e + 4766: 03 13 01 00 lh t1, 0(sp) + 476a: 00 01 + 476c: 68 12 + 476e: 20 06 + 4770: 00 00 + 4772: 01 2e + 4774: 03 13 01 00 lh t1, 0(sp) + 4778: 00 98 + 477a: a7 00 00 12 + 477e: 6d 03 + 4780: 00 00 + 4782: 01 2e + 4784: 03 61 00 00 + 4788: 00 ab + 478a: a7 00 00 12 + 478e: 31 04 + 4790: 00 00 + 4792: 01 2e + 4794: 03 61 00 00 + 4798: 00 cd + 479a: a7 00 00 12 + 479e: 57 03 00 00 + 47a2: 01 2e + 47a4: 03 61 00 00 + 47a8: 00 ef + 47aa: a7 00 00 12 + 47ae: 2c 04 + 47b0: 00 00 + 47b2: 01 2e + 47b4: 03 61 00 00 + 47b8: 00 1c + 47ba: a8 00 + 47bc: 00 00 + 47be: 15 20 + 47c0: 0b 00 00 78 + 47c4: 0c 00 + 47c6: 00 12 + 47c8: 11 06 + 47ca: 00 00 + 47cc: 01 2e + 47ce: 03 13 01 00 lh t1, 0(sp) + 47d2: 00 49 + 47d4: a8 00 + 47d6: 00 12 + 47d8: 16 06 + 47da: 00 00 + 47dc: 01 2e + 47de: 03 13 01 00 lh t1, 0(sp) + 47e2: 00 02 + 47e4: a9 00 + 47e6: 00 12 + 47e8: 1b 06 00 00 + 47ec: 01 2e + 47ee: 03 13 01 00 lh t1, 0(sp) + 47f2: 00 29 + 47f4: ab 00 00 12 + 47f8: 20 06 + 47fa: 00 00 + 47fc: 01 2e + 47fe: 03 13 01 00 lh t1, 0(sp) + 4802: 00 9d + 4804: ab 00 00 12 + 4808: 6d 03 + 480a: 00 00 + 480c: 01 2e + 480e: 03 61 00 00 + 4812: 00 b0 + 4814: ab 00 00 12 + 4818: 31 04 + 481a: 00 00 + 481c: 01 2e + 481e: 03 61 00 00 + 4822: 00 d2 + 4824: ab 00 00 12 + 4828: 57 03 00 00 + 482c: 01 2e + 482e: 03 61 00 00 + 4832: 00 f4 + 4834: ab 00 00 12 + 4838: 2c 04 + 483a: 00 00 + 483c: 01 2e + 483e: 03 61 00 00 + 4842: 00 21 + 4844: ac 00 + 4846: 00 00 + 4848: 15 40 + 484a: 0b 00 00 fe + 484e: 0c 00 + 4850: 00 12 + 4852: 11 06 + 4854: 00 00 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+ 48ee: 03 13 01 00 lh t1, 0(sp) + 48f2: 00 ac + 48f4: b0 00 + 48f6: 00 12 + 48f8: 1b 06 00 00 + 48fc: 01 2e + 48fe: 03 13 01 00 lh t1, 0(sp) + 4902: 00 75 + 4904: b2 00 + 4906: 00 12 + 4908: 20 06 + 490a: 00 00 + 490c: 01 2e + 490e: 03 13 01 00 lh t1, 0(sp) + 4912: 00 e9 + 4914: b2 00 + 4916: 00 12 + 4918: 6d 03 + 491a: 00 00 + 491c: 01 2e + 491e: 03 61 00 00 + 4922: 00 fc + 4924: b2 00 + 4926: 00 12 + 4928: 31 04 + 492a: 00 00 + 492c: 01 2e + 492e: 03 61 00 00 + 4932: 00 1e + 4934: b3 00 00 12 + 4938: 57 03 00 00 + 493c: 01 2e + 493e: 03 61 00 00 + 4942: 00 40 + 4944: b3 00 00 12 + 4948: 2c 04 + 494a: 00 00 + 494c: 01 2e + 494e: 03 61 00 00 + 4952: 00 6d + 4954: b3 00 00 00 add ra, zero, zero + 4958: 15 78 + 495a: 0b 00 00 12 + 495e: 0e 00 + 4960: 00 12 + 4962: 11 06 + 4964: 00 00 + 4966: 01 2e + 4968: 03 13 01 00 lh t1, 0(sp) + 496c: 00 9a + 496e: b3 00 00 12 + 4972: 16 06 + 4974: 00 00 + 4976: 01 2e + 4978: 03 13 01 00 lh t1, 0(sp) + 497c: 00 29 + 497e: b4 00 + 4980: 00 12 + 4982: 1b 06 00 00 + 4986: 01 2e + 4988: 03 13 01 00 lh t1, 0(sp) + 498c: 00 b3 + 498e: b5 00 + 4990: 00 12 + 4992: 20 06 + 4994: 00 00 + 4996: 01 2e + 4998: 03 13 01 00 lh t1, 0(sp) + 499c: 00 3d + 499e: b6 00 + 49a0: 00 12 + 49a2: 6d 03 + 49a4: 00 00 + 49a6: 01 2e + 49a8: 03 61 00 00 + 49ac: 00 50 + 49ae: b6 00 + 49b0: 00 12 + 49b2: 31 04 + 49b4: 00 00 + 49b6: 01 2e + 49b8: 03 61 00 00 + 49bc: 00 72 + 49be: b6 00 + 49c0: 00 12 + 49c2: 57 03 00 00 + 49c6: 01 2e + 49c8: 03 61 00 00 + 49cc: 00 94 + 49ce: b6 00 + 49d0: 00 12 + 49d2: 2c 04 + 49d4: 00 00 + 49d6: 01 2e + 49d8: 03 61 00 00 + 49dc: 00 c1 + 49de: b6 00 + 49e0: 00 00 + 49e2: 15 90 + 49e4: 0b 00 00 3c + 49e8: 0e 00 + 49ea: 00 12 + 49ec: b2 0a + 49ee: 00 00 + 49f0: 01 2e + 49f2: 03 13 01 00 lh t1, 0(sp) + 49f6: 00 ee + 49f8: b6 00 + 49fa: 00 12 + 49fc: 67 0b 00 00 jalr s6, zero + 4a00: 01 2e + 4a02: 03 13 01 00 lh t1, 0(sp) + 4a06: 00 16 + 4a08: b9 00 + 4a0a: 00 00 + 4a0c: 15 c0 + 4a0e: 0b 00 00 66 + 4a12: 0e 00 + 4a14: 00 12 + 4a16: b2 0a + 4a18: 00 00 + 4a1a: 01 2e + 4a1c: 03 13 01 00 lh t1, 0(sp) + 4a20: 00 8b + 4a22: b9 00 + 4a24: 00 12 + 4a26: 67 0b 00 00 jalr s6, zero + 4a2a: 01 2e + 4a2c: 03 13 01 00 lh t1, 0(sp) + 4a30: 00 4b + 4a32: be 00 + 4a34: 00 00 + 4a36: 15 f8 + 4a38: 0b 00 00 90 + 4a3c: 0e 00 + 4a3e: 00 12 + 4a40: b2 0a + 4a42: 00 00 + 4a44: 01 2e + 4a46: 03 13 01 00 lh t1, 0(sp) + 4a4a: 00 a9 + 4a4c: bf 00 00 12 + 4a50: 67 0b 00 00 jalr s6, zero + 4a54: 01 2e + 4a56: 03 13 01 00 lh t1, 0(sp) + 4a5a: 00 d7 + 4a5c: c3 00 00 00 fmadd.s ft1, ft0, ft0, ft0, rne + 4a60: 15 30 + 4a62: 0c 00 + 4a64: 00 ba + 4a66: 0e 00 + 4a68: 00 12 + 4a6a: b2 0a + 4a6c: 00 00 + 4a6e: 01 2e + 4a70: 03 13 01 00 lh t1, 0(sp) + 4a74: 00 5d + 4a76: c9 00 + 4a78: 00 12 + 4a7a: 67 0b 00 00 jalr s6, zero + 4a7e: 01 2e + 4a80: 03 13 01 00 lh t1, 0(sp) + 4a84: 00 8e + 4a86: cb 00 00 00 fnmsub.s ft1, ft0, ft0, ft0, rne + 4a8a: 15 50 + 4a8c: 0c 00 + 4a8e: 00 e4 + 4a90: 0e 00 + 4a92: 00 12 + 4a94: b2 0a + 4a96: 00 00 + 4a98: 01 2e + 4a9a: 03 13 01 00 lh t1, 0(sp) + 4a9e: 00 bc + 4aa0: cb 00 00 12 + 4aa4: 67 0b 00 00 jalr s6, zero + 4aa8: 01 2e + 4aaa: 03 13 01 00 lh t1, 0(sp) + 4aae: 00 27 + 4ab0: cc 00 + 4ab2: 00 00 + 4ab4: 15 70 + 4ab6: 0c 00 + 4ab8: 00 6e + 4aba: 0f 00 00 12 + 4abe: 11 06 + 4ac0: 00 00 + 4ac2: 01 2e + 4ac4: 03 13 01 00 lh t1, 0(sp) + 4ac8: 00 60 + 4aca: cc 00 + 4acc: 00 12 + 4ace: 16 06 + 4ad0: 00 00 + 4ad2: 01 2e + 4ad4: 03 13 01 00 lh t1, 0(sp) + 4ad8: 00 ab + 4ada: cc 00 + 4adc: 00 12 + 4ade: 1b 06 00 00 + 4ae2: 01 2e + 4ae4: 03 13 01 00 lh t1, 0(sp) + 4ae8: 00 42 + 4aea: cd 00 + 4aec: 00 12 + 4aee: 20 06 + 4af0: 00 00 + 4af2: 01 2e + 4af4: 03 13 01 00 lh t1, 0(sp) + 4af8: 00 60 + 4afa: cd 00 + 4afc: 00 12 + 4afe: 6d 03 + 4b00: 00 00 + 4b02: 01 2e + 4b04: 03 61 00 00 + 4b08: 00 73 + 4b0a: cd 00 + 4b0c: 00 12 + 4b0e: 31 04 + 4b10: 00 00 + 4b12: 01 2e + 4b14: 03 61 00 00 + 4b18: 00 95 + 4b1a: cd 00 + 4b1c: 00 12 + 4b1e: 57 03 00 00 + 4b22: 01 2e + 4b24: 03 61 00 00 + 4b28: 00 b7 + 4b2a: cd 00 + 4b2c: 00 12 + 4b2e: 2c 04 + 4b30: 00 00 + 4b32: 01 2e + 4b34: 03 61 00 00 + 4b38: 00 e4 + 4b3a: cd 00 + 4b3c: 00 00 + 4b3e: 17 88 0c 00 auipc a6, 200 + 4b42: 00 13 + 4b44: 5f 5f 78 00 + 4b48: 01 2e + 4b4a: 03 13 01 00 lh t1, 0(sp) + 4b4e: 00 11 + 4b50: ce 00 + 4b52: 00 00 + 4b54: 00 17 + 4b56: b0 0c + 4b58: 00 00 + 4b5a: 12 96 + 4b5c: 0d 00 + 4b5e: 00 01 + 4b60: 2e 03 + 4b62: f3 12 00 00 csrrw t0, ustatus, zero + 4b66: 24 ce + 4b68: 00 00 + 4b6a: 12 dd + 4b6c: 0e 00 + 4b6e: 00 01 + 4b70: 2e 03 + 4b72: f3 12 00 00 csrrw t0, ustatus, zero + 4b76: 44 ce + 4b78: 00 00 + 4b7a: 12 1f + 4b7c: 0e 00 + 4b7e: 00 01 + 4b80: 2e 03 + 4b82: f3 12 00 00 csrrw t0, ustatus, zero + 4b86: 64 ce + 4b88: 00 00 + 4b8a: 12 93 + 4b8c: 0f 00 00 01 fence w, unknown + 4b90: 2e 03 + 4b92: f3 12 00 00 csrrw t0, ustatus, zero + 4b96: 84 ce + 4b98: 00 00 + 4b9a: 12 fd + 4b9c: 0d 00 + 4b9e: 00 01 + 4ba0: 2e 03 + 4ba2: 13 01 00 00 mv sp, zero + 4ba6: a4 ce + 4ba8: 00 00 + 4baa: 00 00 + 4bac: 18 9c + 4bae: 28 01 + 4bb0: 80 48 + 4bb2: 00 00 + 4bb4: 00 50 + 4bb6: 10 00 + 4bb8: 00 19 + 4bba: 9c 0a + 4bbc: 00 00 + 4bbe: 01 2e + 4bc0: 03 25 00 00 lw a0, 0(zero) + 4bc4: 00 1a + 4bc6: 9c 28 + 4bc8: 01 80 + 4bca: 3c 00 + 4bcc: 00 00 + 4bce: 12 13 + 4bd0: 0b 00 00 01 + 4bd4: 2e 03 + 4bd6: f3 12 00 00 csrrw t0, ustatus, zero + 4bda: b7 ce 00 00 lui t4, 12 + 4bde: 12 c5 + 4be0: 0a 00 + 4be2: 00 01 + 4be4: 2e 03 + 4be6: f3 12 00 00 csrrw t0, ustatus, zero + 4bea: cb ce 00 00 fnmsub.s ft9, ft1, ft0, ft0, rmm + 4bee: 12 ec + 4bf0: 0a 00 + 4bf2: 00 01 + 4bf4: 2e 03 + 4bf6: f3 12 00 00 csrrw t0, ustatus, zero + 4bfa: df ce 00 00 + 4bfe: 12 da + 4c00: 0a 00 + 4c02: 00 01 + 4c04: 2e 03 + 4c06: f3 12 00 00 csrrw t0, ustatus, zero + 4c0a: f3 ce 00 00 + 4c0e: 12 01 + 4c10: 0b 00 00 01 + 4c14: 2e 03 + 4c16: 13 01 00 00 mv sp, zero + 4c1a: 13 cf 00 00 xori t5, ra, 0 + 4c1e: 00 00 + 4c20: 18 30 + 4c22: 29 01 + 4c24: 80 0c + 4c26: 00 00 + 4c28: 00 6a + 4c2a: 10 00 + 4c2c: 00 19 + 4c2e: 6e 0f + 4c30: 00 00 + 4c32: 01 2f + 4c34: 03 13 01 00 lh t1, 0(sp) + 4c38: 00 00 + 4c3a: 1b 7c 10 00 + 4c3e: 00 19 + 4c40: 6e 0f + 4c42: 00 00 + 4c44: 01 2f + 4c46: 03 13 01 00 lh t1, 0(sp) + 4c4a: 00 00 + 4c4c: 15 e8 + 4c4e: 0c 00 + 4c50: 00 96 + 4c52: 10 00 + 4c54: 00 12 + 4c56: 6e 0f + 4c58: 00 00 + 4c5a: 01 2f + 4c5c: 03 13 01 00 lh t1, 0(sp) + 4c60: 00 32 + 4c62: cf 00 00 00 fnmadd.s ft1, ft0, ft0, ft0, rne + 4c66: 15 00 + 4c68: 0d 00 + 4c6a: 00 e0 + 4c6c: 10 00 + 4c6e: 00 12 + 4c70: 93 0e 00 00 mv t4, zero + 4c74: 01 2f + 4c76: 03 f3 12 00 + 4c7a: 00 50 + 4c7c: cf 00 00 12 + 4c80: 33 0e 00 00 add t3, zero, zero + 4c84: 01 2f + 4c86: 03 f3 12 00 + 4c8a: 00 70 + 4c8c: cf 00 00 12 + 4c90: 47 0e 00 00 fmsub.s ft8, ft0, ft0, ft0, rne + 4c94: 01 2f + 4c96: 03 f3 12 00 + 4c9a: 00 90 + 4c9c: cf 00 00 12 + 4ca0: ec 0d + 4ca2: 00 00 + 4ca4: 01 2f + 4ca6: 03 f3 12 00 + 4caa: 00 b0 + 4cac: cf 00 00 00 fnmadd.s ft1, ft0, ft0, ft0, rne + 4cb0: 15 18 + 4cb2: 0d 00 + 4cb4: 00 d8 + 4cb6: 12 00 + 4cb8: 00 12 + 4cba: 59 09 + 4cbc: 00 00 + 4cbe: 01 2f + 4cc0: 03 25 00 00 lw a0, 0(zero) + 4cc4: 00 dc + 4cc6: cf 00 00 18 fnmadd.s ft1, ft0, ft0, ft3, rne + 4cca: 5c 2b + 4ccc: 01 80 + 4cce: 7c 00 + 4cd0: 00 00 + 4cd2: 85 11 + 4cd4: 00 00 + 4cd6: 19 74 + 4cd8: 09 00 + 4cda: 00 01 + 4cdc: 2f 03 f3 12 + 4ce0: 00 00 + 4ce2: 12 42 + 4ce4: 09 00 + 4ce6: 00 01 + 4ce8: 2f 03 f3 12 + 4cec: 00 00 + 4cee: 11 d0 + 4cf0: 00 00 + 4cf2: 12 76 + 4cf4: 0a 00 + 4cf6: 00 01 + 4cf8: 2f 03 f3 12 + 4cfc: 00 00 + 4cfe: 24 d0 + 4d00: 00 00 + 4d02: 12 f1 + 4d04: 0e 00 + 4d06: 00 01 + 4d08: 2f 03 fa 12 + 4d0c: 00 00 + 4d0e: 38 d0 + 4d10: 00 00 + 4d12: 18 98 + 4d14: 2b 01 80 08 + 4d18: 00 00 + 4d1a: 00 5c + 4d1c: 11 00 + 4d1e: 00 19 + 4d20: 6e 0f + 4d22: 00 00 + 4d24: 01 2f + 4d26: 03 13 01 00 lh t1, 0(sp) + 4d2a: 00 00 + 4d2c: 1b 6e 11 00 + 4d30: 00 19 + 4d32: 6e 0f + 4d34: 00 00 + 4d36: 01 2f + 4d38: 03 13 01 00 lh t1, 0(sp) + 4d3c: 00 00 + 4d3e: 17 30 0d 00 auipc zero, 211 + 4d42: 00 12 + 4d44: 6e 0f + 4d46: 00 00 + 4d48: 01 2f + 4d4a: 03 13 01 00 lh t1, 0(sp) + 4d4e: 00 cc + 4d50: d1 00 + 4d52: 00 00 + 4d54: 00 18 + 4d56: e8 2b + 4d58: 01 80 + 4d5a: 2c 01 + 4d5c: 00 00 + 4d5e: f9 11 + 4d60: 00 00 + 4d62: 12 9c + 4d64: 0a 00 + 4d66: 00 01 + 4d68: 2f 03 25 00 + 4d6c: 00 00 + 4d6e: ef d1 00 00 jal gp, 53248 + 4d72: 17 48 0d 00 auipc a6, 212 + 4d76: 00 12 + 4d78: 13 0b 00 00 mv s6, zero + 4d7c: 01 2f + 4d7e: 03 f3 12 00 + 4d82: 00 09 + 4d84: d2 00 + 4d86: 00 12 + 4d88: c5 0a + 4d8a: 00 00 + 4d8c: 01 2f + 4d8e: 03 f3 12 00 + 4d92: 00 cb + 4d94: d2 00 + 4d96: 00 12 + 4d98: ec 0a + 4d9a: 00 00 + 4d9c: 01 2f + 4d9e: 03 f3 12 00 + 4da2: 00 75 + 4da4: d3 00 00 12 + 4da8: da 0a + 4daa: 00 00 + 4dac: 01 2f + 4dae: 03 f3 12 00 + 4db2: 00 37 + 4db4: d4 00 + 4db6: 00 12 + 4db8: 01 0b + 4dba: 00 00 + 4dbc: 01 2f + 4dbe: 03 13 01 00 lh t1, 0(sp) + 4dc2: 00 f7 + 4dc4: d4 00 + 4dc6: 00 00 + 4dc8: 00 18 + 4dca: 40 2d + 4dcc: 01 80 + 4dce: 30 00 + 4dd0: 00 00 + 4dd2: 17 12 00 00 auipc tp, 1 + 4dd6: 12 6e + 4dd8: 0f 00 00 01 fence w, unknown + 4ddc: 2f 03 13 01 + 4de0: 00 00 + 4de2: 16 d5 + 4de4: 00 00 + 4de6: 00 18 + 4de8: a4 2d + 4dea: 01 80 + 4dec: 34 00 + 4dee: 00 00 + 4df0: 35 12 + 4df2: 00 00 + 4df4: 12 6e + 4df6: 0f 00 00 01 fence w, unknown + 4dfa: 2f 03 13 01 + 4dfe: 00 00 + 4e00: 5d d5 + 4e02: 00 00 + 4e04: 00 15 + 4e06: 60 0d + 4e08: 00 00 + 4e0a: 4f 12 00 00 fnmadd.s ft4, ft0, ft0, ft0, rtz + 4e0e: 12 6e + 4e10: 0f 00 00 01 fence w, unknown + 4e14: 2f 03 13 01 + 4e18: 00 00 + 4e1a: a4 d5 + 4e1c: 00 00 + 4e1e: 00 18 + 4e20: 18 2e + 4e22: 01 80 + 4e24: 2c 00 + 4e26: 00 00 + 4e28: 91 12 + 4e2a: 00 00 + 4e2c: 19 93 + 4e2e: 0e 00 + 4e30: 00 01 + 4e32: 2f 03 f3 12 + 4e36: 00 00 + 4e38: 19 33 + 4e3a: 0e 00 + 4e3c: 00 01 + 4e3e: 2f 03 f3 12 + 4e42: 00 00 + 4e44: 19 47 + 4e46: 0e 00 + 4e48: 00 01 + 4e4a: 2f 03 f3 12 + 4e4e: 00 00 + 4e50: 12 ec + 4e52: 0d 00 + 4e54: 00 01 + 4e56: 2f 03 f3 12 + 4e5a: 00 00 + 4e5c: 05 d6 + 4e5e: 00 00 + 4e60: 00 18 + 4e62: a0 2e + 4e64: 01 80 + 4e66: 04 00 + 4e68: 00 00 + 4e6a: ab 12 00 00 + 4e6e: 19 6e + 4e70: 0f 00 00 01 fence w, unknown + 4e74: 2f 03 13 01 + 4e78: 00 00 + 4e7a: 00 18 + 4e7c: c4 2e + 4e7e: 01 80 + 4e80: 0c 00 + 4e82: 00 00 + 4e84: c9 12 + 4e86: 00 00 + 4e88: 12 6e + 4e8a: 0f 00 00 01 fence w, unknown + 4e8e: 2f 03 13 01 + 4e92: 00 00 + 4e94: 19 d6 + 4e96: 00 00 + 4e98: 00 1c + 4e9a: 19 6e + 4e9c: 0f 00 00 01 fence w, unknown + 4ea0: 2f 03 13 01 + 4ea4: 00 00 + 4ea6: 00 00 + 4ea8: 1a 70 + 4eaa: 2a 01 + 4eac: 80 2c + 4eae: 00 00 + 4eb0: 00 16 + 4eb2: 83 0d 00 00 lb s11, 0(zero) + 4eb6: 01 2f + 4eb8: 03 1a 01 00 lh s4, 0(sp) + 4ebc: 00 03 + 4ebe: 91 a0 + 4ec0: 7f 00 00 03 + 4ec4: 04 05 + 4ec6: f6 03 + 4ec8: 00 00 + 4eca: 06 13 + 4ecc: 01 00 + 4ece: 00 0a + 4ed0: 13 00 00 07 addi zero, zero, 112 + 4ed4: 53 00 00 00 fadd.s ft0, ft0, ft0, rne + 4ed8: 03 00 1d 13 lb zero, 305(s10) + 4edc: 01 00 + 4ede: 00 07 + 4ee0: 53 00 00 00 fadd.s ft0, ft0, ft0, rne + 4ee4: 07 00 00 60 + 4ee8: 0e 00 + 4eea: 00 04 + 4eec: 00 f9 + 4eee: 0e 00 + 4ef0: 00 04 + 4ef2: 01 c8 + 4ef4: 09 00 + 4ef6: 00 0c + 4ef8: fc 0f + 4efa: 00 00 + 4efc: d5 01 + 4efe: 00 00 + 4f00: f4 2e + 4f02: 01 80 + 4f04: c8 1a + 4f06: 00 00 + 4f08: 56 65 + 4f0a: 00 00 + 4f0c: 02 04 + 4f0e: 05 69 + 4f10: 6e 74 + 4f12: 00 03 + 4f14: 01 06 + 4f16: ad 06 + 4f18: 00 00 + 4f1a: 03 08 05 f1 lb a6, -240(a0) + 4f1e: 03 00 00 04 lb zero, 64(zero) + 4f22: b7 07 00 00 lui a5, 0 + 4f26: 02 4a + 4f28: 01 16 + 4f2a: 4c 00 + 4f2c: 00 00 + 4f2e: 05 3a + 4f30: 00 00 + 4f32: 00 03 + 4f34: 01 08 + 4f36: ab 06 00 00 + 4f3a: 03 04 07 d4 lb s0, -704(a4) + 4f3e: 02 00 + 4f40: 00 03 + 4f42: 08 07 + 4f44: ca 02 + 4f46: 00 00 + 4f48: 03 02 07 ea lb tp, -352(a4) + 4f4c: 02 00 + 4f4e: 00 06 + 4f50: 47 00 00 00 fmsub.s ft0, ft0, ft0, ft0, rne + 4f54: 78 00 + 4f56: 00 00 + 4f58: 07 53 00 00 + 4f5c: 00 ff + 4f5e: 00 05 + 4f60: 68 00 + 4f62: 00 00 + 4f64: 08 fd + 4f66: 02 00 + 4f68: 00 04 + 4f6a: 3c 16 + 4f6c: 78 00 + 4f6e: 00 00 + 4f70: 09 46 + 4f72: 0c 00 + 4f74: 00 03 + 4f76: 48 0f + 4f78: 95 00 + 4f7a: 00 00 + 4f7c: 03 10 04 c0 lh zero, -1024(s0) + 4f80: 00 00 + 4f82: 00 0a + 4f84: 10 03 + 4f86: 4f 03 06 01 fnmadd.s ft6, fa2, fa6, ft0, rne + 4f8a: 00 00 + 4f8c: 0b 60 08 00 + 4f90: 00 03 + 4f92: 59 13 + 4f94: 06 01 + 4f96: 00 00 + 4f98: 04 20 + 4f9a: 00 00 + 4f9c: 0b 66 08 00 + 4fa0: 00 03 + 4fa2: 5a 13 + 4fa4: 06 01 + 4fa6: 00 00 + 4fa8: 04 20 + 4faa: 00 04 + 4fac: 0b 3a 0c 00 + 4fb0: 00 03 + 4fb2: 5b 13 06 01 + 4fb6: 00 00 + 4fb8: 04 20 + 4fba: 00 08 + 4fbc: 0b 40 0c 00 + 4fc0: 00 03 + 4fc2: 5c 13 + 4fc4: 06 01 + 4fc6: 00 00 + 4fc8: 04 10 + 4fca: 10 0c + 4fcc: 0c 65 + 4fce: 78 70 + 4fd0: 00 03 + 4fd2: 5d 0e + 4fd4: 53 00 00 00 fadd.s ft0, ft0, ft0, rne + 4fd8: 04 0f + 4fda: 01 0c + 4fdc: 0b 41 02 00 + 4fe0: 00 03 + 4fe2: 5e 0e + 4fe4: 53 00 00 00 fadd.s ft0, ft0, ft0, rne + 4fe8: 04 01 + 4fea: 00 0c + 4fec: 00 03 + 4fee: 04 07 + 4ff0: cf 02 00 00 fnmadd.s ft5, ft0, ft0, ft0, rne + 4ff4: 0d 74 + 4ff6: 0c 00 + 4ff8: 00 10 + 4ffa: 03 4c 07 33 lbu s8, 816(a4) + 4ffe: 01 00 + 5000: 00 0e + 5002: 66 6c + 5004: 74 00 + 5006: 03 4e 0a 89 lbu t3, -1904(s4) + 500a: 00 00 + 500c: 00 0f + 500e: 8d 0a + 5010: 00 00 + 5012: 03 60 05 9c + 5016: 00 00 + 5018: 00 00 + 501a: 10 a4 + 501c: 0f 00 00 01 fence w, unknown + 5020: 23 01 89 00 sb s0, 2(s2) + 5024: 00 00 + 5026: f4 2e + 5028: 01 80 + 502a: c8 1a + 502c: 00 00 + 502e: 01 9c + 5030: 40 0e + 5032: 00 00 + 5034: 11 61 + 5036: 00 01 + 5038: 23 12 89 00 sh s0, 4(s2) + 503c: 00 00 + 503e: 11 62 + 5040: 00 01 + 5042: 23 1c 89 00 sh s0, 24(s2) + 5046: 00 00 + 5048: 12 f2 + 504a: 08 00 + 504c: 00 01 + 504e: 25 03 + 5050: 25 00 + 5052: 00 00 + 5054: 2d d6 + 5056: 00 00 + 5058: 12 92 + 505a: 0a 00 + 505c: 00 01 + 505e: 25 03 + 5060: 25 00 + 5062: 00 00 + 5064: 77 d8 00 00 + 5068: 13 41 5f 63 xori sp, t5, 1589 + 506c: 00 01 + 506e: 26 03 + 5070: 40 0e + 5072: 00 00 + 5074: 14 41 + 5076: 5f 73 00 01 + 507a: 26 03 + 507c: 40 0e + 507e: 00 00 + 5080: 95 d8 + 5082: 00 00 + 5084: 14 41 + 5086: 5f 65 00 01 + 508a: 26 03 + 508c: 40 0e + 508e: 00 00 + 5090: 6e d9 + 5092: 00 00 + 5094: 15 41 + 5096: 5f 66 00 01 + 509a: 26 03 + 509c: 47 0e 00 00 fmsub.s ft8, ft0, ft0, ft0, rne + 50a0: 03 91 90 7f lh sp, 2041(ra) + 50a4: 13 42 5f 63 xori tp, t5, 1589 + 50a8: 00 01 + 50aa: 27 03 40 0e + 50ae: 00 00 + 50b0: 14 42 + 50b2: 5f 73 00 01 + 50b6: 27 03 40 0e + 50ba: 00 00 + 50bc: 22 db + 50be: 00 00 + 50c0: 14 42 + 50c2: 5f 65 00 01 + 50c6: 27 03 40 0e + 50ca: 00 00 + 50cc: b3 db 00 00 srl s7, ra, zero + 50d0: 15 42 + 50d2: 5f 66 00 01 + 50d6: 27 03 47 0e + 50da: 00 00 + 50dc: 03 91 a0 7f lh sp, 2042(ra) + 50e0: 14 52 + 50e2: 5f 63 00 01 + 50e6: 28 03 + 50e8: 40 0e + 50ea: 00 00 + 50ec: 96 dd + 50ee: 00 00 + 50f0: 14 52 + 50f2: 5f 73 00 01 + 50f6: 28 03 + 50f8: 40 0e + 50fa: 00 00 + 50fc: b6 dd + 50fe: 00 00 + 5100: 14 52 + 5102: 5f 65 00 01 + 5106: 28 03 + 5108: 40 0e + 510a: 00 00 + 510c: d5 de + 510e: 00 00 + 5110: 15 52 + 5112: 5f 66 00 01 + 5116: 28 03 + 5118: 47 0e 00 00 fmsub.s ft8, ft0, ft0, ft0, rne + 511c: 03 91 b0 7f lh sp, 2043(ra) + 5120: 14 72 + 5122: 00 01 + 5124: 29 0a + 5126: 89 00 + 5128: 00 00 + 512a: 3b e1 00 00 + 512e: 16 78 + 5130: 0d 00 + 5132: 00 60 + 5134: 02 00 + 5136: 00 17 + 5138: f8 0b + 513a: 00 00 + 513c: 01 2c + 513e: 03 0d 01 00 lb s10, 0(sp) + 5142: 00 02 + 5144: 91 40 + 5146: 00 16 + 5148: 98 0d + 514a: 00 00 + 514c: a1 02 + 514e: 00 00 + 5150: 18 81 + 5152: 0f 00 00 01 fence w, unknown + 5156: 2c 03 + 5158: 40 0e + 515a: 00 00 + 515c: 03 18 bc 0d lh a6, 219(s8) + 5160: 00 00 + 5162: 01 2c + 5164: 03 40 0e 00 lbu zero, 0(t3) + 5168: 00 1d + 516a: 18 a8 + 516c: 0d 00 + 516e: 00 01 + 5170: 2c 03 + 5172: 40 0e + 5174: 00 00 + 5176: 00 12 + 5178: 0e 0e + 517a: 00 00 + 517c: 01 2c + 517e: 03 40 0e 00 lbu zero, 0(t3) + 5182: 00 59 + 5184: e1 00 + 5186: 00 00 + 5188: 16 b8 + 518a: 0d 00 + 518c: 00 ba + 518e: 02 00 + 5190: 00 17 + 5192: f8 0b + 5194: 00 00 + 5196: 01 2d + 5198: 03 0d 01 00 lb s10, 0(sp) + 519c: 00 02 + 519e: 91 40 + 51a0: 00 16 + 51a2: f8 0d + 51a4: 00 00 + 51a6: fb 02 00 00 + 51aa: 18 81 + 51ac: 0f 00 00 01 fence w, unknown + 51b0: 2d 03 + 51b2: 40 0e + 51b4: 00 00 + 51b6: 03 18 bc 0d lh a6, 219(s8) + 51ba: 00 00 + 51bc: 01 2d + 51be: 03 40 0e 00 lbu zero, 0(t3) + 51c2: 00 1d + 51c4: 18 a8 + 51c6: 0d 00 + 51c8: 00 01 + 51ca: 2d 03 + 51cc: 40 0e + 51ce: 00 00 + 51d0: 00 12 + 51d2: 0e 0e + 51d4: 00 00 + 51d6: 01 2d + 51d8: 03 40 0e 00 lbu zero, 0(t3) + 51dc: 00 7a + 51de: e1 00 + 51e0: 00 00 + 51e2: 16 10 + 51e4: 0e 00 + 51e6: 00 21 + 51e8: 07 00 00 19 + 51ec: f5 10 + 51ee: 00 00 + 51f0: 01 2e + 51f2: 03 b8 31 01 + 51f6: 80 19 + 51f8: 78 10 + 51fa: 00 00 + 51fc: 01 2e + 51fe: 03 54 35 01 lhu s0, 19(a0) + 5202: 80 19 + 5204: fa 10 + 5206: 00 00 + 5208: 01 2e + 520a: 03 3c 33 01 + 520e: 80 19 + 5210: d4 0f + 5212: 00 00 + 5214: 01 2e + 5216: 03 54 34 01 lhu s0, 19(s0) + 521a: 80 12 + 521c: c2 10 + 521e: 00 00 + 5220: 01 2e + 5222: 03 25 00 00 lw a0, 0(zero) + 5226: 00 9b + 5228: e1 00 + 522a: 00 1a + 522c: c0 30 + 522e: 01 80 + 5230: 48 00 + 5232: 00 00 + 5234: 7e 03 + 5236: 00 00 + 5238: 1b 3f 10 00 + 523c: 00 01 + 523e: 2e 03 + 5240: 06 01 + 5242: 00 00 + 5244: 12 52 + 5246: 10 00 + 5248: 00 01 + 524a: 2e 03 + 524c: 06 01 + 524e: 00 00 + 5250: 5d e3 + 5252: 00 00 + 5254: 12 65 + 5256: 10 00 + 5258: 00 01 + 525a: 2e 03 + 525c: 06 01 + 525e: 00 00 + 5260: 8d e3 + 5262: 00 00 + 5264: 00 1a + 5266: c8 31 + 5268: 01 80 + 526a: 14 01 + 526c: 00 00 + 526e: f2 03 + 5270: 00 00 + 5272: 12 9c + 5274: 0a 00 + 5276: 00 01 + 5278: 2e 03 + 527a: 25 00 + 527c: 00 00 + 527e: ce e3 + 5280: 00 00 + 5282: 1c f0 + 5284: 0e 00 + 5286: 00 12 + 5288: 13 0b 00 00 mv s6, zero + 528c: 01 2e + 528e: 03 40 0e 00 lbu zero, 0(t3) + 5292: 00 e8 + 5294: e3 00 00 12 beqz zero, 2336 + 5298: c5 0a + 529a: 00 00 + 529c: 01 2e + 529e: 03 40 0e 00 lbu zero, 0(t3) + 52a2: 00 14 + 52a4: e4 00 + 52a6: 00 12 + 52a8: ec 0a + 52aa: 00 00 + 52ac: 01 2e + 52ae: 03 40 0e 00 lbu zero, 0(t3) + 52b2: 00 3a + 52b4: e4 00 + 52b6: 00 12 + 52b8: da 0a + 52ba: 00 00 + 52bc: 01 2e + 52be: 03 40 0e 00 lbu zero, 0(t3) + 52c2: 00 63 + 52c4: e4 00 + 52c6: 00 12 + 52c8: 01 0b + 52ca: 00 00 + 52cc: 01 2e + 52ce: 03 06 01 00 lb a2, 0(sp) + 52d2: 00 0d + 52d4: e5 00 + 52d6: 00 00 + 52d8: 00 1a + 52da: e0 32 + 52dc: 01 80 + 52de: 58 00 + 52e0: 00 00 + 52e2: 30 04 + 52e4: 00 00 + 52e6: 12 3f + 52e8: 10 00 + 52ea: 00 01 + 52ec: 2e 03 + 52ee: 06 01 + 52f0: 00 00 + 52f2: 2c e5 + 52f4: 00 00 + 52f6: 12 52 + 52f8: 10 00 + 52fa: 00 01 + 52fc: 2e 03 + 52fe: 06 01 + 5300: 00 00 + 5302: 5a e5 + 5304: 00 00 + 5306: 12 65 + 5308: 10 00 + 530a: 00 01 + 530c: 2e 03 + 530e: 06 01 + 5310: 00 00 + 5312: c2 e5 + 5314: 00 00 + 5316: 00 1a + 5318: 68 34 + 531a: 01 80 + 531c: 4c 00 + 531e: 00 00 + 5320: 64 04 + 5322: 00 00 + 5324: 1b 3f 10 00 + 5328: 00 01 + 532a: 2e 03 + 532c: 06 01 + 532e: 00 00 + 5330: 17 52 10 00 auipc tp, 261 + 5334: 00 01 + 5336: 2e 03 + 5338: 06 01 + 533a: 00 00 + 533c: 01 5c + 533e: 1b 65 10 00 + 5342: 00 01 + 5344: 2e 03 + 5346: 06 01 + 5348: 00 00 + 534a: 00 1a + 534c: 64 35 + 534e: 01 80 + 5350: 28 01 + 5352: 00 00 + 5354: d8 04 + 5356: 00 00 + 5358: 12 9c + 535a: 0a 00 + 535c: 00 01 + 535e: 2e 03 + 5360: 25 00 + 5362: 00 00 + 5364: 29 e6 + 5366: 00 00 + 5368: 1c 40 + 536a: 0f 00 00 12 + 536e: 13 0b 00 00 mv s6, zero + 5372: 01 2e + 5374: 03 40 0e 00 lbu zero, 0(t3) + 5378: 00 43 + 537a: e6 00 + 537c: 00 12 + 537e: c5 0a + 5380: 00 00 + 5382: 01 2e + 5384: 03 40 0e 00 lbu zero, 0(t3) + 5388: 00 79 + 538a: e6 00 + 538c: 00 12 + 538e: ec 0a + 5390: 00 00 + 5392: 01 2e + 5394: 03 40 0e 00 lbu zero, 0(t3) + 5398: 00 a9 + 539a: e6 00 + 539c: 00 12 + 539e: da 0a + 53a0: 00 00 + 53a2: 01 2e + 53a4: 03 40 0e 00 lbu zero, 0(t3) + 53a8: 00 d2 + 53aa: e6 00 + 53ac: 00 12 + 53ae: 01 0b + 53b0: 00 00 + 53b2: 01 2e + 53b4: 03 06 01 00 lb a2, 0(sp) + 53b8: 00 7c + 53ba: e7 00 00 00 jalr zero + 53be: 00 1a + 53c0: 90 36 + 53c2: 01 80 + 53c4: 58 00 + 53c6: 00 00 + 53c8: 16 05 + 53ca: 00 00 + 53cc: 12 3f + 53ce: 10 00 + 53d0: 00 01 + 53d2: 2e 03 + 53d4: 06 01 + 53d6: 00 00 + 53d8: 9b e7 00 00 + 53dc: 12 52 + 53de: 10 00 + 53e0: 00 01 + 53e2: 2e 03 + 53e4: 06 01 + 53e6: 00 00 + 53e8: ca e7 + 53ea: 00 00 + 53ec: 12 65 + 53ee: 10 00 + 53f0: 00 01 + 53f2: 2e 03 + 53f4: 06 01 + 53f6: 00 00 + 53f8: 4e e8 + 53fa: 00 00 + 53fc: 00 16 + 53fe: 58 0f + 5400: 00 00 + 5402: 4c 05 + 5404: 00 00 + 5406: 12 3f + 5408: 10 00 + 540a: 00 01 + 540c: 2e 03 + 540e: 06 01 + 5410: 00 00 + 5412: b5 e8 + 5414: 00 00 + 5416: 12 52 + 5418: 10 00 + 541a: 00 01 + 541c: 2e 03 + 541e: 06 01 + 5420: 00 00 + 5422: e3 e8 00 00 bltu ra, zero, 2064 + 5426: 1b 65 10 00 + 542a: 00 01 + 542c: 2e 03 + 542e: 06 01 + 5430: 00 00 + 5432: 00 1d + 5434: 82 05 + 5436: 00 00 + 5438: 1b 93 0e 00 + 543c: 00 01 + 543e: 2e 03 + 5440: 40 0e + 5442: 00 00 + 5444: 1b 33 0e 00 + 5448: 00 01 + 544a: 2e 03 + 544c: 40 0e + 544e: 00 00 + 5450: 1b 47 0e 00 + 5454: 00 01 + 5456: 2e 03 + 5458: 40 0e + 545a: 00 00 + 545c: 1b ec 0d 00 + 5460: 00 01 + 5462: 2e 03 + 5464: 40 0e + 5466: 00 00 + 5468: 00 1d + 546a: b8 05 + 546c: 00 00 + 546e: 1b 93 0e 00 + 5472: 00 01 + 5474: 2e 03 + 5476: 40 0e + 5478: 00 00 + 547a: 1b 33 0e 00 + 547e: 00 01 + 5480: 2e 03 + 5482: 40 0e + 5484: 00 00 + 5486: 1b 47 0e 00 + 548a: 00 01 + 548c: 2e 03 + 548e: 40 0e + 5490: 00 00 + 5492: 1b ec 0d 00 + 5496: 00 01 + 5498: 2e 03 + 549a: 40 0e + 549c: 00 00 + 549e: 00 1a + 54a0: 70 3a + 54a2: 01 80 + 54a4: 28 00 + 54a6: 00 00 + 54a8: 06 06 + 54aa: 00 00 + 54ac: 12 81 + 54ae: 0f 00 00 01 fence w, unknown + 54b2: 2e 03 + 54b4: 40 0e + 54b6: 00 00 + 54b8: 06 e9 + 54ba: 00 00 + 54bc: 12 bc + 54be: 0d 00 + 54c0: 00 01 + 54c2: 2e 03 + 54c4: 40 0e + 54c6: 00 00 + 54c8: 1a e9 + 54ca: 00 00 + 54cc: 12 a8 + 54ce: 0d 00 + 54d0: 00 01 + 54d2: 2e 03 + 54d4: 40 0e + 54d6: 00 00 + 54d8: 2e e9 + 54da: 00 00 + 54dc: 12 0e + 54de: 0e 00 + 54e0: 00 01 + 54e2: 2e 03 + 54e4: 40 0e + 54e6: 00 00 + 54e8: 42 e9 + 54ea: 00 00 + 54ec: 00 1a + 54ee: 00 3b + 54f0: 01 80 + 54f2: 48 00 + 54f4: 00 00 + 54f6: 44 06 + 54f8: 00 00 + 54fa: 12 3f + 54fc: 10 00 + 54fe: 00 01 + 5500: 2e 03 + 5502: 06 01 + 5504: 00 00 + 5506: 56 e9 + 5508: 00 00 + 550a: 12 52 + 550c: 10 00 + 550e: 00 01 + 5510: 2e 03 + 5512: 06 01 + 5514: 00 00 + 5516: fb e9 00 00 + 551a: 12 65 + 551c: 10 00 + 551e: 00 01 + 5520: 2e 03 + 5522: 06 01 + 5524: 00 00 + 5526: 4e eb + 5528: 00 00 + 552a: 00 16 + 552c: 70 0f + 552e: 00 00 + 5530: b4 06 + 5532: 00 00 + 5534: 12 9c + 5536: 0a 00 + 5538: 00 01 + 553a: 2e 03 + 553c: 25 00 + 553e: 00 00 + 5540: 91 eb + 5542: 00 00 + 5544: 1c 70 + 5546: 0f 00 00 12 + 554a: 13 0b 00 00 mv s6, zero + 554e: 01 2e + 5550: 03 40 0e 00 lbu zero, 0(t3) + 5554: 00 bd + 5556: eb 00 00 12 vx_tex ra, zero, zero, sp, rne + 555a: c5 0a + 555c: 00 00 + 555e: 01 2e + 5560: 03 40 0e 00 lbu zero, 0(t3) + 5564: 00 e9 + 5566: eb 00 00 12 vx_tex ra, zero, zero, sp, rne + 556a: ec 0a + 556c: 00 00 + 556e: 01 2e + 5570: 03 40 0e 00 lbu zero, 0(t3) + 5574: 00 15 + 5576: ec 00 + 5578: 00 12 + 557a: da 0a + 557c: 00 00 + 557e: 01 2e + 5580: 03 40 0e 00 lbu zero, 0(t3) + 5584: 00 41 + 5586: ec 00 + 5588: 00 12 + 558a: 01 0b + 558c: 00 00 + 558e: 01 2e + 5590: 03 06 01 00 lb a2, 0(sp) + 5594: 00 15 + 5596: ec 00 + 5598: 00 00 + 559a: 00 1c + 559c: 08 0f + 559e: 00 00 + 55a0: 12 9c + 55a2: 0a 00 + 55a4: 00 01 + 55a6: 2e 03 + 55a8: 25 00 + 55aa: 00 00 + 55ac: 79 ec + 55ae: 00 00 + 55b0: 1c 20 + 55b2: 0f 00 00 12 + 55b6: 13 0b 00 00 mv s6, zero + 55ba: 01 2e + 55bc: 03 40 0e 00 lbu zero, 0(t3) + 55c0: 00 93 + 55c2: ec 00 + 55c4: 00 12 + 55c6: c5 0a + 55c8: 00 00 + 55ca: 01 2e + 55cc: 03 40 0e 00 lbu zero, 0(t3) + 55d0: 00 b3 + 55d2: ec 00 + 55d4: 00 12 + 55d6: ec 0a + 55d8: 00 00 + 55da: 01 2e + 55dc: 03 40 0e 00 lbu zero, 0(t3) + 55e0: 00 d3 + 55e2: ec 00 + 55e4: 00 12 + 55e6: da 0a + 55e8: 00 00 + 55ea: 01 2e + 55ec: 03 40 0e 00 lbu zero, 0(t3) + 55f0: 00 f3 + 55f2: ec 00 + 55f4: 00 12 + 55f6: 01 0b + 55f8: 00 00 + 55fa: 01 2e + 55fc: 03 06 01 00 lb a2, 0(sp) + 5600: 00 1f + 5602: ed 00 + 5604: 00 00 + 5606: 00 00 + 5608: 16 88 + 560a: 0f 00 00 9b + 560e: 0c 00 + 5610: 00 19 + 5612: f7 0f 00 00 + 5616: 01 2e + 5618: 03 6c 3d 01 + 561c: 80 19 + 561e: dd 0f + 5620: 00 00 + 5622: 01 2e + 5624: 03 a8 40 01 lw a6, 20(ra) + 5628: 80 19 + 562a: bd 10 + 562c: 00 00 + 562e: 01 2e + 5630: 03 04 3f 01 lb s0, 19(t5) + 5634: 80 19 + 5636: ff 10 00 00 + 563a: 01 2e + 563c: 03 8c 45 01 lb s8, 20(a1) + 5640: 80 19 + 5642: d9 10 + 5644: 00 00 + 5646: 01 2e + 5648: 03 54 34 01 lhu s0, 19(s0) + 564c: 80 12 + 564e: c2 10 + 5650: 00 00 + 5652: 01 2e + 5654: 03 25 00 00 lw a0, 0(zero) + 5658: 00 3e + 565a: ed 00 + 565c: 00 1a + 565e: 74 3c + 5660: 01 80 + 5662: 5c 00 + 5664: 00 00 + 5666: c4 07 + 5668: 00 00 + 566a: 12 c0 + 566c: 0f 00 00 01 fence w, unknown + 5670: 2e 03 + 5672: 57 0e 00 00 + 5676: 29 ef + 5678: 00 00 + 567a: 12 e2 + 567c: 10 00 + 567e: 00 01 + 5680: 2e 03 + 5682: 06 01 + 5684: 00 00 + 5686: 8a ef + 5688: 00 00 + 568a: 12 1d + 568c: 11 00 + 568e: 00 01 + 5690: 2e 03 + 5692: 06 01 + 5694: 00 00 + 5696: c9 ef + 5698: 00 00 + 569a: 12 ad + 569c: 0f 00 00 01 fence w, unknown + 56a0: 2e 03 + 56a2: 06 01 + 56a4: 00 00 + 56a6: f3 ef 00 00 csrrsi t6, ustatus, 1 + 56aa: 00 1a + 56ac: 78 3d + 56ae: 01 80 + 56b0: 14 01 + 56b2: 00 00 + 56b4: 38 08 + 56b6: 00 00 + 56b8: 12 9c + 56ba: 0a 00 + 56bc: 00 01 + 56be: 2e 03 + 56c0: 25 00 + 56c2: 00 00 + 56c4: 21 f0 + 56c6: 00 00 + 56c8: 1c 58 + 56ca: 10 00 + 56cc: 00 12 + 56ce: 13 0b 00 00 mv s6, zero + 56d2: 01 2e + 56d4: 03 40 0e 00 lbu zero, 0(t3) + 56d8: 00 3b + 56da: f0 00 + 56dc: 00 12 + 56de: c5 0a + 56e0: 00 00 + 56e2: 01 2e + 56e4: 03 40 0e 00 lbu zero, 0(t3) + 56e8: 00 67 + 56ea: f0 00 + 56ec: 00 12 + 56ee: ec 0a + 56f0: 00 00 + 56f2: 01 2e + 56f4: 03 40 0e 00 lbu zero, 0(t3) + 56f8: 00 8d + 56fa: f0 00 + 56fc: 00 12 + 56fe: da 0a + 5700: 00 00 + 5702: 01 2e + 5704: 03 40 0e 00 lbu zero, 0(t3) + 5708: 00 b6 + 570a: f0 00 + 570c: 00 12 + 570e: 01 0b + 5710: 00 00 + 5712: 01 2e + 5714: 03 06 01 00 lb a2, 0(sp) + 5718: 00 60 + 571a: f1 00 + 571c: 00 00 + 571e: 00 1a + 5720: 90 3e + 5722: 01 80 + 5724: 70 00 + 5726: 00 00 + 5728: 86 08 + 572a: 00 00 + 572c: 12 c0 + 572e: 0f 00 00 01 fence w, unknown + 5732: 2e 03 + 5734: 57 0e 00 00 + 5738: 7f f1 00 00 + 573c: 12 e2 + 573e: 10 00 + 5740: 00 01 + 5742: 2e 03 + 5744: 06 01 + 5746: 00 00 + 5748: e0 f1 + 574a: 00 00 + 574c: 12 1d + 574e: 11 00 + 5750: 00 01 + 5752: 2e 03 + 5754: 06 01 + 5756: 00 00 + 5758: 1f f2 00 00 + 575c: 12 ad + 575e: 0f 00 00 01 fence w, unknown + 5762: 2e 03 + 5764: 06 01 + 5766: 00 00 + 5768: 49 f2 + 576a: 00 00 + 576c: 00 1a + 576e: a4 3f + 5770: 01 80 + 5772: 5c 00 + 5774: 00 00 + 5776: d4 08 + 5778: 00 00 + 577a: 12 c0 + 577c: 0f 00 00 01 fence w, unknown + 5780: 2e 03 + 5782: 57 0e 00 00 + 5786: 77 f2 00 00 + 578a: 12 e2 + 578c: 10 00 + 578e: 00 01 + 5790: 2e 03 + 5792: 06 01 + 5794: 00 00 + 5796: d8 f2 + 5798: 00 00 + 579a: 12 1d + 579c: 11 00 + 579e: 00 01 + 57a0: 2e 03 + 57a2: 06 01 + 57a4: 00 00 + 57a6: 18 f3 + 57a8: 00 00 + 57aa: 12 ad + 57ac: 0f 00 00 01 fence w, unknown + 57b0: 2e 03 + 57b2: 06 01 + 57b4: 00 00 + 57b6: 42 f3 + 57b8: 00 00 + 57ba: 00 1a + 57bc: b0 40 + 57be: 01 80 + 57c0: 2c 01 + 57c2: 00 00 + 57c4: 48 09 + 57c6: 00 00 + 57c8: 12 9c + 57ca: 0a 00 + 57cc: 00 01 + 57ce: 2e 03 + 57d0: 25 00 + 57d2: 00 00 + 57d4: 70 f3 + 57d6: 00 00 + 57d8: 1c e0 + 57da: 10 00 + 57dc: 00 12 + 57de: 13 0b 00 00 mv s6, zero + 57e2: 01 2e + 57e4: 03 40 0e 00 lbu zero, 0(t3) + 57e8: 00 8a + 57ea: f3 00 00 12 + 57ee: c5 0a + 57f0: 00 00 + 57f2: 01 2e + 57f4: 03 40 0e 00 lbu zero, 0(t3) + 57f8: 00 c0 + 57fa: f3 00 00 12 + 57fe: ec 0a + 5800: 00 00 + 5802: 01 2e + 5804: 03 40 0e 00 lbu zero, 0(t3) + 5808: 00 f0 + 580a: f3 00 00 12 + 580e: da 0a + 5810: 00 00 + 5812: 01 2e + 5814: 03 40 0e 00 lbu zero, 0(t3) + 5818: 00 19 + 581a: f4 00 + 581c: 00 12 + 581e: 01 0b + 5820: 00 00 + 5822: 01 2e + 5824: 03 06 01 00 lb a2, 0(sp) + 5828: 00 c3 + 582a: f4 00 + 582c: 00 00 + 582e: 00 1a + 5830: e0 41 + 5832: 01 80 + 5834: 70 00 + 5836: 00 00 + 5838: 96 09 + 583a: 00 00 + 583c: 12 c0 + 583e: 0f 00 00 01 fence w, unknown + 5842: 2e 03 + 5844: 57 0e 00 00 + 5848: e2 f4 + 584a: 00 00 + 584c: 12 e2 + 584e: 10 00 + 5850: 00 01 + 5852: 2e 03 + 5854: 06 01 + 5856: 00 00 + 5858: 43 f5 00 00 fmadd.s fa0, ft1, ft0, ft0 + 585c: 12 1d + 585e: 11 00 + 5860: 00 01 + 5862: 2e 03 + 5864: 06 01 + 5866: 00 00 + 5868: 83 f5 00 00 + 586c: 12 ad + 586e: 0f 00 00 01 fence w, unknown + 5872: 2e 03 + 5874: 06 01 + 5876: 00 00 + 5878: ad f5 + 587a: 00 00 + 587c: 00 1a + 587e: ec 42 + 5880: 01 80 + 5882: 58 00 + 5884: 00 00 + 5886: e4 09 + 5888: 00 00 + 588a: 12 c0 + 588c: 0f 00 00 01 fence w, unknown + 5890: 2e 03 + 5892: 57 0e 00 00 + 5896: db f5 00 00 + 589a: 12 e2 + 589c: 10 00 + 589e: 00 01 + 58a0: 2e 03 + 58a2: 06 01 + 58a4: 00 00 + 58a6: 92 f6 + 58a8: 00 00 + 58aa: 12 1d + 58ac: 11 00 + 58ae: 00 01 + 58b0: 2e 03 + 58b2: 06 01 + 58b4: 00 00 + 58b6: 47 f7 00 00 fmsub.s fa4, ft1, ft0, ft0 + 58ba: 12 ad + 58bc: 0f 00 00 01 fence w, unknown + 58c0: 2e 03 + 58c2: 06 01 + 58c4: 00 00 + 58c6: 71 f7 + 58c8: 00 00 + 58ca: 00 1a + 58cc: 4c 43 + 58ce: 01 80 + 58d0: 58 00 + 58d2: 00 00 + 58d4: 32 0a + 58d6: 00 00 + 58d8: 12 c0 + 58da: 0f 00 00 01 fence w, unknown + 58de: 2e 03 + 58e0: 57 0e 00 00 + 58e4: 9f f7 00 00 + 58e8: 12 e2 + 58ea: 10 00 + 58ec: 00 01 + 58ee: 2e 03 + 58f0: 06 01 + 58f2: 00 00 + 58f4: 00 f8 + 58f6: 00 00 + 58f8: 12 1d + 58fa: 11 00 + 58fc: 00 01 + 58fe: 2e 03 + 5900: 06 01 + 5902: 00 00 + 5904: 23 f8 00 00 + 5908: 12 ad + 590a: 0f 00 00 01 fence w, unknown + 590e: 2e 03 + 5910: 06 01 + 5912: 00 00 + 5914: 42 f8 + 5916: 00 00 + 5918: 00 16 + 591a: f8 10 + 591c: 00 00 + 591e: 7c 0a + 5920: 00 00 + 5922: 12 81 + 5924: 0f 00 00 01 fence w, unknown + 5928: 2e 03 + 592a: 40 0e + 592c: 00 00 + 592e: 70 f8 + 5930: 00 00 + 5932: 12 bc + 5934: 0d 00 + 5936: 00 01 + 5938: 2e 03 + 593a: 40 0e + 593c: 00 00 + 593e: 84 f8 + 5940: 00 00 + 5942: 12 a8 + 5944: 0d 00 + 5946: 00 01 + 5948: 2e 03 + 594a: 40 0e + 594c: 00 00 + 594e: 98 f8 + 5950: 00 00 + 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12 bc + 59ea: 0d 00 + 59ec: 00 01 + 59ee: 2e 03 + 59f0: 40 0e + 59f2: 00 00 + 59f4: e1 f8 + 59f6: 00 00 + 59f8: 12 a8 + 59fa: 0d 00 + 59fc: 00 01 + 59fe: 2e 03 + 5a00: 40 0e + 5a02: 00 00 + 5a04: f5 f8 + 5a06: 00 00 + 5a08: 12 0e + 5a0a: 0e 00 + 5a0c: 00 01 + 5a0e: 2e 03 + 5a10: 40 0e + 5a12: 00 00 + 5a14: 09 f9 + 5a16: 00 00 + 5a18: 00 1a + 5a1a: d4 44 + 5a1c: 01 80 + 5a1e: 58 00 + 5a20: 00 00 + 5a22: 80 0b + 5a24: 00 00 + 5a26: 12 c0 + 5a28: 0f 00 00 01 fence w, unknown + 5a2c: 2e 03 + 5a2e: 57 0e 00 00 + 5a32: 2a f9 + 5a34: 00 00 + 5a36: 12 e2 + 5a38: 10 00 + 5a3a: 00 01 + 5a3c: 2e 03 + 5a3e: 06 01 + 5a40: 00 00 + 5a42: e1 f9 + 5a44: 00 00 + 5a46: 12 1d + 5a48: 11 00 + 5a4a: 00 01 + 5a4c: 2e 03 + 5a4e: 06 01 + 5a50: 00 00 + 5a52: 96 fa + 5a54: 00 00 + 5a56: 12 ad + 5a58: 0f 00 00 01 fence w, unknown + 5a5c: 2e 03 + 5a5e: 06 01 + 5a60: 00 00 + 5a62: c0 fa + 5a64: 00 00 + 5a66: 00 1a + 5a68: 34 45 + 5a6a: 01 80 + 5a6c: 54 00 + 5a6e: 00 00 + 5a70: ce 0b + 5a72: 00 00 + 5a74: 12 c0 + 5a76: 0f 00 00 01 fence w, unknown + 5a7a: 2e 03 + 5a7c: 57 0e 00 00 + 5a80: f9 fa + 5a82: 00 00 + 5a84: 12 e2 + 5a86: 10 00 + 5a88: 00 01 + 5a8a: 2e 03 + 5a8c: 06 01 + 5a8e: 00 00 + 5a90: 5a fb + 5a92: 00 00 + 5a94: 12 1d + 5a96: 11 00 + 5a98: 00 01 + 5a9a: 2e 03 + 5a9c: 06 01 + 5a9e: 00 00 + 5aa0: 7d fb + 5aa2: 00 00 + 5aa4: 12 ad + 5aa6: 0f 00 00 01 fence w, unknown + 5aaa: 2e 03 + 5aac: 06 01 + 5aae: 00 00 + 5ab0: 9c fb + 5ab2: 00 00 + 5ab4: 00 1c + 5ab6: 70 10 + 5ab8: 00 00 + 5aba: 12 a7 + 5abc: 10 00 + 5abe: 00 01 + 5ac0: 2e 03 + 5ac2: 25 00 + 5ac4: 00 00 + 5ac6: ca fb + 5ac8: 00 00 + 5aca: 16 90 + 5acc: 10 00 + 5ace: 00 2d + 5ad0: 0c 00 + 5ad2: 00 12 + 5ad4: 81 0f + 5ad6: 00 00 + 5ad8: 01 2e + 5ada: 03 40 0e 00 lbu zero, 0(t3) + 5ade: 00 35 + 5ae0: fc 00 + 5ae2: 00 12 + 5ae4: bc 0d + 5ae6: 00 00 + 5ae8: 01 2e + 5aea: 03 40 0e 00 lbu zero, 0(t3) + 5aee: 00 b7 + 5af0: fc 00 + 5af2: 00 12 + 5af4: a8 0d + 5af6: 00 00 + 5af8: 01 2e + 5afa: 03 40 0e 00 lbu zero, 0(t3) + 5afe: 00 52 + 5b00: fd 00 + 5b02: 00 12 + 5b04: 0e 0e + 5b06: 00 00 + 5b08: 01 2e + 5b0a: 03 40 0e 00 lbu zero, 0(t3) + 5b0e: 00 c5 + 5b10: fd 00 + 5b12: 00 00 + 5b14: 1c a8 + 5b16: 10 00 + 5b18: 00 12 + 5b1a: 9c 0a + 5b1c: 00 00 + 5b1e: 01 2e + 5b20: 03 25 00 00 lw a0, 0(zero) + 5b24: 00 11 + 5b26: fe 00 + 5b28: 00 1c + 5b2a: c0 10 + 5b2c: 00 00 + 5b2e: 12 13 + 5b30: 0b 00 00 01 + 5b34: 2e 03 + 5b36: 40 0e + 5b38: 00 00 + 5b3a: 2b fe 00 00 + 5b3e: 12 c5 + 5b40: 0a 00 + 5b42: 00 01 + 5b44: 2e 03 + 5b46: 40 0e + 5b48: 00 00 + 5b4a: 61 fe + 5b4c: 00 00 + 5b4e: 12 ec + 5b50: 0a 00 + 5b52: 00 01 + 5b54: 2e 03 + 5b56: 40 0e + 5b58: 00 00 + 5b5a: 91 fe + 5b5c: 00 00 + 5b5e: 12 da + 5b60: 0a 00 + 5b62: 00 01 + 5b64: 2e 03 + 5b66: 40 0e + 5b68: 00 00 + 5b6a: d0 fe + 5b6c: 00 00 + 5b6e: 12 01 + 5b70: 0b 00 00 01 + 5b74: 2e 03 + 5b76: 06 01 + 5b78: 00 00 + 5b7a: 6f ff 00 00 jal t5, 61440 + 5b7e: 00 00 + 5b80: 00 00 + 5b82: 16 18 + 5b84: 11 00 + 5b86: 00 26 + 5b88: 0e 00 + 5b8a: 00 12 + 5b8c: 04 11 + 5b8e: 00 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5c22: 2f 03 40 0e + 5c26: 00 00 + 5c28: 4d 00 + 5c2a: 01 00 + 5c2c: 00 1a + 5c2e: dc 37 + 5c30: 01 80 + 5c32: 08 00 + 5c34: 00 00 + 5c36: 60 0d + 5c38: 00 00 + 5c3a: 1b 6e 0f 00 + 5c3e: 00 01 + 5c40: 2f 03 06 01 + 5c44: 00 00 + 5c46: 00 1d + 5c48: 72 0d + 5c4a: 00 00 + 5c4c: 1b 6e 0f 00 + 5c50: 00 01 + 5c52: 2f 03 06 01 + 5c56: 00 00 + 5c58: 00 1c + 5c5a: 88 11 + 5c5c: 00 00 + 5c5e: 12 6e + 5c60: 0f 00 00 01 fence w, unknown + 5c64: 2f 03 06 01 + 5c68: 00 00 + 5c6a: 7b 00 01 00 + 5c6e: 00 00 + 5c70: 1a cc + 5c72: 38 01 + 5c74: 80 30 + 5c76: 00 00 + 5c78: 00 a7 + 5c7a: 0d 00 + 5c7c: 00 12 + 5c7e: 6e 0f + 5c80: 00 00 + 5c82: 01 2f + 5c84: 03 06 01 00 lb a2, 0(sp) + 5c88: 00 c5 + 5c8a: 00 01 + 5c8c: 00 00 + 5c8e: 1a 5c + 5c90: 48 01 + 5c92: 80 34 + 5c94: 00 00 + 5c96: 00 c5 + 5c98: 0d 00 + 5c9a: 00 12 + 5c9c: 6e 0f + 5c9e: 00 00 + 5ca0: 01 2f + 5ca2: 03 06 01 00 lb a2, 0(sp) + 5ca6: 00 0c + 5ca8: 01 01 + 5caa: 00 00 + 5cac: 16 a0 + 5cae: 11 00 + 5cb0: 00 df + 5cb2: 0d 00 + 5cb4: 00 12 + 5cb6: 6e 0f + 5cb8: 00 00 + 5cba: 01 2f + 5cbc: 03 06 01 00 lb a2, 0(sp) + 5cc0: 00 53 + 5cc2: 01 01 + 5cc4: 00 00 + 5cc6: 1c b8 + 5cc8: 11 00 + 5cca: 00 12 + 5ccc: 93 0e 00 00 mv t4, zero + 5cd0: 01 2f + 5cd2: 03 40 0e 00 lbu zero, 0(t3) + 5cd6: 00 b4 + 5cd8: 01 01 + 5cda: 00 12 + 5cdc: 33 0e 00 00 add t3, zero, zero + 5ce0: 01 2f + 5ce2: 03 40 0e 00 lbu zero, 0(t3) + 5ce6: 00 c8 + 5ce8: 01 01 + 5cea: 00 12 + 5cec: 47 0e 00 00 fmsub.s ft8, ft0, ft0, ft0, rne + 5cf0: 01 2f + 5cf2: 03 40 0e 00 lbu zero, 0(t3) + 5cf6: 00 dc + 5cf8: 01 01 + 5cfa: 00 12 + 5cfc: ec 0d + 5cfe: 00 00 + 5d00: 01 2f + 5d02: 03 40 0e 00 lbu zero, 0(t3) + 5d06: 00 f0 + 5d08: 01 01 + 5d0a: 00 00 + 5d0c: 00 1e + 5d0e: ac 39 + 5d10: 01 80 + 5d12: 2c 00 + 5d14: 00 00 + 5d16: 17 83 0d 00 auipc t1, 216 + 5d1a: 00 01 + 5d1c: 2f 03 0d 01 + 5d20: 00 00 + 5d22: 02 91 + 5d24: 40 00 + 5d26: 00 03 + 5d28: 04 05 + 5d2a: f6 03 + 5d2c: 00 00 + 5d2e: 06 06 + 5d30: 01 00 + 5d32: 00 57 + 5d34: 0e 00 + 5d36: 00 07 + 5d38: 53 00 00 00 fadd.s ft0, ft0, ft0, rne + 5d3c: 03 00 1f 06 lb zero, 97(t5) + 5d40: 01 00 + 5d42: 00 07 + 5d44: 53 00 00 00 fadd.s ft0, ft0, ft0, rne + 5d48: 02 00 + 5d4a: 00 d0 + 5d4c: 02 00 + 5d4e: 00 04 + 5d50: 00 ba + 5d52: 10 00 + 5d54: 00 04 + 5d56: 01 c8 + 5d58: 09 00 + 5d5a: 00 0c + 5d5c: 43 11 00 00 fmadd.s ft2, ft0, ft0, ft0, rtz + 5d60: d5 01 + 5d62: 00 00 + 5d64: bc 49 + 5d66: 01 80 + 5d68: ac 01 + 5d6a: 00 00 + 5d6c: 91 94 + 5d6e: 00 00 + 5d70: 02 04 + 5d72: 05 69 + 5d74: 6e 74 + 5d76: 00 03 + 5d78: 01 06 + 5d7a: ad 06 + 5d7c: 00 00 + 5d7e: 04 82 + 5d80: 01 00 + 5d82: 00 02 + 5d84: 48 01 + 5d86: 0d 25 + 5d88: 00 00 + 5d8a: 00 03 + 5d8c: 08 05 + 5d8e: f1 03 + 5d90: 00 00 + 5d92: 04 b7 + 5d94: 07 00 00 02 + 5d98: 4a 01 + 5d9a: 16 59 + 5d9c: 00 00 + 5d9e: 00 05 + 5da0: 47 00 00 00 fmsub.s ft0, ft0, ft0, ft0, rne + 5da4: 03 01 08 ab lb sp, -1360(a6) + 5da8: 06 00 + 5daa: 00 04 + 5dac: 81 01 + 5dae: 00 00 + 5db0: 02 4b + 5db2: 01 16 + 5db4: 6d 00 + 5db6: 00 00 + 5db8: 03 04 07 d4 lb s0, -704(a4) + 5dbc: 02 00 + 5dbe: 00 03 + 5dc0: 08 07 + 5dc2: ca 02 + 5dc4: 00 00 + 5dc6: 03 02 07 ea lb tp, -352(a4) + 5dca: 02 00 + 5dcc: 00 06 + 5dce: 54 00 + 5dd0: 00 00 + 5dd2: 92 00 + 5dd4: 00 00 + 5dd6: 07 6d 00 00 + 5dda: 00 ff + 5ddc: 00 05 + 5dde: 82 00 + 5de0: 00 00 + 5de2: 08 fd + 5de4: 02 00 + 5de6: 00 04 + 5de8: 3c 16 + 5dea: 92 00 + 5dec: 00 00 + 5dee: 09 46 + 5df0: 0c 00 + 5df2: 00 03 + 5df4: 48 0f + 5df6: af 00 00 00 + 5dfa: 03 10 04 c0 lh zero, -1024(s0) + 5dfe: 00 00 + 5e00: 00 0a + 5e02: 10 03 + 5e04: 4f 03 20 01 fnmadd.s ft6, ft0, fs2, ft0, rne + 5e08: 00 00 + 5e0a: 0b 60 08 00 + 5e0e: 00 03 + 5e10: 59 13 + 5e12: 20 01 + 5e14: 00 00 + 5e16: 04 20 + 5e18: 00 00 + 5e1a: 0b 66 08 00 + 5e1e: 00 03 + 5e20: 5a 13 + 5e22: 20 01 + 5e24: 00 00 + 5e26: 04 20 + 5e28: 00 04 + 5e2a: 0b 3a 0c 00 + 5e2e: 00 03 + 5e30: 5b 13 20 01 + 5e34: 00 00 + 5e36: 04 20 + 5e38: 00 08 + 5e3a: 0b 40 0c 00 + 5e3e: 00 03 + 5e40: 5c 13 + 5e42: 20 01 + 5e44: 00 00 + 5e46: 04 10 + 5e48: 10 0c + 5e4a: 0c 65 + 5e4c: 78 70 + 5e4e: 00 03 + 5e50: 5d 0e + 5e52: 6d 00 + 5e54: 00 00 + 5e56: 04 0f + 5e58: 01 0c + 5e5a: 0b 41 02 00 + 5e5e: 00 03 + 5e60: 5e 0e + 5e62: 6d 00 + 5e64: 00 00 + 5e66: 04 01 + 5e68: 00 0c + 5e6a: 00 03 + 5e6c: 04 07 + 5e6e: cf 02 00 00 fnmadd.s ft5, ft0, ft0, ft0, rne + 5e72: 0d 74 + 5e74: 0c 00 + 5e76: 00 10 + 5e78: 03 4c 07 4d lbu s8, 1232(a4) + 5e7c: 01 00 + 5e7e: 00 0e + 5e80: 66 6c + 5e82: 74 00 + 5e84: 03 4e 0a a3 lbu t3, -1488(s4) + 5e88: 00 00 + 5e8a: 00 0f + 5e8c: 8d 0a + 5e8e: 00 00 + 5e90: 03 60 05 b6 + 5e94: 00 00 + 5e96: 00 00 + 5e98: 10 72 + 5e9a: 11 00 + 5e9c: 00 01 + 5e9e: 23 01 33 00 sb gp, 2(t1) + 5ea2: 00 00 + 5ea4: bc 49 + 5ea6: 01 80 + 5ea8: ac 01 + 5eaa: 00 00 + 5eac: 01 9c + 5eae: c0 02 + 5eb0: 00 00 + 5eb2: 11 61 + 5eb4: 00 01 + 5eb6: 23 13 a3 00 sh a0, 6(t1) + 5eba: 00 00 + 5ebc: 12 f2 + 5ebe: 08 00 + 5ec0: 00 01 + 5ec2: 25 03 + 5ec4: 25 00 + 5ec6: 00 00 + 5ec8: 10 02 + 5eca: 01 00 + 5ecc: 13 92 0a 00 slli tp, s5, 0 + 5ed0: 00 01 + 5ed2: 25 03 + 5ed4: 25 00 + 5ed6: 00 00 + 5ed8: 14 41 + 5eda: 5f 63 00 01 + 5ede: 26 03 + 5ee0: c0 02 + 5ee2: 00 00 + 5ee4: 15 41 + 5ee6: 5f 73 00 01 + 5eea: 26 03 + 5eec: c0 02 + 5eee: 00 00 + 5ef0: 5a 02 + 5ef2: 01 00 + 5ef4: 15 41 + 5ef6: 5f 65 00 01 + 5efa: 26 03 + 5efc: c0 02 + 5efe: 00 00 + 5f00: 2f 03 01 00 + 5f04: 16 41 + 5f06: 5f 66 00 01 + 5f0a: 26 03 + 5f0c: c7 02 00 00 fmsub.s ft5, ft0, ft0, ft0, rne + 5f10: 02 91 + 5f12: 70 15 + 5f14: 72 00 + 5f16: 01 27 + 5f18: 0b 60 00 00 + 5f1c: 00 17 + 5f1e: 04 01 + 5f20: 00 17 + 5f22: d0 11 + 5f24: 00 00 + 5f26: ef 01 00 00 jal gp, 0 + 5f2a: 18 f8 + 5f2c: 0b 00 00 01 + 5f30: 2a 03 + 5f32: 27 01 00 00 + 5f36: 02 91 + 5f38: 60 00 + 5f3a: 17 f8 11 00 auipc a6, 287 + 5f3e: 00 53 + 5f40: 02 00 + 5f42: 00 12 + 5f44: 30 11 + 5f46: 00 00 + 5f48: 01 2b + 5f4a: 03 25 00 00 lw a0, 0(zero) + 5f4e: 00 67 + 5f50: 04 01 + 5f52: 00 19 + 5f54: 18 12 + 5f56: 00 00 + 5f58: 13 13 0b 00 slli t1, s6, 0 + 5f5c: 00 01 + 5f5e: 2b 03 c0 02 + 5f62: 00 00 + 5f64: 13 c5 0a 00 xori a0, s5, 0 + 5f68: 00 01 + 5f6a: 2b 03 c0 02 + 5f6e: 00 00 + 5f70: 13 ec 0a 00 ori s8, s5, 0 + 5f74: 00 01 + 5f76: 2b 03 c0 02 + 5f7a: 00 00 + 5f7c: 12 da + 5f7e: 0a 00 + 5f80: 00 01 + 5f82: 2b 03 c0 02 + 5f86: 00 00 + 5f88: ce 04 + 5f8a: 01 00 + 5f8c: 12 01 + 5f8e: 0b 00 00 01 + 5f92: 2b 03 20 01 + 5f96: 00 00 + 5f98: e2 04 + 5f9a: 01 00 + 5f9c: 00 00 + 5f9e: 19 38 + 5fa0: 12 00 + 5fa2: 00 12 + 5fa4: 30 11 + 5fa6: 00 00 + 5fa8: 01 2b + 5faa: 03 25 00 00 lw a0, 0(zero) + 5fae: 00 35 + 5fb0: 05 01 + 5fb2: 00 19 + 5fb4: 50 12 + 5fb6: 00 00 + 5fb8: 12 13 + 5fba: 0b 00 00 01 + 5fbe: 2b 03 c0 02 + 5fc2: 00 00 + 5fc4: 67 05 01 00 jalr a0, sp + 5fc8: 12 c5 + 5fca: 0a 00 + 5fcc: 00 01 + 5fce: 2b 03 c0 02 + 5fd2: 00 00 + 5fd4: 5c 06 + 5fd6: 01 00 + 5fd8: 12 ec + 5fda: 0a 00 + 5fdc: 00 01 + 5fde: 2b 03 c0 02 + 5fe2: 00 00 + 5fe4: 36 07 + 5fe6: 01 00 + 5fe8: 12 da + 5fea: 0a 00 + 5fec: 00 01 + 5fee: 2b 03 c0 02 + 5ff2: 00 00 + 5ff4: c1 07 + 5ff6: 01 00 + 5ff8: 12 01 + 5ffa: 0b 00 00 01 + 5ffe: 2b 03 20 01 + 6002: 00 00 + 6004: 4a 08 + 6006: 01 00 + 6008: 00 00 + 600a: 00 03 + 600c: 04 05 + 600e: f6 03 + 6010: 00 00 + 6012: 1a 20 + 6014: 01 00 + 6016: 00 07 + 6018: 6d 00 + 601a: 00 00 + 601c: 03 00 00 ba lb zero, -1120(zero) + 6020: 03 00 00 04 lb zero, 64(zero) + 6024: 00 40 + 6026: 12 00 + 6028: 00 04 + 602a: 01 c8 + 602c: 09 00 + 602e: 00 0c + 6030: 7c 11 + 6032: 00 00 + 6034: d5 01 + 6036: 00 00 + 6038: 68 4b + 603a: 01 80 + 603c: 50 01 + 603e: 00 00 + 6040: ec 98 + 6042: 00 00 + 6044: 02 04 + 6046: 05 69 + 6048: 6e 74 + 604a: 00 03 + 604c: 01 06 + 604e: ad 06 + 6050: 00 00 + 6052: 04 82 + 6054: 01 00 + 6056: 00 02 + 6058: 48 01 + 605a: 0d 25 + 605c: 00 00 + 605e: 00 03 + 6060: 08 05 + 6062: f1 03 + 6064: 00 00 + 6066: 04 b7 + 6068: 07 00 00 02 + 606c: 4a 01 + 606e: 16 59 + 6070: 00 00 + 6072: 00 05 + 6074: 47 00 00 00 fmsub.s ft0, ft0, ft0, ft0, rne + 6078: 03 01 08 ab lb sp, -1360(a6) + 607c: 06 00 + 607e: 00 04 + 6080: 81 01 + 6082: 00 00 + 6084: 02 4b + 6086: 01 16 + 6088: 6d 00 + 608a: 00 00 + 608c: 03 04 07 d4 lb s0, -704(a4) + 6090: 02 00 + 6092: 00 03 + 6094: 08 07 + 6096: ca 02 + 6098: 00 00 + 609a: 03 02 07 ea lb tp, -352(a4) + 609e: 02 00 + 60a0: 00 06 + 60a2: 54 00 + 60a4: 00 00 + 60a6: 92 00 + 60a8: 00 00 + 60aa: 07 6d 00 00 + 60ae: 00 ff + 60b0: 00 05 + 60b2: 82 00 + 60b4: 00 00 + 60b6: 08 fd + 60b8: 02 00 + 60ba: 00 04 + 60bc: 3c 16 + 60be: 92 00 + 60c0: 00 00 + 60c2: 09 46 + 60c4: 0c 00 + 60c6: 00 03 + 60c8: 48 0f + 60ca: af 00 00 00 + 60ce: 03 10 04 c0 lh zero, -1024(s0) + 60d2: 00 00 + 60d4: 00 0a + 60d6: 10 03 + 60d8: 4f 03 20 01 fnmadd.s ft6, ft0, fs2, ft0, rne + 60dc: 00 00 + 60de: 0b 60 08 00 + 60e2: 00 03 + 60e4: 59 13 + 60e6: 20 01 + 60e8: 00 00 + 60ea: 04 20 + 60ec: 00 00 + 60ee: 0b 66 08 00 + 60f2: 00 03 + 60f4: 5a 13 + 60f6: 20 01 + 60f8: 00 00 + 60fa: 04 20 + 60fc: 00 04 + 60fe: 0b 3a 0c 00 + 6102: 00 03 + 6104: 5b 13 20 01 + 6108: 00 00 + 610a: 04 20 + 610c: 00 08 + 610e: 0b 40 0c 00 + 6112: 00 03 + 6114: 5c 13 + 6116: 20 01 + 6118: 00 00 + 611a: 04 10 + 611c: 10 0c + 611e: 0c 65 + 6120: 78 70 + 6122: 00 03 + 6124: 5d 0e + 6126: 6d 00 + 6128: 00 00 + 612a: 04 0f + 612c: 01 0c + 612e: 0b 41 02 00 + 6132: 00 03 + 6134: 5e 0e + 6136: 6d 00 + 6138: 00 00 + 613a: 04 01 + 613c: 00 0c + 613e: 00 03 + 6140: 04 07 + 6142: cf 02 00 00 fnmadd.s ft5, ft0, ft0, ft0, rne + 6146: 0d 74 + 6148: 0c 00 + 614a: 00 10 + 614c: 03 4c 07 4d lbu s8, 1232(a4) + 6150: 01 00 + 6152: 00 0e + 6154: 66 6c + 6156: 74 00 + 6158: 03 4e 0a a3 lbu t3, -1488(s4) + 615c: 00 00 + 615e: 00 0f + 6160: 8d 0a + 6162: 00 00 + 6164: 03 60 05 b6 + 6168: 00 00 + 616a: 00 00 + 616c: 10 ba + 616e: 11 00 + 6170: 00 01 + 6172: 24 01 + 6174: a3 00 00 00 sb zero, 1(zero) + 6178: 68 4b + 617a: 01 80 + 617c: 50 01 + 617e: 00 00 + 6180: 01 9c + 6182: aa 03 + 6184: 00 00 + 6186: 11 69 + 6188: 00 01 + 618a: 24 15 + 618c: 33 00 00 00 add zero, zero, zero + 6190: 69 08 + 6192: 01 00 + 6194: 12 41 + 6196: 5f 63 00 01 + 619a: 26 03 + 619c: aa 03 + 619e: 00 00 + 61a0: 13 41 5f 73 xori sp, t5, 1845 + 61a4: 00 01 + 61a6: 26 03 + 61a8: aa 03 + 61aa: 00 00 + 61ac: 95 08 + 61ae: 01 00 + 61b0: 13 41 5f 65 xori sp, t5, 1621 + 61b4: 00 01 + 61b6: 26 03 + 61b8: aa 03 + 61ba: 00 00 + 61bc: bf 08 01 00 + 61c0: 14 41 + 61c2: 5f 66 00 01 + 61c6: 26 03 + 61c8: b1 03 + 61ca: 00 00 + 61cc: 02 91 + 61ce: 60 13 + 61d0: 61 00 + 61d2: 01 27 + 61d4: 0a a3 + 61d6: 00 00 + 61d8: 00 e9 + 61da: 08 01 + 61dc: 00 15 + 61de: 78 12 + 61e0: 00 00 + 61e2: 94 03 + 61e4: 00 00 + 61e6: 16 ad + 61e8: 11 00 + 61ea: 00 01 + 61ec: 29 03 + 61ee: 17 98 12 00 auipc a6, 297 + 61f2: 00 18 + 61f4: c6 11 + 61f6: 00 00 + 61f8: 01 29 + 61fa: 03 60 00 00 + 61fe: 00 3d + 6200: 09 01 + 6202: 00 15 + 6204: b0 12 + 6206: 00 00 + 6208: fe 01 + 620a: 00 00 + 620c: 18 d6 + 620e: 11 00 + 6210: 00 01 + 6212: 29 03 + 6214: 25 00 + 6216: 00 00 + 6218: 66 09 + 621a: 01 00 + 621c: 00 15 + 621e: d0 12 + 6220: 00 00 + 6222: 48 02 + 6224: 00 00 + 6226: 18 81 + 6228: 0f 00 00 01 fence w, unknown + 622c: 29 03 + 622e: aa 03 + 6230: 00 00 + 6232: 84 09 + 6234: 01 00 + 6236: 18 bc + 6238: 0d 00 + 623a: 00 01 + 623c: 29 03 + 623e: aa 03 + 6240: 00 00 + 6242: dc 09 + 6244: 01 00 + 6246: 18 a8 + 6248: 0d 00 + 624a: 00 01 + 624c: 29 03 + 624e: aa 03 + 6250: 00 00 + 6252: 4c 0a + 6254: 01 00 + 6256: 18 0e + 6258: 0e 00 + 625a: 00 01 + 625c: 29 03 + 625e: aa 03 + 6260: 00 00 + 6262: a5 0a + 6264: 01 00 + 6266: 00 19 + 6268: 7e 02 + 626a: 00 00 + 626c: 1a 81 + 626e: 0f 00 00 01 fence w, unknown + 6272: 29 03 + 6274: aa 03 + 6276: 00 00 + 6278: 1a bc + 627a: 0d 00 + 627c: 00 01 + 627e: 29 03 + 6280: aa 03 + 6282: 00 00 + 6284: 1a a8 + 6286: 0d 00 + 6288: 00 01 + 628a: 29 03 + 628c: aa 03 + 628e: 00 00 + 6290: 1a 0e + 6292: 0e 00 + 6294: 00 01 + 6296: 29 03 + 6298: aa 03 + 629a: 00 00 + 629c: 00 1b + 629e: 1a 04 + 62a0: 11 00 + 62a2: 00 01 + 62a4: 29 03 + 62a6: 25 00 + 62a8: 00 00 + 62aa: 19 29 + 62ac: 03 00 00 1a lb zero, 416(zero) + 62b0: e2 0f + 62b2: 00 00 + 62b4: 01 29 + 62b6: 03 aa 03 00 lw s4, 0(t2) + 62ba: 00 1a + 62bc: 2a 10 + 62be: 00 00 + 62c0: 01 29 + 62c2: 03 aa 03 00 lw s4, 0(t2) + 62c6: 00 1a + 62c8: 7d 10 + 62ca: 00 00 + 62cc: 01 29 + 62ce: 03 aa 03 00 lw s4, 0(t2) + 62d2: 00 1a + 62d4: 92 10 + 62d6: 00 00 + 62d8: 01 29 + 62da: 03 b1 03 00 + 62de: 00 19 + 62e0: f6 02 + 62e2: 00 00 + 62e4: 1a 81 + 62e6: 0f 00 00 01 fence w, unknown + 62ea: 29 03 + 62ec: aa 03 + 62ee: 00 00 + 62f0: 1a bc + 62f2: 0d 00 + 62f4: 00 01 + 62f6: 29 03 + 62f8: aa 03 + 62fa: 00 00 + 62fc: 1a a8 + 62fe: 0d 00 + 6300: 00 01 + 6302: 29 03 + 6304: aa 03 + 6306: 00 00 + 6308: 1a 0e + 630a: 0e 00 + 630c: 00 01 + 630e: 29 03 + 6310: aa 03 + 6312: 00 00 + 6314: 00 19 + 6316: 08 03 + 6318: 00 00 + 631a: 1a 6e + 631c: 0f 00 00 01 fence w, unknown + 6320: 29 03 + 6322: 20 01 + 6324: 00 00 + 6326: 00 19 + 6328: 1a 03 + 632a: 00 00 + 632c: 1a 6e + 632e: 0f 00 00 01 fence w, unknown + 6332: 29 03 + 6334: 20 01 + 6336: 00 00 + 6338: 00 1b + 633a: 1a 6e + 633c: 0f 00 00 01 fence w, unknown + 6340: 29 03 + 6342: 20 01 + 6344: 00 00 + 6346: 00 00 + 6348: 19 3b + 634a: 03 00 00 1a lb zero, 416(zero) + 634e: 6e 0f + 6350: 00 00 + 6352: 01 29 + 6354: 03 20 01 00 lw zero, 0(sp) + 6358: 00 00 + 635a: 19 4d + 635c: 03 00 00 1a lb zero, 416(zero) + 6360: 6e 0f + 6362: 00 00 + 6364: 01 29 + 6366: 03 20 01 00 lw zero, 0(sp) + 636a: 00 00 + 636c: 19 5f + 636e: 03 00 00 1a lb zero, 416(zero) + 6372: 6e 0f + 6374: 00 00 + 6376: 01 29 + 6378: 03 20 01 00 lw zero, 0(sp) + 637c: 00 00 + 637e: 1b 1a 93 0e + 6382: 00 00 + 6384: 01 29 + 6386: 03 aa 03 00 lw s4, 0(t2) + 638a: 00 1a + 638c: 33 0e 00 00 add t3, zero, zero + 6390: 01 29 + 6392: 03 aa 03 00 lw s4, 0(t2) + 6396: 00 1a + 6398: 47 0e 00 00 fmsub.s ft8, ft0, ft0, ft0, rne + 639c: 01 29 + 639e: 03 aa 03 00 lw s4, 0(t2) + 63a2: 00 1a + 63a4: ec 0d + 63a6: 00 00 + 63a8: 01 29 + 63aa: 03 aa 03 00 lw s4, 0(t2) + 63ae: 00 00 + 63b0: 00 00 + 63b2: 00 17 + 63b4: f0 12 + 63b6: 00 00 + 63b8: 1c 83 + 63ba: 0d 00 + 63bc: 00 01 + 63be: 2a 03 + 63c0: 27 01 00 00 + 63c4: 02 91 + 63c6: 50 00 + 63c8: 00 03 + 63ca: 04 05 + 63cc: f6 03 + 63ce: 00 00 + 63d0: 1d 20 + 63d2: 01 00 + 63d4: 00 07 + 63d6: 6d 00 + 63d8: 00 00 + 63da: 03 00 00 ab lb zero, -1360(zero) + 63de: 02 00 + 63e0: 00 04 + 63e2: 00 e1 + 63e4: 13 00 00 04 addi zero, zero, 64 + 63e8: 01 c8 + 63ea: 09 00 + 63ec: 00 0c + 63ee: e6 11 + 63f0: 00 00 + 63f2: d5 01 + 63f4: 00 00 + 63f6: b8 4c + 63f8: 01 80 + 63fa: 0c 01 + 63fc: 00 00 + 63fe: 89 9c + 6400: 00 00 + 6402: 02 04 + 6404: 04 eb + 6406: 03 00 00 03 lb zero, 48(zero) + 640a: 04 05 + 640c: 69 6e + 640e: 74 00 + 6410: 02 01 + 6412: 06 ad + 6414: 06 00 + 6416: 00 02 + 6418: 08 05 + 641a: f1 03 + 641c: 00 00 + 641e: 04 b7 + 6420: 07 00 00 02 + 6424: 4a 01 + 6426: 16 53 + 6428: 00 00 + 642a: 00 05 + 642c: 41 00 + 642e: 00 00 + 6430: 02 01 + 6432: 08 ab + 6434: 06 00 + 6436: 00 02 + 6438: 04 07 + 643a: d4 02 + 643c: 00 00 + 643e: 02 08 + 6440: 07 ca 02 00 + 6444: 00 02 + 6446: 02 07 + 6448: ea 02 + 644a: 00 00 + 644c: 06 4e + 644e: 00 00 + 6450: 00 7f + 6452: 00 00 + 6454: 00 07 + 6456: 5a 00 + 6458: 00 00 + 645a: ff 00 05 6f + 645e: 00 00 + 6460: 00 08 + 6462: fd 02 + 6464: 00 00 + 6466: 05 3c + 6468: 16 7f + 646a: 00 00 + 646c: 00 09 + 646e: 4c 12 + 6470: 00 00 + 6472: 03 45 0f 25 lbu a0, 592(t5) + 6476: 00 00 + 6478: 00 0a + 647a: 04 03 + 647c: 4a 03 + 647e: d6 00 + 6480: 00 00 + 6482: 0b 3b 12 00 + 6486: 00 03 + 6488: 51 0e + 648a: 5a 00 + 648c: 00 00 + 648e: 04 17 + 6490: 09 00 + 6492: 0c 65 + 6494: 78 70 + 6496: 00 03 + 6498: 52 0e + 649a: 5a 00 + 649c: 00 00 + 649e: 04 08 + 64a0: 01 00 + 64a2: 0b 41 02 00 + 64a6: 00 03 + 64a8: 53 0e 5a 00 fadd.s ft8, fs4, ft5, rne + 64ac: 00 00 + 64ae: 04 01 + 64b0: 00 00 + 64b2: 00 0d + 64b4: 40 12 + 64b6: 00 00 + 64b8: 04 03 + 64ba: 47 07 fc 00 fmsub.s fa4, fs8, fa5, ft0, rne + 64be: 00 00 + 64c0: 0e 66 + 64c2: 6c 74 + 64c4: 00 03 + 64c6: 49 0a + 64c8: 90 00 + 64ca: 00 00 + 64cc: 0f 8d 0a 00 + 64d0: 00 03 + 64d2: 55 05 + 64d4: 9c 00 + 64d6: 00 00 + 64d8: 00 09 + 64da: 7f 08 00 00 + 64de: 04 48 + 64e0: 0f 08 01 00 + 64e4: 00 02 + 64e6: 08 04 + 64e8: c5 00 + 64ea: 00 00 + 64ec: 0a 08 + 64ee: 04 4f + 64f0: 03 59 01 00 lhu s2, 0(sp) + 64f4: 00 0b + 64f6: 60 08 + 64f8: 00 00 + 64fa: 04 57 + 64fc: 0e 5a + 64fe: 00 00 + 6500: 00 04 + 6502: 20 00 + 6504: 00 0b + 6506: 66 08 + 6508: 00 00 + 650a: 04 58 + 650c: 0e 5a + 650e: 00 00 + 6510: 00 04 + 6512: 14 0c + 6514: 04 0c + 6516: 65 78 + 6518: 70 00 + 651a: 04 59 + 651c: 0e 5a + 651e: 00 00 + 6520: 00 04 + 6522: 0b 01 04 0b + 6526: 41 02 + 6528: 00 00 + 652a: 04 5a + 652c: 0e 5a + 652e: 00 00 + 6530: 00 04 + 6532: 01 00 + 6534: 04 00 + 6536: 0d 6a + 6538: 0a 00 + 653a: 00 08 + 653c: 04 4c + 653e: 07 7f 01 00 + 6542: 00 0e + 6544: 66 6c + 6546: 74 00 + 6548: 04 4e + 654a: 0a fc + 654c: 00 00 + 654e: 00 0f + 6550: 8d 0a + 6552: 00 00 + 6554: 04 5c + 6556: 05 0f + 6558: 01 00 + 655a: 00 00 + 655c: 10 53 + 655e: 12 00 + 6560: 00 01 + 6562: 25 01 + 6564: fc 00 + 6566: 00 00 + 6568: b8 4c + 656a: 01 80 + 656c: 0c 01 + 656e: 00 00 + 6570: 01 9c + 6572: a0 02 + 6574: 00 00 + 6576: 11 61 + 6578: 00 01 + 657a: 25 17 + 657c: 90 00 + 657e: 00 00 + 6580: ff 0a 01 00 + 6584: 12 f2 + 6586: 08 00 + 6588: 00 01 + 658a: 27 03 2c 00 + 658e: 00 00 + 6590: 6c 0b + 6592: 01 00 + 6594: 13 92 0a 00 slli tp, s5, 0 + 6598: 00 01 + 659a: 27 03 2c 00 + 659e: 00 00 + 65a0: 14 41 + 65a2: 5f 63 00 01 + 65a6: 28 03 + 65a8: a0 02 + 65aa: 00 00 + 65ac: 15 41 + 65ae: 5f 73 00 01 + 65b2: 28 03 + 65b4: a0 02 + 65b6: 00 00 + 65b8: ae 0b + 65ba: 01 00 + 65bc: 15 41 + 65be: 5f 65 00 01 + 65c2: 28 03 + 65c4: a0 02 + 65c6: 00 00 + 65c8: d6 0b + 65ca: 01 00 + 65cc: 15 41 + 65ce: 5f 66 00 01 + 65d2: 28 03 + 65d4: a7 02 00 00 + 65d8: 2a 0c + 65da: 01 00 + 65dc: 14 52 + 65de: 5f 63 00 01 + 65e2: 29 03 + 65e4: a0 02 + 65e6: 00 00 + 65e8: 15 52 + 65ea: 5f 73 00 01 + 65ee: 29 03 + 65f0: a0 02 + 65f2: 00 00 + 65f4: ae 0b + 65f6: 01 00 + 65f8: 15 52 + 65fa: 5f 65 00 01 + 65fe: 29 03 + 6600: a0 02 + 6602: 00 00 + 6604: 69 0c + 6606: 01 00 + 6608: 12 d3 + 660a: 08 00 + 660c: 00 01 + 660e: 29 03 + 6610: a7 02 00 00 + 6614: 95 0c + 6616: 01 00 + 6618: 12 97 + 661a: 0a 00 + 661c: 00 01 + 661e: 29 03 + 6620: a7 02 00 00 + 6624: d5 0c + 6626: 01 00 + 6628: 14 72 + 662a: 00 01 + 662c: 2a 0a + 662e: fc 00 + 6630: 00 00 + 6632: 16 10 + 6634: 13 00 00 6b addi zero, zero, 1712 + 6638: 02 00 + 663a: 00 13 + 663c: 26 12 + 663e: 00 00 + 6640: 01 2d + 6642: 03 d6 00 00 lhu a2, 0(ra) + 6646: 00 00 + 6648: 17 4c 4d 01 auipc s8, 5332 + 664c: 80 40 + 664e: 00 00 + 6650: 00 89 + 6652: 02 00 + 6654: 00 12 + 6656: 19 12 + 6658: 00 00 + 665a: 01 2f + 665c: 03 2c 00 00 lw s8, 0(zero) + 6660: 00 45 + 6662: 0d 01 + 6664: 00 00 + 6666: 18 04 + 6668: 4d 01 + 666a: 80 20 + 666c: 00 00 + 666e: 00 13 + 6670: 6c 08 + 6672: 00 00 + 6674: 01 33 + 6676: 03 59 01 00 lhu s2, 0(sp) + 667a: 00 00 + 667c: 00 02 + 667e: 04 05 + 6680: f6 03 + 6682: 00 00 + 6684: 02 04 + 6686: 07 cf 02 00 + 668a: 00 00 + 668c: fd 03 + 668e: 00 00 + 6690: 04 00 + 6692: 4d 15 + 6694: 00 00 + 6696: 04 01 + 6698: c8 09 + 669a: 00 00 + 669c: 0c 61 + 669e: 12 00 + 66a0: 00 d5 + 66a2: 01 00 + 66a4: 00 c4 + 66a6: 4d 01 + 66a8: 80 28 + 66aa: 02 00 + 66ac: 00 6c + 66ae: a0 00 + 66b0: 00 02 + 66b2: 08 04 + 66b4: c5 00 + 66b6: 00 00 + 66b8: 03 04 05 69 lb s0, 1680(a0) + 66bc: 6e 74 + 66be: 00 02 + 66c0: 01 06 + 66c2: ad 06 + 66c4: 00 00 + 66c6: 02 08 + 66c8: 05 f1 + 66ca: 03 00 00 04 lb zero, 64(zero) + 66ce: b7 07 00 00 lui a5, 0 + 66d2: 02 4a + 66d4: 01 16 + 66d6: 53 00 00 00 fadd.s ft0, ft0, ft0, rne + 66da: 05 41 + 66dc: 00 00 + 66de: 00 02 + 66e0: 01 08 + 66e2: ab 06 00 00 + 66e6: 02 04 + 66e8: 07 d4 02 00 + 66ec: 00 02 + 66ee: 08 07 + 66f0: ca 02 + 66f2: 00 00 + 66f4: 02 02 + 66f6: 07 ea 02 00 + 66fa: 00 06 + 66fc: 4e 00 + 66fe: 00 00 + 6700: 7f 00 00 00 + 6704: 07 5a 00 00 + 6708: 00 ff + 670a: 00 05 + 670c: 6f 00 00 00 j 0 + 6710: 08 fd + 6712: 02 00 + 6714: 00 05 + 6716: 3c 16 + 6718: 7f 00 00 00 + 671c: 09 7f + 671e: 08 00 + 6720: 00 03 + 6722: 48 0f + 6724: 25 00 + 6726: 00 00 + 6728: 0a 08 + 672a: 03 4f 03 e6 lbu t5, -416(t1) + 672e: 00 00 + 6730: 00 0b + 6732: 60 08 + 6734: 00 00 + 6736: 03 57 0e 5a lhu a4, 1440(t3) + 673a: 00 00 + 673c: 00 04 + 673e: 20 00 + 6740: 00 0b + 6742: 66 08 + 6744: 00 00 + 6746: 03 58 0e 5a lhu a6, 1440(t3) + 674a: 00 00 + 674c: 00 04 + 674e: 14 0c + 6750: 04 0c + 6752: 65 78 + 6754: 70 00 + 6756: 03 59 0e 5a lhu s2, 1440(t3) + 675a: 00 00 + 675c: 00 04 + 675e: 0b 01 04 0b + 6762: 41 02 + 6764: 00 00 + 6766: 03 5a 0e 5a lhu s4, 1440(t3) + 676a: 00 00 + 676c: 00 04 + 676e: 01 00 + 6770: 04 00 + 6772: 0d 6a + 6774: 0a 00 + 6776: 00 08 + 6778: 03 4c 07 0c lbu s8, 192(a4) + 677c: 01 00 + 677e: 00 0e + 6780: 66 6c + 6782: 74 00 + 6784: 03 4e 0a 90 lbu t3, -1792(s4) + 6788: 00 00 + 678a: 00 0f + 678c: 8d 0a + 678e: 00 00 + 6790: 03 5c 05 9c lhu s8, -1600(a0) + 6794: 00 00 + 6796: 00 00 + 6798: 09 46 + 679a: 0c 00 + 679c: 00 04 + 679e: 48 0f + 67a0: 18 01 + 67a2: 00 00 + 67a4: 02 10 + 67a6: 04 c0 + 67a8: 00 00 + 67aa: 00 0a + 67ac: 10 04 + 67ae: 4f 03 89 01 fnmadd.s ft6, fs2, fs8, ft0, rne + 67b2: 00 00 + 67b4: 0b 60 08 00 + 67b8: 00 04 + 67ba: 59 13 + 67bc: 89 01 + 67be: 00 00 + 67c0: 04 20 + 67c2: 00 00 + 67c4: 0b 66 08 00 + 67c8: 00 04 + 67ca: 5a 13 + 67cc: 89 01 + 67ce: 00 00 + 67d0: 04 20 + 67d2: 00 04 + 67d4: 0b 3a 0c 00 + 67d8: 00 04 + 67da: 5b 13 89 01 + 67de: 00 00 + 67e0: 04 20 + 67e2: 00 08 + 67e4: 0b 40 0c 00 + 67e8: 00 04 + 67ea: 5c 13 + 67ec: 89 01 + 67ee: 00 00 + 67f0: 04 10 + 67f2: 10 0c + 67f4: 0c 65 + 67f6: 78 70 + 67f8: 00 04 + 67fa: 5d 0e + 67fc: 5a 00 + 67fe: 00 00 + 6800: 04 0f + 6802: 01 0c + 6804: 0b 41 02 00 + 6808: 00 04 + 680a: 5e 0e + 680c: 5a 00 + 680e: 00 00 + 6810: 04 01 + 6812: 00 0c + 6814: 00 02 + 6816: 04 07 + 6818: cf 02 00 00 fnmadd.s ft5, ft0, ft0, ft0, rne + 681c: 0d 74 + 681e: 0c 00 + 6820: 00 10 + 6822: 04 4c + 6824: 07 b6 01 00 + 6828: 00 0e + 682a: 66 6c + 682c: 74 00 + 682e: 04 4e + 6830: 0a 0c + 6832: 01 00 + 6834: 00 0f + 6836: 8d 0a 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6a82: 01 00 + 6a84: 00 07 + 6a86: 5a 00 + 6a88: 00 00 + 6a8a: 03 00 00 7e lb zero, 2016(zero) + 6a8e: 05 00 + 6a90: 00 04 + 6a92: 00 f0 + 6a94: 16 00 + 6a96: 00 04 + 6a98: 01 c8 + 6a9a: 09 00 + 6a9c: 00 0c + 6a9e: a2 12 + 6aa0: 00 00 + 6aa2: d5 01 + 6aa4: 00 00 + 6aa6: ec 4f + 6aa8: 01 80 + 6aaa: dc 04 + 6aac: 00 00 + 6aae: c7 a6 00 00 fmsub.s fa3, ft1, ft0, ft0, rdn + 6ab2: 02 04 + 6ab4: 05 69 + 6ab6: 6e 74 + 6ab8: 00 03 + 6aba: 01 06 + 6abc: ad 06 + 6abe: 00 00 + 6ac0: 03 08 05 f1 lb a6, -240(a0) + 6ac4: 03 00 00 04 lb zero, 64(zero) + 6ac8: b7 07 00 00 lui a5, 0 + 6acc: 02 4a + 6ace: 01 16 + 6ad0: 4c 00 + 6ad2: 00 00 + 6ad4: 05 3a + 6ad6: 00 00 + 6ad8: 00 03 + 6ada: 01 08 + 6adc: ab 06 00 00 + 6ae0: 03 04 07 d4 lb s0, -704(a4) + 6ae4: 02 00 + 6ae6: 00 03 + 6ae8: 08 07 + 6aea: ca 02 + 6aec: 00 00 + 6aee: 03 02 07 ea lb tp, -352(a4) + 6af2: 02 00 + 6af4: 00 06 + 6af6: 47 00 00 00 fmsub.s ft0, ft0, ft0, ft0, rne + 6afa: 78 00 + 6afc: 00 00 + 6afe: 07 53 00 00 + 6b02: 00 ff + 6b04: 00 05 + 6b06: 68 00 + 6b08: 00 00 + 6b0a: 08 fd + 6b0c: 02 00 + 6b0e: 00 05 + 6b10: 3c 16 + 6b12: 78 00 + 6b14: 00 00 + 6b16: 09 7f + 6b18: 08 00 + 6b1a: 00 03 + 6b1c: 48 0f + 6b1e: 95 00 + 6b20: 00 00 + 6b22: 03 08 04 c5 lb a6, -944(s0) + 6b26: 00 00 + 6b28: 00 0a + 6b2a: 08 03 + 6b2c: 4f 03 e6 00 fnmadd.s ft6, fa2, fa4, ft0, rne + 6b30: 00 00 + 6b32: 0b 60 08 00 + 6b36: 00 03 + 6b38: 57 0e 53 00 + 6b3c: 00 00 + 6b3e: 04 20 + 6b40: 00 00 + 6b42: 0b 66 08 00 + 6b46: 00 03 + 6b48: 58 0e + 6b4a: 53 00 00 00 fadd.s ft0, ft0, ft0, rne + 6b4e: 04 14 + 6b50: 0c 04 + 6b52: 0c 65 + 6b54: 78 70 + 6b56: 00 03 + 6b58: 59 0e + 6b5a: 53 00 00 00 fadd.s ft0, ft0, ft0, rne + 6b5e: 04 0b + 6b60: 01 04 + 6b62: 0b 41 02 00 + 6b66: 00 03 + 6b68: 5a 0e + 6b6a: 53 00 00 00 fadd.s ft0, ft0, ft0, rne + 6b6e: 04 01 + 6b70: 00 04 + 6b72: 00 0d + 6b74: 6a 0a + 6b76: 00 00 + 6b78: 08 03 + 6b7a: 4c 07 + 6b7c: 0c 01 + 6b7e: 00 00 + 6b80: 0e 66 + 6b82: 6c 74 + 6b84: 00 03 + 6b86: 4e 0a + 6b88: 89 00 + 6b8a: 00 00 + 6b8c: 0f 8d 0a 00 + 6b90: 00 03 + 6b92: 5c 05 + 6b94: 9c 00 + 6b96: 00 00 + 6b98: 00 09 + 6b9a: 46 0c + 6b9c: 00 00 + 6b9e: 04 48 + 6ba0: 0f 18 01 00 + 6ba4: 00 03 + 6ba6: 10 04 + 6ba8: c0 00 + 6baa: 00 00 + 6bac: 0a 10 + 6bae: 04 4f + 6bb0: 03 89 01 00 lb s2, 0(gp) + 6bb4: 00 0b + 6bb6: 60 08 + 6bb8: 00 00 + 6bba: 04 59 + 6bbc: 13 89 01 00 mv s2, gp + 6bc0: 00 04 + 6bc2: 20 00 + 6bc4: 00 0b + 6bc6: 66 08 + 6bc8: 00 00 + 6bca: 04 5a + 6bcc: 13 89 01 00 mv s2, gp + 6bd0: 00 04 + 6bd2: 20 00 + 6bd4: 04 0b + 6bd6: 3a 0c + 6bd8: 00 00 + 6bda: 04 5b + 6bdc: 13 89 01 00 mv s2, gp + 6be0: 00 04 + 6be2: 20 00 + 6be4: 08 0b + 6be6: 40 0c + 6be8: 00 00 + 6bea: 04 5c + 6bec: 13 89 01 00 mv s2, gp + 6bf0: 00 04 + 6bf2: 10 10 + 6bf4: 0c 0c + 6bf6: 65 78 + 6bf8: 70 00 + 6bfa: 04 5d + 6bfc: 0e 53 + 6bfe: 00 00 + 6c00: 00 04 + 6c02: 0f 01 0c 0b + 6c06: 41 02 + 6c08: 00 00 + 6c0a: 04 5e + 6c0c: 0e 53 + 6c0e: 00 00 + 6c10: 00 04 + 6c12: 01 00 + 6c14: 0c 00 + 6c16: 03 04 07 cf lb s0, -784(a4) + 6c1a: 02 00 + 6c1c: 00 0d + 6c1e: 74 0c + 6c20: 00 00 + 6c22: 10 04 + 6c24: 4c 07 + 6c26: b6 01 + 6c28: 00 00 + 6c2a: 0e 66 + 6c2c: 6c 74 + 6c2e: 00 04 + 6c30: 4e 0a + 6c32: 0c 01 + 6c34: 00 00 + 6c36: 0f 8d 0a 00 + 6c3a: 00 04 + 6c3c: 60 05 + 6c3e: 1f 01 00 00 + 6c42: 00 10 + 6c44: 00 13 + 6c46: 00 00 + 6c48: 01 24 + 6c4a: 01 89 + 6c4c: 00 00 + 6c4e: 00 ec + 6c50: 4f 01 80 dc + 6c54: 04 00 + 6c56: 00 01 + 6c58: 9c 6e + 6c5a: 05 00 + 6c5c: 00 11 + 6c5e: 61 00 + 6c60: 01 24 + 6c62: 16 0c + 6c64: 01 00 + 6c66: 00 12 + 6c68: f2 08 + 6c6a: 00 00 + 6c6c: 01 26 + 6c6e: 03 25 00 00 lw a0, 0(zero) + 6c72: 00 b8 + 6c74: 11 01 + 6c76: 00 12 + 6c78: 92 0a + 6c7a: 00 00 + 6c7c: 01 26 + 6c7e: 03 25 00 00 lw a0, 0(zero) + 6c82: 00 7c + 6c84: 12 01 + 6c86: 00 13 + 6c88: 41 5f + 6c8a: 63 00 01 27 beq sp, a6, 608 + 6c8e: 03 6e 05 00 + 6c92: 00 14 + 6c94: 41 5f + 6c96: 73 00 01 27 + 6c9a: 03 6e 05 00 + 6c9e: 00 9a + 6ca0: 12 01 + 6ca2: 00 14 + 6ca4: 41 5f + 6ca6: 65 00 + 6ca8: 01 27 + 6caa: 03 6e 05 00 + 6cae: 00 c3 + 6cb0: 12 01 + 6cb2: 00 15 + 6cb4: 41 5f + 6cb6: 66 00 + 6cb8: 01 27 + 6cba: 03 75 05 00 + 6cbe: 00 02 + 6cc0: 91 70 + 6cc2: 13 52 5f 63 + 6cc6: 00 01 + 6cc8: 28 03 + 6cca: 6e 05 + 6ccc: 00 00 + 6cce: 14 52 + 6cd0: 5f 73 00 01 + 6cd4: 28 03 + 6cd6: 6e 05 + 6cd8: 00 00 + 6cda: e9 13 + 6cdc: 01 00 + 6cde: 14 52 + 6ce0: 5f 65 00 01 + 6ce4: 28 03 + 6ce6: 6e 05 + 6ce8: 00 00 + 6cea: 07 14 01 00 + 6cee: 12 d3 + 6cf0: 08 00 + 6cf2: 00 01 + 6cf4: 28 03 + 6cf6: 89 01 + 6cf8: 00 00 + 6cfa: 2c 15 + 6cfc: 01 00 + 6cfe: 12 97 + 6d00: 0a 00 + 6d02: 00 01 + 6d04: 28 03 + 6d06: 89 01 + 6d08: 00 00 + 6d0a: e1 15 + 6d0c: 01 00 + 6d0e: 13 72 00 01 andi tp, zero, 16 + 6d12: 29 0a + 6d14: 89 00 + 6d16: 00 00 + 6d18: 16 04 + 6d1a: 50 01 + 6d1c: 80 38 + 6d1e: 00 00 + 6d20: 00 a8 + 6d22: 02 00 + 6d24: 00 17 + 6d26: f8 0b + 6d28: 00 00 + 6d2a: 01 2c + 6d2c: 03 90 01 00 lh zero, 0(gp) + 6d30: 00 02 + 6d32: 91 60 + 6d34: 00 18 + 6d36: b0 13 + 6d38: 00 00 + 6d3a: e9 02 + 6d3c: 00 00 + 6d3e: 19 81 + 6d40: 0f 00 00 01 fence w, unknown + 6d44: 2c 03 + 6d46: 6e 05 + 6d48: 00 00 + 6d4a: 03 19 bc 0d lh s2, 219(s8) + 6d4e: 00 00 + 6d50: 01 2c + 6d52: 03 6e 05 00 + 6d56: 00 1d + 6d58: 19 a8 + 6d5a: 0d 00 + 6d5c: 00 01 + 6d5e: 2c 03 + 6d60: 6e 05 + 6d62: 00 00 + 6d64: 00 12 + 6d66: 0e 0e + 6d68: 00 00 + 6d6a: 01 2c + 6d6c: 03 6e 05 00 + 6d70: 00 d6 + 6d72: 16 01 + 6d74: 00 00 + 6d76: 18 78 + 6d78: 14 00 + 6d7a: 00 59 + 6d7c: 03 00 00 12 lb zero, 288(zero) + 6d80: 9c 0a + 6d82: 00 00 + 6d84: 01 2e + 6d86: 03 25 00 00 lw a0, 0(zero) + 6d8a: 00 f7 + 6d8c: 16 01 + 6d8e: 00 1a + 6d90: a0 14 + 6d92: 00 00 + 6d94: 12 13 + 6d96: 0b 00 00 01 + 6d9a: 2e 03 + 6d9c: 6e 05 + 6d9e: 00 00 + 6da0: 11 17 + 6da2: 01 00 + 6da4: 12 c5 + 6da6: 0a 00 + 6da8: 00 01 + 6daa: 2e 03 + 6dac: 6e 05 + 6dae: 00 00 + 6db0: a4 17 + 6db2: 01 00 + 6db4: 12 ec + 6db6: 0a 00 + 6db8: 00 01 + 6dba: 2e 03 + 6dbc: 6e 05 + 6dbe: 00 00 + 6dc0: 25 18 + 6dc2: 01 00 + 6dc4: 12 da + 6dc6: 0a 00 + 6dc8: 00 01 + 6dca: 2e 03 + 6dcc: 6e 05 + 6dce: 00 00 + 6dd0: 79 18 + 6dd2: 01 00 + 6dd4: 12 01 + 6dd6: 0b 00 00 01 + 6dda: 2e 03 + 6ddc: 89 01 + 6dde: 00 00 + 6de0: 23 19 01 00 sh zero, 18(sp) + 6de4: 00 00 + 6de6: 16 9c + 6de8: 51 01 + 6dea: 80 3c + 6dec: 00 00 + 6dee: 00 bd + 6df0: 03 00 00 1b lb zero, 432(zero) + 6df4: 9c 0a + 6df6: 00 00 + 6df8: 01 2e + 6dfa: 03 25 00 00 lw a0, 0(zero) + 6dfe: 00 1a + 6e00: 60 14 + 6e02: 00 00 + 6e04: 1b 13 0b 00 + 6e08: 00 01 + 6e0a: 2e 03 + 6e0c: 6e 05 + 6e0e: 00 00 + 6e10: 1b c5 0a 00 + 6e14: 00 01 + 6e16: 2e 03 + 6e18: 6e 05 + 6e1a: 00 00 + 6e1c: 1b ec 0a 00 + 6e20: 00 01 + 6e22: 2e 03 + 6e24: 6e 05 + 6e26: 00 00 + 6e28: 12 da + 6e2a: 0a 00 + 6e2c: 00 01 + 6e2e: 2e 03 + 6e30: 6e 05 + 6e32: 00 00 + 6e34: 42 19 + 6e36: 01 00 + 6e38: 12 01 + 6e3a: 0b 00 00 01 + 6e3e: 2e 03 + 6e40: 89 01 + 6e42: 00 00 + 6e44: 56 19 + 6e46: 01 00 + 6e48: 00 00 + 6e4a: 1c 0d + 6e4c: 04 00 + 6e4e: 00 1b + 6e50: 9c 0a + 6e52: 00 00 + 6e54: 01 2e + 6e56: 03 25 00 00 lw a0, 0(zero) + 6e5a: 00 1d + 6e5c: 1b 13 0b 00 + 6e60: 00 01 + 6e62: 2e 03 + 6e64: 6e 05 + 6e66: 00 00 + 6e68: 1b c5 0a 00 + 6e6c: 00 01 + 6e6e: 2e 03 + 6e70: 6e 05 + 6e72: 00 00 + 6e74: 1b ec 0a 00 + 6e78: 00 01 + 6e7a: 2e 03 + 6e7c: 6e 05 + 6e7e: 00 00 + 6e80: 1b da 0a 00 + 6e84: 00 01 + 6e86: 2e 03 + 6e88: 6e 05 + 6e8a: 00 00 + 6e8c: 1b 01 0b 00 + 6e90: 00 01 + 6e92: 2e 03 + 6e94: 89 01 + 6e96: 00 00 + 6e98: 00 00 + 6e9a: 18 d0 + 6e9c: 14 00 + 6e9e: 00 53 + 6ea0: 04 00 + 6ea2: 00 12 + 6ea4: 93 0e 00 00 mv t4, zero + 6ea8: 01 2e + 6eaa: 03 6e 05 00 + 6eae: 00 99 + 6eb0: 19 01 + 6eb2: 00 12 + 6eb4: 33 0e 00 00 add t3, zero, zero + 6eb8: 01 2e + 6eba: 03 6e 05 00 + 6ebe: 00 ad + 6ec0: 19 01 + 6ec2: 00 12 + 6ec4: 47 0e 00 00 fmsub.s ft8, ft0, ft0, ft0, rne + 6ec8: 01 2e + 6eca: 03 6e 05 00 + 6ece: 00 c1 + 6ed0: 19 01 + 6ed2: 00 1b + 6ed4: ec 0d + 6ed6: 00 00 + 6ed8: 01 2e + 6eda: 03 6e 05 00 + 6ede: 00 00 + 6ee0: 18 d0 + 6ee2: 13 00 00 5b addi zero, zero, 1456 + 6ee6: 05 00 + 6ee8: 00 12 + 6eea: 04 11 + 6eec: 00 00 + 6eee: 01 32 + 6ef0: 03 25 00 00 lw a0, 0(zero) + 6ef4: 00 d5 + 6ef6: 19 01 + 6ef8: 00 18 + 6efa: 30 14 + 6efc: 00 00 + 6efe: 18 05 + 6f00: 00 00 + 6f02: 1b e2 0f 00 + 6f06: 00 01 + 6f08: 32 03 + 6f0a: 6e 05 + 6f0c: 00 00 + 6f0e: 12 2a + 6f10: 10 00 + 6f12: 00 01 + 6f14: 32 03 + 6f16: 6e 05 + 6f18: 00 00 + 6f1a: 16 1a + 6f1c: 01 00 + 6f1e: 12 7d + 6f20: 10 00 + 6f22: 00 01 + 6f24: 32 03 + 6f26: 6e 05 + 6f28: 00 00 + 6f2a: 34 1a + 6f2c: 01 00 + 6f2e: 12 d4 + 6f30: 12 00 + 6f32: 00 01 + 6f34: 32 03 + 6f36: 89 01 + 6f38: 00 00 + 6f3a: 54 1a + 6f3c: 01 00 + 6f3e: 12 ea + 6f40: 12 00 + 6f42: 00 01 + 6f44: 32 03 + 6f46: 89 01 + 6f48: 00 00 + 6f4a: d7 1a 01 00 + 6f4e: 16 ac + 6f50: 53 01 80 0c + 6f54: 00 00 + 6f56: 00 df + 6f58: 04 00 + 6f5a: 00 14 + 6f5c: 5f 5f 78 00 + 6f60: 01 32 + 6f62: 03 89 01 00 lb s2, 0(gp) + 6f66: 00 00 + 6f68: 1b 01 00 00 + 6f6c: 16 20 + 6f6e: 54 01 + 6f70: 80 0c + 6f72: 00 00 + 6f74: 00 fd + 6f76: 04 00 + 6f78: 00 14 + 6f7a: 5f 5f 78 00 + 6f7e: 01 32 + 6f80: 03 89 01 00 lb s2, 0(gp) + 6f84: 00 26 + 6f86: 1b 01 00 00 + 6f8a: 1e 3c + 6f8c: 54 01 + 6f8e: 80 0c + 6f90: 00 00 + 6f92: 00 14 + 6f94: 5f 5f 78 00 + 6f98: 01 32 + 6f9a: 03 89 01 00 lb s2, 0(gp) + 6f9e: 00 4c + 6fa0: 1b 01 00 00 + 6fa4: 00 16 + 6fa6: e0 50 + 6fa8: 01 80 + 6faa: 04 00 + 6fac: 00 00 + 6fae: 32 05 + 6fb0: 00 00 + 6fb2: 13 5f 5f 78 + 6fb6: 00 01 + 6fb8: 32 03 + 6fba: 89 01 + 6fbc: 00 00 + 6fbe: 00 1c + 6fc0: 44 05 + 6fc2: 00 00 + 6fc4: 13 5f 5f 78 + 6fc8: 00 01 + 6fca: 32 03 + 6fcc: 89 01 + 6fce: 00 00 + 6fd0: 00 1a + 6fd2: 18 14 + 6fd4: 00 00 + 6fd6: 14 5f + 6fd8: 5f 78 00 01 + 6fdc: 32 03 + 6fde: 89 01 + 6fe0: 00 00 + 6fe2: 72 1b + 6fe4: 01 00 + 6fe6: 00 00 + 6fe8: 1a 48 + 6fea: 14 00 + 6fec: 00 1b + 6fee: 6c 08 + 6ff0: 00 00 + 6ff2: 01 32 + 6ff4: 03 e6 00 00 + 6ff8: 00 00 + 6ffa: 00 03 + 6ffc: 04 05 + 6ffe: f6 03 + 7000: 00 00 + 7002: 1f 89 01 00 + 7006: 00 07 + 7008: 53 00 00 00 fadd.s ft0, ft0, ft0, rne + 700c: 03 00 00 66 lb zero, 1632(zero) + 7010: 0b 00 00 04 + 7014: 00 a7 + 7016: 18 00 + 7018: 00 04 + 701a: 01 c8 + 701c: 09 00 + 701e: 00 0c + 7020: 6d 04 + 7022: 00 00 + 7024: d5 01 + 7026: 00 00 + 7028: 80 b1 + 702a: 00 00 + 702c: 02 04 + 702e: 05 69 + 7030: 6e 74 + 7032: 00 03 + 7034: 04 07 + 7036: d4 02 + 7038: 00 00 + 703a: 03 08 05 f1 lb a6, -240(a0) + 703e: 03 00 00 03 lb zero, 48(zero) + 7042: 10 04 + 7044: c0 00 + 7046: 00 00 + 7048: 03 01 06 ad lb sp, -1328(a2) + 704c: 06 00 + 704e: 00 03 + 7050: 01 08 + 7052: ab 06 00 00 + 7056: 03 02 05 00 lb tp, 0(a0) + 705a: 00 00 + 705c: 00 03 + 705e: 02 07 + 7060: ea 02 + 7062: 00 00 + 7064: 03 04 05 f6 lb s0, -160(a0) + 7068: 03 00 00 03 lb zero, 48(zero) + 706c: 04 07 + 706e: cf 02 00 00 fnmadd.s ft5, ft0, ft0, ft0, rne + 7072: 03 08 07 ca lb a6, -864(a4) + 7076: 02 00 + 7078: 00 04 + 707a: 4a 03 + 707c: 00 00 + 707e: 01 5e + 7080: 01 17 + 7082: 24 00 + 7084: 00 00 + 7086: 05 25 + 7088: 04 00 + 708a: 00 02 + 708c: 2e 0e + 708e: 55 00 + 7090: 00 00 + 7092: 05 33 + 7094: 06 00 + 7096: 00 02 + 7098: 74 0e + 709a: 55 00 + 709c: 00 00 + 709e: 05 15 + 70a0: 07 00 00 02 + 70a4: 93 17 1d 00 slli a5, s10, 1 + 70a8: 00 00 + 70aa: 06 04 + 70ac: 02 a5 + 70ae: 03 bd 00 00 + 70b2: 00 07 + 70b4: 31 03 + 70b6: 00 00 + 70b8: 02 a7 + 70ba: 0c 6a + 70bc: 00 00 + 70be: 00 07 + 70c0: 9c 02 + 70c2: 00 00 + 70c4: 02 a8 + 70c6: 13 bd 00 00 sltiu s10, ra, 0 + 70ca: 00 00 + 70cc: 08 40 + 70ce: 00 00 + 70d0: 00 cd + 70d2: 00 00 + 70d4: 00 09 + 70d6: 24 00 + 70d8: 00 00 + 70da: 03 00 0a 08 lb zero, 128(s4) + 70de: 02 a2 + 70e0: 09 f1 + 70e2: 00 00 + 70e4: 00 0b + 70e6: 9b 03 00 00 + 70ea: 02 a4 + 70ec: 07 1d 00 00 + 70f0: 00 00 + 70f2: 0b 25 06 00 + 70f6: 00 02 + 70f8: a9 05 + 70fa: 9b 00 00 00 + 70fe: 04 00 + 7100: 05 4a + 7102: 04 00 + 7104: 00 02 + 7106: aa 03 + 7108: cd 00 + 710a: 00 00 + 710c: 0c 04 + 710e: 05 be + 7110: 06 00 + 7112: 00 03 + 7114: 16 19 + 7116: 5c 00 + 7118: 00 00 + 711a: 05 55 + 711c: 04 00 + 711e: 00 04 + 7120: 0c 0d + 7122: 1d 00 + 7124: 00 00 + 7126: 05 cb + 7128: 04 00 + 712a: 00 03 + 712c: 23 1b 0b 01 sh a6, 22(s6) + 7130: 00 00 + 7132: 0d d4 + 7134: 03 00 00 18 lb zero, 384(zero) + 7138: 03 34 08 7d + 713c: 01 00 + 713e: 00 0b + 7140: d5 07 + 7142: 00 00 + 7144: 03 36 13 7d + 7148: 01 00 + 714a: 00 00 + 714c: 0e 5f + 714e: 6b 00 03 37 vx_tex zero, t1, a6, t1, rne + 7152: 07 1d 00 00 + 7156: 00 04 + 7158: 0b 02 06 00 + 715c: 00 03 + 715e: 37 0b 1d 00 lui s6, 464 + 7162: 00 00 + 7164: 08 0b + 7166: 40 02 + 7168: 00 00 + 716a: 03 37 14 1d + 716e: 00 00 + 7170: 00 0c + 7172: 0b 6b 01 00 + 7176: 00 03 + 7178: 37 1b 1d 00 lui s6, 465 + 717c: 00 00 + 717e: 10 0e + 7180: 5f 78 00 03 + 7184: 38 0b + 7186: 83 01 00 00 lb gp, 0(zero) + 718a: 14 00 + 718c: 0f 04 23 01 + 7190: 00 00 + 7192: 08 ff + 7194: 00 00 + 7196: 00 93 + 7198: 01 00 + 719a: 00 09 + 719c: 24 00 + 719e: 00 00 + 71a0: 00 00 + 71a2: 0d 7f + 71a4: 02 00 + 71a6: 00 24 + 71a8: 03 3c 08 16 + 71ac: 02 00 + 71ae: 00 0b + 71b0: f8 00 + 71b2: 00 00 + 71b4: 03 3e 09 1d + 71b8: 00 00 + 71ba: 00 00 + 71bc: 0b 73 07 00 + 71c0: 00 03 + 71c2: 3f 09 1d 00 + 71c6: 00 00 + 71c8: 04 0b + 71ca: 14 01 + 71cc: 00 00 + 71ce: 03 40 09 1d lbu zero, 464(s2) + 71d2: 00 00 + 71d4: 00 08 + 71d6: 0b c6 07 00 + 71da: 00 03 + 71dc: 41 09 + 71de: 1d 00 + 71e0: 00 00 + 71e2: 0c 0b + 71e4: ff 03 00 00 + 71e8: 03 42 09 1d lbu tp, 464(s2) + 71ec: 00 00 + 71ee: 00 10 + 71f0: 0b 91 03 00 + 71f4: 00 03 + 71f6: 43 09 1d 00 fmadd.s fs2, fs10, ft1, ft0, rne + 71fa: 00 00 + 71fc: 14 0b + 71fe: fe 06 + 7200: 00 00 + 7202: 03 44 09 1d lbu s0, 464(s2) + 7206: 00 00 + 7208: 00 18 + 720a: 0b d4 04 00 + 720e: 00 03 + 7210: 45 09 + 7212: 1d 00 + 7214: 00 00 + 7216: 1c 0b + 7218: 59 07 + 721a: 00 00 + 721c: 03 46 09 1d lbu a2, 464(s2) + 7220: 00 00 + 7222: 00 20 + 7224: 00 10 + 7226: 31 01 + 7228: 00 00 + 722a: 08 01 + 722c: 03 4f 08 5b lbu t5, 1456(a6) + 7230: 02 00 + 7232: 00 0b + 7234: 33 02 00 00 add tp, zero, zero + 7238: 03 50 0a 5b lhu zero, 1456(s4) + 723c: 02 00 + 723e: 00 00 + 7240: 0b a7 04 00 + 7244: 00 03 + 7246: 51 09 + 7248: 5b 02 00 00 + 724c: 80 11 + 724e: a2 06 + 7250: 00 00 + 7252: 03 53 0a ff lhu t1, -16(s4) + 7256: 00 00 + 7258: 00 00 + 725a: 01 11 + 725c: 63 01 00 00 beqz zero, 2 + 7260: 03 56 0a ff lhu a2, -16(s4) + 7264: 00 00 + 7266: 00 04 + 7268: 01 00 + 726a: 08 fd + 726c: 00 00 + 726e: 00 6b + 7270: 02 00 + 7272: 00 09 + 7274: 24 00 + 7276: 00 00 + 7278: 1f 00 10 08 + 727c: 04 00 + 727e: 00 90 + 7280: 01 03 + 7282: 62 08 + 7284: ae 02 + 7286: 00 00 + 7288: 0b d5 07 00 + 728c: 00 03 + 728e: 63 12 ae 02 bne t3, a0, 36 + 7292: 00 00 + 7294: 00 0b + 7296: e9 05 + 7298: 00 00 + 729a: 03 64 06 1d + 729e: 00 00 + 72a0: 00 04 + 72a2: 0b 3b 02 00 + 72a6: 00 03 + 72a8: 66 09 + 72aa: b4 02 + 72ac: 00 00 + 72ae: 08 0b + 72b0: 31 01 + 72b2: 00 00 + 72b4: 03 67 1e 16 + 72b8: 02 00 + 72ba: 00 88 + 72bc: 00 0f + 72be: 04 6b + 72c0: 02 00 + 72c2: 00 08 + 72c4: c4 02 + 72c6: 00 00 + 72c8: c4 02 + 72ca: 00 00 + 72cc: 09 24 + 72ce: 00 00 + 72d0: 00 1f + 72d2: 00 0f + 72d4: 04 ca + 72d6: 02 00 + 72d8: 00 12 + 72da: 0d bf + 72dc: 07 00 00 08 + 72e0: 03 7a 08 f3 + 72e4: 02 00 + 72e6: 00 0b + 72e8: 0e 01 + 72ea: 00 00 + 72ec: 03 7b 11 f3 + 72f0: 02 00 + 72f2: 00 00 + 72f4: 0b 1c 00 00 + 72f8: 00 03 + 72fa: 7c 06 + 72fc: 1d 00 + 72fe: 00 00 + 7300: 04 00 + 7302: 0f 04 40 00 + 7306: 00 00 + 7308: 0d c5 + 730a: 05 00 + 730c: 00 68 + 730e: 03 ba 08 3c + 7312: 04 00 + 7314: 00 0e + 7316: 5f 70 00 03 + 731a: bb 12 f3 02 + 731e: 00 00 + 7320: 00 0e + 7322: 5f 72 00 03 + 7326: bc 07 + 7328: 1d 00 + 732a: 00 00 + 732c: 04 0e + 732e: 5f 77 00 03 + 7332: bd 07 + 7334: 1d 00 + 7336: 00 00 + 7338: 08 0b + 733a: 5c 01 + 733c: 00 00 + 733e: 03 be 09 47 + 7342: 00 00 + 7344: 00 0c + 7346: 0b ab 02 00 + 734a: 00 03 + 734c: bf 09 47 00 + 7350: 00 00 + 7352: 0e 0e + 7354: 5f 62 66 00 + 7358: 03 c0 11 cb lbu zero, -847(gp) + 735c: 02 00 + 735e: 00 10 + 7360: 0b a8 00 00 + 7364: 00 03 + 7366: c1 07 + 7368: 1d 00 + 736a: 00 00 + 736c: 18 0b + 736e: 3f 01 00 00 + 7372: 03 c8 0a fd lbu a6, -48(s5) + 7376: 00 00 + 7378: 00 1c + 737a: 0b 67 04 00 + 737e: 00 03 + 7380: ca 1d + 7382: c0 05 + 7384: 00 00 + 7386: 20 0b + 7388: 8a 03 + 738a: 00 00 + 738c: 03 cc 1d ef lbu s8, -271(s11) + 7390: 05 00 + 7392: 00 24 + 7394: 0b 2d 06 00 + 7398: 00 03 + 739a: cf 0d 13 06 + 739e: 00 00 + 73a0: 28 0b + 73a2: 01 01 + 73a4: 00 00 + 73a6: 03 d0 09 2d lhu zero, 720(s3) + 73aa: 06 00 + 73ac: 00 2c + 73ae: 0e 5f + 73b0: 75 62 + 73b2: 00 03 + 73b4: d3 11 cb 02 + 73b8: 00 00 + 73ba: 30 0e + 73bc: 5f 75 70 00 + 73c0: 03 d4 12 f3 lhu s0, -207(t0) + 73c4: 02 00 + 73c6: 00 38 + 73c8: 0e 5f + 73ca: 75 72 + 73cc: 00 03 + 73ce: d5 07 + 73d0: 1d 00 + 73d2: 00 00 + 73d4: 3c 0b + 73d6: 08 01 + 73d8: 00 00 + 73da: 03 d8 11 33 lhu a6, 817(gp) + 73de: 06 00 + 73e0: 00 40 + 73e2: 0b 41 07 00 + 73e6: 00 03 + 73e8: d9 11 + 73ea: 43 06 00 00 fmadd.s fa2, ft0, ft0, ft0, rne + 73ee: 43 0e 5f 6c + 73f2: 62 00 + 73f4: 03 dc 11 cb lhu s8, -847(gp) + 73f8: 02 00 + 73fa: 00 44 + 73fc: 0b 44 06 00 + 7400: 00 03 + 7402: df 07 1d 00 + 7406: 00 00 + 7408: 4c 0b + 740a: cc 03 + 740c: 00 00 + 740e: 03 e0 0a 77 + 7412: 00 00 + 7414: 00 50 + 7416: 0b 5b 00 00 + 741a: 00 03 + 741c: e3 12 5a 04 bne s4, t0, 2116 + 7420: 00 00 + 7422: 54 0b + 7424: 51 03 + 7426: 00 00 + 7428: 03 e7 0c 17 + 742c: 01 00 + 742e: 00 58 + 7430: 0b 93 02 00 + 7434: 00 03 + 7436: e9 0e + 7438: f1 00 + 743a: 00 00 + 743c: 5c 0b + 743e: de 04 + 7440: 00 00 + 7442: 03 ea 09 1d + 7446: 00 00 + 7448: 00 64 + 744a: 00 13 + 744c: 8f 00 00 00 + 7450: 5a 04 + 7452: 00 00 + 7454: 14 5a + 7456: 04 00 + 7458: 00 14 + 745a: fd 00 + 745c: 00 00 + 745e: 14 ae + 7460: 05 00 + 7462: 00 14 + 7464: 1d 00 + 7466: 00 00 + 7468: 00 0f + 746a: 04 65 + 746c: 04 00 + 746e: 00 15 + 7470: 5a 04 + 7472: 00 00 + 7474: 16 0a + 7476: 06 00 + 7478: 00 28 + 747a: 04 03 + 747c: 65 02 + 747e: 08 ae + 7480: 05 00 + 7482: 00 17 + 7484: c4 04 + 7486: 00 00 + 7488: 03 67 02 07 + 748c: 1d 00 + 748e: 00 00 + 7490: 00 17 + 7492: 0e 07 + 7494: 00 00 + 7496: 03 6c 02 0b + 749a: 9f 06 00 00 + 749e: 04 17 + 74a0: f6 06 + 74a2: 00 00 + 74a4: 03 6c 02 14 + 74a8: 9f 06 00 00 + 74ac: 08 17 + 74ae: 46 02 + 74b0: 00 00 + 74b2: 03 6c 02 1e + 74b6: 9f 06 00 00 + 74ba: 0c 17 + 74bc: e4 05 + 74be: 00 00 + 74c0: 03 6e 02 08 + 74c4: 1d 00 + 74c6: 00 00 + 74c8: 10 17 + 74ca: 2a 00 + 74cc: 00 00 + 74ce: 03 6f 02 08 + 74d2: 9f 08 00 00 + 74d6: 14 17 + 74d8: 66 02 + 74da: 00 00 + 74dc: 03 72 02 07 + 74e0: 1d 00 + 74e2: 00 00 + 74e4: 30 17 + 74e6: af 07 00 00 + 74ea: 03 73 02 16 + 74ee: b4 08 + 74f0: 00 00 + 74f2: 34 17 + 74f4: 1a 04 + 74f6: 00 00 + 74f8: 03 75 02 07 + 74fc: 1d 00 + 74fe: 00 00 + 7500: 38 17 + 7502: f8 05 + 7504: 00 00 + 7506: 03 77 02 0a + 750a: c5 08 + 750c: 00 00 + 750e: 3c 17 + 7510: 29 03 + 7512: 00 00 + 7514: 03 7a 02 13 + 7518: 7d 01 + 751a: 00 00 + 751c: 40 17 + 751e: 77 01 00 00 + 7522: 03 7b 02 07 + 7526: 1d 00 + 7528: 00 00 + 752a: 44 17 + 752c: aa 07 + 752e: 00 00 + 7530: 03 7c 02 13 + 7534: 7d 01 + 7536: 00 00 + 7538: 48 17 + 753a: 36 04 + 753c: 00 00 + 753e: 03 7d 02 14 + 7542: cb 08 00 00 fnmsub.s fa7, ft0, ft0, ft0, rne + 7546: 4c 17 + 7548: a3 02 00 00 sb zero, 5(zero) + 754c: 03 80 02 07 lb zero, 112(t0) + 7550: 1d 00 + 7552: 00 00 + 7554: 50 17 + 7556: ae 01 + 7558: 00 00 + 755a: 03 81 02 09 lb sp, 144(t0) + 755e: ae 05 + 7560: 00 00 + 7562: 54 17 + 7564: bd 04 + 7566: 00 00 + 7568: 03 a4 02 07 lw s0, 112(t0) + 756c: 7a 08 + 756e: 00 00 + 7570: 58 18 + 7572: 08 04 + 7574: 00 00 + 7576: 03 a8 02 13 lw a6, 304(t0) + 757a: ae 02 + 757c: 00 00 + 757e: 48 01 + 7580: 18 07 + 7582: 03 00 00 03 lb zero, 48(zero) + 7586: a9 02 + 7588: 12 6b + 758a: 02 00 + 758c: 00 4c + 758e: 01 18 + 7590: 28 07 + 7592: 00 00 + 7594: 03 ad 02 0c lw s10, 192(t0) + 7598: dc 08 + 759a: 00 00 + 759c: dc 02 + 759e: 18 47 + 75a0: 01 00 + 75a2: 00 03 + 75a4: b2 02 + 75a6: 10 60 + 75a8: 06 00 + 75aa: 00 e0 + 75ac: 02 18 + 75ae: 2c 01 + 75b0: 00 00 + 75b2: 03 b4 02 0a + 75b6: e8 08 + 75b8: 00 00 + 75ba: ec 02 + 75bc: 00 0f + 75be: 04 b4 + 75c0: 05 00 + 75c2: 00 03 + 75c4: 01 08 + 75c6: b4 06 + 75c8: 00 00 + 75ca: 15 b4 + 75cc: 05 00 + 75ce: 00 0f + 75d0: 04 3c + 75d2: 04 00 + 75d4: 00 13 + 75d6: 8f 00 00 00 + 75da: e4 05 + 75dc: 00 00 + 75de: 14 5a + 75e0: 04 00 + 75e2: 00 14 + 75e4: fd 00 + 75e6: 00 00 + 75e8: 14 e4 + 75ea: 05 00 + 75ec: 00 14 + 75ee: 1d 00 + 75f0: 00 00 + 75f2: 00 0f + 75f4: 04 bb + 75f6: 05 00 + 75f8: 00 15 + 75fa: e4 05 + 75fc: 00 00 + 75fe: 0f 04 c6 05 + 7602: 00 00 + 7604: 13 83 00 00 mv t1, ra + 7608: 00 13 + 760a: 06 00 + 760c: 00 14 + 760e: 5a 04 + 7610: 00 00 + 7612: 14 fd + 7614: 00 00 + 7616: 00 14 + 7618: 83 00 00 00 lb ra, 0(zero) + 761c: 14 1d + 761e: 00 00 + 7620: 00 00 + 7622: 0f 04 f5 05 + 7626: 00 00 + 7628: 13 1d 00 00 slli s10, zero, 0 + 762c: 00 2d + 762e: 06 00 + 7630: 00 14 + 7632: 5a 04 + 7634: 00 00 + 7636: 14 fd + 7638: 00 00 + 763a: 00 00 + 763c: 0f 04 19 06 + 7640: 00 00 + 7642: 08 40 + 7644: 00 00 + 7646: 00 43 + 7648: 06 00 + 764a: 00 09 + 764c: 24 00 + 764e: 00 00 + 7650: 02 00 + 7652: 08 40 + 7654: 00 00 + 7656: 00 53 + 7658: 06 00 + 765a: 00 09 + 765c: 24 00 + 765e: 00 00 + 7660: 00 00 + 7662: 04 70 + 7664: 01 00 + 7666: 00 03 + 7668: 24 01 + 766a: 1a f9 + 766c: 02 00 + 766e: 00 19 + 7670: 08 07 + 7672: 00 00 + 7674: 0c 03 + 7676: 28 01 + 7678: 08 99 + 767a: 06 00 + 767c: 00 17 + 767e: d5 07 + 7680: 00 00 + 7682: 03 2a 01 11 lw s4, 272(sp) + 7686: 99 06 + 7688: 00 00 + 768a: 00 17 + 768c: c3 02 00 00 fmadd.s ft5, ft0, ft0, ft0, rne + 7690: 03 2b 01 07 lw s6, 112(sp) + 7694: 1d 00 + 7696: 00 00 + 7698: 04 17 + 769a: e6 04 + 769c: 00 00 + 769e: 03 2c 01 0b lw s8, 176(sp) + 76a2: 9f 06 00 00 + 76a6: 08 00 + 76a8: 0f 04 60 06 + 76ac: 00 00 + 76ae: 0f 04 53 06 + 76b2: 00 00 + 76b4: 19 22 + 76b6: 00 00 + 76b8: 00 0e + 76ba: 03 44 01 08 lbu s0, 128(sp) + 76be: de 06 + 76c0: 00 00 + 76c2: 17 72 06 00 auipc tp, 103 + 76c6: 00 03 + 76c8: 45 01 + 76ca: 12 de + 76cc: 06 00 + 76ce: 00 00 + 76d0: 17 67 03 00 auipc a4, 54 + 76d4: 00 03 + 76d6: 46 01 + 76d8: 12 de + 76da: 06 00 + 76dc: 00 06 + 76de: 17 b9 06 00 auipc s2, 107 + 76e2: 00 03 + 76e4: 47 01 12 4e + 76e8: 00 00 + 76ea: 00 0c + 76ec: 00 08 + 76ee: 4e 00 + 76f0: 00 00 + 76f2: ee 06 + 76f4: 00 00 + 76f6: 09 24 + 76f8: 00 00 + 76fa: 00 02 + 76fc: 00 1a + 76fe: d0 03 + 7700: 85 02 + 7702: 07 03 08 00 + 7706: 00 17 + 7708: a3 03 00 00 sb zero, 7(zero) + 770c: 03 87 02 18 lb a4, 384(t0) + 7710: 24 00 + 7712: 00 00 + 7714: 00 17 + 7716: 8e 06 + 7718: 00 00 + 771a: 03 88 02 12 lb a6, 288(t0) + 771e: ae 05 + 7720: 00 00 + 7722: 04 17 + 7724: 1c 03 + 7726: 00 00 + 7728: 03 89 02 10 lb s2, 256(t0) + 772c: 03 08 00 00 lb a6, 0(zero) + 7730: 08 17 + 7732: 64 07 + 7734: 00 00 + 7736: 03 8a 02 17 lb s4, 368(t0) + 773a: 93 01 00 00 mv gp, zero + 773e: 24 17 + 7740: 4e 02 + 7742: 00 00 + 7744: 03 8b 02 0f lb s6, 240(t0) + 7748: 1d 00 + 774a: 00 00 + 774c: 48 17 + 774e: d0 07 + 7750: 00 00 + 7752: 03 8c 02 2c lb s8, 704(t0) + 7756: 63 00 00 00 beqz zero, 0 + 775a: 50 17 + 775c: 7c 07 + 775e: 00 00 + 7760: 03 8d 02 1a lb s10, 416(t0) + 7764: a5 06 + 7766: 00 00 + 7768: 58 17 + 776a: d7 05 00 00 + 776e: 03 8e 02 16 lb t3, 352(t0) + 7772: f1 00 + 7774: 00 00 + 7776: 68 17 + 7778: 9c 07 + 777a: 00 00 + 777c: 03 8f 02 16 lb t5, 352(t0) + 7780: f1 00 + 7782: 00 00 + 7784: 70 17 + 7786: 1e 01 + 7788: 00 00 + 778a: 03 90 02 16 lh zero, 352(t0) + 778e: f1 00 + 7790: 00 00 + 7792: 78 17 + 7794: 1e 07 + 7796: 00 00 + 7798: 03 91 02 10 lh sp, 256(t0) + 779c: 13 08 00 00 mv a6, zero + 77a0: 80 17 + 77a2: 10 03 + 77a4: 00 00 + 77a6: 03 92 02 10 lh tp, 256(t0) + 77aa: 23 08 00 00 sb zero, 16(zero) + 77ae: 88 17 + 77b0: 4e 00 + 77b2: 00 00 + 77b4: 03 93 02 0f lh t1, 240(t0) + 77b8: 1d 00 + 77ba: 00 00 + 77bc: a0 17 + 77be: c7 01 00 00 fmsub.s ft3, ft0, ft0, ft0, rne + 77c2: 03 94 02 16 lh s0, 352(t0) + 77c6: f1 00 + 77c8: 00 00 + 77ca: a4 17 + 77cc: e1 00 + 77ce: 00 00 + 77d0: 03 95 02 16 lh a0, 352(t0) + 77d4: f1 00 + 77d6: 00 00 + 77d8: ac 17 + 77da: b6 01 + 77dc: 00 00 + 77de: 03 96 02 16 lh a2, 352(t0) + 77e2: f1 00 + 77e4: 00 00 + 77e6: b4 17 + 77e8: 61 00 + 77ea: 00 00 + 77ec: 03 97 02 16 lh a4, 352(t0) + 77f0: f1 00 + 77f2: 00 00 + 77f4: bc 17 + 77f6: 8d 00 + 77f8: 00 00 + 77fa: 03 98 02 16 lh a6, 352(t0) + 77fe: f1 00 + 7800: 00 00 + 7802: c4 17 + 7804: c2 04 + 7806: 00 00 + 7808: 03 99 02 08 lh s2, 128(t0) + 780c: 1d 00 + 780e: 00 00 + 7810: cc 00 + 7812: 08 b4 + 7814: 05 00 + 7816: 00 13 + 7818: 08 00 + 781a: 00 09 + 781c: 24 00 + 781e: 00 00 + 7820: 19 00 + 7822: 08 b4 + 7824: 05 00 + 7826: 00 23 + 7828: 08 00 + 782a: 00 09 + 782c: 24 00 + 782e: 00 00 + 7830: 07 00 08 b4 + 7834: 05 00 + 7836: 00 33 + 7838: 08 00 + 783a: 00 09 + 783c: 24 00 + 783e: 00 00 + 7840: 17 00 1a f0 auipc zero, 983456 + 7844: 03 9e 02 07 lh t3, 112(t0) + 7848: 5a 08 + 784a: 00 00 + 784c: 17 dc 03 00 auipc s8, 61 + 7850: 00 03 + 7852: a1 02 + 7854: 1b 5a 08 00 + 7858: 00 00 + 785a: 17 5d 02 00 auipc s10, 37 + 785e: 00 03 + 7860: a2 02 + 7862: 18 6a + 7864: 08 00 + 7866: 00 78 + 7868: 00 08 + 786a: f3 02 00 00 + 786e: 6a 08 + 7870: 00 00 + 7872: 09 24 + 7874: 00 00 + 7876: 00 1d + 7878: 00 08 + 787a: 24 00 + 787c: 00 00 + 787e: 7a 08 + 7880: 00 00 + 7882: 09 24 + 7884: 00 00 + 7886: 00 1d + 7888: 00 1b + 788a: f0 03 + 788c: 83 02 03 9f lb t0, -1552(t1) + 7890: 08 00 + 7892: 00 1c + 7894: 0a 06 + 7896: 00 00 + 7898: 03 9a 02 0b lh s4, 176(t0) + 789c: ee 06 + 789e: 00 00 + 78a0: 1c 47 + 78a2: 07 00 00 03 + 78a6: a3 02 0b 33 sb a6, 805(s6) + 78aa: 08 00 + 78ac: 00 00 + 78ae: 08 b4 + 78b0: 05 00 + 78b2: 00 af + 78b4: 08 00 + 78b6: 00 09 + 78b8: 24 00 + 78ba: 00 00 + 78bc: 18 00 + 78be: 1d d6 + 78c0: 00 00 + 78c2: 00 0f + 78c4: 04 af + 78c6: 08 00 + 78c8: 00 1e + 78ca: c5 08 + 78cc: 00 00 + 78ce: 14 5a + 78d0: 04 00 + 78d2: 00 00 + 78d4: 0f 04 ba 08 + 78d8: 00 00 + 78da: 0f 04 7d 01 + 78de: 00 00 + 78e0: 1e dc + 78e2: 08 00 + 78e4: 00 14 + 78e6: 1d 00 + 78e8: 00 00 + 78ea: 00 0f + 78ec: 04 e2 + 78ee: 08 00 + 78f0: 00 0f + 78f2: 04 d1 + 78f4: 08 00 + 78f6: 00 08 + 78f8: 53 06 00 00 fadd.s fa2, ft0, ft0, rne + 78fc: f8 08 + 78fe: 00 00 + 7900: 09 24 + 7902: 00 00 + 7904: 00 02 + 7906: 00 1f + 7908: e2 06 + 790a: 00 00 + 790c: 03 33 03 17 + 7910: 5a 04 + 7912: 00 00 + 7914: 1f db 06 00 + 7918: 00 03 + 791a: 34 03 + 791c: 1d 60 + 791e: 04 00 + 7920: 00 08 + 7922: ea 05 + 7924: 00 00 + 7926: 1d 09 + 7928: 00 00 + 792a: 20 00 + 792c: 15 12 + 792e: 09 00 + 7930: 00 21 + 7932: a1 01 + 7934: 00 00 + 7936: 05 14 + 7938: 24 1d + 793a: 09 00 + 793c: 00 21 + 793e: cd 05 + 7940: 00 00 + 7942: 05 15 + 7944: 15 1d + 7946: 00 00 + 7948: 00 0f + 794a: 04 40 + 794c: 09 00 + 794e: 00 13 + 7950: 1d 00 + 7952: 00 00 + 7954: 54 09 + 7956: 00 00 + 7958: 14 54 + 795a: 09 00 + 795c: 00 14 + 795e: 54 09 + 7960: 00 00 + 7962: 00 0f + 7964: 04 5a + 7966: 09 00 + 7968: 00 22 + 796a: 21 10 + 796c: 04 00 + 796e: 00 06 + 7970: 67 0e ae 05 jalr t3, 90(t3) + 7974: 00 00 + 7976: 21 42 + 7978: 03 00 00 07 lb zero, 112(zero) + 797c: 10 0f + 797e: 73 09 00 00 + 7982: 0f 04 ae 05 + 7986: 00 00 + 7988: 21 13 + 798a: 04 00 + 798c: 00 07 + 798e: fc 0e + 7990: ae 05 + 7992: 00 00 + 7994: 21 b1 + 7996: 00 00 + 7998: 00 07 + 799a: fd 0c + 799c: 1d 00 + 799e: 00 00 + 79a0: 21 78 + 79a2: 06 00 + 79a4: 00 07 + 79a6: fd 14 + 79a8: 1d 00 + 79aa: 00 00 + 79ac: 21 8b + 79ae: 07 00 00 07 + 79b2: fd 1c + 79b4: 1d 00 + 79b6: 00 00 + 79b8: 21 81 + 79ba: 03 00 00 07 lb zero, 112(zero) + 79be: ff 0c 1d 00 + 79c2: 00 00 + 79c4: 21 40 + 79c6: 04 00 + 79c8: 00 08 + 79ca: 9a 16 + 79cc: 55 00 + 79ce: 00 00 + 79d0: 21 35 + 79d2: 00 00 + 79d4: 00 08 + 79d6: 9b 15 1d 00 + 79da: 00 00 + 79dc: 08 ae + 79de: 05 00 + 79e0: 00 dd + 79e2: 09 00 + 79e4: 00 09 + 79e6: 24 00 + 79e8: 00 00 + 79ea: 01 00 + 79ec: 21 f0 + 79ee: 00 00 + 79f0: 00 08 + 79f2: 9e 17 + 79f4: cd 09 + 79f6: 00 00 + 79f8: 05 b1 + 79fa: 02 00 + 79fc: 00 09 + 79fe: 2a 16 + 7a00: 24 00 + 7a02: 00 00 + 7a04: 05 bb + 7a06: 05 00 + 7a08: 00 09 + 7a0a: 2f 15 01 0a + 7a0e: 00 00 + 7a10: 0f 04 07 0a + 7a14: 00 00 + 7a16: 13 e9 09 00 ori s2, s3, 0 + 7a1a: 00 16 + 7a1c: 0a 00 + 7a1e: 00 14 + 7a20: 54 09 + 7a22: 00 00 + 7a24: 00 05 + 7a26: db 07 00 00 + 7a2a: 09 36 + 7a2c: 0f 3a 09 00 + 7a30: 00 21 + 7a32: 0a 00 + 7a34: 00 00 + 7a36: 09 bb + 7a38: 12 f5 + 7a3a: 09 00 + 7a3c: 00 21 + 7a3e: c6 06 + 7a40: 00 00 + 7a42: 09 be + 7a44: 10 16 + 7a46: 0a 00 + 7a48: 00 23 + 7a4a: 84 02 + 7a4c: 00 00 + 7a4e: 07 04 24 00 + 7a52: 00 00 + 7a54: 0a 18 + 7a56: 06 77 + 7a58: 0a 00 + 7a5a: 00 24 + 7a5c: 9d 04 + 7a5e: 00 00 + 7a60: 00 24 + 7a62: 5c 03 + 7a64: 00 00 + 7a66: 01 24 + 7a68: 37 03 00 00 lui t1, 0 + 7a6c: 02 24 + 7a6e: b0 03 + 7a70: 00 00 + 7a72: 03 24 94 04 lw s0, 73(s0) + 7a76: 00 00 + 7a78: 04 24 + 7a7a: 92 07 + 7a7c: 00 00 + 7a7e: 05 24 + 7a80: 81 07 + 7a82: 00 00 + 7a84: 06 00 + 7a86: 21 cc + 7a88: 00 00 + 7a8a: 00 0a + 7a8c: 21 1c + 7a8e: 3a 0a + 7a90: 00 00 + 7a92: 23 bb 03 00 + 7a96: 00 07 + 7a98: 04 24 + 7a9a: 00 00 + 7a9c: 00 0a + 7a9e: 23 06 a8 0a sb a0, 172(a6) + 7aa2: 00 00 + 7aa4: 24 b1 + 7aa6: 05 00 + 7aa8: 00 00 + 7aaa: 24 b3 + 7aac: 04 00 + 7aae: 00 01 + 7ab0: 24 9b + 7ab2: 06 00 + 7ab4: 00 02 + 7ab6: 00 21 + 7ab8: 4f 01 00 00 fnmadd.s ft2, ft0, ft0, ft0, rne + 7abc: 0a 28 + 7abe: 1e 83 + 7ac0: 0a 00 + 7ac2: 00 23 + 7ac4: 70 00 + 7ac6: 00 00 + 7ac8: 07 04 24 00 + 7acc: 00 00 + 7ace: 0a 2b + 7ad0: 06 d3 + 7ad2: 0a 00 + 7ad4: 00 24 + 7ad6: 4d 06 + 7ad8: 00 00 + 7ada: 00 24 + 7adc: 3b 06 00 00 + 7ae0: 01 00 + 7ae2: 21 89 + 7ae4: 01 00 + 7ae6: 00 0a + 7ae8: 2f 2a b4 0a + 7aec: 00 00 + 7aee: 21 72 + 7af0: 03 00 00 0b lb zero, 176(zero) + 7af4: 29 1a + 7af6: 1d 09 + 7af8: 00 00 + 7afa: 21 62 + 7afc: 06 00 + 7afe: 00 0b + 7b00: 38 1a + 7b02: 1d 09 + 7b04: 00 00 + 7b06: 05 b7 + 7b08: 07 00 00 0c + 7b0c: 7b 16 40 00 + 7b10: 00 00 + 7b12: 15 f7 + 7b14: 0a 00 + 7b16: 00 03 + 7b18: 04 04 + 7b1a: eb 03 00 00 vx_tex t2, zero, zero, zero, rne + 7b1e: 03 08 03 e3 lb a6, -464(t1) + 7b22: 03 00 00 03 lb zero, 48(zero) + 7b26: 08 04 + 7b28: c5 00 + 7b2a: 00 00 + 7b2c: 03 10 03 3f lh zero, 1008(t1) + 7b30: 00 00 + 7b32: 00 03 + 7b34: 20 03 + 7b36: b8 00 + 7b38: 00 00 + 7b3a: 08 03 + 7b3c: 0b 00 00 3b + 7b40: 0b 00 00 09 + 7b44: 24 00 + 7b46: 00 00 + 7b48: ff 00 15 2b + 7b4c: 0b 00 00 1f + 7b50: 32 07 + 7b52: 00 00 + 7b54: 0c fc + 7b56: 01 16 + 7b58: 3b 0b 00 00 + 7b5c: 1f fd 02 00 + 7b60: 00 0c + 7b62: 02 02 + 7b64: 16 3b + 7b66: 0b 00 00 25 + 7b6a: 4d 0b + 7b6c: 00 00 + 7b6e: 0d b2 + 7b70: 02 0f + 7b72: 05 03 + 7b74: 98 60 + 7b76: 01 80 + 7b78: 00 d3 + 7b7a: 0b 00 00 04 + 7b7e: 00 8f + 7b80: 1a 00 + 7b82: 00 04 + 7b84: 01 c8 + 7b86: 09 00 + 7b88: 00 0c + 7b8a: 6d 04 + 7b8c: 00 00 + 7b8e: d5 01 + 7b90: 00 00 + 7b92: c8 54 + 7b94: 01 80 + 7b96: 4c 00 + 7b98: 00 00 + 7b9a: a5 b3 + 7b9c: 00 00 + 7b9e: 02 04 + 7ba0: 05 69 + 7ba2: 6e 74 + 7ba4: 00 03 + 7ba6: 04 07 + 7ba8: d4 02 + 7baa: 00 00 + 7bac: 03 08 05 f1 lb a6, -240(a0) + 7bb0: 03 00 00 03 lb zero, 48(zero) + 7bb4: 10 04 + 7bb6: c0 00 + 7bb8: 00 00 + 7bba: 03 01 06 ad lb sp, -1328(a2) + 7bbe: 06 00 + 7bc0: 00 03 + 7bc2: 01 08 + 7bc4: ab 06 00 00 + 7bc8: 03 02 05 00 lb tp, 0(a0) + 7bcc: 00 00 + 7bce: 00 03 + 7bd0: 02 07 + 7bd2: ea 02 + 7bd4: 00 00 + 7bd6: 03 04 05 f6 lb s0, -160(a0) + 7bda: 03 00 00 03 lb zero, 48(zero) + 7bde: 04 07 + 7be0: cf 02 00 00 fnmadd.s ft5, ft0, ft0, ft0, rne + 7be4: 03 08 07 ca lb a6, -864(a4) + 7be8: 02 00 + 7bea: 00 04 + 7bec: 4a 03 + 7bee: 00 00 + 7bf0: 02 5e + 7bf2: 01 17 + 7bf4: 2c 00 + 7bf6: 00 00 + 7bf8: 05 25 + 7bfa: 04 00 + 7bfc: 00 03 + 7bfe: 2e 0e + 7c00: 5d 00 + 7c02: 00 00 + 7c04: 05 33 + 7c06: 06 00 + 7c08: 00 03 + 7c0a: 74 0e + 7c0c: 5d 00 + 7c0e: 00 00 + 7c10: 05 15 + 7c12: 07 00 00 03 + 7c16: 93 17 25 00 slli a5, a0, 2 + 7c1a: 00 00 + 7c1c: 06 04 + 7c1e: 03 a5 03 c5 lw a0, -944(t2) + 7c22: 00 00 + 7c24: 00 07 + 7c26: 31 03 + 7c28: 00 00 + 7c2a: 03 a7 0c 72 lw a4, 1824(s9) + 7c2e: 00 00 + 7c30: 00 07 + 7c32: 9c 02 + 7c34: 00 00 + 7c36: 03 a8 13 c5 lw a6, -943(t2) + 7c3a: 00 00 + 7c3c: 00 00 + 7c3e: 08 48 + 7c40: 00 00 + 7c42: 00 d5 + 7c44: 00 00 + 7c46: 00 09 + 7c48: 2c 00 + 7c4a: 00 00 + 7c4c: 03 00 0a 08 lb zero, 128(s4) + 7c50: 03 a2 09 f9 lw tp, -112(s3) + 7c54: 00 00 + 7c56: 00 0b + 7c58: 9b 03 00 00 + 7c5c: 03 a4 07 25 lw s0, 592(a5) + 7c60: 00 00 + 7c62: 00 00 + 7c64: 0b 25 06 00 + 7c68: 00 03 + 7c6a: a9 05 + 7c6c: a3 00 00 00 sb zero, 1(zero) + 7c70: 04 00 + 7c72: 05 4a + 7c74: 04 00 + 7c76: 00 03 + 7c78: aa 03 + 7c7a: d5 00 + 7c7c: 00 00 + 7c7e: 0c 04 + 7c80: 05 be + 7c82: 06 00 + 7c84: 00 04 + 7c86: 16 19 + 7c88: 64 00 + 7c8a: 00 00 + 7c8c: 05 55 + 7c8e: 04 00 + 7c90: 00 05 + 7c92: 0c 0d + 7c94: 25 00 + 7c96: 00 00 + 7c98: 05 cb + 7c9a: 04 00 + 7c9c: 00 04 + 7c9e: 23 1b 13 01 sh a7, 22(t1) + 7ca2: 00 00 + 7ca4: 0d d4 + 7ca6: 03 00 00 18 lb zero, 384(zero) + 7caa: 04 34 + 7cac: 08 85 + 7cae: 01 00 + 7cb0: 00 0b + 7cb2: d5 07 + 7cb4: 00 00 + 7cb6: 04 36 + 7cb8: 13 85 01 00 mv a0, gp + 7cbc: 00 00 + 7cbe: 0e 5f + 7cc0: 6b 00 04 37 vx_tex zero, s0, a6, t1, rne + 7cc4: 07 25 00 00 flw fa0, 0(zero) + 7cc8: 00 04 + 7cca: 0b 02 06 00 + 7cce: 00 04 + 7cd0: 37 0b 25 00 lui s6, 592 + 7cd4: 00 00 + 7cd6: 08 0b + 7cd8: 40 02 + 7cda: 00 00 + 7cdc: 04 37 + 7cde: 14 25 + 7ce0: 00 00 + 7ce2: 00 0c + 7ce4: 0b 6b 01 00 + 7ce8: 00 04 + 7cea: 37 1b 25 00 lui s6, 593 + 7cee: 00 00 + 7cf0: 10 0e + 7cf2: 5f 78 00 04 + 7cf6: 38 0b + 7cf8: 8b 01 00 00 + 7cfc: 14 00 + 7cfe: 0f 04 2b 01 + 7d02: 00 00 + 7d04: 08 07 + 7d06: 01 00 + 7d08: 00 9b + 7d0a: 01 00 + 7d0c: 00 09 + 7d0e: 2c 00 + 7d10: 00 00 + 7d12: 00 00 + 7d14: 0d 7f + 7d16: 02 00 + 7d18: 00 24 + 7d1a: 04 3c + 7d1c: 08 1e + 7d1e: 02 00 + 7d20: 00 0b + 7d22: f8 00 + 7d24: 00 00 + 7d26: 04 3e + 7d28: 09 25 + 7d2a: 00 00 + 7d2c: 00 00 + 7d2e: 0b 73 07 00 + 7d32: 00 04 + 7d34: 3f 09 25 00 + 7d38: 00 00 + 7d3a: 04 0b + 7d3c: 14 01 + 7d3e: 00 00 + 7d40: 04 40 + 7d42: 09 25 + 7d44: 00 00 + 7d46: 00 08 + 7d48: 0b c6 07 00 + 7d4c: 00 04 + 7d4e: 41 09 + 7d50: 25 00 + 7d52: 00 00 + 7d54: 0c 0b + 7d56: ff 03 00 00 + 7d5a: 04 42 + 7d5c: 09 25 + 7d5e: 00 00 + 7d60: 00 10 + 7d62: 0b 91 03 00 + 7d66: 00 04 + 7d68: 43 09 25 00 fmadd.s fs2, fa0, ft2, ft0, rne + 7d6c: 00 00 + 7d6e: 14 0b + 7d70: fe 06 + 7d72: 00 00 + 7d74: 04 44 + 7d76: 09 25 + 7d78: 00 00 + 7d7a: 00 18 + 7d7c: 0b d4 04 00 + 7d80: 00 04 + 7d82: 45 09 + 7d84: 25 00 + 7d86: 00 00 + 7d88: 1c 0b + 7d8a: 59 07 + 7d8c: 00 00 + 7d8e: 04 46 + 7d90: 09 25 + 7d92: 00 00 + 7d94: 00 20 + 7d96: 00 10 + 7d98: 31 01 + 7d9a: 00 00 + 7d9c: 08 01 + 7d9e: 04 4f + 7da0: 08 63 + 7da2: 02 00 + 7da4: 00 0b + 7da6: 33 02 00 00 add tp, zero, zero + 7daa: 04 50 + 7dac: 0a 63 + 7dae: 02 00 + 7db0: 00 00 + 7db2: 0b a7 04 00 + 7db6: 00 04 + 7db8: 51 09 + 7dba: 63 02 00 00 beqz zero, 4 + 7dbe: 80 11 + 7dc0: a2 06 + 7dc2: 00 00 + 7dc4: 04 53 + 7dc6: 0a 07 + 7dc8: 01 00 + 7dca: 00 00 + 7dcc: 01 11 + 7dce: 63 01 00 00 beqz zero, 2 + 7dd2: 04 56 + 7dd4: 0a 07 + 7dd6: 01 00 + 7dd8: 00 04 + 7dda: 01 00 + 7ddc: 08 05 + 7dde: 01 00 + 7de0: 00 73 + 7de2: 02 00 + 7de4: 00 09 + 7de6: 2c 00 + 7de8: 00 00 + 7dea: 1f 00 10 08 + 7dee: 04 00 + 7df0: 00 90 + 7df2: 01 04 + 7df4: 62 08 + 7df6: b6 02 + 7df8: 00 00 + 7dfa: 0b d5 07 00 + 7dfe: 00 04 + 7e00: 63 12 b6 02 bne a2, a1, 36 + 7e04: 00 00 + 7e06: 00 0b + 7e08: e9 05 + 7e0a: 00 00 + 7e0c: 04 64 + 7e0e: 06 25 + 7e10: 00 00 + 7e12: 00 04 + 7e14: 0b 3b 02 00 + 7e18: 00 04 + 7e1a: 66 09 + 7e1c: bc 02 + 7e1e: 00 00 + 7e20: 08 0b + 7e22: 31 01 + 7e24: 00 00 + 7e26: 04 67 + 7e28: 1e 1e + 7e2a: 02 00 + 7e2c: 00 88 + 7e2e: 00 0f + 7e30: 04 73 + 7e32: 02 00 + 7e34: 00 08 + 7e36: cc 02 + 7e38: 00 00 + 7e3a: cc 02 + 7e3c: 00 00 + 7e3e: 09 2c + 7e40: 00 00 + 7e42: 00 1f + 7e44: 00 0f + 7e46: 04 d2 + 7e48: 02 00 + 7e4a: 00 12 + 7e4c: 0d bf + 7e4e: 07 00 00 08 + 7e52: 04 7a + 7e54: 08 fb + 7e56: 02 00 + 7e58: 00 0b + 7e5a: 0e 01 + 7e5c: 00 00 + 7e5e: 04 7b + 7e60: 11 fb + 7e62: 02 00 + 7e64: 00 00 + 7e66: 0b 1c 00 00 + 7e6a: 00 04 + 7e6c: 7c 06 + 7e6e: 25 00 + 7e70: 00 00 + 7e72: 04 00 + 7e74: 0f 04 48 00 + 7e78: 00 00 + 7e7a: 0d c5 + 7e7c: 05 00 + 7e7e: 00 68 + 7e80: 04 ba + 7e82: 08 44 + 7e84: 04 00 + 7e86: 00 0e + 7e88: 5f 70 00 04 + 7e8c: bb 12 fb 02 + 7e90: 00 00 + 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8558: 2c 00 + 855a: 00 00 + 855c: 01 00 + 855e: 21 f0 + 8560: 00 00 + 8562: 00 09 + 8564: 9e 17 + 8566: d5 09 + 8568: 00 00 + 856a: 05 b1 + 856c: 02 00 + 856e: 00 0a + 8570: 2a 16 + 8572: 2c 00 + 8574: 00 00 + 8576: 05 bb + 8578: 05 00 + 857a: 00 0a + 857c: 2f 15 09 0a + 8580: 00 00 + 8582: 0f 04 0f 0a + 8586: 00 00 + 8588: 13 f1 09 00 andi sp, s3, 0 + 858c: 00 1e + 858e: 0a 00 + 8590: 00 14 + 8592: 5c 09 + 8594: 00 00 + 8596: 00 05 + 8598: db 07 00 00 + 859c: 0a 36 + 859e: 0f 42 09 00 + 85a2: 00 21 + 85a4: 0a 00 + 85a6: 00 00 + 85a8: 0a bb + 85aa: 12 fd + 85ac: 09 00 + 85ae: 00 21 + 85b0: c6 06 + 85b2: 00 00 + 85b4: 0a be + 85b6: 10 1e + 85b8: 0a 00 + 85ba: 00 23 + 85bc: 84 02 + 85be: 00 00 + 85c0: 07 04 2c 00 + 85c4: 00 00 + 85c6: 0b 18 06 7f + 85ca: 0a 00 + 85cc: 00 24 + 85ce: 9d 04 + 85d0: 00 00 + 85d2: 00 24 + 85d4: 5c 03 + 85d6: 00 00 + 85d8: 01 24 + 85da: 37 03 00 00 lui t1, 0 + 85de: 02 24 + 85e0: b0 03 + 85e2: 00 00 + 85e4: 03 24 94 04 lw s0, 73(s0) + 85e8: 00 00 + 85ea: 04 24 + 85ec: 92 07 + 85ee: 00 00 + 85f0: 05 24 + 85f2: 81 07 + 85f4: 00 00 + 85f6: 06 00 + 85f8: 21 cc + 85fa: 00 00 + 85fc: 00 0b + 85fe: 21 1c + 8600: 42 0a + 8602: 00 00 + 8604: 23 bb 03 00 + 8608: 00 07 + 860a: 04 2c + 860c: 00 00 + 860e: 00 0b + 8610: 23 06 b0 0a sb a1, 172(zero) + 8614: 00 00 + 8616: 24 b1 + 8618: 05 00 + 861a: 00 00 + 861c: 24 b3 + 861e: 04 00 + 8620: 00 01 + 8622: 24 9b + 8624: 06 00 + 8626: 00 02 + 8628: 00 21 + 862a: 4f 01 00 00 fnmadd.s ft2, ft0, ft0, ft0, rne + 862e: 0b 28 1e 8b + 8632: 0a 00 + 8634: 00 23 + 8636: 70 00 + 8638: 00 00 + 863a: 07 04 2c 00 + 863e: 00 00 + 8640: 0b 2b 06 db + 8644: 0a 00 + 8646: 00 24 + 8648: 4d 06 + 864a: 00 00 + 864c: 00 24 + 864e: 3b 06 00 00 + 8652: 01 00 + 8654: 21 89 + 8656: 01 00 + 8658: 00 0b + 865a: 2f 2a bc 0a + 865e: 00 00 + 8660: 21 72 + 8662: 03 00 00 0c lb zero, 192(zero) + 8666: 29 1a + 8668: 25 09 + 866a: 00 00 + 866c: 21 62 + 866e: 06 00 + 8670: 00 0c + 8672: 38 1a + 8674: 25 09 + 8676: 00 00 + 8678: 05 b7 + 867a: 07 00 00 0d + 867e: 7b 16 48 00 + 8682: 00 00 + 8684: 15 ff + 8686: 0a 00 + 8688: 00 05 + 868a: 82 01 + 868c: 00 00 + 868e: 0d 80 + 8690: 0f 25 00 00 + 8694: 00 05 + 8696: 81 01 + 8698: 00 00 + 869a: 0d 81 + 869c: 16 2c + 869e: 00 00 + 86a0: 00 03 + 86a2: 04 04 + 86a4: eb 03 00 00 vx_tex t2, zero, zero, zero, rne + 86a8: 03 08 03 e3 lb a6, -464(t1) + 86ac: 03 00 00 03 lb zero, 48(zero) + 86b0: 08 04 + 86b2: c5 00 + 86b4: 00 00 + 86b6: 03 10 03 3f lh zero, 1008(t1) + 86ba: 00 00 + 86bc: 00 03 + 86be: 20 03 + 86c0: b8 00 + 86c2: 00 00 + 86c4: 08 0b + 86c6: 0b 00 00 5b + 86ca: 0b 00 00 09 + 86ce: 2c 00 + 86d0: 00 00 + 86d2: ff 00 15 4b + 86d6: 0b 00 00 1f + 86da: 32 07 + 86dc: 00 00 + 86de: 0d fc + 86e0: 01 16 + 86e2: 5b 0b 00 00 + 86e6: 1f fd 02 00 + 86ea: 00 0d + 86ec: 02 02 + 86ee: 16 5b + 86f0: 0b 00 00 25 + 86f4: 0d 13 + 86f6: 00 00 + 86f8: 01 c2 + 86fa: 02 01 + 86fc: 25 00 + 86fe: 00 00 + 8700: c8 54 + 8702: 01 80 + 8704: 4c 00 + 8706: 00 00 + 8708: 01 9c + 870a: 26 78 + 870c: 00 01 + 870e: c2 02 + 8710: 12 1c + 8712: 0b 00 00 85 + 8716: 1b 01 00 27 + 871a: 72 65 + 871c: 74 00 + 871e: 01 c4 + 8720: 02 09 + 8722: 10 0b + 8724: 00 00 + 8726: 28 e8 + 8728: 14 00 + 872a: 00 29 + 872c: d6 06 + 872e: 00 00 + 8730: 01 c6 + 8732: 02 03 + 8734: 1c 0b + 8736: 00 00 + 8738: b1 1b + 873a: 01 00 + 873c: 2a 5f + 873e: 5f 61 00 01 + 8742: c6 02 + 8744: 03 1c 0b 00 lh s8, 0(s6) + 8748: 00 dd + 874a: 1b 01 00 00 + 874e: 00 00 + +Disassembly of section .debug_abbrev: + +00000000 .debug_abbrev: + 0: 01 11 + 2: 01 25 + 4: 0e 13 + 6: 0b 03 0e 1b + a: 0e 11 + c: 01 12 + e: 06 10 + 10: 17 00 00 02 auipc zero, 8192 + 14: 24 00 + 16: 0b 0b 3e 0b + 1a: 03 0e 00 00 lb t3, 0(zero) + 1e: 03 24 00 0b lw s0, 176(zero) + 22: 0b 3e 0b 03 + 26: 08 00 + 28: 00 04 + 2a: 16 00 + 2c: 03 0e 3a 0b lb t3, 179(s4) + 30: 3b 05 39 0b + 34: 49 13 + 36: 00 00 + 38: 05 16 + 3a: 00 03 + 3c: 0e 3a + 3e: 0b 3b 0b 39 + 42: 0b 49 13 00 + 46: 00 06 + 48: 17 01 0b 0b auipc sp, 45232 + 4c: 3a 0b + 4e: 3b 0b 39 0b + 52: 01 13 + 54: 00 00 + 56: 07 0d 00 03 + 5a: 0e 3a + 5c: 0b 3b 0b 39 + 60: 0b 49 13 00 + 64: 00 08 + 66: 01 01 + 68: 49 13 + 6a: 01 13 + 6c: 00 00 + 6e: 09 21 + 70: 00 49 + 72: 13 2f 0b 00 slti t5, s6, 0 + 76: 00 0a + 78: 13 01 0b 0b addi sp, s6, 176 + 7c: 3a 0b + 7e: 3b 0b 39 0b + 82: 01 13 + 84: 00 00 + 86: 0b 0d 00 03 + 8a: 0e 3a + 8c: 0b 3b 0b 39 + 90: 0b 49 13 38 + 94: 0b 00 00 0c + 98: 0f 00 0b 0b + 9c: 00 00 + 9e: 0d 13 + a0: 01 03 + a2: 0e 0b + a4: 0b 3a 0b 3b + a8: 0b 39 0b 01 + ac: 13 00 00 0e addi zero, zero, 224 + b0: 0d 00 + b2: 03 08 3a 0b lb a6, 179(s4) + b6: 3b 0b 39 0b + ba: 49 13 + bc: 38 0b + be: 00 00 + c0: 0f 0f 00 0b + c4: 0b 49 13 00 + c8: 00 10 + ca: 13 01 03 0e addi sp, t1, 224 + ce: 0b 05 3a 0b + d2: 3b 0b 39 0b + d6: 01 13 + d8: 00 00 + da: 11 0d + dc: 00 03 + de: 0e 3a + e0: 0b 3b 0b 39 + e4: 0b 49 13 38 + e8: 05 00 + ea: 00 12 + ec: 15 00 + ee: 27 19 00 00 + f2: 13 15 01 27 + f6: 19 49 + f8: 13 01 13 00 addi sp, t1, 1 + fc: 00 14 + fe: 05 00 + 100: 49 13 + 102: 00 00 + 104: 15 26 + 106: 00 49 + 108: 13 00 00 16 addi zero, zero, 352 + 10c: 13 01 03 0e addi sp, t1, 224 + 110: 0b 05 3a 0b + 114: 3b 05 39 0b + 118: 01 13 + 11a: 00 00 + 11c: 17 0d 00 03 auipc s10, 12288 + 120: 0e 3a + 122: 0b 3b 05 39 + 126: 0b 49 13 38 + 12a: 0b 00 00 18 + 12e: 0d 00 + 130: 03 0e 3a 0b lb t3, 179(s4) + 134: 3b 05 39 0b + 138: 49 13 + 13a: 38 05 + 13c: 00 00 + 13e: 19 13 + 140: 01 03 + 142: 0e 0b + 144: 0b 3a 0b 3b + 148: 05 39 + 14a: 0b 01 13 00 + 14e: 00 1a + 150: 13 01 0b 0b addi sp, s6, 176 + 154: 3a 0b + 156: 3b 05 39 0b + 15a: 01 13 + 15c: 00 00 + 15e: 1b 17 01 0b + 162: 0b 3a 0b 3b + 166: 05 39 + 168: 0b 01 13 00 + 16c: 00 1c + 16e: 0d 00 + 170: 03 0e 3a 0b lb t3, 179(s4) + 174: 3b 05 39 0b + 178: 49 13 + 17a: 00 00 + 17c: 1d 13 + 17e: 00 03 + 180: 0e 3c + 182: 19 00 + 184: 00 1e + 186: 15 01 + 188: 27 19 01 13 + 18c: 00 00 + 18e: 1f 34 00 03 + 192: 0e 3a + 194: 0b 3b 05 39 + 198: 0b 49 13 3f + 19c: 19 3c + 19e: 19 00 + 1a0: 00 20 + 1a2: 21 00 + 1a4: 00 00 + 1a6: 21 34 + 1a8: 00 03 + 1aa: 0e 3a + 1ac: 0b 3b 0b 39 + 1b0: 0b 49 13 3f + 1b4: 19 3c + 1b6: 19 00 + 1b8: 00 22 + 1ba: 26 00 + 1bc: 00 00 + 1be: 23 04 01 03 sb a6, 40(sp) + 1c2: 0e 3e + 1c4: 0b 0b 0b 49 + 1c8: 13 3a 0b 3b sltiu s4, s6, 944 + 1cc: 0b 39 0b 01 + 1d0: 13 00 00 24 addi zero, zero, 576 + 1d4: 28 00 + 1d6: 03 0e 1c 0b lb t3, 177(s8) + 1da: 00 00 + 1dc: 25 0d + 1de: 00 03 + 1e0: 08 3a + 1e2: 0b 3b 05 39 + 1e6: 0b 49 13 38 + 1ea: 0b 00 00 26 + 1ee: 0d 00 + 1f0: 03 08 3a 0b lb a6, 179(s4) + 1f4: 3b 05 39 0b + 1f8: 49 13 + 1fa: 00 00 + 1fc: 27 2e 01 3f fsw fa6, 1020(sp) + 200: 19 03 + 202: 0e 3a + 204: 0b 3b 05 39 + 208: 0b 27 19 49 + 20c: 13 11 01 12 + 210: 06 40 + 212: 18 97 + 214: 42 19 + 216: 01 13 + 218: 00 00 + 21a: 28 05 + 21c: 00 03 + 21e: 08 3a + 220: 0b 3b 05 39 + 224: 0b 49 13 02 + 228: 17 00 00 29 auipc zero, 167936 + 22c: 1d 01 + 22e: 31 13 + 230: 52 01 + 232: 55 17 + 234: 58 0b + 236: 59 05 + 238: 57 0b 00 00 + 23c: 2a 05 + 23e: 00 31 + 240: 13 02 17 00 addi tp, a4, 1 + 244: 00 2b + 246: 0b 01 55 17 + 24a: 00 00 + 24c: 2c 34 + 24e: 00 31 + 250: 13 00 00 2d addi zero, zero, 720 + 254: 34 00 + 256: 31 13 + 258: 02 17 + 25a: 00 00 + 25c: 2e 0b + 25e: 01 31 + 260: 13 55 17 01 srli a0, a4, 17 + 264: 13 00 00 2f addi zero, zero, 752 + 268: 0b 01 31 13 + 26c: 11 01 + 26e: 12 06 + 270: 01 13 + 272: 00 00 + 274: 30 0b + 276: 01 31 + 278: 13 55 17 00 srli a0, a4, 1 + 27c: 00 31 + 27e: 2e 01 + 280: 03 0e 3a 0b lb t3, 179(s4) + 284: 3b 05 39 0b + 288: 27 19 49 13 + 28c: 20 0b + 28e: 01 13 + 290: 00 00 + 292: 32 05 + 294: 00 03 + 296: 08 3a + 298: 0b 3b 05 39 + 29c: 0b 49 13 00 + 2a0: 00 33 + 2a2: 34 00 + 2a4: 03 08 3a 0b lb a6, 179(s4) + 2a8: 3b 05 39 0b + 2ac: 49 13 + 2ae: 00 00 + 2b0: 34 0b + 2b2: 01 01 + 2b4: 13 00 00 35 addi zero, zero, 848 + 2b8: 34 00 + 2ba: 03 0e 3a 0b lb t3, 179(s4) + 2be: 3b 05 39 0b + 2c2: 49 13 + 2c4: 00 00 + 2c6: 36 0b + 2c8: 01 00 + 2ca: 00 00 + 2cc: 01 11 + 2ce: 01 25 + 2d0: 0e 13 + 2d2: 0b 03 0e 1b + 2d6: 0e 11 + 2d8: 01 12 + 2da: 06 10 + 2dc: 17 00 00 02 auipc zero, 8192 + 2e0: 24 00 + 2e2: 0b 0b 3e 0b + 2e6: 03 0e 00 00 lb t3, 0(zero) + 2ea: 03 24 00 0b lw s0, 176(zero) + 2ee: 0b 3e 0b 03 + 2f2: 08 00 + 2f4: 00 04 + 2f6: 16 00 + 2f8: 03 0e 3a 0b lb t3, 179(s4) + 2fc: 3b 05 39 0b + 300: 49 13 + 302: 00 00 + 304: 05 16 + 306: 00 03 + 308: 0e 3a + 30a: 0b 3b 0b 39 + 30e: 0b 49 13 00 + 312: 00 06 + 314: 17 01 0b 0b auipc sp, 45232 + 318: 3a 0b + 31a: 3b 0b 39 0b + 31e: 01 13 + 320: 00 00 + 322: 07 0d 00 03 + 326: 0e 3a + 328: 0b 3b 0b 39 + 32c: 0b 49 13 00 + 330: 00 08 + 332: 01 01 + 334: 49 13 + 336: 01 13 + 338: 00 00 + 33a: 09 21 + 33c: 00 49 + 33e: 13 2f 0b 00 slti t5, s6, 0 + 342: 00 0a + 344: 13 01 0b 0b addi sp, s6, 176 + 348: 3a 0b + 34a: 3b 0b 39 0b + 34e: 01 13 + 350: 00 00 + 352: 0b 0d 00 03 + 356: 0e 3a + 358: 0b 3b 0b 39 + 35c: 0b 49 13 38 + 360: 0b 00 00 0c + 364: 0f 00 0b 0b + 368: 00 00 + 36a: 0d 13 + 36c: 01 03 + 36e: 0e 0b + 370: 0b 3a 0b 3b + 374: 0b 39 0b 01 + 378: 13 00 00 0e addi zero, zero, 224 + 37c: 0d 00 + 37e: 03 08 3a 0b lb a6, 179(s4) + 382: 3b 0b 39 0b + 386: 49 13 + 388: 38 0b + 38a: 00 00 + 38c: 0f 0f 00 0b + 390: 0b 49 13 00 + 394: 00 10 + 396: 13 01 03 0e addi sp, t1, 224 + 39a: 0b 05 3a 0b + 39e: 3b 0b 39 0b + 3a2: 01 13 + 3a4: 00 00 + 3a6: 11 0d + 3a8: 00 03 + 3aa: 0e 3a + 3ac: 0b 3b 0b 39 + 3b0: 0b 49 13 38 + 3b4: 05 00 + 3b6: 00 12 + 3b8: 15 00 + 3ba: 27 19 00 00 + 3be: 13 15 01 27 + 3c2: 19 49 + 3c4: 13 01 13 00 addi sp, t1, 1 + 3c8: 00 14 + 3ca: 05 00 + 3cc: 49 13 + 3ce: 00 00 + 3d0: 15 26 + 3d2: 00 49 + 3d4: 13 00 00 16 addi zero, zero, 352 + 3d8: 13 01 03 0e addi sp, t1, 224 + 3dc: 0b 05 3a 0b + 3e0: 3b 05 39 0b + 3e4: 01 13 + 3e6: 00 00 + 3e8: 17 0d 00 03 auipc s10, 12288 + 3ec: 0e 3a + 3ee: 0b 3b 05 39 + 3f2: 0b 49 13 38 + 3f6: 0b 00 00 18 + 3fa: 0d 00 + 3fc: 03 0e 3a 0b lb t3, 179(s4) + 400: 3b 05 39 0b + 404: 49 13 + 406: 38 05 + 408: 00 00 + 40a: 19 13 + 40c: 01 03 + 40e: 0e 0b + 410: 0b 3a 0b 3b + 414: 05 39 + 416: 0b 01 13 00 + 41a: 00 1a + 41c: 13 01 0b 0b addi sp, s6, 176 + 420: 3a 0b + 422: 3b 05 39 0b + 426: 01 13 + 428: 00 00 + 42a: 1b 17 01 0b + 42e: 0b 3a 0b 3b + 432: 05 39 + 434: 0b 01 13 00 + 438: 00 1c + 43a: 0d 00 + 43c: 03 0e 3a 0b lb t3, 179(s4) + 440: 3b 05 39 0b + 444: 49 13 + 446: 00 00 + 448: 1d 13 + 44a: 00 03 + 44c: 0e 3c + 44e: 19 00 + 450: 00 1e + 452: 15 01 + 454: 27 19 01 13 + 458: 00 00 + 45a: 1f 34 00 03 + 45e: 0e 3a + 460: 0b 3b 05 39 + 464: 0b 49 13 3f + 468: 19 3c + 46a: 19 00 + 46c: 00 20 + 46e: 21 00 + 470: 00 00 + 472: 21 34 + 474: 00 03 + 476: 0e 3a + 478: 0b 3b 0b 39 + 47c: 0b 49 13 3f + 480: 19 3c + 482: 19 00 + 484: 00 22 + 486: 26 00 + 488: 00 00 + 48a: 23 04 01 03 sb a6, 40(sp) + 48e: 0e 3e + 490: 0b 0b 0b 49 + 494: 13 3a 0b 3b sltiu s4, s6, 944 + 498: 0b 39 0b 01 + 49c: 13 00 00 24 addi zero, zero, 576 + 4a0: 28 00 + 4a2: 03 0e 1c 0b lb t3, 177(s8) + 4a6: 00 00 + 4a8: 25 0d + 4aa: 00 03 + 4ac: 08 3a + 4ae: 0b 3b 05 39 + 4b2: 0b 49 13 38 + 4b6: 0b 00 00 26 + 4ba: 0d 00 + 4bc: 03 08 3a 0b lb a6, 179(s4) + 4c0: 3b 05 39 0b + 4c4: 49 13 + 4c6: 00 00 + 4c8: 27 2e 01 3f fsw fa6, 1020(sp) + 4cc: 19 03 + 4ce: 0e 3a + 4d0: 0b 3b 05 39 + 4d4: 0b 27 19 49 + 4d8: 13 11 01 12 + 4dc: 06 40 + 4de: 18 97 + 4e0: 42 19 + 4e2: 01 13 + 4e4: 00 00 + 4e6: 28 05 + 4e8: 00 03 + 4ea: 08 3a + 4ec: 0b 3b 05 39 + 4f0: 0b 49 13 02 + 4f4: 17 00 00 29 auipc zero, 167936 + 4f8: 34 00 + 4fa: 03 08 3a 0b lb a6, 179(s4) + 4fe: 3b 05 39 0b + 502: 49 13 + 504: 02 17 + 506: 00 00 + 508: 2a 1d + 50a: 01 31 + 50c: 13 52 01 55 + 510: 17 58 0b 59 auipc a6, 364725 + 514: 05 57 + 516: 0b 00 00 2b + 51a: 05 00 + 51c: 31 13 + 51e: 02 17 + 520: 00 00 + 522: 2c 0b + 524: 01 55 + 526: 17 00 00 2d auipc zero, 184320 + 52a: 34 00 + 52c: 31 13 + 52e: 00 00 + 530: 2e 34 + 532: 00 31 + 534: 13 02 17 00 addi tp, a4, 1 + 538: 00 2f + 53a: 0b 01 31 13 + 53e: 55 17 + 540: 01 13 + 542: 00 00 + 544: 30 0b + 546: 01 31 + 548: 13 11 01 12 + 54c: 06 01 + 54e: 13 00 00 31 addi zero, zero, 784 + 552: 0b 01 31 13 + 556: 11 01 + 558: 12 06 + 55a: 00 00 + 55c: 32 34 + 55e: 00 31 + 560: 13 02 18 00 addi tp, a6, 1 + 564: 00 33 + 566: 2e 01 + 568: 03 0e 3a 0b lb t3, 179(s4) + 56c: 3b 05 39 0b + 570: 27 19 49 13 + 574: 20 0b + 576: 01 13 + 578: 00 00 + 57a: 34 05 + 57c: 00 03 + 57e: 08 3a + 580: 0b 3b 05 39 + 584: 0b 49 13 00 + 588: 00 35 + 58a: 34 00 + 58c: 03 08 3a 0b lb a6, 179(s4) + 590: 3b 05 39 0b + 594: 49 13 + 596: 00 00 + 598: 36 0b + 59a: 01 01 + 59c: 13 00 00 37 addi zero, zero, 880 + 5a0: 34 00 + 5a2: 03 0e 3a 0b lb t3, 179(s4) + 5a6: 3b 05 39 0b + 5aa: 49 13 + 5ac: 00 00 + 5ae: 38 0b + 5b0: 01 00 + 5b2: 00 00 + 5b4: 01 11 + 5b6: 01 25 + 5b8: 0e 13 + 5ba: 0b 03 0e 1b + 5be: 0e 11 + 5c0: 01 12 + 5c2: 06 10 + 5c4: 17 00 00 02 auipc zero, 8192 + 5c8: 24 00 + 5ca: 0b 0b 3e 0b + 5ce: 03 0e 00 00 lb t3, 0(zero) + 5d2: 03 24 00 0b lw s0, 176(zero) + 5d6: 0b 3e 0b 03 + 5da: 08 00 + 5dc: 00 04 + 5de: 16 00 + 5e0: 03 0e 3a 0b lb t3, 179(s4) + 5e4: 3b 05 39 0b + 5e8: 49 13 + 5ea: 00 00 + 5ec: 05 26 + 5ee: 00 49 + 5f0: 13 00 00 06 addi zero, zero, 96 + 5f4: 01 01 + 5f6: 49 13 + 5f8: 01 13 + 5fa: 00 00 + 5fc: 07 21 00 49 flw ft2, 1168(zero) + 600: 13 2f 0b 00 slti t5, s6, 0 + 604: 00 08 + 606: 34 00 + 608: 03 0e 3a 0b lb t3, 179(s4) + 60c: 3b 0b 39 0b + 610: 49 13 + 612: 3f 19 3c 19 + 616: 00 00 + 618: 09 16 + 61a: 00 03 + 61c: 0e 3a + 61e: 0b 3b 0b 39 + 622: 0b 49 13 00 + 626: 00 0a + 628: 13 01 0b 0b addi sp, s6, 176 + 62c: 3a 0b + 62e: 3b 0b 39 0b + 632: 01 13 + 634: 00 00 + 636: 0b 0d 00 03 + 63a: 0e 3a + 63c: 0b 3b 0b 39 + 640: 0b 49 13 0b + 644: 0b 0d 0b 0c + 648: 0b 38 0b 00 + 64c: 00 0c + 64e: 0d 00 + 650: 03 08 3a 0b lb a6, 179(s4) + 654: 3b 0b 39 0b + 658: 49 13 + 65a: 0b 0b 0d 0b + 65e: 0c 0b + 660: 38 0b + 662: 00 00 + 664: 0d 17 + 666: 01 03 + 668: 0e 0b + 66a: 0b 3a 0b 3b + 66e: 0b 39 0b 01 + 672: 13 00 00 0e addi zero, zero, 224 + 676: 0d 00 + 678: 03 08 3a 0b lb a6, 179(s4) + 67c: 3b 0b 39 0b + 680: 49 13 + 682: 00 00 + 684: 0f 0d 00 03 + 688: 0e 3a + 68a: 0b 3b 0b 39 + 68e: 0b 49 13 00 + 692: 00 10 + 694: 2e 01 + 696: 3f 19 03 0e + 69a: 3a 0b + 69c: 3b 0b 39 0b + 6a0: 27 19 49 13 + 6a4: 11 01 + 6a6: 12 06 + 6a8: 40 18 + 6aa: 96 42 + 6ac: 19 01 + 6ae: 13 00 00 11 addi zero, zero, 272 + 6b2: 05 00 + 6b4: 03 08 3a 0b lb a6, 179(s4) + 6b8: 3b 0b 39 0b + 6bc: 49 13 + 6be: 02 17 + 6c0: 00 00 + 6c2: 12 34 + 6c4: 00 03 + 6c6: 0e 3a + 6c8: 0b 3b 0b 39 + 6cc: 0b 49 13 02 + 6d0: 17 00 00 13 auipc zero, 77824 + 6d4: 34 00 + 6d6: 03 08 3a 0b lb a6, 179(s4) + 6da: 3b 0b 39 0b + 6de: 49 13 + 6e0: 02 17 + 6e2: 00 00 + 6e4: 14 34 + 6e6: 00 03 + 6e8: 08 3a + 6ea: 0b 3b 0b 39 + 6ee: 0b 49 13 00 + 6f2: 00 15 + 6f4: 0b 01 55 17 + 6f8: 01 13 + 6fa: 00 00 + 6fc: 16 34 + 6fe: 00 03 + 700: 0e 3a + 702: 0b 3b 0b 39 + 706: 0b 49 13 00 + 70a: 00 17 + 70c: 0b 01 11 01 + 710: 12 06 + 712: 01 13 + 714: 00 00 + 716: 18 0b + 718: 01 55 + 71a: 17 00 00 19 auipc zero, 102400 + 71e: 0b 01 01 13 + 722: 00 00 + 724: 1a 0b + 726: 01 00 + 728: 00 00 + 72a: 01 11 + 72c: 01 25 + 72e: 0e 13 + 730: 0b 03 0e 1b + 734: 0e 11 + 736: 01 12 + 738: 06 10 + 73a: 17 00 00 02 auipc zero, 8192 + 73e: 24 00 + 740: 0b 0b 3e 0b + 744: 03 0e 00 00 lb t3, 0(zero) + 748: 03 24 00 0b lw s0, 176(zero) + 74c: 0b 3e 0b 03 + 750: 08 00 + 752: 00 04 + 754: 16 00 + 756: 03 0e 3a 0b lb t3, 179(s4) + 75a: 3b 05 39 0b + 75e: 49 13 + 760: 00 00 + 762: 05 26 + 764: 00 49 + 766: 13 00 00 06 addi zero, zero, 96 + 76a: 01 01 + 76c: 49 13 + 76e: 01 13 + 770: 00 00 + 772: 07 21 00 49 flw ft2, 1168(zero) + 776: 13 2f 0b 00 slti t5, s6, 0 + 77a: 00 08 + 77c: 34 00 + 77e: 03 0e 3a 0b lb t3, 179(s4) + 782: 3b 0b 39 0b + 786: 49 13 + 788: 3f 19 3c 19 + 78c: 00 00 + 78e: 09 16 + 790: 00 03 + 792: 0e 3a + 794: 0b 3b 0b 39 + 798: 0b 49 13 00 + 79c: 00 0a + 79e: 13 01 0b 0b addi sp, s6, 176 + 7a2: 3a 0b + 7a4: 3b 0b 39 0b + 7a8: 01 13 + 7aa: 00 00 + 7ac: 0b 0d 00 03 + 7b0: 0e 3a + 7b2: 0b 3b 0b 39 + 7b6: 0b 49 13 0b + 7ba: 0b 0d 0b 0c + 7be: 0b 38 0b 00 + 7c2: 00 0c + 7c4: 0d 00 + 7c6: 03 08 3a 0b lb a6, 179(s4) + 7ca: 3b 0b 39 0b + 7ce: 49 13 + 7d0: 0b 0b 0d 0b + 7d4: 0c 0b + 7d6: 38 0b + 7d8: 00 00 + 7da: 0d 17 + 7dc: 01 03 + 7de: 0e 0b + 7e0: 0b 3a 0b 3b + 7e4: 0b 39 0b 01 + 7e8: 13 00 00 0e addi zero, zero, 224 + 7ec: 0d 00 + 7ee: 03 08 3a 0b lb a6, 179(s4) + 7f2: 3b 0b 39 0b + 7f6: 49 13 + 7f8: 00 00 + 7fa: 0f 0d 00 03 + 7fe: 0e 3a + 800: 0b 3b 0b 39 + 804: 0b 49 13 00 + 808: 00 10 + 80a: 2e 01 + 80c: 3f 19 03 0e + 810: 3a 0b + 812: 3b 0b 39 0b + 816: 27 19 49 13 + 81a: 11 01 + 81c: 12 06 + 81e: 40 18 + 820: 96 42 + 822: 19 01 + 824: 13 00 00 11 addi zero, zero, 272 + 828: 05 00 + 82a: 03 08 3a 0b lb a6, 179(s4) + 82e: 3b 0b 39 0b + 832: 49 13 + 834: 02 17 + 836: 00 00 + 838: 12 34 + 83a: 00 03 + 83c: 0e 3a + 83e: 0b 3b 0b 39 + 842: 0b 49 13 02 + 846: 17 00 00 13 auipc zero, 77824 + 84a: 34 00 + 84c: 03 08 3a 0b lb a6, 179(s4) + 850: 3b 0b 39 0b + 854: 49 13 + 856: 02 17 + 858: 00 00 + 85a: 14 34 + 85c: 00 03 + 85e: 08 3a + 860: 0b 3b 0b 39 + 864: 0b 49 13 00 + 868: 00 15 + 86a: 0b 01 55 17 + 86e: 01 13 + 870: 00 00 + 872: 16 34 + 874: 00 03 + 876: 0e 3a + 878: 0b 3b 0b 39 + 87c: 0b 49 13 00 + 880: 00 17 + 882: 0b 01 55 17 + 886: 00 00 + 888: 18 0b + 88a: 01 11 + 88c: 01 12 + 88e: 06 01 + 890: 13 00 00 19 addi zero, zero, 400 + 894: 0b 01 01 13 + 898: 00 00 + 89a: 1a 0b + 89c: 01 00 + 89e: 00 1b + 8a0: 0b 01 11 01 + 8a4: 12 06 + 8a6: 00 00 + 8a8: 1c 01 + 8aa: 01 49 + 8ac: 13 00 00 00 nop + 8b0: 01 11 + 8b2: 01 25 + 8b4: 0e 13 + 8b6: 0b 03 0e 1b + 8ba: 0e 11 + 8bc: 01 12 + 8be: 06 10 + 8c0: 17 00 00 02 auipc zero, 8192 + 8c4: 16 00 + 8c6: 03 0e 3a 0b lb t3, 179(s4) + 8ca: 3b 0b 39 0b + 8ce: 49 13 + 8d0: 00 00 + 8d2: 03 24 00 0b lw s0, 176(zero) + 8d6: 0b 3e 0b 03 + 8da: 08 00 + 8dc: 00 04 + 8de: 24 00 + 8e0: 0b 0b 3e 0b + 8e4: 03 0e 00 00 lb t3, 0(zero) + 8e8: 05 16 + 8ea: 00 03 + 8ec: 0e 3a + 8ee: 0b 3b 05 39 + 8f2: 0b 49 13 00 + 8f6: 00 06 + 8f8: 26 00 + 8fa: 49 13 + 8fc: 00 00 + 8fe: 07 01 01 49 + 902: 13 01 13 00 addi sp, t1, 1 + 906: 00 08 + 908: 21 00 + 90a: 49 13 + 90c: 2f 0b 00 00 + 910: 09 34 + 912: 00 03 + 914: 0e 3a + 916: 0b 3b 0b 39 + 91a: 0b 49 13 3f + 91e: 19 3c + 920: 19 00 + 922: 00 0a + 924: 13 01 0b 0b addi sp, s6, 176 + 928: 3a 0b + 92a: 3b 0b 39 0b + 92e: 01 13 + 930: 00 00 + 932: 0b 0d 00 03 + 936: 0e 3a + 938: 0b 3b 0b 39 + 93c: 0b 49 13 0b + 940: 0b 0d 0b 0c + 944: 0b 38 0b 00 + 948: 00 0c + 94a: 0d 00 + 94c: 03 08 3a 0b lb a6, 179(s4) + 950: 3b 0b 39 0b + 954: 49 13 + 956: 0b 0b 0d 0b + 95a: 0c 0b + 95c: 38 0b + 95e: 00 00 + 960: 0d 17 + 962: 01 03 + 964: 0e 0b + 966: 0b 3a 0b 3b + 96a: 0b 39 0b 01 + 96e: 13 00 00 0e addi zero, zero, 224 + 972: 0d 00 + 974: 03 08 3a 0b lb a6, 179(s4) + 978: 3b 0b 39 0b + 97c: 49 13 + 97e: 00 00 + 980: 0f 0d 00 03 + 984: 0e 3a + 986: 0b 3b 0b 39 + 98a: 0b 49 13 00 + 98e: 00 10 + 990: 2e 01 + 992: 3f 19 03 0e + 996: 3a 0b + 998: 3b 0b 39 0b + 99c: 27 19 49 13 + 9a0: 11 01 + 9a2: 12 06 + 9a4: 40 18 + 9a6: 97 42 19 01 auipc t0, 4500 + 9aa: 13 00 00 11 addi zero, zero, 272 + 9ae: 05 00 + 9b0: 03 08 3a 0b lb a6, 179(s4) + 9b4: 3b 0b 39 0b + 9b8: 49 13 + 9ba: 00 00 + 9bc: 12 34 + 9be: 00 03 + 9c0: 0e 3a + 9c2: 0b 3b 0b 39 + 9c6: 0b 49 13 02 + 9ca: 17 00 00 13 auipc zero, 77824 + 9ce: 34 00 + 9d0: 03 0e 3a 0b lb t3, 179(s4) + 9d4: 3b 0b 39 0b + 9d8: 49 13 + 9da: 00 00 + 9dc: 14 34 + 9de: 00 03 + 9e0: 08 3a + 9e2: 0b 3b 0b 39 + 9e6: 0b 49 13 00 + 9ea: 00 15 + 9ec: 34 00 + 9ee: 03 08 3a 0b lb a6, 179(s4) + 9f2: 3b 0b 39 0b + 9f6: 49 13 + 9f8: 02 18 + 9fa: 00 00 + 9fc: 16 34 + 9fe: 00 03 + a00: 08 3a + a02: 0b 3b 0b 39 + a06: 0b 49 13 02 + a0a: 17 00 00 17 auipc zero, 94208 + a0e: 0b 01 55 17 + a12: 01 13 + a14: 00 00 + a16: 18 34 + a18: 00 03 + a1a: 0e 3a + a1c: 0b 3b 0b 39 + a20: 0b 49 13 02 + a24: 18 00 + a26: 00 19 + a28: 0b 01 01 13 + a2c: 00 00 + a2e: 1a 0b + a30: 01 11 + a32: 01 12 + a34: 06 01 + a36: 13 00 00 1b addi zero, zero, 432 + a3a: 0b 01 55 17 + a3e: 00 00 + a40: 1c 01 + a42: 01 49 + a44: 13 00 00 00 nop + a48: 01 11 + a4a: 01 25 + a4c: 0e 13 + a4e: 0b 03 0e 1b + a52: 0e 11 + a54: 01 12 + a56: 06 10 + a58: 17 00 00 02 auipc zero, 8192 + a5c: 16 00 + a5e: 03 0e 3a 0b lb t3, 179(s4) + a62: 3b 0b 39 0b + a66: 49 13 + a68: 00 00 + a6a: 03 24 00 0b lw s0, 176(zero) + a6e: 0b 3e 0b 03 + a72: 08 00 + a74: 00 04 + a76: 24 00 + a78: 0b 0b 3e 0b + a7c: 03 0e 00 00 lb t3, 0(zero) + a80: 05 16 + a82: 00 03 + a84: 0e 3a + a86: 0b 3b 05 39 + a8a: 0b 49 13 00 + a8e: 00 06 + a90: 26 00 + a92: 49 13 + a94: 00 00 + a96: 07 01 01 49 + a9a: 13 01 13 00 addi sp, t1, 1 + a9e: 00 08 + aa0: 21 00 + aa2: 49 13 + aa4: 2f 0b 00 00 + aa8: 09 34 + aaa: 00 03 + aac: 0e 3a + aae: 0b 3b 0b 39 + ab2: 0b 49 13 3f + ab6: 19 3c + ab8: 19 00 + aba: 00 0a + abc: 13 01 0b 0b addi sp, s6, 176 + ac0: 3a 0b + ac2: 3b 0b 39 0b + ac6: 01 13 + ac8: 00 00 + aca: 0b 0d 00 03 + ace: 0e 3a + ad0: 0b 3b 0b 39 + ad4: 0b 49 13 0b + ad8: 0b 0d 0b 0c + adc: 0b 38 0b 00 + ae0: 00 0c + ae2: 0d 00 + ae4: 03 08 3a 0b lb a6, 179(s4) + ae8: 3b 0b 39 0b + aec: 49 13 + aee: 0b 0b 0d 0b + af2: 0c 0b + af4: 38 0b + af6: 00 00 + af8: 0d 17 + afa: 01 03 + afc: 0e 0b + afe: 0b 3a 0b 3b + b02: 0b 39 0b 01 + b06: 13 00 00 0e addi zero, zero, 224 + b0a: 0d 00 + b0c: 03 08 3a 0b lb a6, 179(s4) + b10: 3b 0b 39 0b + b14: 49 13 + b16: 00 00 + b18: 0f 0d 00 03 + b1c: 0e 3a + b1e: 0b 3b 0b 39 + b22: 0b 49 13 00 + b26: 00 10 + b28: 2e 01 + b2a: 3f 19 03 0e + b2e: 3a 0b + b30: 3b 0b 39 0b + b34: 27 19 49 13 + b38: 11 01 + b3a: 12 06 + b3c: 40 18 + b3e: 97 42 19 01 auipc t0, 4500 + b42: 13 00 00 11 addi zero, zero, 272 + b46: 05 00 + b48: 03 08 3a 0b lb a6, 179(s4) + b4c: 3b 0b 39 0b + b50: 49 13 + b52: 00 00 + b54: 12 34 + b56: 00 03 + b58: 0e 3a + b5a: 0b 3b 0b 39 + b5e: 0b 49 13 02 + b62: 17 00 00 13 auipc zero, 77824 + b66: 34 00 + b68: 03 0e 3a 0b lb t3, 179(s4) + b6c: 3b 0b 39 0b + b70: 49 13 + b72: 00 00 + b74: 14 34 + b76: 00 03 + b78: 08 3a + b7a: 0b 3b 0b 39 + b7e: 0b 49 13 00 + b82: 00 15 + b84: 34 00 + b86: 03 08 3a 0b lb a6, 179(s4) + b8a: 3b 0b 39 0b + b8e: 49 13 + b90: 02 17 + b92: 00 00 + b94: 16 34 + b96: 00 03 + b98: 08 3a + b9a: 0b 3b 0b 39 + b9e: 0b 49 13 02 + ba2: 18 00 + ba4: 00 17 + ba6: 0b 01 55 17 + baa: 01 13 + bac: 00 00 + bae: 18 34 + bb0: 00 03 + bb2: 0e 3a + bb4: 0b 3b 0b 39 + bb8: 0b 49 13 02 + bbc: 18 00 + bbe: 00 19 + bc0: 0b 01 01 13 + bc4: 00 00 + bc6: 1a 0b + bc8: 01 55 + bca: 17 00 00 1b auipc zero, 110592 + bce: 01 01 + bd0: 49 13 + bd2: 00 00 + bd4: 00 01 + bd6: 11 01 + bd8: 25 0e + bda: 13 0b 03 0e addi s6, t1, 224 + bde: 1b 0e 11 01 + be2: 12 06 + be4: 10 17 + be6: 00 00 + be8: 02 16 + bea: 00 03 + bec: 0e 3a + bee: 0b 3b 0b 39 + bf2: 0b 49 13 00 + bf6: 00 03 + bf8: 24 00 + bfa: 0b 0b 3e 0b + bfe: 03 08 00 00 lb a6, 0(zero) + c02: 04 24 + c04: 00 0b + c06: 0b 3e 0b 03 + c0a: 0e 00 + c0c: 00 05 + c0e: 16 00 + c10: 03 0e 3a 0b lb t3, 179(s4) + c14: 3b 05 39 0b + c18: 49 13 + c1a: 00 00 + c1c: 06 26 + c1e: 00 49 + c20: 13 00 00 07 addi zero, zero, 112 + c24: 01 01 + c26: 49 13 + c28: 01 13 + c2a: 00 00 + c2c: 08 21 + c2e: 00 49 + c30: 13 2f 0b 00 slti t5, s6, 0 + c34: 00 09 + c36: 34 00 + c38: 03 0e 3a 0b lb t3, 179(s4) + c3c: 3b 0b 39 0b + c40: 49 13 + c42: 3f 19 3c 19 + c46: 00 00 + c48: 0a 13 + c4a: 01 0b + c4c: 0b 3a 0b 3b + c50: 0b 39 0b 01 + c54: 13 00 00 0b addi zero, zero, 176 + c58: 0d 00 + c5a: 03 0e 3a 0b lb t3, 179(s4) + c5e: 3b 0b 39 0b + c62: 49 13 + c64: 0b 0b 0d 0b + c68: 0c 0b + c6a: 38 0b + c6c: 00 00 + c6e: 0c 0d + c70: 00 03 + c72: 08 3a + c74: 0b 3b 0b 39 + c78: 0b 49 13 0b + c7c: 0b 0d 0b 0c + c80: 0b 38 0b 00 + c84: 00 0d + c86: 17 01 03 0e auipc sp, 57392 + c8a: 0b 0b 3a 0b + c8e: 3b 0b 39 0b + c92: 01 13 + c94: 00 00 + c96: 0e 0d + c98: 00 03 + c9a: 08 3a + c9c: 0b 3b 0b 39 + ca0: 0b 49 13 00 + ca4: 00 0f + ca6: 0d 00 + ca8: 03 0e 3a 0b lb t3, 179(s4) + cac: 3b 0b 39 0b + cb0: 49 13 + cb2: 00 00 + cb4: 10 2e + cb6: 01 3f + cb8: 19 03 + cba: 0e 3a + cbc: 0b 3b 0b 39 + cc0: 0b 27 19 49 + cc4: 13 11 01 12 + cc8: 06 40 + cca: 18 97 + ccc: 42 19 + cce: 01 13 + cd0: 00 00 + cd2: 11 05 + cd4: 00 03 + cd6: 08 3a + cd8: 0b 3b 0b 39 + cdc: 0b 49 13 00 + ce0: 00 12 + ce2: 34 00 + ce4: 03 0e 3a 0b lb t3, 179(s4) + ce8: 3b 0b 39 0b + cec: 49 13 + cee: 02 17 + cf0: 00 00 + cf2: 13 34 00 03 sltiu s0, zero, 48 + cf6: 0e 3a + cf8: 0b 3b 0b 39 + cfc: 0b 49 13 00 + d00: 00 14 + d02: 34 00 + d04: 03 08 3a 0b lb a6, 179(s4) + d08: 3b 0b 39 0b + d0c: 49 13 + d0e: 00 00 + d10: 15 34 + d12: 00 03 + d14: 08 3a + d16: 0b 3b 0b 39 + d1a: 0b 49 13 02 + d1e: 17 00 00 16 auipc zero, 90112 + d22: 34 00 + d24: 03 08 3a 0b lb a6, 179(s4) + d28: 3b 0b 39 0b + d2c: 49 13 + d2e: 02 18 + d30: 00 00 + d32: 17 0b 01 55 auipc s6, 348176 + d36: 17 01 13 00 auipc sp, 304 + d3a: 00 18 + d3c: 34 00 + d3e: 03 0e 3a 0b lb t3, 179(s4) + d42: 3b 0b 39 0b + d46: 49 13 + d48: 02 18 + d4a: 00 00 + d4c: 19 0b + d4e: 01 01 + d50: 13 00 00 1a addi zero, zero, 416 + d54: 0b 01 55 17 + d58: 00 00 + d5a: 1b 01 01 49 + d5e: 13 00 00 00 nop + d62: 01 11 + d64: 01 25 + d66: 0e 13 + d68: 0b 03 0e 1b + d6c: 0e 11 + d6e: 01 12 + d70: 06 10 + d72: 17 00 00 02 auipc zero, 8192 + d76: 24 00 + d78: 0b 0b 3e 0b + d7c: 03 08 00 00 lb a6, 0(zero) + d80: 03 24 00 0b lw s0, 176(zero) + d84: 0b 3e 0b 03 + d88: 0e 00 + d8a: 00 04 + d8c: 16 00 + d8e: 03 0e 3a 0b lb t3, 179(s4) + d92: 3b 05 39 0b + d96: 49 13 + d98: 00 00 + d9a: 05 26 + d9c: 00 49 + d9e: 13 00 00 06 addi zero, zero, 96 + da2: 01 01 + da4: 49 13 + da6: 01 13 + da8: 00 00 + daa: 07 21 00 49 flw ft2, 1168(zero) + dae: 13 2f 0b 00 slti t5, s6, 0 + db2: 00 08 + db4: 34 00 + db6: 03 0e 3a 0b lb t3, 179(s4) + dba: 3b 0b 39 0b + dbe: 49 13 + dc0: 3f 19 3c 19 + dc4: 00 00 + dc6: 09 16 + dc8: 00 03 + dca: 0e 3a + dcc: 0b 3b 0b 39 + dd0: 0b 49 13 00 + dd4: 00 0a + dd6: 13 01 0b 0b addi sp, s6, 176 + dda: 3a 0b + ddc: 3b 0b 39 0b + de0: 01 13 + de2: 00 00 + de4: 0b 0d 00 03 + de8: 0e 3a + dea: 0b 3b 0b 39 + dee: 0b 49 13 0b + df2: 0b 0d 0b 0c + df6: 0b 38 0b 00 + dfa: 00 0c + dfc: 0d 00 + dfe: 03 08 3a 0b lb a6, 179(s4) + e02: 3b 0b 39 0b + e06: 49 13 + e08: 0b 0b 0d 0b + e0c: 0c 0b + e0e: 38 0b + e10: 00 00 + e12: 0d 17 + e14: 01 03 + e16: 0e 0b + e18: 0b 3a 0b 3b + e1c: 0b 39 0b 01 + e20: 13 00 00 0e addi zero, zero, 224 + e24: 0d 00 + e26: 03 08 3a 0b lb a6, 179(s4) + e2a: 3b 0b 39 0b + e2e: 49 13 + e30: 00 00 + e32: 0f 0d 00 03 + e36: 0e 3a + e38: 0b 3b 0b 39 + e3c: 0b 49 13 00 + e40: 00 10 + e42: 2e 01 + e44: 3f 19 03 0e + e48: 3a 0b + e4a: 3b 0b 39 0b + e4e: 27 19 49 13 + e52: 11 01 + e54: 12 06 + e56: 40 18 + e58: 96 42 + e5a: 19 01 + e5c: 13 00 00 11 addi zero, zero, 272 + e60: 05 00 + e62: 03 08 3a 0b lb a6, 179(s4) + e66: 3b 0b 39 0b + e6a: 49 13 + e6c: 00 00 + e6e: 12 34 + e70: 00 03 + e72: 0e 3a + e74: 0b 3b 0b 39 + e78: 0b 49 13 02 + e7c: 17 00 00 13 auipc zero, 77824 + e80: 34 00 + e82: 03 08 3a 0b lb a6, 179(s4) + e86: 3b 0b 39 0b + e8a: 49 13 + e8c: 02 17 + e8e: 00 00 + e90: 14 34 + e92: 00 03 + e94: 08 3a + e96: 0b 3b 0b 39 + e9a: 0b 49 13 02 + e9e: 18 00 + ea0: 00 15 + ea2: 0b 01 55 17 + ea6: 01 13 + ea8: 00 00 + eaa: 16 34 + eac: 00 03 + eae: 0e 3a + eb0: 0b 3b 0b 39 + eb4: 0b 49 13 02 + eb8: 18 00 + eba: 00 17 + ebc: 0b 01 55 17 + ec0: 00 00 + ec2: 18 0b + ec4: 01 11 + ec6: 01 12 + ec8: 06 01 + eca: 13 00 00 19 addi zero, zero, 400 + ece: 34 00 + ed0: 03 0e 3a 0b lb t3, 179(s4) + ed4: 3b 0b 39 0b + ed8: 49 13 + eda: 00 00 + edc: 1a 0b + ede: 01 11 + ee0: 01 12 + ee2: 06 00 + ee4: 00 1b + ee6: 0b 01 01 13 + eea: 00 00 + eec: 1c 0b + eee: 01 00 + ef0: 00 1d + ef2: 01 01 + ef4: 49 13 + ef6: 00 00 + ef8: 00 01 + efa: 11 01 + efc: 25 0e + efe: 13 0b 03 0e addi s6, t1, 224 + f02: 1b 0e 11 01 + f06: 12 06 + f08: 10 17 + f0a: 00 00 + f0c: 02 24 + f0e: 00 0b + f10: 0b 3e 0b 03 + f14: 08 00 + f16: 00 03 + f18: 24 00 + f1a: 0b 0b 3e 0b + f1e: 03 0e 00 00 lb t3, 0(zero) + f22: 04 16 + f24: 00 03 + f26: 0e 3a + f28: 0b 3b 05 39 + f2c: 0b 49 13 00 + f30: 00 05 + f32: 26 00 + f34: 49 13 + f36: 00 00 + f38: 06 01 + f3a: 01 49 + f3c: 13 01 13 00 addi sp, t1, 1 + f40: 00 07 + f42: 21 00 + f44: 49 13 + f46: 2f 0b 00 00 + f4a: 08 34 + f4c: 00 03 + f4e: 0e 3a + f50: 0b 3b 0b 39 + f54: 0b 49 13 3f + f58: 19 3c + f5a: 19 00 + f5c: 00 09 + f5e: 16 00 + f60: 03 0e 3a 0b lb t3, 179(s4) + f64: 3b 0b 39 0b + f68: 49 13 + f6a: 00 00 + f6c: 0a 13 + f6e: 01 0b + f70: 0b 3a 0b 3b + f74: 0b 39 0b 01 + f78: 13 00 00 0b addi zero, zero, 176 + f7c: 0d 00 + f7e: 03 0e 3a 0b lb t3, 179(s4) + f82: 3b 0b 39 0b + f86: 49 13 + f88: 0b 0b 0d 0b + f8c: 0c 0b + f8e: 38 0b + f90: 00 00 + f92: 0c 0d + f94: 00 03 + f96: 08 3a + f98: 0b 3b 0b 39 + f9c: 0b 49 13 0b + fa0: 0b 0d 0b 0c + fa4: 0b 38 0b 00 + fa8: 00 0d + faa: 17 01 03 0e auipc sp, 57392 + fae: 0b 0b 3a 0b + fb2: 3b 0b 39 0b + fb6: 01 13 + fb8: 00 00 + fba: 0e 0d + fbc: 00 03 + fbe: 08 3a + fc0: 0b 3b 0b 39 + fc4: 0b 49 13 00 + fc8: 00 0f + fca: 0d 00 + fcc: 03 0e 3a 0b lb t3, 179(s4) + fd0: 3b 0b 39 0b + fd4: 49 13 + fd6: 00 00 + fd8: 10 2e + fda: 01 3f + fdc: 19 03 + fde: 0e 3a + fe0: 0b 3b 0b 39 + fe4: 0b 27 19 49 + fe8: 13 11 01 12 + fec: 06 40 + fee: 18 96 + ff0: 42 19 + ff2: 01 13 + ff4: 00 00 + ff6: 11 05 + ff8: 00 03 + ffa: 08 3a + ffc: 0b 3b 0b 39 + 1000: 0b 49 13 00 + 1004: 00 12 + 1006: 34 00 + 1008: 03 0e 3a 0b lb t3, 179(s4) + 100c: 3b 0b 39 0b + 1010: 49 13 + 1012: 02 17 + 1014: 00 00 + 1016: 13 34 00 03 sltiu s0, zero, 48 + 101a: 08 3a + 101c: 0b 3b 0b 39 + 1020: 0b 49 13 00 + 1024: 00 14 + 1026: 34 00 + 1028: 03 08 3a 0b lb a6, 179(s4) + 102c: 3b 0b 39 0b + 1030: 49 13 + 1032: 02 17 + 1034: 00 00 + 1036: 15 34 + 1038: 00 03 + 103a: 08 3a + 103c: 0b 3b 0b 39 + 1040: 0b 49 13 02 + 1044: 18 00 + 1046: 00 16 + 1048: 0b 01 55 17 + 104c: 01 13 + 104e: 00 00 + 1050: 17 34 00 03 auipc s0, 12291 + 1054: 0e 3a + 1056: 0b 3b 0b 39 + 105a: 0b 49 13 02 + 105e: 18 00 + 1060: 00 18 + 1062: 34 00 + 1064: 03 0e 3a 0b lb t3, 179(s4) + 1068: 3b 0b 39 0b + 106c: 49 13 + 106e: 1c 0b + 1070: 00 00 + 1072: 19 0a + 1074: 00 03 + 1076: 0e 3a + 1078: 0b 3b 0b 39 + 107c: 0b 11 01 00 + 1080: 00 1a + 1082: 0b 01 11 01 + 1086: 12 06 + 1088: 01 13 + 108a: 00 00 + 108c: 1b 34 00 03 + 1090: 0e 3a + 1092: 0b 3b 0b 39 + 1096: 0b 49 13 00 + 109a: 00 1c + 109c: 0b 01 55 17 + 10a0: 00 00 + 10a2: 1d 0b + 10a4: 01 01 + 10a6: 13 00 00 1e addi zero, zero, 480 + 10aa: 0b 01 11 01 + 10ae: 12 06 + 10b0: 00 00 + 10b2: 1f 01 01 49 + 10b6: 13 00 00 00 nop + 10ba: 01 11 + 10bc: 01 25 + 10be: 0e 13 + 10c0: 0b 03 0e 1b + 10c4: 0e 11 + 10c6: 01 12 + 10c8: 06 10 + 10ca: 17 00 00 02 auipc zero, 8192 + 10ce: 24 00 + 10d0: 0b 0b 3e 0b + 10d4: 03 08 00 00 lb a6, 0(zero) + 10d8: 03 24 00 0b lw s0, 176(zero) + 10dc: 0b 3e 0b 03 + 10e0: 0e 00 + 10e2: 00 04 + 10e4: 16 00 + 10e6: 03 0e 3a 0b lb t3, 179(s4) + 10ea: 3b 05 39 0b + 10ee: 49 13 + 10f0: 00 00 + 10f2: 05 26 + 10f4: 00 49 + 10f6: 13 00 00 06 addi zero, zero, 96 + 10fa: 01 01 + 10fc: 49 13 + 10fe: 01 13 + 1100: 00 00 + 1102: 07 21 00 49 flw ft2, 1168(zero) + 1106: 13 2f 0b 00 slti t5, s6, 0 + 110a: 00 08 + 110c: 34 00 + 110e: 03 0e 3a 0b lb t3, 179(s4) + 1112: 3b 0b 39 0b + 1116: 49 13 + 1118: 3f 19 3c 19 + 111c: 00 00 + 111e: 09 16 + 1120: 00 03 + 1122: 0e 3a + 1124: 0b 3b 0b 39 + 1128: 0b 49 13 00 + 112c: 00 0a + 112e: 13 01 0b 0b addi sp, s6, 176 + 1132: 3a 0b + 1134: 3b 0b 39 0b + 1138: 01 13 + 113a: 00 00 + 113c: 0b 0d 00 03 + 1140: 0e 3a + 1142: 0b 3b 0b 39 + 1146: 0b 49 13 0b + 114a: 0b 0d 0b 0c + 114e: 0b 38 0b 00 + 1152: 00 0c + 1154: 0d 00 + 1156: 03 08 3a 0b lb a6, 179(s4) + 115a: 3b 0b 39 0b + 115e: 49 13 + 1160: 0b 0b 0d 0b + 1164: 0c 0b + 1166: 38 0b + 1168: 00 00 + 116a: 0d 17 + 116c: 01 03 + 116e: 0e 0b + 1170: 0b 3a 0b 3b + 1174: 0b 39 0b 01 + 1178: 13 00 00 0e addi zero, zero, 224 + 117c: 0d 00 + 117e: 03 08 3a 0b lb a6, 179(s4) + 1182: 3b 0b 39 0b + 1186: 49 13 + 1188: 00 00 + 118a: 0f 0d 00 03 + 118e: 0e 3a + 1190: 0b 3b 0b 39 + 1194: 0b 49 13 00 + 1198: 00 10 + 119a: 2e 01 + 119c: 3f 19 03 0e + 11a0: 3a 0b + 11a2: 3b 0b 39 0b + 11a6: 27 19 49 13 + 11aa: 11 01 + 11ac: 12 06 + 11ae: 40 18 + 11b0: 97 42 19 01 auipc t0, 4500 + 11b4: 13 00 00 11 addi zero, zero, 272 + 11b8: 05 00 + 11ba: 03 08 3a 0b lb a6, 179(s4) + 11be: 3b 0b 39 0b + 11c2: 49 13 + 11c4: 00 00 + 11c6: 12 34 + 11c8: 00 03 + 11ca: 0e 3a + 11cc: 0b 3b 0b 39 + 11d0: 0b 49 13 02 + 11d4: 17 00 00 13 auipc zero, 77824 + 11d8: 34 00 + 11da: 03 0e 3a 0b lb t3, 179(s4) + 11de: 3b 0b 39 0b + 11e2: 49 13 + 11e4: 00 00 + 11e6: 14 34 + 11e8: 00 03 + 11ea: 08 3a + 11ec: 0b 3b 0b 39 + 11f0: 0b 49 13 00 + 11f4: 00 15 + 11f6: 34 00 + 11f8: 03 08 3a 0b lb a6, 179(s4) + 11fc: 3b 0b 39 0b + 1200: 49 13 + 1202: 02 17 + 1204: 00 00 + 1206: 16 34 + 1208: 00 03 + 120a: 08 3a + 120c: 0b 3b 0b 39 + 1210: 0b 49 13 02 + 1214: 18 00 + 1216: 00 17 + 1218: 0b 01 55 17 + 121c: 01 13 + 121e: 00 00 + 1220: 18 34 + 1222: 00 03 + 1224: 0e 3a + 1226: 0b 3b 0b 39 + 122a: 0b 49 13 02 + 122e: 18 00 + 1230: 00 19 + 1232: 0b 01 55 17 + 1236: 00 00 + 1238: 1a 01 + 123a: 01 49 + 123c: 13 00 00 00 nop + 1240: 01 11 + 1242: 01 25 + 1244: 0e 13 + 1246: 0b 03 0e 1b + 124a: 0e 11 + 124c: 01 12 + 124e: 06 10 + 1250: 17 00 00 02 auipc zero, 8192 + 1254: 24 00 + 1256: 0b 0b 3e 0b + 125a: 03 08 00 00 lb a6, 0(zero) + 125e: 03 24 00 0b lw s0, 176(zero) + 1262: 0b 3e 0b 03 + 1266: 0e 00 + 1268: 00 04 + 126a: 16 00 + 126c: 03 0e 3a 0b lb t3, 179(s4) + 1270: 3b 05 39 0b + 1274: 49 13 + 1276: 00 00 + 1278: 05 26 + 127a: 00 49 + 127c: 13 00 00 06 addi zero, zero, 96 + 1280: 01 01 + 1282: 49 13 + 1284: 01 13 + 1286: 00 00 + 1288: 07 21 00 49 flw ft2, 1168(zero) + 128c: 13 2f 0b 00 slti t5, s6, 0 + 1290: 00 08 + 1292: 34 00 + 1294: 03 0e 3a 0b lb t3, 179(s4) + 1298: 3b 0b 39 0b + 129c: 49 13 + 129e: 3f 19 3c 19 + 12a2: 00 00 + 12a4: 09 16 + 12a6: 00 03 + 12a8: 0e 3a + 12aa: 0b 3b 0b 39 + 12ae: 0b 49 13 00 + 12b2: 00 0a + 12b4: 13 01 0b 0b addi sp, s6, 176 + 12b8: 3a 0b + 12ba: 3b 0b 39 0b + 12be: 01 13 + 12c0: 00 00 + 12c2: 0b 0d 00 03 + 12c6: 0e 3a + 12c8: 0b 3b 0b 39 + 12cc: 0b 49 13 0b + 12d0: 0b 0d 0b 0c + 12d4: 0b 38 0b 00 + 12d8: 00 0c + 12da: 0d 00 + 12dc: 03 08 3a 0b lb a6, 179(s4) + 12e0: 3b 0b 39 0b + 12e4: 49 13 + 12e6: 0b 0b 0d 0b + 12ea: 0c 0b + 12ec: 38 0b + 12ee: 00 00 + 12f0: 0d 17 + 12f2: 01 03 + 12f4: 0e 0b + 12f6: 0b 3a 0b 3b + 12fa: 0b 39 0b 01 + 12fe: 13 00 00 0e addi zero, zero, 224 + 1302: 0d 00 + 1304: 03 08 3a 0b lb a6, 179(s4) + 1308: 3b 0b 39 0b + 130c: 49 13 + 130e: 00 00 + 1310: 0f 0d 00 03 + 1314: 0e 3a + 1316: 0b 3b 0b 39 + 131a: 0b 49 13 00 + 131e: 00 10 + 1320: 2e 01 + 1322: 3f 19 03 0e + 1326: 3a 0b + 1328: 3b 0b 39 0b + 132c: 27 19 49 13 + 1330: 11 01 + 1332: 12 06 + 1334: 40 18 + 1336: 96 42 + 1338: 19 01 + 133a: 13 00 00 11 addi zero, zero, 272 + 133e: 05 00 + 1340: 03 08 3a 0b lb a6, 179(s4) + 1344: 3b 0b 39 0b + 1348: 49 13 + 134a: 02 17 + 134c: 00 00 + 134e: 12 34 + 1350: 00 03 + 1352: 08 3a + 1354: 0b 3b 0b 39 + 1358: 0b 49 13 00 + 135c: 00 13 + 135e: 34 00 + 1360: 03 08 3a 0b lb a6, 179(s4) + 1364: 3b 0b 39 0b + 1368: 49 13 + 136a: 02 17 + 136c: 00 00 + 136e: 14 34 + 1370: 00 03 + 1372: 08 3a + 1374: 0b 3b 0b 39 + 1378: 0b 49 13 02 + 137c: 18 00 + 137e: 00 15 + 1380: 0b 01 55 17 + 1384: 01 13 + 1386: 00 00 + 1388: 16 0a + 138a: 00 03 + 138c: 0e 3a + 138e: 0b 3b 0b 39 + 1392: 0b 00 00 17 + 1396: 0b 01 55 17 + 139a: 00 00 + 139c: 18 34 + 139e: 00 03 + 13a0: 0e 3a + 13a2: 0b 3b 0b 39 + 13a6: 0b 49 13 02 + 13aa: 17 00 00 19 auipc zero, 102400 + 13ae: 0b 01 01 13 + 13b2: 00 00 + 13b4: 1a 34 + 13b6: 00 03 + 13b8: 0e 3a + 13ba: 0b 3b 0b 39 + 13be: 0b 49 13 00 + 13c2: 00 1b + 13c4: 0b 01 00 00 + 13c8: 1c 34 + 13ca: 00 03 + 13cc: 0e 3a + 13ce: 0b 3b 0b 39 + 13d2: 0b 49 13 02 + 13d6: 18 00 + 13d8: 00 1d + 13da: 01 01 + 13dc: 49 13 + 13de: 00 00 + 13e0: 00 01 + 13e2: 11 01 + 13e4: 25 0e + 13e6: 13 0b 03 0e addi s6, t1, 224 + 13ea: 1b 0e 11 01 + 13ee: 12 06 + 13f0: 10 17 + 13f2: 00 00 + 13f4: 02 24 + 13f6: 00 0b + 13f8: 0b 3e 0b 03 + 13fc: 0e 00 + 13fe: 00 03 + 1400: 24 00 + 1402: 0b 0b 3e 0b + 1406: 03 08 00 00 lb a6, 0(zero) + 140a: 04 16 + 140c: 00 03 + 140e: 0e 3a + 1410: 0b 3b 05 39 + 1414: 0b 49 13 00 + 1418: 00 05 + 141a: 26 00 + 141c: 49 13 + 141e: 00 00 + 1420: 06 01 + 1422: 01 49 + 1424: 13 01 13 00 addi sp, t1, 1 + 1428: 00 07 + 142a: 21 00 + 142c: 49 13 + 142e: 2f 0b 00 00 + 1432: 08 34 + 1434: 00 03 + 1436: 0e 3a + 1438: 0b 3b 0b 39 + 143c: 0b 49 13 3f + 1440: 19 3c + 1442: 19 00 + 1444: 00 09 + 1446: 16 00 + 1448: 03 0e 3a 0b lb t3, 179(s4) + 144c: 3b 0b 39 0b + 1450: 49 13 + 1452: 00 00 + 1454: 0a 13 + 1456: 01 0b + 1458: 0b 3a 0b 3b + 145c: 0b 39 0b 01 + 1460: 13 00 00 0b addi zero, zero, 176 + 1464: 0d 00 + 1466: 03 0e 3a 0b lb t3, 179(s4) + 146a: 3b 0b 39 0b + 146e: 49 13 + 1470: 0b 0b 0d 0b + 1474: 0c 0b + 1476: 38 0b + 1478: 00 00 + 147a: 0c 0d + 147c: 00 03 + 147e: 08 3a + 1480: 0b 3b 0b 39 + 1484: 0b 49 13 0b + 1488: 0b 0d 0b 0c + 148c: 0b 38 0b 00 + 1490: 00 0d + 1492: 17 01 03 0e auipc sp, 57392 + 1496: 0b 0b 3a 0b + 149a: 3b 0b 39 0b + 149e: 01 13 + 14a0: 00 00 + 14a2: 0e 0d + 14a4: 00 03 + 14a6: 08 3a + 14a8: 0b 3b 0b 39 + 14ac: 0b 49 13 00 + 14b0: 00 0f + 14b2: 0d 00 + 14b4: 03 0e 3a 0b lb t3, 179(s4) + 14b8: 3b 0b 39 0b + 14bc: 49 13 + 14be: 00 00 + 14c0: 10 2e + 14c2: 01 3f + 14c4: 19 03 + 14c6: 0e 3a + 14c8: 0b 3b 0b 39 + 14cc: 0b 27 19 49 + 14d0: 13 11 01 12 + 14d4: 06 40 + 14d6: 18 96 + 14d8: 42 19 + 14da: 01 13 + 14dc: 00 00 + 14de: 11 05 + 14e0: 00 03 + 14e2: 08 3a + 14e4: 0b 3b 0b 39 + 14e8: 0b 49 13 02 + 14ec: 17 00 00 12 auipc zero, 73728 + 14f0: 34 00 + 14f2: 03 0e 3a 0b lb t3, 179(s4) + 14f6: 3b 0b 39 0b + 14fa: 49 13 + 14fc: 02 17 + 14fe: 00 00 + 1500: 13 34 00 03 sltiu s0, zero, 48 + 1504: 0e 3a + 1506: 0b 3b 0b 39 + 150a: 0b 49 13 00 + 150e: 00 14 + 1510: 34 00 + 1512: 03 08 3a 0b lb a6, 179(s4) + 1516: 3b 0b 39 0b + 151a: 49 13 + 151c: 00 00 + 151e: 15 34 + 1520: 00 03 + 1522: 08 3a + 1524: 0b 3b 0b 39 + 1528: 0b 49 13 02 + 152c: 17 00 00 16 auipc zero, 90112 + 1530: 0b 01 55 17 + 1534: 01 13 + 1536: 00 00 + 1538: 17 0b 01 11 auipc s6, 69648 + 153c: 01 12 + 153e: 06 01 + 1540: 13 00 00 18 addi zero, zero, 384 + 1544: 0b 01 11 01 + 1548: 12 06 + 154a: 00 00 + 154c: 00 01 + 154e: 11 01 + 1550: 25 0e + 1552: 13 0b 03 0e addi s6, t1, 224 + 1556: 1b 0e 11 01 + 155a: 12 06 + 155c: 10 17 + 155e: 00 00 + 1560: 02 24 + 1562: 00 0b + 1564: 0b 3e 0b 03 + 1568: 0e 00 + 156a: 00 03 + 156c: 24 00 + 156e: 0b 0b 3e 0b + 1572: 03 08 00 00 lb a6, 0(zero) + 1576: 04 16 + 1578: 00 03 + 157a: 0e 3a + 157c: 0b 3b 05 39 + 1580: 0b 49 13 00 + 1584: 00 05 + 1586: 26 00 + 1588: 49 13 + 158a: 00 00 + 158c: 06 01 + 158e: 01 49 + 1590: 13 01 13 00 addi sp, t1, 1 + 1594: 00 07 + 1596: 21 00 + 1598: 49 13 + 159a: 2f 0b 00 00 + 159e: 08 34 + 15a0: 00 03 + 15a2: 0e 3a + 15a4: 0b 3b 0b 39 + 15a8: 0b 49 13 3f + 15ac: 19 3c + 15ae: 19 00 + 15b0: 00 09 + 15b2: 16 00 + 15b4: 03 0e 3a 0b lb t3, 179(s4) + 15b8: 3b 0b 39 0b + 15bc: 49 13 + 15be: 00 00 + 15c0: 0a 13 + 15c2: 01 0b + 15c4: 0b 3a 0b 3b + 15c8: 0b 39 0b 01 + 15cc: 13 00 00 0b addi zero, zero, 176 + 15d0: 0d 00 + 15d2: 03 0e 3a 0b lb t3, 179(s4) + 15d6: 3b 0b 39 0b + 15da: 49 13 + 15dc: 0b 0b 0d 0b + 15e0: 0c 0b + 15e2: 38 0b + 15e4: 00 00 + 15e6: 0c 0d + 15e8: 00 03 + 15ea: 08 3a + 15ec: 0b 3b 0b 39 + 15f0: 0b 49 13 0b + 15f4: 0b 0d 0b 0c + 15f8: 0b 38 0b 00 + 15fc: 00 0d + 15fe: 17 01 03 0e auipc sp, 57392 + 1602: 0b 0b 3a 0b + 1606: 3b 0b 39 0b + 160a: 01 13 + 160c: 00 00 + 160e: 0e 0d + 1610: 00 03 + 1612: 08 3a + 1614: 0b 3b 0b 39 + 1618: 0b 49 13 00 + 161c: 00 0f + 161e: 0d 00 + 1620: 03 0e 3a 0b lb t3, 179(s4) + 1624: 3b 0b 39 0b + 1628: 49 13 + 162a: 00 00 + 162c: 10 2e + 162e: 01 3f + 1630: 19 03 + 1632: 0e 3a + 1634: 0b 3b 0b 39 + 1638: 0b 27 19 49 + 163c: 13 11 01 12 + 1640: 06 40 + 1642: 18 96 + 1644: 42 19 + 1646: 01 13 + 1648: 00 00 + 164a: 11 05 + 164c: 00 03 + 164e: 08 3a + 1650: 0b 3b 0b 39 + 1654: 0b 49 13 02 + 1658: 17 00 00 12 auipc zero, 73728 + 165c: 34 00 + 165e: 03 0e 3a 0b lb t3, 179(s4) + 1662: 3b 0b 39 0b + 1666: 49 13 + 1668: 02 17 + 166a: 00 00 + 166c: 13 34 00 03 sltiu s0, zero, 48 + 1670: 0e 3a + 1672: 0b 3b 0b 39 + 1676: 0b 49 13 00 + 167a: 00 14 + 167c: 34 00 + 167e: 03 08 3a 0b lb a6, 179(s4) + 1682: 3b 0b 39 0b + 1686: 49 13 + 1688: 00 00 + 168a: 15 34 + 168c: 00 03 + 168e: 08 3a + 1690: 0b 3b 0b 39 + 1694: 0b 49 13 02 + 1698: 17 00 00 16 auipc zero, 90112 + 169c: 34 00 + 169e: 03 08 3a 0b lb a6, 179(s4) + 16a2: 3b 0b 39 0b + 16a6: 49 13 + 16a8: 02 18 + 16aa: 00 00 + 16ac: 17 0b 01 55 auipc s6, 348176 + 16b0: 17 01 13 00 auipc sp, 304 + 16b4: 00 18 + 16b6: 0b 01 01 13 + 16ba: 00 00 + 16bc: 19 0b + 16be: 01 11 + 16c0: 01 12 + 16c2: 06 01 + 16c4: 13 00 00 1a addi zero, zero, 416 + 16c8: 0b 01 55 17 + 16cc: 00 00 + 16ce: 1b 0b 01 11 + 16d2: 01 12 + 16d4: 06 00 + 16d6: 00 1c + 16d8: 34 00 + 16da: 03 0e 3a 0b lb t3, 179(s4) + 16de: 3b 0b 39 0b + 16e2: 49 13 + 16e4: 02 18 + 16e6: 00 00 + 16e8: 1d 01 + 16ea: 01 49 + 16ec: 13 00 00 00 nop + 16f0: 01 11 + 16f2: 01 25 + 16f4: 0e 13 + 16f6: 0b 03 0e 1b + 16fa: 0e 11 + 16fc: 01 12 + 16fe: 06 10 + 1700: 17 00 00 02 auipc zero, 8192 + 1704: 24 00 + 1706: 0b 0b 3e 0b + 170a: 03 08 00 00 lb a6, 0(zero) + 170e: 03 24 00 0b lw s0, 176(zero) + 1712: 0b 3e 0b 03 + 1716: 0e 00 + 1718: 00 04 + 171a: 16 00 + 171c: 03 0e 3a 0b lb t3, 179(s4) + 1720: 3b 05 39 0b + 1724: 49 13 + 1726: 00 00 + 1728: 05 26 + 172a: 00 49 + 172c: 13 00 00 06 addi zero, zero, 96 + 1730: 01 01 + 1732: 49 13 + 1734: 01 13 + 1736: 00 00 + 1738: 07 21 00 49 flw ft2, 1168(zero) + 173c: 13 2f 0b 00 slti t5, s6, 0 + 1740: 00 08 + 1742: 34 00 + 1744: 03 0e 3a 0b lb t3, 179(s4) + 1748: 3b 0b 39 0b + 174c: 49 13 + 174e: 3f 19 3c 19 + 1752: 00 00 + 1754: 09 16 + 1756: 00 03 + 1758: 0e 3a + 175a: 0b 3b 0b 39 + 175e: 0b 49 13 00 + 1762: 00 0a + 1764: 13 01 0b 0b addi sp, s6, 176 + 1768: 3a 0b + 176a: 3b 0b 39 0b + 176e: 01 13 + 1770: 00 00 + 1772: 0b 0d 00 03 + 1776: 0e 3a + 1778: 0b 3b 0b 39 + 177c: 0b 49 13 0b + 1780: 0b 0d 0b 0c + 1784: 0b 38 0b 00 + 1788: 00 0c + 178a: 0d 00 + 178c: 03 08 3a 0b lb a6, 179(s4) + 1790: 3b 0b 39 0b + 1794: 49 13 + 1796: 0b 0b 0d 0b + 179a: 0c 0b + 179c: 38 0b + 179e: 00 00 + 17a0: 0d 17 + 17a2: 01 03 + 17a4: 0e 0b + 17a6: 0b 3a 0b 3b + 17aa: 0b 39 0b 01 + 17ae: 13 00 00 0e addi zero, zero, 224 + 17b2: 0d 00 + 17b4: 03 08 3a 0b lb a6, 179(s4) + 17b8: 3b 0b 39 0b + 17bc: 49 13 + 17be: 00 00 + 17c0: 0f 0d 00 03 + 17c4: 0e 3a + 17c6: 0b 3b 0b 39 + 17ca: 0b 49 13 00 + 17ce: 00 10 + 17d0: 2e 01 + 17d2: 3f 19 03 0e + 17d6: 3a 0b + 17d8: 3b 0b 39 0b + 17dc: 27 19 49 13 + 17e0: 11 01 + 17e2: 12 06 + 17e4: 40 18 + 17e6: 97 42 19 01 auipc t0, 4500 + 17ea: 13 00 00 11 addi zero, zero, 272 + 17ee: 05 00 + 17f0: 03 08 3a 0b lb a6, 179(s4) + 17f4: 3b 0b 39 0b + 17f8: 49 13 + 17fa: 00 00 + 17fc: 12 34 + 17fe: 00 03 + 1800: 0e 3a + 1802: 0b 3b 0b 39 + 1806: 0b 49 13 02 + 180a: 17 00 00 13 auipc zero, 77824 + 180e: 34 00 + 1810: 03 08 3a 0b lb a6, 179(s4) + 1814: 3b 0b 39 0b + 1818: 49 13 + 181a: 00 00 + 181c: 14 34 + 181e: 00 03 + 1820: 08 3a + 1822: 0b 3b 0b 39 + 1826: 0b 49 13 02 + 182a: 17 00 00 15 auipc zero, 86016 + 182e: 34 00 + 1830: 03 08 3a 0b lb a6, 179(s4) + 1834: 3b 0b 39 0b + 1838: 49 13 + 183a: 02 18 + 183c: 00 00 + 183e: 16 0b + 1840: 01 11 + 1842: 01 12 + 1844: 06 01 + 1846: 13 00 00 17 addi zero, zero, 368 + 184a: 34 00 + 184c: 03 0e 3a 0b lb t3, 179(s4) + 1850: 3b 0b 39 0b + 1854: 49 13 + 1856: 02 18 + 1858: 00 00 + 185a: 18 0b + 185c: 01 55 + 185e: 17 01 13 00 auipc sp, 304 + 1862: 00 19 + 1864: 34 00 + 1866: 03 0e 3a 0b lb t3, 179(s4) + 186a: 3b 0b 39 0b + 186e: 49 13 + 1870: 1c 0b + 1872: 00 00 + 1874: 1a 0b + 1876: 01 55 + 1878: 17 00 00 1b auipc zero, 110592 + 187c: 34 00 + 187e: 03 0e 3a 0b lb t3, 179(s4) + 1882: 3b 0b 39 0b + 1886: 49 13 + 1888: 00 00 + 188a: 1c 0b + 188c: 01 01 + 188e: 13 00 00 1d addi zero, zero, 464 + 1892: 0b 01 00 00 + 1896: 1e 0b + 1898: 01 11 + 189a: 01 12 + 189c: 06 00 + 189e: 00 1f + 18a0: 01 01 + 18a2: 49 13 + 18a4: 00 00 + 18a6: 00 01 + 18a8: 11 01 + 18aa: 25 0e + 18ac: 13 0b 03 0e addi s6, t1, 224 + 18b0: 1b 0e 10 17 + 18b4: 00 00 + 18b6: 02 24 + 18b8: 00 0b + 18ba: 0b 3e 0b 03 + 18be: 08 00 + 18c0: 00 03 + 18c2: 24 00 + 18c4: 0b 0b 3e 0b + 18c8: 03 0e 00 00 lb t3, 0(zero) + 18cc: 04 16 + 18ce: 00 03 + 18d0: 0e 3a + 18d2: 0b 3b 05 39 + 18d6: 0b 49 13 00 + 18da: 00 05 + 18dc: 16 00 + 18de: 03 0e 3a 0b lb t3, 179(s4) + 18e2: 3b 0b 39 0b + 18e6: 49 13 + 18e8: 00 00 + 18ea: 06 17 + 18ec: 01 0b + 18ee: 0b 3a 0b 3b + 18f2: 0b 39 0b 01 + 18f6: 13 00 00 07 addi zero, zero, 112 + 18fa: 0d 00 + 18fc: 03 0e 3a 0b lb t3, 179(s4) + 1900: 3b 0b 39 0b + 1904: 49 13 + 1906: 00 00 + 1908: 08 01 + 190a: 01 49 + 190c: 13 01 13 00 addi sp, t1, 1 + 1910: 00 09 + 1912: 21 00 + 1914: 49 13 + 1916: 2f 0b 00 00 + 191a: 0a 13 + 191c: 01 0b + 191e: 0b 3a 0b 3b + 1922: 0b 39 0b 01 + 1926: 13 00 00 0b addi zero, zero, 176 + 192a: 0d 00 + 192c: 03 0e 3a 0b lb t3, 179(s4) + 1930: 3b 0b 39 0b + 1934: 49 13 + 1936: 38 0b + 1938: 00 00 + 193a: 0c 0f + 193c: 00 0b + 193e: 0b 00 00 0d + 1942: 13 01 03 0e addi sp, t1, 224 + 1946: 0b 0b 3a 0b + 194a: 3b 0b 39 0b + 194e: 01 13 + 1950: 00 00 + 1952: 0e 0d + 1954: 00 03 + 1956: 08 3a + 1958: 0b 3b 0b 39 + 195c: 0b 49 13 38 + 1960: 0b 00 00 0f + 1964: 0f 00 0b 0b + 1968: 49 13 + 196a: 00 00 + 196c: 10 13 + 196e: 01 03 + 1970: 0e 0b + 1972: 05 3a + 1974: 0b 3b 0b 39 + 1978: 0b 01 13 00 + 197c: 00 11 + 197e: 0d 00 + 1980: 03 0e 3a 0b lb t3, 179(s4) + 1984: 3b 0b 39 0b + 1988: 49 13 + 198a: 38 05 + 198c: 00 00 + 198e: 12 15 + 1990: 00 27 + 1992: 19 00 + 1994: 00 13 + 1996: 15 01 + 1998: 27 19 49 13 + 199c: 01 13 + 199e: 00 00 + 19a0: 14 05 + 19a2: 00 49 + 19a4: 13 00 00 15 addi zero, zero, 336 + 19a8: 26 00 + 19aa: 49 13 + 19ac: 00 00 + 19ae: 16 13 + 19b0: 01 03 + 19b2: 0e 0b + 19b4: 05 3a + 19b6: 0b 3b 05 39 + 19ba: 0b 01 13 00 + 19be: 00 17 + 19c0: 0d 00 + 19c2: 03 0e 3a 0b lb t3, 179(s4) + 19c6: 3b 05 39 0b + 19ca: 49 13 + 19cc: 38 0b + 19ce: 00 00 + 19d0: 18 0d + 19d2: 00 03 + 19d4: 0e 3a + 19d6: 0b 3b 05 39 + 19da: 0b 49 13 38 + 19de: 05 00 + 19e0: 00 19 + 19e2: 13 01 03 0e addi sp, t1, 224 + 19e6: 0b 0b 3a 0b + 19ea: 3b 05 39 0b + 19ee: 01 13 + 19f0: 00 00 + 19f2: 1a 13 + 19f4: 01 0b + 19f6: 0b 3a 0b 3b + 19fa: 05 39 + 19fc: 0b 01 13 00 + 1a00: 00 1b + 1a02: 17 01 0b 0b auipc sp, 45232 + 1a06: 3a 0b + 1a08: 3b 05 39 0b + 1a0c: 01 13 + 1a0e: 00 00 + 1a10: 1c 0d + 1a12: 00 03 + 1a14: 0e 3a + 1a16: 0b 3b 05 39 + 1a1a: 0b 49 13 00 + 1a1e: 00 1d + 1a20: 13 00 03 0e addi zero, t1, 224 + 1a24: 3c 19 + 1a26: 00 00 + 1a28: 1e 15 + 1a2a: 01 27 + 1a2c: 19 01 + 1a2e: 13 00 00 1f addi zero, zero, 496 + 1a32: 34 00 + 1a34: 03 0e 3a 0b lb t3, 179(s4) + 1a38: 3b 05 39 0b + 1a3c: 49 13 + 1a3e: 3f 19 3c 19 + 1a42: 00 00 + 1a44: 20 21 + 1a46: 00 00 + 1a48: 00 21 + 1a4a: 34 00 + 1a4c: 03 0e 3a 0b lb t3, 179(s4) + 1a50: 3b 0b 39 0b + 1a54: 49 13 + 1a56: 3f 19 3c 19 + 1a5a: 00 00 + 1a5c: 22 26 + 1a5e: 00 00 + 1a60: 00 23 + 1a62: 04 01 + 1a64: 03 0e 3e 0b lb t3, 179(t3) + 1a68: 0b 0b 49 13 + 1a6c: 3a 0b + 1a6e: 3b 0b 39 0b + 1a72: 01 13 + 1a74: 00 00 + 1a76: 24 28 + 1a78: 00 03 + 1a7a: 0e 1c + 1a7c: 0b 00 00 25 + 1a80: 34 00 + 1a82: 47 13 3a 0b + 1a86: 3b 05 39 0b + 1a8a: 02 18 + 1a8c: 00 00 + 1a8e: 00 01 + 1a90: 11 01 + 1a92: 25 0e + 1a94: 13 0b 03 0e addi s6, t1, 224 + 1a98: 1b 0e 11 01 + 1a9c: 12 06 + 1a9e: 10 17 + 1aa0: 00 00 + 1aa2: 02 24 + 1aa4: 00 0b + 1aa6: 0b 3e 0b 03 + 1aaa: 08 00 + 1aac: 00 03 + 1aae: 24 00 + 1ab0: 0b 0b 3e 0b + 1ab4: 03 0e 00 00 lb t3, 0(zero) + 1ab8: 04 16 + 1aba: 00 03 + 1abc: 0e 3a + 1abe: 0b 3b 05 39 + 1ac2: 0b 49 13 00 + 1ac6: 00 05 + 1ac8: 16 00 + 1aca: 03 0e 3a 0b lb t3, 179(s4) + 1ace: 3b 0b 39 0b + 1ad2: 49 13 + 1ad4: 00 00 + 1ad6: 06 17 + 1ad8: 01 0b + 1ada: 0b 3a 0b 3b + 1ade: 0b 39 0b 01 + 1ae2: 13 00 00 07 addi zero, zero, 112 + 1ae6: 0d 00 + 1ae8: 03 0e 3a 0b lb t3, 179(s4) + 1aec: 3b 0b 39 0b + 1af0: 49 13 + 1af2: 00 00 + 1af4: 08 01 + 1af6: 01 49 + 1af8: 13 01 13 00 addi sp, t1, 1 + 1afc: 00 09 + 1afe: 21 00 + 1b00: 49 13 + 1b02: 2f 0b 00 00 + 1b06: 0a 13 + 1b08: 01 0b + 1b0a: 0b 3a 0b 3b + 1b0e: 0b 39 0b 01 + 1b12: 13 00 00 0b addi zero, zero, 176 + 1b16: 0d 00 + 1b18: 03 0e 3a 0b lb t3, 179(s4) + 1b1c: 3b 0b 39 0b + 1b20: 49 13 + 1b22: 38 0b + 1b24: 00 00 + 1b26: 0c 0f + 1b28: 00 0b + 1b2a: 0b 00 00 0d + 1b2e: 13 01 03 0e addi sp, t1, 224 + 1b32: 0b 0b 3a 0b + 1b36: 3b 0b 39 0b + 1b3a: 01 13 + 1b3c: 00 00 + 1b3e: 0e 0d + 1b40: 00 03 + 1b42: 08 3a + 1b44: 0b 3b 0b 39 + 1b48: 0b 49 13 38 + 1b4c: 0b 00 00 0f + 1b50: 0f 00 0b 0b + 1b54: 49 13 + 1b56: 00 00 + 1b58: 10 13 + 1b5a: 01 03 + 1b5c: 0e 0b + 1b5e: 05 3a + 1b60: 0b 3b 0b 39 + 1b64: 0b 01 13 00 + 1b68: 00 11 + 1b6a: 0d 00 + 1b6c: 03 0e 3a 0b lb t3, 179(s4) + 1b70: 3b 0b 39 0b + 1b74: 49 13 + 1b76: 38 05 + 1b78: 00 00 + 1b7a: 12 15 + 1b7c: 00 27 + 1b7e: 19 00 + 1b80: 00 13 + 1b82: 15 01 + 1b84: 27 19 49 13 + 1b88: 01 13 + 1b8a: 00 00 + 1b8c: 14 05 + 1b8e: 00 49 + 1b90: 13 00 00 15 addi zero, zero, 336 + 1b94: 26 00 + 1b96: 49 13 + 1b98: 00 00 + 1b9a: 16 13 + 1b9c: 01 03 + 1b9e: 0e 0b + 1ba0: 05 3a + 1ba2: 0b 3b 05 39 + 1ba6: 0b 01 13 00 + 1baa: 00 17 + 1bac: 0d 00 + 1bae: 03 0e 3a 0b lb t3, 179(s4) + 1bb2: 3b 05 39 0b + 1bb6: 49 13 + 1bb8: 38 0b + 1bba: 00 00 + 1bbc: 18 0d + 1bbe: 00 03 + 1bc0: 0e 3a + 1bc2: 0b 3b 05 39 + 1bc6: 0b 49 13 38 + 1bca: 05 00 + 1bcc: 00 19 + 1bce: 13 01 03 0e addi sp, t1, 224 + 1bd2: 0b 0b 3a 0b + 1bd6: 3b 05 39 0b + 1bda: 01 13 + 1bdc: 00 00 + 1bde: 1a 13 + 1be0: 01 0b + 1be2: 0b 3a 0b 3b + 1be6: 05 39 + 1be8: 0b 01 13 00 + 1bec: 00 1b + 1bee: 17 01 0b 0b auipc sp, 45232 + 1bf2: 3a 0b + 1bf4: 3b 05 39 0b + 1bf8: 01 13 + 1bfa: 00 00 + 1bfc: 1c 0d + 1bfe: 00 03 + 1c00: 0e 3a + 1c02: 0b 3b 05 39 + 1c06: 0b 49 13 00 + 1c0a: 00 1d + 1c0c: 13 00 03 0e addi zero, t1, 224 + 1c10: 3c 19 + 1c12: 00 00 + 1c14: 1e 15 + 1c16: 01 27 + 1c18: 19 01 + 1c1a: 13 00 00 1f addi zero, zero, 496 + 1c1e: 34 00 + 1c20: 03 0e 3a 0b lb t3, 179(s4) + 1c24: 3b 05 39 0b + 1c28: 49 13 + 1c2a: 3f 19 3c 19 + 1c2e: 00 00 + 1c30: 20 21 + 1c32: 00 00 + 1c34: 00 21 + 1c36: 34 00 + 1c38: 03 0e 3a 0b lb t3, 179(s4) + 1c3c: 3b 0b 39 0b + 1c40: 49 13 + 1c42: 3f 19 3c 19 + 1c46: 00 00 + 1c48: 22 26 + 1c4a: 00 00 + 1c4c: 00 23 + 1c4e: 04 01 + 1c50: 03 0e 3e 0b lb t3, 179(t3) + 1c54: 0b 0b 49 13 + 1c58: 3a 0b + 1c5a: 3b 0b 39 0b + 1c5e: 01 13 + 1c60: 00 00 + 1c62: 24 28 + 1c64: 00 03 + 1c66: 0e 1c + 1c68: 0b 00 00 25 + 1c6c: 2e 01 + 1c6e: 3f 19 03 0e + 1c72: 3a 0b + 1c74: 3b 05 39 0b + 1c78: 27 19 49 13 + 1c7c: 11 01 + 1c7e: 12 06 + 1c80: 40 18 + 1c82: 97 42 19 00 auipc t0, 404 + 1c86: 00 26 + 1c88: 05 00 + 1c8a: 03 08 3a 0b lb a6, 179(s4) + 1c8e: 3b 05 39 0b + 1c92: 49 13 + 1c94: 02 17 + 1c96: 00 00 + 1c98: 27 34 00 03 + 1c9c: 08 3a + 1c9e: 0b 3b 05 39 + 1ca2: 0b 49 13 00 + 1ca6: 00 28 + 1ca8: 0b 01 55 17 + 1cac: 00 00 + 1cae: 29 34 + 1cb0: 00 03 + 1cb2: 0e 3a + 1cb4: 0b 3b 05 39 + 1cb8: 0b 49 13 02 + 1cbc: 17 00 00 2a auipc zero, 172032 + 1cc0: 34 00 + 1cc2: 03 08 3a 0b lb a6, 179(s4) + 1cc6: 3b 05 39 0b + 1cca: 49 13 + 1ccc: 02 17 + 1cce: 00 00 + 1cd0: 00 + +Disassembly of section .debug_line: + +00000000 .debug_line: + 0: 1f 09 00 00 + 4: 03 00 1b 02 lb zero, 33(s6) + 8: 00 00 + a: 01 01 + c: fb 0e 0d 00 + 10: 01 01 + 12: 01 01 + 14: 00 00 + 16: 00 01 + 18: 00 00 + 1a: 01 2e + 1c: 2e 2f + 1e: 2e 2e + 20: 2f 2e 2e 2f + 24: 2e 2e + 26: 2f 72 69 73 + 2a: 63 76 2d 67 bgeu s10, s2, 1644 + 2e: 63 63 2f 6c bltu t5, sp, 1734 + 32: 69 62 + 34: 67 63 63 00 + 38: 2f 68 6f 6d + 3c: 65 2f + 3e: 62 6c + 40: 61 69 + 42: 73 65 2f 64 csrrsi a0, 1602, 30 + 46: 65 76 + 48: 2f 72 69 73 + 4c: 63 76 2d 67 bgeu s10, s2, 1644 + 50: 6e 75 + 52: 2d 74 + 54: 6f 6f 6c 63 jal t5, 812598 + 58: 68 61 + 5a: 69 6e + 5c: 2f 62 75 69 + 60: 6c 64 + 62: 2f 62 75 69 + 66: 6c 64 + 68: 2d 67 + 6a: 63 63 2d 6e bltu s10, sp, 1766 + 6e: 65 77 + 70: 6c 69 + 72: 62 2d + 74: 73 74 61 67 csrrci s0, 1654, 2 + 78: 65 32 + 7a: 2f 67 63 63 + 7e: 2f 69 6e 63 + 82: 6c 75 + 84: 64 65 + 86: 00 2f + 88: 68 6f + 8a: 6d 65 + 8c: 2f 62 6c 61 + 90: 69 73 + 92: 65 2f + 94: 64 65 + 96: 76 2f + 98: 72 69 + 9a: 73 63 76 2d csrrsi t1, 727, 12 + 9e: 67 6e 75 2d + a2: 74 6f + a4: 6f 6c 63 68 jal s8, 222854 + a8: 61 69 + aa: 6e 2f + ac: 64 72 + ae: 6f 70 73 2f j 228086 + b2: 72 69 + b4: 73 63 76 33 csrrsi t1, mhpmevent23, 12 + b8: 32 2d + ba: 75 6e + bc: 6b 6e 6f 77 + c0: 6e 2d + c2: 65 6c + c4: 66 2f + c6: 69 6e + c8: 63 6c 75 64 bltu a0, t2, 1624 + cc: 65 2f + ce: 73 79 73 00 csrrci s2, 7, 6 + d2: 2f 68 6f 6d + d6: 65 2f + d8: 62 6c + da: 61 69 + dc: 73 65 2f 64 csrrsi a0, 1602, 30 + e0: 65 76 + e2: 2f 72 69 73 + e6: 63 76 2d 67 bgeu s10, s2, 1644 + ea: 6e 75 + ec: 2d 74 + ee: 6f 6f 6c 63 jal t5, 812598 + f2: 68 61 + f4: 69 6e + f6: 2f 64 72 6f + fa: 70 73 + fc: 2f 72 69 73 + 100: 63 76 33 32 bgeu t1, gp, 812 + 104: 2d 75 + 106: 6e 6b + 108: 6e 6f + 10a: 77 6e 2d 65 + 10e: 6c 66 + 110: 2f 69 6e 63 + 114: 6c 75 + 116: 64 65 + 118: 00 2e + 11a: 2e 2f + 11c: 2e 2e + 11e: 2f 2e 2e 2f + 122: 2e 2e + 124: 2f 72 69 73 + 128: 63 76 2d 67 bgeu s10, s2, 1644 + 12c: 63 63 2f 6c bltu t5, sp, 1734 + 130: 69 62 + 132: 67 63 63 2f + 136: 2e 2e + 138: 2f 69 6e 63 + 13c: 6c 75 + 13e: 64 65 + 140: 00 2e + 142: 2e 2f + 144: 2e 2e + 146: 2f 2e 2e 2f + 14a: 2e 2e + 14c: 2f 72 69 73 + 150: 63 76 2d 67 bgeu s10, s2, 1644 + 154: 63 63 2f 6c bltu t5, sp, 1734 + 158: 69 62 + 15a: 67 63 63 2f + 15e: 2e 2e + 160: 2f 67 63 63 + 164: 2f 63 6f 6e + 168: 66 69 + 16a: 67 2f 72 69 + 16e: 73 63 76 00 csrrsi t1, 7, 12 + 172: 2e 2e + 174: 2f 2e 2e 2f + 178: 2e 2f + 17a: 67 63 63 00 + 17e: 00 6c + 180: 69 62 + 182: 67 63 63 32 + 186: 2e 63 + 188: 00 01 + 18a: 00 00 + 18c: 73 74 64 64 csrrci s0, 1606, 8 + 190: 65 66 + 192: 2e 68 + 194: 00 02 + 196: 00 00 + 198: 5f 74 79 70 + 19c: 65 73 + 19e: 2e 68 + 1a0: 00 03 + 1a2: 00 00 + 1a4: 72 65 + 1a6: 65 6e + 1a8: 74 2e + 1aa: 68 00 + 1ac: 03 00 00 6c lb zero, 1728(zero) + 1b0: 6f 63 6b 2e jal t1, 746214 + 1b4: 68 00 + 1b6: 03 00 00 65 lb zero, 1616(zero) + 1ba: 72 72 + 1bc: 6e 6f + 1be: 2e 68 + 1c0: 00 03 + 1c2: 00 00 + 1c4: 73 74 64 6c csrrci s0, 1734, 8 + 1c8: 69 62 + 1ca: 2e 68 + 1cc: 00 04 + 1ce: 00 00 + 1d0: 75 6e + 1d2: 69 73 + 1d4: 74 64 + 1d6: 2e 68 + 1d8: 00 03 + 1da: 00 00 + 1dc: 74 69 + 1de: 6d 65 + 1e0: 2e 68 + 1e2: 00 04 + 1e4: 00 00 + 1e6: 68 61 + 1e8: 73 68 74 61 csrrsi a6, 1559, 8 + 1ec: 62 2e + 1ee: 68 00 + 1f0: 05 00 + 1f2: 00 72 + 1f4: 69 73 + 1f6: 63 76 2d 6f bgeu s10, s2, 1772 + 1fa: 70 74 + 1fc: 73 2e 68 00 csrrs t3, 6, a6 + 200: 06 00 + 202: 00 69 + 204: 6e 73 + 206: 6e 2d + 208: 63 6f 6e 73 bltu t3, s6, 1854 + 20c: 74 61 + 20e: 6e 74 + 210: 73 2e 68 00 csrrs t3, 6, a6 + 214: 07 00 00 6c + 218: 69 62 + 21a: 67 63 63 32 + 21e: 2e 68 + 220: 00 01 + 222: 00 00 + 224: 00 05 + 226: 01 00 + 228: 05 02 + 22a: ac ff + 22c: 00 80 + 22e: 03 a6 0a 01 lw a2, 16(s5) + 232: 05 03 + 234: 03 01 09 00 lb sp, 0(s2) + 238: 00 01 + 23a: 05 01 + 23c: 06 03 + 23e: 7f 09 00 00 + 242: 01 05 + 244: 03 06 03 d2 lb a2, -736(t1) + 248: 7d 09 + 24a: 04 00 + 24c: 01 03 + 24e: 01 09 + 250: 00 00 + 252: 01 03 + 254: 01 09 + 256: 00 00 + 258: 01 03 + 25a: 01 09 + 25c: 00 00 + 25e: 01 03 + 260: 01 09 + 262: 00 00 + 264: 01 03 + 266: 01 09 + 268: 00 00 + 26a: 01 03 + 26c: 02 09 + 26e: 00 00 + 270: 01 05 + 272: 01 06 + 274: 03 a7 02 09 lw a4, 144(t0) + 278: 00 00 + 27a: 01 05 + 27c: 06 03 + 27e: d9 7d + 280: 09 04 + 282: 00 01 + 284: 05 03 + 286: 06 03 + 288: 01 09 + 28a: 04 00 + 28c: 01 05 + 28e: 06 06 + 290: 03 00 09 00 lb zero, 0(s2) + 294: 00 01 + 296: 05 03 + 298: 06 03 + 29a: 01 09 + 29c: 04 00 + 29e: 01 05 + 2a0: 06 06 + 2a2: 03 00 09 00 lb zero, 0(s2) + 2a6: 00 01 + 2a8: 05 03 + 2aa: 06 03 + 2ac: 01 09 + 2ae: 04 00 + 2b0: 01 03 + 2b2: 25 09 + 2b4: 00 00 + 2b6: 01 05 + 2b8: 06 06 + 2ba: 03 00 09 00 lb zero, 0(s2) + 2be: 00 01 + 2c0: 05 07 + 2c2: 06 03 + 2c4: 02 09 + 2c6: 04 00 + 2c8: 01 05 + 2ca: 0a 06 + 2cc: 03 00 09 08 lb zero, 128(s2) + 2d0: 00 01 + 2d2: 05 04 + 2d4: 06 03 + 2d6: 04 09 + 2d8: 04 00 + 2da: 01 03 + 2dc: 00 09 + 2de: 00 00 + 2e0: 01 03 + 2e2: 00 09 + 2e4: 00 00 + 2e6: 01 03 + 2e8: 00 09 + 2ea: 00 00 + 2ec: 01 03 + 2ee: 00 09 + 2f0: 00 00 + 2f2: 01 03 + 2f4: 00 09 + 2f6: 14 00 + 2f8: 01 03 + 2fa: 00 09 + 2fc: 18 00 + 2fe: 01 03 + 300: 02 09 + 302: 00 00 + 304: 01 05 + 306: 07 06 03 00 + 30a: 09 00 + 30c: 00 01 + 30e: 05 08 + 310: 06 03 + 312: 05 09 + 314: 04 00 + 316: 01 05 + 318: 11 06 + 31a: 03 01 09 00 lb sp, 0(s2) + 31e: 00 01 + 320: 05 1e + 322: 03 00 09 04 lb zero, 64(s2) + 326: 00 01 + 328: 05 0b + 32a: 03 7f 09 04 + 32e: 00 01 + 330: 05 08 + 332: 06 03 + 334: 01 09 + 336: 04 00 + 338: 01 05 + 33a: 0b 06 03 00 + 33e: 09 00 + 340: 00 01 + 342: 05 08 + 344: 06 03 + 346: 01 09 + 348: 04 00 + 34a: 01 05 + 34c: 0b 06 03 00 + 350: 09 00 + 352: 00 01 + 354: 05 04 + 356: 06 03 + 358: 03 09 04 00 lb s2, 0(s0) + 35c: 01 03 + 35e: 00 09 + 360: 00 00 + 362: 01 03 + 364: 00 09 + 366: 00 00 + 368: 01 03 + 36a: 00 09 + 36c: 00 00 + 36e: 01 03 + 370: 00 09 + 372: 04 00 + 374: 01 03 + 376: 00 09 + 378: 0c 00 + 37a: 01 03 + 37c: 00 09 + 37e: 08 00 + 380: 01 03 + 382: 00 09 + 384: 00 00 + 386: 01 03 + 388: 00 09 + 38a: 08 00 + 38c: 01 03 + 38e: 00 09 + 390: 08 00 + 392: 01 03 + 394: 00 09 + 396: 04 00 + 398: 01 03 + 39a: 00 09 + 39c: 08 00 + 39e: 01 03 + 3a0: 00 09 + 3a2: 04 00 + 3a4: 01 03 + 3a6: 00 09 + 3a8: 04 00 + 3aa: 01 03 + 3ac: 00 09 + 3ae: 08 00 + 3b0: 01 03 + 3b2: 00 09 + 3b4: 04 00 + 3b6: 01 03 + 3b8: 00 09 + 3ba: 04 00 + 3bc: 01 03 + 3be: 00 09 + 3c0: 0c 00 + 3c2: 01 03 + 3c4: 00 09 + 3c6: 0c 00 + 3c8: 01 03 + 3ca: 00 09 + 3cc: 00 00 + 3ce: 01 03 + 3d0: 00 09 + 3d2: 08 00 + 3d4: 01 03 + 3d6: 00 09 + 3d8: 08 00 + 3da: 01 03 + 3dc: 00 09 + 3de: 04 00 + 3e0: 01 03 + 3e2: 00 09 + 3e4: 04 00 + 3e6: 01 03 + 3e8: 00 09 + 3ea: 04 00 + 3ec: 01 03 + 3ee: 00 09 + 3f0: 00 00 + 3f2: 01 03 + 3f4: 00 09 + 3f6: 08 00 + 3f8: 01 03 + 3fa: 00 09 + 3fc: 00 00 + 3fe: 01 03 + 400: 01 09 + 402: 00 00 + 404: 01 05 + 406: 0b 06 03 fe + 40a: 00 09 + 40c: 00 00 + 40e: 01 05 + 410: 04 03 + 412: f5 7e + 414: 09 08 + 416: 00 01 + 418: 06 03 + 41a: 15 09 + 41c: 14 00 + 41e: 01 05 + 420: 07 06 03 00 + 424: 09 00 + 426: 00 01 + 428: 05 06 + 42a: 06 03 + 42c: 01 09 + 42e: 04 00 + 430: 01 05 + 432: 09 06 + 434: 03 00 09 00 lb zero, 0(s2) + 438: 00 01 + 43a: 05 04 + 43c: 06 03 + 43e: 02 09 + 440: 08 00 + 442: 01 03 + 444: 00 09 + 446: 00 00 + 448: 01 03 + 44a: 00 09 + 44c: 00 00 + 44e: 01 03 + 450: 00 09 + 452: 00 00 + 454: 01 03 + 456: 00 09 + 458: 00 00 + 45a: 01 03 + 45c: 00 09 + 45e: 14 00 + 460: 01 03 + 462: 00 09 + 464: 18 00 + 466: 01 03 + 468: 02 09 + 46a: 00 00 + 46c: 01 05 + 46e: 07 06 03 00 + 472: 09 00 + 474: 00 01 + 476: 05 08 + 478: 06 03 + 47a: 09 09 + 47c: 04 00 + 47e: 01 05 + 480: 0b 06 03 00 + 484: 09 00 + 486: 00 01 + 488: 05 08 + 48a: 06 03 + 48c: 01 09 + 48e: 04 00 + 490: 01 05 + 492: 0b 06 03 00 + 496: 09 00 + 498: 00 01 + 49a: 05 08 + 49c: 06 03 + 49e: 0d 09 + 4a0: 04 00 + 4a2: 01 05 + 4a4: 04 03 + 4a6: 05 09 + 4a8: 00 00 + 4aa: 01 03 + 4ac: 00 09 + 4ae: 00 00 + 4b0: 01 03 + 4b2: 00 09 + 4b4: 00 00 + 4b6: 01 03 + 4b8: 00 09 + 4ba: 00 00 + 4bc: 01 03 + 4be: 00 09 + 4c0: 04 00 + 4c2: 01 03 + 4c4: 00 09 + 4c6: 08 00 + 4c8: 01 03 + 4ca: 00 09 + 4cc: 08 00 + 4ce: 01 03 + 4d0: 00 09 + 4d2: 04 00 + 4d4: 01 03 + 4d6: 00 09 + 4d8: 0c 00 + 4da: 01 03 + 4dc: 00 09 + 4de: 00 00 + 4e0: 01 03 + 4e2: 00 09 + 4e4: 08 00 + 4e6: 01 03 + 4e8: 00 09 + 4ea: 08 00 + 4ec: 01 03 + 4ee: 00 09 + 4f0: 04 00 + 4f2: 01 03 + 4f4: 00 09 + 4f6: 04 00 + 4f8: 01 03 + 4fa: 00 09 + 4fc: 08 00 + 4fe: 01 03 + 500: 00 09 + 502: 04 00 + 504: 01 03 + 506: 00 09 + 508: 04 00 + 50a: 01 03 + 50c: 00 09 + 50e: 0c 00 + 510: 01 03 + 512: 00 09 + 514: 0c 00 + 516: 01 03 + 518: 00 09 + 51a: 00 00 + 51c: 01 03 + 51e: 00 09 + 520: 08 00 + 522: 01 03 + 524: 00 09 + 526: 08 00 + 528: 01 03 + 52a: 00 09 + 52c: 04 00 + 52e: 01 03 + 530: 00 09 + 532: 04 00 + 534: 01 03 + 536: 00 09 + 538: 04 00 + 53a: 01 03 + 53c: 00 09 + 53e: 00 00 + 540: 01 03 + 542: 00 09 + 544: 08 00 + 546: 01 05 + 548: 03 03 e3 00 lb t1, 14(t1) + 54c: 09 00 + 54e: 00 01 + 550: 03 01 09 00 lb sp, 0(s2) + 554: 00 01 + 556: 05 01 + 558: 06 03 + 55a: e1 00 + 55c: 09 00 + 55e: 00 01 + 560: 05 04 + 562: 03 9d 7e 09 lh s10, 151(t4) + 566: 04 00 + 568: 01 05 + 56a: 08 06 + 56c: 03 12 09 14 lh tp, 320(s2) + 570: 00 01 + 572: 03 02 09 00 lb tp, 0(s2) + 576: 00 01 + 578: 05 0b + 57a: 06 03 + 57c: 00 09 + 57e: 00 00 + 580: 01 05 + 582: 08 06 + 584: 03 01 09 04 lb sp, 64(s2) + 588: 00 01 + 58a: 05 0b + 58c: 06 03 + 58e: 00 09 + 590: 00 00 + 592: 01 05 + 594: 08 06 + 596: 03 01 09 04 lb sp, 64(s2) + 59a: 00 01 + 59c: 05 0b + 59e: 06 03 + 5a0: 01 09 + 5a2: 00 00 + 5a4: 01 05 + 5a6: 11 03 + 5a8: 7f 09 04 00 + 5ac: 01 05 + 5ae: 1e 03 + 5b0: 00 09 + 5b2: 04 00 + 5b4: 01 05 + 5b6: 08 03 + 5b8: 03 09 04 00 lb s2, 0(s0) + 5bc: 01 05 + 5be: 0b 03 7d 09 + 5c2: 04 00 + 5c4: 01 05 + 5c6: 08 06 + 5c8: 03 01 09 04 lb sp, 64(s2) + 5cc: 00 01 + 5ce: 03 02 09 00 lb tp, 0(s2) + 5d2: 00 01 + 5d4: 03 00 09 00 lb zero, 0(s2) + 5d8: 00 01 + 5da: 03 00 09 00 lb zero, 0(s2) + 5de: 00 01 + 5e0: 03 00 09 00 lb zero, 0(s2) + 5e4: 00 01 + 5e6: 03 00 09 00 lb zero, 0(s2) + 5ea: 00 01 + 5ec: 03 00 09 0c lb zero, 192(s2) + 5f0: 00 01 + 5f2: 03 00 09 00 lb zero, 0(s2) + 5f6: 00 01 + 5f8: 03 00 09 08 lb zero, 128(s2) + 5fc: 00 01 + 5fe: 03 00 09 0c lb zero, 192(s2) + 602: 00 01 + 604: 03 00 09 00 lb zero, 0(s2) + 608: 00 01 + 60a: 03 00 09 08 lb zero, 128(s2) + 60e: 00 01 + 610: 03 00 09 08 lb zero, 128(s2) + 614: 00 01 + 616: 03 00 09 04 lb zero, 64(s2) + 61a: 00 01 + 61c: 03 00 09 04 lb zero, 64(s2) + 620: 00 01 + 622: 03 00 09 08 lb zero, 128(s2) + 626: 00 01 + 628: 03 00 09 04 lb zero, 64(s2) + 62c: 00 01 + 62e: 03 00 09 04 lb zero, 64(s2) + 632: 00 01 + 634: 03 00 09 0c lb zero, 192(s2) + 638: 00 01 + 63a: 03 00 09 08 lb zero, 128(s2) + 63e: 00 01 + 640: 03 00 09 04 lb zero, 64(s2) + 644: 00 01 + 646: 03 00 09 08 lb zero, 128(s2) + 64a: 00 01 + 64c: 03 00 09 08 lb zero, 128(s2) + 650: 00 01 + 652: 03 00 09 04 lb zero, 64(s2) + 656: 00 01 + 658: 03 00 09 04 lb zero, 64(s2) + 65c: 00 01 + 65e: 03 00 09 08 lb zero, 128(s2) + 662: 00 01 + 664: 03 00 09 08 lb zero, 128(s2) + 668: 00 01 + 66a: 03 00 09 04 lb zero, 64(s2) + 66e: 00 01 + 670: 05 07 + 672: 03 15 09 04 lh a0, 64(s2) + 676: 00 01 + 678: 05 0a + 67a: 06 03 + 67c: 00 09 + 67e: 00 00 + 680: 01 05 + 682: 04 06 + 684: 03 13 09 04 lh t1, 64(s2) + 688: 00 01 + 68a: 03 00 09 00 lb zero, 0(s2) + 68e: 00 01 + 690: 03 00 09 00 lb zero, 0(s2) + 694: 00 01 + 696: 03 00 09 00 lb zero, 0(s2) + 69a: 00 01 + 69c: 03 00 09 00 lb zero, 0(s2) + 6a0: 00 01 + 6a2: 03 00 09 14 lb zero, 320(s2) + 6a6: 00 01 + 6a8: 03 00 09 20 lb zero, 512(s2) + 6ac: 00 01 + 6ae: 03 01 09 00 lb sp, 0(s2) + 6b2: 00 01 + 6b4: 05 07 + 6b6: 06 03 + 6b8: 00 09 + 6ba: 00 00 + 6bc: 01 05 + 6be: 08 06 + 6c0: 03 0a 09 04 lb s4, 64(s2) + 6c4: 00 01 + 6c6: 06 03 + 6c8: 02 09 + 6ca: 00 00 + 6cc: 01 05 + 6ce: 0b 03 7e 09 + 6d2: 04 00 + 6d4: 01 05 + 6d6: 14 03 + 6d8: 00 09 + 6da: 04 00 + 6dc: 01 05 + 6de: 04 03 + 6e0: 75 09 + 6e2: 0c 00 + 6e4: 01 05 + 6e6: 08 06 + 6e8: 03 1e 09 14 lh t3, 320(s2) + 6ec: 00 01 + 6ee: 03 03 09 00 lb t1, 0(s2) + 6f2: 00 01 + 6f4: 03 02 09 00 lb tp, 0(s2) + 6f8: 00 01 + 6fa: 05 1e + 6fc: 06 03 + 6fe: 00 09 + 700: 00 00 + 702: 01 05 + 704: 11 03 + 706: 00 09 + 708: 04 00 + 70a: 01 05 + 70c: 0b 03 00 09 + 710: 04 00 + 712: 01 05 + 714: 08 06 + 716: 03 01 09 04 lb sp, 64(s2) + 71a: 00 01 + 71c: 06 03 + 71e: 05 09 + 720: 00 00 + 722: 01 05 + 724: 0b 03 7b 09 + 728: 04 00 + 72a: 01 05 + 72c: 08 06 + 72e: 03 01 09 04 lb sp, 64(s2) + 732: 00 01 + 734: 05 0b + 736: 06 03 + 738: 00 09 + 73a: 00 00 + 73c: 01 05 + 73e: 08 06 + 740: 03 01 09 04 lb sp, 64(s2) + 744: 00 01 + 746: 06 03 + 748: 03 09 00 00 lb s2, 0(zero) + 74c: 01 05 + 74e: 11 03 + 750: 7d 09 + 752: 04 00 + 754: 01 05 + 756: 1e 03 + 758: 00 09 + 75a: 04 00 + 75c: 01 05 + 75e: 0b 03 00 09 + 762: 04 00 + 764: 01 05 + 766: 08 06 + 768: 03 01 09 04 lb sp, 64(s2) + 76c: 00 01 + 76e: 03 02 09 00 lb tp, 0(s2) + 772: 00 01 + 774: 03 00 09 00 lb zero, 0(s2) + 778: 00 01 + 77a: 03 00 09 00 lb zero, 0(s2) + 77e: 00 01 + 780: 03 00 09 00 lb zero, 0(s2) + 784: 00 01 + 786: 03 00 09 00 lb zero, 0(s2) + 78a: 00 01 + 78c: 03 00 09 08 lb zero, 128(s2) + 790: 00 01 + 792: 03 00 09 00 lb zero, 0(s2) + 796: 00 01 + 798: 03 00 09 08 lb zero, 128(s2) + 79c: 00 01 + 79e: 03 00 09 0c lb zero, 192(s2) + 7a2: 00 01 + 7a4: 03 00 09 00 lb zero, 0(s2) + 7a8: 00 01 + 7aa: 03 00 09 08 lb zero, 128(s2) + 7ae: 00 01 + 7b0: 03 00 09 08 lb zero, 128(s2) + 7b4: 00 01 + 7b6: 03 00 09 04 lb zero, 64(s2) + 7ba: 00 01 + 7bc: 03 00 09 04 lb zero, 64(s2) + 7c0: 00 01 + 7c2: 03 00 09 08 lb zero, 128(s2) + 7c6: 00 01 + 7c8: 03 00 09 04 lb zero, 64(s2) + 7cc: 00 01 + 7ce: 03 00 09 04 lb zero, 64(s2) + 7d2: 00 01 + 7d4: 03 00 09 04 lb zero, 64(s2) + 7d8: 00 01 + 7da: 03 00 09 08 lb zero, 128(s2) + 7de: 00 01 + 7e0: 03 00 09 0c lb zero, 192(s2) + 7e4: 00 01 + 7e6: 03 00 09 08 lb zero, 128(s2) + 7ea: 00 01 + 7ec: 03 00 09 08 lb zero, 128(s2) + 7f0: 00 01 + 7f2: 03 00 09 04 lb zero, 64(s2) + 7f6: 00 01 + 7f8: 03 00 09 04 lb zero, 64(s2) + 7fc: 00 01 + 7fe: 03 00 09 08 lb zero, 128(s2) + 802: 00 01 + 804: 06 03 + 806: 01 09 + 808: 04 00 + 80a: 01 03 + 80c: 7f 09 04 00 + 810: 01 03 + 812: 01 09 + 814: 04 00 + 816: 01 03 + 818: 7f 09 08 00 + 81c: 01 06 + 81e: 03 00 09 04 lb zero, 64(s2) + 822: 00 01 + 824: 03 00 09 00 lb zero, 0(s2) + 828: 00 01 + 82a: 03 00 09 00 lb zero, 0(s2) + 82e: 00 01 + 830: 03 01 09 00 lb sp, 0(s2) + 834: 00 01 + 836: 03 00 09 00 lb zero, 0(s2) + 83a: 00 01 + 83c: 03 00 09 00 lb zero, 0(s2) + 840: 00 01 + 842: 03 00 09 00 lb zero, 0(s2) + 846: 00 01 + 848: 03 00 09 00 lb zero, 0(s2) + 84c: 00 01 + 84e: 03 00 09 08 lb zero, 128(s2) + 852: 00 01 + 854: 03 00 09 00 lb zero, 0(s2) + 858: 00 01 + 85a: 03 00 09 04 lb zero, 64(s2) + 85e: 00 01 + 860: 03 00 09 04 lb zero, 64(s2) + 864: 00 01 + 866: 03 00 09 00 lb zero, 0(s2) + 86a: 00 01 + 86c: 03 00 09 04 lb zero, 64(s2) + 870: 00 01 + 872: 03 00 09 14 lb zero, 320(s2) + 876: 00 01 + 878: 03 00 09 00 lb zero, 0(s2) + 87c: 00 01 + 87e: 03 00 09 00 lb zero, 0(s2) + 882: 00 01 + 884: 03 00 09 04 lb zero, 64(s2) + 888: 00 01 + 88a: 03 00 09 04 lb zero, 64(s2) + 88e: 00 01 + 890: 03 00 09 08 lb zero, 128(s2) + 894: 00 01 + 896: 03 00 09 00 lb zero, 0(s2) + 89a: 00 01 + 89c: 03 02 09 00 lb tp, 0(s2) + 8a0: 00 01 + 8a2: 05 0b + 8a4: 06 03 + 8a6: 00 09 + 8a8: 00 00 + 8aa: 01 05 + 8ac: 14 03 + 8ae: 00 09 + 8b0: 04 00 + 8b2: 01 05 + 8b4: 08 03 + 8b6: 7e 09 + 8b8: 04 00 + 8ba: 01 05 + 8bc: 0b 03 7d 09 + 8c0: 14 00 + 8c2: 01 05 + 8c4: 08 03 + 8c6: 03 09 04 00 lb s2, 0(s0) + 8ca: 01 05 + 8cc: 0b 03 08 09 + 8d0: 04 00 + 8d2: 01 05 + 8d4: 21 03 + 8d6: 7a 09 + 8d8: 04 00 + 8da: 01 05 + 8dc: 05 06 + 8de: 03 02 09 04 lb tp, 64(s2) + 8e2: 00 01 + 8e4: 05 07 + 8e6: 06 03 + 8e8: 00 09 + 8ea: 00 00 + 8ec: 01 05 + 8ee: 05 06 + 8f0: 03 01 09 04 lb sp, 64(s2) + 8f4: 00 01 + 8f6: 03 00 09 00 lb zero, 0(s2) + 8fa: 00 01 + 8fc: 03 00 09 00 lb zero, 0(s2) + 900: 00 01 + 902: 03 00 09 00 lb zero, 0(s2) + 906: 00 01 + 908: 03 00 09 00 lb zero, 0(s2) + 90c: 00 01 + 90e: 05 07 + 910: 06 03 + 912: 43 09 04 00 fmadd.s fs2, fs0, ft0, ft0, rne + 916: 01 03 + 918: 7f 09 04 00 + 91c: 01 09 + 91e: 08 00 + 920: 00 01 + 922: 01 bd + 924: 09 00 + 926: 00 03 + 928: 00 1b + 92a: 02 00 + 92c: 00 01 + 92e: 01 fb + 930: 0e 0d + 932: 00 01 + 934: 01 01 + 936: 01 00 + 938: 00 00 + 93a: 01 00 + 93c: 00 01 + 93e: 2e 2e + 940: 2f 2e 2e 2f + 944: 2e 2e + 946: 2f 2e 2e 2f + 94a: 72 69 + 94c: 73 63 76 2d csrrsi t1, 727, 12 + 950: 67 63 63 2f + 954: 6c 69 + 956: 62 67 + 958: 63 63 00 2f bltu zero, a6, 742 + 95c: 68 6f + 95e: 6d 65 + 960: 2f 62 6c 61 + 964: 69 73 + 966: 65 2f + 968: 64 65 + 96a: 76 2f + 96c: 72 69 + 96e: 73 63 76 2d csrrsi t1, 727, 12 + 972: 67 6e 75 2d + 976: 74 6f + 978: 6f 6c 63 68 jal s8, 222854 + 97c: 61 69 + 97e: 6e 2f + 980: 62 75 + 982: 69 6c + 984: 64 2f + 986: 62 75 + 988: 69 6c + 98a: 64 2d + 98c: 67 63 63 2d + 990: 6e 65 + 992: 77 6c 69 62 + 996: 2d 73 + 998: 74 61 + 99a: 67 65 32 2f + 99e: 67 63 63 2f + 9a2: 69 6e + 9a4: 63 6c 75 64 bltu a0, t2, 1624 + 9a8: 65 00 + 9aa: 2f 68 6f 6d + 9ae: 65 2f + 9b0: 62 6c + 9b2: 61 69 + 9b4: 73 65 2f 64 csrrsi a0, 1602, 30 + 9b8: 65 76 + 9ba: 2f 72 69 73 + 9be: 63 76 2d 67 bgeu s10, s2, 1644 + 9c2: 6e 75 + 9c4: 2d 74 + 9c6: 6f 6f 6c 63 jal t5, 812598 + 9ca: 68 61 + 9cc: 69 6e + 9ce: 2f 64 72 6f + 9d2: 70 73 + 9d4: 2f 72 69 73 + 9d8: 63 76 33 32 bgeu t1, gp, 812 + 9dc: 2d 75 + 9de: 6e 6b + 9e0: 6e 6f + 9e2: 77 6e 2d 65 + 9e6: 6c 66 + 9e8: 2f 69 6e 63 + 9ec: 6c 75 + 9ee: 64 65 + 9f0: 2f 73 79 73 + 9f4: 00 2f + 9f6: 68 6f + 9f8: 6d 65 + 9fa: 2f 62 6c 61 + 9fe: 69 73 + a00: 65 2f + a02: 64 65 + a04: 76 2f + a06: 72 69 + a08: 73 63 76 2d csrrsi t1, 727, 12 + a0c: 67 6e 75 2d + a10: 74 6f + a12: 6f 6c 63 68 jal s8, 222854 + a16: 61 69 + a18: 6e 2f + a1a: 64 72 + a1c: 6f 70 73 2f j 228086 + a20: 72 69 + a22: 73 63 76 33 csrrsi t1, mhpmevent23, 12 + a26: 32 2d + a28: 75 6e + a2a: 6b 6e 6f 77 + a2e: 6e 2d + a30: 65 6c + a32: 66 2f + a34: 69 6e + a36: 63 6c 75 64 bltu a0, t2, 1624 + a3a: 65 00 + a3c: 2e 2e + a3e: 2f 2e 2e 2f + a42: 2e 2e + a44: 2f 2e 2e 2f + a48: 72 69 + a4a: 73 63 76 2d csrrsi t1, 727, 12 + a4e: 67 63 63 2f + a52: 6c 69 + a54: 62 67 + a56: 63 63 2f 2e bltu t5, sp, 742 + a5a: 2e 2f + a5c: 69 6e + a5e: 63 6c 75 64 bltu a0, t2, 1624 + a62: 65 00 + a64: 2e 2e + a66: 2f 2e 2e 2f + a6a: 2e 2e + a6c: 2f 2e 2e 2f + a70: 72 69 + a72: 73 63 76 2d csrrsi t1, 727, 12 + a76: 67 63 63 2f + a7a: 6c 69 + a7c: 62 67 + a7e: 63 63 2f 2e bltu t5, sp, 742 + a82: 2e 2f + a84: 67 63 63 2f + a88: 63 6f 6e 66 bltu t3, t1, 1662 + a8c: 69 67 + a8e: 2f 72 69 73 + a92: 63 76 00 2e bgeu zero, zero, 748 + a96: 2e 2f + a98: 2e 2e + a9a: 2f 2e 2f 67 + a9e: 63 63 00 00 bltu zero, zero, 6 + aa2: 6c 69 + aa4: 62 67 + aa6: 63 63 32 2e bltu tp, gp, 742 + aaa: 63 00 01 00 beqz sp, 0 + aae: 00 73 + ab0: 74 64 + ab2: 64 65 + ab4: 66 2e + ab6: 68 00 + ab8: 02 00 + aba: 00 5f + abc: 74 79 + abe: 70 65 + ac0: 73 2e 68 00 csrrs t3, 6, a6 + ac4: 03 00 00 72 lb zero, 1824(zero) + ac8: 65 65 + aca: 6e 74 + acc: 2e 68 + ace: 00 03 + ad0: 00 00 + ad2: 6c 6f + ad4: 63 6b 2e 68 bltu t3, sp, 1686 + ad8: 00 03 + ada: 00 00 + adc: 65 72 + ade: 72 6e + ae0: 6f 2e 68 00 jal t3, 532486 + ae4: 03 00 00 73 lb zero, 1840(zero) + ae8: 74 64 + aea: 6c 69 + aec: 62 2e + aee: 68 00 + af0: 04 00 + af2: 00 75 + af4: 6e 69 + af6: 73 74 64 2e csrrci s0, 742, 8 + afa: 68 00 + afc: 03 00 00 74 lb zero, 1856(zero) + b00: 69 6d + b02: 65 2e + b04: 68 00 + b06: 04 00 + b08: 00 68 + b0a: 61 73 + b0c: 68 74 + b0e: 61 62 + b10: 2e 68 + b12: 00 05 + b14: 00 00 + b16: 72 69 + b18: 73 63 76 2d csrrsi t1, 727, 12 + b1c: 6f 70 74 73 j 294710 + b20: 2e 68 + b22: 00 06 + b24: 00 00 + b26: 69 6e + b28: 73 6e 2d 63 csrrsi t3, 1586, 26 + b2c: 6f 6e 73 74 jal t3, 225094 + b30: 61 6e + b32: 74 73 + b34: 2e 68 + b36: 00 07 + b38: 00 00 + b3a: 6c 69 + b3c: 62 67 + b3e: 63 63 32 2e bltu tp, gp, 742 + b42: 68 00 + b44: 01 00 + b46: 00 00 + b48: 05 01 + b4a: 00 05 + b4c: 02 e0 + b4e: 03 01 80 03 lb sp, 56(zero) + b52: 9a 0a + b54: 01 05 + b56: 03 03 01 09 lb t1, 144(sp) + b5a: 00 00 + b5c: 01 03 + b5e: 02 09 + b60: 00 00 + b62: 01 03 + b64: db 7d 09 00 + b68: 00 01 + b6a: 03 01 09 00 lb sp, 0(s2) + b6e: 00 01 + b70: 03 01 09 00 lb sp, 0(s2) + b74: 00 01 + b76: 03 01 09 00 lb sp, 0(s2) + b7a: 00 01 + b7c: 03 01 09 00 lb sp, 0(s2) + b80: 00 01 + b82: 03 01 09 00 lb sp, 0(s2) + b86: 00 01 + b88: 03 02 09 00 lb tp, 0(s2) + b8c: 00 01 + b8e: 05 06 + b90: 06 03 + b92: 00 09 + b94: 00 00 + b96: 01 05 + b98: 03 06 03 01 lb a2, 16(t1) + b9c: 09 04 + b9e: 00 01 + ba0: 05 06 + ba2: 06 03 + ba4: 00 09 + ba6: 00 00 + ba8: 01 05 + baa: 03 06 03 01 lb a2, 16(t1) + bae: 09 04 + bb0: 00 01 + bb2: 05 06 + bb4: 06 03 + bb6: 00 09 + bb8: 00 00 + bba: 01 05 + bbc: 03 06 03 01 lb a2, 16(t1) + bc0: 09 04 + bc2: 00 01 + bc4: 05 06 + bc6: 06 03 + bc8: 00 09 + bca: 00 00 + bcc: 01 05 + bce: 03 06 03 25 lb a2, 592(t1) + bd2: 09 04 + bd4: 00 01 + bd6: 05 06 + bd8: 06 03 + bda: 00 09 + bdc: 00 00 + bde: 01 05 + be0: 07 06 03 02 + be4: 09 04 + be6: 00 01 + be8: 05 0a + bea: 06 03 + bec: 00 09 + bee: 08 00 + bf0: 01 05 + bf2: 04 06 + bf4: 03 04 09 04 lb s0, 64(s2) + bf8: 00 01 + bfa: 03 00 09 00 lb zero, 0(s2) + bfe: 00 01 + c00: 03 00 09 00 lb zero, 0(s2) + c04: 00 01 + c06: 03 00 09 00 lb zero, 0(s2) + c0a: 00 01 + c0c: 03 00 09 00 lb zero, 0(s2) + c10: 00 01 + c12: 03 00 09 14 lb zero, 320(s2) + c16: 00 01 + c18: 03 00 09 18 lb zero, 384(s2) + c1c: 00 01 + c1e: 03 02 09 00 lb tp, 0(s2) + c22: 00 01 + c24: 05 07 + c26: 06 03 + c28: 00 09 + c2a: 00 00 + c2c: 01 05 + c2e: 08 06 + c30: 03 05 09 04 lb a0, 64(s2) + c34: 00 01 + c36: 05 11 + c38: 06 03 + c3a: 01 09 + c3c: 00 00 + c3e: 01 05 + c40: 1e 03 + c42: 00 09 + c44: 04 00 + c46: 01 05 + c48: 0b 03 7f 09 + c4c: 04 00 + c4e: 01 05 + c50: 08 06 + c52: 03 01 09 04 lb sp, 64(s2) + c56: 00 01 + c58: 05 0b + c5a: 06 03 + c5c: 00 09 + c5e: 00 00 + c60: 01 05 + c62: 08 06 + c64: 03 01 09 04 lb sp, 64(s2) + c68: 00 01 + c6a: 05 0b + c6c: 06 03 + c6e: 00 09 + c70: 00 00 + c72: 01 05 + c74: 04 06 + c76: 03 03 09 04 lb t1, 64(s2) + c7a: 00 01 + c7c: 03 00 09 00 lb zero, 0(s2) + c80: 00 01 + c82: 03 00 09 00 lb zero, 0(s2) + c86: 00 01 + c88: 03 00 09 00 lb zero, 0(s2) + c8c: 00 01 + c8e: 03 00 09 04 lb zero, 64(s2) + c92: 00 01 + c94: 03 00 09 0c lb zero, 192(s2) + c98: 00 01 + c9a: 03 00 09 00 lb zero, 0(s2) + c9e: 00 01 + ca0: 03 00 09 08 lb zero, 128(s2) + ca4: 00 01 + ca6: 03 00 09 0c lb zero, 192(s2) + caa: 00 01 + cac: 03 00 09 00 lb zero, 0(s2) + cb0: 00 01 + cb2: 03 00 09 04 lb zero, 64(s2) + cb6: 00 01 + cb8: 03 00 09 04 lb zero, 64(s2) + cbc: 00 01 + cbe: 03 00 09 04 lb zero, 64(s2) + cc2: 00 01 + cc4: 03 00 09 04 lb zero, 64(s2) + cc8: 00 01 + cca: 03 00 09 04 lb zero, 64(s2) + cce: 00 01 + cd0: 03 00 09 04 lb zero, 64(s2) + cd4: 00 01 + cd6: 03 00 09 04 lb zero, 64(s2) + cda: 00 01 + cdc: 03 00 09 0c lb zero, 192(s2) + ce0: 00 01 + ce2: 03 00 09 04 lb zero, 64(s2) + ce6: 00 01 + ce8: 03 00 09 08 lb zero, 128(s2) + cec: 00 01 + cee: 03 00 09 04 lb zero, 64(s2) + cf2: 00 01 + cf4: 03 00 09 04 lb zero, 64(s2) + cf8: 00 01 + cfa: 03 00 09 04 lb zero, 64(s2) + cfe: 00 01 + d00: 03 00 09 04 lb zero, 64(s2) + d04: 00 01 + d06: 03 00 09 04 lb zero, 64(s2) + d0a: 00 01 + d0c: 03 00 09 04 lb zero, 64(s2) + d10: 00 01 + d12: 03 00 09 00 lb zero, 0(s2) + d16: 00 01 + d18: 03 00 09 00 lb zero, 0(s2) + d1c: 00 01 + d1e: 03 01 09 00 lb sp, 0(s2) + d22: 00 01 + d24: 03 29 09 00 lw s2, 0(s2) + d28: 00 01 + d2a: 05 07 + d2c: 03 05 09 00 lb a0, 0(s2) + d30: 00 01 + d32: 05 04 + d34: 03 02 09 00 lb tp, 0(s2) + d38: 00 01 + d3a: 05 12 + d3c: 06 03 + d3e: 00 09 + d40: 00 00 + d42: 01 05 + d44: 04 06 + d46: 03 01 09 04 lb sp, 64(s2) + d4a: 00 01 + d4c: 03 01 09 00 lb sp, 0(s2) + d50: 00 01 + d52: 05 0c + d54: 06 03 + d56: 00 09 + d58: 00 00 + d5a: 01 05 + d5c: 03 06 03 da lb a2, -608(t1) + d60: 00 09 + d62: 04 00 + d64: 01 03 + d66: 01 09 + d68: 00 00 + d6a: 01 03 + d6c: d8 00 + d6e: 09 00 + d70: 00 01 + d72: 05 01 + d74: 06 03 + d76: 01 09 + d78: 00 00 + d7a: 01 05 + d7c: 04 03 + d7e: 8d 7e + d80: 09 04 + d82: 00 01 + d84: 06 03 + d86: 15 09 + d88: 14 00 + d8a: 01 05 + d8c: 07 06 03 00 + d90: 09 00 + d92: 00 01 + d94: 05 06 + d96: 06 03 + d98: 01 09 + d9a: 04 00 + d9c: 01 05 + d9e: 09 06 + da0: 03 00 09 00 lb zero, 0(s2) + da4: 00 01 + da6: 05 04 + da8: 06 03 + daa: 02 09 + dac: 08 00 + dae: 01 03 + db0: 00 09 + db2: 00 00 + db4: 01 03 + db6: 00 09 + db8: 00 00 + dba: 01 03 + dbc: 00 09 + dbe: 00 00 + dc0: 01 03 + dc2: 00 09 + dc4: 00 00 + dc6: 01 03 + dc8: 00 09 + dca: 14 00 + dcc: 01 03 + dce: 00 09 + dd0: 18 00 + dd2: 01 03 + dd4: 02 09 + dd6: 00 00 + dd8: 01 05 + dda: 07 06 03 00 + dde: 09 00 + de0: 00 01 + de2: 05 08 + de4: 06 03 + de6: 09 09 + de8: 04 00 + dea: 01 05 + dec: 0b 06 03 00 + df0: 09 00 + df2: 00 01 + df4: 05 08 + df6: 06 03 + df8: 01 09 + dfa: 04 00 + dfc: 01 03 + dfe: 0d 09 + e00: 00 00 + e02: 01 05 + e04: 04 03 + e06: 05 09 + e08: 00 00 + e0a: 01 03 + e0c: 00 09 + e0e: 00 00 + e10: 01 03 + e12: 00 09 + e14: 00 00 + e16: 01 03 + e18: 00 09 + e1a: 00 00 + e1c: 01 03 + e1e: 00 09 + e20: 04 00 + e22: 01 03 + e24: 00 09 + e26: 08 00 + e28: 01 03 + e2a: 00 09 + e2c: 08 00 + e2e: 01 03 + e30: 00 09 + e32: 04 00 + e34: 01 03 + e36: 00 09 + e38: 0c 00 + e3a: 01 03 + e3c: 00 09 + e3e: 00 00 + e40: 01 03 + e42: 00 09 + e44: 04 00 + e46: 01 03 + e48: 00 09 + e4a: 04 00 + e4c: 01 03 + e4e: 00 09 + e50: 04 00 + e52: 01 03 + e54: 00 09 + e56: 04 00 + e58: 01 03 + e5a: 00 09 + e5c: 04 00 + e5e: 01 03 + e60: 00 09 + e62: 04 00 + e64: 01 03 + e66: 00 09 + e68: 04 00 + e6a: 01 03 + e6c: 00 09 + e6e: 0c 00 + e70: 01 03 + e72: 00 09 + e74: 04 00 + e76: 01 03 + e78: 00 09 + e7a: 08 00 + e7c: 01 03 + e7e: 00 09 + e80: 04 00 + e82: 01 03 + e84: 00 09 + e86: 04 00 + e88: 01 03 + e8a: 00 09 + e8c: 04 00 + e8e: 01 03 + e90: 00 09 + e92: 04 00 + e94: 01 03 + e96: 00 09 + e98: 04 00 + e9a: 01 03 + e9c: 00 09 + e9e: 04 00 + ea0: 01 03 + ea2: 00 09 + ea4: 00 00 + ea6: 01 06 + ea8: 03 62 09 04 + eac: 00 01 + eae: 05 08 + eb0: 06 03 + eb2: 12 09 + eb4: 14 00 + eb6: 01 03 + eb8: 02 09 + eba: 00 00 + ebc: 01 05 + ebe: 0b 06 03 00 + ec2: 09 00 + ec4: 00 01 + ec6: 05 08 + ec8: 06 03 + eca: 01 09 + ecc: 04 00 + ece: 01 05 + ed0: 0b 06 03 00 + ed4: 09 00 + ed6: 00 01 + ed8: 05 08 + eda: 06 03 + edc: 01 09 + ede: 04 00 + ee0: 01 05 + ee2: 0b 06 03 01 + ee6: 09 00 + ee8: 00 01 + eea: 05 1e + eec: 03 7f 09 04 + ef0: 00 01 + ef2: 05 08 + ef4: 03 03 09 04 lb t1, 64(s2) + ef8: 00 01 + efa: 05 11 + efc: 03 7d 09 08 + f00: 00 01 + f02: 05 0b + f04: 03 00 09 04 lb zero, 64(s2) + f08: 00 01 + f0a: 05 08 + f0c: 06 03 + f0e: 01 09 + f10: 04 00 + f12: 01 03 + f14: 02 09 + f16: 00 00 + f18: 01 03 + f1a: 00 09 + f1c: 00 00 + f1e: 01 03 + f20: 00 09 + f22: 00 00 + f24: 01 03 + f26: 00 09 + f28: 00 00 + f2a: 01 03 + f2c: 00 09 + f2e: 00 00 + f30: 01 03 + f32: 00 09 + f34: 08 00 + f36: 01 03 + f38: 00 09 + f3a: 00 00 + f3c: 01 03 + f3e: 00 09 + f40: 08 00 + f42: 01 03 + f44: 00 09 + f46: 0c 00 + f48: 01 03 + f4a: 00 09 + f4c: 00 00 + f4e: 01 03 + f50: 00 09 + f52: 04 00 + f54: 01 03 + f56: 00 09 + f58: 04 00 + f5a: 01 03 + f5c: 00 09 + f5e: 04 00 + f60: 01 03 + f62: 00 09 + f64: 04 00 + f66: 01 03 + f68: 00 09 + f6a: 04 00 + f6c: 01 03 + f6e: 00 09 + f70: 04 00 + f72: 01 03 + f74: 00 09 + f76: 04 00 + f78: 01 03 + f7a: 00 09 + f7c: 0c 00 + f7e: 01 03 + f80: 00 09 + f82: 08 00 + f84: 01 03 + f86: 00 09 + f88: 04 00 + f8a: 01 03 + f8c: 00 09 + f8e: 04 00 + f90: 01 03 + f92: 00 09 + f94: 04 00 + f96: 01 03 + f98: 00 09 + f9a: 04 00 + f9c: 01 03 + f9e: 00 09 + fa0: 04 00 + fa2: 01 03 + fa4: 00 09 + fa6: 04 00 + fa8: 01 03 + faa: 00 09 + fac: 04 00 + fae: 01 03 + fb0: 00 09 + fb2: 00 00 + fb4: 01 05 + fb6: 07 03 15 09 + fba: 04 00 + fbc: 01 05 + fbe: 0a 06 + fc0: 03 00 09 00 lb zero, 0(s2) + fc4: 00 01 + fc6: 05 04 + fc8: 06 03 + fca: 13 09 04 00 mv s2, s0 + fce: 01 03 + fd0: 00 09 + fd2: 00 00 + fd4: 01 03 + fd6: 00 09 + fd8: 00 00 + fda: 01 03 + fdc: 00 09 + fde: 00 00 + fe0: 01 03 + fe2: 00 09 + fe4: 00 00 + fe6: 01 03 + fe8: 00 09 + fea: 14 00 + fec: 01 03 + fee: 00 09 + ff0: 20 00 + ff2: 01 03 + ff4: 01 09 + ff6: 00 00 + ff8: 01 05 + ffa: 07 06 03 00 + ffe: 09 00 + 1000: 00 01 + 1002: 05 08 + 1004: 06 03 + 1006: 0a 09 + 1008: 04 00 + 100a: 01 05 + 100c: 0b 06 03 00 + 1010: 09 00 + 1012: 00 01 + 1014: 05 14 + 1016: 03 00 09 04 lb zero, 64(s2) + 101a: 00 01 + 101c: 05 05 + 101e: 06 03 + 1020: 02 09 + 1022: 04 00 + 1024: 01 03 + 1026: 01 09 + 1028: 00 00 + 102a: 01 03 + 102c: 00 09 + 102e: 00 00 + 1030: 01 03 + 1032: 00 09 + 1034: 00 00 + 1036: 01 03 + 1038: 00 09 + 103a: 04 00 + 103c: 01 03 + 103e: 00 09 + 1040: 0c 00 + 1042: 01 03 + 1044: 00 09 + 1046: 00 00 + 1048: 01 05 + 104a: 08 03 + 104c: 05 09 + 104e: 00 00 + 1050: 01 03 + 1052: 02 09 + 1054: 00 00 + 1056: 01 05 + 1058: 05 03 + 105a: 02 09 + 105c: 00 00 + 105e: 01 03 + 1060: 01 09 + 1062: 00 00 + 1064: 01 03 + 1066: 01 09 + 1068: 00 00 + 106a: 01 05 + 106c: 0d 06 + 106e: 03 00 09 00 lb zero, 0(s2) + 1072: 00 01 + 1074: 05 04 + 1076: 03 67 09 0c + 107a: 00 01 + 107c: 05 08 + 107e: 06 03 + 1080: 1e 09 + 1082: 14 00 + 1084: 01 03 + 1086: 03 09 00 00 lb s2, 0(zero) + 108a: 01 03 + 108c: 02 09 + 108e: 00 00 + 1090: 01 05 + 1092: 1e 06 + 1094: 03 00 09 00 lb zero, 0(s2) + 1098: 00 01 + 109a: 05 11 + 109c: 03 00 09 04 lb zero, 64(s2) + 10a0: 00 01 + 10a2: 05 0b + 10a4: 03 00 09 04 lb zero, 64(s2) + 10a8: 00 01 + 10aa: 05 08 + 10ac: 06 03 + 10ae: 01 09 + 10b0: 04 00 + 10b2: 01 05 + 10b4: 0b 06 03 01 + 10b8: 09 00 + 10ba: 00 01 + 10bc: 05 08 + 10be: 03 04 09 04 lb s0, 64(s2) + 10c2: 00 01 + 10c4: 05 11 + 10c6: 03 7d 09 08 + 10ca: 00 01 + 10cc: 05 1e + 10ce: 03 00 09 04 lb zero, 64(s2) + 10d2: 00 01 + 10d4: 05 0b + 10d6: 03 00 09 04 lb zero, 64(s2) + 10da: 00 01 + 10dc: 05 08 + 10de: 03 03 09 04 lb t1, 64(s2) + 10e2: 00 01 + 10e4: 05 0b + 10e6: 03 7b 09 0c + 10ea: 00 01 + 10ec: 05 08 + 10ee: 06 03 + 10f0: 01 09 + 10f2: 04 00 + 10f4: 01 03 + 10f6: 01 09 + 10f8: 00 00 + 10fa: 01 03 + 10fc: 01 09 + 10fe: 00 00 + 1100: 01 05 + 1102: 0b 06 03 00 + 1106: 09 00 + 1108: 00 01 + 110a: 05 08 + 110c: 06 03 + 110e: 02 09 + 1110: 04 00 + 1112: 01 03 + 1114: 00 09 + 1116: 00 00 + 1118: 01 03 + 111a: 00 09 + 111c: 00 00 + 111e: 01 03 + 1120: 00 09 + 1122: 00 00 + 1124: 01 03 + 1126: 00 09 + 1128: 00 00 + 112a: 01 03 + 112c: 00 09 + 112e: 00 00 + 1130: 01 03 + 1132: 00 09 + 1134: 00 00 + 1136: 01 03 + 1138: 00 09 + 113a: 04 00 + 113c: 01 03 + 113e: 00 09 + 1140: 0c 00 + 1142: 01 03 + 1144: 00 09 + 1146: 00 00 + 1148: 01 03 + 114a: 00 09 + 114c: 08 00 + 114e: 01 03 + 1150: 00 09 + 1152: 08 00 + 1154: 01 03 + 1156: 00 09 + 1158: 04 00 + 115a: 01 03 + 115c: 00 09 + 115e: 04 00 + 1160: 01 03 + 1162: 00 09 + 1164: 08 00 + 1166: 01 03 + 1168: 00 09 + 116a: 04 00 + 116c: 01 03 + 116e: 00 09 + 1170: 04 00 + 1172: 01 03 + 1174: 00 09 + 1176: 0c 00 + 1178: 01 03 + 117a: 00 09 + 117c: 0c 00 + 117e: 01 03 + 1180: 00 09 + 1182: 00 00 + 1184: 01 03 + 1186: 00 09 + 1188: 08 00 + 118a: 01 03 + 118c: 00 09 + 118e: 08 00 + 1190: 01 03 + 1192: 00 09 + 1194: 04 00 + 1196: 01 03 + 1198: 00 09 + 119a: 04 00 + 119c: 01 03 + 119e: 00 09 + 11a0: 08 00 + 11a2: 01 03 + 11a4: 00 09 + 11a6: 04 00 + 11a8: 01 06 + 11aa: 03 01 09 04 lb sp, 64(s2) + 11ae: 00 01 + 11b0: 03 7f 09 04 + 11b4: 00 01 + 11b6: 06 03 + 11b8: 00 09 + 11ba: 04 00 + 11bc: 01 03 + 11be: 00 09 + 11c0: 00 00 + 11c2: 01 03 + 11c4: 01 09 + 11c6: 00 00 + 11c8: 01 03 + 11ca: 00 09 + 11cc: 00 00 + 11ce: 01 03 + 11d0: 00 09 + 11d2: 00 00 + 11d4: 01 03 + 11d6: 00 09 + 11d8: 00 00 + 11da: 01 03 + 11dc: 00 09 + 11de: 08 00 + 11e0: 01 03 + 11e2: 00 09 + 11e4: 08 00 + 11e6: 01 03 + 11e8: 00 09 + 11ea: 04 00 + 11ec: 01 03 + 11ee: 00 09 + 11f0: 00 00 + 11f2: 01 03 + 11f4: 00 09 + 11f6: 04 00 + 11f8: 01 03 + 11fa: 00 09 + 11fc: 00 00 + 11fe: 01 03 + 1200: 00 09 + 1202: 04 00 + 1204: 01 03 + 1206: 00 09 + 1208: 08 00 + 120a: 01 03 + 120c: 00 09 + 120e: 04 00 + 1210: 01 03 + 1212: 00 09 + 1214: 08 00 + 1216: 01 03 + 1218: 00 09 + 121a: 04 00 + 121c: 01 03 + 121e: 00 09 + 1220: 04 00 + 1222: 01 03 + 1224: 00 09 + 1226: 1c 00 + 1228: 01 03 + 122a: 00 09 + 122c: 04 00 + 122e: 01 03 + 1230: 02 09 + 1232: 00 00 + 1234: 01 05 + 1236: 0b 06 03 00 + 123a: 09 00 + 123c: 00 01 + 123e: 05 14 + 1240: 03 00 09 04 lb zero, 64(s2) + 1244: 00 01 + 1246: 05 21 + 1248: 03 00 09 04 lb zero, 64(s2) + 124c: 00 01 + 124e: 05 05 + 1250: 06 03 + 1252: 02 09 + 1254: 04 00 + 1256: 01 03 + 1258: 01 09 + 125a: 00 00 + 125c: 01 03 + 125e: 00 09 + 1260: 00 00 + 1262: 01 03 + 1264: 00 09 + 1266: 00 00 + 1268: 01 03 + 126a: 00 09 + 126c: 04 00 + 126e: 01 03 + 1270: 00 09 + 1272: 0c 00 + 1274: 01 03 + 1276: 00 09 + 1278: 04 00 + 127a: 01 05 + 127c: 08 03 + 127e: 03 09 00 00 lb s2, 0(zero) + 1282: 01 03 + 1284: 03 09 00 00 lb s2, 0(zero) + 1288: 01 05 + 128a: 05 03 + 128c: 02 09 + 128e: 00 00 + 1290: 01 03 + 1292: 00 09 + 1294: 00 00 + 1296: 01 03 + 1298: 00 09 + 129a: 00 00 + 129c: 01 03 + 129e: 00 09 + 12a0: 04 00 + 12a2: 01 03 + 12a4: 00 09 + 12a6: 0c 00 + 12a8: 01 03 + 12aa: 00 09 + 12ac: 00 00 + 12ae: 01 03 + 12b0: 01 09 + 12b2: 00 00 + 12b4: 01 05 + 12b6: 14 06 + 12b8: 03 00 09 00 lb zero, 0(s2) + 12bc: 00 01 + 12be: 05 20 + 12c0: 03 00 09 04 lb zero, 64(s2) + 12c4: 00 01 + 12c6: 05 05 + 12c8: 06 03 + 12ca: 01 09 + 12cc: 04 00 + 12ce: 01 03 + 12d0: 01 09 + 12d2: 00 00 + 12d4: 01 05 + 12d6: 0d 06 + 12d8: 03 00 09 00 lb zero, 0(s2) + 12dc: 00 01 + 12de: 09 0c + 12e0: 00 00 + 12e2: 01 01 + 12e4: 49 12 + 12e6: 00 00 + 12e8: 03 00 93 00 lb zero, 9(t1) + 12ec: 00 00 + 12ee: 01 01 + 12f0: fb 0e 0d 00 + 12f4: 01 01 + 12f6: 01 01 + 12f8: 00 00 + 12fa: 00 01 + 12fc: 00 00 + 12fe: 01 2e + 1300: 2e 2f + 1302: 2e 2e + 1304: 2f 2e 2e 2f + 1308: 2e 2e + 130a: 2f 72 69 73 + 130e: 63 76 2d 67 bgeu s10, s2, 1644 + 1312: 63 63 2f 6c bltu t5, sp, 1734 + 1316: 69 62 + 1318: 67 63 63 2f + 131c: 73 6f 66 74 csrrsi t5, 1862, 12 + 1320: 2d 66 + 1322: 70 00 + 1324: 2e 2e + 1326: 2f 2e 2e 2f + 132a: 2e 2e + 132c: 2f 2e 2e 2f + 1330: 72 69 + 1332: 73 63 76 2d csrrsi t1, 727, 12 + 1336: 67 63 63 2f + 133a: 6c 69 + 133c: 62 67 + 133e: 63 63 2f 2e bltu t5, sp, 742 + 1342: 2e 2f + 1344: 69 6e + 1346: 63 6c 75 64 bltu a0, t2, 1624 + 134a: 65 00 + 134c: 00 64 + 134e: 69 76 + 1350: 64 66 + 1352: 33 2e 63 00 slt t3, t1, t1 + 1356: 01 00 + 1358: 00 73 + 135a: 6f 66 74 2d jal a2, 289494 + 135e: 66 70 + 1360: 2e 68 + 1362: 00 01 + 1364: 00 00 + 1366: 64 6f + 1368: 75 62 + 136a: 6c 65 + 136c: 2e 68 + 136e: 00 01 + 1370: 00 00 + 1372: 6c 6f + 1374: 6e 67 + 1376: 6c 6f + 1378: 6e 67 + 137a: 2e 68 + 137c: 00 02 + 137e: 00 00 + 1380: 00 05 + 1382: 01 00 + 1384: 05 02 + 1386: f0 07 + 1388: 01 80 + 138a: 03 23 01 05 lw t1, 80(sp) + 138e: 03 03 01 09 lb t1, 144(sp) + 1392: 00 00 + 1394: 01 03 + 1396: 00 09 + 1398: 00 00 + 139a: 01 05 + 139c: 0d 03 + 139e: 00 09 + 13a0: 00 00 + 13a2: 01 05 + 13a4: 03 03 01 09 lb t1, 144(sp) + 13a8: 00 00 + 13aa: 01 03 + 13ac: 00 09 + 13ae: 00 00 + 13b0: 01 03 + 13b2: 00 09 + 13b4: 00 00 + 13b6: 01 03 + 13b8: 00 09 + 13ba: 00 00 + 13bc: 01 03 + 13be: 01 09 + 13c0: 00 00 + 13c2: 01 03 + 13c4: 00 09 + 13c6: 00 00 + 13c8: 01 03 + 13ca: 00 09 + 13cc: 00 00 + 13ce: 01 03 + 13d0: 00 09 + 13d2: 00 00 + 13d4: 01 03 + 13d6: 01 09 + 13d8: 00 00 + 13da: 01 03 + 13dc: 00 09 + 13de: 00 00 + 13e0: 01 03 + 13e2: 00 09 + 13e4: 00 00 + 13e6: 01 03 + 13e8: 00 09 + 13ea: 00 00 + 13ec: 01 03 + 13ee: 01 09 + 13f0: 00 00 + 13f2: 01 03 + 13f4: 02 09 + 13f6: 00 00 + 13f8: 01 03 + 13fa: 00 09 + 13fc: 00 00 + 13fe: 01 05 + 1400: 01 06 + 1402: 03 79 09 00 + 1406: 00 01 + 1408: 03 00 09 30 lb zero, 768(s2) + 140c: 00 01 + 140e: 05 03 + 1410: 03 07 09 0c lb a4, 192(s2) + 1414: 00 01 + 1416: 06 03 + 1418: 00 09 + 141a: 04 00 + 141c: 01 03 + 141e: 01 09 + 1420: 00 00 + 1422: 01 03 + 1424: 00 09 + 1426: 00 00 + 1428: 01 03 + 142a: 00 09 + 142c: 00 00 + 142e: 01 03 + 1430: 00 09 + 1432: 00 00 + 1434: 01 03 + 1436: 00 09 + 1438: 00 00 + 143a: 01 03 + 143c: 00 09 + 143e: 00 00 + 1440: 01 03 + 1442: 00 09 + 1444: 10 00 + 1446: 01 03 + 1448: 00 09 + 144a: 00 00 + 144c: 01 03 + 144e: 00 09 + 1450: 04 00 + 1452: 01 03 + 1454: 00 09 + 1456: 00 00 + 1458: 01 03 + 145a: 00 09 + 145c: 00 00 + 145e: 01 00 + 1460: 02 04 + 1462: 01 03 + 1464: 00 09 + 1466: 10 00 + 1468: 01 00 + 146a: 02 04 + 146c: 01 03 + 146e: 00 09 + 1470: 00 00 + 1472: 01 00 + 1474: 02 04 + 1476: 01 03 + 1478: 00 09 + 147a: 00 00 + 147c: 01 00 + 147e: 02 04 + 1480: 01 03 + 1482: 00 09 + 1484: 00 00 + 1486: 01 00 + 1488: 02 04 + 148a: 01 03 + 148c: 00 09 + 148e: 14 00 + 1490: 01 00 + 1492: 02 04 + 1494: 01 03 + 1496: 00 09 + 1498: 04 00 + 149a: 01 00 + 149c: 02 04 + 149e: 01 03 + 14a0: 00 09 + 14a2: 00 00 + 14a4: 01 00 + 14a6: 02 04 + 14a8: 01 03 + 14aa: 00 09 + 14ac: 04 00 + 14ae: 01 00 + 14b0: 02 04 + 14b2: 01 03 + 14b4: 00 09 + 14b6: 00 00 + 14b8: 01 00 + 14ba: 02 04 + 14bc: 29 03 + 14be: 00 09 + 14c0: 00 00 + 14c2: 01 00 + 14c4: 02 04 + 14c6: 29 03 + 14c8: 00 09 + 14ca: 00 00 + 14cc: 01 06 + 14ce: 03 79 09 04 + 14d2: 00 01 + 14d4: 00 02 + 14d6: 04 02 + 14d8: 06 03 + 14da: 07 09 08 00 + 14de: 01 00 + 14e0: 02 04 + 14e2: 0d 03 + 14e4: 00 09 + 14e6: 08 00 + 14e8: 01 00 + 14ea: 02 04 + 14ec: 0d 03 + 14ee: 00 09 + 14f0: 00 00 + 14f2: 01 00 + 14f4: 02 04 + 14f6: 0d 03 + 14f8: 00 09 + 14fa: 00 00 + 14fc: 01 00 + 14fe: 02 04 + 1500: 0d 03 + 1502: 00 09 + 1504: 00 00 + 1506: 01 00 + 1508: 02 04 + 150a: 11 03 + 150c: 00 09 + 150e: 04 00 + 1510: 01 00 + 1512: 02 04 + 1514: 11 03 + 1516: 00 09 + 1518: 00 00 + 151a: 01 00 + 151c: 02 04 + 151e: 11 03 + 1520: 00 09 + 1522: 00 00 + 1524: 01 00 + 1526: 02 04 + 1528: 11 03 + 152a: 00 09 + 152c: 00 00 + 152e: 01 00 + 1530: 02 04 + 1532: 11 03 + 1534: 00 09 + 1536: 08 00 + 1538: 01 00 + 153a: 02 04 + 153c: 1f 03 00 09 + 1540: 00 00 + 1542: 01 00 + 1544: 02 04 + 1546: 1f 03 00 09 + 154a: 00 00 + 154c: 01 00 + 154e: 02 04 + 1550: 1f 03 00 09 + 1554: 04 00 + 1556: 01 00 + 1558: 02 04 + 155a: 20 03 + 155c: 00 09 + 155e: 08 00 + 1560: 01 00 + 1562: 02 04 + 1564: 20 03 + 1566: 00 09 + 1568: 08 00 + 156a: 01 00 + 156c: 02 04 + 156e: 20 03 + 1570: 00 09 + 1572: 10 00 + 1574: 01 00 + 1576: 02 04 + 1578: 20 03 + 157a: 00 09 + 157c: 04 00 + 157e: 01 00 + 1580: 02 04 + 1582: 29 03 + 1584: 00 09 + 1586: 00 00 + 1588: 01 00 + 158a: 02 04 + 158c: 18 03 + 158e: 00 09 + 1590: 0c 00 + 1592: 01 00 + 1594: 02 04 + 1596: 18 03 + 1598: 00 09 + 159a: 00 00 + 159c: 01 00 + 159e: 02 04 + 15a0: 18 03 + 15a2: 00 09 + 15a4: 00 00 + 15a6: 01 00 + 15a8: 02 04 + 15aa: 18 03 + 15ac: 00 09 + 15ae: 00 00 + 15b0: 01 00 + 15b2: 02 04 + 15b4: 18 03 + 15b6: 00 09 + 15b8: 04 00 + 15ba: 01 00 + 15bc: 02 04 + 15be: 18 03 + 15c0: 00 09 + 15c2: 00 00 + 15c4: 01 00 + 15c6: 02 04 + 15c8: 21 03 + 15ca: 00 09 + 15cc: 08 00 + 15ce: 01 00 + 15d0: 02 04 + 15d2: 21 03 + 15d4: 00 09 + 15d6: 08 00 + 15d8: 01 00 + 15da: 02 04 + 15dc: 03 03 00 09 lb t1, 144(zero) + 15e0: 08 00 + 15e2: 01 00 + 15e4: 02 04 + 15e6: 2c 06 + 15e8: 03 00 09 08 lb zero, 128(s2) + 15ec: 00 01 + 15ee: 00 02 + 15f0: 04 2c + 15f2: 06 03 + 15f4: 00 09 + 15f6: 08 00 + 15f8: 01 00 + 15fa: 02 04 + 15fc: 2c 03 + 15fe: 00 09 + 1600: 00 00 + 1602: 01 00 + 1604: 02 04 + 1606: 08 03 + 1608: 00 09 + 160a: 10 00 + 160c: 01 00 + 160e: 02 04 + 1610: 08 03 + 1612: 00 09 + 1614: 00 00 + 1616: 01 00 + 1618: 02 04 + 161a: 08 03 + 161c: 01 09 + 161e: 00 00 + 1620: 01 00 + 1622: 02 04 + 1624: 08 03 + 1626: 00 09 + 1628: 00 00 + 162a: 01 00 + 162c: 02 04 + 162e: 08 03 + 1630: 00 09 + 1632: 00 00 + 1634: 01 00 + 1636: 02 04 + 1638: 08 03 + 163a: 00 09 + 163c: 00 00 + 163e: 01 00 + 1640: 02 04 + 1642: 08 03 + 1644: 00 09 + 1646: 00 00 + 1648: 01 00 + 164a: 02 04 + 164c: 08 03 + 164e: 00 09 + 1650: 10 00 + 1652: 01 00 + 1654: 02 04 + 1656: 08 03 + 1658: 00 09 + 165a: 04 00 + 165c: 01 00 + 165e: 02 04 + 1660: 08 03 + 1662: 00 09 + 1664: 04 00 + 1666: 01 00 + 1668: 02 04 + 166a: 08 03 + 166c: 00 09 + 166e: 04 00 + 1670: 01 00 + 1672: 02 04 + 1674: 08 03 + 1676: 00 09 + 1678: 00 00 + 167a: 01 00 + 167c: 02 04 + 167e: 08 03 + 1680: 00 09 + 1682: 00 00 + 1684: 01 06 + 1686: 03 00 09 04 lb zero, 64(s2) + 168a: 00 01 + 168c: 00 02 + 168e: 04 01 + 1690: 06 03 + 1692: 00 09 + 1694: 08 00 + 1696: 01 00 + 1698: 02 04 + 169a: 01 03 + 169c: 00 09 + 169e: 00 00 + 16a0: 01 00 + 16a2: 02 04 + 16a4: 01 03 + 16a6: 00 09 + 16a8: 00 00 + 16aa: 01 00 + 16ac: 02 04 + 16ae: 01 03 + 16b0: 00 09 + 16b2: 00 00 + 16b4: 01 00 + 16b6: 02 04 + 16b8: 01 03 + 16ba: 00 09 + 16bc: 14 00 + 16be: 01 00 + 16c0: 02 04 + 16c2: 01 03 + 16c4: 00 09 + 16c6: 04 00 + 16c8: 01 00 + 16ca: 02 04 + 16cc: 01 03 + 16ce: 00 09 + 16d0: 00 00 + 16d2: 01 00 + 16d4: 02 04 + 16d6: 01 03 + 16d8: 00 09 + 16da: 04 00 + 16dc: 01 00 + 16de: 02 04 + 16e0: 01 03 + 16e2: 00 09 + 16e4: 00 00 + 16e6: 01 00 + 16e8: 02 04 + 16ea: 29 03 + 16ec: 00 09 + 16ee: 00 00 + 16f0: 01 00 + 16f2: 02 04 + 16f4: 29 03 + 16f6: 00 09 + 16f8: 00 00 + 16fa: 01 00 + 16fc: 02 04 + 16fe: 08 03 + 1700: 00 09 + 1702: 04 00 + 1704: 01 00 + 1706: 02 04 + 1708: 08 03 + 170a: 00 09 + 170c: 00 00 + 170e: 01 00 + 1710: 02 04 + 1712: 08 03 + 1714: 01 09 + 1716: 00 00 + 1718: 01 00 + 171a: 02 04 + 171c: 08 03 + 171e: 00 09 + 1720: 00 00 + 1722: 01 00 + 1724: 02 04 + 1726: 08 03 + 1728: 00 09 + 172a: 18 00 + 172c: 01 00 + 172e: 02 04 + 1730: 08 03 + 1732: 00 09 + 1734: 00 00 + 1736: 01 06 + 1738: 03 7e 09 28 + 173c: 00 01 + 173e: 00 02 + 1740: 04 02 + 1742: 06 03 + 1744: 01 09 + 1746: 1c 00 + 1748: 01 00 + 174a: 02 04 + 174c: 0d 03 + 174e: 00 09 + 1750: 08 00 + 1752: 01 00 + 1754: 02 04 + 1756: 0d 03 + 1758: 00 09 + 175a: 00 00 + 175c: 01 00 + 175e: 02 04 + 1760: 0d 03 + 1762: 00 09 + 1764: 00 00 + 1766: 01 00 + 1768: 02 04 + 176a: 0d 03 + 176c: 00 09 + 176e: 00 00 + 1770: 01 00 + 1772: 02 04 + 1774: 11 03 + 1776: 00 09 + 1778: 04 00 + 177a: 01 00 + 177c: 02 04 + 177e: 11 03 + 1780: 00 09 + 1782: 00 00 + 1784: 01 00 + 1786: 02 04 + 1788: 11 03 + 178a: 00 09 + 178c: 00 00 + 178e: 01 00 + 1790: 02 04 + 1792: 11 03 + 1794: 00 09 + 1796: 00 00 + 1798: 01 00 + 179a: 02 04 + 179c: 11 03 + 179e: 00 09 + 17a0: 0c 00 + 17a2: 01 00 + 17a4: 02 04 + 17a6: 1f 03 00 09 + 17aa: 00 00 + 17ac: 01 00 + 17ae: 02 04 + 17b0: 1f 03 00 09 + 17b4: 00 00 + 17b6: 01 00 + 17b8: 02 04 + 17ba: 1f 03 00 09 + 17be: 04 00 + 17c0: 01 00 + 17c2: 02 04 + 17c4: 20 03 + 17c6: 00 09 + 17c8: 08 00 + 17ca: 01 00 + 17cc: 02 04 + 17ce: 20 03 + 17d0: 00 09 + 17d2: 08 00 + 17d4: 01 00 + 17d6: 02 04 + 17d8: 20 03 + 17da: 00 09 + 17dc: 10 00 + 17de: 01 00 + 17e0: 02 04 + 17e2: 20 03 + 17e4: 00 09 + 17e6: 04 00 + 17e8: 01 00 + 17ea: 02 04 + 17ec: 29 03 + 17ee: 00 09 + 17f0: 00 00 + 17f2: 01 00 + 17f4: 02 04 + 17f6: 18 03 + 17f8: 00 09 + 17fa: 0c 00 + 17fc: 01 00 + 17fe: 02 04 + 1800: 18 03 + 1802: 00 09 + 1804: 00 00 + 1806: 01 00 + 1808: 02 04 + 180a: 18 03 + 180c: 00 09 + 180e: 00 00 + 1810: 01 00 + 1812: 02 04 + 1814: 18 03 + 1816: 00 09 + 1818: 00 00 + 181a: 01 00 + 181c: 02 04 + 181e: 18 03 + 1820: 00 09 + 1822: 08 00 + 1824: 01 00 + 1826: 02 04 + 1828: 18 03 + 182a: 00 09 + 182c: 00 00 + 182e: 01 00 + 1830: 02 04 + 1832: 21 03 + 1834: 00 09 + 1836: 08 00 + 1838: 01 00 + 183a: 02 04 + 183c: 21 03 + 183e: 00 09 + 1840: 08 00 + 1842: 01 00 + 1844: 02 04 + 1846: 03 03 00 09 lb t1, 144(zero) + 184a: 08 00 + 184c: 01 00 + 184e: 02 04 + 1850: 2c 03 + 1852: 00 09 + 1854: 08 00 + 1856: 01 00 + 1858: 02 04 + 185a: 2c 03 + 185c: 00 09 + 185e: 00 00 + 1860: 01 06 + 1862: 03 00 09 0c lb zero, 192(s2) + 1866: 00 01 + 1868: 00 02 + 186a: 04 02 + 186c: 06 03 + 186e: 01 09 + 1870: 3c 00 + 1872: 01 00 + 1874: 02 04 + 1876: 02 03 + 1878: 00 09 + 187a: 00 00 + 187c: 01 00 + 187e: 02 04 + 1880: 02 03 + 1882: 00 09 + 1884: 00 00 + 1886: 01 00 + 1888: 02 04 + 188a: 02 03 + 188c: 00 09 + 188e: 00 00 + 1890: 01 00 + 1892: 02 04 + 1894: 02 03 + 1896: 00 09 + 1898: 00 00 + 189a: 01 00 + 189c: 02 04 + 189e: 02 03 + 18a0: 00 09 + 18a2: 00 00 + 18a4: 01 00 + 18a6: 02 04 + 18a8: 02 03 + 18aa: 00 09 + 18ac: 00 00 + 18ae: 01 00 + 18b0: 02 04 + 18b2: 02 03 + 18b4: 00 09 + 18b6: 00 00 + 18b8: 01 00 + 18ba: 02 04 + 18bc: 02 03 + 18be: 00 09 + 18c0: 00 00 + 18c2: 01 00 + 18c4: 02 04 + 18c6: 02 03 + 18c8: 00 09 + 18ca: 00 00 + 18cc: 01 00 + 18ce: 02 04 + 18d0: 0b 06 03 00 + 18d4: 09 04 + 18d6: 00 01 + 18d8: 00 02 + 18da: 04 0c + 18dc: 03 00 09 04 lb zero, 64(s2) + 18e0: 00 01 + 18e2: 00 02 + 18e4: 04 0e + 18e6: 06 03 + 18e8: 00 09 + 18ea: 04 00 + 18ec: 01 00 + 18ee: 02 04 + 18f0: 0e 03 + 18f2: 00 09 + 18f4: 00 00 + 18f6: 01 00 + 18f8: 02 04 + 18fa: 0e 03 + 18fc: 00 09 + 18fe: 08 00 + 1900: 01 00 + 1902: 02 04 + 1904: 13 03 00 09 addi t1, zero, 144 + 1908: 0c 00 + 190a: 01 00 + 190c: 02 04 + 190e: 13 03 00 09 addi t1, zero, 144 + 1912: 00 00 + 1914: 01 00 + 1916: 02 04 + 1918: 13 03 00 09 addi t1, zero, 144 + 191c: 00 00 + 191e: 01 00 + 1920: 02 04 + 1922: 13 03 00 09 addi t1, zero, 144 + 1926: 0c 00 + 1928: 01 00 + 192a: 02 04 + 192c: 13 03 00 09 addi t1, zero, 144 + 1930: 14 00 + 1932: 01 00 + 1934: 02 04 + 1936: 13 03 00 09 addi t1, zero, 144 + 193a: 00 00 + 193c: 01 00 + 193e: 02 04 + 1940: 13 03 00 09 addi t1, zero, 144 + 1944: 00 00 + 1946: 01 00 + 1948: 02 04 + 194a: 13 03 00 09 addi t1, zero, 144 + 194e: 00 00 + 1950: 01 00 + 1952: 02 04 + 1954: 13 03 00 09 addi t1, zero, 144 + 1958: 00 00 + 195a: 01 00 + 195c: 02 04 + 195e: 13 03 00 09 addi t1, zero, 144 + 1962: 00 00 + 1964: 01 00 + 1966: 02 04 + 1968: 13 03 00 09 addi t1, zero, 144 + 196c: 00 00 + 196e: 01 00 + 1970: 02 04 + 1972: 13 03 00 09 addi t1, zero, 144 + 1976: 00 00 + 1978: 01 00 + 197a: 02 04 + 197c: 13 03 00 09 addi t1, zero, 144 + 1980: 00 00 + 1982: 01 00 + 1984: 02 04 + 1986: 13 03 00 09 addi t1, zero, 144 + 198a: 10 00 + 198c: 01 00 + 198e: 02 04 + 1990: 13 03 00 09 addi t1, zero, 144 + 1994: 08 00 + 1996: 01 00 + 1998: 02 04 + 199a: 16 03 + 199c: 00 09 + 199e: 04 00 + 19a0: 01 00 + 19a2: 02 04 + 19a4: 16 03 + 19a6: 00 09 + 19a8: 08 00 + 19aa: 01 00 + 19ac: 02 04 + 19ae: 18 03 + 19b0: 00 09 + 19b2: 04 00 + 19b4: 01 00 + 19b6: 02 04 + 19b8: 1a 03 + 19ba: 00 09 + 19bc: 04 00 + 19be: 01 00 + 19c0: 02 04 + 19c2: 1c 03 + 19c4: 00 09 + 19c6: 08 00 + 19c8: 01 00 + 19ca: 02 04 + 19cc: 1c 03 + 19ce: 00 09 + 19d0: 04 00 + 19d2: 01 00 + 19d4: 02 04 + 19d6: 1c 03 + 19d8: 00 09 + 19da: 00 00 + 19dc: 01 00 + 19de: 02 04 + 19e0: 1c 03 + 19e2: 00 09 + 19e4: 04 00 + 19e6: 01 00 + 19e8: 02 04 + 19ea: 1c 03 + 19ec: 00 09 + 19ee: 14 00 + 19f0: 01 00 + 19f2: 02 04 + 19f4: 1c 03 + 19f6: 00 09 + 19f8: 08 00 + 19fa: 01 00 + 19fc: 02 04 + 19fe: 1d 03 + 1a00: 00 09 + 1a02: 04 00 + 1a04: 01 00 + 1a06: 02 04 + 1a08: 1d 03 + 1a0a: 00 09 + 1a0c: 08 00 + 1a0e: 01 00 + 1a10: 02 04 + 1a12: 1f 03 00 09 + 1a16: 04 00 + 1a18: 01 00 + 1a1a: 02 04 + 1a1c: 21 03 + 1a1e: 00 09 + 1a20: 04 00 + 1a22: 01 00 + 1a24: 02 04 + 1a26: 23 03 00 09 sb a6, 134(zero) + 1a2a: 08 00 + 1a2c: 01 00 + 1a2e: 02 04 + 1a30: 23 03 00 09 sb a6, 134(zero) + 1a34: 04 00 + 1a36: 01 00 + 1a38: 02 04 + 1a3a: 23 03 00 09 sb a6, 134(zero) + 1a3e: 0c 00 + 1a40: 01 00 + 1a42: 02 04 + 1a44: 23 03 00 09 sb a6, 134(zero) + 1a48: 00 00 + 1a4a: 01 00 + 1a4c: 02 04 + 1a4e: 23 03 00 09 sb a6, 134(zero) + 1a52: 00 00 + 1a54: 01 00 + 1a56: 02 04 + 1a58: 23 03 00 09 sb a6, 134(zero) + 1a5c: 00 00 + 1a5e: 01 00 + 1a60: 02 04 + 1a62: 23 03 00 09 sb a6, 134(zero) + 1a66: 00 00 + 1a68: 01 00 + 1a6a: 02 04 + 1a6c: 23 03 00 09 sb a6, 134(zero) + 1a70: 00 00 + 1a72: 01 00 + 1a74: 02 04 + 1a76: 23 03 00 09 sb a6, 134(zero) + 1a7a: 00 00 + 1a7c: 01 00 + 1a7e: 02 04 + 1a80: 23 03 00 09 sb a6, 134(zero) + 1a84: 0c 00 + 1a86: 01 00 + 1a88: 02 04 + 1a8a: 23 03 00 09 sb a6, 134(zero) + 1a8e: 00 00 + 1a90: 01 00 + 1a92: 02 04 + 1a94: 23 03 00 09 sb a6, 134(zero) + 1a98: 04 00 + 1a9a: 01 00 + 1a9c: 02 04 + 1a9e: 23 03 00 09 sb a6, 134(zero) + 1aa2: 08 00 + 1aa4: 01 00 + 1aa6: 02 04 + 1aa8: 23 03 00 09 sb a6, 134(zero) + 1aac: 00 00 + 1aae: 01 00 + 1ab0: 02 04 + 1ab2: 23 03 00 09 sb a6, 134(zero) + 1ab6: 04 00 + 1ab8: 01 00 + 1aba: 02 04 + 1abc: 23 03 00 09 sb a6, 134(zero) + 1ac0: 14 00 + 1ac2: 01 00 + 1ac4: 02 04 + 1ac6: 23 03 00 09 sb a6, 134(zero) + 1aca: 00 00 + 1acc: 01 00 + 1ace: 02 04 + 1ad0: 23 03 00 09 sb a6, 134(zero) + 1ad4: 00 00 + 1ad6: 01 00 + 1ad8: 02 04 + 1ada: 24 03 + 1adc: 00 09 + 1ade: 04 00 + 1ae0: 01 00 + 1ae2: 02 04 + 1ae4: 26 03 + 1ae6: 00 09 + 1ae8: 04 00 + 1aea: 01 00 + 1aec: 02 04 + 1aee: 26 03 + 1af0: 00 09 + 1af2: 10 00 + 1af4: 01 00 + 1af6: 02 04 + 1af8: 26 03 + 1afa: 00 09 + 1afc: 10 00 + 1afe: 01 00 + 1b00: 02 04 + 1b02: 26 03 + 1b04: 00 09 + 1b06: 00 00 + 1b08: 01 00 + 1b0a: 02 04 + 1b0c: 26 03 + 1b0e: 00 09 + 1b10: 00 00 + 1b12: 01 00 + 1b14: 02 04 + 1b16: 28 06 + 1b18: 03 00 09 04 lb zero, 64(s2) + 1b1c: 00 01 + 1b1e: 00 02 + 1b20: 04 29 + 1b22: 03 00 09 08 lb zero, 128(s2) + 1b26: 00 01 + 1b28: 00 02 + 1b2a: 04 2b + 1b2c: 06 03 + 1b2e: 00 09 + 1b30: 04 00 + 1b32: 01 00 + 1b34: 02 04 + 1b36: 2b 03 00 09 + 1b3a: 14 00 + 1b3c: 01 00 + 1b3e: 02 04 + 1b40: 2b 03 00 09 + 1b44: 00 00 + 1b46: 01 00 + 1b48: 02 04 + 1b4a: 2b 03 00 09 + 1b4e: 00 00 + 1b50: 01 00 + 1b52: 02 04 + 1b54: 2b 03 00 09 + 1b58: 00 00 + 1b5a: 01 00 + 1b5c: 02 04 + 1b5e: 2b 03 00 09 + 1b62: 00 00 + 1b64: 01 00 + 1b66: 02 04 + 1b68: 2b 03 00 09 + 1b6c: 00 00 + 1b6e: 01 00 + 1b70: 02 04 + 1b72: 2b 03 00 09 + 1b76: 00 00 + 1b78: 01 00 + 1b7a: 02 04 + 1b7c: 2e 06 + 1b7e: 03 00 09 04 lb zero, 64(s2) + 1b82: 00 01 + 1b84: 00 02 + 1b86: 04 2f + 1b88: 03 00 09 04 lb zero, 64(s2) + 1b8c: 00 01 + 1b8e: 00 02 + 1b90: 04 31 + 1b92: 03 00 09 04 lb zero, 64(s2) + 1b96: 00 01 + 1b98: 00 02 + 1b9a: 04 34 + 1b9c: 03 00 09 04 lb zero, 64(s2) + 1ba0: 00 01 + 1ba2: 00 02 + 1ba4: 04 35 + 1ba6: 03 00 09 04 lb zero, 64(s2) + 1baa: 00 01 + 1bac: 00 02 + 1bae: 04 37 + 1bb0: 06 03 + 1bb2: 00 09 + 1bb4: 04 00 + 1bb6: 01 00 + 1bb8: 02 04 + 1bba: 37 03 00 09 lui t1, 36864 + 1bbe: 10 00 + 1bc0: 01 00 + 1bc2: 02 04 + 1bc4: 37 03 00 09 lui t1, 36864 + 1bc8: 00 00 + 1bca: 01 00 + 1bcc: 02 04 + 1bce: 37 03 00 09 lui t1, 36864 + 1bd2: 00 00 + 1bd4: 01 00 + 1bd6: 02 04 + 1bd8: 37 03 00 09 lui t1, 36864 + 1bdc: 00 00 + 1bde: 01 00 + 1be0: 02 04 + 1be2: 37 03 00 09 lui t1, 36864 + 1be6: 04 00 + 1be8: 01 00 + 1bea: 02 04 + 1bec: 39 03 + 1bee: 00 09 + 1bf0: 00 00 + 1bf2: 01 00 + 1bf4: 02 04 + 1bf6: 39 03 + 1bf8: 00 09 + 1bfa: 00 00 + 1bfc: 01 00 + 1bfe: 02 04 + 1c00: 39 03 + 1c02: 00 09 + 1c04: 00 00 + 1c06: 01 00 + 1c08: 02 04 + 1c0a: 39 03 + 1c0c: 00 09 + 1c0e: 00 00 + 1c10: 01 00 + 1c12: 02 04 + 1c14: 39 03 + 1c16: 00 09 + 1c18: 04 00 + 1c1a: 01 00 + 1c1c: 02 04 + 1c1e: 39 03 + 1c20: 00 09 + 1c22: 0c 00 + 1c24: 01 00 + 1c26: 02 04 + 1c28: 39 03 + 1c2a: 00 09 + 1c2c: 00 00 + 1c2e: 01 00 + 1c30: 02 04 + 1c32: 39 03 + 1c34: 00 09 + 1c36: 00 00 + 1c38: 01 00 + 1c3a: 02 04 + 1c3c: 3b 03 00 09 + 1c40: 08 00 + 1c42: 01 00 + 1c44: 02 04 + 1c46: 3b 03 00 09 + 1c4a: 00 00 + 1c4c: 01 00 + 1c4e: 02 04 + 1c50: 3b 03 00 09 + 1c54: 00 00 + 1c56: 01 00 + 1c58: 02 04 + 1c5a: 3b 03 00 09 + 1c5e: 00 00 + 1c60: 01 00 + 1c62: 02 04 + 1c64: 3b 03 00 09 + 1c68: 00 00 + 1c6a: 01 00 + 1c6c: 02 04 + 1c6e: 3b 03 00 09 + 1c72: 00 00 + 1c74: 01 00 + 1c76: 02 04 + 1c78: 3b 03 00 09 + 1c7c: 00 00 + 1c7e: 01 00 + 1c80: 02 04 + 1c82: 3b 03 00 09 + 1c86: 04 00 + 1c88: 01 00 + 1c8a: 02 04 + 1c8c: 3b 03 00 09 + 1c90: 10 00 + 1c92: 01 00 + 1c94: 02 04 + 1c96: 3b 03 00 09 + 1c9a: 08 00 + 1c9c: 01 00 + 1c9e: 02 04 + 1ca0: 3d 03 + 1ca2: 00 09 + 1ca4: 04 00 + 1ca6: 01 00 + 1ca8: 02 04 + 1caa: 3d 03 + 1cac: 00 09 + 1cae: 08 00 + 1cb0: 01 00 + 1cb2: 02 04 + 1cb4: 3f 03 00 09 + 1cb8: 04 00 + 1cba: 01 00 + 1cbc: 02 04 + 1cbe: 41 03 + 1cc0: 00 09 + 1cc2: 04 00 + 1cc4: 01 00 + 1cc6: 02 04 + 1cc8: 43 03 00 09 fmadd.s ft6, ft0, fa6, ft1, rne + 1ccc: 08 00 + 1cce: 01 00 + 1cd0: 02 04 + 1cd2: 43 03 00 09 fmadd.s ft6, ft0, fa6, ft1, rne + 1cd6: 04 00 + 1cd8: 01 00 + 1cda: 02 04 + 1cdc: 43 03 00 09 fmadd.s ft6, ft0, fa6, ft1, rne + 1ce0: 00 00 + 1ce2: 01 00 + 1ce4: 02 04 + 1ce6: 43 03 00 09 fmadd.s ft6, ft0, fa6, ft1, rne + 1cea: 04 00 + 1cec: 01 00 + 1cee: 02 04 + 1cf0: 43 03 00 09 fmadd.s ft6, ft0, fa6, ft1, rne + 1cf4: 10 00 + 1cf6: 01 00 + 1cf8: 02 04 + 1cfa: 43 03 00 09 fmadd.s ft6, ft0, fa6, ft1, rne + 1cfe: 08 00 + 1d00: 01 00 + 1d02: 02 04 + 1d04: 44 03 + 1d06: 00 09 + 1d08: 08 00 + 1d0a: 01 00 + 1d0c: 02 04 + 1d0e: 44 03 + 1d10: 00 09 + 1d12: 08 00 + 1d14: 01 00 + 1d16: 02 04 + 1d18: 46 03 + 1d1a: 00 09 + 1d1c: 04 00 + 1d1e: 01 00 + 1d20: 02 04 + 1d22: 48 03 + 1d24: 00 09 + 1d26: 04 00 + 1d28: 01 00 + 1d2a: 02 04 + 1d2c: 4a 03 + 1d2e: 00 09 + 1d30: 08 00 + 1d32: 01 00 + 1d34: 02 04 + 1d36: 4a 03 + 1d38: 00 09 + 1d3a: 14 00 + 1d3c: 01 00 + 1d3e: 02 04 + 1d40: 4a 03 + 1d42: 00 09 + 1d44: 00 00 + 1d46: 01 00 + 1d48: 02 04 + 1d4a: 4a 03 + 1d4c: 00 09 + 1d4e: 00 00 + 1d50: 01 00 + 1d52: 02 04 + 1d54: 4a 03 + 1d56: 00 09 + 1d58: 00 00 + 1d5a: 01 00 + 1d5c: 02 04 + 1d5e: 4a 03 + 1d60: 00 09 + 1d62: 00 00 + 1d64: 01 00 + 1d66: 02 04 + 1d68: 4a 03 + 1d6a: 00 09 + 1d6c: 00 00 + 1d6e: 01 00 + 1d70: 02 04 + 1d72: 4a 03 + 1d74: 00 09 + 1d76: 00 00 + 1d78: 01 00 + 1d7a: 02 04 + 1d7c: 4a 03 + 1d7e: 00 09 + 1d80: 00 00 + 1d82: 01 00 + 1d84: 02 04 + 1d86: 4a 03 + 1d88: 00 09 + 1d8a: 04 00 + 1d8c: 01 00 + 1d8e: 02 04 + 1d90: 4a 03 + 1d92: 00 09 + 1d94: 00 00 + 1d96: 01 00 + 1d98: 02 04 + 1d9a: 4a 03 + 1d9c: 00 09 + 1d9e: 00 00 + 1da0: 01 00 + 1da2: 02 04 + 1da4: 4a 03 + 1da6: 00 09 + 1da8: 04 00 + 1daa: 01 00 + 1dac: 02 04 + 1dae: 4a 03 + 1db0: 00 09 + 1db2: 00 00 + 1db4: 01 00 + 1db6: 02 04 + 1db8: 4a 03 + 1dba: 00 09 + 1dbc: 04 00 + 1dbe: 01 00 + 1dc0: 02 04 + 1dc2: 4a 03 + 1dc4: 00 09 + 1dc6: 04 00 + 1dc8: 01 00 + 1dca: 02 04 + 1dcc: 4a 03 + 1dce: 00 09 + 1dd0: 0c 00 + 1dd2: 01 00 + 1dd4: 02 04 + 1dd6: 4a 03 + 1dd8: 00 09 + 1dda: 04 00 + 1ddc: 01 00 + 1dde: 02 04 + 1de0: 4b 03 00 09 fnmsub.s ft6, ft0, fa6, ft1, rne + 1de4: 04 00 + 1de6: 01 00 + 1de8: 02 04 + 1dea: 4d 03 + 1dec: 00 09 + 1dee: 08 00 + 1df0: 01 00 + 1df2: 02 04 + 1df4: 4d 03 + 1df6: 00 09 + 1df8: 08 00 + 1dfa: 01 00 + 1dfc: 02 04 + 1dfe: 4d 03 + 1e00: 00 09 + 1e02: 18 00 + 1e04: 01 00 + 1e06: 02 04 + 1e08: 4d 03 + 1e0a: 00 09 + 1e0c: 00 00 + 1e0e: 01 00 + 1e10: 02 04 + 1e12: 4d 03 + 1e14: 00 09 + 1e16: 00 00 + 1e18: 01 00 + 1e1a: 02 04 + 1e1c: 4f 06 03 00 fnmadd.s fa2, ft6, ft0, ft0, rne + 1e20: 09 04 + 1e22: 00 01 + 1e24: 00 02 + 1e26: 04 50 + 1e28: 03 00 09 04 lb zero, 64(s2) + 1e2c: 00 01 + 1e2e: 00 02 + 1e30: 04 52 + 1e32: 06 03 + 1e34: 00 09 + 1e36: 08 00 + 1e38: 01 00 + 1e3a: 02 04 + 1e3c: 52 03 + 1e3e: 00 09 + 1e40: 08 00 + 1e42: 01 00 + 1e44: 02 04 + 1e46: 52 03 + 1e48: 00 09 + 1e4a: 00 00 + 1e4c: 01 00 + 1e4e: 02 04 + 1e50: 52 03 + 1e52: 00 09 + 1e54: 00 00 + 1e56: 01 00 + 1e58: 02 04 + 1e5a: 52 03 + 1e5c: 00 09 + 1e5e: 00 00 + 1e60: 01 00 + 1e62: 02 04 + 1e64: 52 03 + 1e66: 00 09 + 1e68: 00 00 + 1e6a: 01 00 + 1e6c: 02 04 + 1e6e: 52 03 + 1e70: 00 09 + 1e72: 00 00 + 1e74: 01 00 + 1e76: 02 04 + 1e78: 52 03 + 1e7a: 00 09 + 1e7c: 00 00 + 1e7e: 01 00 + 1e80: 02 04 + 1e82: 58 06 + 1e84: 03 00 09 04 lb zero, 64(s2) + 1e88: 00 01 + 1e8a: 00 02 + 1e8c: 04 5b + 1e8e: 03 00 09 04 lb zero, 64(s2) + 1e92: 00 01 + 1e94: 00 02 + 1e96: 04 5c + 1e98: 03 00 09 04 lb zero, 64(s2) + 1e9c: 00 01 + 1e9e: 00 02 + 1ea0: 04 5e + 1ea2: 06 03 + 1ea4: 00 09 + 1ea6: 04 00 + 1ea8: 01 00 + 1eaa: 02 04 + 1eac: 5e 03 + 1eae: 00 09 + 1eb0: 04 00 + 1eb2: 01 00 + 1eb4: 02 04 + 1eb6: 5e 03 + 1eb8: 00 09 + 1eba: 00 00 + 1ebc: 01 00 + 1ebe: 02 04 + 1ec0: 5e 03 + 1ec2: 00 09 + 1ec4: 00 00 + 1ec6: 01 00 + 1ec8: 02 04 + 1eca: 5e 03 + 1ecc: 00 09 + 1ece: 04 00 + 1ed0: 01 00 + 1ed2: 02 04 + 1ed4: 5e 03 + 1ed6: 00 09 + 1ed8: 0c 00 + 1eda: 01 00 + 1edc: 02 04 + 1ede: 60 03 + 1ee0: 00 09 + 1ee2: 04 00 + 1ee4: 01 00 + 1ee6: 02 04 + 1ee8: 60 03 + 1eea: 00 09 + 1eec: 00 00 + 1eee: 01 00 + 1ef0: 02 04 + 1ef2: 62 06 + 1ef4: 03 00 09 04 lb zero, 64(s2) + 1ef8: 00 01 + 1efa: 00 02 + 1efc: 04 63 + 1efe: 06 03 + 1f00: 00 09 + 1f02: 04 00 + 1f04: 01 00 + 1f06: 02 04 + 1f08: 02 03 + 1f0a: 01 09 + 1f0c: 04 00 + 1f0e: 01 00 + 1f10: 02 04 + 1f12: 02 03 + 1f14: 00 09 + 1f16: 04 00 + 1f18: 01 00 + 1f1a: 02 04 + 1f1c: 06 03 + 1f1e: 00 09 + 1f20: 04 00 + 1f22: 01 00 + 1f24: 02 04 + 1f26: 06 03 + 1f28: 00 09 + 1f2a: 00 00 + 1f2c: 01 00 + 1f2e: 02 04 + 1f30: 08 03 + 1f32: 00 09 + 1f34: 08 00 + 1f36: 01 00 + 1f38: 02 04 + 1f3a: 08 03 + 1f3c: 00 09 + 1f3e: 08 00 + 1f40: 01 03 + 1f42: 00 09 + 1f44: 10 00 + 1f46: 01 03 + 1f48: 00 09 + 1f4a: 00 00 + 1f4c: 01 00 + 1f4e: 02 04 + 1f50: 0a 03 + 1f52: 00 09 + 1f54: 0c 00 + 1f56: 01 00 + 1f58: 02 04 + 1f5a: 0a 03 + 1f5c: 00 09 + 1f5e: 00 00 + 1f60: 01 00 + 1f62: 02 04 + 1f64: 0a 03 + 1f66: 00 09 + 1f68: 00 00 + 1f6a: 01 00 + 1f6c: 02 04 + 1f6e: 0a 03 + 1f70: 00 09 + 1f72: 04 00 + 1f74: 01 00 + 1f76: 02 04 + 1f78: 15 03 + 1f7a: 00 09 + 1f7c: 00 00 + 1f7e: 01 00 + 1f80: 02 04 + 1f82: 15 03 + 1f84: 00 09 + 1f86: 08 00 + 1f88: 01 00 + 1f8a: 02 04 + 1f8c: 0f 03 7f 09 + 1f90: 08 00 + 1f92: 01 00 + 1f94: 02 04 + 1f96: 0f 03 00 09 + 1f9a: 04 00 + 1f9c: 01 00 + 1f9e: 02 04 + 1fa0: 0f 03 00 09 + 1fa4: 00 00 + 1fa6: 01 00 + 1fa8: 02 04 + 1faa: 0f 03 00 09 + 1fae: 00 00 + 1fb0: 01 00 + 1fb2: 02 04 + 1fb4: 08 06 + 1fb6: 03 7e 09 08 + 1fba: 00 01 + 1fbc: 00 02 + 1fbe: 04 08 + 1fc0: 06 03 + 1fc2: 02 09 + 1fc4: 04 00 + 1fc6: 01 00 + 1fc8: 02 04 + 1fca: 08 03 + 1fcc: 00 09 + 1fce: 00 00 + 1fd0: 01 00 + 1fd2: 02 04 + 1fd4: 08 03 + 1fd6: 00 09 + 1fd8: 00 00 + 1fda: 01 00 + 1fdc: 02 04 + 1fde: 08 03 + 1fe0: 00 09 + 1fe2: 00 00 + 1fe4: 01 00 + 1fe6: 02 04 + 1fe8: 6c 03 + 1fea: 00 09 + 1fec: 0c 00 + 1fee: 01 00 + 1ff0: 02 04 + 1ff2: 6c 03 + 1ff4: 01 09 + 1ff6: 00 00 + 1ff8: 01 00 + 1ffa: 02 04 + 1ffc: 6c 03 + 1ffe: 00 09 + 2000: 00 00 + 2002: 01 00 + 2004: 02 04 + 2006: 6c 03 + 2008: 00 09 + 200a: 00 00 + 200c: 01 06 + 200e: 03 00 09 08 lb zero, 128(s2) + 2012: 00 01 + 2014: 00 02 + 2016: 04 05 + 2018: 03 7e 09 14 + 201c: 00 01 + 201e: 00 02 + 2020: 04 05 + 2022: 06 03 + 2024: 01 09 + 2026: 04 00 + 2028: 01 00 + 202a: 02 04 + 202c: 05 03 + 202e: 00 09 + 2030: 00 00 + 2032: 01 00 + 2034: 02 04 + 2036: 05 03 + 2038: 00 09 + 203a: 00 00 + 203c: 01 00 + 203e: 02 04 + 2040: 05 03 + 2042: 00 09 + 2044: 00 00 + 2046: 01 00 + 2048: 02 04 + 204a: 03 03 00 09 lb t1, 144(zero) + 204e: 04 00 + 2050: 01 06 + 2052: 03 01 09 04 lb sp, 64(s2) + 2056: 00 01 + 2058: 03 7f 09 10 + 205c: 00 01 + 205e: 06 03 + 2060: 01 09 + 2062: 14 00 + 2064: 01 03 + 2066: 00 09 + 2068: 00 00 + 206a: 01 00 + 206c: 02 04 + 206e: 15 03 + 2070: 00 09 + 2072: 04 00 + 2074: 01 00 + 2076: 02 04 + 2078: 15 03 + 207a: 00 09 + 207c: 00 00 + 207e: 01 00 + 2080: 02 04 + 2082: 15 03 + 2084: 00 09 + 2086: 00 00 + 2088: 01 03 + 208a: 00 09 + 208c: 08 00 + 208e: 01 03 + 2090: 00 09 + 2092: 00 00 + 2094: 01 00 + 2096: 02 04 + 2098: 09 03 + 209a: 00 09 + 209c: 04 00 + 209e: 01 00 + 20a0: 02 04 + 20a2: 09 03 + 20a4: 00 09 + 20a6: 00 00 + 20a8: 01 00 + 20aa: 02 04 + 20ac: 18 03 + 20ae: 00 09 + 20b0: 08 00 + 20b2: 01 00 + 20b4: 02 04 + 20b6: 18 03 + 20b8: 00 09 + 20ba: 0c 00 + 20bc: 01 00 + 20be: 02 04 + 20c0: 1a 03 + 20c2: 00 09 + 20c4: 04 00 + 20c6: 01 00 + 20c8: 02 04 + 20ca: 1a 03 + 20cc: 00 09 + 20ce: 00 00 + 20d0: 01 00 + 20d2: 02 04 + 20d4: 1a 03 + 20d6: 00 09 + 20d8: 00 00 + 20da: 01 00 + 20dc: 02 04 + 20de: 1a 03 + 20e0: 00 09 + 20e2: 00 00 + 20e4: 01 06 + 20e6: 03 00 09 08 lb zero, 128(s2) + 20ea: 00 01 + 20ec: 00 02 + 20ee: 04 77 + 20f0: 06 03 + 20f2: 00 09 + 20f4: 14 00 + 20f6: 01 00 + 20f8: 02 04 + 20fa: 77 03 00 09 + 20fe: 00 00 + 2100: 01 00 + 2102: 02 04 + 2104: 77 03 00 09 + 2108: 00 00 + 210a: 01 00 + 210c: 02 04 + 210e: 77 03 00 09 + 2112: 00 00 + 2114: 01 00 + 2116: 02 04 + 2118: 77 03 00 09 + 211c: 00 00 + 211e: 01 00 + 2120: 02 04 + 2122: 77 03 00 09 + 2126: 00 00 + 2128: 01 00 + 212a: 02 04 + 212c: 77 03 00 09 + 2130: 00 00 + 2132: 01 00 + 2134: 02 04 + 2136: 77 03 00 09 + 213a: 00 00 + 213c: 01 00 + 213e: 02 04 + 2140: 77 03 00 09 + 2144: 24 00 + 2146: 01 00 + 2148: 02 04 + 214a: 77 03 00 09 + 214e: 00 00 + 2150: 01 00 + 2152: 02 04 + 2154: 77 03 01 09 + 2158: 00 00 + 215a: 01 00 + 215c: 02 04 + 215e: 77 03 00 09 + 2162: 00 00 + 2164: 01 00 + 2166: 02 04 + 2168: 77 06 03 7f + 216c: 09 00 + 216e: 00 01 + 2170: 00 02 + 2172: 04 77 + 2174: 03 01 09 04 lb sp, 64(s2) + 2178: 00 01 + 217a: 00 02 + 217c: 04 01 + 217e: 06 03 + 2180: 00 09 + 2182: 04 00 + 2184: 01 00 + 2186: 02 04 + 2188: 01 03 + 218a: 00 09 + 218c: 04 00 + 218e: 01 00 + 2190: 02 04 + 2192: 01 03 + 2194: 02 09 + 2196: 00 00 + 2198: 01 05 + 219a: 01 06 + 219c: 03 01 09 00 lb sp, 0(s2) + 21a0: 00 01 + 21a2: 05 03 + 21a4: 06 03 + 21a6: 7c 09 + 21a8: 34 00 + 21aa: 01 03 + 21ac: 00 09 + 21ae: 20 00 + 21b0: 01 00 + 21b2: 02 04 + 21b4: 26 03 + 21b6: 00 09 + 21b8: 0c 00 + 21ba: 01 00 + 21bc: 02 04 + 21be: 26 03 + 21c0: 00 09 + 21c2: 00 00 + 21c4: 01 03 + 21c6: 00 09 + 21c8: 0c 00 + 21ca: 01 00 + 21cc: 02 04 + 21ce: 07 03 00 09 + 21d2: 08 00 + 21d4: 01 00 + 21d6: 02 04 + 21d8: 07 03 00 09 + 21dc: 00 00 + 21de: 01 00 + 21e0: 02 04 + 21e2: 27 03 00 09 + 21e6: 08 00 + 21e8: 01 00 + 21ea: 02 04 + 21ec: 27 03 00 09 + 21f0: 00 00 + 21f2: 01 00 + 21f4: 02 04 + 21f6: 27 03 00 09 + 21fa: 00 00 + 21fc: 01 00 + 21fe: 02 04 + 2200: 27 03 00 09 + 2204: 00 00 + 2206: 01 00 + 2208: 02 04 + 220a: 27 03 00 09 + 220e: 00 00 + 2210: 01 00 + 2212: 02 04 + 2214: 27 03 00 09 + 2218: 00 00 + 221a: 01 00 + 221c: 02 04 + 221e: 27 03 00 09 + 2222: 00 00 + 2224: 01 00 + 2226: 02 04 + 2228: 27 03 00 09 + 222c: 00 00 + 222e: 01 00 + 2230: 02 04 + 2232: 27 03 00 09 + 2236: 00 00 + 2238: 01 00 + 223a: 02 04 + 223c: 29 03 + 223e: 00 09 + 2240: 0c 00 + 2242: 01 00 + 2244: 02 04 + 2246: 29 03 + 2248: 00 09 + 224a: 08 00 + 224c: 01 03 + 224e: 00 09 + 2250: 14 00 + 2252: 01 03 + 2254: 00 09 + 2256: 00 00 + 2258: 01 00 + 225a: 02 04 + 225c: 2b 03 00 09 + 2260: 0c 00 + 2262: 01 00 + 2264: 02 04 + 2266: 2b 03 00 09 + 226a: 00 00 + 226c: 01 00 + 226e: 02 04 + 2270: 2b 03 00 09 + 2274: 00 00 + 2276: 01 00 + 2278: 02 04 + 227a: 2b 03 00 09 + 227e: 00 00 + 2280: 01 00 + 2282: 02 04 + 2284: 36 06 + 2286: 03 00 09 04 lb zero, 64(s2) + 228a: 00 01 + 228c: 00 02 + 228e: 04 36 + 2290: 06 03 + 2292: 00 09 + 2294: 08 00 + 2296: 01 03 + 2298: 00 09 + 229a: 04 00 + 229c: 01 03 + 229e: 00 09 + 22a0: 00 00 + 22a2: 01 00 + 22a4: 02 04 + 22a6: 36 03 + 22a8: 00 09 + 22aa: 08 00 + 22ac: 01 00 + 22ae: 02 04 + 22b0: 36 03 + 22b2: 00 09 + 22b4: 00 00 + 22b6: 01 00 + 22b8: 02 04 + 22ba: 36 03 + 22bc: 00 09 + 22be: 00 00 + 22c0: 01 00 + 22c2: 02 04 + 22c4: 36 03 + 22c6: 00 09 + 22c8: 00 00 + 22ca: 01 03 + 22cc: 00 09 + 22ce: 08 00 + 22d0: 01 03 + 22d2: 00 09 + 22d4: 00 00 + 22d6: 01 00 + 22d8: 02 04 + 22da: 2a 03 + 22dc: 00 09 + 22de: 08 00 + 22e0: 01 00 + 22e2: 02 04 + 22e4: 2a 03 + 22e6: 00 09 + 22e8: 00 00 + 22ea: 01 00 + 22ec: 02 04 + 22ee: 3b 03 00 09 + 22f2: 0c 00 + 22f4: 01 00 + 22f6: 02 04 + 22f8: 3b 03 00 09 + 22fc: 08 00 + 22fe: 01 00 + 2300: 02 04 + 2302: 3c 03 + 2304: 00 09 + 2306: 08 00 + 2308: 01 00 + 230a: 02 04 + 230c: 3e 03 + 230e: 00 09 + 2310: 08 00 + 2312: 01 00 + 2314: 02 04 + 2316: 3e 03 + 2318: 00 09 + 231a: 1c 00 + 231c: 01 00 + 231e: 02 04 + 2320: 4b 03 00 09 fnmsub.s ft6, ft0, fa6, ft1, rne + 2324: 04 00 + 2326: 01 00 + 2328: 02 04 + 232a: 4b 03 00 09 fnmsub.s ft6, ft0, fa6, ft1, rne + 232e: 00 00 + 2330: 01 00 + 2332: 02 04 + 2334: 4c 03 + 2336: 00 09 + 2338: 08 00 + 233a: 01 00 + 233c: 02 04 + 233e: 4c 03 + 2340: 00 09 + 2342: 08 00 + 2344: 01 03 + 2346: 00 09 + 2348: 10 00 + 234a: 01 03 + 234c: 00 09 + 234e: 00 00 + 2350: 01 00 + 2352: 02 04 + 2354: 4e 03 + 2356: 00 09 + 2358: 0c 00 + 235a: 01 00 + 235c: 02 04 + 235e: 4e 03 + 2360: 00 09 + 2362: 00 00 + 2364: 01 00 + 2366: 02 04 + 2368: 4e 03 + 236a: 00 09 + 236c: 00 00 + 236e: 01 00 + 2370: 02 04 + 2372: 4e 03 + 2374: 00 09 + 2376: 04 00 + 2378: 01 00 + 237a: 02 04 + 237c: 59 03 + 237e: 00 09 + 2380: 00 00 + 2382: 01 00 + 2384: 02 04 + 2386: 59 03 + 2388: 00 09 + 238a: 08 00 + 238c: 01 00 + 238e: 02 04 + 2390: 3f 03 00 09 + 2394: 08 00 + 2396: 01 00 + 2398: 02 04 + 239a: 47 06 03 00 fmsub.s fa2, ft6, ft0, ft0, rne + 239e: 09 18 + 23a0: 00 01 + 23a2: 00 02 + 23a4: 04 4a + 23a6: 03 00 09 08 lb zero, 128(s2) + 23aa: 00 01 + 23ac: 00 02 + 23ae: 04 4a + 23b0: 06 03 + 23b2: 00 09 + 23b4: 0c 00 + 23b6: 01 03 + 23b8: 00 09 + 23ba: 08 00 + 23bc: 01 03 + 23be: 00 09 + 23c0: 00 00 + 23c2: 01 00 + 23c4: 02 04 + 23c6: 59 03 + 23c8: 00 09 + 23ca: 04 00 + 23cc: 01 00 + 23ce: 02 04 + 23d0: 59 03 + 23d2: 00 09 + 23d4: 00 00 + 23d6: 01 00 + 23d8: 02 04 + 23da: 59 03 + 23dc: 00 09 + 23de: 00 00 + 23e0: 01 03 + 23e2: 00 09 + 23e4: 08 00 + 23e6: 01 03 + 23e8: 00 09 + 23ea: 00 00 + 23ec: 01 00 + 23ee: 02 04 + 23f0: 4d 03 + 23f2: 00 09 + 23f4: 04 00 + 23f6: 01 00 + 23f8: 02 04 + 23fa: 4d 03 + 23fc: 00 09 + 23fe: 00 00 + 2400: 01 00 + 2402: 02 04 + 2404: 5c 03 + 2406: 00 09 + 2408: 08 00 + 240a: 01 00 + 240c: 02 04 + 240e: 5c 03 + 2410: 00 09 + 2412: 00 00 + 2414: 01 00 + 2416: 02 04 + 2418: 5c 03 + 241a: 00 09 + 241c: 00 00 + 241e: 01 00 + 2420: 02 04 + 2422: 5c 03 + 2424: 00 09 + 2426: 04 00 + 2428: 01 06 + 242a: 03 00 09 0c lb zero, 192(s2) + 242e: 00 01 + 2430: 00 02 + 2432: 04 5d + 2434: 06 03 + 2436: 00 09 + 2438: 08 00 + 243a: 01 00 + 243c: 02 04 + 243e: 5d 03 + 2440: 00 09 + 2442: 00 00 + 2444: 01 00 + 2446: 02 04 + 2448: 5d 03 + 244a: 00 09 + 244c: 00 00 + 244e: 01 00 + 2450: 02 04 + 2452: 5d 03 + 2454: 00 09 + 2456: 0c 00 + 2458: 01 00 + 245a: 02 04 + 245c: 5d 03 + 245e: 00 09 + 2460: 04 00 + 2462: 01 00 + 2464: 02 04 + 2466: 60 06 + 2468: 03 00 09 04 lb zero, 64(s2) + 246c: 00 01 + 246e: 03 00 09 08 lb zero, 128(s2) + 2472: 00 01 + 2474: 00 02 + 2476: 04 61 + 2478: 06 03 + 247a: 00 09 + 247c: 04 00 + 247e: 01 00 + 2480: 02 04 + 2482: 3d 03 + 2484: 00 09 + 2486: 08 00 + 2488: 01 00 + 248a: 02 04 + 248c: 3d 03 + 248e: 00 09 + 2490: 00 00 + 2492: 01 00 + 2494: 02 04 + 2496: 64 03 + 2498: 00 09 + 249a: 08 00 + 249c: 01 00 + 249e: 02 04 + 24a0: 64 03 + 24a2: 00 09 + 24a4: 00 00 + 24a6: 01 00 + 24a8: 02 04 + 24aa: 64 03 + 24ac: 00 09 + 24ae: 00 00 + 24b0: 01 00 + 24b2: 02 04 + 24b4: 64 03 + 24b6: 00 09 + 24b8: 00 00 + 24ba: 01 00 + 24bc: 02 04 + 24be: 64 03 + 24c0: 00 09 + 24c2: 08 00 + 24c4: 01 06 + 24c6: 03 00 09 0c lb zero, 192(s2) + 24ca: 00 01 + 24cc: 00 02 + 24ce: 04 65 + 24d0: 06 03 + 24d2: 00 09 + 24d4: 0c 00 + 24d6: 01 00 + 24d8: 02 04 + 24da: 65 03 + 24dc: 00 09 + 24de: 00 00 + 24e0: 01 00 + 24e2: 02 04 + 24e4: 74 03 + 24e6: 00 09 + 24e8: 04 00 + 24ea: 01 06 + 24ec: 03 00 09 08 lb zero, 128(s2) + 24f0: 00 01 + 24f2: 06 03 + 24f4: 00 09 + 24f6: 08 00 + 24f8: 01 03 + 24fa: 00 09 + 24fc: 00 00 + 24fe: 01 03 + 2500: 00 09 + 2502: 10 00 + 2504: 01 03 + 2506: 00 09 + 2508: 00 00 + 250a: 01 06 + 250c: 03 7f 09 1c + 2510: 00 01 + 2512: 03 01 09 08 lb sp, 128(s2) + 2516: 00 01 + 2518: 03 7f 09 20 + 251c: 00 01 + 251e: 06 03 + 2520: 00 09 + 2522: 04 00 + 2524: 01 03 + 2526: 00 09 + 2528: 00 00 + 252a: 01 09 + 252c: 08 00 + 252e: 00 01 + 2530: 01 59 + 2532: 10 00 + 2534: 00 03 + 2536: 00 93 + 2538: 00 00 + 253a: 00 01 + 253c: 01 fb + 253e: 0e 0d + 2540: 00 01 + 2542: 01 01 + 2544: 01 00 + 2546: 00 00 + 2548: 01 00 + 254a: 00 01 + 254c: 2e 2e + 254e: 2f 2e 2e 2f + 2552: 2e 2e + 2554: 2f 2e 2e 2f + 2558: 72 69 + 255a: 73 63 76 2d csrrsi t1, 727, 12 + 255e: 67 63 63 2f + 2562: 6c 69 + 2564: 62 67 + 2566: 63 63 2f 73 bltu t5, s2, 1830 + 256a: 6f 66 74 2d jal a2, 289494 + 256e: 66 70 + 2570: 00 2e + 2572: 2e 2f + 2574: 2e 2e + 2576: 2f 2e 2e 2f + 257a: 2e 2e + 257c: 2f 72 69 73 + 2580: 63 76 2d 67 bgeu s10, s2, 1644 + 2584: 63 63 2f 6c bltu t5, sp, 1734 + 2588: 69 62 + 258a: 67 63 63 2f + 258e: 2e 2e + 2590: 2f 69 6e 63 + 2594: 6c 75 + 2596: 64 65 + 2598: 00 00 + 259a: 6d 75 + 259c: 6c 64 + 259e: 66 33 + 25a0: 2e 63 + 25a2: 00 01 + 25a4: 00 00 + 25a6: 73 6f 66 74 csrrsi t5, 1862, 12 + 25aa: 2d 66 + 25ac: 70 2e + 25ae: 68 00 + 25b0: 01 00 + 25b2: 00 64 + 25b4: 6f 75 62 6c jal a0, 161478 + 25b8: 65 2e + 25ba: 68 00 + 25bc: 01 00 + 25be: 00 6c + 25c0: 6f 6e 67 6c jal t3, 485062 + 25c4: 6f 6e 67 2e jal t3, 484070 + 25c8: 68 00 + 25ca: 02 00 + 25cc: 00 00 + 25ce: 05 01 + 25d0: 00 05 + 25d2: 02 b0 + 25d4: 10 01 + 25d6: 80 03 + 25d8: 23 01 05 03 sb a6, 34(a0) + 25dc: 03 01 09 00 lb sp, 0(s2) + 25e0: 00 01 + 25e2: 03 00 09 00 lb zero, 0(s2) + 25e6: 00 01 + 25e8: 05 0d + 25ea: 03 00 09 00 lb zero, 0(s2) + 25ee: 00 01 + 25f0: 05 03 + 25f2: 03 01 09 00 lb sp, 0(s2) + 25f6: 00 01 + 25f8: 03 00 09 00 lb zero, 0(s2) + 25fc: 00 01 + 25fe: 03 00 09 00 lb zero, 0(s2) + 2602: 00 01 + 2604: 03 00 09 00 lb zero, 0(s2) + 2608: 00 01 + 260a: 03 01 09 00 lb sp, 0(s2) + 260e: 00 01 + 2610: 03 00 09 00 lb zero, 0(s2) + 2614: 00 01 + 2616: 03 00 09 00 lb zero, 0(s2) + 261a: 00 01 + 261c: 03 00 09 00 lb zero, 0(s2) + 2620: 00 01 + 2622: 03 01 09 00 lb sp, 0(s2) + 2626: 00 01 + 2628: 03 00 09 00 lb zero, 0(s2) + 262c: 00 01 + 262e: 03 00 09 00 lb zero, 0(s2) + 2632: 00 01 + 2634: 03 00 09 00 lb zero, 0(s2) + 2638: 00 01 + 263a: 03 01 09 00 lb sp, 0(s2) + 263e: 00 01 + 2640: 03 02 09 00 lb tp, 0(s2) + 2644: 00 01 + 2646: 03 00 09 00 lb zero, 0(s2) + 264a: 00 01 + 264c: 05 01 + 264e: 06 03 + 2650: 79 09 + 2652: 00 00 + 2654: 01 03 + 2656: 00 09 + 2658: 30 00 + 265a: 01 05 + 265c: 03 03 07 09 lb t1, 144(a4) + 2660: 0c 00 + 2662: 01 06 + 2664: 03 00 09 04 lb zero, 64(s2) + 2668: 00 01 + 266a: 03 01 09 00 lb sp, 0(s2) + 266e: 00 01 + 2670: 03 00 09 00 lb zero, 0(s2) + 2674: 00 01 + 2676: 03 00 09 00 lb zero, 0(s2) + 267a: 00 01 + 267c: 03 00 09 00 lb zero, 0(s2) + 2680: 00 01 + 2682: 03 00 09 00 lb zero, 0(s2) + 2686: 00 01 + 2688: 03 00 09 00 lb zero, 0(s2) + 268c: 00 01 + 268e: 03 00 09 10 lb zero, 256(s2) + 2692: 00 01 + 2694: 03 00 09 00 lb zero, 0(s2) + 2698: 00 01 + 269a: 03 00 09 04 lb zero, 64(s2) + 269e: 00 01 + 26a0: 03 00 09 00 lb zero, 0(s2) + 26a4: 00 01 + 26a6: 03 00 09 00 lb zero, 0(s2) + 26aa: 00 01 + 26ac: 00 02 + 26ae: 04 01 + 26b0: 03 00 09 10 lb zero, 256(s2) + 26b4: 00 01 + 26b6: 00 02 + 26b8: 04 01 + 26ba: 03 00 09 00 lb zero, 0(s2) + 26be: 00 01 + 26c0: 00 02 + 26c2: 04 01 + 26c4: 03 00 09 00 lb zero, 0(s2) + 26c8: 00 01 + 26ca: 00 02 + 26cc: 04 01 + 26ce: 03 00 09 00 lb zero, 0(s2) + 26d2: 00 01 + 26d4: 00 02 + 26d6: 04 01 + 26d8: 03 00 09 14 lb zero, 320(s2) + 26dc: 00 01 + 26de: 00 02 + 26e0: 04 01 + 26e2: 03 00 09 04 lb zero, 64(s2) + 26e6: 00 01 + 26e8: 00 02 + 26ea: 04 01 + 26ec: 03 00 09 00 lb zero, 0(s2) + 26f0: 00 01 + 26f2: 00 02 + 26f4: 04 01 + 26f6: 03 00 09 04 lb zero, 64(s2) + 26fa: 00 01 + 26fc: 00 02 + 26fe: 04 01 + 2700: 03 00 09 00 lb zero, 0(s2) + 2704: 00 01 + 2706: 00 02 + 2708: 04 29 + 270a: 03 00 09 00 lb zero, 0(s2) + 270e: 00 01 + 2710: 00 02 + 2712: 04 29 + 2714: 03 00 09 00 lb zero, 0(s2) + 2718: 00 01 + 271a: 06 03 + 271c: 79 09 + 271e: 04 00 + 2720: 01 00 + 2722: 02 04 + 2724: 02 06 + 2726: 03 07 09 08 lb a4, 128(s2) + 272a: 00 01 + 272c: 00 02 + 272e: 04 0d + 2730: 03 00 09 08 lb zero, 128(s2) + 2734: 00 01 + 2736: 00 02 + 2738: 04 0d + 273a: 03 00 09 00 lb zero, 0(s2) + 273e: 00 01 + 2740: 00 02 + 2742: 04 0d + 2744: 03 00 09 00 lb zero, 0(s2) + 2748: 00 01 + 274a: 00 02 + 274c: 04 0d + 274e: 03 00 09 00 lb zero, 0(s2) + 2752: 00 01 + 2754: 00 02 + 2756: 04 11 + 2758: 03 00 09 04 lb zero, 64(s2) + 275c: 00 01 + 275e: 00 02 + 2760: 04 11 + 2762: 03 00 09 00 lb zero, 0(s2) + 2766: 00 01 + 2768: 00 02 + 276a: 04 11 + 276c: 03 00 09 00 lb zero, 0(s2) + 2770: 00 01 + 2772: 00 02 + 2774: 04 11 + 2776: 03 00 09 00 lb zero, 0(s2) + 277a: 00 01 + 277c: 00 02 + 277e: 04 11 + 2780: 03 00 09 08 lb zero, 128(s2) + 2784: 00 01 + 2786: 00 02 + 2788: 04 1f + 278a: 03 00 09 00 lb zero, 0(s2) + 278e: 00 01 + 2790: 00 02 + 2792: 04 1f + 2794: 03 00 09 00 lb zero, 0(s2) + 2798: 00 01 + 279a: 00 02 + 279c: 04 1f + 279e: 03 00 09 04 lb zero, 64(s2) + 27a2: 00 01 + 27a4: 00 02 + 27a6: 04 20 + 27a8: 03 00 09 08 lb zero, 128(s2) + 27ac: 00 01 + 27ae: 00 02 + 27b0: 04 20 + 27b2: 03 00 09 08 lb zero, 128(s2) + 27b6: 00 01 + 27b8: 00 02 + 27ba: 04 20 + 27bc: 03 00 09 10 lb zero, 256(s2) + 27c0: 00 01 + 27c2: 00 02 + 27c4: 04 20 + 27c6: 03 00 09 04 lb zero, 64(s2) + 27ca: 00 01 + 27cc: 00 02 + 27ce: 04 29 + 27d0: 03 00 09 00 lb zero, 0(s2) + 27d4: 00 01 + 27d6: 00 02 + 27d8: 04 18 + 27da: 03 00 09 0c lb zero, 192(s2) + 27de: 00 01 + 27e0: 00 02 + 27e2: 04 18 + 27e4: 03 00 09 00 lb zero, 0(s2) + 27e8: 00 01 + 27ea: 00 02 + 27ec: 04 18 + 27ee: 03 00 09 00 lb zero, 0(s2) + 27f2: 00 01 + 27f4: 00 02 + 27f6: 04 18 + 27f8: 03 00 09 00 lb zero, 0(s2) + 27fc: 00 01 + 27fe: 00 02 + 2800: 04 18 + 2802: 03 00 09 04 lb zero, 64(s2) + 2806: 00 01 + 2808: 00 02 + 280a: 04 18 + 280c: 03 00 09 00 lb zero, 0(s2) + 2810: 00 01 + 2812: 00 02 + 2814: 04 21 + 2816: 03 00 09 08 lb zero, 128(s2) + 281a: 00 01 + 281c: 00 02 + 281e: 04 21 + 2820: 03 00 09 08 lb zero, 128(s2) + 2824: 00 01 + 2826: 00 02 + 2828: 04 03 + 282a: 03 00 09 08 lb zero, 128(s2) + 282e: 00 01 + 2830: 00 02 + 2832: 04 2c + 2834: 06 03 + 2836: 00 09 + 2838: 08 00 + 283a: 01 00 + 283c: 02 04 + 283e: 2c 06 + 2840: 03 00 09 08 lb zero, 128(s2) + 2844: 00 01 + 2846: 00 02 + 2848: 04 2c + 284a: 03 00 09 00 lb zero, 0(s2) + 284e: 00 01 + 2850: 00 02 + 2852: 04 08 + 2854: 03 00 09 10 lb zero, 256(s2) + 2858: 00 01 + 285a: 00 02 + 285c: 04 08 + 285e: 03 00 09 00 lb zero, 0(s2) + 2862: 00 01 + 2864: 00 02 + 2866: 04 08 + 2868: 03 01 09 00 lb sp, 0(s2) + 286c: 00 01 + 286e: 00 02 + 2870: 04 08 + 2872: 03 00 09 00 lb zero, 0(s2) + 2876: 00 01 + 2878: 00 02 + 287a: 04 08 + 287c: 03 00 09 00 lb zero, 0(s2) + 2880: 00 01 + 2882: 00 02 + 2884: 04 08 + 2886: 03 00 09 00 lb zero, 0(s2) + 288a: 00 01 + 288c: 00 02 + 288e: 04 08 + 2890: 03 00 09 00 lb zero, 0(s2) + 2894: 00 01 + 2896: 00 02 + 2898: 04 08 + 289a: 03 00 09 10 lb zero, 256(s2) + 289e: 00 01 + 28a0: 00 02 + 28a2: 04 08 + 28a4: 03 00 09 04 lb zero, 64(s2) + 28a8: 00 01 + 28aa: 00 02 + 28ac: 04 08 + 28ae: 03 00 09 04 lb zero, 64(s2) + 28b2: 00 01 + 28b4: 00 02 + 28b6: 04 08 + 28b8: 03 00 09 04 lb zero, 64(s2) + 28bc: 00 01 + 28be: 00 02 + 28c0: 04 08 + 28c2: 03 00 09 00 lb zero, 0(s2) + 28c6: 00 01 + 28c8: 00 02 + 28ca: 04 08 + 28cc: 03 00 09 00 lb zero, 0(s2) + 28d0: 00 01 + 28d2: 06 03 + 28d4: 00 09 + 28d6: 04 00 + 28d8: 01 00 + 28da: 02 04 + 28dc: 01 06 + 28de: 03 00 09 08 lb zero, 128(s2) + 28e2: 00 01 + 28e4: 00 02 + 28e6: 04 01 + 28e8: 03 00 09 00 lb zero, 0(s2) + 28ec: 00 01 + 28ee: 00 02 + 28f0: 04 01 + 28f2: 03 00 09 00 lb zero, 0(s2) + 28f6: 00 01 + 28f8: 00 02 + 28fa: 04 01 + 28fc: 03 00 09 00 lb zero, 0(s2) + 2900: 00 01 + 2902: 00 02 + 2904: 04 01 + 2906: 03 00 09 14 lb zero, 320(s2) + 290a: 00 01 + 290c: 00 02 + 290e: 04 01 + 2910: 03 00 09 08 lb zero, 128(s2) + 2914: 00 01 + 2916: 00 02 + 2918: 04 01 + 291a: 03 00 09 00 lb zero, 0(s2) + 291e: 00 01 + 2920: 00 02 + 2922: 04 01 + 2924: 03 00 09 00 lb zero, 0(s2) + 2928: 00 01 + 292a: 00 02 + 292c: 04 01 + 292e: 03 00 09 00 lb zero, 0(s2) + 2932: 00 01 + 2934: 00 02 + 2936: 04 29 + 2938: 03 00 09 00 lb zero, 0(s2) + 293c: 00 01 + 293e: 00 02 + 2940: 04 29 + 2942: 03 00 09 00 lb zero, 0(s2) + 2946: 00 01 + 2948: 00 02 + 294a: 04 08 + 294c: 03 00 09 04 lb zero, 64(s2) + 2950: 00 01 + 2952: 00 02 + 2954: 04 08 + 2956: 03 00 09 00 lb zero, 0(s2) + 295a: 00 01 + 295c: 00 02 + 295e: 04 08 + 2960: 03 01 09 00 lb sp, 0(s2) + 2964: 00 01 + 2966: 00 02 + 2968: 04 08 + 296a: 03 00 09 00 lb zero, 0(s2) + 296e: 00 01 + 2970: 00 02 + 2972: 04 08 + 2974: 03 00 09 18 lb zero, 384(s2) + 2978: 00 01 + 297a: 00 02 + 297c: 04 08 + 297e: 03 00 09 04 lb zero, 64(s2) + 2982: 00 01 + 2984: 06 03 + 2986: 7e 09 + 2988: 28 00 + 298a: 01 00 + 298c: 02 04 + 298e: 02 06 + 2990: 03 01 09 1c lb sp, 448(s2) + 2994: 00 01 + 2996: 00 02 + 2998: 04 0d + 299a: 03 00 09 08 lb zero, 128(s2) + 299e: 00 01 + 29a0: 00 02 + 29a2: 04 0d + 29a4: 03 00 09 00 lb zero, 0(s2) + 29a8: 00 01 + 29aa: 00 02 + 29ac: 04 0d + 29ae: 03 00 09 00 lb zero, 0(s2) + 29b2: 00 01 + 29b4: 00 02 + 29b6: 04 0d + 29b8: 03 00 09 00 lb zero, 0(s2) + 29bc: 00 01 + 29be: 00 02 + 29c0: 04 11 + 29c2: 03 00 09 04 lb zero, 64(s2) + 29c6: 00 01 + 29c8: 00 02 + 29ca: 04 11 + 29cc: 03 00 09 00 lb zero, 0(s2) + 29d0: 00 01 + 29d2: 00 02 + 29d4: 04 11 + 29d6: 03 00 09 00 lb zero, 0(s2) + 29da: 00 01 + 29dc: 00 02 + 29de: 04 11 + 29e0: 03 00 09 00 lb zero, 0(s2) + 29e4: 00 01 + 29e6: 00 02 + 29e8: 04 11 + 29ea: 03 00 09 08 lb zero, 128(s2) + 29ee: 00 01 + 29f0: 00 02 + 29f2: 04 1f + 29f4: 03 00 09 00 lb zero, 0(s2) + 29f8: 00 01 + 29fa: 00 02 + 29fc: 04 1f + 29fe: 03 00 09 00 lb zero, 0(s2) + 2a02: 00 01 + 2a04: 00 02 + 2a06: 04 1f + 2a08: 03 00 09 04 lb zero, 64(s2) + 2a0c: 00 01 + 2a0e: 00 02 + 2a10: 04 20 + 2a12: 03 00 09 08 lb zero, 128(s2) + 2a16: 00 01 + 2a18: 00 02 + 2a1a: 04 20 + 2a1c: 03 00 09 08 lb zero, 128(s2) + 2a20: 00 01 + 2a22: 00 02 + 2a24: 04 20 + 2a26: 03 00 09 10 lb zero, 256(s2) + 2a2a: 00 01 + 2a2c: 00 02 + 2a2e: 04 20 + 2a30: 03 00 09 04 lb zero, 64(s2) + 2a34: 00 01 + 2a36: 00 02 + 2a38: 04 29 + 2a3a: 03 00 09 00 lb zero, 0(s2) + 2a3e: 00 01 + 2a40: 00 02 + 2a42: 04 18 + 2a44: 03 00 09 0c lb zero, 192(s2) + 2a48: 00 01 + 2a4a: 00 02 + 2a4c: 04 18 + 2a4e: 03 00 09 00 lb zero, 0(s2) + 2a52: 00 01 + 2a54: 00 02 + 2a56: 04 18 + 2a58: 03 00 09 00 lb zero, 0(s2) + 2a5c: 00 01 + 2a5e: 00 02 + 2a60: 04 18 + 2a62: 03 00 09 00 lb zero, 0(s2) + 2a66: 00 01 + 2a68: 00 02 + 2a6a: 04 18 + 2a6c: 03 00 09 08 lb zero, 128(s2) + 2a70: 00 01 + 2a72: 00 02 + 2a74: 04 18 + 2a76: 03 00 09 00 lb zero, 0(s2) + 2a7a: 00 01 + 2a7c: 00 02 + 2a7e: 04 21 + 2a80: 03 00 09 08 lb zero, 128(s2) + 2a84: 00 01 + 2a86: 00 02 + 2a88: 04 21 + 2a8a: 03 00 09 08 lb zero, 128(s2) + 2a8e: 00 01 + 2a90: 00 02 + 2a92: 04 03 + 2a94: 03 00 09 08 lb zero, 128(s2) + 2a98: 00 01 + 2a9a: 00 02 + 2a9c: 04 2c + 2a9e: 03 00 09 08 lb zero, 128(s2) + 2aa2: 00 01 + 2aa4: 00 02 + 2aa6: 04 2c + 2aa8: 03 00 09 00 lb zero, 0(s2) + 2aac: 00 01 + 2aae: 06 03 + 2ab0: 00 09 + 2ab2: 0c 00 + 2ab4: 01 03 + 2ab6: 01 09 + 2ab8: 3c 00 + 2aba: 01 00 + 2abc: 02 04 + 2abe: 77 06 03 01 + 2ac2: 09 14 + 2ac4: 00 01 + 2ac6: 00 02 + 2ac8: 04 77 + 2aca: 03 00 09 00 lb zero, 0(s2) + 2ace: 00 01 + 2ad0: 00 02 + 2ad2: 04 77 + 2ad4: 03 00 09 00 lb zero, 0(s2) + 2ad8: 00 01 + 2ada: 00 02 + 2adc: 04 77 + 2ade: 03 00 09 00 lb zero, 0(s2) + 2ae2: 00 01 + 2ae4: 00 02 + 2ae6: 04 77 + 2ae8: 03 00 09 00 lb zero, 0(s2) + 2aec: 00 01 + 2aee: 00 02 + 2af0: 04 77 + 2af2: 03 00 09 00 lb zero, 0(s2) + 2af6: 00 01 + 2af8: 00 02 + 2afa: 04 77 + 2afc: 03 00 09 00 lb zero, 0(s2) + 2b00: 00 01 + 2b02: 00 02 + 2b04: 04 77 + 2b06: 03 00 09 00 lb zero, 0(s2) + 2b0a: 00 01 + 2b0c: 00 02 + 2b0e: 04 77 + 2b10: 03 00 09 28 lb zero, 640(s2) + 2b14: 00 01 + 2b16: 00 02 + 2b18: 04 77 + 2b1a: 03 00 09 00 lb zero, 0(s2) + 2b1e: 00 01 + 2b20: 00 02 + 2b22: 04 77 + 2b24: 03 01 09 00 lb sp, 0(s2) + 2b28: 00 01 + 2b2a: 00 02 + 2b2c: 04 77 + 2b2e: 03 00 09 00 lb zero, 0(s2) + 2b32: 00 01 + 2b34: 00 02 + 2b36: 04 01 + 2b38: 03 00 09 04 lb zero, 64(s2) + 2b3c: 00 01 + 2b3e: 00 02 + 2b40: 04 01 + 2b42: 03 00 09 04 lb zero, 64(s2) + 2b46: 00 01 + 2b48: 00 02 + 2b4a: 04 01 + 2b4c: 03 02 09 00 lb tp, 0(s2) + 2b50: 00 01 + 2b52: 05 01 + 2b54: 06 03 + 2b56: 01 09 + 2b58: 00 00 + 2b5a: 01 05 + 2b5c: 03 00 02 04 lb zero, 64(tp) + 2b60: 02 06 + 2b62: 03 7b 09 34 + 2b66: 00 01 + 2b68: 00 02 + 2b6a: 04 02 + 2b6c: 03 00 09 00 lb zero, 0(s2) + 2b70: 00 01 + 2b72: 00 02 + 2b74: 04 02 + 2b76: 03 00 09 00 lb zero, 0(s2) + 2b7a: 00 01 + 2b7c: 00 02 + 2b7e: 04 02 + 2b80: 03 00 09 00 lb zero, 0(s2) + 2b84: 00 01 + 2b86: 00 02 + 2b88: 04 02 + 2b8a: 03 00 09 00 lb zero, 0(s2) + 2b8e: 00 01 + 2b90: 00 02 + 2b92: 04 02 + 2b94: 03 00 09 00 lb zero, 0(s2) + 2b98: 00 01 + 2b9a: 00 02 + 2b9c: 04 02 + 2b9e: 03 00 09 00 lb zero, 0(s2) + 2ba2: 00 01 + 2ba4: 00 02 + 2ba6: 04 02 + 2ba8: 03 00 09 00 lb zero, 0(s2) + 2bac: 00 01 + 2bae: 00 02 + 2bb0: 04 02 + 2bb2: 03 00 09 00 lb zero, 0(s2) + 2bb6: 00 01 + 2bb8: 00 02 + 2bba: 04 02 + 2bbc: 03 00 09 00 lb zero, 0(s2) + 2bc0: 00 01 + 2bc2: 00 02 + 2bc4: 04 02 + 2bc6: 03 00 09 00 lb zero, 0(s2) + 2bca: 00 01 + 2bcc: 00 02 + 2bce: 04 02 + 2bd0: 03 00 09 0c lb zero, 192(s2) + 2bd4: 00 01 + 2bd6: 00 02 + 2bd8: 04 02 + 2bda: 03 00 09 00 lb zero, 0(s2) + 2bde: 00 01 + 2be0: 00 02 + 2be2: 04 02 + 2be4: 03 00 09 04 lb zero, 64(s2) + 2be8: 00 01 + 2bea: 00 02 + 2bec: 04 02 + 2bee: 03 00 09 10 lb zero, 256(s2) + 2bf2: 00 01 + 2bf4: 00 02 + 2bf6: 04 02 + 2bf8: 03 00 09 00 lb zero, 0(s2) + 2bfc: 00 01 + 2bfe: 00 02 + 2c00: 04 02 + 2c02: 03 00 09 04 lb zero, 64(s2) + 2c06: 00 01 + 2c08: 00 02 + 2c0a: 04 02 + 2c0c: 03 00 09 10 lb zero, 256(s2) + 2c10: 00 01 + 2c12: 00 02 + 2c14: 04 02 + 2c16: 03 00 09 00 lb zero, 0(s2) + 2c1a: 00 01 + 2c1c: 00 02 + 2c1e: 04 02 + 2c20: 03 00 09 00 lb zero, 0(s2) + 2c24: 00 01 + 2c26: 00 02 + 2c28: 04 09 + 2c2a: 03 00 09 04 lb zero, 64(s2) + 2c2e: 00 01 + 2c30: 00 02 + 2c32: 04 0b + 2c34: 03 00 09 04 lb zero, 64(s2) + 2c38: 00 01 + 2c3a: 00 02 + 2c3c: 04 0b + 2c3e: 03 00 09 0c lb zero, 192(s2) + 2c42: 00 01 + 2c44: 00 02 + 2c46: 04 0b + 2c48: 03 00 09 10 lb zero, 256(s2) + 2c4c: 00 01 + 2c4e: 00 02 + 2c50: 04 0b + 2c52: 03 00 09 00 lb zero, 0(s2) + 2c56: 00 01 + 2c58: 00 02 + 2c5a: 04 0b + 2c5c: 03 00 09 00 lb zero, 0(s2) + 2c60: 00 01 + 2c62: 00 02 + 2c64: 04 0b + 2c66: 03 00 09 00 lb zero, 0(s2) + 2c6a: 00 01 + 2c6c: 00 02 + 2c6e: 04 0b + 2c70: 03 00 09 00 lb zero, 0(s2) + 2c74: 00 01 + 2c76: 00 02 + 2c78: 04 0b + 2c7a: 03 00 09 00 lb zero, 0(s2) + 2c7e: 00 01 + 2c80: 00 02 + 2c82: 04 0b + 2c84: 03 00 09 00 lb zero, 0(s2) + 2c88: 00 01 + 2c8a: 00 02 + 2c8c: 04 0b + 2c8e: 03 00 09 00 lb zero, 0(s2) + 2c92: 00 01 + 2c94: 00 02 + 2c96: 04 0b + 2c98: 03 00 09 00 lb zero, 0(s2) + 2c9c: 00 01 + 2c9e: 00 02 + 2ca0: 04 0b + 2ca2: 03 00 09 04 lb zero, 64(s2) + 2ca6: 00 01 + 2ca8: 00 02 + 2caa: 04 0b + 2cac: 03 00 09 00 lb zero, 0(s2) + 2cb0: 00 01 + 2cb2: 00 02 + 2cb4: 04 0b + 2cb6: 03 00 09 04 lb zero, 64(s2) + 2cba: 00 01 + 2cbc: 00 02 + 2cbe: 04 0b + 2cc0: 03 00 09 14 lb zero, 320(s2) + 2cc4: 00 01 + 2cc6: 00 02 + 2cc8: 04 0b + 2cca: 03 00 09 00 lb zero, 0(s2) + 2cce: 00 01 + 2cd0: 00 02 + 2cd2: 04 0b + 2cd4: 03 00 09 00 lb zero, 0(s2) + 2cd8: 00 01 + 2cda: 00 02 + 2cdc: 04 0c + 2cde: 03 00 09 04 lb zero, 64(s2) + 2ce2: 00 01 + 2ce4: 00 02 + 2ce6: 04 0e + 2ce8: 03 00 09 08 lb zero, 128(s2) + 2cec: 00 01 + 2cee: 00 02 + 2cf0: 04 0e + 2cf2: 03 00 09 08 lb zero, 128(s2) + 2cf6: 00 01 + 2cf8: 00 02 + 2cfa: 04 0e + 2cfc: 03 00 09 28 lb zero, 640(s2) + 2d00: 00 01 + 2d02: 00 02 + 2d04: 04 0e + 2d06: 03 00 09 00 lb zero, 0(s2) + 2d0a: 00 01 + 2d0c: 00 02 + 2d0e: 04 0e + 2d10: 03 00 09 00 lb zero, 0(s2) + 2d14: 00 01 + 2d16: 00 02 + 2d18: 04 0e + 2d1a: 03 00 09 00 lb zero, 0(s2) + 2d1e: 00 01 + 2d20: 00 02 + 2d22: 04 0e + 2d24: 03 00 09 00 lb zero, 0(s2) + 2d28: 00 01 + 2d2a: 00 02 + 2d2c: 04 0e + 2d2e: 03 00 09 00 lb zero, 0(s2) + 2d32: 00 01 + 2d34: 00 02 + 2d36: 04 0e + 2d38: 03 00 09 00 lb zero, 0(s2) + 2d3c: 00 01 + 2d3e: 00 02 + 2d40: 04 0e + 2d42: 03 00 09 00 lb zero, 0(s2) + 2d46: 00 01 + 2d48: 00 02 + 2d4a: 04 0e + 2d4c: 03 00 09 00 lb zero, 0(s2) + 2d50: 00 01 + 2d52: 00 02 + 2d54: 04 0e + 2d56: 03 00 09 04 lb zero, 64(s2) + 2d5a: 00 01 + 2d5c: 00 02 + 2d5e: 04 0e + 2d60: 03 00 09 00 lb zero, 0(s2) + 2d64: 00 01 + 2d66: 00 02 + 2d68: 04 0e + 2d6a: 03 00 09 0c lb zero, 192(s2) + 2d6e: 00 01 + 2d70: 00 02 + 2d72: 04 0e + 2d74: 03 00 09 00 lb zero, 0(s2) + 2d78: 00 01 + 2d7a: 00 02 + 2d7c: 04 0e + 2d7e: 03 00 09 04 lb zero, 64(s2) + 2d82: 00 01 + 2d84: 00 02 + 2d86: 04 0e + 2d88: 03 00 09 04 lb zero, 64(s2) + 2d8c: 00 01 + 2d8e: 00 02 + 2d90: 04 0f + 2d92: 03 00 09 04 lb zero, 64(s2) + 2d96: 00 01 + 2d98: 00 02 + 2d9a: 04 11 + 2d9c: 03 00 09 04 lb zero, 64(s2) + 2da0: 00 01 + 2da2: 00 02 + 2da4: 04 11 + 2da6: 03 00 09 24 lb zero, 576(s2) + 2daa: 00 01 + 2dac: 00 02 + 2dae: 04 11 + 2db0: 03 00 09 00 lb zero, 0(s2) + 2db4: 00 01 + 2db6: 00 02 + 2db8: 04 11 + 2dba: 03 00 09 00 lb zero, 0(s2) + 2dbe: 00 01 + 2dc0: 00 02 + 2dc2: 04 11 + 2dc4: 03 00 09 00 lb zero, 0(s2) + 2dc8: 00 01 + 2dca: 00 02 + 2dcc: 04 11 + 2dce: 03 00 09 00 lb zero, 0(s2) + 2dd2: 00 01 + 2dd4: 00 02 + 2dd6: 04 11 + 2dd8: 03 00 09 00 lb zero, 0(s2) + 2ddc: 00 01 + 2dde: 00 02 + 2de0: 04 11 + 2de2: 03 00 09 00 lb zero, 0(s2) + 2de6: 00 01 + 2de8: 00 02 + 2dea: 04 11 + 2dec: 03 00 09 00 lb zero, 0(s2) + 2df0: 00 01 + 2df2: 00 02 + 2df4: 04 11 + 2df6: 03 00 09 00 lb zero, 0(s2) + 2dfa: 00 01 + 2dfc: 00 02 + 2dfe: 04 11 + 2e00: 03 00 09 00 lb zero, 0(s2) + 2e04: 00 01 + 2e06: 00 02 + 2e08: 04 11 + 2e0a: 03 00 09 00 lb zero, 0(s2) + 2e0e: 00 01 + 2e10: 00 02 + 2e12: 04 11 + 2e14: 03 00 09 00 lb zero, 0(s2) + 2e18: 00 01 + 2e1a: 00 02 + 2e1c: 04 11 + 2e1e: 03 00 09 04 lb zero, 64(s2) + 2e22: 00 01 + 2e24: 00 02 + 2e26: 04 11 + 2e28: 03 00 09 04 lb zero, 64(s2) + 2e2c: 00 01 + 2e2e: 00 02 + 2e30: 04 11 + 2e32: 03 00 09 0c lb zero, 192(s2) + 2e36: 00 01 + 2e38: 00 02 + 2e3a: 04 11 + 2e3c: 03 00 09 04 lb zero, 64(s2) + 2e40: 00 01 + 2e42: 00 02 + 2e44: 04 12 + 2e46: 03 00 09 04 lb zero, 64(s2) + 2e4a: 00 01 + 2e4c: 00 02 + 2e4e: 04 14 + 2e50: 03 00 09 04 lb zero, 64(s2) + 2e54: 00 01 + 2e56: 00 02 + 2e58: 04 14 + 2e5a: 03 00 09 00 lb zero, 0(s2) + 2e5e: 00 01 + 2e60: 00 02 + 2e62: 04 14 + 2e64: 03 00 09 00 lb zero, 0(s2) + 2e68: 00 01 + 2e6a: 00 02 + 2e6c: 04 14 + 2e6e: 03 00 09 00 lb zero, 0(s2) + 2e72: 00 01 + 2e74: 00 02 + 2e76: 04 14 + 2e78: 03 00 09 00 lb zero, 0(s2) + 2e7c: 00 01 + 2e7e: 00 02 + 2e80: 04 14 + 2e82: 03 00 09 00 lb zero, 0(s2) + 2e86: 00 01 + 2e88: 00 02 + 2e8a: 04 14 + 2e8c: 03 00 09 18 lb zero, 384(s2) + 2e90: 00 01 + 2e92: 00 02 + 2e94: 04 14 + 2e96: 03 00 09 08 lb zero, 128(s2) + 2e9a: 00 01 + 2e9c: 00 02 + 2e9e: 04 14 + 2ea0: 03 00 09 04 lb zero, 64(s2) + 2ea4: 00 01 + 2ea6: 00 02 + 2ea8: 04 14 + 2eaa: 03 00 09 00 lb zero, 0(s2) + 2eae: 00 01 + 2eb0: 00 02 + 2eb2: 04 14 + 2eb4: 03 00 09 04 lb zero, 64(s2) + 2eb8: 00 01 + 2eba: 00 02 + 2ebc: 04 14 + 2ebe: 03 00 09 00 lb zero, 0(s2) + 2ec2: 00 01 + 2ec4: 00 02 + 2ec6: 04 14 + 2ec8: 03 00 09 00 lb zero, 0(s2) + 2ecc: 00 01 + 2ece: 00 02 + 2ed0: 04 14 + 2ed2: 03 00 09 00 lb zero, 0(s2) + 2ed6: 00 01 + 2ed8: 00 02 + 2eda: 04 14 + 2edc: 03 00 09 00 lb zero, 0(s2) + 2ee0: 00 01 + 2ee2: 00 02 + 2ee4: 04 14 + 2ee6: 03 00 09 00 lb zero, 0(s2) + 2eea: 00 01 + 2eec: 00 02 + 2eee: 04 14 + 2ef0: 03 00 09 04 lb zero, 64(s2) + 2ef4: 00 01 + 2ef6: 00 02 + 2ef8: 04 14 + 2efa: 03 00 09 04 lb zero, 64(s2) + 2efe: 00 01 + 2f00: 00 02 + 2f02: 04 14 + 2f04: 03 00 09 04 lb zero, 64(s2) + 2f08: 00 01 + 2f0a: 00 02 + 2f0c: 04 14 + 2f0e: 03 00 09 00 lb zero, 0(s2) + 2f12: 00 01 + 2f14: 00 02 + 2f16: 04 14 + 2f18: 03 00 09 04 lb zero, 64(s2) + 2f1c: 00 01 + 2f1e: 00 02 + 2f20: 04 14 + 2f22: 03 00 09 00 lb zero, 0(s2) + 2f26: 00 01 + 2f28: 00 02 + 2f2a: 04 14 + 2f2c: 03 00 09 00 lb zero, 0(s2) + 2f30: 00 01 + 2f32: 00 02 + 2f34: 04 14 + 2f36: 03 00 09 00 lb zero, 0(s2) + 2f3a: 00 01 + 2f3c: 00 02 + 2f3e: 04 14 + 2f40: 03 00 09 00 lb zero, 0(s2) + 2f44: 00 01 + 2f46: 00 02 + 2f48: 04 14 + 2f4a: 03 00 09 00 lb zero, 0(s2) + 2f4e: 00 01 + 2f50: 00 02 + 2f52: 04 14 + 2f54: 03 00 09 00 lb zero, 0(s2) + 2f58: 00 01 + 2f5a: 00 02 + 2f5c: 04 14 + 2f5e: 03 00 09 00 lb zero, 0(s2) + 2f62: 00 01 + 2f64: 00 02 + 2f66: 04 14 + 2f68: 03 00 09 00 lb zero, 0(s2) + 2f6c: 00 01 + 2f6e: 00 02 + 2f70: 04 14 + 2f72: 03 00 09 00 lb zero, 0(s2) + 2f76: 00 01 + 2f78: 00 02 + 2f7a: 04 14 + 2f7c: 03 00 09 00 lb zero, 0(s2) + 2f80: 00 01 + 2f82: 00 02 + 2f84: 04 14 + 2f86: 03 00 09 00 lb zero, 0(s2) + 2f8a: 00 01 + 2f8c: 00 02 + 2f8e: 04 14 + 2f90: 03 00 09 00 lb zero, 0(s2) + 2f94: 00 01 + 2f96: 00 02 + 2f98: 04 14 + 2f9a: 03 00 09 00 lb zero, 0(s2) + 2f9e: 00 01 + 2fa0: 00 02 + 2fa2: 04 14 + 2fa4: 03 00 09 00 lb zero, 0(s2) + 2fa8: 00 01 + 2faa: 00 02 + 2fac: 04 14 + 2fae: 03 00 09 00 lb zero, 0(s2) + 2fb2: 00 01 + 2fb4: 00 02 + 2fb6: 04 14 + 2fb8: 03 00 09 00 lb zero, 0(s2) + 2fbc: 00 01 + 2fbe: 00 02 + 2fc0: 04 14 + 2fc2: 03 00 09 00 lb zero, 0(s2) + 2fc6: 00 01 + 2fc8: 00 02 + 2fca: 04 14 + 2fcc: 03 00 09 00 lb zero, 0(s2) + 2fd0: 00 01 + 2fd2: 00 02 + 2fd4: 04 14 + 2fd6: 03 00 09 00 lb zero, 0(s2) + 2fda: 00 01 + 2fdc: 00 02 + 2fde: 04 14 + 2fe0: 03 00 09 00 lb zero, 0(s2) + 2fe4: 00 01 + 2fe6: 00 02 + 2fe8: 04 14 + 2fea: 03 00 09 00 lb zero, 0(s2) + 2fee: 00 01 + 2ff0: 00 02 + 2ff2: 04 14 + 2ff4: 03 00 09 00 lb zero, 0(s2) + 2ff8: 00 01 + 2ffa: 00 02 + 2ffc: 04 14 + 2ffe: 03 00 09 00 lb zero, 0(s2) + 3002: 00 01 + 3004: 00 02 + 3006: 04 14 + 3008: 03 00 09 00 lb zero, 0(s2) + 300c: 00 01 + 300e: 00 02 + 3010: 04 14 + 3012: 03 00 09 00 lb zero, 0(s2) + 3016: 00 01 + 3018: 00 02 + 301a: 04 14 + 301c: 03 00 09 50 lb zero, 1280(s2) + 3020: 00 01 + 3022: 00 02 + 3024: 04 14 + 3026: 03 00 09 00 lb zero, 0(s2) + 302a: 00 01 + 302c: 00 02 + 302e: 04 14 + 3030: 03 00 09 00 lb zero, 0(s2) + 3034: 00 01 + 3036: 00 02 + 3038: 04 14 + 303a: 03 00 09 00 lb zero, 0(s2) + 303e: 00 01 + 3040: 00 02 + 3042: 04 14 + 3044: 03 00 09 00 lb zero, 0(s2) + 3048: 00 01 + 304a: 00 02 + 304c: 04 14 + 304e: 03 00 09 00 lb zero, 0(s2) + 3052: 00 01 + 3054: 00 02 + 3056: 04 14 + 3058: 03 00 09 00 lb zero, 0(s2) + 305c: 00 01 + 305e: 00 02 + 3060: 04 14 + 3062: 03 00 09 04 lb zero, 64(s2) + 3066: 00 01 + 3068: 00 02 + 306a: 04 14 + 306c: 03 00 09 00 lb zero, 0(s2) + 3070: 00 01 + 3072: 00 02 + 3074: 04 14 + 3076: 03 00 09 00 lb zero, 0(s2) + 307a: 00 01 + 307c: 00 02 + 307e: 04 14 + 3080: 03 00 09 00 lb zero, 0(s2) + 3084: 00 01 + 3086: 00 02 + 3088: 04 14 + 308a: 03 00 09 00 lb zero, 0(s2) + 308e: 00 01 + 3090: 00 02 + 3092: 04 26 + 3094: 03 00 09 04 lb zero, 64(s2) + 3098: 00 01 + 309a: 00 02 + 309c: 04 26 + 309e: 03 00 09 00 lb zero, 0(s2) + 30a2: 00 01 + 30a4: 00 02 + 30a6: 04 26 + 30a8: 03 00 09 14 lb zero, 320(s2) + 30ac: 00 01 + 30ae: 00 02 + 30b0: 04 02 + 30b2: 03 01 09 04 lb sp, 64(s2) + 30b6: 00 01 + 30b8: 00 02 + 30ba: 04 02 + 30bc: 03 00 09 04 lb zero, 64(s2) + 30c0: 00 01 + 30c2: 00 02 + 30c4: 04 06 + 30c6: 03 00 09 04 lb zero, 64(s2) + 30ca: 00 01 + 30cc: 00 02 + 30ce: 04 06 + 30d0: 03 00 09 00 lb zero, 0(s2) + 30d4: 00 01 + 30d6: 00 02 + 30d8: 04 08 + 30da: 03 00 09 08 lb zero, 128(s2) + 30de: 00 01 + 30e0: 00 02 + 30e2: 04 08 + 30e4: 03 00 09 08 lb zero, 128(s2) + 30e8: 00 01 + 30ea: 03 00 09 10 lb zero, 256(s2) + 30ee: 00 01 + 30f0: 03 00 09 00 lb zero, 0(s2) + 30f4: 00 01 + 30f6: 00 02 + 30f8: 04 0a + 30fa: 03 00 09 0c lb zero, 192(s2) + 30fe: 00 01 + 3100: 00 02 + 3102: 04 0a + 3104: 03 00 09 00 lb zero, 0(s2) + 3108: 00 01 + 310a: 00 02 + 310c: 04 0a + 310e: 03 00 09 00 lb zero, 0(s2) + 3112: 00 01 + 3114: 00 02 + 3116: 04 0a + 3118: 03 00 09 04 lb zero, 64(s2) + 311c: 00 01 + 311e: 00 02 + 3120: 04 15 + 3122: 03 00 09 00 lb zero, 0(s2) + 3126: 00 01 + 3128: 00 02 + 312a: 04 15 + 312c: 03 00 09 08 lb zero, 128(s2) + 3130: 00 01 + 3132: 00 02 + 3134: 04 07 + 3136: 06 03 + 3138: 7d 09 + 313a: 08 00 + 313c: 01 00 + 313e: 02 04 + 3140: 07 06 03 02 + 3144: 09 04 + 3146: 00 01 + 3148: 00 02 + 314a: 04 2f + 314c: 03 00 09 0c lb zero, 192(s2) + 3150: 00 01 + 3152: 00 02 + 3154: 04 2f + 3156: 03 01 09 00 lb sp, 0(s2) + 315a: 00 01 + 315c: 00 02 + 315e: 04 2f + 3160: 03 00 09 00 lb zero, 0(s2) + 3164: 00 01 + 3166: 00 02 + 3168: 04 2f + 316a: 03 00 09 00 lb zero, 0(s2) + 316e: 00 01 + 3170: 06 03 + 3172: 00 09 + 3174: 08 00 + 3176: 01 00 + 3178: 02 04 + 317a: 04 03 + 317c: 7e 09 + 317e: 1c 00 + 3180: 01 00 + 3182: 02 04 + 3184: 04 06 + 3186: 03 01 09 04 lb sp, 64(s2) + 318a: 00 01 + 318c: 06 03 + 318e: 00 09 + 3190: 04 00 + 3192: 01 06 + 3194: 03 01 09 08 lb sp, 128(s2) + 3198: 00 01 + 319a: 03 00 09 00 lb zero, 0(s2) + 319e: 00 01 + 31a0: 00 02 + 31a2: 04 15 + 31a4: 03 00 09 04 lb zero, 64(s2) + 31a8: 00 01 + 31aa: 00 02 + 31ac: 04 15 + 31ae: 03 00 09 00 lb zero, 0(s2) + 31b2: 00 01 + 31b4: 00 02 + 31b6: 04 15 + 31b8: 03 00 09 00 lb zero, 0(s2) + 31bc: 00 01 + 31be: 03 00 09 08 lb zero, 128(s2) + 31c2: 00 01 + 31c4: 03 00 09 00 lb zero, 0(s2) + 31c8: 00 01 + 31ca: 00 02 + 31cc: 04 09 + 31ce: 03 00 09 04 lb zero, 64(s2) + 31d2: 00 01 + 31d4: 00 02 + 31d6: 04 09 + 31d8: 03 00 09 00 lb zero, 0(s2) + 31dc: 00 01 + 31de: 00 02 + 31e0: 04 18 + 31e2: 03 00 09 08 lb zero, 128(s2) + 31e6: 00 01 + 31e8: 00 02 + 31ea: 04 18 + 31ec: 03 00 09 0c lb zero, 192(s2) + 31f0: 00 01 + 31f2: 00 02 + 31f4: 04 1a + 31f6: 03 00 09 04 lb zero, 64(s2) + 31fa: 00 01 + 31fc: 00 02 + 31fe: 04 1a + 3200: 03 00 09 00 lb zero, 0(s2) + 3204: 00 01 + 3206: 00 02 + 3208: 04 1a + 320a: 03 00 09 00 lb zero, 0(s2) + 320e: 00 01 + 3210: 00 02 + 3212: 04 1a + 3214: 03 00 09 00 lb zero, 0(s2) + 3218: 00 01 + 321a: 06 03 + 321c: 00 09 + 321e: 08 00 + 3220: 01 06 + 3222: 03 00 09 18 lb zero, 384(s2) + 3226: 00 01 + 3228: 03 00 09 20 lb zero, 512(s2) + 322c: 00 01 + 322e: 00 02 + 3230: 04 26 + 3232: 03 00 09 0c lb zero, 192(s2) + 3236: 00 01 + 3238: 00 02 + 323a: 04 26 + 323c: 03 00 09 00 lb zero, 0(s2) + 3240: 00 01 + 3242: 03 00 09 0c lb zero, 192(s2) + 3246: 00 01 + 3248: 00 02 + 324a: 04 07 + 324c: 03 00 09 08 lb zero, 128(s2) + 3250: 00 01 + 3252: 00 02 + 3254: 04 07 + 3256: 03 00 09 00 lb zero, 0(s2) + 325a: 00 01 + 325c: 00 02 + 325e: 04 27 + 3260: 03 00 09 08 lb zero, 128(s2) + 3264: 00 01 + 3266: 00 02 + 3268: 04 27 + 326a: 03 00 09 00 lb zero, 0(s2) + 326e: 00 01 + 3270: 00 02 + 3272: 04 27 + 3274: 03 00 09 00 lb zero, 0(s2) + 3278: 00 01 + 327a: 00 02 + 327c: 04 27 + 327e: 03 00 09 00 lb zero, 0(s2) + 3282: 00 01 + 3284: 00 02 + 3286: 04 27 + 3288: 03 00 09 00 lb zero, 0(s2) + 328c: 00 01 + 328e: 00 02 + 3290: 04 27 + 3292: 03 00 09 00 lb zero, 0(s2) + 3296: 00 01 + 3298: 00 02 + 329a: 04 27 + 329c: 03 00 09 00 lb zero, 0(s2) + 32a0: 00 01 + 32a2: 00 02 + 32a4: 04 27 + 32a6: 03 00 09 00 lb zero, 0(s2) + 32aa: 00 01 + 32ac: 00 02 + 32ae: 04 27 + 32b0: 03 00 09 00 lb zero, 0(s2) + 32b4: 00 01 + 32b6: 00 02 + 32b8: 04 29 + 32ba: 03 00 09 0c lb zero, 192(s2) + 32be: 00 01 + 32c0: 00 02 + 32c2: 04 29 + 32c4: 03 00 09 08 lb zero, 128(s2) + 32c8: 00 01 + 32ca: 03 00 09 14 lb zero, 320(s2) + 32ce: 00 01 + 32d0: 03 00 09 00 lb zero, 0(s2) + 32d4: 00 01 + 32d6: 00 02 + 32d8: 04 2b + 32da: 03 00 09 0c lb zero, 192(s2) + 32de: 00 01 + 32e0: 00 02 + 32e2: 04 2b + 32e4: 03 00 09 00 lb zero, 0(s2) + 32e8: 00 01 + 32ea: 00 02 + 32ec: 04 2b + 32ee: 03 00 09 00 lb zero, 0(s2) + 32f2: 00 01 + 32f4: 00 02 + 32f6: 04 2b + 32f8: 03 00 09 00 lb zero, 0(s2) + 32fc: 00 01 + 32fe: 00 02 + 3300: 04 36 + 3302: 06 03 + 3304: 00 09 + 3306: 04 00 + 3308: 01 00 + 330a: 02 04 + 330c: 36 06 + 330e: 03 00 09 08 lb zero, 128(s2) + 3312: 00 01 + 3314: 03 00 09 04 lb zero, 64(s2) + 3318: 00 01 + 331a: 03 00 09 00 lb zero, 0(s2) + 331e: 00 01 + 3320: 00 02 + 3322: 04 36 + 3324: 03 00 09 08 lb zero, 128(s2) + 3328: 00 01 + 332a: 00 02 + 332c: 04 36 + 332e: 03 00 09 00 lb zero, 0(s2) + 3332: 00 01 + 3334: 00 02 + 3336: 04 36 + 3338: 03 00 09 00 lb zero, 0(s2) + 333c: 00 01 + 333e: 00 02 + 3340: 04 36 + 3342: 03 00 09 00 lb zero, 0(s2) + 3346: 00 01 + 3348: 03 00 09 08 lb zero, 128(s2) + 334c: 00 01 + 334e: 03 00 09 00 lb zero, 0(s2) + 3352: 00 01 + 3354: 00 02 + 3356: 04 2a + 3358: 03 00 09 08 lb zero, 128(s2) + 335c: 00 01 + 335e: 00 02 + 3360: 04 2a + 3362: 03 00 09 00 lb zero, 0(s2) + 3366: 00 01 + 3368: 00 02 + 336a: 04 3b + 336c: 03 00 09 0c lb zero, 192(s2) + 3370: 00 01 + 3372: 00 02 + 3374: 04 3b + 3376: 03 00 09 08 lb zero, 128(s2) + 337a: 00 01 + 337c: 00 02 + 337e: 04 3c + 3380: 03 00 09 08 lb zero, 128(s2) + 3384: 00 01 + 3386: 00 02 + 3388: 04 3e + 338a: 03 00 09 08 lb zero, 128(s2) + 338e: 00 01 + 3390: 00 02 + 3392: 04 3e + 3394: 03 00 09 1c lb zero, 448(s2) + 3398: 00 01 + 339a: 00 02 + 339c: 04 4b + 339e: 03 00 09 04 lb zero, 64(s2) + 33a2: 00 01 + 33a4: 00 02 + 33a6: 04 4b + 33a8: 03 00 09 00 lb zero, 0(s2) + 33ac: 00 01 + 33ae: 00 02 + 33b0: 04 4c + 33b2: 03 00 09 08 lb zero, 128(s2) + 33b6: 00 01 + 33b8: 00 02 + 33ba: 04 4c + 33bc: 03 00 09 08 lb zero, 128(s2) + 33c0: 00 01 + 33c2: 03 00 09 10 lb zero, 256(s2) + 33c6: 00 01 + 33c8: 03 00 09 00 lb zero, 0(s2) + 33cc: 00 01 + 33ce: 00 02 + 33d0: 04 4e + 33d2: 03 00 09 0c lb zero, 192(s2) + 33d6: 00 01 + 33d8: 00 02 + 33da: 04 4e + 33dc: 03 00 09 00 lb zero, 0(s2) + 33e0: 00 01 + 33e2: 00 02 + 33e4: 04 4e + 33e6: 03 00 09 00 lb zero, 0(s2) + 33ea: 00 01 + 33ec: 00 02 + 33ee: 04 4e + 33f0: 03 00 09 04 lb zero, 64(s2) + 33f4: 00 01 + 33f6: 00 02 + 33f8: 04 59 + 33fa: 03 00 09 00 lb zero, 0(s2) + 33fe: 00 01 + 3400: 00 02 + 3402: 04 59 + 3404: 03 00 09 08 lb zero, 128(s2) + 3408: 00 01 + 340a: 00 02 + 340c: 04 3f + 340e: 03 00 09 08 lb zero, 128(s2) + 3412: 00 01 + 3414: 00 02 + 3416: 04 47 + 3418: 06 03 + 341a: 00 09 + 341c: 18 00 + 341e: 01 00 + 3420: 02 04 + 3422: 4a 03 + 3424: 00 09 + 3426: 08 00 + 3428: 01 00 + 342a: 02 04 + 342c: 4a 06 + 342e: 03 00 09 0c lb zero, 192(s2) + 3432: 00 01 + 3434: 03 00 09 08 lb zero, 128(s2) + 3438: 00 01 + 343a: 03 00 09 00 lb zero, 0(s2) + 343e: 00 01 + 3440: 00 02 + 3442: 04 59 + 3444: 03 00 09 04 lb zero, 64(s2) + 3448: 00 01 + 344a: 00 02 + 344c: 04 59 + 344e: 03 00 09 00 lb zero, 0(s2) + 3452: 00 01 + 3454: 00 02 + 3456: 04 59 + 3458: 03 00 09 00 lb zero, 0(s2) + 345c: 00 01 + 345e: 03 00 09 08 lb zero, 128(s2) + 3462: 00 01 + 3464: 03 00 09 00 lb zero, 0(s2) + 3468: 00 01 + 346a: 00 02 + 346c: 04 4d + 346e: 03 00 09 04 lb zero, 64(s2) + 3472: 00 01 + 3474: 00 02 + 3476: 04 4d + 3478: 03 00 09 00 lb zero, 0(s2) + 347c: 00 01 + 347e: 00 02 + 3480: 04 5c + 3482: 03 00 09 08 lb zero, 128(s2) + 3486: 00 01 + 3488: 00 02 + 348a: 04 5c + 348c: 03 00 09 00 lb zero, 0(s2) + 3490: 00 01 + 3492: 00 02 + 3494: 04 5c + 3496: 03 00 09 00 lb zero, 0(s2) + 349a: 00 01 + 349c: 00 02 + 349e: 04 5c + 34a0: 03 00 09 04 lb zero, 64(s2) + 34a4: 00 01 + 34a6: 06 03 + 34a8: 00 09 + 34aa: 0c 00 + 34ac: 01 00 + 34ae: 02 04 + 34b0: 5d 06 + 34b2: 03 00 09 08 lb zero, 128(s2) + 34b6: 00 01 + 34b8: 00 02 + 34ba: 04 5d + 34bc: 03 00 09 00 lb zero, 0(s2) + 34c0: 00 01 + 34c2: 00 02 + 34c4: 04 5d + 34c6: 03 00 09 00 lb zero, 0(s2) + 34ca: 00 01 + 34cc: 00 02 + 34ce: 04 5d + 34d0: 03 00 09 0c lb zero, 192(s2) + 34d4: 00 01 + 34d6: 00 02 + 34d8: 04 5d + 34da: 03 00 09 04 lb zero, 64(s2) + 34de: 00 01 + 34e0: 00 02 + 34e2: 04 60 + 34e4: 06 03 + 34e6: 00 09 + 34e8: 04 00 + 34ea: 01 03 + 34ec: 00 09 + 34ee: 08 00 + 34f0: 01 00 + 34f2: 02 04 + 34f4: 61 06 + 34f6: 03 00 09 04 lb zero, 64(s2) + 34fa: 00 01 + 34fc: 00 02 + 34fe: 04 3d + 3500: 03 00 09 08 lb zero, 128(s2) + 3504: 00 01 + 3506: 00 02 + 3508: 04 3d + 350a: 03 00 09 00 lb zero, 0(s2) + 350e: 00 01 + 3510: 00 02 + 3512: 04 64 + 3514: 03 00 09 08 lb zero, 128(s2) + 3518: 00 01 + 351a: 00 02 + 351c: 04 64 + 351e: 03 00 09 00 lb zero, 0(s2) + 3522: 00 01 + 3524: 00 02 + 3526: 04 64 + 3528: 03 00 09 00 lb zero, 0(s2) + 352c: 00 01 + 352e: 00 02 + 3530: 04 64 + 3532: 03 00 09 00 lb zero, 0(s2) + 3536: 00 01 + 3538: 00 02 + 353a: 04 64 + 353c: 03 00 09 08 lb zero, 128(s2) + 3540: 00 01 + 3542: 06 03 + 3544: 00 09 + 3546: 0c 00 + 3548: 01 00 + 354a: 02 04 + 354c: 65 06 + 354e: 03 00 09 0c lb zero, 192(s2) + 3552: 00 01 + 3554: 00 02 + 3556: 04 65 + 3558: 03 00 09 00 lb zero, 0(s2) + 355c: 00 01 + 355e: 00 02 + 3560: 04 74 + 3562: 03 00 09 04 lb zero, 64(s2) + 3566: 00 01 + 3568: 06 03 + 356a: 00 09 + 356c: 08 00 + 356e: 01 06 + 3570: 03 00 09 08 lb zero, 128(s2) + 3574: 00 01 + 3576: 03 00 09 00 lb zero, 0(s2) + 357a: 00 01 + 357c: 03 00 09 10 lb zero, 256(s2) + 3580: 00 01 + 3582: 03 00 09 00 lb zero, 0(s2) + 3586: 00 01 + 3588: 09 30 + 358a: 00 00 + 358c: 01 01 + 358e: 28 03 + 3590: 00 00 + 3592: 03 00 a3 00 lb zero, 10(t1) + 3596: 00 00 + 3598: 01 01 + 359a: fb 0e 0d 00 + 359e: 01 01 + 35a0: 01 01 + 35a2: 00 00 + 35a4: 00 01 + 35a6: 00 00 + 35a8: 01 2e + 35aa: 2e 2f + 35ac: 2e 2e + 35ae: 2f 2e 2e 2f + 35b2: 2e 2e + 35b4: 2f 72 69 73 + 35b8: 63 76 2d 67 bgeu s10, s2, 1644 + 35bc: 63 63 2f 6c bltu t5, sp, 1734 + 35c0: 69 62 + 35c2: 67 63 63 2f + 35c6: 73 6f 66 74 csrrsi t5, 1862, 12 + 35ca: 2d 66 + 35cc: 70 00 + 35ce: 2e 00 + 35d0: 2e 2e + 35d2: 2f 2e 2e 2f + 35d6: 2e 2e + 35d8: 2f 2e 2e 2f + 35dc: 72 69 + 35de: 73 63 76 2d csrrsi t1, 727, 12 + 35e2: 67 63 63 2f + 35e6: 6c 69 + 35e8: 62 67 + 35ea: 63 63 2f 2e bltu t5, sp, 742 + 35ee: 2e 2f + 35f0: 69 6e + 35f2: 63 6c 75 64 bltu a0, t2, 1624 + 35f6: 65 00 + 35f8: 00 65 + 35fa: 71 74 + 35fc: 66 32 + 35fe: 2e 63 + 3600: 00 01 + 3602: 00 00 + 3604: 73 66 70 2d csrrsi a2, 727, 0 + 3608: 6d 61 + 360a: 63 68 69 6e bltu s2, t1, 1776 + 360e: 65 2e + 3610: 68 00 + 3612: 02 00 + 3614: 00 73 + 3616: 6f 66 74 2d jal a2, 289494 + 361a: 66 70 + 361c: 2e 68 + 361e: 00 01 + 3620: 00 00 + 3622: 71 75 + 3624: 61 64 + 3626: 2e 68 + 3628: 00 01 + 362a: 00 00 + 362c: 6c 6f + 362e: 6e 67 + 3630: 6c 6f + 3632: 6e 67 + 3634: 2e 68 + 3636: 00 03 + 3638: 00 00 + 363a: 00 05 + 363c: 01 00 + 363e: 05 02 + 3640: 58 18 + 3642: 01 80 + 3644: 03 23 01 05 lw t1, 80(sp) + 3648: 03 03 01 09 lb t1, 144(sp) + 364c: 00 00 + 364e: 01 03 + 3650: 00 09 + 3652: 00 00 + 3654: 01 05 + 3656: 0d 03 + 3658: 00 09 + 365a: 00 00 + 365c: 01 05 + 365e: 03 03 01 09 lb t1, 144(sp) + 3662: 00 00 + 3664: 01 03 + 3666: 00 09 + 3668: 00 00 + 366a: 01 03 + 366c: 00 09 + 366e: 00 00 + 3670: 01 03 + 3672: 00 09 + 3674: 00 00 + 3676: 01 03 + 3678: 01 09 + 367a: 00 00 + 367c: 01 03 + 367e: 00 09 + 3680: 00 00 + 3682: 01 03 + 3684: 00 09 + 3686: 00 00 + 3688: 01 03 + 368a: 00 09 + 368c: 00 00 + 368e: 01 03 + 3690: 01 09 + 3692: 00 00 + 3694: 01 03 + 3696: 02 09 + 3698: 00 00 + 369a: 01 03 + 369c: 00 09 + 369e: 00 00 + 36a0: 01 05 + 36a2: 01 06 + 36a4: 03 7a 09 00 + 36a8: 00 01 + 36aa: 05 03 + 36ac: 03 06 09 24 lb a2, 576(s2) + 36b0: 00 01 + 36b2: 06 03 + 36b4: 00 09 + 36b6: 04 00 + 36b8: 01 03 + 36ba: 01 09 + 36bc: 00 00 + 36be: 01 03 + 36c0: 00 09 + 36c2: 00 00 + 36c4: 01 03 + 36c6: 00 09 + 36c8: 00 00 + 36ca: 01 03 + 36cc: 00 09 + 36ce: 00 00 + 36d0: 01 03 + 36d2: 00 09 + 36d4: 00 00 + 36d6: 01 03 + 36d8: 00 09 + 36da: 00 00 + 36dc: 01 03 + 36de: 00 09 + 36e0: 00 00 + 36e2: 01 06 + 36e4: 03 01 09 1c lb sp, 448(s2) + 36e8: 00 01 + 36ea: 06 03 + 36ec: 7f 09 08 00 + 36f0: 01 03 + 36f2: 00 09 + 36f4: 00 00 + 36f6: 01 03 + 36f8: 00 09 + 36fa: 00 00 + 36fc: 01 03 + 36fe: 01 09 + 3700: 00 00 + 3702: 01 03 + 3704: 00 09 + 3706: 00 00 + 3708: 01 03 + 370a: 00 09 + 370c: 00 00 + 370e: 01 03 + 3710: 00 09 + 3712: 00 00 + 3714: 01 03 + 3716: 00 09 + 3718: 00 00 + 371a: 01 03 + 371c: 00 09 + 371e: 00 00 + 3720: 01 03 + 3722: 00 09 + 3724: 00 00 + 3726: 01 03 + 3728: 00 09 + 372a: 04 00 + 372c: 01 03 + 372e: 00 09 + 3730: 04 00 + 3732: 01 03 + 3734: 00 09 + 3736: 04 00 + 3738: 01 03 + 373a: 01 09 + 373c: 00 00 + 373e: 01 03 + 3740: 00 09 + 3742: 00 00 + 3744: 01 03 + 3746: 00 09 + 3748: 00 00 + 374a: 01 03 + 374c: 00 09 + 374e: 00 00 + 3750: 01 03 + 3752: 00 09 + 3754: 00 00 + 3756: 01 00 + 3758: 02 04 + 375a: 14 06 + 375c: 03 00 09 04 lb zero, 64(s2) + 3760: 00 01 + 3762: 03 00 09 10 lb zero, 256(s2) + 3766: 00 01 + 3768: 00 02 + 376a: 04 17 + 376c: 03 00 09 08 lb zero, 128(s2) + 3770: 00 01 + 3772: 00 02 + 3774: 04 18 + 3776: 03 00 09 04 lb zero, 64(s2) + 377a: 00 01 + 377c: 00 02 + 377e: 04 4e + 3780: 06 03 + 3782: 00 09 + 3784: 10 00 + 3786: 01 00 + 3788: 02 04 + 378a: 4e 03 + 378c: 00 09 + 378e: 00 00 + 3790: 01 00 + 3792: 02 04 + 3794: 4e 03 + 3796: 00 09 + 3798: 00 00 + 379a: 01 00 + 379c: 02 04 + 379e: 4e 03 + 37a0: 00 09 + 37a2: 00 00 + 37a4: 01 00 + 37a6: 02 04 + 37a8: 4e 03 + 37aa: 00 09 + 37ac: 00 00 + 37ae: 01 00 + 37b0: 02 04 + 37b2: 4e 03 + 37b4: 00 09 + 37b6: 00 00 + 37b8: 01 00 + 37ba: 02 04 + 37bc: 4e 03 + 37be: 00 09 + 37c0: 00 00 + 37c2: 01 00 + 37c4: 02 04 + 37c6: 4e 03 + 37c8: 00 09 + 37ca: 00 00 + 37cc: 01 00 + 37ce: 02 04 + 37d0: 4e 03 + 37d2: 00 09 + 37d4: 00 00 + 37d6: 01 00 + 37d8: 02 04 + 37da: 4e 03 + 37dc: 00 09 + 37de: 00 00 + 37e0: 01 00 + 37e2: 02 04 + 37e4: 50 06 + 37e6: 03 00 09 08 lb zero, 128(s2) + 37ea: 00 01 + 37ec: 00 02 + 37ee: 04 52 + 37f0: 03 00 09 04 lb zero, 64(s2) + 37f4: 00 01 + 37f6: 00 02 + 37f8: 04 54 + 37fa: 03 00 09 04 lb zero, 64(s2) + 37fe: 00 01 + 3800: 00 02 + 3802: 04 56 + 3804: 03 00 09 04 lb zero, 64(s2) + 3808: 00 01 + 380a: 00 02 + 380c: 04 58 + 380e: 03 00 09 04 lb zero, 64(s2) + 3812: 00 01 + 3814: 00 02 + 3816: 04 59 + 3818: 03 00 09 04 lb zero, 64(s2) + 381c: 00 01 + 381e: 00 02 + 3820: 04 5c + 3822: 03 00 09 04 lb zero, 64(s2) + 3826: 00 01 + 3828: 05 01 + 382a: 03 04 09 10 lb s0, 256(s2) + 382e: 00 01 + 3830: 05 03 + 3832: 00 02 + 3834: 04 01 + 3836: 06 03 + 3838: 7d 09 + 383a: 08 00 + 383c: 01 06 + 383e: 03 7f 09 08 + 3842: 00 01 + 3844: 06 03 + 3846: 00 09 + 3848: 08 00 + 384a: 01 03 + 384c: 00 09 + 384e: 00 00 + 3850: 01 03 + 3852: 00 09 + 3854: 00 00 + 3856: 01 03 + 3858: 00 09 + 385a: 00 00 + 385c: 01 03 + 385e: 00 09 + 3860: 00 00 + 3862: 01 03 + 3864: 00 09 + 3866: 00 00 + 3868: 01 03 + 386a: 00 09 + 386c: 00 00 + 386e: 01 00 + 3870: 02 04 + 3872: 34 03 + 3874: 00 09 + 3876: 0c 00 + 3878: 01 00 + 387a: 02 04 + 387c: 36 06 + 387e: 03 00 09 10 lb zero, 256(s2) + 3882: 00 01 + 3884: 00 02 + 3886: 04 3c + 3888: 06 03 + 388a: 00 09 + 388c: 0c 00 + 388e: 01 00 + 3890: 02 04 + 3892: 3c 03 + 3894: 00 09 + 3896: 00 00 + 3898: 01 00 + 389a: 02 04 + 389c: 3d 03 + 389e: 00 09 + 38a0: 10 00 + 38a2: 01 00 + 38a4: 02 04 + 38a6: 3f 06 03 00 + 38aa: 09 10 + 38ac: 00 01 + 38ae: 03 00 09 0c lb zero, 192(s2) + 38b2: 00 01 + 38b4: 09 08 + 38b6: 00 00 + 38b8: 01 01 + 38ba: 94 03 + 38bc: 00 00 + 38be: 03 00 a3 00 lb zero, 10(t1) + 38c2: 00 00 + 38c4: 01 01 + 38c6: fb 0e 0d 00 + 38ca: 01 01 + 38cc: 01 01 + 38ce: 00 00 + 38d0: 00 01 + 38d2: 00 00 + 38d4: 01 2e + 38d6: 2e 2f + 38d8: 2e 2e + 38da: 2f 2e 2e 2f + 38de: 2e 2e + 38e0: 2f 72 69 73 + 38e4: 63 76 2d 67 bgeu s10, s2, 1644 + 38e8: 63 63 2f 6c bltu t5, sp, 1734 + 38ec: 69 62 + 38ee: 67 63 63 2f + 38f2: 73 6f 66 74 csrrsi t5, 1862, 12 + 38f6: 2d 66 + 38f8: 70 00 + 38fa: 2e 00 + 38fc: 2e 2e + 38fe: 2f 2e 2e 2f + 3902: 2e 2e + 3904: 2f 2e 2e 2f + 3908: 72 69 + 390a: 73 63 76 2d csrrsi t1, 727, 12 + 390e: 67 63 63 2f + 3912: 6c 69 + 3914: 62 67 + 3916: 63 63 2f 2e bltu t5, sp, 742 + 391a: 2e 2f + 391c: 69 6e + 391e: 63 6c 75 64 bltu a0, t2, 1624 + 3922: 65 00 + 3924: 00 67 + 3926: 65 74 + 3928: 66 32 + 392a: 2e 63 + 392c: 00 01 + 392e: 00 00 + 3930: 73 66 70 2d csrrsi a2, 727, 0 + 3934: 6d 61 + 3936: 63 68 69 6e bltu s2, t1, 1776 + 393a: 65 2e + 393c: 68 00 + 393e: 02 00 + 3940: 00 73 + 3942: 6f 66 74 2d jal a2, 289494 + 3946: 66 70 + 3948: 2e 68 + 394a: 00 01 + 394c: 00 00 + 394e: 71 75 + 3950: 61 64 + 3952: 2e 68 + 3954: 00 01 + 3956: 00 00 + 3958: 6c 6f + 395a: 6e 67 + 395c: 6c 6f + 395e: 6e 67 + 3960: 2e 68 + 3962: 00 03 + 3964: 00 00 + 3966: 00 05 + 3968: 01 00 + 396a: 05 02 + 396c: 84 19 + 396e: 01 80 + 3970: 03 23 01 05 lw t1, 80(sp) + 3974: 03 03 01 09 lb t1, 144(sp) + 3978: 00 00 + 397a: 01 03 + 397c: 00 09 + 397e: 00 00 + 3980: 01 05 + 3982: 0d 03 + 3984: 00 09 + 3986: 00 00 + 3988: 01 05 + 398a: 03 03 01 09 lb t1, 144(sp) + 398e: 00 00 + 3990: 01 03 + 3992: 00 09 + 3994: 00 00 + 3996: 01 03 + 3998: 00 09 + 399a: 00 00 + 399c: 01 03 + 399e: 00 09 + 39a0: 00 00 + 39a2: 01 03 + 39a4: 01 09 + 39a6: 00 00 + 39a8: 01 03 + 39aa: 00 09 + 39ac: 00 00 + 39ae: 01 03 + 39b0: 00 09 + 39b2: 00 00 + 39b4: 01 03 + 39b6: 00 09 + 39b8: 00 00 + 39ba: 01 03 + 39bc: 01 09 + 39be: 00 00 + 39c0: 01 03 + 39c2: 02 09 + 39c4: 00 00 + 39c6: 01 03 + 39c8: 00 09 + 39ca: 00 00 + 39cc: 01 05 + 39ce: 01 06 + 39d0: 03 7a 09 00 + 39d4: 00 01 + 39d6: 05 03 + 39d8: 03 06 09 24 lb a2, 576(s2) + 39dc: 00 01 + 39de: 06 03 + 39e0: 00 09 + 39e2: 04 00 + 39e4: 01 03 + 39e6: 01 09 + 39e8: 00 00 + 39ea: 01 03 + 39ec: 00 09 + 39ee: 00 00 + 39f0: 01 03 + 39f2: 00 09 + 39f4: 00 00 + 39f6: 01 03 + 39f8: 00 09 + 39fa: 00 00 + 39fc: 01 03 + 39fe: 00 09 + 3a00: 00 00 + 3a02: 01 03 + 3a04: 00 09 + 3a06: 00 00 + 3a08: 01 03 + 3a0a: 00 09 + 3a0c: 00 00 + 3a0e: 01 06 + 3a10: 03 01 09 10 lb sp, 256(s2) + 3a14: 00 01 + 3a16: 03 7f 09 08 + 3a1a: 00 01 + 3a1c: 06 03 + 3a1e: 00 09 + 3a20: 08 00 + 3a22: 01 03 + 3a24: 00 09 + 3a26: 00 00 + 3a28: 01 03 + 3a2a: 00 09 + 3a2c: 04 00 + 3a2e: 01 03 + 3a30: 01 09 + 3a32: 00 00 + 3a34: 01 03 + 3a36: 00 09 + 3a38: 00 00 + 3a3a: 01 03 + 3a3c: 00 09 + 3a3e: 00 00 + 3a40: 01 03 + 3a42: 00 09 + 3a44: 00 00 + 3a46: 01 03 + 3a48: 00 09 + 3a4a: 00 00 + 3a4c: 01 03 + 3a4e: 00 09 + 3a50: 00 00 + 3a52: 01 03 + 3a54: 00 09 + 3a56: 00 00 + 3a58: 01 03 + 3a5a: 00 09 + 3a5c: 04 00 + 3a5e: 01 03 + 3a60: 00 09 + 3a62: 04 00 + 3a64: 01 03 + 3a66: 00 09 + 3a68: 04 00 + 3a6a: 01 03 + 3a6c: 01 09 + 3a6e: 00 00 + 3a70: 01 03 + 3a72: 00 09 + 3a74: 00 00 + 3a76: 01 03 + 3a78: 00 09 + 3a7a: 00 00 + 3a7c: 01 03 + 3a7e: 00 09 + 3a80: 00 00 + 3a82: 01 03 + 3a84: 00 09 + 3a86: 00 00 + 3a88: 01 00 + 3a8a: 02 04 + 3a8c: 14 06 + 3a8e: 03 00 09 04 lb zero, 64(s2) + 3a92: 00 01 + 3a94: 00 02 + 3a96: 04 01 + 3a98: 06 03 + 3a9a: 01 09 + 3a9c: 10 00 + 3a9e: 01 00 + 3aa0: 02 04 + 3aa2: 17 06 03 7f auipc a2, 520240 + 3aa6: 09 0c + 3aa8: 00 01 + 3aaa: 00 02 + 3aac: 04 18 + 3aae: 03 00 09 04 lb zero, 64(s2) + 3ab2: 00 01 + 3ab4: 00 02 + 3ab6: 04 3e + 3ab8: 06 03 + 3aba: 00 09 + 3abc: 10 00 + 3abe: 01 00 + 3ac0: 02 04 + 3ac2: 3e 03 + 3ac4: 00 09 + 3ac6: 00 00 + 3ac8: 01 00 + 3aca: 02 04 + 3acc: 3e 03 + 3ace: 00 09 + 3ad0: 00 00 + 3ad2: 01 00 + 3ad4: 02 04 + 3ad6: 3e 03 + 3ad8: 00 09 + 3ada: 00 00 + 3adc: 01 00 + 3ade: 02 04 + 3ae0: 3e 03 + 3ae2: 00 09 + 3ae4: 00 00 + 3ae6: 01 00 + 3ae8: 02 04 + 3aea: 3e 03 + 3aec: 00 09 + 3aee: 00 00 + 3af0: 01 00 + 3af2: 02 04 + 3af4: 3e 03 + 3af6: 00 09 + 3af8: 00 00 + 3afa: 01 00 + 3afc: 02 04 + 3afe: 3e 03 + 3b00: 00 09 + 3b02: 00 00 + 3b04: 01 00 + 3b06: 02 04 + 3b08: 3e 03 + 3b0a: 00 09 + 3b0c: 00 00 + 3b0e: 01 00 + 3b10: 02 04 + 3b12: 3e 03 + 3b14: 00 09 + 3b16: 00 00 + 3b18: 01 00 + 3b1a: 02 04 + 3b1c: 3e 03 + 3b1e: 00 09 + 3b20: 00 00 + 3b22: 01 00 + 3b24: 02 04 + 3b26: 3e 03 + 3b28: 00 09 + 3b2a: 00 00 + 3b2c: 01 00 + 3b2e: 02 04 + 3b30: 3f 06 03 00 + 3b34: 09 04 + 3b36: 00 01 + 3b38: 00 02 + 3b3a: 04 3f + 3b3c: 06 03 + 3b3e: 00 09 + 3b40: 10 00 + 3b42: 01 00 + 3b44: 02 04 + 3b46: 45 06 + 3b48: 03 00 09 04 lb zero, 64(s2) + 3b4c: 00 01 + 3b4e: 06 03 + 3b50: 00 09 + 3b52: 10 00 + 3b54: 01 00 + 3b56: 02 04 + 3b58: 50 03 + 3b5a: 00 09 + 3b5c: 04 00 + 3b5e: 01 00 + 3b60: 02 04 + 3b62: 50 03 + 3b64: 00 09 + 3b66: 00 00 + 3b68: 01 06 + 3b6a: 03 00 09 08 lb zero, 128(s2) + 3b6e: 00 01 + 3b70: 05 01 + 3b72: 03 04 09 04 lb s0, 64(s2) + 3b76: 00 01 + 3b78: 05 03 + 3b7a: 03 7c 09 08 + 3b7e: 00 01 + 3b80: 00 02 + 3b82: 04 66 + 3b84: 06 03 + 3b86: 00 09 + 3b88: 08 00 + 3b8a: 01 00 + 3b8c: 03 04 92 01 lb s0, 25(tp) + 3b90: 03 00 09 04 lb zero, 64(s2) + 3b94: 00 01 + 3b96: 00 02 + 3b98: 04 6d + 3b9a: 03 00 09 08 lb zero, 128(s2) + 3b9e: 00 01 + 3ba0: 00 02 + 3ba2: 04 74 + 3ba4: 06 03 + 3ba6: 00 09 + 3ba8: 04 00 + 3baa: 01 00 + 3bac: 02 04 + 3bae: 75 03 + 3bb0: 00 09 + 3bb2: 04 00 + 3bb4: 01 00 + 3bb6: 02 04 + 3bb8: 78 03 + 3bba: 00 09 + 3bbc: 04 00 + 3bbe: 01 00 + 3bc0: 02 04 + 3bc2: 79 03 + 3bc4: 00 09 + 3bc6: 04 00 + 3bc8: 01 00 + 3bca: 02 04 + 3bcc: 7c 03 + 3bce: 00 09 + 3bd0: 04 00 + 3bd2: 01 00 + 3bd4: 02 04 + 3bd6: 7d 03 + 3bd8: 00 09 + 3bda: 04 00 + 3bdc: 01 00 + 3bde: 03 04 8c 01 lb s0, 24(s8) + 3be2: 06 03 + 3be4: 00 09 + 3be6: 04 00 + 3be8: 01 00 + 3bea: 03 04 8f 01 lb s0, 24(t5) + 3bee: 06 03 + 3bf0: 00 09 + 3bf2: 04 00 + 3bf4: 01 00 + 3bf6: 03 04 90 01 lb s0, 25(zero) + 3bfa: 03 00 09 04 lb zero, 64(s2) + 3bfe: 00 01 + 3c00: 03 00 09 04 lb zero, 64(s2) + 3c04: 00 01 + 3c06: 06 03 + 3c08: 00 09 + 3c0a: 10 00 + 3c0c: 01 03 + 3c0e: 00 09 + 3c10: 08 00 + 3c12: 01 03 + 3c14: 00 09 + 3c16: 08 00 + 3c18: 01 03 + 3c1a: 00 09 + 3c1c: 0c 00 + 3c1e: 01 03 + 3c20: 00 09 + 3c22: 04 00 + 3c24: 01 03 + 3c26: 00 09 + 3c28: 00 00 + 3c2a: 01 03 + 3c2c: 00 09 + 3c2e: 00 00 + 3c30: 01 00 + 3c32: 02 04 + 3c34: 5f 03 00 09 + 3c38: 04 00 + 3c3a: 01 00 + 3c3c: 02 04 + 3c3e: 7f 03 00 09 + 3c42: 04 00 + 3c44: 01 06 + 3c46: 03 00 09 04 lb zero, 64(s2) + 3c4a: 00 01 + 3c4c: 09 08 + 3c4e: 00 00 + 3c50: 01 01 + 3c52: 94 03 + 3c54: 00 00 + 3c56: 03 00 a3 00 lb zero, 10(t1) + 3c5a: 00 00 + 3c5c: 01 01 + 3c5e: fb 0e 0d 00 + 3c62: 01 01 + 3c64: 01 01 + 3c66: 00 00 + 3c68: 00 01 + 3c6a: 00 00 + 3c6c: 01 2e + 3c6e: 2e 2f + 3c70: 2e 2e + 3c72: 2f 2e 2e 2f + 3c76: 2e 2e + 3c78: 2f 72 69 73 + 3c7c: 63 76 2d 67 bgeu s10, s2, 1644 + 3c80: 63 63 2f 6c bltu t5, sp, 1734 + 3c84: 69 62 + 3c86: 67 63 63 2f + 3c8a: 73 6f 66 74 csrrsi t5, 1862, 12 + 3c8e: 2d 66 + 3c90: 70 00 + 3c92: 2e 00 + 3c94: 2e 2e + 3c96: 2f 2e 2e 2f + 3c9a: 2e 2e + 3c9c: 2f 2e 2e 2f + 3ca0: 72 69 + 3ca2: 73 63 76 2d csrrsi t1, 727, 12 + 3ca6: 67 63 63 2f + 3caa: 6c 69 + 3cac: 62 67 + 3cae: 63 63 2f 2e bltu t5, sp, 742 + 3cb2: 2e 2f + 3cb4: 69 6e + 3cb6: 63 6c 75 64 bltu a0, t2, 1624 + 3cba: 65 00 + 3cbc: 00 6c + 3cbe: 65 74 + 3cc0: 66 32 + 3cc2: 2e 63 + 3cc4: 00 01 + 3cc6: 00 00 + 3cc8: 73 66 70 2d csrrsi a2, 727, 0 + 3ccc: 6d 61 + 3cce: 63 68 69 6e bltu s2, t1, 1776 + 3cd2: 65 2e + 3cd4: 68 00 + 3cd6: 02 00 + 3cd8: 00 73 + 3cda: 6f 66 74 2d jal a2, 289494 + 3cde: 66 70 + 3ce0: 2e 68 + 3ce2: 00 01 + 3ce4: 00 00 + 3ce6: 71 75 + 3ce8: 61 64 + 3cea: 2e 68 + 3cec: 00 01 + 3cee: 00 00 + 3cf0: 6c 6f + 3cf2: 6e 67 + 3cf4: 6c 6f + 3cf6: 6e 67 + 3cf8: 2e 68 + 3cfa: 00 03 + 3cfc: 00 00 + 3cfe: 00 05 + 3d00: 01 00 + 3d02: 05 02 + 3d04: d0 1a + 3d06: 01 80 + 3d08: 03 23 01 05 lw t1, 80(sp) + 3d0c: 03 03 01 09 lb t1, 144(sp) + 3d10: 00 00 + 3d12: 01 03 + 3d14: 00 09 + 3d16: 00 00 + 3d18: 01 05 + 3d1a: 0d 03 + 3d1c: 00 09 + 3d1e: 00 00 + 3d20: 01 05 + 3d22: 03 03 01 09 lb t1, 144(sp) + 3d26: 00 00 + 3d28: 01 03 + 3d2a: 00 09 + 3d2c: 00 00 + 3d2e: 01 03 + 3d30: 00 09 + 3d32: 00 00 + 3d34: 01 03 + 3d36: 00 09 + 3d38: 00 00 + 3d3a: 01 03 + 3d3c: 01 09 + 3d3e: 00 00 + 3d40: 01 03 + 3d42: 00 09 + 3d44: 00 00 + 3d46: 01 03 + 3d48: 00 09 + 3d4a: 00 00 + 3d4c: 01 03 + 3d4e: 00 09 + 3d50: 00 00 + 3d52: 01 03 + 3d54: 01 09 + 3d56: 00 00 + 3d58: 01 03 + 3d5a: 02 09 + 3d5c: 00 00 + 3d5e: 01 03 + 3d60: 00 09 + 3d62: 00 00 + 3d64: 01 05 + 3d66: 01 06 + 3d68: 03 7a 09 00 + 3d6c: 00 01 + 3d6e: 05 03 + 3d70: 03 06 09 24 lb a2, 576(s2) + 3d74: 00 01 + 3d76: 06 03 + 3d78: 00 09 + 3d7a: 04 00 + 3d7c: 01 03 + 3d7e: 01 09 + 3d80: 00 00 + 3d82: 01 03 + 3d84: 00 09 + 3d86: 00 00 + 3d88: 01 03 + 3d8a: 00 09 + 3d8c: 00 00 + 3d8e: 01 03 + 3d90: 00 09 + 3d92: 00 00 + 3d94: 01 03 + 3d96: 00 09 + 3d98: 00 00 + 3d9a: 01 03 + 3d9c: 00 09 + 3d9e: 00 00 + 3da0: 01 03 + 3da2: 00 09 + 3da4: 00 00 + 3da6: 01 06 + 3da8: 03 01 09 10 lb sp, 256(s2) + 3dac: 00 01 + 3dae: 03 7f 09 08 + 3db2: 00 01 + 3db4: 06 03 + 3db6: 00 09 + 3db8: 08 00 + 3dba: 01 03 + 3dbc: 00 09 + 3dbe: 00 00 + 3dc0: 01 03 + 3dc2: 00 09 + 3dc4: 04 00 + 3dc6: 01 03 + 3dc8: 01 09 + 3dca: 00 00 + 3dcc: 01 03 + 3dce: 00 09 + 3dd0: 00 00 + 3dd2: 01 03 + 3dd4: 00 09 + 3dd6: 00 00 + 3dd8: 01 03 + 3dda: 00 09 + 3ddc: 00 00 + 3dde: 01 03 + 3de0: 00 09 + 3de2: 00 00 + 3de4: 01 03 + 3de6: 00 09 + 3de8: 00 00 + 3dea: 01 03 + 3dec: 00 09 + 3dee: 00 00 + 3df0: 01 03 + 3df2: 00 09 + 3df4: 04 00 + 3df6: 01 03 + 3df8: 00 09 + 3dfa: 04 00 + 3dfc: 01 03 + 3dfe: 00 09 + 3e00: 04 00 + 3e02: 01 03 + 3e04: 01 09 + 3e06: 00 00 + 3e08: 01 03 + 3e0a: 00 09 + 3e0c: 00 00 + 3e0e: 01 03 + 3e10: 00 09 + 3e12: 00 00 + 3e14: 01 03 + 3e16: 00 09 + 3e18: 00 00 + 3e1a: 01 03 + 3e1c: 00 09 + 3e1e: 00 00 + 3e20: 01 00 + 3e22: 02 04 + 3e24: 14 06 + 3e26: 03 00 09 04 lb zero, 64(s2) + 3e2a: 00 01 + 3e2c: 00 02 + 3e2e: 04 01 + 3e30: 06 03 + 3e32: 01 09 + 3e34: 10 00 + 3e36: 01 00 + 3e38: 02 04 + 3e3a: 17 06 03 7f auipc a2, 520240 + 3e3e: 09 0c + 3e40: 00 01 + 3e42: 00 02 + 3e44: 04 18 + 3e46: 03 00 09 04 lb zero, 64(s2) + 3e4a: 00 01 + 3e4c: 00 02 + 3e4e: 04 3e + 3e50: 06 03 + 3e52: 00 09 + 3e54: 10 00 + 3e56: 01 00 + 3e58: 02 04 + 3e5a: 3e 03 + 3e5c: 00 09 + 3e5e: 00 00 + 3e60: 01 00 + 3e62: 02 04 + 3e64: 3e 03 + 3e66: 00 09 + 3e68: 00 00 + 3e6a: 01 00 + 3e6c: 02 04 + 3e6e: 3e 03 + 3e70: 00 09 + 3e72: 00 00 + 3e74: 01 00 + 3e76: 02 04 + 3e78: 3e 03 + 3e7a: 00 09 + 3e7c: 00 00 + 3e7e: 01 00 + 3e80: 02 04 + 3e82: 3e 03 + 3e84: 00 09 + 3e86: 00 00 + 3e88: 01 00 + 3e8a: 02 04 + 3e8c: 3e 03 + 3e8e: 00 09 + 3e90: 00 00 + 3e92: 01 00 + 3e94: 02 04 + 3e96: 3e 03 + 3e98: 00 09 + 3e9a: 00 00 + 3e9c: 01 00 + 3e9e: 02 04 + 3ea0: 3e 03 + 3ea2: 00 09 + 3ea4: 00 00 + 3ea6: 01 00 + 3ea8: 02 04 + 3eaa: 3e 03 + 3eac: 00 09 + 3eae: 00 00 + 3eb0: 01 00 + 3eb2: 02 04 + 3eb4: 3e 03 + 3eb6: 00 09 + 3eb8: 00 00 + 3eba: 01 00 + 3ebc: 02 04 + 3ebe: 3e 03 + 3ec0: 00 09 + 3ec2: 00 00 + 3ec4: 01 00 + 3ec6: 02 04 + 3ec8: 3f 06 03 00 + 3ecc: 09 04 + 3ece: 00 01 + 3ed0: 00 02 + 3ed2: 04 3f + 3ed4: 06 03 + 3ed6: 00 09 + 3ed8: 10 00 + 3eda: 01 00 + 3edc: 02 04 + 3ede: 45 06 + 3ee0: 03 00 09 04 lb zero, 64(s2) + 3ee4: 00 01 + 3ee6: 06 03 + 3ee8: 00 09 + 3eea: 10 00 + 3eec: 01 00 + 3eee: 02 04 + 3ef0: 50 03 + 3ef2: 00 09 + 3ef4: 04 00 + 3ef6: 01 00 + 3ef8: 02 04 + 3efa: 50 03 + 3efc: 00 09 + 3efe: 00 00 + 3f00: 01 06 + 3f02: 03 00 09 08 lb zero, 128(s2) + 3f06: 00 01 + 3f08: 05 01 + 3f0a: 03 04 09 04 lb s0, 64(s2) + 3f0e: 00 01 + 3f10: 05 03 + 3f12: 03 7c 09 08 + 3f16: 00 01 + 3f18: 00 02 + 3f1a: 04 66 + 3f1c: 06 03 + 3f1e: 00 09 + 3f20: 08 00 + 3f22: 01 00 + 3f24: 03 04 92 01 lb s0, 25(tp) + 3f28: 03 00 09 04 lb zero, 64(s2) + 3f2c: 00 01 + 3f2e: 00 02 + 3f30: 04 6d + 3f32: 03 00 09 08 lb zero, 128(s2) + 3f36: 00 01 + 3f38: 00 02 + 3f3a: 04 74 + 3f3c: 06 03 + 3f3e: 00 09 + 3f40: 04 00 + 3f42: 01 00 + 3f44: 02 04 + 3f46: 75 03 + 3f48: 00 09 + 3f4a: 04 00 + 3f4c: 01 00 + 3f4e: 02 04 + 3f50: 78 03 + 3f52: 00 09 + 3f54: 04 00 + 3f56: 01 00 + 3f58: 02 04 + 3f5a: 79 03 + 3f5c: 00 09 + 3f5e: 04 00 + 3f60: 01 00 + 3f62: 02 04 + 3f64: 7c 03 + 3f66: 00 09 + 3f68: 04 00 + 3f6a: 01 00 + 3f6c: 02 04 + 3f6e: 7d 03 + 3f70: 00 09 + 3f72: 04 00 + 3f74: 01 00 + 3f76: 03 04 8c 01 lb s0, 24(s8) + 3f7a: 06 03 + 3f7c: 00 09 + 3f7e: 04 00 + 3f80: 01 00 + 3f82: 03 04 8f 01 lb s0, 24(t5) + 3f86: 06 03 + 3f88: 00 09 + 3f8a: 04 00 + 3f8c: 01 00 + 3f8e: 03 04 90 01 lb s0, 25(zero) + 3f92: 03 00 09 04 lb zero, 64(s2) + 3f96: 00 01 + 3f98: 03 00 09 04 lb zero, 64(s2) + 3f9c: 00 01 + 3f9e: 06 03 + 3fa0: 00 09 + 3fa2: 10 00 + 3fa4: 01 03 + 3fa6: 00 09 + 3fa8: 08 00 + 3faa: 01 03 + 3fac: 00 09 + 3fae: 08 00 + 3fb0: 01 03 + 3fb2: 00 09 + 3fb4: 0c 00 + 3fb6: 01 03 + 3fb8: 00 09 + 3fba: 04 00 + 3fbc: 01 03 + 3fbe: 00 09 + 3fc0: 00 00 + 3fc2: 01 03 + 3fc4: 00 09 + 3fc6: 00 00 + 3fc8: 01 00 + 3fca: 02 04 + 3fcc: 5f 03 00 09 + 3fd0: 04 00 + 3fd2: 01 00 + 3fd4: 02 04 + 3fd6: 7f 03 00 09 + 3fda: 04 00 + 3fdc: 01 06 + 3fde: 03 00 09 04 lb zero, 64(s2) + 3fe2: 00 01 + 3fe4: 09 08 + 3fe6: 00 00 + 3fe8: 01 01 + 3fea: 68 25 + 3fec: 00 00 + 3fee: 03 00 91 00 lb zero, 9(sp) + 3ff2: 00 00 + 3ff4: 01 01 + 3ff6: fb 0e 0d 00 + 3ffa: 01 01 + 3ffc: 01 01 + 3ffe: 00 00 + 4000: 00 01 + 4002: 00 00 + 4004: 01 2e + 4006: 2e 2f + 4008: 2e 2e + 400a: 2f 2e 2e 2f + 400e: 2e 2e + 4010: 2f 72 69 73 + 4014: 63 76 2d 67 bgeu s10, s2, 1644 + 4018: 63 63 2f 6c bltu t5, sp, 1734 + 401c: 69 62 + 401e: 67 63 63 2f + 4022: 73 6f 66 74 csrrsi t5, 1862, 12 + 4026: 2d 66 + 4028: 70 00 + 402a: 2e 2e + 402c: 2f 2e 2e 2f + 4030: 2e 2e + 4032: 2f 2e 2e 2f + 4036: 72 69 + 4038: 73 63 76 2d csrrsi t1, 727, 12 + 403c: 67 63 63 2f + 4040: 6c 69 + 4042: 62 67 + 4044: 63 63 2f 2e bltu t5, sp, 742 + 4048: 2e 2f + 404a: 69 6e + 404c: 63 6c 75 64 bltu a0, t2, 1624 + 4050: 65 00 + 4052: 00 6d + 4054: 75 6c + 4056: 74 66 + 4058: 33 2e 63 00 slt t3, t1, t1 + 405c: 01 00 + 405e: 00 73 + 4060: 6f 66 74 2d jal a2, 289494 + 4064: 66 70 + 4066: 2e 68 + 4068: 00 01 + 406a: 00 00 + 406c: 71 75 + 406e: 61 64 + 4070: 2e 68 + 4072: 00 01 + 4074: 00 00 + 4076: 6c 6f + 4078: 6e 67 + 407a: 6c 6f + 407c: 6e 67 + 407e: 2e 68 + 4080: 00 02 + 4082: 00 00 + 4084: 00 05 + 4086: 01 00 + 4088: 05 02 + 408a: 1c 1c + 408c: 01 80 + 408e: 03 23 01 05 lw t1, 80(sp) + 4092: 03 03 01 09 lb t1, 144(sp) + 4096: 00 00 + 4098: 01 03 + 409a: 00 09 + 409c: 00 00 + 409e: 01 05 + 40a0: 0d 03 + 40a2: 00 09 + 40a4: 00 00 + 40a6: 01 05 + 40a8: 03 03 01 09 lb t1, 144(sp) + 40ac: 00 00 + 40ae: 01 03 + 40b0: 00 09 + 40b2: 00 00 + 40b4: 01 03 + 40b6: 00 09 + 40b8: 00 00 + 40ba: 01 03 + 40bc: 00 09 + 40be: 00 00 + 40c0: 01 03 + 40c2: 01 09 + 40c4: 00 00 + 40c6: 01 03 + 40c8: 00 09 + 40ca: 00 00 + 40cc: 01 03 + 40ce: 00 09 + 40d0: 00 00 + 40d2: 01 03 + 40d4: 00 09 + 40d6: 00 00 + 40d8: 01 03 + 40da: 01 09 + 40dc: 00 00 + 40de: 01 03 + 40e0: 00 09 + 40e2: 00 00 + 40e4: 01 03 + 40e6: 00 09 + 40e8: 00 00 + 40ea: 01 03 + 40ec: 00 09 + 40ee: 00 00 + 40f0: 01 03 + 40f2: 01 09 + 40f4: 00 00 + 40f6: 01 03 + 40f8: 02 09 + 40fa: 00 00 + 40fc: 01 03 + 40fe: 00 09 + 4100: 00 00 + 4102: 01 05 + 4104: 01 06 + 4106: 03 79 09 00 + 410a: 00 01 + 410c: 05 03 + 410e: 03 07 09 5c lb a4, 1472(s2) + 4112: 00 01 + 4114: 06 03 + 4116: 00 09 + 4118: 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5cc8: 00 00 + 5cca: 01 00 + 5ccc: 02 04 + 5cce: 15 03 + 5cd0: 00 09 + 5cd2: 14 00 + 5cd4: 01 00 + 5cd6: 02 04 + 5cd8: 15 03 + 5cda: 00 09 + 5cdc: 00 00 + 5cde: 01 06 + 5ce0: 03 7d 09 08 + 5ce4: 00 01 + 5ce6: 00 02 + 5ce8: 04 60 + 5cea: 06 03 + 5cec: 02 09 + 5cee: 04 00 + 5cf0: 01 00 + 5cf2: 02 04 + 5cf4: 60 03 + 5cf6: 00 09 + 5cf8: 20 00 + 5cfa: 01 00 + 5cfc: 02 04 + 5cfe: 60 03 + 5d00: 00 09 + 5d02: 00 00 + 5d04: 01 00 + 5d06: 02 04 + 5d08: 64 03 + 5d0a: 00 09 + 5d0c: 00 00 + 5d0e: 01 00 + 5d10: 02 04 + 5d12: 64 03 + 5d14: 01 09 + 5d16: 00 00 + 5d18: 01 00 + 5d1a: 02 04 + 5d1c: 64 03 + 5d1e: 00 09 + 5d20: 00 00 + 5d22: 01 00 + 5d24: 02 04 + 5d26: 64 03 + 5d28: 00 09 + 5d2a: 00 00 + 5d2c: 01 06 + 5d2e: 03 00 09 08 lb zero, 128(s2) + 5d32: 00 01 + 5d34: 00 02 + 5d36: 04 03 + 5d38: 06 03 + 5d3a: 00 09 + 5d3c: 10 00 + 5d3e: 01 00 + 5d40: 02 04 + 5d42: 03 03 00 09 lb t1, 144(zero) + 5d46: 00 00 + 5d48: 01 06 + 5d4a: 03 7e 09 14 + 5d4e: 00 01 + 5d50: 00 02 + 5d52: 04 62 + 5d54: 06 03 + 5d56: 01 09 + 5d58: 04 00 + 5d5a: 01 00 + 5d5c: 02 04 + 5d5e: 62 03 + 5d60: 00 09 + 5d62: 24 00 + 5d64: 01 00 + 5d66: 02 04 + 5d68: 62 03 + 5d6a: 00 09 + 5d6c: 00 00 + 5d6e: 01 06 + 5d70: 03 00 09 04 lb zero, 64(s2) + 5d74: 00 01 + 5d76: 06 03 + 5d78: 01 09 + 5d7a: 0c 00 + 5d7c: 01 03 + 5d7e: 00 09 + 5d80: 00 00 + 5d82: 01 00 + 5d84: 02 04 + 5d86: 15 03 + 5d88: 00 09 + 5d8a: 04 00 + 5d8c: 01 00 + 5d8e: 02 04 + 5d90: 15 03 + 5d92: 00 09 + 5d94: 00 00 + 5d96: 01 00 + 5d98: 02 04 + 5d9a: 15 03 + 5d9c: 00 09 + 5d9e: 00 00 + 5da0: 01 03 + 5da2: 00 09 + 5da4: 10 00 + 5da6: 01 03 + 5da8: 00 09 + 5daa: 00 00 + 5dac: 01 00 + 5dae: 02 04 + 5db0: 09 03 + 5db2: 00 09 + 5db4: 04 00 + 5db6: 01 00 + 5db8: 02 04 + 5dba: 09 03 + 5dbc: 00 09 + 5dbe: 00 00 + 5dc0: 01 00 + 5dc2: 02 04 + 5dc4: 18 03 + 5dc6: 00 09 + 5dc8: 0c 00 + 5dca: 01 00 + 5dcc: 02 04 + 5dce: 18 03 + 5dd0: 00 09 + 5dd2: 10 00 + 5dd4: 01 00 + 5dd6: 02 04 + 5dd8: 1a 03 + 5dda: 00 09 + 5ddc: 0c 00 + 5dde: 01 00 + 5de0: 02 04 + 5de2: 1a 03 + 5de4: 00 09 + 5de6: 00 00 + 5de8: 01 00 + 5dea: 02 04 + 5dec: 1a 03 + 5dee: 00 09 + 5df0: 00 00 + 5df2: 01 00 + 5df4: 02 04 + 5df6: 1a 03 + 5df8: 00 09 + 5dfa: 00 00 + 5dfc: 01 00 + 5dfe: 02 04 + 5e00: 1a 03 + 5e02: 00 09 + 5e04: 00 00 + 5e06: 01 00 + 5e08: 02 04 + 5e0a: 1a 03 + 5e0c: 00 09 + 5e0e: 00 00 + 5e10: 01 00 + 5e12: 02 04 + 5e14: 1a 03 + 5e16: 00 09 + 5e18: 00 00 + 5e1a: 01 00 + 5e1c: 02 04 + 5e1e: 1a 03 + 5e20: 00 09 + 5e22: 00 00 + 5e24: 01 00 + 5e26: 02 04 + 5e28: 1a 03 + 5e2a: 00 09 + 5e2c: 00 00 + 5e2e: 01 00 + 5e30: 02 04 + 5e32: 22 03 + 5e34: 00 09 + 5e36: 08 00 + 5e38: 01 00 + 5e3a: 02 04 + 5e3c: 22 03 + 5e3e: 00 09 + 5e40: 1c 00 + 5e42: 01 00 + 5e44: 02 04 + 5e46: 22 03 + 5e48: 00 09 + 5e4a: 00 00 + 5e4c: 01 00 + 5e4e: 02 04 + 5e50: 23 03 00 09 sb a6, 134(zero) + 5e54: 04 00 + 5e56: 01 00 + 5e58: 02 04 + 5e5a: 23 03 00 09 sb a6, 134(zero) + 5e5e: 00 00 + 5e60: 01 00 + 5e62: 02 04 + 5e64: 23 03 00 09 sb a6, 134(zero) + 5e68: 00 00 + 5e6a: 01 00 + 5e6c: 02 04 + 5e6e: 23 03 00 09 sb a6, 134(zero) + 5e72: 00 00 + 5e74: 01 06 + 5e76: 03 00 09 0c lb zero, 192(s2) + 5e7a: 00 01 + 5e7c: 00 03 + 5e7e: 04 91 + 5e80: 01 06 + 5e82: 03 00 09 10 lb zero, 256(s2) + 5e86: 00 01 + 5e88: 00 03 + 5e8a: 04 91 + 5e8c: 01 03 + 5e8e: 00 09 + 5e90: 00 00 + 5e92: 01 00 + 5e94: 03 04 91 01 lb s0, 25(sp) + 5e98: 03 00 09 00 lb zero, 0(s2) + 5e9c: 00 01 + 5e9e: 00 03 + 5ea0: 04 91 + 5ea2: 01 03 + 5ea4: 00 09 + 5ea6: 00 00 + 5ea8: 01 00 + 5eaa: 03 04 91 01 lb s0, 25(sp) + 5eae: 03 00 09 20 lb zero, 512(s2) + 5eb2: 00 01 + 5eb4: 00 03 + 5eb6: 04 91 + 5eb8: 01 03 + 5eba: 00 09 + 5ebc: 04 00 + 5ebe: 01 00 + 5ec0: 03 04 91 01 lb s0, 25(sp) + 5ec4: 03 00 09 04 lb zero, 64(s2) + 5ec8: 00 01 + 5eca: 00 03 + 5ecc: 04 91 + 5ece: 01 03 + 5ed0: 00 09 + 5ed2: 00 00 + 5ed4: 01 00 + 5ed6: 03 04 91 01 lb s0, 25(sp) + 5eda: 03 00 09 00 lb zero, 0(s2) + 5ede: 00 01 + 5ee0: 00 03 + 5ee2: 04 91 + 5ee4: 01 03 + 5ee6: 00 09 + 5ee8: 00 00 + 5eea: 01 00 + 5eec: 03 04 91 01 lb s0, 25(sp) + 5ef0: 03 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5f7a: 33 03 00 09 + 5f7e: 18 00 + 5f80: 01 00 + 5f82: 02 04 + 5f84: 33 03 00 09 + 5f88: 00 00 + 5f8a: 01 03 + 5f8c: 00 09 + 5f8e: 08 00 + 5f90: 01 00 + 5f92: 02 04 + 5f94: 31 03 + 5f96: 00 09 + 5f98: 04 00 + 5f9a: 01 00 + 5f9c: 02 04 + 5f9e: 31 03 + 5fa0: 00 09 + 5fa2: 00 00 + 5fa4: 01 03 + 5fa6: 00 09 + 5fa8: 20 00 + 5faa: 01 00 + 5fac: 02 04 + 5fae: 07 03 00 09 + 5fb2: 08 00 + 5fb4: 01 00 + 5fb6: 02 04 + 5fb8: 07 03 00 09 + 5fbc: 00 00 + 5fbe: 01 00 + 5fc0: 02 04 + 5fc2: 34 03 + 5fc4: 00 09 + 5fc6: 08 00 + 5fc8: 01 00 + 5fca: 02 04 + 5fcc: 34 03 + 5fce: 00 09 + 5fd0: 00 00 + 5fd2: 01 00 + 5fd4: 02 04 + 5fd6: 34 03 + 5fd8: 00 09 + 5fda: 00 00 + 5fdc: 01 00 + 5fde: 02 04 + 5fe0: 34 03 + 5fe2: 00 09 + 5fe4: 00 00 + 5fe6: 01 00 + 5fe8: 02 04 + 5fea: 34 03 + 5fec: 00 09 + 5fee: 00 00 + 5ff0: 01 00 + 5ff2: 02 04 + 5ff4: 34 03 + 5ff6: 00 09 + 5ff8: 14 00 + 5ffa: 01 00 + 5ffc: 02 04 + 5ffe: 34 03 + 6000: 00 09 + 6002: 00 00 + 6004: 01 00 + 6006: 02 04 + 6008: 34 03 + 600a: 00 09 + 600c: 00 00 + 600e: 01 00 + 6010: 02 04 + 6012: 34 03 + 6014: 00 09 + 6016: 00 00 + 6018: 01 00 + 601a: 02 04 + 601c: 36 03 + 601e: 00 09 + 6020: 04 00 + 6022: 01 00 + 6024: 02 04 + 6026: 36 03 + 6028: 00 09 + 602a: 08 00 + 602c: 01 03 + 602e: 00 09 + 6030: 10 00 + 6032: 01 03 + 6034: 00 09 + 6036: 00 00 + 6038: 01 00 + 603a: 02 04 + 603c: 38 03 + 603e: 00 09 + 6040: 0c 00 + 6042: 01 00 + 6044: 02 04 + 6046: 38 03 + 6048: 00 09 + 604a: 00 00 + 604c: 01 00 + 604e: 02 04 + 6050: 38 03 + 6052: 00 09 + 6054: 00 00 + 6056: 01 00 + 6058: 02 04 + 605a: 38 03 + 605c: 00 09 + 605e: 08 00 + 6060: 01 00 + 6062: 02 04 + 6064: 38 03 + 6066: 00 09 + 6068: 00 00 + 606a: 01 00 + 606c: 02 04 + 606e: 43 03 00 09 fmadd.s ft6, ft0, fa6, ft1, rne + 6072: 00 00 + 6074: 01 00 + 6076: 02 04 + 6078: 43 03 00 09 fmadd.s ft6, ft0, fa6, ft1, rne + 607c: 00 00 + 607e: 01 00 + 6080: 02 04 + 6082: 43 03 00 09 fmadd.s ft6, ft0, fa6, ft1, rne + 6086: 08 00 + 6088: 01 00 + 608a: 02 04 + 608c: 43 03 00 09 fmadd.s ft6, ft0, fa6, ft1, rne + 6090: 00 00 + 6092: 01 00 + 6094: 02 04 + 6096: 43 03 00 09 fmadd.s ft6, ft0, fa6, ft1, rne + 609a: 08 00 + 609c: 01 03 + 609e: 00 09 + 60a0: 08 00 + 60a2: 01 03 + 60a4: 00 09 + 60a6: 00 00 + 60a8: 01 00 + 60aa: 02 04 + 60ac: 43 03 00 09 fmadd.s ft6, ft0, fa6, ft1, rne + 60b0: 04 00 + 60b2: 01 00 + 60b4: 02 04 + 60b6: 43 03 00 09 fmadd.s ft6, ft0, fa6, ft1, rne + 60ba: 00 00 + 60bc: 01 00 + 60be: 02 04 + 60c0: 43 03 00 09 fmadd.s ft6, ft0, fa6, ft1, rne + 60c4: 00 00 + 60c6: 01 03 + 60c8: 00 09 + 60ca: 0c 00 + 60cc: 01 03 + 60ce: 00 09 + 60d0: 00 00 + 60d2: 01 00 + 60d4: 02 04 + 60d6: 37 03 00 09 lui t1, 36864 + 60da: 04 00 + 60dc: 01 00 + 60de: 02 04 + 60e0: 37 03 00 09 lui t1, 36864 + 60e4: 00 00 + 60e6: 01 00 + 60e8: 02 04 + 60ea: 35 03 + 60ec: 00 09 + 60ee: 0c 00 + 60f0: 01 00 + 60f2: 02 04 + 60f4: 35 03 + 60f6: 00 09 + 60f8: 08 00 + 60fa: 01 00 + 60fc: 02 04 + 60fe: 47 03 00 09 fmsub.s ft6, ft0, fa6, ft1, rne + 6102: 08 00 + 6104: 01 00 + 6106: 02 04 + 6108: 47 03 00 09 fmsub.s ft6, ft0, fa6, ft1, rne + 610c: 00 00 + 610e: 01 00 + 6110: 02 04 + 6112: 47 03 00 09 fmsub.s ft6, ft0, fa6, ft1, rne + 6116: 00 00 + 6118: 01 00 + 611a: 02 04 + 611c: 47 03 00 09 fmsub.s ft6, ft0, fa6, ft1, rne + 6120: 00 00 + 6122: 01 00 + 6124: 02 04 + 6126: 47 03 00 09 fmsub.s ft6, ft0, fa6, ft1, rne + 612a: 00 00 + 612c: 01 00 + 612e: 02 04 + 6130: 47 03 00 09 fmsub.s ft6, ft0, fa6, ft1, rne + 6134: 00 00 + 6136: 01 00 + 6138: 02 04 + 613a: 47 03 00 09 fmsub.s ft6, ft0, fa6, ft1, rne + 613e: 00 00 + 6140: 01 00 + 6142: 02 04 + 6144: 47 03 00 09 fmsub.s ft6, ft0, fa6, ft1, rne + 6148: 04 00 + 614a: 01 00 + 614c: 02 04 + 614e: 47 03 00 09 fmsub.s ft6, ft0, fa6, ft1, rne + 6152: 00 00 + 6154: 01 00 + 6156: 02 04 + 6158: 47 03 00 09 fmsub.s ft6, ft0, fa6, ft1, rne + 615c: 00 00 + 615e: 01 00 + 6160: 02 04 + 6162: 49 03 + 6164: 00 09 + 6166: 08 00 + 6168: 01 00 + 616a: 02 04 + 616c: 4c 03 + 616e: 00 09 + 6170: 04 00 + 6172: 01 06 + 6174: 03 00 09 0c lb zero, 192(s2) + 6178: 00 01 + 617a: 00 02 + 617c: 04 51 + 617e: 06 03 + 6180: 00 09 + 6182: 10 00 + 6184: 01 00 + 6186: 02 04 + 6188: 51 03 + 618a: 00 09 + 618c: 14 00 + 618e: 01 00 + 6190: 02 04 + 6192: 51 03 + 6194: 00 09 + 6196: 00 00 + 6198: 01 00 + 619a: 02 04 + 619c: 4b 03 00 09 fnmsub.s ft6, ft0, fa6, ft1, rne + 61a0: 1c 00 + 61a2: 01 00 + 61a4: 02 04 + 61a6: 4b 03 00 09 fnmsub.s ft6, ft0, fa6, ft1, rne + 61aa: 18 00 + 61ac: 01 00 + 61ae: 02 04 + 61b0: 4e 06 + 61b2: 03 00 09 04 lb zero, 64(s2) + 61b6: 00 01 + 61b8: 00 02 + 61ba: 04 4e + 61bc: 06 03 + 61be: 00 09 + 61c0: 14 00 + 61c2: 01 00 + 61c4: 02 04 + 61c6: 4e 03 + 61c8: 00 09 + 61ca: 08 00 + 61cc: 01 00 + 61ce: 02 04 + 61d0: 52 03 + 61d2: 00 09 + 61d4: 14 00 + 61d6: 01 00 + 61d8: 02 04 + 61da: 55 06 + 61dc: 03 00 09 08 lb zero, 128(s2) + 61e0: 00 01 + 61e2: 00 02 + 61e4: 04 55 + 61e6: 06 03 + 61e8: 00 09 + 61ea: 18 00 + 61ec: 01 00 + 61ee: 02 04 + 61f0: 57 06 03 00 + 61f4: 09 08 + 61f6: 00 01 + 61f8: 00 02 + 61fa: 04 54 + 61fc: 06 03 + 61fe: 00 09 + 6200: 08 00 + 6202: 01 00 + 6204: 02 04 + 6206: 54 03 + 6208: 00 09 + 620a: 28 00 + 620c: 01 00 + 620e: 02 04 + 6210: 58 03 + 6212: 00 09 + 6214: 04 00 + 6216: 01 00 + 6218: 02 04 + 621a: 58 03 + 621c: 00 09 + 621e: 10 00 + 6220: 01 00 + 6222: 02 04 + 6224: 57 03 00 09 + 6228: 04 00 + 622a: 01 00 + 622c: 02 04 + 622e: 59 03 + 6230: 00 09 + 6232: 04 00 + 6234: 01 00 + 6236: 02 04 + 6238: 59 03 + 623a: 00 09 + 623c: 00 00 + 623e: 01 00 + 6240: 02 04 + 6242: 59 03 + 6244: 00 09 + 6246: 00 00 + 6248: 01 00 + 624a: 02 04 + 624c: 59 03 + 624e: 00 09 + 6250: 10 00 + 6252: 01 00 + 6254: 02 04 + 6256: 59 03 + 6258: 00 09 + 625a: 00 00 + 625c: 01 00 + 625e: 02 04 + 6260: 59 03 + 6262: 00 09 + 6264: 00 00 + 6266: 01 00 + 6268: 02 04 + 626a: 5a 03 + 626c: 00 09 + 626e: 10 00 + 6270: 01 00 + 6272: 02 04 + 6274: 5a 03 + 6276: 00 09 + 6278: 04 00 + 627a: 01 03 + 627c: 00 09 + 627e: 10 00 + 6280: 01 03 + 6282: 00 09 + 6284: 00 00 + 6286: 01 00 + 6288: 02 04 + 628a: 5c 03 + 628c: 00 09 + 628e: 08 00 + 6290: 01 00 + 6292: 02 04 + 6294: 5c 03 + 6296: 00 09 + 6298: 00 00 + 629a: 01 00 + 629c: 02 04 + 629e: 5c 03 + 62a0: 00 09 + 62a2: 00 00 + 62a4: 01 00 + 62a6: 02 04 + 62a8: 5c 03 + 62aa: 00 09 + 62ac: 10 00 + 62ae: 01 00 + 62b0: 02 04 + 62b2: 5c 03 + 62b4: 00 09 + 62b6: 0c 00 + 62b8: 01 00 + 62ba: 02 04 + 62bc: 5c 03 + 62be: 00 09 + 62c0: 00 00 + 62c2: 01 00 + 62c4: 02 04 + 62c6: 5c 03 + 62c8: 00 09 + 62ca: 0c 00 + 62cc: 01 00 + 62ce: 02 04 + 62d0: 5c 03 + 62d2: 00 09 + 62d4: 04 00 + 62d6: 01 00 + 62d8: 02 04 + 62da: 67 06 03 00 jalr a2, t1 + 62de: 09 04 + 62e0: 00 01 + 62e2: 00 02 + 62e4: 04 5b + 62e6: 06 03 + 62e8: 00 09 + 62ea: 04 00 + 62ec: 01 00 + 62ee: 02 04 + 62f0: 5b 03 00 09 + 62f4: 00 00 + 62f6: 01 00 + 62f8: 02 04 + 62fa: 6a 03 + 62fc: 00 09 + 62fe: 0c 00 + 6300: 01 00 + 6302: 02 04 + 6304: 6a 03 + 6306: 00 09 + 6308: 00 00 + 630a: 01 00 + 630c: 02 04 + 630e: 6a 03 + 6310: 00 09 + 6312: 10 00 + 6314: 01 00 + 6316: 02 04 + 6318: 6a 03 + 631a: 00 09 + 631c: 04 00 + 631e: 01 00 + 6320: 02 04 + 6322: 6a 03 + 6324: 00 09 + 6326: 00 00 + 6328: 01 06 + 632a: 03 00 09 04 lb zero, 64(s2) + 632e: 00 01 + 6330: 06 03 + 6332: 00 09 + 6334: 08 00 + 6336: 01 03 + 6338: 00 09 + 633a: 00 00 + 633c: 01 00 + 633e: 02 04 + 6340: 62 03 + 6342: 00 09 + 6344: 04 00 + 6346: 01 00 + 6348: 02 04 + 634a: 62 03 + 634c: 00 09 + 634e: 00 00 + 6350: 01 00 + 6352: 02 04 + 6354: 62 03 + 6356: 00 09 + 6358: 00 00 + 635a: 01 00 + 635c: 02 04 + 635e: 62 03 + 6360: 00 09 + 6362: 10 00 + 6364: 01 00 + 6366: 02 04 + 6368: 62 03 + 636a: 00 09 + 636c: 0c 00 + 636e: 01 00 + 6370: 02 04 + 6372: 62 03 + 6374: 00 09 + 6376: 00 00 + 6378: 01 00 + 637a: 02 04 + 637c: 62 03 + 637e: 00 09 + 6380: 0c 00 + 6382: 01 00 + 6384: 02 04 + 6386: 62 03 + 6388: 00 09 + 638a: 04 00 + 638c: 01 03 + 638e: 00 09 + 6390: 08 00 + 6392: 01 03 + 6394: 00 09 + 6396: 00 00 + 6398: 01 00 + 639a: 02 04 + 639c: 67 03 00 09 jalr t1, 144(zero) + 63a0: 04 00 + 63a2: 01 00 + 63a4: 02 04 + 63a6: 67 03 00 09 jalr t1, 144(zero) + 63aa: 00 00 + 63ac: 01 00 + 63ae: 02 04 + 63b0: 67 03 00 09 jalr t1, 144(zero) + 63b4: 00 00 + 63b6: 01 00 + 63b8: 02 04 + 63ba: 67 03 00 09 jalr t1, 144(zero) + 63be: 14 00 + 63c0: 01 00 + 63c2: 02 04 + 63c4: 67 03 00 09 jalr t1, 144(zero) + 63c8: 0c 00 + 63ca: 01 00 + 63cc: 02 04 + 63ce: 67 03 00 09 jalr t1, 144(zero) + 63d2: 00 00 + 63d4: 01 00 + 63d6: 02 04 + 63d8: 67 03 00 09 jalr t1, 144(zero) + 63dc: 08 00 + 63de: 01 00 + 63e0: 02 04 + 63e2: 67 03 00 09 jalr t1, 144(zero) + 63e6: 04 00 + 63e8: 01 00 + 63ea: 02 04 + 63ec: 74 03 + 63ee: 00 09 + 63f0: 10 00 + 63f2: 01 00 + 63f4: 02 04 + 63f6: 74 03 + 63f8: 00 09 + 63fa: 1c 00 + 63fc: 01 00 + 63fe: 02 04 + 6400: 74 03 + 6402: 00 09 + 6404: 00 00 + 6406: 01 00 + 6408: 02 04 + 640a: 75 03 + 640c: 00 09 + 640e: 04 00 + 6410: 01 00 + 6412: 02 04 + 6414: 75 03 + 6416: 00 09 + 6418: 0c 00 + 641a: 01 00 + 641c: 02 04 + 641e: 75 03 + 6420: 00 09 + 6422: 00 00 + 6424: 01 00 + 6426: 02 04 + 6428: 75 03 + 642a: 00 09 + 642c: 00 00 + 642e: 01 00 + 6430: 02 04 + 6432: 7a 06 + 6434: 03 00 09 04 lb zero, 64(s2) + 6438: 00 01 + 643a: 03 00 09 08 lb zero, 128(s2) + 643e: 00 01 + 6440: 00 02 + 6442: 04 7b + 6444: 06 03 + 6446: 00 09 + 6448: 04 00 + 644a: 01 00 + 644c: 02 04 + 644e: 48 03 + 6450: 00 09 + 6452: 08 00 + 6454: 01 00 + 6456: 02 04 + 6458: 48 03 + 645a: 00 09 + 645c: 00 00 + 645e: 01 00 + 6460: 02 04 + 6462: 7c 03 + 6464: 00 09 + 6466: 20 00 + 6468: 01 00 + 646a: 02 04 + 646c: 7c 03 + 646e: 00 09 + 6470: 10 00 + 6472: 01 00 + 6474: 02 04 + 6476: 7c 03 + 6478: 00 09 + 647a: 00 00 + 647c: 01 00 + 647e: 02 04 + 6480: 7c 03 + 6482: 00 09 + 6484: 00 00 + 6486: 01 00 + 6488: 02 04 + 648a: 7c 03 + 648c: 00 09 + 648e: 08 00 + 6490: 01 06 + 6492: 03 00 09 0c lb zero, 192(s2) + 6496: 00 01 + 6498: 00 02 + 649a: 04 7f + 649c: 06 03 + 649e: 00 09 + 64a0: 08 00 + 64a2: 01 00 + 64a4: 02 04 + 64a6: 7f 03 00 09 + 64aa: 00 00 + 64ac: 01 00 + 64ae: 03 04 8e 01 lb s0, 24(t3) + 64b2: 03 00 09 0c lb zero, 192(s2) + 64b6: 00 01 + 64b8: 00 02 + 64ba: 04 03 + 64bc: 03 00 09 04 lb zero, 64(s2) + 64c0: 00 01 + 64c2: 03 00 09 08 lb zero, 128(s2) + 64c6: 00 01 + 64c8: 03 00 09 00 lb zero, 0(s2) + 64cc: 00 01 + 64ce: 00 03 + 64d0: 04 86 + 64d2: 01 03 + 64d4: 00 09 + 64d6: 04 00 + 64d8: 01 00 + 64da: 03 04 86 01 lb s0, 24(a2) + 64de: 03 00 09 00 lb zero, 0(s2) + 64e2: 00 01 + 64e4: 00 03 + 64e6: 04 86 + 64e8: 01 03 + 64ea: 00 09 + 64ec: 00 00 + 64ee: 01 00 + 64f0: 03 04 86 01 lb s0, 24(a2) + 64f4: 03 00 09 08 lb zero, 128(s2) + 64f8: 00 01 + 64fa: 00 03 + 64fc: 04 86 + 64fe: 01 03 + 6500: 00 09 + 6502: 00 00 + 6504: 01 00 + 6506: 03 04 86 01 lb s0, 24(a2) + 650a: 03 00 09 00 lb zero, 0(s2) + 650e: 00 01 + 6510: 00 03 + 6512: 04 86 + 6514: 01 03 + 6516: 00 09 + 6518: 00 00 + 651a: 01 00 + 651c: 03 04 86 01 lb s0, 24(a2) + 6520: 03 00 09 00 lb zero, 0(s2) + 6524: 00 01 + 6526: 03 00 09 04 lb zero, 64(s2) + 652a: 00 01 + 652c: 03 00 09 00 lb zero, 0(s2) + 6530: 00 01 + 6532: 00 02 + 6534: 04 04 + 6536: 03 00 09 08 lb zero, 128(s2) + 653a: 00 01 + 653c: 00 02 + 653e: 04 04 + 6540: 03 00 09 00 lb zero, 0(s2) + 6544: 00 01 + 6546: 00 02 + 6548: 04 04 + 654a: 03 00 09 14 lb zero, 320(s2) + 654e: 00 01 + 6550: 09 08 + 6552: 00 00 + 6554: 01 01 + 6556: 37 2f 00 00 lui t5, 2 + 655a: 03 00 91 00 lb zero, 9(sp) + 655e: 00 00 + 6560: 01 01 + 6562: fb 0e 0d 00 + 6566: 01 01 + 6568: 01 01 + 656a: 00 00 + 656c: 00 01 + 656e: 00 00 + 6570: 01 2e + 6572: 2e 2f + 6574: 2e 2e + 6576: 2f 2e 2e 2f + 657a: 2e 2e + 657c: 2f 72 69 73 + 6580: 63 76 2d 67 bgeu s10, s2, 1644 + 6584: 63 63 2f 6c bltu t5, sp, 1734 + 6588: 69 62 + 658a: 67 63 63 2f + 658e: 73 6f 66 74 csrrsi t5, 1862, 12 + 6592: 2d 66 + 6594: 70 00 + 6596: 2e 2e + 6598: 2f 2e 2e 2f + 659c: 2e 2e + 659e: 2f 2e 2e 2f + 65a2: 72 69 + 65a4: 73 63 76 2d csrrsi t1, 727, 12 + 65a8: 67 63 63 2f + 65ac: 6c 69 + 65ae: 62 67 + 65b0: 63 63 2f 2e bltu t5, sp, 742 + 65b4: 2e 2f + 65b6: 69 6e + 65b8: 63 6c 75 64 bltu a0, t2, 1624 + 65bc: 65 00 + 65be: 00 73 + 65c0: 75 62 + 65c2: 74 66 + 65c4: 33 2e 63 00 slt t3, t1, t1 + 65c8: 01 00 + 65ca: 00 73 + 65cc: 6f 66 74 2d jal a2, 289494 + 65d0: 66 70 + 65d2: 2e 68 + 65d4: 00 01 + 65d6: 00 00 + 65d8: 71 75 + 65da: 61 64 + 65dc: 2e 68 + 65de: 00 01 + 65e0: 00 00 + 65e2: 6c 6f + 65e4: 6e 67 + 65e6: 6c 6f + 65e8: 6e 67 + 65ea: 2e 68 + 65ec: 00 02 + 65ee: 00 00 + 65f0: 00 05 + 65f2: 01 00 + 65f4: 05 02 + 65f6: f4 2e + 65f8: 01 80 + 65fa: 03 23 01 05 lw t1, 80(sp) + 65fe: 03 03 01 09 lb t1, 144(sp) + 6602: 00 00 + 6604: 01 03 + 6606: 00 09 + 6608: 00 00 + 660a: 01 05 + 660c: 0d 03 + 660e: 00 09 + 6610: 00 00 + 6612: 01 05 + 6614: 03 03 01 09 lb t1, 144(sp) + 6618: 00 00 + 661a: 01 03 + 661c: 00 09 + 661e: 00 00 + 6620: 01 03 + 6622: 00 09 + 6624: 00 00 + 6626: 01 03 + 6628: 00 09 + 662a: 00 00 + 662c: 01 03 + 662e: 01 09 + 6630: 00 00 + 6632: 01 03 + 6634: 00 09 + 6636: 00 00 + 6638: 01 03 + 663a: 00 09 + 663c: 00 00 + 663e: 01 03 + 6640: 00 09 + 6642: 00 00 + 6644: 01 03 + 6646: 01 09 + 6648: 00 00 + 664a: 01 03 + 664c: 00 09 + 664e: 00 00 + 6650: 01 03 + 6652: 00 09 + 6654: 00 00 + 6656: 01 03 + 6658: 00 09 + 665a: 00 00 + 665c: 01 03 + 665e: 01 09 + 6660: 00 00 + 6662: 01 03 + 6664: 02 09 + 6666: 00 00 + 6668: 01 03 + 666a: 00 09 + 666c: 00 00 + 666e: 01 05 + 6670: 01 06 + 6672: 03 79 09 00 + 6676: 00 01 + 6678: 03 00 09 3c lb zero, 960(s2) + 667c: 00 01 + 667e: 05 03 + 6680: 03 07 09 10 lb a4, 256(s2) + 6684: 00 01 + 6686: 06 03 + 6688: 00 09 + 668a: 04 00 + 668c: 01 03 + 668e: 01 09 + 6690: 00 00 + 6692: 01 03 + 6694: 00 09 + 6696: 00 00 + 6698: 01 03 + 669a: 00 09 + 669c: 00 00 + 669e: 01 03 + 66a0: 00 09 + 66a2: 00 00 + 66a4: 01 03 + 66a6: 00 09 + 66a8: 18 00 + 66aa: 01 03 + 66ac: 00 09 + 66ae: 0c 00 + 66b0: 01 03 + 66b2: 00 09 + 66b4: 04 00 + 66b6: 01 03 + 66b8: 00 09 + 66ba: 00 00 + 66bc: 01 03 + 66be: 00 09 + 66c0: 04 00 + 66c2: 01 03 + 66c4: 00 09 + 66c6: 04 00 + 66c8: 01 03 + 66ca: 00 09 + 66cc: 04 00 + 66ce: 01 03 + 66d0: 00 09 + 66d2: 00 00 + 66d4: 01 03 + 66d6: 00 09 + 66d8: 00 00 + 66da: 01 03 + 66dc: 00 09 + 66de: 00 00 + 66e0: 01 03 + 66e2: 00 09 + 66e4: 00 00 + 66e6: 01 03 + 66e8: 00 09 + 66ea: 00 00 + 66ec: 01 03 + 66ee: 00 09 + 66f0: 00 00 + 66f2: 01 03 + 66f4: 00 09 + 66f6: 00 00 + 66f8: 01 03 + 66fa: 00 09 + 66fc: 00 00 + 66fe: 01 03 + 6700: 00 09 + 6702: 00 00 + 6704: 01 00 + 6706: 02 04 + 6708: 08 03 + 670a: 00 09 + 670c: 08 00 + 670e: 01 00 + 6710: 02 04 + 6712: 08 03 + 6714: 00 09 + 6716: 1c 00 + 6718: 01 00 + 671a: 02 04 + 671c: 08 03 + 671e: 00 09 + 6720: 00 00 + 6722: 01 00 + 6724: 02 04 + 6726: 09 03 + 6728: 00 09 + 672a: 04 00 + 672c: 01 00 + 672e: 02 04 + 6730: 09 06 + 6732: 03 01 09 04 lb sp, 64(s2) + 6736: 00 01 + 6738: 00 02 + 673a: 04 09 + 673c: 03 7f 09 08 + 6740: 00 01 + 6742: 00 02 + 6744: 04 09 + 6746: 03 01 09 04 lb sp, 64(s2) + 674a: 00 01 + 674c: 00 02 + 674e: 04 09 + 6750: 03 7f 09 08 + 6754: 00 01 + 6756: 00 02 + 6758: 04 09 + 675a: 06 03 + 675c: 00 09 + 675e: 04 00 + 6760: 01 00 + 6762: 02 04 + 6764: 09 03 + 6766: 00 09 + 6768: 00 00 + 676a: 01 00 + 676c: 02 04 + 676e: 09 03 + 6770: 00 09 + 6772: 00 00 + 6774: 01 00 + 6776: 02 04 + 6778: 09 03 + 677a: 01 09 + 677c: 00 00 + 677e: 01 00 + 6780: 02 04 + 6782: 09 03 + 6784: 00 09 + 6786: 00 00 + 6788: 01 00 + 678a: 02 04 + 678c: 09 03 + 678e: 00 09 + 6790: 00 00 + 6792: 01 00 + 6794: 02 04 + 6796: 09 03 + 6798: 00 09 + 679a: 00 00 + 679c: 01 00 + 679e: 02 04 + 67a0: 09 03 + 67a2: 00 09 + 67a4: 00 00 + 67a6: 01 00 + 67a8: 02 04 + 67aa: 09 03 + 67ac: 00 09 + 67ae: 10 00 + 67b0: 01 00 + 67b2: 02 04 + 67b4: 09 03 + 67b6: 00 09 + 67b8: 04 00 + 67ba: 01 00 + 67bc: 02 04 + 67be: 09 03 + 67c0: 00 09 + 67c2: 04 00 + 67c4: 01 00 + 67c6: 02 04 + 67c8: 09 03 + 67ca: 00 09 + 67cc: 04 00 + 67ce: 01 00 + 67d0: 02 04 + 67d2: 09 03 + 67d4: 00 09 + 67d6: 04 00 + 67d8: 01 00 + 67da: 02 04 + 67dc: 09 03 + 67de: 00 09 + 67e0: 04 00 + 67e2: 01 00 + 67e4: 02 04 + 67e6: 09 03 + 67e8: 00 09 + 67ea: 00 00 + 67ec: 01 00 + 67ee: 02 04 + 67f0: 09 03 + 67f2: 00 09 + 67f4: 00 00 + 67f6: 01 00 + 67f8: 02 04 + 67fa: 09 03 + 67fc: 00 09 + 67fe: 00 00 + 6800: 01 00 + 6802: 02 04 + 6804: 09 03 + 6806: 00 09 + 6808: 00 00 + 680a: 01 00 + 680c: 02 04 + 680e: 09 03 + 6810: 00 09 + 6812: 00 00 + 6814: 01 00 + 6816: 02 04 + 6818: 09 03 + 681a: 00 09 + 681c: 00 00 + 681e: 01 00 + 6820: 02 04 + 6822: 09 03 + 6824: 00 09 + 6826: 00 00 + 6828: 01 00 + 682a: 02 04 + 682c: 09 03 + 682e: 00 09 + 6830: 00 00 + 6832: 01 00 + 6834: 02 04 + 6836: 09 03 + 6838: 00 09 + 683a: 00 00 + 683c: 01 00 + 683e: 02 04 + 6840: 08 03 + 6842: 00 09 + 6844: 08 00 + 6846: 01 00 + 6848: 02 04 + 684a: 08 03 + 684c: 00 09 + 684e: 1c 00 + 6850: 01 00 + 6852: 02 04 + 6854: 08 03 + 6856: 00 09 + 6858: 00 00 + 685a: 01 00 + 685c: 02 04 + 685e: 09 03 + 6860: 00 09 + 6862: 04 00 + 6864: 01 00 + 6866: 02 04 + 6868: 09 06 + 686a: 03 01 09 04 lb sp, 64(s2) + 686e: 00 01 + 6870: 00 02 + 6872: 04 09 + 6874: 03 7f 09 08 + 6878: 00 01 + 687a: 00 02 + 687c: 04 09 + 687e: 06 03 + 6880: 00 09 + 6882: 08 00 + 6884: 01 00 + 6886: 02 04 + 6888: 09 03 + 688a: 00 09 + 688c: 00 00 + 688e: 01 00 + 6890: 02 04 + 6892: 09 03 + 6894: 00 09 + 6896: 00 00 + 6898: 01 00 + 689a: 02 04 + 689c: 09 03 + 689e: 01 09 + 68a0: 00 00 + 68a2: 01 00 + 68a4: 02 04 + 68a6: 09 03 + 68a8: 00 09 + 68aa: 00 00 + 68ac: 01 00 + 68ae: 02 04 + 68b0: 02 06 + 68b2: 03 00 09 04 lb zero, 64(s2) + 68b6: 00 01 + 68b8: 00 02 + 68ba: 04 03 + 68bc: 06 03 + 68be: 00 09 + 68c0: 1c 00 + 68c2: 01 00 + 68c4: 02 04 + 68c6: 0b 03 00 09 + 68ca: 04 00 + 68cc: 01 00 + 68ce: 02 04 + 68d0: 0b 03 00 09 + 68d4: 00 00 + 68d6: 01 00 + 68d8: 02 04 + 68da: 0b 03 00 09 + 68de: 00 00 + 68e0: 01 00 + 68e2: 02 04 + 68e4: 0b 03 00 09 + 68e8: 00 00 + 68ea: 01 00 + 68ec: 02 04 + 68ee: 0b 03 00 09 + 68f2: 00 00 + 68f4: 01 00 + 68f6: 02 04 + 68f8: 0b 03 00 09 + 68fc: 00 00 + 68fe: 01 00 + 6900: 02 04 + 6902: 0b 03 00 09 + 6906: 00 00 + 6908: 01 00 + 690a: 02 04 + 690c: 0b 03 00 09 + 6910: 00 00 + 6912: 01 00 + 6914: 02 04 + 6916: 0c 03 + 6918: 00 09 + 691a: 08 00 + 691c: 01 00 + 691e: 02 04 + 6920: 0c 03 + 6922: 00 09 + 6924: 00 00 + 6926: 01 00 + 6928: 02 04 + 692a: 0c 03 + 692c: 00 09 + 692e: 00 00 + 6930: 01 00 + 6932: 02 04 + 6934: 0e 03 + 6936: 00 09 + 6938: 04 00 + 693a: 01 00 + 693c: 02 04 + 693e: 0e 03 + 6940: 00 09 + 6942: 00 00 + 6944: 01 00 + 6946: 02 04 + 6948: 10 03 + 694a: 00 09 + 694c: 10 00 + 694e: 01 00 + 6950: 02 04 + 6952: 12 03 + 6954: 00 09 + 6956: 1c 00 + 6958: 01 00 + 695a: 02 04 + 695c: 12 03 + 695e: 00 09 + 6960: 00 00 + 6962: 01 00 + 6964: 02 04 + 6966: 14 06 + 6968: 03 00 09 0c lb zero, 192(s2) + 696c: 00 01 + 696e: 00 02 + 6970: 04 16 + 6972: 03 00 09 10 lb zero, 256(s2) + 6976: 00 01 + 6978: 03 00 09 08 lb zero, 128(s2) + 697c: 00 01 + 697e: 00 02 + 6980: 04 1a + 6982: 06 03 + 6984: 00 09 + 6986: 04 00 + 6988: 01 00 + 698a: 02 04 + 698c: 1a 03 + 698e: 00 09 + 6990: 00 00 + 6992: 01 00 + 6994: 02 04 + 6996: 1a 03 + 6998: 00 09 + 699a: 10 00 + 699c: 01 03 + 699e: 00 09 + 69a0: 00 00 + 69a2: 01 03 + 69a4: 00 09 + 69a6: 00 00 + 69a8: 01 03 + 69aa: 00 09 + 69ac: 00 00 + 69ae: 01 03 + 69b0: 01 09 + 69b2: 00 00 + 69b4: 01 03 + 69b6: 00 09 + 69b8: 00 00 + 69ba: 01 03 + 69bc: 00 09 + 69be: 00 00 + 69c0: 01 06 + 69c2: 03 7f 09 00 + 69c6: 00 01 + 69c8: 00 02 + 69ca: 04 13 + 69cc: 06 03 + 69ce: 00 09 + 69d0: 08 00 + 69d2: 01 00 + 69d4: 02 04 + 69d6: 13 03 00 09 addi t1, zero, 144 + 69da: 00 00 + 69dc: 01 00 + 69de: 02 04 + 69e0: 13 03 00 09 addi t1, zero, 144 + 69e4: 04 00 + 69e6: 01 00 + 69e8: 02 04 + 69ea: 1c 03 + 69ec: 00 09 + 69ee: 04 00 + 69f0: 01 00 + 69f2: 02 04 + 69f4: 1c 03 + 69f6: 00 09 + 69f8: 00 00 + 69fa: 01 00 + 69fc: 02 04 + 69fe: 1c 03 + 6a00: 00 09 + 6a02: 00 00 + 6a04: 01 00 + 6a06: 02 04 + 6a08: 1c 03 + 6a0a: 00 09 + 6a0c: 00 00 + 6a0e: 01 00 + 6a10: 02 04 + 6a12: 1c 03 + 6a14: 00 09 + 6a16: 28 00 + 6a18: 01 00 + 6a1a: 02 04 + 6a1c: 1c 03 + 6a1e: 00 09 + 6a20: 00 00 + 6a22: 01 00 + 6a24: 02 04 + 6a26: 1c 03 + 6a28: 00 09 + 6a2a: 00 00 + 6a2c: 01 00 + 6a2e: 02 04 + 6a30: 1c 03 + 6a32: 00 09 + 6a34: 00 00 + 6a36: 01 00 + 6a38: 02 04 + 6a3a: 1c 03 + 6a3c: 00 09 + 6a3e: 00 00 + 6a40: 01 00 + 6a42: 02 04 + 6a44: 1c 03 + 6a46: 00 09 + 6a48: 00 00 + 6a4a: 01 00 + 6a4c: 02 04 + 6a4e: 1c 03 + 6a50: 00 09 + 6a52: 00 00 + 6a54: 01 00 + 6a56: 02 04 + 6a58: 1c 03 + 6a5a: 00 09 + 6a5c: 00 00 + 6a5e: 01 00 + 6a60: 02 04 + 6a62: 1c 03 + 6a64: 00 09 + 6a66: 1c 00 + 6a68: 01 00 + 6a6a: 02 04 + 6a6c: 1c 03 + 6a6e: 00 09 + 6a70: 00 00 + 6a72: 01 00 + 6a74: 02 04 + 6a76: 1c 03 + 6a78: 00 09 + 6a7a: 04 00 + 6a7c: 01 00 + 6a7e: 02 04 + 6a80: 1c 03 + 6a82: 00 09 + 6a84: 00 00 + 6a86: 01 00 + 6a88: 02 04 + 6a8a: 5b 03 00 09 + 6a8e: 00 00 + 6a90: 01 00 + 6a92: 02 04 + 6a94: 5b 03 00 09 + 6a98: 00 00 + 6a9a: 01 00 + 6a9c: 02 04 + 6a9e: 5b 06 03 7f + 6aa2: 09 00 + 6aa4: 00 01 + 6aa6: 00 02 + 6aa8: 04 5b + 6aaa: 03 01 09 04 lb sp, 64(s2) + 6aae: 00 01 + 6ab0: 00 02 + 6ab2: 04 1d + 6ab4: 06 03 + 6ab6: 00 09 + 6ab8: 04 00 + 6aba: 01 00 + 6abc: 02 04 + 6abe: 21 03 + 6ac0: 00 09 + 6ac2: 10 00 + 6ac4: 01 00 + 6ac6: 02 04 + 6ac8: 21 03 + 6aca: 00 09 + 6acc: 00 00 + 6ace: 01 00 + 6ad0: 02 04 + 6ad2: 23 06 03 00 sb zero, 12(t1) + 6ad6: 09 14 + 6ad8: 00 01 + 6ada: 00 02 + 6adc: 04 27 + 6ade: 06 03 + 6ae0: 00 09 + 6ae2: 10 00 + 6ae4: 01 00 + 6ae6: 02 04 + 6ae8: 27 03 00 09 + 6aec: 00 00 + 6aee: 01 00 + 6af0: 02 04 + 6af2: 27 03 00 09 + 6af6: 10 00 + 6af8: 01 06 + 6afa: 03 01 09 00 lb sp, 0(s2) + 6afe: 00 01 + 6b00: 00 02 + 6b02: 04 11 + 6b04: 06 03 + 6b06: 7f 09 08 00 + 6b0a: 01 00 + 6b0c: 02 04 + 6b0e: 2c 03 + 6b10: 00 09 + 6b12: 0c 00 + 6b14: 01 00 + 6b16: 02 04 + 6b18: 2c 03 + 6b1a: 00 09 + 6b1c: 00 00 + 6b1e: 01 00 + 6b20: 02 04 + 6b22: 2c 06 + 6b24: 03 77 09 0c + 6b28: 00 01 + 6b2a: 00 02 + 6b2c: 04 2c + 6b2e: 03 09 09 04 lb s2, 64(s2) + 6b32: 00 01 + 6b34: 00 02 + 6b36: 04 2e + 6b38: 03 00 09 04 lb zero, 64(s2) + 6b3c: 00 01 + 6b3e: 00 02 + 6b40: 04 2e + 6b42: 03 77 09 08 + 6b46: 00 01 + 6b48: 00 02 + 6b4a: 04 32 + 6b4c: 06 03 + 6b4e: 09 09 + 6b50: 08 00 + 6b52: 01 00 + 6b54: 02 04 + 6b56: 32 03 + 6b58: 00 09 + 6b5a: 00 00 + 6b5c: 01 00 + 6b5e: 02 04 + 6b60: 32 03 + 6b62: 00 09 + 6b64: 10 00 + 6b66: 01 00 + 6b68: 03 04 cd 02 lb s0, 44(s10) + 6b6c: 03 00 09 00 lb zero, 0(s2) + 6b70: 00 01 + 6b72: 00 02 + 6b74: 04 2b + 6b76: 03 00 09 0c lb zero, 192(s2) + 6b7a: 00 01 + 6b7c: 00 02 + 6b7e: 04 2b + 6b80: 03 00 09 10 lb zero, 256(s2) + 6b84: 00 01 + 6b86: 00 02 + 6b88: 04 35 + 6b8a: 03 00 09 10 lb zero, 256(s2) + 6b8e: 00 01 + 6b90: 00 02 + 6b92: 04 35 + 6b94: 03 00 09 00 lb zero, 0(s2) + 6b98: 00 01 + 6b9a: 00 02 + 6b9c: 04 35 + 6b9e: 03 00 09 00 lb zero, 0(s2) + 6ba2: 00 01 + 6ba4: 00 02 + 6ba6: 04 35 + 6ba8: 03 00 09 00 lb zero, 0(s2) + 6bac: 00 01 + 6bae: 00 02 + 6bb0: 04 35 + 6bb2: 03 00 09 00 lb zero, 0(s2) + 6bb6: 00 01 + 6bb8: 00 02 + 6bba: 04 35 + 6bbc: 03 00 09 00 lb zero, 0(s2) + 6bc0: 00 01 + 6bc2: 00 02 + 6bc4: 04 35 + 6bc6: 03 00 09 00 lb zero, 0(s2) + 6bca: 00 01 + 6bcc: 00 02 + 6bce: 04 35 + 6bd0: 03 00 09 04 lb zero, 64(s2) + 6bd4: 00 01 + 6bd6: 00 02 + 6bd8: 04 35 + 6bda: 03 00 09 00 lb zero, 0(s2) + 6bde: 00 01 + 6be0: 00 02 + 6be2: 04 35 + 6be4: 03 00 09 00 lb zero, 0(s2) + 6be8: 00 01 + 6bea: 00 02 + 6bec: 04 37 + 6bee: 03 00 09 08 lb zero, 128(s2) + 6bf2: 00 01 + 6bf4: 00 02 + 6bf6: 04 3a + 6bf8: 03 00 09 04 lb zero, 64(s2) + 6bfc: 00 01 + 6bfe: 06 03 + 6c00: 00 09 + 6c02: 0c 00 + 6c04: 01 00 + 6c06: 02 04 + 6c08: 3f 06 03 00 + 6c0c: 09 0c + 6c0e: 00 01 + 6c10: 00 02 + 6c12: 04 3f + 6c14: 03 00 09 14 lb zero, 320(s2) + 6c18: 00 01 + 6c1a: 00 02 + 6c1c: 04 3f + 6c1e: 03 00 09 00 lb zero, 0(s2) + 6c22: 00 01 + 6c24: 00 02 + 6c26: 04 39 + 6c28: 03 00 09 1c lb zero, 448(s2) + 6c2c: 00 01 + 6c2e: 00 02 + 6c30: 04 39 + 6c32: 03 00 09 14 lb zero, 320(s2) + 6c36: 00 01 + 6c38: 00 02 + 6c3a: 04 3c + 6c3c: 06 03 + 6c3e: 00 09 + 6c40: 04 00 + 6c42: 01 00 + 6c44: 02 04 + 6c46: 3c 06 + 6c48: 03 00 09 14 lb zero, 320(s2) + 6c4c: 00 01 + 6c4e: 00 02 + 6c50: 04 3c + 6c52: 03 00 09 10 lb zero, 256(s2) + 6c56: 00 01 + 6c58: 00 02 + 6c5a: 04 40 + 6c5c: 03 00 09 08 lb zero, 128(s2) + 6c60: 00 01 + 6c62: 00 02 + 6c64: 04 43 + 6c66: 06 03 + 6c68: 00 09 + 6c6a: 08 00 + 6c6c: 01 00 + 6c6e: 02 04 + 6c70: 43 06 03 00 fmadd.s fa2, ft6, ft0, ft0, rne + 6c74: 09 18 + 6c76: 00 01 + 6c78: 00 02 + 6c7a: 04 45 + 6c7c: 06 03 + 6c7e: 00 09 + 6c80: 08 00 + 6c82: 01 00 + 6c84: 02 04 + 6c86: 42 06 + 6c88: 03 00 09 08 lb zero, 128(s2) + 6c8c: 00 01 + 6c8e: 00 02 + 6c90: 04 42 + 6c92: 03 00 09 20 lb zero, 512(s2) + 6c96: 00 01 + 6c98: 00 02 + 6c9a: 04 46 + 6c9c: 03 00 09 08 lb zero, 128(s2) + 6ca0: 00 01 + 6ca2: 00 02 + 6ca4: 04 46 + 6ca6: 03 00 09 0c lb zero, 192(s2) + 6caa: 00 01 + 6cac: 00 02 + 6cae: 04 45 + 6cb0: 03 00 09 04 lb zero, 64(s2) + 6cb4: 00 01 + 6cb6: 00 02 + 6cb8: 04 47 + 6cba: 03 00 09 04 lb zero, 64(s2) + 6cbe: 00 01 + 6cc0: 00 02 + 6cc2: 04 47 + 6cc4: 03 00 09 00 lb zero, 0(s2) + 6cc8: 00 01 + 6cca: 00 02 + 6ccc: 04 47 + 6cce: 03 00 09 00 lb zero, 0(s2) + 6cd2: 00 01 + 6cd4: 06 03 + 6cd6: 00 09 + 6cd8: 0c 00 + 6cda: 01 06 + 6cdc: 03 00 09 04 lb zero, 64(s2) + 6ce0: 00 01 + 6ce2: 03 00 09 00 lb zero, 0(s2) + 6ce6: 00 01 + 6ce8: 03 00 09 00 lb zero, 0(s2) + 6cec: 00 01 + 6cee: 03 00 09 00 lb zero, 0(s2) + 6cf2: 00 01 + 6cf4: 03 00 09 18 lb zero, 384(s2) + 6cf8: 00 01 + 6cfa: 03 00 09 00 lb zero, 0(s2) + 6cfe: 00 01 + 6d00: 03 00 09 00 lb zero, 0(s2) + 6d04: 00 01 + 6d06: 03 00 09 00 lb zero, 0(s2) + 6d0a: 00 01 + 6d0c: 03 00 09 0c lb zero, 192(s2) + 6d10: 00 01 + 6d12: 03 00 09 0c lb zero, 192(s2) + 6d16: 00 01 + 6d18: 03 00 09 04 lb zero, 64(s2) + 6d1c: 00 01 + 6d1e: 03 00 09 00 lb zero, 0(s2) + 6d22: 00 01 + 6d24: 03 00 09 20 lb zero, 512(s2) + 6d28: 00 01 + 6d2a: 03 00 09 00 lb zero, 0(s2) + 6d2e: 00 01 + 6d30: 03 00 09 04 lb zero, 64(s2) + 6d34: 00 01 + 6d36: 06 03 + 6d38: 7e 09 + 6d3a: 00 00 + 6d3c: 01 00 + 6d3e: 03 04 8b 01 lb s0, 24(s6) + 6d42: 06 03 + 6d44: 02 09 + 6d46: 04 00 + 6d48: 01 00 + 6d4a: 03 04 fa 01 lb s0, 31(s4) + 6d4e: 03 00 09 10 lb zero, 256(s2) + 6d52: 00 01 + 6d54: 00 03 + 6d56: 04 fa + 6d58: 01 03 + 6d5a: 00 09 + 6d5c: 10 00 + 6d5e: 01 00 + 6d60: 03 04 fa 01 lb s0, 31(s4) + 6d64: 03 00 09 08 lb zero, 128(s2) + 6d68: 00 01 + 6d6a: 00 03 + 6d6c: 04 fa + 6d6e: 01 03 + 6d70: 00 09 + 6d72: 00 00 + 6d74: 01 00 + 6d76: 03 04 fa 01 lb s0, 31(s4) + 6d7a: 03 00 09 00 lb zero, 0(s2) + 6d7e: 00 01 + 6d80: 00 03 + 6d82: 04 fa + 6d84: 01 03 + 6d86: 00 09 + 6d88: 00 00 + 6d8a: 01 00 + 6d8c: 03 04 fa 01 lb s0, 31(s4) + 6d90: 03 00 09 00 lb zero, 0(s2) + 6d94: 00 01 + 6d96: 00 03 + 6d98: 04 fa + 6d9a: 01 03 + 6d9c: 00 09 + 6d9e: 00 00 + 6da0: 01 00 + 6da2: 03 04 fa 01 lb s0, 31(s4) + 6da6: 03 00 09 00 lb zero, 0(s2) + 6daa: 00 01 + 6dac: 00 03 + 6dae: 04 fa + 6db0: 01 03 + 6db2: 00 09 + 6db4: 00 00 + 6db6: 01 00 + 6db8: 03 04 fa 01 lb s0, 31(s4) + 6dbc: 03 00 09 00 lb zero, 0(s2) + 6dc0: 00 01 + 6dc2: 00 03 + 6dc4: 04 fa + 6dc6: 01 03 + 6dc8: 00 09 + 6dca: 00 00 + 6dcc: 01 00 + 6dce: 03 04 fa 01 lb s0, 31(s4) + 6dd2: 03 00 09 00 lb zero, 0(s2) + 6dd6: 00 01 + 6dd8: 00 03 + 6dda: 04 fa + 6ddc: 01 03 + 6dde: 00 09 + 6de0: 00 00 + 6de2: 01 00 + 6de4: 03 04 fa 01 lb s0, 31(s4) + 6de8: 03 00 09 00 lb zero, 0(s2) + 6dec: 00 01 + 6dee: 00 03 + 6df0: 04 fa + 6df2: 01 03 + 6df4: 00 09 + 6df6: 08 00 + 6df8: 01 00 + 6dfa: 03 04 fa 01 lb s0, 31(s4) + 6dfe: 03 00 09 00 lb zero, 0(s2) + 6e02: 00 01 + 6e04: 00 03 + 6e06: 04 87 + 6e08: 02 03 + 6e0a: 00 09 + 6e0c: 04 00 + 6e0e: 01 00 + 6e10: 03 04 87 02 lb s0, 40(a4) + 6e14: 03 00 09 1c lb zero, 448(s2) + 6e18: 00 01 + 6e1a: 00 03 + 6e1c: 04 87 + 6e1e: 02 03 + 6e20: 00 09 + 6e22: 00 00 + 6e24: 01 00 + 6e26: 03 04 88 02 lb s0, 40(a6) + 6e2a: 03 00 09 04 lb zero, 64(s2) + 6e2e: 00 01 + 6e30: 00 03 + 6e32: 04 88 + 6e34: 02 03 + 6e36: 00 09 + 6e38: 0c 00 + 6e3a: 01 00 + 6e3c: 03 04 88 02 lb s0, 40(a6) + 6e40: 03 00 09 00 lb zero, 0(s2) + 6e44: 00 01 + 6e46: 00 03 + 6e48: 04 88 + 6e4a: 02 03 + 6e4c: 00 09 + 6e4e: 00 00 + 6e50: 01 00 + 6e52: 03 04 88 02 lb s0, 40(a6) + 6e56: 03 00 09 00 lb zero, 0(s2) + 6e5a: 00 01 + 6e5c: 00 03 + 6e5e: 04 88 + 6e60: 02 03 + 6e62: 00 09 + 6e64: 10 00 + 6e66: 01 00 + 6e68: 03 04 88 02 lb s0, 40(a6) + 6e6c: 03 00 09 00 lb zero, 0(s2) + 6e70: 00 01 + 6e72: 00 03 + 6e74: 04 8d + 6e76: 02 03 + 6e78: 00 09 + 6e7a: 0c 00 + 6e7c: 01 00 + 6e7e: 03 04 8d 02 lb s0, 40(s10) + 6e82: 03 00 09 00 lb zero, 0(s2) + 6e86: 00 01 + 6e88: 00 03 + 6e8a: 04 90 + 6e8c: 02 06 + 6e8e: 03 00 09 04 lb zero, 64(s2) + 6e92: 00 01 + 6e94: 00 03 + 6e96: 04 91 + 6e98: 02 03 + 6e9a: 00 09 + 6e9c: 08 00 + 6e9e: 01 00 + 6ea0: 03 04 98 02 lb s0, 41(a6) + 6ea4: 06 03 + 6ea6: 00 09 + 6ea8: 04 00 + 6eaa: 01 00 + 6eac: 03 04 98 02 lb s0, 41(a6) + 6eb0: 03 00 09 00 lb zero, 0(s2) + 6eb4: 00 01 + 6eb6: 00 02 + 6eb8: 04 0f + 6eba: 03 00 09 20 lb zero, 512(s2) + 6ebe: 00 01 + 6ec0: 00 02 + 6ec2: 04 4d + 6ec4: 03 00 09 10 lb zero, 256(s2) + 6ec8: 00 01 + 6eca: 00 02 + 6ecc: 04 4d + 6ece: 03 00 09 04 lb zero, 64(s2) + 6ed2: 00 01 + 6ed4: 00 02 + 6ed6: 04 4d + 6ed8: 03 00 09 00 lb zero, 0(s2) + 6edc: 00 01 + 6ede: 00 02 + 6ee0: 04 4f + 6ee2: 03 00 09 04 lb zero, 64(s2) + 6ee6: 00 01 + 6ee8: 00 02 + 6eea: 04 51 + 6eec: 03 00 09 1c lb zero, 448(s2) + 6ef0: 00 01 + 6ef2: 00 02 + 6ef4: 04 51 + 6ef6: 03 00 09 00 lb zero, 0(s2) + 6efa: 00 01 + 6efc: 00 02 + 6efe: 04 53 + 6f00: 06 03 + 6f02: 00 09 + 6f04: 0c 00 + 6f06: 01 00 + 6f08: 02 04 + 6f0a: 55 03 + 6f0c: 00 09 + 6f0e: 10 00 + 6f10: 01 03 + 6f12: 00 09 + 6f14: 08 00 + 6f16: 01 00 + 6f18: 02 04 + 6f1a: 59 06 + 6f1c: 03 00 09 04 lb zero, 64(s2) + 6f20: 00 01 + 6f22: 00 02 + 6f24: 04 59 + 6f26: 03 00 09 00 lb zero, 0(s2) + 6f2a: 00 01 + 6f2c: 00 02 + 6f2e: 04 59 + 6f30: 03 00 09 10 lb zero, 256(s2) + 6f34: 00 01 + 6f36: 00 03 + 6f38: 04 a8 + 6f3a: 05 03 + 6f3c: 00 09 + 6f3e: 00 00 + 6f40: 01 00 + 6f42: 03 04 a8 05 lb s0, 90(a6) + 6f46: 03 00 09 00 lb zero, 0(s2) + 6f4a: 00 01 + 6f4c: 00 03 + 6f4e: 04 a8 + 6f50: 05 03 + 6f52: 00 09 + 6f54: 00 00 + 6f56: 01 00 + 6f58: 03 04 a8 05 lb s0, 90(a6) + 6f5c: 03 01 09 00 lb sp, 0(s2) + 6f60: 00 01 + 6f62: 00 03 + 6f64: 04 a8 + 6f66: 05 03 + 6f68: 00 09 + 6f6a: 00 00 + 6f6c: 01 00 + 6f6e: 03 04 a8 05 lb s0, 90(a6) + 6f72: 03 00 09 00 lb zero, 0(s2) + 6f76: 00 01 + 6f78: 00 02 + 6f7a: 04 52 + 6f7c: 03 7f 09 0c + 6f80: 00 01 + 6f82: 00 02 + 6f84: 04 52 + 6f86: 03 00 09 00 lb zero, 0(s2) + 6f8a: 00 01 + 6f8c: 00 02 + 6f8e: 04 52 + 6f90: 03 00 09 04 lb zero, 64(s2) + 6f94: 00 01 + 6f96: 00 02 + 6f98: 04 5b + 6f9a: 03 00 09 04 lb zero, 64(s2) + 6f9e: 00 01 + 6fa0: 00 02 + 6fa2: 04 5b + 6fa4: 03 00 09 00 lb zero, 0(s2) + 6fa8: 00 01 + 6faa: 00 02 + 6fac: 04 5b + 6fae: 03 00 09 00 lb zero, 0(s2) + 6fb2: 00 01 + 6fb4: 00 02 + 6fb6: 04 5b + 6fb8: 03 00 09 00 lb zero, 0(s2) + 6fbc: 00 01 + 6fbe: 00 02 + 6fc0: 04 5b + 6fc2: 03 00 09 40 lb zero, 1024(s2) + 6fc6: 00 01 + 6fc8: 00 02 + 6fca: 04 5b + 6fcc: 03 00 09 00 lb zero, 0(s2) + 6fd0: 00 01 + 6fd2: 00 02 + 6fd4: 04 5b + 6fd6: 03 00 09 00 lb zero, 0(s2) + 6fda: 00 01 + 6fdc: 00 02 + 6fde: 04 5b + 6fe0: 03 00 09 00 lb zero, 0(s2) + 6fe4: 00 01 + 6fe6: 00 02 + 6fe8: 04 5b + 6fea: 03 00 09 00 lb zero, 0(s2) + 6fee: 00 01 + 6ff0: 00 02 + 6ff2: 04 5b + 6ff4: 03 00 09 00 lb zero, 0(s2) + 6ff8: 00 01 + 6ffa: 00 02 + 6ffc: 04 5b + 6ffe: 03 00 09 00 lb zero, 0(s2) + 7002: 00 01 + 7004: 00 02 + 7006: 04 5b + 7008: 03 00 09 00 lb zero, 0(s2) + 700c: 00 01 + 700e: 00 02 + 7010: 04 5b + 7012: 03 00 09 04 lb zero, 64(s2) + 7016: 00 01 + 7018: 00 02 + 701a: 04 5b + 701c: 03 00 09 00 lb zero, 0(s2) + 7020: 00 01 + 7022: 00 02 + 7024: 04 5c + 7026: 03 00 09 08 lb zero, 128(s2) + 702a: 00 01 + 702c: 00 02 + 702e: 04 60 + 7030: 03 00 09 10 lb zero, 256(s2) + 7034: 00 01 + 7036: 00 02 + 7038: 04 60 + 703a: 03 00 09 00 lb zero, 0(s2) + 703e: 00 01 + 7040: 00 02 + 7042: 04 62 + 7044: 06 03 + 7046: 00 09 + 7048: 14 00 + 704a: 01 00 + 704c: 02 04 + 704e: 66 06 + 7050: 03 00 09 10 lb zero, 256(s2) + 7054: 00 01 + 7056: 00 02 + 7058: 04 66 + 705a: 03 00 09 00 lb zero, 0(s2) + 705e: 00 01 + 7060: 00 03 + 7062: 04 c2 + 7064: 02 06 + 7066: 03 00 09 0c lb zero, 192(s2) + 706a: 00 01 + 706c: 00 03 + 706e: 04 c2 + 7070: 02 06 + 7072: 03 00 09 04 lb zero, 64(s2) + 7076: 00 01 + 7078: 00 02 + 707a: 04 50 + 707c: 03 00 09 04 lb zero, 64(s2) + 7080: 00 01 + 7082: 00 02 + 7084: 04 6b + 7086: 03 00 09 0c lb zero, 192(s2) + 708a: 00 01 + 708c: 00 02 + 708e: 04 6b + 7090: 03 00 09 00 lb zero, 0(s2) + 7094: 00 01 + 7096: 00 02 + 7098: 04 6b + 709a: 06 03 + 709c: 77 09 0c 00 + 70a0: 01 00 + 70a2: 02 04 + 70a4: 6b 03 09 09 vx_tex t1, s2, a6, ra, rne + 70a8: 04 00 + 70aa: 01 00 + 70ac: 02 04 + 70ae: 6d 03 + 70b0: 00 09 + 70b2: 04 00 + 70b4: 01 00 + 70b6: 02 04 + 70b8: 6d 03 + 70ba: 77 09 08 00 + 70be: 01 00 + 70c0: 02 04 + 70c2: 71 06 + 70c4: 03 09 09 08 lb s2, 128(s2) + 70c8: 00 01 + 70ca: 00 02 + 70cc: 04 71 + 70ce: 03 00 09 00 lb zero, 0(s2) + 70d2: 00 01 + 70d4: 00 02 + 70d6: 04 71 + 70d8: 03 00 09 10 lb zero, 256(s2) + 70dc: 00 01 + 70de: 00 02 + 70e0: 04 6a + 70e2: 03 00 09 08 lb zero, 128(s2) + 70e6: 00 01 + 70e8: 00 02 + 70ea: 04 6a + 70ec: 03 00 09 10 lb zero, 256(s2) + 70f0: 00 01 + 70f2: 00 02 + 70f4: 04 74 + 70f6: 03 00 09 10 lb zero, 256(s2) + 70fa: 00 01 + 70fc: 00 02 + 70fe: 04 74 + 7100: 03 00 09 00 lb zero, 0(s2) + 7104: 00 01 + 7106: 00 02 + 7108: 04 74 + 710a: 03 00 09 00 lb zero, 0(s2) + 710e: 00 01 + 7110: 00 02 + 7112: 04 74 + 7114: 03 00 09 00 lb zero, 0(s2) + 7118: 00 01 + 711a: 00 02 + 711c: 04 74 + 711e: 03 00 09 00 lb zero, 0(s2) + 7122: 00 01 + 7124: 00 02 + 7126: 04 74 + 7128: 03 00 09 00 lb zero, 0(s2) + 712c: 00 01 + 712e: 00 02 + 7130: 04 74 + 7132: 03 00 09 00 lb zero, 0(s2) + 7136: 00 01 + 7138: 00 02 + 713a: 04 74 + 713c: 03 00 09 08 lb zero, 128(s2) + 7140: 00 01 + 7142: 00 02 + 7144: 04 74 + 7146: 03 00 09 00 lb zero, 0(s2) + 714a: 00 01 + 714c: 00 02 + 714e: 04 74 + 7150: 03 00 09 00 lb zero, 0(s2) + 7154: 00 01 + 7156: 00 02 + 7158: 04 76 + 715a: 03 00 09 08 lb zero, 128(s2) + 715e: 00 01 + 7160: 00 02 + 7162: 04 79 + 7164: 03 00 09 10 lb zero, 256(s2) + 7168: 00 01 + 716a: 06 03 + 716c: 00 09 + 716e: 0c 00 + 7170: 01 00 + 7172: 02 04 + 7174: 7e 06 + 7176: 03 00 09 08 lb zero, 128(s2) + 717a: 00 01 + 717c: 00 02 + 717e: 04 7e + 7180: 03 00 09 14 lb zero, 320(s2) + 7184: 00 01 + 7186: 00 02 + 7188: 04 7e + 718a: 03 00 09 00 lb zero, 0(s2) + 718e: 00 01 + 7190: 00 02 + 7192: 04 78 + 7194: 03 00 09 1c lb zero, 448(s2) + 7198: 00 01 + 719a: 00 02 + 719c: 04 78 + 719e: 03 00 09 14 lb zero, 320(s2) + 71a2: 00 01 + 71a4: 00 02 + 71a6: 04 7b + 71a8: 06 03 + 71aa: 00 09 + 71ac: 04 00 + 71ae: 01 00 + 71b0: 02 04 + 71b2: 7b 06 03 00 + 71b6: 09 24 + 71b8: 00 01 + 71ba: 00 02 + 71bc: 04 7b + 71be: 03 00 09 08 lb zero, 128(s2) + 71c2: 00 01 + 71c4: 00 02 + 71c6: 04 7f + 71c8: 03 00 09 08 lb zero, 128(s2) + 71cc: 00 01 + 71ce: 00 03 + 71d0: 04 82 + 71d2: 01 06 + 71d4: 03 00 09 08 lb zero, 128(s2) + 71d8: 00 01 + 71da: 00 03 + 71dc: 04 82 + 71de: 01 06 + 71e0: 03 00 09 18 lb zero, 384(s2) + 71e4: 00 01 + 71e6: 00 03 + 71e8: 04 84 + 71ea: 01 06 + 71ec: 03 00 09 08 lb zero, 128(s2) + 71f0: 00 01 + 71f2: 00 03 + 71f4: 04 81 + 71f6: 01 06 + 71f8: 03 00 09 08 lb zero, 128(s2) + 71fc: 00 01 + 71fe: 00 03 + 7200: 04 81 + 7202: 01 03 + 7204: 00 09 + 7206: 20 00 + 7208: 01 00 + 720a: 03 04 85 01 lb s0, 24(a0) + 720e: 03 00 09 08 lb zero, 128(s2) + 7212: 00 01 + 7214: 00 03 + 7216: 04 85 + 7218: 01 03 + 721a: 00 09 + 721c: 0c 00 + 721e: 01 00 + 7220: 03 04 84 01 lb s0, 24(s0) + 7224: 03 00 09 04 lb zero, 64(s2) + 7228: 00 01 + 722a: 00 03 + 722c: 04 86 + 722e: 01 03 + 7230: 00 09 + 7232: 04 00 + 7234: 01 00 + 7236: 03 04 86 01 lb s0, 24(a2) + 723a: 03 00 09 00 lb zero, 0(s2) + 723e: 00 01 + 7240: 00 03 + 7242: 04 86 + 7244: 01 03 + 7246: 00 09 + 7248: 00 00 + 724a: 01 06 + 724c: 03 00 09 0c lb zero, 192(s2) + 7250: 00 01 + 7252: 06 03 + 7254: 00 09 + 7256: 04 00 + 7258: 01 03 + 725a: 00 09 + 725c: 00 00 + 725e: 01 03 + 7260: 00 09 + 7262: 00 00 + 7264: 01 03 + 7266: 00 09 + 7268: 00 00 + 726a: 01 03 + 726c: 00 09 + 726e: 18 00 + 7270: 01 03 + 7272: 00 09 + 7274: 00 00 + 7276: 01 03 + 7278: 00 09 + 727a: 00 00 + 727c: 01 03 + 727e: 00 09 + 7280: 00 00 + 7282: 01 03 + 7284: 00 09 + 7286: 0c 00 + 7288: 01 03 + 728a: 00 09 + 728c: 0c 00 + 728e: 01 03 + 7290: 00 09 + 7292: 04 00 + 7294: 01 03 + 7296: 00 09 + 7298: 00 00 + 729a: 01 03 + 729c: 00 09 + 729e: 20 00 + 72a0: 01 03 + 72a2: 00 09 + 72a4: 00 00 + 72a6: 01 03 + 72a8: 00 09 + 72aa: 04 00 + 72ac: 01 06 + 72ae: 03 7f 09 00 + 72b2: 00 01 + 72b4: 00 02 + 72b6: 04 4e + 72b8: 06 03 + 72ba: 01 09 + 72bc: 08 00 + 72be: 01 00 + 72c0: 03 04 8c 01 lb s0, 24(s8) + 72c4: 03 00 09 20 lb zero, 512(s2) + 72c8: 00 01 + 72ca: 00 03 + 72cc: 04 8e + 72ce: 01 03 + 72d0: 00 09 + 72d2: 10 00 + 72d4: 01 00 + 72d6: 03 04 8e 01 lb s0, 24(t3) + 72da: 03 00 09 00 lb zero, 0(s2) + 72de: 00 01 + 72e0: 00 03 + 72e2: 04 90 + 72e4: 01 03 + 72e6: 00 09 + 72e8: 04 00 + 72ea: 01 00 + 72ec: 03 04 90 01 lb s0, 25(zero) + 72f0: 03 00 09 00 lb zero, 0(s2) + 72f4: 00 01 + 72f6: 00 03 + 72f8: 04 90 + 72fa: 01 03 + 72fc: 00 09 + 72fe: 10 00 + 7300: 01 00 + 7302: 02 04 + 7304: 01 06 + 7306: 03 01 09 00 lb sp, 0(s2) + 730a: 00 01 + 730c: 06 03 + 730e: 00 09 + 7310: 24 00 + 7312: 01 03 + 7314: 00 09 + 7316: 00 00 + 7318: 01 03 + 731a: 00 09 + 731c: 00 00 + 731e: 01 03 + 7320: 00 09 + 7322: 00 00 + 7324: 01 03 + 7326: 00 09 + 7328: 00 00 + 732a: 01 03 + 732c: 00 09 + 732e: 00 00 + 7330: 01 03 + 7332: 00 09 + 7334: 10 00 + 7336: 01 03 + 7338: 00 09 + 733a: 00 00 + 733c: 01 03 + 733e: 00 09 + 7340: 00 00 + 7342: 01 03 + 7344: 00 09 + 7346: 00 00 + 7348: 01 03 + 734a: 00 09 + 734c: 00 00 + 734e: 01 03 + 7350: 00 09 + 7352: 00 00 + 7354: 01 03 + 7356: 00 09 + 7358: 00 00 + 735a: 01 03 + 735c: 00 09 + 735e: 00 00 + 7360: 01 03 + 7362: 00 09 + 7364: 00 00 + 7366: 01 03 + 7368: 00 09 + 736a: 00 00 + 736c: 01 03 + 736e: 00 09 + 7370: 00 00 + 7372: 01 00 + 7374: 02 04 + 7376: 10 03 + 7378: 00 09 + 737a: 08 00 + 737c: 01 00 + 737e: 02 04 + 7380: 10 03 + 7382: 00 09 + 7384: 1c 00 + 7386: 01 00 + 7388: 02 04 + 738a: 10 03 + 738c: 00 09 + 738e: 00 00 + 7390: 01 00 + 7392: 02 04 + 7394: 11 03 + 7396: 00 09 + 7398: 04 00 + 739a: 01 00 + 739c: 02 04 + 739e: 11 03 + 73a0: 00 09 + 73a2: 08 00 + 73a4: 01 00 + 73a6: 02 04 + 73a8: 11 03 + 73aa: 00 09 + 73ac: 00 00 + 73ae: 01 00 + 73b0: 02 04 + 73b2: 11 03 + 73b4: 00 09 + 73b6: 00 00 + 73b8: 01 00 + 73ba: 02 04 + 73bc: 11 03 + 73be: 00 09 + 73c0: 00 00 + 73c2: 01 00 + 73c4: 02 04 + 73c6: 16 06 + 73c8: 03 00 09 0c lb zero, 192(s2) + 73cc: 00 01 + 73ce: 00 02 + 73d0: 04 16 + 73d2: 06 03 + 73d4: 00 09 + 73d6: 08 00 + 73d8: 01 00 + 73da: 02 04 + 73dc: 16 03 + 73de: 00 09 + 73e0: 04 00 + 73e2: 01 06 + 73e4: 03 00 09 08 lb zero, 128(s2) + 73e8: 00 01 + 73ea: 00 02 + 73ec: 04 19 + 73ee: 06 03 + 73f0: 00 09 + 73f2: 14 00 + 73f4: 01 00 + 73f6: 02 04 + 73f8: 19 03 + 73fa: 00 09 + 73fc: 00 00 + 73fe: 01 00 + 7400: 02 04 + 7402: 1d 03 + 7404: 00 09 + 7406: 10 00 + 7408: 01 00 + 740a: 02 04 + 740c: 1d 03 + 740e: 00 09 + 7410: 00 00 + 7412: 01 00 + 7414: 02 04 + 7416: 1d 03 + 7418: 00 09 + 741a: 00 00 + 741c: 01 00 + 741e: 02 04 + 7420: 1d 03 + 7422: 00 09 + 7424: 08 00 + 7426: 01 00 + 7428: 02 04 + 742a: 1d 03 + 742c: 00 09 + 742e: 00 00 + 7430: 01 00 + 7432: 02 04 + 7434: 28 03 + 7436: 00 09 + 7438: 00 00 + 743a: 01 00 + 743c: 02 04 + 743e: 28 03 + 7440: 00 09 + 7442: 00 00 + 7444: 01 00 + 7446: 02 04 + 7448: 28 03 + 744a: 00 09 + 744c: 0c 00 + 744e: 01 00 + 7450: 02 04 + 7452: 28 03 + 7454: 00 09 + 7456: 00 00 + 7458: 01 00 + 745a: 02 04 + 745c: 28 03 + 745e: 00 09 + 7460: 0c 00 + 7462: 01 00 + 7464: 03 04 91 01 lb s0, 25(sp) + 7468: 03 7f 09 0c + 746c: 00 01 + 746e: 00 03 + 7470: 04 96 + 7472: 01 03 + 7474: 00 09 + 7476: 10 00 + 7478: 01 00 + 747a: 03 04 96 01 lb s0, 25(a2) + 747e: 03 00 09 00 lb zero, 0(s2) + 7482: 00 01 + 7484: 00 03 + 7486: 04 96 + 7488: 01 03 + 748a: 00 09 + 748c: 10 00 + 748e: 01 00 + 7490: 03 04 97 01 lb s0, 25(a4) + 7494: 03 00 09 04 lb zero, 64(s2) + 7498: 00 01 + 749a: 00 03 + 749c: 04 97 + 749e: 01 03 + 74a0: 00 09 + 74a2: 00 00 + 74a4: 01 00 + 74a6: 03 04 97 01 lb s0, 25(a4) + 74aa: 03 00 09 00 lb zero, 0(s2) + 74ae: 00 01 + 74b0: 00 03 + 74b2: 04 97 + 74b4: 01 03 + 74b6: 00 09 + 74b8: 00 00 + 74ba: 01 00 + 74bc: 03 04 97 01 lb s0, 25(a4) + 74c0: 03 00 09 00 lb zero, 0(s2) + 74c4: 00 01 + 74c6: 00 03 + 74c8: 04 97 + 74ca: 01 03 + 74cc: 00 09 + 74ce: 10 00 + 74d0: 01 00 + 74d2: 03 04 97 01 lb s0, 25(a4) + 74d6: 03 00 09 00 lb zero, 0(s2) + 74da: 00 01 + 74dc: 00 03 + 74de: 04 97 + 74e0: 01 03 + 74e2: 00 09 + 74e4: 00 00 + 74e6: 01 00 + 74e8: 03 04 97 01 lb s0, 25(a4) + 74ec: 03 00 09 00 lb zero, 0(s2) + 74f0: 00 01 + 74f2: 00 03 + 74f4: 04 97 + 74f6: 01 03 + 74f8: 00 09 + 74fa: 30 00 + 74fc: 01 00 + 74fe: 03 04 97 01 lb s0, 25(a4) + 7502: 03 00 09 00 lb zero, 0(s2) + 7506: 00 01 + 7508: 00 03 + 750a: 04 97 + 750c: 01 03 + 750e: 00 09 + 7510: 00 00 + 7512: 01 00 + 7514: 03 04 97 01 lb s0, 25(a4) + 7518: 03 00 09 00 lb zero, 0(s2) + 751c: 00 01 + 751e: 00 03 + 7520: 04 97 + 7522: 01 03 + 7524: 00 09 + 7526: 04 00 + 7528: 01 00 + 752a: 03 04 97 01 lb s0, 25(a4) + 752e: 03 00 09 00 lb zero, 0(s2) + 7532: 00 01 + 7534: 00 03 + 7536: 04 97 + 7538: 01 03 + 753a: 00 09 + 753c: 00 00 + 753e: 01 00 + 7540: 03 04 97 01 lb s0, 25(a4) + 7544: 03 00 09 00 lb zero, 0(s2) + 7548: 00 01 + 754a: 06 03 + 754c: 00 09 + 754e: 08 00 + 7550: 01 00 + 7552: 03 04 99 01 lb s0, 25(s2) + 7556: 06 03 + 7558: 00 09 + 755a: 08 00 + 755c: 01 00 + 755e: 03 04 99 01 lb s0, 25(s2) + 7562: 03 00 09 10 lb zero, 256(s2) + 7566: 00 01 + 7568: 00 03 + 756a: 04 99 + 756c: 01 06 + 756e: 03 01 09 00 lb sp, 0(s2) + 7572: 00 01 + 7574: 00 03 + 7576: 04 99 + 7578: 01 03 + 757a: 7f 09 04 00 + 757e: 01 00 + 7580: 02 04 + 7582: 08 06 + 7584: 03 01 09 04 lb sp, 64(s2) + 7588: 00 01 + 758a: 00 02 + 758c: 04 08 + 758e: 03 00 09 00 lb zero, 0(s2) + 7592: 00 01 + 7594: 00 02 + 7596: 04 2c + 7598: 06 03 + 759a: 00 09 + 759c: 0c 00 + 759e: 01 00 + 75a0: 02 04 + 75a2: 2c 06 + 75a4: 03 00 09 08 lb zero, 128(s2) + 75a8: 00 01 + 75aa: 00 02 + 75ac: 04 2c + 75ae: 03 00 09 04 lb zero, 64(s2) + 75b2: 00 01 + 75b4: 06 03 + 75b6: 00 09 + 75b8: 04 00 + 75ba: 01 00 + 75bc: 02 04 + 75be: 2f 06 03 00 + 75c2: 09 0c + 75c4: 00 01 + 75c6: 00 02 + 75c8: 04 2f + 75ca: 03 00 09 00 lb zero, 0(s2) + 75ce: 00 01 + 75d0: 00 02 + 75d2: 04 33 + 75d4: 03 00 09 0c lb zero, 192(s2) + 75d8: 00 01 + 75da: 00 02 + 75dc: 04 33 + 75de: 03 00 09 00 lb zero, 0(s2) + 75e2: 00 01 + 75e4: 00 02 + 75e6: 04 33 + 75e8: 03 00 09 00 lb zero, 0(s2) + 75ec: 00 01 + 75ee: 00 02 + 75f0: 04 33 + 75f2: 03 00 09 10 lb zero, 256(s2) + 75f6: 00 01 + 75f8: 00 02 + 75fa: 04 33 + 75fc: 03 00 09 0c lb zero, 192(s2) + 7600: 00 01 + 7602: 00 02 + 7604: 04 33 + 7606: 03 00 09 00 lb zero, 0(s2) + 760a: 00 01 + 760c: 00 02 + 760e: 04 33 + 7610: 03 00 09 0c lb zero, 192(s2) + 7614: 00 01 + 7616: 00 02 + 7618: 04 33 + 761a: 03 00 09 04 lb zero, 64(s2) + 761e: 00 01 + 7620: 00 02 + 7622: 04 3e + 7624: 06 03 + 7626: 00 09 + 7628: 04 00 + 762a: 01 00 + 762c: 02 04 + 762e: 36 06 + 7630: 03 00 09 04 lb zero, 64(s2) + 7634: 00 01 + 7636: 00 02 + 7638: 04 36 + 763a: 03 00 09 00 lb zero, 0(s2) + 763e: 00 01 + 7640: 00 02 + 7642: 04 41 + 7644: 03 00 09 04 lb zero, 64(s2) + 7648: 00 01 + 764a: 00 02 + 764c: 04 43 + 764e: 03 00 09 08 lb zero, 128(s2) + 7652: 00 01 + 7654: 00 02 + 7656: 04 45 + 7658: 03 00 09 04 lb zero, 64(s2) + 765c: 00 01 + 765e: 00 02 + 7660: 04 46 + 7662: 03 00 09 0c lb zero, 192(s2) + 7666: 00 01 + 7668: 00 02 + 766a: 04 46 + 766c: 03 00 09 00 lb zero, 0(s2) + 7670: 00 01 + 7672: 00 02 + 7674: 04 46 + 7676: 03 00 09 08 lb zero, 128(s2) + 767a: 00 01 + 767c: 06 03 + 767e: 00 09 + 7680: 08 00 + 7682: 01 00 + 7684: 02 04 + 7686: 56 06 + 7688: 03 00 09 10 lb zero, 256(s2) + 768c: 00 01 + 768e: 00 02 + 7690: 04 56 + 7692: 03 00 09 00 lb zero, 0(s2) + 7696: 00 01 + 7698: 00 02 + 769a: 04 56 + 769c: 03 00 09 00 lb zero, 0(s2) + 76a0: 00 01 + 76a2: 00 02 + 76a4: 04 56 + 76a6: 03 00 09 00 lb zero, 0(s2) + 76aa: 00 01 + 76ac: 00 02 + 76ae: 04 56 + 76b0: 03 00 09 00 lb zero, 0(s2) + 76b4: 00 01 + 76b6: 00 02 + 76b8: 04 56 + 76ba: 03 00 09 00 lb zero, 0(s2) + 76be: 00 01 + 76c0: 00 02 + 76c2: 04 56 + 76c4: 03 00 09 00 lb zero, 0(s2) + 76c8: 00 01 + 76ca: 00 02 + 76cc: 04 56 + 76ce: 03 00 09 00 lb zero, 0(s2) + 76d2: 00 01 + 76d4: 00 02 + 76d6: 04 56 + 76d8: 03 00 09 00 lb zero, 0(s2) + 76dc: 00 01 + 76de: 00 02 + 76e0: 04 56 + 76e2: 03 00 09 00 lb zero, 0(s2) + 76e6: 00 01 + 76e8: 00 02 + 76ea: 04 5e + 76ec: 03 00 09 08 lb zero, 128(s2) + 76f0: 00 01 + 76f2: 00 02 + 76f4: 04 5e + 76f6: 03 00 09 1c lb zero, 448(s2) + 76fa: 00 01 + 76fc: 00 02 + 76fe: 04 5e + 7700: 03 00 09 00 lb zero, 0(s2) + 7704: 00 01 + 7706: 00 02 + 7708: 04 5f + 770a: 03 00 09 04 lb zero, 64(s2) + 770e: 00 01 + 7710: 00 02 + 7712: 04 5f + 7714: 03 00 09 10 lb zero, 256(s2) + 7718: 00 01 + 771a: 00 02 + 771c: 04 5f + 771e: 03 00 09 00 lb zero, 0(s2) + 7722: 00 01 + 7724: 00 02 + 7726: 04 5f + 7728: 03 00 09 00 lb zero, 0(s2) + 772c: 00 01 + 772e: 00 02 + 7730: 04 64 + 7732: 06 03 + 7734: 00 09 + 7736: 08 00 + 7738: 01 00 + 773a: 02 04 + 773c: 68 06 + 773e: 03 00 09 1c lb zero, 448(s2) + 7742: 00 01 + 7744: 00 02 + 7746: 04 68 + 7748: 03 00 09 00 lb zero, 0(s2) + 774c: 00 01 + 774e: 00 02 + 7750: 04 68 + 7752: 03 00 09 10 lb zero, 256(s2) + 7756: 00 01 + 7758: 00 02 + 775a: 04 6e + 775c: 03 00 09 04 lb zero, 64(s2) + 7760: 00 01 + 7762: 00 02 + 7764: 04 6e + 7766: 03 00 09 00 lb zero, 0(s2) + 776a: 00 01 + 776c: 00 02 + 776e: 04 6e + 7770: 03 00 09 00 lb zero, 0(s2) + 7774: 00 01 + 7776: 00 02 + 7778: 04 6e + 777a: 03 00 09 00 lb zero, 0(s2) + 777e: 00 01 + 7780: 00 02 + 7782: 04 6e + 7784: 03 00 09 00 lb zero, 0(s2) + 7788: 00 01 + 778a: 00 02 + 778c: 04 6e + 778e: 03 00 09 20 lb zero, 512(s2) + 7792: 00 01 + 7794: 00 02 + 7796: 04 6e + 7798: 03 00 09 04 lb zero, 64(s2) + 779c: 00 01 + 779e: 00 02 + 77a0: 04 6e + 77a2: 03 00 09 04 lb zero, 64(s2) + 77a6: 00 01 + 77a8: 00 02 + 77aa: 04 6e + 77ac: 03 00 09 00 lb zero, 0(s2) + 77b0: 00 01 + 77b2: 00 02 + 77b4: 04 6e + 77b6: 03 00 09 00 lb zero, 0(s2) + 77ba: 00 01 + 77bc: 00 02 + 77be: 04 6e + 77c0: 03 00 09 00 lb zero, 0(s2) + 77c4: 00 01 + 77c6: 00 02 + 77c8: 04 6e + 77ca: 03 00 09 04 lb zero, 64(s2) + 77ce: 00 01 + 77d0: 00 02 + 77d2: 04 6e + 77d4: 03 00 09 00 lb zero, 0(s2) + 77d8: 00 01 + 77da: 00 02 + 77dc: 04 6e + 77de: 03 01 09 00 lb sp, 0(s2) + 77e2: 00 01 + 77e4: 00 02 + 77e6: 04 6e + 77e8: 03 00 09 00 lb zero, 0(s2) + 77ec: 00 01 + 77ee: 00 02 + 77f0: 04 01 + 77f2: 03 00 09 04 lb zero, 64(s2) + 77f6: 00 01 + 77f8: 00 02 + 77fa: 04 03 + 77fc: 03 00 09 04 lb zero, 64(s2) + 7800: 00 01 + 7802: 00 02 + 7804: 04 03 + 7806: 03 02 09 00 lb tp, 0(s2) + 780a: 00 01 + 780c: 05 01 + 780e: 00 02 + 7810: 04 03 + 7812: 06 03 + 7814: 01 09 + 7816: 00 00 + 7818: 01 05 + 781a: 0a 00 + 781c: 02 04 + 781e: 03 03 7f 09 lb t1, 151(t5) + 7822: 08 00 + 7824: 01 05 + 7826: 01 00 + 7828: 02 04 + 782a: 03 03 01 09 lb t1, 144(sp) + 782e: 10 00 + 7830: 01 05 + 7832: 03 00 03 04 lb zero, 64(t1) + 7836: 8f 01 06 03 + 783a: 7b 09 28 00 + 783e: 01 00 + 7840: 03 04 8f 01 lb s0, 24(t5) + 7844: 03 00 09 00 lb zero, 0(s2) + 7848: 00 01 + 784a: 00 03 + 784c: 04 9d + 784e: 01 06 + 7850: 03 00 09 08 lb zero, 128(s2) + 7854: 00 01 + 7856: 00 03 + 7858: 04 9f + 785a: 01 03 + 785c: 00 09 + 785e: 04 00 + 7860: 01 00 + 7862: 03 04 9f 01 lb s0, 25(t5) + 7866: 03 77 09 08 + 786a: 00 01 + 786c: 00 03 + 786e: 04 9f + 7870: 01 06 + 7872: 03 09 09 08 lb s2, 128(s2) + 7876: 00 01 + 7878: 00 03 + 787a: 04 9f + 787c: 01 03 + 787e: 00 09 + 7880: 00 00 + 7882: 01 00 + 7884: 03 04 9f 01 lb s0, 25(t5) + 7888: 03 00 09 00 lb zero, 0(s2) + 788c: 00 01 + 788e: 00 03 + 7890: 04 a4 + 7892: 01 06 + 7894: 03 00 09 04 lb zero, 64(s2) + 7898: 00 01 + 789a: 00 03 + 789c: 04 a6 + 789e: 01 03 + 78a0: 00 09 + 78a2: 10 00 + 78a4: 01 06 + 78a6: 03 00 09 08 lb zero, 128(s2) + 78aa: 00 01 + 78ac: 03 00 09 00 lb zero, 0(s2) + 78b0: 00 01 + 78b2: 03 00 09 00 lb zero, 0(s2) + 78b6: 00 01 + 78b8: 00 03 + 78ba: 04 b6 + 78bc: 01 03 + 78be: 00 09 + 78c0: 04 00 + 78c2: 01 00 + 78c4: 03 04 b6 01 lb s0, 27(a2) + 78c8: 03 00 09 00 lb zero, 0(s2) + 78cc: 00 01 + 78ce: 00 03 + 78d0: 04 b6 + 78d2: 01 03 + 78d4: 00 09 + 78d6: 00 00 + 78d8: 01 00 + 78da: 03 04 b6 01 lb s0, 27(a2) + 78de: 03 00 09 00 lb zero, 0(s2) + 78e2: 00 01 + 78e4: 00 03 + 78e6: 04 b6 + 78e8: 01 03 + 78ea: 00 09 + 78ec: 00 00 + 78ee: 01 00 + 78f0: 03 04 b6 01 lb s0, 27(a2) + 78f4: 03 00 09 00 lb zero, 0(s2) + 78f8: 00 01 + 78fa: 00 03 + 78fc: 04 b6 + 78fe: 01 03 + 7900: 00 09 + 7902: 00 00 + 7904: 01 00 + 7906: 03 04 b6 01 lb s0, 27(a2) + 790a: 03 00 09 00 lb zero, 0(s2) + 790e: 00 01 + 7910: 00 03 + 7912: 04 b6 + 7914: 01 03 + 7916: 00 09 + 7918: 00 00 + 791a: 01 00 + 791c: 03 04 b6 01 lb s0, 27(a2) + 7920: 03 00 09 00 lb zero, 0(s2) + 7924: 00 01 + 7926: 00 03 + 7928: 04 b6 + 792a: 01 03 + 792c: 00 09 + 792e: 14 00 + 7930: 01 00 + 7932: 03 04 b6 01 lb s0, 27(a2) + 7936: 03 00 09 00 lb zero, 0(s2) + 793a: 00 01 + 793c: 00 03 + 793e: 04 b6 + 7940: 01 03 + 7942: 00 09 + 7944: 00 00 + 7946: 01 00 + 7948: 03 04 b6 01 lb s0, 27(a2) + 794c: 03 00 09 00 lb zero, 0(s2) + 7950: 00 01 + 7952: 00 03 + 7954: 04 b6 + 7956: 01 03 + 7958: 00 09 + 795a: 00 00 + 795c: 01 00 + 795e: 03 04 b6 01 lb s0, 27(a2) + 7962: 03 00 09 00 lb zero, 0(s2) + 7966: 00 01 + 7968: 00 03 + 796a: 04 b6 + 796c: 01 03 + 796e: 00 09 + 7970: 00 00 + 7972: 01 00 + 7974: 03 04 b6 01 lb s0, 27(a2) + 7978: 03 00 09 00 lb zero, 0(s2) + 797c: 00 01 + 797e: 00 03 + 7980: 04 b6 + 7982: 01 03 + 7984: 00 09 + 7986: 00 00 + 7988: 01 00 + 798a: 03 04 b6 01 lb s0, 27(a2) + 798e: 03 00 09 00 lb zero, 0(s2) + 7992: 00 01 + 7994: 00 03 + 7996: 04 b6 + 7998: 01 03 + 799a: 00 09 + 799c: 00 00 + 799e: 01 00 + 79a0: 03 04 d2 01 lb s0, 29(tp) + 79a4: 03 00 09 08 lb zero, 128(s2) + 79a8: 00 01 + 79aa: 00 03 + 79ac: 04 d2 + 79ae: 01 03 + 79b0: 00 09 + 79b2: 1c 00 + 79b4: 01 00 + 79b6: 03 04 d2 01 lb s0, 29(tp) + 79ba: 03 00 09 00 lb zero, 0(s2) + 79be: 00 01 + 79c0: 00 03 + 79c2: 04 ba + 79c4: 04 03 + 79c6: 00 09 + 79c8: 04 00 + 79ca: 01 00 + 79cc: 03 04 ba 04 lb s0, 75(s4) + 79d0: 03 00 09 10 lb zero, 256(s2) + 79d4: 00 01 + 79d6: 00 03 + 79d8: 04 a3 + 79da: 01 03 + 79dc: 00 09 + 79de: 04 00 + 79e0: 01 00 + 79e2: 03 04 a3 01 lb s0, 26(t1) + 79e6: 03 00 09 00 lb zero, 0(s2) + 79ea: 00 01 + 79ec: 00 03 + 79ee: 04 a3 + 79f0: 01 03 + 79f2: 00 09 + 79f4: 00 00 + 79f6: 01 06 + 79f8: 03 77 09 04 + 79fc: 00 01 + 79fe: 00 03 + 7a00: 04 aa + 7a02: 01 06 + 7a04: 03 09 09 08 lb s2, 128(s2) + 7a08: 00 01 + 7a0a: 00 03 + 7a0c: 04 aa + 7a0e: 01 03 + 7a10: 00 09 + 7a12: 00 00 + 7a14: 01 00 + 7a16: 03 04 aa 01 lb s0, 26(s4) + 7a1a: 03 00 09 00 lb zero, 0(s2) + 7a1e: 00 01 + 7a20: 00 03 + 7a22: 04 aa + 7a24: 01 06 + 7a26: 03 77 09 00 + 7a2a: 00 01 + 7a2c: 00 03 + 7a2e: 04 aa + 7a30: 01 03 + 7a32: 09 09 + 7a34: 04 00 + 7a36: 01 00 + 7a38: 03 04 ab 01 lb s0, 26(s6) + 7a3c: 06 03 + 7a3e: 00 09 + 7a40: 04 00 + 7a42: 01 00 + 7a44: 03 04 ba 04 lb s0, 75(s4) + 7a48: 06 03 + 7a4a: 00 09 + 7a4c: 10 00 + 7a4e: 01 00 + 7a50: 03 04 ac 01 lb s0, 26(s8) + 7a54: 06 03 + 7a56: 00 09 + 7a58: 0c 00 + 7a5a: 01 00 + 7a5c: 03 04 ae 01 lb s0, 26(t3) + 7a60: 03 00 09 10 lb zero, 256(s2) + 7a64: 00 01 + 7a66: 00 03 + 7a68: 04 8d + 7a6a: 01 03 + 7a6c: 00 09 + 7a6e: 14 00 + 7a70: 01 00 + 7a72: 03 04 8d 01 lb s0, 24(s10) + 7a76: 03 00 09 00 lb zero, 0(s2) + 7a7a: 00 01 + 7a7c: 00 03 + 7a7e: 04 8d + 7a80: 01 03 + 7a82: 00 09 + 7a84: 00 00 + 7a86: 01 00 + 7a88: 03 04 8d 01 lb s0, 24(s10) + 7a8c: 03 00 09 00 lb zero, 0(s2) + 7a90: 00 01 + 7a92: 00 03 + 7a94: 04 8d + 7a96: 01 03 + 7a98: 00 09 + 7a9a: 10 00 + 7a9c: 01 00 + 7a9e: 03 04 8d 01 lb s0, 24(s10) + 7aa2: 03 00 09 00 lb zero, 0(s2) + 7aa6: 00 01 + 7aa8: 00 03 + 7aaa: 04 8d + 7aac: 01 03 + 7aae: 00 09 + 7ab0: 00 00 + 7ab2: 01 00 + 7ab4: 03 04 8d 01 lb s0, 24(s10) + 7ab8: 03 00 09 00 lb zero, 0(s2) + 7abc: 00 01 + 7abe: 00 03 + 7ac0: 04 8d + 7ac2: 01 03 + 7ac4: 00 09 + 7ac6: 18 00 + 7ac8: 01 00 + 7aca: 03 04 8d 01 lb s0, 24(s10) + 7ace: 03 00 09 00 lb zero, 0(s2) + 7ad2: 00 01 + 7ad4: 00 03 + 7ad6: 04 8d + 7ad8: 01 03 + 7ada: 00 09 + 7adc: 00 00 + 7ade: 01 00 + 7ae0: 03 04 8d 01 lb s0, 24(s10) + 7ae4: 03 00 09 00 lb zero, 0(s2) + 7ae8: 00 01 + 7aea: 00 03 + 7aec: 04 8d + 7aee: 01 03 + 7af0: 00 09 + 7af2: 1c 00 + 7af4: 01 00 + 7af6: 03 04 8d 01 lb s0, 24(s10) + 7afa: 03 00 09 00 lb zero, 0(s2) + 7afe: 00 01 + 7b00: 00 03 + 7b02: 04 8d + 7b04: 01 03 + 7b06: 00 09 + 7b08: 04 00 + 7b0a: 01 00 + 7b0c: 03 04 8d 01 lb s0, 24(s10) + 7b10: 03 00 09 00 lb zero, 0(s2) + 7b14: 00 01 + 7b16: 00 03 + 7b18: 04 8d + 7b1a: 01 03 + 7b1c: 00 09 + 7b1e: 00 00 + 7b20: 01 00 + 7b22: 03 04 8d 01 lb s0, 24(s10) + 7b26: 03 00 09 00 lb zero, 0(s2) + 7b2a: 00 01 + 7b2c: 00 03 + 7b2e: 04 8d + 7b30: 01 03 + 7b32: 00 09 + 7b34: 00 00 + 7b36: 01 00 + 7b38: 03 04 8d 01 lb s0, 24(s10) + 7b3c: 03 00 09 00 lb zero, 0(s2) + 7b40: 00 01 + 7b42: 00 03 + 7b44: 04 8d + 7b46: 01 03 + 7b48: 00 09 + 7b4a: 00 00 + 7b4c: 01 00 + 7b4e: 03 04 8d 01 lb s0, 24(s10) + 7b52: 03 00 09 00 lb zero, 0(s2) + 7b56: 00 01 + 7b58: 00 03 + 7b5a: 04 8d + 7b5c: 01 03 + 7b5e: 00 09 + 7b60: 00 00 + 7b62: 01 00 + 7b64: 03 04 8d 01 lb s0, 24(s10) + 7b68: 03 00 09 00 lb zero, 0(s2) + 7b6c: 00 01 + 7b6e: 00 03 + 7b70: 04 8d + 7b72: 01 03 + 7b74: 00 09 + 7b76: 00 00 + 7b78: 01 00 + 7b7a: 03 04 8d 01 lb s0, 24(s10) + 7b7e: 03 00 09 00 lb zero, 0(s2) + 7b82: 00 01 + 7b84: 00 03 + 7b86: 04 8d + 7b88: 01 03 + 7b8a: 00 09 + 7b8c: 00 00 + 7b8e: 01 00 + 7b90: 03 04 8d 01 lb s0, 24(s10) + 7b94: 03 00 09 00 lb zero, 0(s2) + 7b98: 00 01 + 7b9a: 00 03 + 7b9c: 04 8d + 7b9e: 01 03 + 7ba0: 00 09 + 7ba2: 00 00 + 7ba4: 01 00 + 7ba6: 03 04 8d 01 lb s0, 24(s10) + 7baa: 03 00 09 00 lb zero, 0(s2) + 7bae: 00 01 + 7bb0: 00 03 + 7bb2: 04 8d + 7bb4: 01 03 + 7bb6: 00 09 + 7bb8: 00 00 + 7bba: 01 00 + 7bbc: 03 04 e4 01 lb s0, 30(s0) + 7bc0: 03 00 09 08 lb zero, 128(s2) + 7bc4: 00 01 + 7bc6: 00 03 + 7bc8: 04 e4 + 7bca: 01 03 + 7bcc: 00 09 + 7bce: 1c 00 + 7bd0: 01 00 + 7bd2: 03 04 e4 01 lb s0, 30(s0) + 7bd6: 03 00 09 00 lb zero, 0(s2) + 7bda: 00 01 + 7bdc: 00 03 + 7bde: 04 e5 + 7be0: 01 03 + 7be2: 00 09 + 7be4: 04 00 + 7be6: 01 00 + 7be8: 03 04 e5 01 lb s0, 30(a0) + 7bec: 03 00 09 00 lb zero, 0(s2) + 7bf0: 00 01 + 7bf2: 00 03 + 7bf4: 04 e5 + 7bf6: 01 03 + 7bf8: 00 09 + 7bfa: 00 00 + 7bfc: 01 00 + 7bfe: 03 04 e5 01 lb s0, 30(a0) + 7c02: 03 00 09 00 lb zero, 0(s2) + 7c06: 00 01 + 7c08: 00 03 + 7c0a: 04 e5 + 7c0c: 01 03 + 7c0e: 00 09 + 7c10: 00 00 + 7c12: 01 00 + 7c14: 03 04 e5 01 lb s0, 30(a0) + 7c18: 03 00 09 00 lb zero, 0(s2) + 7c1c: 00 01 + 7c1e: 00 03 + 7c20: 04 e5 + 7c22: 01 03 + 7c24: 00 09 + 7c26: 00 00 + 7c28: 01 06 + 7c2a: 03 00 09 0c lb zero, 192(s2) + 7c2e: 00 01 + 7c30: 03 01 09 0c lb sp, 192(s2) + 7c34: 00 01 + 7c36: 03 7f 09 04 + 7c3a: 00 01 + 7c3c: 00 03 + 7c3e: 04 ea + 7c40: 01 06 + 7c42: 03 00 09 08 lb zero, 128(s2) + 7c46: 00 01 + 7c48: 00 03 + 7c4a: 04 ea + 7c4c: 01 03 + 7c4e: 00 09 + 7c50: 00 00 + 7c52: 01 00 + 7c54: 03 04 ed 01 lb s0, 30(s10) + 7c58: 06 03 + 7c5a: 00 09 + 7c5c: 04 00 + 7c5e: 01 00 + 7c60: 03 04 ee 01 lb s0, 30(t3) + 7c64: 03 00 09 08 lb zero, 128(s2) + 7c68: 00 01 + 7c6a: 00 03 + 7c6c: 04 f5 + 7c6e: 01 06 + 7c70: 03 00 09 04 lb zero, 64(s2) + 7c74: 00 01 + 7c76: 00 03 + 7c78: 04 f5 + 7c7a: 01 03 + 7c7c: 00 09 + 7c7e: 00 00 + 7c80: 01 00 + 7c82: 03 04 f5 01 lb s0, 31(a0) + 7c86: 06 03 + 7c88: 01 09 + 7c8a: 18 00 + 7c8c: 01 00 + 7c8e: 03 04 f5 01 lb s0, 31(a0) + 7c92: 03 7f 09 04 + 7c96: 00 01 + 7c98: 00 03 + 7c9a: 04 98 + 7c9c: 02 03 + 7c9e: 00 09 + 7ca0: 04 00 + 7ca2: 01 00 + 7ca4: 03 04 f1 01 lb s0, 31(sp) + 7ca8: 03 00 09 08 lb zero, 128(s2) + 7cac: 00 01 + 7cae: 00 03 + 7cb0: 04 f2 + 7cb2: 01 03 + 7cb4: 00 09 + 7cb6: 08 00 + 7cb8: 01 00 + 7cba: 03 04 97 02 lb s0, 41(a4) + 7cbe: 06 03 + 7cc0: 00 09 + 7cc2: 04 00 + 7cc4: 01 00 + 7cc6: 03 04 97 02 lb s0, 41(a4) + 7cca: 03 00 09 00 lb zero, 0(s2) + 7cce: 00 01 + 7cd0: 00 03 + 7cd2: 04 98 + 7cd4: 02 06 + 7cd6: 03 01 09 10 lb sp, 256(s2) + 7cda: 00 01 + 7cdc: 00 03 + 7cde: 04 94 + 7ce0: 02 03 + 7ce2: 7f 09 08 00 + 7ce6: 01 00 + 7ce8: 03 04 95 02 lb s0, 41(a0) + 7cec: 03 00 09 08 lb zero, 128(s2) + 7cf0: 00 01 + 7cf2: 00 02 + 7cf4: 04 0d + 7cf6: 06 03 + 7cf8: 00 09 + 7cfa: 08 00 + 7cfc: 01 00 + 7cfe: 02 04 + 7d00: 0d 03 + 7d02: 00 09 + 7d04: 00 00 + 7d06: 01 00 + 7d08: 03 04 9d 02 lb s0, 41(s10) + 7d0c: 03 00 09 04 lb zero, 64(s2) + 7d10: 00 01 + 7d12: 00 03 + 7d14: 04 9d + 7d16: 02 03 + 7d18: 00 09 + 7d1a: 00 00 + 7d1c: 01 00 + 7d1e: 03 04 9d 02 lb s0, 41(s10) + 7d22: 03 00 09 00 lb zero, 0(s2) + 7d26: 00 01 + 7d28: 00 03 + 7d2a: 04 9f + 7d2c: 02 03 + 7d2e: 00 09 + 7d30: 10 00 + 7d32: 01 00 + 7d34: 03 04 a1 02 lb s0, 42(sp) + 7d38: 03 00 09 1c lb zero, 448(s2) + 7d3c: 00 01 + 7d3e: 00 03 + 7d40: 04 a1 + 7d42: 02 03 + 7d44: 00 09 + 7d46: 00 00 + 7d48: 01 00 + 7d4a: 03 04 a3 02 lb s0, 42(t1) + 7d4e: 06 03 + 7d50: 00 09 + 7d52: 0c 00 + 7d54: 01 00 + 7d56: 03 04 a5 02 lb s0, 42(a0) + 7d5a: 03 00 09 10 lb zero, 256(s2) + 7d5e: 00 01 + 7d60: 03 00 09 08 lb zero, 128(s2) + 7d64: 00 01 + 7d66: 00 03 + 7d68: 04 a9 + 7d6a: 02 06 + 7d6c: 03 00 09 04 lb zero, 64(s2) + 7d70: 00 01 + 7d72: 00 03 + 7d74: 04 a9 + 7d76: 02 03 + 7d78: 00 09 + 7d7a: 00 00 + 7d7c: 01 00 + 7d7e: 03 04 a9 02 lb s0, 42(s2) + 7d82: 03 00 09 10 lb zero, 256(s2) + 7d86: 00 01 + 7d88: 00 03 + 7d8a: 04 a2 + 7d8c: 02 03 + 7d8e: 00 09 + 7d90: 04 00 + 7d92: 01 00 + 7d94: 03 04 a2 02 lb s0, 42(tp) + 7d98: 03 00 09 00 lb zero, 0(s2) + 7d9c: 00 01 + 7d9e: 00 03 + 7da0: 04 a2 + 7da2: 02 03 + 7da4: 00 09 + 7da6: 04 00 + 7da8: 01 00 + 7daa: 03 04 ab 02 lb s0, 42(s6) + 7dae: 03 00 09 04 lb zero, 64(s2) + 7db2: 00 01 + 7db4: 00 03 + 7db6: 04 ab + 7db8: 02 03 + 7dba: 00 09 + 7dbc: 00 00 + 7dbe: 01 00 + 7dc0: 03 04 ab 02 lb s0, 42(s6) + 7dc4: 03 00 09 00 lb zero, 0(s2) + 7dc8: 00 01 + 7dca: 00 03 + 7dcc: 04 ab + 7dce: 02 03 + 7dd0: 00 09 + 7dd2: 00 00 + 7dd4: 01 00 + 7dd6: 03 04 ab 02 lb s0, 42(s6) + 7dda: 03 00 09 00 lb zero, 0(s2) + 7dde: 00 01 + 7de0: 00 03 + 7de2: 04 ab + 7de4: 02 03 + 7de6: 00 09 + 7de8: 04 00 + 7dea: 01 00 + 7dec: 03 04 ab 02 lb s0, 42(s6) + 7df0: 03 00 09 00 lb zero, 0(s2) + 7df4: 00 01 + 7df6: 00 03 + 7df8: 04 ab + 7dfa: 02 03 + 7dfc: 00 09 + 7dfe: 04 00 + 7e00: 01 00 + 7e02: 03 04 ab 02 lb s0, 42(s6) + 7e06: 03 00 09 08 lb zero, 128(s2) + 7e0a: 00 01 + 7e0c: 00 03 + 7e0e: 04 ab + 7e10: 02 03 + 7e12: 00 09 + 7e14: 04 00 + 7e16: 01 00 + 7e18: 03 04 ad 02 lb s0, 42(s10) + 7e1c: 06 03 + 7e1e: 00 09 + 7e20: 08 00 + 7e22: 01 00 + 7e24: 03 04 b2 02 lb s0, 43(tp) + 7e28: 03 00 09 08 lb zero, 128(s2) + 7e2c: 00 01 + 7e2e: 00 03 + 7e30: 04 b2 + 7e32: 02 06 + 7e34: 03 00 09 04 lb zero, 64(s2) + 7e38: 00 01 + 7e3a: 00 03 + 7e3c: 04 b2 + 7e3e: 02 03 + 7e40: 00 09 + 7e42: 04 00 + 7e44: 01 00 + 7e46: 03 04 b2 02 lb s0, 43(tp) + 7e4a: 03 00 09 04 lb zero, 64(s2) + 7e4e: 00 01 + 7e50: 00 03 + 7e52: 04 b2 + 7e54: 02 03 + 7e56: 00 09 + 7e58: 04 00 + 7e5a: 01 00 + 7e5c: 03 04 b3 02 lb s0, 43(t1) + 7e60: 06 03 + 7e62: 00 09 + 7e64: 04 00 + 7e66: 01 00 + 7e68: 03 04 b8 02 lb s0, 43(a6) + 7e6c: 06 03 + 7e6e: 00 09 + 7e70: 08 00 + 7e72: 01 00 + 7e74: 03 04 b8 02 lb s0, 43(a6) + 7e78: 03 00 09 10 lb zero, 256(s2) + 7e7c: 00 01 + 7e7e: 00 03 + 7e80: 04 b8 + 7e82: 02 03 + 7e84: 00 09 + 7e86: 04 00 + 7e88: 01 00 + 7e8a: 03 04 b8 02 lb s0, 43(a6) + 7e8e: 03 00 09 04 lb zero, 64(s2) + 7e92: 00 01 + 7e94: 00 03 + 7e96: 04 b8 + 7e98: 02 03 + 7e9a: 00 09 + 7e9c: 04 00 + 7e9e: 01 00 + 7ea0: 03 04 b8 02 lb s0, 43(a6) + 7ea4: 03 00 09 00 lb zero, 0(s2) + 7ea8: 00 01 + 7eaa: 00 03 + 7eac: 04 8e + 7eae: 03 06 03 7f lb a2, 2032(t1) + 7eb2: 09 00 + 7eb4: 00 01 + 7eb6: 00 03 + 7eb8: 04 8e + 7eba: 03 03 01 09 lb t1, 144(sp) + 7ebe: 04 00 + 7ec0: 01 00 + 7ec2: 03 04 ac 02 lb s0, 42(s8) + 7ec6: 06 03 + 7ec8: 00 09 + 7eca: 04 00 + 7ecc: 01 00 + 7ece: 03 04 bc 02 lb s0, 43(s8) + 7ed2: 03 00 09 0c lb zero, 192(s2) + 7ed6: 00 01 + 7ed8: 00 03 + 7eda: 04 bc + 7edc: 02 03 + 7ede: 00 09 + 7ee0: 00 00 + 7ee2: 01 00 + 7ee4: 03 04 be 02 lb s0, 43(t3) + 7ee8: 06 03 + 7eea: 00 09 + 7eec: 14 00 + 7eee: 01 00 + 7ef0: 03 04 c2 02 lb s0, 44(tp) + 7ef4: 06 03 + 7ef6: 00 09 + 7ef8: 10 00 + 7efa: 01 00 + 7efc: 03 04 c2 02 lb s0, 44(tp) + 7f00: 03 00 09 00 lb zero, 0(s2) + 7f04: 00 01 + 7f06: 00 03 + 7f08: 04 a0 + 7f0a: 02 03 + 7f0c: 00 09 + 7f0e: 10 00 + 7f10: 01 00 + 7f12: 03 04 c7 02 lb s0, 44(a4) + 7f16: 03 00 09 0c lb zero, 192(s2) + 7f1a: 00 01 + 7f1c: 00 03 + 7f1e: 04 c7 + 7f20: 02 03 + 7f22: 00 09 + 7f24: 00 00 + 7f26: 01 00 + 7f28: 03 04 c7 02 lb s0, 44(a4) + 7f2c: 06 03 + 7f2e: 77 09 0c 00 + 7f32: 01 00 + 7f34: 03 04 c7 02 lb s0, 44(a4) + 7f38: 03 09 09 04 lb s2, 64(s2) + 7f3c: 00 01 + 7f3e: 00 03 + 7f40: 04 c9 + 7f42: 02 03 + 7f44: 00 09 + 7f46: 04 00 + 7f48: 01 00 + 7f4a: 03 04 c9 02 lb s0, 44(s2) + 7f4e: 03 77 09 08 + 7f52: 00 01 + 7f54: 00 03 + 7f56: 04 cd + 7f58: 02 06 + 7f5a: 03 09 09 08 lb s2, 128(s2) + 7f5e: 00 01 + 7f60: 00 03 + 7f62: 04 cd + 7f64: 02 03 + 7f66: 00 09 + 7f68: 00 00 + 7f6a: 01 00 + 7f6c: 03 04 c6 02 lb s0, 44(a2) + 7f70: 03 00 09 14 lb zero, 320(s2) + 7f74: 00 01 + 7f76: 00 03 + 7f78: 04 c6 + 7f7a: 02 03 + 7f7c: 00 09 + 7f7e: 10 00 + 7f80: 01 00 + 7f82: 03 04 d0 02 lb s0, 45(zero) + 7f86: 03 00 09 0c lb zero, 192(s2) + 7f8a: 00 01 + 7f8c: 00 03 + 7f8e: 04 d0 + 7f90: 02 03 + 7f92: 00 09 + 7f94: 00 00 + 7f96: 01 00 + 7f98: 03 04 d0 02 lb s0, 45(zero) + 7f9c: 03 00 09 00 lb zero, 0(s2) + 7fa0: 00 01 + 7fa2: 00 03 + 7fa4: 04 d0 + 7fa6: 02 03 + 7fa8: 00 09 + 7faa: 00 00 + 7fac: 01 00 + 7fae: 03 04 d0 02 lb s0, 45(zero) + 7fb2: 03 00 09 00 lb zero, 0(s2) + 7fb6: 00 01 + 7fb8: 00 03 + 7fba: 04 d0 + 7fbc: 02 03 + 7fbe: 00 09 + 7fc0: 00 00 + 7fc2: 01 00 + 7fc4: 03 04 d0 02 lb s0, 45(zero) + 7fc8: 03 00 09 00 lb zero, 0(s2) + 7fcc: 00 01 + 7fce: 00 03 + 7fd0: 04 d0 + 7fd2: 02 03 + 7fd4: 00 09 + 7fd6: 04 00 + 7fd8: 01 00 + 7fda: 03 04 d0 02 lb s0, 45(zero) + 7fde: 03 00 09 00 lb zero, 0(s2) + 7fe2: 00 01 + 7fe4: 00 03 + 7fe6: 04 d0 + 7fe8: 02 03 + 7fea: 00 09 + 7fec: 00 00 + 7fee: 01 00 + 7ff0: 03 04 d2 02 lb s0, 45(tp) + 7ff4: 03 00 09 08 lb zero, 128(s2) + 7ff8: 00 01 + 7ffa: 00 03 + 7ffc: 04 d5 + 7ffe: 02 03 + 8000: 00 09 + 8002: 04 00 + 8004: 01 06 + 8006: 03 00 09 0c lb zero, 192(s2) + 800a: 00 01 + 800c: 00 03 + 800e: 04 da + 8010: 02 06 + 8012: 03 00 09 0c lb zero, 192(s2) + 8016: 00 01 + 8018: 00 03 + 801a: 04 da + 801c: 02 03 + 801e: 00 09 + 8020: 14 00 + 8022: 01 00 + 8024: 03 04 da 02 lb s0, 45(s4) + 8028: 03 00 09 00 lb zero, 0(s2) + 802c: 00 01 + 802e: 00 03 + 8030: 04 d4 + 8032: 02 03 + 8034: 00 09 + 8036: 1c 00 + 8038: 01 00 + 803a: 03 04 d4 02 lb s0, 45(s0) + 803e: 03 00 09 14 lb zero, 320(s2) + 8042: 00 01 + 8044: 00 03 + 8046: 04 d7 + 8048: 02 06 + 804a: 03 00 09 04 lb zero, 64(s2) + 804e: 00 01 + 8050: 00 03 + 8052: 04 d7 + 8054: 02 06 + 8056: 03 00 09 14 lb zero, 320(s2) + 805a: 00 01 + 805c: 00 03 + 805e: 04 d7 + 8060: 02 03 + 8062: 00 09 + 8064: 10 00 + 8066: 01 00 + 8068: 03 04 db 02 lb s0, 45(s6) + 806c: 03 00 09 08 lb zero, 128(s2) + 8070: 00 01 + 8072: 00 03 + 8074: 04 de + 8076: 02 06 + 8078: 03 00 09 08 lb zero, 128(s2) + 807c: 00 01 + 807e: 00 03 + 8080: 04 de + 8082: 02 06 + 8084: 03 00 09 18 lb zero, 384(s2) + 8088: 00 01 + 808a: 00 03 + 808c: 04 e0 + 808e: 02 06 + 8090: 03 00 09 08 lb zero, 128(s2) + 8094: 00 01 + 8096: 00 03 + 8098: 04 dd + 809a: 02 06 + 809c: 03 00 09 08 lb zero, 128(s2) + 80a0: 00 01 + 80a2: 00 03 + 80a4: 04 dd + 80a6: 02 03 + 80a8: 00 09 + 80aa: 20 00 + 80ac: 01 00 + 80ae: 03 04 e1 02 lb s0, 46(sp) + 80b2: 03 00 09 08 lb zero, 128(s2) + 80b6: 00 01 + 80b8: 00 03 + 80ba: 04 e1 + 80bc: 02 03 + 80be: 00 09 + 80c0: 0c 00 + 80c2: 01 00 + 80c4: 03 04 e0 02 lb s0, 46(zero) + 80c8: 03 00 09 04 lb zero, 64(s2) + 80cc: 00 01 + 80ce: 00 03 + 80d0: 04 e2 + 80d2: 02 03 + 80d4: 00 09 + 80d6: 04 00 + 80d8: 01 00 + 80da: 03 04 e2 02 lb s0, 46(tp) + 80de: 03 00 09 00 lb zero, 0(s2) + 80e2: 00 01 + 80e4: 00 03 + 80e6: 04 e2 + 80e8: 02 03 + 80ea: 00 09 + 80ec: 00 00 + 80ee: 01 06 + 80f0: 03 00 09 0c lb zero, 192(s2) + 80f4: 00 01 + 80f6: 06 03 + 80f8: 00 09 + 80fa: 04 00 + 80fc: 01 03 + 80fe: 00 09 + 8100: 00 00 + 8102: 01 03 + 8104: 00 09 + 8106: 00 00 + 8108: 01 03 + 810a: 00 09 + 810c: 00 00 + 810e: 01 03 + 8110: 00 09 + 8112: 00 00 + 8114: 01 03 + 8116: 00 09 + 8118: 0c 00 + 811a: 01 03 + 811c: 00 09 + 811e: 00 00 + 8120: 01 03 + 8122: 00 09 + 8124: 04 00 + 8126: 01 03 + 8128: 00 09 + 812a: 08 00 + 812c: 01 03 + 812e: 00 09 + 8130: 04 00 + 8132: 01 00 + 8134: 03 04 e7 02 lb s0, 46(a4) + 8138: 06 03 + 813a: 00 09 + 813c: 08 00 + 813e: 01 00 + 8140: 03 04 ec 02 lb s0, 46(s8) + 8144: 03 00 09 08 lb zero, 128(s2) + 8148: 00 01 + 814a: 00 03 + 814c: 04 ec + 814e: 02 06 + 8150: 03 00 09 04 lb zero, 64(s2) + 8154: 00 01 + 8156: 00 03 + 8158: 04 ec + 815a: 02 03 + 815c: 00 09 + 815e: 0c 00 + 8160: 01 00 + 8162: 03 04 ec 02 lb s0, 46(s8) + 8166: 03 00 09 04 lb zero, 64(s2) + 816a: 00 01 + 816c: 00 03 + 816e: 04 ec + 8170: 02 03 + 8172: 00 09 + 8174: 04 00 + 8176: 01 00 + 8178: 03 04 ed 02 lb s0, 46(s10) + 817c: 06 03 + 817e: 00 09 + 8180: 04 00 + 8182: 01 00 + 8184: 03 04 f2 02 lb s0, 47(tp) + 8188: 06 03 + 818a: 00 09 + 818c: 08 00 + 818e: 01 00 + 8190: 03 04 f2 02 lb s0, 47(tp) + 8194: 03 00 09 18 lb zero, 384(s2) + 8198: 00 01 + 819a: 00 03 + 819c: 04 f2 + 819e: 02 03 + 81a0: 00 09 + 81a2: 04 00 + 81a4: 01 00 + 81a6: 03 04 f2 02 lb s0, 47(tp) + 81aa: 03 00 09 04 lb zero, 64(s2) + 81ae: 00 01 + 81b0: 00 03 + 81b2: 04 f2 + 81b4: 02 03 + 81b6: 00 09 + 81b8: 00 00 + 81ba: 01 00 + 81bc: 03 04 f2 02 lb s0, 47(tp) + 81c0: 06 03 + 81c2: 7e 09 + 81c4: 00 00 + 81c6: 01 00 + 81c8: 03 04 8f 03 lb s0, 56(t5) + 81cc: 06 03 + 81ce: 02 09 + 81d0: 04 00 + 81d2: 01 00 + 81d4: 03 04 df 04 lb s0, 77(t5) + 81d8: 03 00 09 0c lb zero, 192(s2) + 81dc: 00 01 + 81de: 00 03 + 81e0: 04 df + 81e2: 04 03 + 81e4: 00 09 + 81e6: 00 00 + 81e8: 01 00 + 81ea: 03 04 9e 02 lb s0, 41(t3) + 81ee: 03 00 09 18 lb zero, 384(s2) + 81f2: 00 01 + 81f4: 00 03 + 81f6: 04 f3 + 81f8: 02 03 + 81fa: 00 09 + 81fc: 10 00 + 81fe: 01 00 + 8200: 03 04 f3 02 lb s0, 47(t1) + 8204: 03 00 09 04 lb zero, 64(s2) + 8208: 00 01 + 820a: 00 03 + 820c: 04 f3 + 820e: 02 03 + 8210: 00 09 + 8212: 00 00 + 8214: 01 00 + 8216: 03 04 f3 02 lb s0, 47(t1) + 821a: 03 00 09 00 lb zero, 0(s2) + 821e: 00 01 + 8220: 00 03 + 8222: 04 f5 + 8224: 02 03 + 8226: 00 09 + 8228: 04 00 + 822a: 01 00 + 822c: 03 04 f7 02 lb s0, 47(a4) + 8230: 03 00 09 1c lb zero, 448(s2) + 8234: 00 01 + 8236: 00 03 + 8238: 04 f7 + 823a: 02 03 + 823c: 00 09 + 823e: 00 00 + 8240: 01 00 + 8242: 03 04 f9 02 lb s0, 47(s2) + 8246: 06 03 + 8248: 00 09 + 824a: 0c 00 + 824c: 01 00 + 824e: 03 04 fb 02 lb s0, 47(s6) + 8252: 03 00 09 10 lb zero, 256(s2) + 8256: 00 01 + 8258: 03 00 09 08 lb zero, 128(s2) + 825c: 00 01 + 825e: 00 03 + 8260: 04 ff + 8262: 02 06 + 8264: 03 00 09 04 lb zero, 64(s2) + 8268: 00 01 + 826a: 00 03 + 826c: 04 ff + 826e: 02 03 + 8270: 00 09 + 8272: 00 00 + 8274: 01 00 + 8276: 03 04 ff 02 lb s0, 47(t5) + 827a: 03 00 09 10 lb zero, 256(s2) + 827e: 00 01 + 8280: 00 03 + 8282: 04 f8 + 8284: 02 03 + 8286: 00 09 + 8288: 08 00 + 828a: 01 00 + 828c: 03 04 f8 02 lb s0, 47(a6) + 8290: 03 00 09 00 lb zero, 0(s2) + 8294: 00 01 + 8296: 00 03 + 8298: 04 f8 + 829a: 02 03 + 829c: 00 09 + 829e: 04 00 + 82a0: 01 00 + 82a2: 03 04 81 03 lb s0, 56(sp) + 82a6: 03 00 09 04 lb zero, 64(s2) + 82aa: 00 01 + 82ac: 00 03 + 82ae: 04 81 + 82b0: 03 03 00 09 lb t1, 144(zero) + 82b4: 00 00 + 82b6: 01 00 + 82b8: 03 04 81 03 lb s0, 56(sp) + 82bc: 03 00 09 00 lb zero, 0(s2) + 82c0: 00 01 + 82c2: 00 03 + 82c4: 04 81 + 82c6: 03 03 00 09 lb t1, 144(zero) + 82ca: 00 00 + 82cc: 01 00 + 82ce: 03 04 81 03 lb s0, 56(sp) + 82d2: 03 00 09 00 lb zero, 0(s2) + 82d6: 00 01 + 82d8: 00 03 + 82da: 04 81 + 82dc: 03 03 00 09 lb t1, 144(zero) + 82e0: 04 00 + 82e2: 01 00 + 82e4: 03 04 81 03 lb s0, 56(sp) + 82e8: 03 00 09 00 lb zero, 0(s2) + 82ec: 00 01 + 82ee: 00 03 + 82f0: 04 81 + 82f2: 03 03 00 09 lb t1, 144(zero) + 82f6: 04 00 + 82f8: 01 00 + 82fa: 03 04 81 03 lb s0, 56(sp) + 82fe: 03 00 09 08 lb zero, 128(s2) + 8302: 00 01 + 8304: 00 03 + 8306: 04 81 + 8308: 03 03 00 09 lb t1, 144(zero) + 830c: 04 00 + 830e: 01 00 + 8310: 03 04 83 03 lb s0, 56(t1) + 8314: 06 03 + 8316: 00 09 + 8318: 08 00 + 831a: 01 00 + 831c: 03 04 88 03 lb s0, 56(a6) + 8320: 03 00 09 08 lb zero, 128(s2) + 8324: 00 01 + 8326: 00 03 + 8328: 04 88 + 832a: 03 06 03 00 lb a2, 0(t1) + 832e: 09 04 + 8330: 00 01 + 8332: 00 03 + 8334: 04 88 + 8336: 03 03 00 09 lb t1, 144(zero) + 833a: 04 00 + 833c: 01 00 + 833e: 03 04 88 03 lb s0, 56(a6) + 8342: 03 00 09 04 lb zero, 64(s2) + 8346: 00 01 + 8348: 00 03 + 834a: 04 88 + 834c: 03 03 00 09 lb t1, 144(zero) + 8350: 04 00 + 8352: 01 00 + 8354: 03 04 89 03 lb s0, 56(s2) + 8358: 06 03 + 835a: 00 09 + 835c: 04 00 + 835e: 01 00 + 8360: 03 04 8e 03 lb s0, 56(t3) + 8364: 06 03 + 8366: 00 09 + 8368: 08 00 + 836a: 01 00 + 836c: 03 04 8e 03 lb s0, 56(t3) + 8370: 03 00 09 10 lb zero, 256(s2) + 8374: 00 01 + 8376: 00 03 + 8378: 04 8e + 837a: 03 03 00 09 lb t1, 144(zero) + 837e: 04 00 + 8380: 01 00 + 8382: 03 04 8e 03 lb s0, 56(t3) + 8386: 03 00 09 04 lb zero, 64(s2) + 838a: 00 01 + 838c: 00 03 + 838e: 04 8e + 8390: 03 03 00 09 lb t1, 144(zero) + 8394: 04 00 + 8396: 01 00 + 8398: 03 04 8e 03 lb s0, 56(t3) + 839c: 03 00 09 00 lb zero, 0(s2) + 83a0: 00 01 + 83a2: 00 03 + 83a4: 04 82 + 83a6: 03 03 00 09 lb t1, 144(zero) + 83aa: 08 00 + 83ac: 01 00 + 83ae: 03 04 92 03 lb s0, 57(tp) + 83b2: 03 00 09 0c lb zero, 192(s2) + 83b6: 00 01 + 83b8: 00 03 + 83ba: 04 92 + 83bc: 03 03 00 09 lb t1, 144(zero) + 83c0: 00 00 + 83c2: 01 00 + 83c4: 03 04 94 03 lb s0, 57(s0) + 83c8: 06 03 + 83ca: 00 09 + 83cc: 14 00 + 83ce: 01 00 + 83d0: 03 04 98 03 lb s0, 57(a6) + 83d4: 06 03 + 83d6: 00 09 + 83d8: 10 00 + 83da: 01 00 + 83dc: 03 04 98 03 lb s0, 57(a6) + 83e0: 03 00 09 00 lb zero, 0(s2) + 83e4: 00 01 + 83e6: 00 03 + 83e8: 04 98 + 83ea: 03 03 00 09 lb t1, 144(zero) + 83ee: 10 00 + 83f0: 01 00 + 83f2: 03 04 a3 03 lb s0, 58(t1) + 83f6: 06 03 + 83f8: 00 09 + 83fa: 00 00 + 83fc: 01 00 + 83fe: 03 04 f6 02 lb s0, 47(a2) + 8402: 06 03 + 8404: 00 09 + 8406: 08 00 + 8408: 01 00 + 840a: 03 04 9d 03 lb s0, 57(s10) + 840e: 03 00 09 0c lb zero, 192(s2) + 8412: 00 01 + 8414: 00 03 + 8416: 04 9d + 8418: 03 03 00 09 lb t1, 144(zero) + 841c: 00 00 + 841e: 01 00 + 8420: 03 04 9d 03 lb s0, 57(s10) + 8424: 06 03 + 8426: 77 09 0c 00 + 842a: 01 00 + 842c: 03 04 9d 03 lb s0, 57(s10) + 8430: 03 09 09 04 lb s2, 64(s2) + 8434: 00 01 + 8436: 00 03 + 8438: 04 9f + 843a: 03 03 00 09 lb t1, 144(zero) + 843e: 04 00 + 8440: 01 00 + 8442: 03 04 9f 03 lb s0, 57(t5) + 8446: 03 77 09 08 + 844a: 00 01 + 844c: 00 03 + 844e: 04 a3 + 8450: 03 06 03 09 lb a2, 144(t1) + 8454: 09 08 + 8456: 00 01 + 8458: 00 03 + 845a: 04 a3 + 845c: 03 03 00 09 lb t1, 144(zero) + 8460: 00 00 + 8462: 01 00 + 8464: 03 04 a3 03 lb s0, 58(t1) + 8468: 03 00 09 10 lb zero, 256(s2) + 846c: 00 01 + 846e: 00 03 + 8470: 04 9c + 8472: 03 03 00 09 lb t1, 144(zero) + 8476: 08 00 + 8478: 01 00 + 847a: 03 04 9c 03 lb s0, 57(s8) + 847e: 03 00 09 10 lb zero, 256(s2) + 8482: 00 01 + 8484: 00 03 + 8486: 04 a6 + 8488: 03 03 00 09 lb t1, 144(zero) + 848c: 08 00 + 848e: 01 00 + 8490: 03 04 a6 03 lb s0, 58(a2) + 8494: 03 00 09 00 lb zero, 0(s2) + 8498: 00 01 + 849a: 00 03 + 849c: 04 a6 + 849e: 03 03 00 09 lb t1, 144(zero) + 84a2: 00 00 + 84a4: 01 00 + 84a6: 03 04 a6 03 lb s0, 58(a2) + 84aa: 03 00 09 00 lb zero, 0(s2) + 84ae: 00 01 + 84b0: 00 03 + 84b2: 04 a6 + 84b4: 03 03 00 09 lb t1, 144(zero) + 84b8: 00 00 + 84ba: 01 00 + 84bc: 03 04 a6 03 lb s0, 58(a2) + 84c0: 03 00 09 00 lb zero, 0(s2) + 84c4: 00 01 + 84c6: 00 03 + 84c8: 04 a6 + 84ca: 03 03 00 09 lb t1, 144(zero) + 84ce: 00 00 + 84d0: 01 00 + 84d2: 03 04 a6 03 lb s0, 58(a2) + 84d6: 03 00 09 08 lb zero, 128(s2) + 84da: 00 01 + 84dc: 00 03 + 84de: 04 a6 + 84e0: 03 03 00 09 lb t1, 144(zero) + 84e4: 00 00 + 84e6: 01 00 + 84e8: 03 04 a6 03 lb s0, 58(a2) + 84ec: 03 00 09 00 lb zero, 0(s2) + 84f0: 00 01 + 84f2: 00 03 + 84f4: 04 a8 + 84f6: 03 03 00 09 lb t1, 144(zero) + 84fa: 08 00 + 84fc: 01 00 + 84fe: 03 04 ab 03 lb s0, 58(s6) + 8502: 03 00 09 10 lb zero, 256(s2) + 8506: 00 01 + 8508: 06 03 + 850a: 00 09 + 850c: 0c 00 + 850e: 01 00 + 8510: 03 04 b0 03 lb s0, 59(zero) + 8514: 06 03 + 8516: 00 09 + 8518: 0c 00 + 851a: 01 00 + 851c: 03 04 b0 03 lb s0, 59(zero) + 8520: 03 00 09 14 lb zero, 320(s2) + 8524: 00 01 + 8526: 00 03 + 8528: 04 b0 + 852a: 03 03 00 09 lb t1, 144(zero) + 852e: 00 00 + 8530: 01 00 + 8532: 03 04 aa 03 lb s0, 58(s4) + 8536: 03 00 09 1c lb zero, 448(s2) + 853a: 00 01 + 853c: 00 03 + 853e: 04 aa + 8540: 03 03 00 09 lb t1, 144(zero) + 8544: 14 00 + 8546: 01 00 + 8548: 03 04 ad 03 lb s0, 58(s10) + 854c: 06 03 + 854e: 00 09 + 8550: 04 00 + 8552: 01 00 + 8554: 03 04 ad 03 lb s0, 58(s10) + 8558: 06 03 + 855a: 00 09 + 855c: 24 00 + 855e: 01 00 + 8560: 03 04 ad 03 lb s0, 58(s10) + 8564: 03 00 09 08 lb zero, 128(s2) + 8568: 00 01 + 856a: 00 03 + 856c: 04 b1 + 856e: 03 03 00 09 lb t1, 144(zero) + 8572: 08 00 + 8574: 01 00 + 8576: 03 04 b4 03 lb s0, 59(s0) + 857a: 06 03 + 857c: 00 09 + 857e: 08 00 + 8580: 01 00 + 8582: 03 04 b4 03 lb s0, 59(s0) + 8586: 06 03 + 8588: 00 09 + 858a: 18 00 + 858c: 01 00 + 858e: 03 04 b6 03 lb s0, 59(a2) + 8592: 06 03 + 8594: 00 09 + 8596: 08 00 + 8598: 01 00 + 859a: 03 04 b3 03 lb s0, 59(t1) + 859e: 06 03 + 85a0: 00 09 + 85a2: 08 00 + 85a4: 01 00 + 85a6: 03 04 b3 03 lb s0, 59(t1) + 85aa: 03 00 09 20 lb zero, 512(s2) + 85ae: 00 01 + 85b0: 00 03 + 85b2: 04 b7 + 85b4: 03 03 00 09 lb t1, 144(zero) + 85b8: 08 00 + 85ba: 01 00 + 85bc: 03 04 b7 03 lb s0, 59(a4) + 85c0: 03 00 09 0c lb zero, 192(s2) + 85c4: 00 01 + 85c6: 00 03 + 85c8: 04 b6 + 85ca: 03 03 00 09 lb t1, 144(zero) + 85ce: 04 00 + 85d0: 01 00 + 85d2: 03 04 b8 03 lb s0, 59(a6) + 85d6: 03 00 09 04 lb zero, 64(s2) + 85da: 00 01 + 85dc: 00 03 + 85de: 04 b8 + 85e0: 03 03 00 09 lb t1, 144(zero) + 85e4: 00 00 + 85e6: 01 00 + 85e8: 03 04 b8 03 lb s0, 59(a6) + 85ec: 03 00 09 00 lb zero, 0(s2) + 85f0: 00 01 + 85f2: 06 03 + 85f4: 00 09 + 85f6: 0c 00 + 85f8: 01 06 + 85fa: 03 00 09 04 lb zero, 64(s2) + 85fe: 00 01 + 8600: 03 00 09 00 lb zero, 0(s2) + 8604: 00 01 + 8606: 03 00 09 00 lb zero, 0(s2) + 860a: 00 01 + 860c: 03 00 09 00 lb zero, 0(s2) + 8610: 00 01 + 8612: 03 00 09 00 lb zero, 0(s2) + 8616: 00 01 + 8618: 03 00 09 0c lb zero, 192(s2) + 861c: 00 01 + 861e: 03 00 09 00 lb zero, 0(s2) + 8622: 00 01 + 8624: 03 00 09 04 lb zero, 64(s2) + 8628: 00 01 + 862a: 03 00 09 08 lb zero, 128(s2) + 862e: 00 01 + 8630: 03 00 09 04 lb zero, 64(s2) + 8634: 00 01 + 8636: 00 03 + 8638: 04 bd + 863a: 03 06 03 00 lb a2, 0(t1) + 863e: 09 08 + 8640: 00 01 + 8642: 00 03 + 8644: 04 c2 + 8646: 03 03 00 09 lb t1, 144(zero) + 864a: 08 00 + 864c: 01 00 + 864e: 03 04 c2 03 lb s0, 60(tp) + 8652: 06 03 + 8654: 00 09 + 8656: 08 00 + 8658: 01 00 + 865a: 03 04 c2 03 lb s0, 60(tp) + 865e: 03 00 09 08 lb zero, 128(s2) + 8662: 00 01 + 8664: 00 03 + 8666: 04 c2 + 8668: 03 03 00 09 lb t1, 144(zero) + 866c: 04 00 + 866e: 01 00 + 8670: 03 04 c2 03 lb s0, 60(tp) + 8674: 03 00 09 04 lb zero, 64(s2) + 8678: 00 01 + 867a: 00 03 + 867c: 04 c3 + 867e: 03 06 03 00 lb a2, 0(t1) + 8682: 09 04 + 8684: 00 01 + 8686: 00 03 + 8688: 04 c8 + 868a: 03 06 03 00 lb a2, 0(t1) + 868e: 09 08 + 8690: 00 01 + 8692: 00 03 + 8694: 04 c8 + 8696: 03 03 00 09 lb t1, 144(zero) + 869a: 18 00 + 869c: 01 00 + 869e: 03 04 c8 03 lb s0, 60(a6) + 86a2: 03 00 09 00 lb zero, 0(s2) + 86a6: 00 01 + 86a8: 00 03 + 86aa: 04 c8 + 86ac: 03 03 00 09 lb t1, 144(zero) + 86b0: 04 00 + 86b2: 01 00 + 86b4: 03 04 c8 03 lb s0, 60(a6) + 86b8: 03 00 09 04 lb zero, 64(s2) + 86bc: 00 01 + 86be: 00 03 + 86c0: 04 c8 + 86c2: 03 06 03 7f lb a2, 2032(t1) + 86c6: 09 00 + 86c8: 00 01 + 86ca: 06 03 + 86cc: 01 09 + 86ce: 0c 00 + 86d0: 01 00 + 86d2: 03 04 f4 02 lb s0, 47(s0) + 86d6: 03 00 09 14 lb zero, 320(s2) + 86da: 00 01 + 86dc: 00 03 + 86de: 04 c9 + 86e0: 03 03 00 09 lb t1, 144(zero) + 86e4: 20 00 + 86e6: 01 00 + 86e8: 03 04 cb 03 lb s0, 60(s6) + 86ec: 03 00 09 1c lb zero, 448(s2) + 86f0: 00 01 + 86f2: 00 03 + 86f4: 04 cb + 86f6: 03 03 00 09 lb t1, 144(zero) + 86fa: 00 00 + 86fc: 01 00 + 86fe: 03 04 cd 03 lb s0, 60(s10) + 8702: 03 00 09 04 lb zero, 64(s2) + 8706: 00 01 + 8708: 00 03 + 870a: 04 cd + 870c: 03 03 00 09 lb t1, 144(zero) + 8710: 10 00 + 8712: 01 00 + 8714: 03 04 f2 03 lb s0, 63(tp) + 8718: 03 00 09 08 lb zero, 128(s2) + 871c: 00 01 + 871e: 00 03 + 8720: 04 ce + 8722: 03 03 00 09 lb t1, 144(zero) + 8726: 0c 00 + 8728: 01 00 + 872a: 03 04 d4 03 lb s0, 61(s0) + 872e: 03 00 09 04 lb zero, 64(s2) + 8732: 00 01 + 8734: 00 03 + 8736: 04 d4 + 8738: 03 03 00 09 lb t1, 144(zero) + 873c: 00 00 + 873e: 01 00 + 8740: 03 04 d4 03 lb s0, 61(s0) + 8744: 03 00 09 10 lb zero, 256(s2) + 8748: 00 01 + 874a: 00 03 + 874c: 04 d4 + 874e: 03 03 00 09 lb t1, 144(zero) + 8752: 00 00 + 8754: 01 00 + 8756: 03 04 d5 03 lb s0, 61(a0) + 875a: 03 00 09 04 lb zero, 64(s2) + 875e: 00 01 + 8760: 00 03 + 8762: 04 d5 + 8764: 03 03 00 09 lb t1, 144(zero) + 8768: 00 00 + 876a: 01 00 + 876c: 03 04 d5 03 lb s0, 61(a0) + 8770: 03 00 09 00 lb zero, 0(s2) + 8774: 00 01 + 8776: 00 03 + 8778: 04 d5 + 877a: 03 03 00 09 lb t1, 144(zero) + 877e: 00 00 + 8780: 01 00 + 8782: 03 04 d5 03 lb s0, 61(a0) + 8786: 03 00 09 00 lb zero, 0(s2) + 878a: 00 01 + 878c: 00 03 + 878e: 04 d5 + 8790: 03 03 00 09 lb t1, 144(zero) + 8794: 00 00 + 8796: 01 00 + 8798: 03 04 d5 03 lb s0, 61(a0) + 879c: 03 00 09 04 lb zero, 64(s2) + 87a0: 00 01 + 87a2: 00 03 + 87a4: 04 d5 + 87a6: 03 03 00 09 lb t1, 144(zero) + 87aa: 00 00 + 87ac: 01 00 + 87ae: 03 04 d5 03 lb s0, 61(a0) + 87b2: 03 00 09 04 lb zero, 64(s2) + 87b6: 00 01 + 87b8: 00 03 + 87ba: 04 d5 + 87bc: 03 03 00 09 lb t1, 144(zero) + 87c0: 08 00 + 87c2: 01 00 + 87c4: 03 04 d5 03 lb s0, 61(a0) + 87c8: 03 00 09 04 lb zero, 64(s2) + 87cc: 00 01 + 87ce: 00 03 + 87d0: 04 d7 + 87d2: 03 06 03 00 lb a2, 0(t1) + 87d6: 09 08 + 87d8: 00 01 + 87da: 00 03 + 87dc: 04 dc + 87de: 03 03 00 09 lb t1, 144(zero) + 87e2: 04 00 + 87e4: 01 00 + 87e6: 03 04 dc 03 lb s0, 61(s8) + 87ea: 06 03 + 87ec: 00 09 + 87ee: 08 00 + 87f0: 01 00 + 87f2: 03 04 dc 03 lb s0, 61(s8) + 87f6: 03 00 09 00 lb zero, 0(s2) + 87fa: 00 01 + 87fc: 00 03 + 87fe: 04 dc + 8800: 03 03 00 09 lb t1, 144(zero) + 8804: 04 00 + 8806: 01 00 + 8808: 03 04 dc 03 lb s0, 61(s8) + 880c: 03 00 09 04 lb zero, 64(s2) + 8810: 00 01 + 8812: 00 03 + 8814: 04 dd + 8816: 03 06 03 00 lb a2, 0(t1) + 881a: 09 08 + 881c: 00 01 + 881e: 00 03 + 8820: 04 e2 + 8822: 03 06 03 00 lb a2, 0(t1) + 8826: 09 04 + 8828: 00 01 + 882a: 00 03 + 882c: 04 e2 + 882e: 03 03 00 09 lb t1, 144(zero) + 8832: 10 00 + 8834: 01 00 + 8836: 03 04 e2 03 lb s0, 62(tp) + 883a: 03 00 09 04 lb zero, 64(s2) + 883e: 00 01 + 8840: 00 03 + 8842: 04 e2 + 8844: 03 03 00 09 lb t1, 144(zero) + 8848: 04 00 + 884a: 01 00 + 884c: 03 04 e2 03 lb s0, 62(tp) + 8850: 03 00 09 04 lb zero, 64(s2) + 8854: 00 01 + 8856: 00 03 + 8858: 04 e2 + 885a: 03 03 00 09 lb t1, 144(zero) + 885e: 00 00 + 8860: 01 00 + 8862: 03 04 e2 03 lb s0, 62(tp) + 8866: 03 00 09 00 lb zero, 0(s2) + 886a: 00 01 + 886c: 00 03 + 886e: 04 e3 + 8870: 03 03 00 09 lb t1, 144(zero) + 8874: 08 00 + 8876: 01 00 + 8878: 03 04 e3 03 lb s0, 62(t1) + 887c: 03 00 09 00 lb zero, 0(s2) + 8880: 00 01 + 8882: 00 03 + 8884: 04 e3 + 8886: 03 03 00 09 lb t1, 144(zero) + 888a: 00 00 + 888c: 01 00 + 888e: 03 04 e3 03 lb s0, 62(t1) + 8892: 03 00 09 00 lb zero, 0(s2) + 8896: 00 01 + 8898: 00 03 + 889a: 04 e3 + 889c: 03 03 00 09 lb t1, 144(zero) + 88a0: 00 00 + 88a2: 01 00 + 88a4: 03 04 e3 03 lb s0, 62(t1) + 88a8: 03 00 09 04 lb zero, 64(s2) + 88ac: 00 01 + 88ae: 00 03 + 88b0: 04 e3 + 88b2: 03 03 00 09 lb t1, 144(zero) + 88b6: 00 00 + 88b8: 01 00 + 88ba: 03 04 e3 03 lb s0, 62(t1) + 88be: 03 00 09 04 lb zero, 64(s2) + 88c2: 00 01 + 88c4: 00 03 + 88c6: 04 e3 + 88c8: 03 03 00 09 lb t1, 144(zero) + 88cc: 08 00 + 88ce: 01 00 + 88d0: 03 04 e3 03 lb s0, 62(t1) + 88d4: 03 00 09 04 lb zero, 64(s2) + 88d8: 00 01 + 88da: 00 03 + 88dc: 04 e5 + 88de: 03 06 03 00 lb a2, 0(t1) + 88e2: 09 08 + 88e4: 00 01 + 88e6: 00 03 + 88e8: 04 ea + 88ea: 03 03 00 09 lb t1, 144(zero) + 88ee: 04 00 + 88f0: 01 00 + 88f2: 03 04 ea 03 lb s0, 62(s4) + 88f6: 06 03 + 88f8: 00 09 + 88fa: 08 00 + 88fc: 01 00 + 88fe: 03 04 ea 03 lb s0, 62(s4) + 8902: 03 00 09 00 lb zero, 0(s2) + 8906: 00 01 + 8908: 00 03 + 890a: 04 ea + 890c: 03 03 00 09 lb t1, 144(zero) + 8910: 04 00 + 8912: 01 00 + 8914: 03 04 ea 03 lb s0, 62(s4) + 8918: 03 00 09 08 lb zero, 128(s2) + 891c: 00 01 + 891e: 00 03 + 8920: 04 eb + 8922: 03 06 03 00 lb a2, 0(t1) + 8926: 09 04 + 8928: 00 01 + 892a: 00 03 + 892c: 04 f0 + 892e: 03 06 03 00 lb a2, 0(t1) + 8932: 09 04 + 8934: 00 01 + 8936: 00 03 + 8938: 04 f0 + 893a: 03 03 00 09 lb t1, 144(zero) + 893e: 10 00 + 8940: 01 00 + 8942: 03 04 f0 03 lb s0, 63(zero) + 8946: 03 00 09 04 lb zero, 64(s2) + 894a: 00 01 + 894c: 00 03 + 894e: 04 f0 + 8950: 03 03 00 09 lb t1, 144(zero) + 8954: 04 00 + 8956: 01 00 + 8958: 03 04 f0 03 lb s0, 63(zero) + 895c: 03 00 09 04 lb zero, 64(s2) + 8960: 00 01 + 8962: 00 03 + 8964: 04 f0 + 8966: 03 03 00 09 lb t1, 144(zero) + 896a: 00 00 + 896c: 01 00 + 896e: 03 04 e4 03 lb s0, 62(s0) + 8972: 03 00 09 08 lb zero, 128(s2) + 8976: 00 01 + 8978: 00 03 + 897a: 04 cc + 897c: 03 03 00 09 lb t1, 144(zero) + 8980: 14 00 + 8982: 01 00 + 8984: 03 04 cc 03 lb s0, 60(s8) + 8988: 03 00 09 00 lb zero, 0(s2) + 898c: 00 01 + 898e: 00 03 + 8990: 04 f6 + 8992: 03 06 03 00 lb a2, 0(t1) + 8996: 09 0c + 8998: 00 01 + 899a: 00 03 + 899c: 04 f8 + 899e: 03 03 00 09 lb t1, 144(zero) + 89a2: 04 00 + 89a4: 01 00 + 89a6: 03 04 f8 03 lb s0, 63(a6) + 89aa: 03 77 09 08 + 89ae: 00 01 + 89b0: 00 03 + 89b2: 04 f8 + 89b4: 03 06 03 09 lb a2, 144(t1) + 89b8: 09 08 + 89ba: 00 01 + 89bc: 00 03 + 89be: 04 f8 + 89c0: 03 03 00 09 lb t1, 144(zero) + 89c4: 00 00 + 89c6: 01 00 + 89c8: 03 04 f8 03 lb s0, 63(a6) + 89cc: 03 00 09 00 lb zero, 0(s2) + 89d0: 00 01 + 89d2: 00 03 + 89d4: 04 fd + 89d6: 03 06 03 00 lb a2, 0(t1) + 89da: 09 04 + 89dc: 00 01 + 89de: 00 03 + 89e0: 04 ff + 89e2: 03 03 00 09 lb t1, 144(zero) + 89e6: 04 00 + 89e8: 01 06 + 89ea: 03 00 09 08 lb zero, 128(s2) + 89ee: 00 01 + 89f0: 03 00 09 00 lb zero, 0(s2) + 89f4: 00 01 + 89f6: 03 00 09 00 lb zero, 0(s2) + 89fa: 00 01 + 89fc: 00 03 + 89fe: 04 9d + 8a00: 04 03 + 8a02: 00 09 + 8a04: 04 00 + 8a06: 01 00 + 8a08: 03 04 9d 04 lb s0, 73(s10) + 8a0c: 03 00 09 00 lb zero, 0(s2) + 8a10: 00 01 + 8a12: 00 03 + 8a14: 04 9d + 8a16: 04 03 + 8a18: 00 09 + 8a1a: 00 00 + 8a1c: 01 00 + 8a1e: 03 04 9d 04 lb s0, 73(s10) + 8a22: 03 00 09 00 lb zero, 0(s2) + 8a26: 00 01 + 8a28: 00 03 + 8a2a: 04 9d + 8a2c: 04 03 + 8a2e: 00 09 + 8a30: 00 00 + 8a32: 01 00 + 8a34: 03 04 9d 04 lb s0, 73(s10) + 8a38: 03 00 09 00 lb zero, 0(s2) + 8a3c: 00 01 + 8a3e: 00 03 + 8a40: 04 9d + 8a42: 04 03 + 8a44: 00 09 + 8a46: 00 00 + 8a48: 01 00 + 8a4a: 03 04 9d 04 lb s0, 73(s10) + 8a4e: 03 00 09 00 lb zero, 0(s2) + 8a52: 00 01 + 8a54: 00 03 + 8a56: 04 9d + 8a58: 04 03 + 8a5a: 00 09 + 8a5c: 00 00 + 8a5e: 01 00 + 8a60: 03 04 9d 04 lb s0, 73(s10) + 8a64: 03 00 09 00 lb zero, 0(s2) + 8a68: 00 01 + 8a6a: 00 03 + 8a6c: 04 9d + 8a6e: 04 03 + 8a70: 00 09 + 8a72: 14 00 + 8a74: 01 00 + 8a76: 03 04 9d 04 lb s0, 73(s10) + 8a7a: 03 00 09 00 lb zero, 0(s2) + 8a7e: 00 01 + 8a80: 00 03 + 8a82: 04 9d + 8a84: 04 03 + 8a86: 00 09 + 8a88: 00 00 + 8a8a: 01 00 + 8a8c: 03 04 9d 04 lb s0, 73(s10) + 8a90: 03 00 09 00 lb zero, 0(s2) + 8a94: 00 01 + 8a96: 00 03 + 8a98: 04 9d + 8a9a: 04 03 + 8a9c: 00 09 + 8a9e: 00 00 + 8aa0: 01 00 + 8aa2: 03 04 9d 04 lb s0, 73(s10) + 8aa6: 03 00 09 00 lb zero, 0(s2) + 8aaa: 00 01 + 8aac: 00 03 + 8aae: 04 9d + 8ab0: 04 03 + 8ab2: 00 09 + 8ab4: 00 00 + 8ab6: 01 00 + 8ab8: 03 04 9d 04 lb s0, 73(s10) + 8abc: 03 00 09 00 lb zero, 0(s2) + 8ac0: 00 01 + 8ac2: 00 03 + 8ac4: 04 9d + 8ac6: 04 03 + 8ac8: 00 09 + 8aca: 00 00 + 8acc: 01 00 + 8ace: 03 04 9d 04 lb s0, 73(s10) + 8ad2: 03 00 09 00 lb zero, 0(s2) + 8ad6: 00 01 + 8ad8: 00 03 + 8ada: 04 9d + 8adc: 04 03 + 8ade: 00 09 + 8ae0: 00 00 + 8ae2: 01 00 + 8ae4: 03 04 b9 04 lb s0, 75(s2) + 8ae8: 03 00 09 04 lb zero, 64(s2) + 8aec: 00 01 + 8aee: 00 03 + 8af0: 04 b9 + 8af2: 04 03 + 8af4: 00 09 + 8af6: 1c 00 + 8af8: 01 00 + 8afa: 03 04 b9 04 lb s0, 75(s2) + 8afe: 03 00 09 00 lb zero, 0(s2) + 8b02: 00 01 + 8b04: 00 03 + 8b06: 04 fc + 8b08: 03 03 00 09 lb t1, 144(zero) + 8b0c: 08 00 + 8b0e: 01 00 + 8b10: 03 04 fc 03 lb s0, 63(s8) + 8b14: 03 00 09 00 lb zero, 0(s2) + 8b18: 00 01 + 8b1a: 00 03 + 8b1c: 04 fc + 8b1e: 03 03 00 09 lb t1, 144(zero) + 8b22: 00 00 + 8b24: 01 06 + 8b26: 03 77 09 04 + 8b2a: 00 01 + 8b2c: 00 03 + 8b2e: 04 83 + 8b30: 04 06 + 8b32: 03 09 09 08 lb s2, 128(s2) + 8b36: 00 01 + 8b38: 00 03 + 8b3a: 04 83 + 8b3c: 04 03 + 8b3e: 00 09 + 8b40: 00 00 + 8b42: 01 00 + 8b44: 03 04 83 04 lb s0, 72(t1) + 8b48: 03 00 09 00 lb zero, 0(s2) + 8b4c: 00 01 + 8b4e: 00 03 + 8b50: 04 84 + 8b52: 04 03 + 8b54: 00 09 + 8b56: 04 00 + 8b58: 01 00 + 8b5a: 03 04 86 04 lb s0, 72(a2) + 8b5e: 03 00 09 04 lb zero, 64(s2) + 8b62: 00 01 + 8b64: 00 03 + 8b66: 04 86 + 8b68: 04 03 + 8b6a: 00 09 + 8b6c: 00 00 + 8b6e: 01 00 + 8b70: 03 04 86 04 lb s0, 72(a2) + 8b74: 03 00 09 14 lb zero, 320(s2) + 8b78: 00 01 + 8b7a: 00 03 + 8b7c: 04 86 + 8b7e: 04 03 + 8b80: 00 09 + 8b82: 00 00 + 8b84: 01 00 + 8b86: 03 04 86 04 lb s0, 72(a2) + 8b8a: 03 00 09 00 lb zero, 0(s2) + 8b8e: 00 01 + 8b90: 00 03 + 8b92: 04 86 + 8b94: 04 03 + 8b96: 00 09 + 8b98: 00 00 + 8b9a: 01 00 + 8b9c: 03 04 86 04 lb s0, 72(a2) + 8ba0: 03 00 09 00 lb zero, 0(s2) + 8ba4: 00 01 + 8ba6: 00 03 + 8ba8: 04 86 + 8baa: 04 03 + 8bac: 00 09 + 8bae: 00 00 + 8bb0: 01 00 + 8bb2: 03 04 86 04 lb s0, 72(a2) + 8bb6: 03 00 09 00 lb zero, 0(s2) + 8bba: 00 01 + 8bbc: 00 03 + 8bbe: 04 86 + 8bc0: 04 03 + 8bc2: 00 09 + 8bc4: 00 00 + 8bc6: 01 00 + 8bc8: 03 04 86 04 lb s0, 72(a2) + 8bcc: 03 00 09 00 lb zero, 0(s2) + 8bd0: 00 01 + 8bd2: 00 03 + 8bd4: 04 8f + 8bd6: 04 03 + 8bd8: 00 09 + 8bda: 04 00 + 8bdc: 01 00 + 8bde: 03 04 8f 04 lb s0, 72(t5) + 8be2: 03 00 09 1c lb zero, 448(s2) + 8be6: 00 01 + 8be8: 00 03 + 8bea: 04 8f + 8bec: 04 03 + 8bee: 00 09 + 8bf0: 00 00 + 8bf2: 01 00 + 8bf4: 03 04 90 04 lb s0, 73(zero) + 8bf8: 03 00 09 04 lb zero, 64(s2) + 8bfc: 00 01 + 8bfe: 00 03 + 8c00: 04 90 + 8c02: 04 03 + 8c04: 00 09 + 8c06: 14 00 + 8c08: 01 00 + 8c0a: 03 04 87 04 lb s0, 72(a4) + 8c0e: 03 00 09 10 lb zero, 256(s2) + 8c12: 00 01 + 8c14: 00 03 + 8c16: 04 87 + 8c18: 04 03 + 8c1a: 00 09 + 8c1c: 00 00 + 8c1e: 01 06 + 8c20: 03 77 09 18 + 8c24: 00 01 + 8c26: 00 03 + 8c28: 04 85 + 8c2a: 04 06 + 8c2c: 03 09 09 04 lb s2, 64(s2) + 8c30: 00 01 + 8c32: 00 03 + 8c34: 04 95 + 8c36: 04 03 + 8c38: 00 09 + 8c3a: 04 00 + 8c3c: 01 00 + 8c3e: 03 04 95 04 lb s0, 73(a0) + 8c42: 03 00 09 00 lb zero, 0(s2) + 8c46: 00 01 + 8c48: 00 03 + 8c4a: 04 ca + 8c4c: 03 03 00 09 lb t1, 144(zero) + 8c50: 14 00 + 8c52: 01 00 + 8c54: 03 04 ca 03 lb s0, 60(s4) + 8c58: 03 00 09 00 lb zero, 0(s2) + 8c5c: 00 01 + 8c5e: 00 03 + 8c60: 04 ca + 8c62: 03 03 00 09 lb t1, 144(zero) + 8c66: 00 00 + 8c68: 01 00 + 8c6a: 03 04 ca 03 lb s0, 60(s4) + 8c6e: 03 00 09 00 lb zero, 0(s2) + 8c72: 00 01 + 8c74: 00 03 + 8c76: 04 ca + 8c78: 03 03 00 09 lb t1, 144(zero) + 8c7c: 00 00 + 8c7e: 01 00 + 8c80: 03 04 ca 03 lb s0, 60(s4) + 8c84: 03 00 09 00 lb zero, 0(s2) + 8c88: 00 01 + 8c8a: 00 03 + 8c8c: 04 ca + 8c8e: 03 03 00 09 lb t1, 144(zero) + 8c92: 04 00 + 8c94: 01 00 + 8c96: 03 04 ca 03 lb s0, 60(s4) + 8c9a: 03 00 09 00 lb zero, 0(s2) + 8c9e: 00 01 + 8ca0: 00 03 + 8ca2: 04 ca + 8ca4: 03 03 00 09 lb t1, 144(zero) + 8ca8: 04 00 + 8caa: 01 00 + 8cac: 03 04 ca 03 lb s0, 60(s4) + 8cb0: 03 00 09 08 lb zero, 128(s2) + 8cb4: 00 01 + 8cb6: 00 03 + 8cb8: 04 ca + 8cba: 03 03 00 09 lb t1, 144(zero) + 8cbe: 04 00 + 8cc0: 01 00 + 8cc2: 03 04 c0 04 lb s0, 76(zero) + 8cc6: 06 03 + 8cc8: 00 09 + 8cca: 08 00 + 8ccc: 01 00 + 8cce: 03 04 c5 04 lb s0, 76(a0) + 8cd2: 03 00 09 04 lb zero, 64(s2) + 8cd6: 00 01 + 8cd8: 00 03 + 8cda: 04 c5 + 8cdc: 04 06 + 8cde: 03 00 09 08 lb zero, 128(s2) + 8ce2: 00 01 + 8ce4: 00 03 + 8ce6: 04 c5 + 8ce8: 04 03 + 8cea: 00 09 + 8cec: 00 00 + 8cee: 01 00 + 8cf0: 03 04 c5 04 lb s0, 76(a0) + 8cf4: 03 00 09 04 lb zero, 64(s2) + 8cf8: 00 01 + 8cfa: 00 03 + 8cfc: 04 c5 + 8cfe: 04 03 + 8d00: 00 09 + 8d02: 04 00 + 8d04: 01 00 + 8d06: 03 04 c6 04 lb s0, 76(a2) + 8d0a: 06 03 + 8d0c: 00 09 + 8d0e: 08 00 + 8d10: 01 00 + 8d12: 03 04 cb 04 lb s0, 76(s6) + 8d16: 06 03 + 8d18: 00 09 + 8d1a: 04 00 + 8d1c: 01 00 + 8d1e: 03 04 cb 04 lb s0, 76(s6) + 8d22: 03 00 09 10 lb zero, 256(s2) + 8d26: 00 01 + 8d28: 00 03 + 8d2a: 04 cb + 8d2c: 04 03 + 8d2e: 00 09 + 8d30: 04 00 + 8d32: 01 00 + 8d34: 03 04 cb 04 lb s0, 76(s6) + 8d38: 03 00 09 04 lb zero, 64(s2) + 8d3c: 00 01 + 8d3e: 00 03 + 8d40: 04 cb + 8d42: 04 03 + 8d44: 00 09 + 8d46: 04 00 + 8d48: 01 00 + 8d4a: 03 04 cb 04 lb s0, 76(s6) + 8d4e: 03 00 09 00 lb zero, 0(s2) + 8d52: 00 01 + 8d54: 00 03 + 8d56: 04 cb + 8d58: 04 03 + 8d5a: 00 09 + 8d5c: 00 00 + 8d5e: 01 00 + 8d60: 03 04 cc 04 lb s0, 76(s8) + 8d64: 03 00 09 08 lb zero, 128(s2) + 8d68: 00 01 + 8d6a: 00 03 + 8d6c: 04 cc + 8d6e: 04 03 + 8d70: 00 09 + 8d72: 00 00 + 8d74: 01 00 + 8d76: 03 04 cc 04 lb s0, 76(s8) + 8d7a: 03 00 09 00 lb zero, 0(s2) + 8d7e: 00 01 + 8d80: 00 03 + 8d82: 04 cc + 8d84: 04 03 + 8d86: 00 09 + 8d88: 00 00 + 8d8a: 01 00 + 8d8c: 03 04 cc 04 lb s0, 76(s8) + 8d90: 03 00 09 00 lb zero, 0(s2) + 8d94: 00 01 + 8d96: 00 03 + 8d98: 04 cc + 8d9a: 04 03 + 8d9c: 00 09 + 8d9e: 04 00 + 8da0: 01 00 + 8da2: 03 04 cc 04 lb s0, 76(s8) + 8da6: 03 00 09 00 lb zero, 0(s2) + 8daa: 00 01 + 8dac: 00 03 + 8dae: 04 cc + 8db0: 04 03 + 8db2: 00 09 + 8db4: 04 00 + 8db6: 01 00 + 8db8: 03 04 cc 04 lb s0, 76(s8) + 8dbc: 03 00 09 08 lb zero, 128(s2) + 8dc0: 00 01 + 8dc2: 00 03 + 8dc4: 04 cc + 8dc6: 04 03 + 8dc8: 00 09 + 8dca: 04 00 + 8dcc: 01 00 + 8dce: 03 04 ce 04 lb s0, 76(t3) + 8dd2: 06 03 + 8dd4: 00 09 + 8dd6: 08 00 + 8dd8: 01 00 + 8dda: 03 04 d3 04 lb s0, 77(t1) + 8dde: 03 00 09 04 lb zero, 64(s2) + 8de2: 00 01 + 8de4: 00 03 + 8de6: 04 d3 + 8de8: 04 06 + 8dea: 03 00 09 08 lb zero, 128(s2) + 8dee: 00 01 + 8df0: 00 03 + 8df2: 04 d3 + 8df4: 04 03 + 8df6: 00 09 + 8df8: 00 00 + 8dfa: 01 00 + 8dfc: 03 04 d3 04 lb s0, 77(t1) + 8e00: 03 00 09 04 lb zero, 64(s2) + 8e04: 00 01 + 8e06: 00 03 + 8e08: 04 d3 + 8e0a: 04 03 + 8e0c: 00 09 + 8e0e: 04 00 + 8e10: 01 00 + 8e12: 03 04 d4 04 lb s0, 77(s0) + 8e16: 06 03 + 8e18: 00 09 + 8e1a: 04 00 + 8e1c: 01 00 + 8e1e: 03 04 d9 04 lb s0, 77(s2) + 8e22: 06 03 + 8e24: 00 09 + 8e26: 04 00 + 8e28: 01 00 + 8e2a: 03 04 d9 04 lb s0, 77(s2) + 8e2e: 03 00 09 10 lb zero, 256(s2) + 8e32: 00 01 + 8e34: 00 03 + 8e36: 04 d9 + 8e38: 04 03 + 8e3a: 00 09 + 8e3c: 04 00 + 8e3e: 01 00 + 8e40: 03 04 d9 04 lb s0, 77(s2) + 8e44: 03 00 09 04 lb zero, 64(s2) + 8e48: 00 01 + 8e4a: 00 03 + 8e4c: 04 d9 + 8e4e: 04 03 + 8e50: 00 09 + 8e52: 04 00 + 8e54: 01 00 + 8e56: 03 04 d9 04 lb s0, 77(s2) + 8e5a: 03 00 09 00 lb zero, 0(s2) + 8e5e: 00 01 + 8e60: 00 03 + 8e62: 04 e1 + 8e64: 04 03 + 8e66: 00 09 + 8e68: 04 00 + 8e6a: 01 00 + 8e6c: 03 04 e1 04 lb s0, 78(sp) + 8e70: 03 00 09 00 lb zero, 0(s2) + 8e74: 00 01 + 8e76: 00 03 + 8e78: 04 e4 + 8e7a: 04 03 + 8e7c: 00 09 + 8e7e: 08 00 + 8e80: 01 00 + 8e82: 03 04 e4 04 lb s0, 78(s0) + 8e86: 03 00 09 00 lb zero, 0(s2) + 8e8a: 00 01 + 8e8c: 00 03 + 8e8e: 04 e4 + 8e90: 04 03 + 8e92: 00 09 + 8e94: 00 00 + 8e96: 01 00 + 8e98: 03 04 e4 04 lb s0, 78(s0) + 8e9c: 03 00 09 00 lb zero, 0(s2) + 8ea0: 00 01 + 8ea2: 00 03 + 8ea4: 04 e4 + 8ea6: 04 03 + 8ea8: 00 09 + 8eaa: 04 00 + 8eac: 01 00 + 8eae: 03 04 86 05 lb s0, 88(a2) + 8eb2: 03 00 09 00 lb zero, 0(s2) + 8eb6: 00 01 + 8eb8: 00 03 + 8eba: 04 86 + 8ebc: 05 03 + 8ebe: 00 09 + 8ec0: 00 00 + 8ec2: 01 00 + 8ec4: 03 04 86 05 lb s0, 88(a2) + 8ec8: 03 00 09 04 lb zero, 64(s2) + 8ecc: 00 01 + 8ece: 00 03 + 8ed0: 04 86 + 8ed2: 05 03 + 8ed4: 00 09 + 8ed6: 00 00 + 8ed8: 01 00 + 8eda: 03 04 86 05 lb s0, 88(a2) + 8ede: 03 00 09 00 lb zero, 0(s2) + 8ee2: 00 01 + 8ee4: 00 03 + 8ee6: 04 86 + 8ee8: 05 03 + 8eea: 00 09 + 8eec: 00 00 + 8eee: 01 00 + 8ef0: 03 04 86 05 lb s0, 88(a2) + 8ef4: 03 00 09 0c lb zero, 192(s2) + 8ef8: 00 01 + 8efa: 00 03 + 8efc: 04 86 + 8efe: 05 03 + 8f00: 00 09 + 8f02: 00 00 + 8f04: 01 00 + 8f06: 03 04 86 05 lb s0, 88(a2) + 8f0a: 03 00 09 00 lb zero, 0(s2) + 8f0e: 00 01 + 8f10: 06 03 + 8f12: 00 09 + 8f14: 10 00 + 8f16: 01 00 + 8f18: 03 04 8c 05 lb s0, 88(s8) + 8f1c: 06 03 + 8f1e: 00 09 + 8f20: 14 00 + 8f22: 01 00 + 8f24: 03 04 8f 05 lb s0, 88(t5) + 8f28: 06 03 + 8f2a: 00 09 + 8f2c: 04 00 + 8f2e: 01 00 + 8f30: 03 04 8f 05 lb s0, 88(t5) + 8f34: 06 03 + 8f36: 00 09 + 8f38: 10 00 + 8f3a: 01 00 + 8f3c: 03 04 91 05 lb s0, 89(sp) + 8f40: 06 03 + 8f42: 00 09 + 8f44: 08 00 + 8f46: 01 00 + 8f48: 03 04 cd 04 lb s0, 76(s10) + 8f4c: 06 03 + 8f4e: 00 09 + 8f50: 08 00 + 8f52: 01 00 + 8f54: 03 04 db 04 lb s0, 77(s6) + 8f58: 03 00 09 10 lb zero, 256(s2) + 8f5c: 00 01 + 8f5e: 00 03 + 8f60: 04 db + 8f62: 04 03 + 8f64: 00 09 + 8f66: 00 00 + 8f68: 01 00 + 8f6a: 03 04 db 04 lb s0, 77(s6) + 8f6e: 03 00 09 08 lb zero, 128(s2) + 8f72: 00 01 + 8f74: 00 03 + 8f76: 04 a6 + 8f78: 05 03 + 8f7a: 00 09 + 8f7c: 00 00 + 8f7e: 01 00 + 8f80: 03 04 a6 05 lb s0, 90(a2) + 8f84: 03 00 09 00 lb zero, 0(s2) + 8f88: 00 01 + 8f8a: 00 03 + 8f8c: 04 e3 + 8f8e: 04 03 + 8f90: 00 09 + 8f92: 08 00 + 8f94: 01 00 + 8f96: 03 04 ed 04 lb s0, 78(s10) + 8f9a: 03 00 09 08 lb zero, 128(s2) + 8f9e: 00 01 + 8fa0: 00 03 + 8fa2: 04 ed + 8fa4: 04 03 + 8fa6: 00 09 + 8fa8: 00 00 + 8faa: 01 00 + 8fac: 03 04 ed 04 lb s0, 78(s10) + 8fb0: 03 00 09 00 lb zero, 0(s2) + 8fb4: 00 01 + 8fb6: 00 03 + 8fb8: 04 ed + 8fba: 04 03 + 8fbc: 00 09 + 8fbe: 00 00 + 8fc0: 01 00 + 8fc2: 03 04 ed 04 lb s0, 78(s10) + 8fc6: 03 00 09 04 lb zero, 64(s2) + 8fca: 00 01 + 8fcc: 00 03 + 8fce: 04 ed + 8fd0: 04 03 + 8fd2: 00 09 + 8fd4: 00 00 + 8fd6: 01 00 + 8fd8: 03 04 ec 04 lb s0, 78(s8) + 8fdc: 03 00 09 08 lb zero, 128(s2) + 8fe0: 00 01 + 8fe2: 00 03 + 8fe4: 04 f7 + 8fe6: 04 03 + 8fe8: 00 09 + 8fea: 08 00 + 8fec: 01 00 + 8fee: 03 04 f7 04 lb s0, 79(a4) + 8ff2: 03 00 09 00 lb zero, 0(s2) + 8ff6: 00 01 + 8ff8: 00 03 + 8ffa: 04 f7 + 8ffc: 04 03 + 8ffe: 00 09 + 9000: 00 00 + 9002: 01 00 + 9004: 03 04 f7 04 lb s0, 79(a4) + 9008: 03 00 09 00 lb zero, 0(s2) + 900c: 00 01 + 900e: 00 03 + 9010: 04 f7 + 9012: 04 03 + 9014: 00 09 + 9016: 04 00 + 9018: 01 00 + 901a: 03 04 f7 04 lb s0, 79(a4) + 901e: 03 00 09 00 lb zero, 0(s2) + 9022: 00 01 + 9024: 00 03 + 9026: 04 ff + 9028: 04 03 + 902a: 00 09 + 902c: 08 00 + 902e: 01 00 + 9030: 03 04 ff 04 lb s0, 79(t5) + 9034: 03 00 09 00 lb zero, 0(s2) + 9038: 00 01 + 903a: 00 03 + 903c: 04 ff + 903e: 04 03 + 9040: 00 09 + 9042: 00 00 + 9044: 01 00 + 9046: 03 04 ff 04 lb s0, 79(t5) + 904a: 03 00 09 00 lb zero, 0(s2) + 904e: 00 01 + 9050: 00 03 + 9052: 04 ff + 9054: 04 03 + 9056: 00 09 + 9058: 08 00 + 905a: 01 00 + 905c: 03 04 ff 04 lb s0, 79(t5) + 9060: 03 00 09 00 lb zero, 0(s2) + 9064: 00 01 + 9066: 06 03 + 9068: 00 09 + 906a: 14 00 + 906c: 01 00 + 906e: 03 04 8b 05 lb s0, 88(s6) + 9072: 06 03 + 9074: 00 09 + 9076: 04 00 + 9078: 01 00 + 907a: 03 04 8b 05 lb s0, 88(s6) + 907e: 03 00 09 14 lb zero, 320(s2) + 9082: 00 01 + 9084: 00 03 + 9086: 04 8b + 9088: 05 03 + 908a: 00 09 + 908c: 00 00 + 908e: 01 00 + 9090: 03 04 8e 05 lb s0, 88(t3) + 9094: 03 00 09 0c lb zero, 192(s2) + 9098: 00 01 + 909a: 00 03 + 909c: 04 8e + 909e: 05 03 + 90a0: 00 09 + 90a2: 1c 00 + 90a4: 01 00 + 90a6: 03 04 92 05 lb s0, 89(tp) + 90aa: 03 00 09 08 lb zero, 128(s2) + 90ae: 00 01 + 90b0: 00 03 + 90b2: 04 92 + 90b4: 05 03 + 90b6: 00 09 + 90b8: 10 00 + 90ba: 01 00 + 90bc: 03 04 91 05 lb s0, 89(sp) + 90c0: 03 00 09 04 lb zero, 64(s2) + 90c4: 00 01 + 90c6: 00 03 + 90c8: 04 93 + 90ca: 05 03 + 90cc: 00 09 + 90ce: 04 00 + 90d0: 01 00 + 90d2: 03 04 93 05 lb s0, 89(t1) + 90d6: 03 00 09 00 lb zero, 0(s2) + 90da: 00 01 + 90dc: 00 03 + 90de: 04 94 + 90e0: 05 03 + 90e2: 00 09 + 90e4: 04 00 + 90e6: 01 00 + 90e8: 03 04 94 05 lb s0, 89(s0) + 90ec: 03 00 09 0c lb zero, 192(s2) + 90f0: 00 01 + 90f2: 00 03 + 90f4: 04 94 + 90f6: 05 03 + 90f8: 00 09 + 90fa: 00 00 + 90fc: 01 00 + 90fe: 03 04 94 05 lb s0, 89(s0) + 9102: 03 00 09 00 lb zero, 0(s2) + 9106: 00 01 + 9108: 00 03 + 910a: 04 94 + 910c: 05 03 + 910e: 00 09 + 9110: 00 00 + 9112: 01 00 + 9114: 03 04 94 05 lb s0, 89(s0) + 9118: 03 00 09 00 lb zero, 0(s2) + 911c: 00 01 + 911e: 00 03 + 9120: 04 94 + 9122: 05 03 + 9124: 00 09 + 9126: 00 00 + 9128: 01 00 + 912a: 03 04 94 05 lb s0, 89(s0) + 912e: 03 00 09 00 lb zero, 0(s2) + 9132: 00 01 + 9134: 00 03 + 9136: 04 94 + 9138: 05 03 + 913a: 00 09 + 913c: 04 00 + 913e: 01 00 + 9140: 03 04 94 05 lb s0, 89(s0) + 9144: 03 00 09 00 lb zero, 0(s2) + 9148: 00 01 + 914a: 00 03 + 914c: 04 94 + 914e: 05 03 + 9150: 00 09 + 9152: 00 00 + 9154: 01 00 + 9156: 03 04 96 05 lb s0, 89(a2) + 915a: 03 00 09 08 lb zero, 128(s2) + 915e: 00 01 + 9160: 00 03 + 9162: 04 99 + 9164: 05 03 + 9166: 00 09 + 9168: 10 00 + 916a: 01 06 + 916c: 03 00 09 0c lb zero, 192(s2) + 9170: 00 01 + 9172: 00 03 + 9174: 04 9e + 9176: 05 06 + 9178: 03 00 09 0c lb zero, 192(s2) + 917c: 00 01 + 917e: 00 03 + 9180: 04 9e + 9182: 05 03 + 9184: 00 09 + 9186: 14 00 + 9188: 01 00 + 918a: 03 04 9e 05 lb s0, 89(t3) + 918e: 03 00 09 00 lb zero, 0(s2) + 9192: 00 01 + 9194: 00 03 + 9196: 04 98 + 9198: 05 03 + 919a: 00 09 + 919c: 1c 00 + 919e: 01 00 + 91a0: 03 04 98 05 lb s0, 89(a6) + 91a4: 03 00 09 18 lb zero, 384(s2) + 91a8: 00 01 + 91aa: 00 03 + 91ac: 04 9b + 91ae: 05 06 + 91b0: 03 00 09 04 lb zero, 64(s2) + 91b4: 00 01 + 91b6: 00 03 + 91b8: 04 9b + 91ba: 05 06 + 91bc: 03 00 09 24 lb zero, 576(s2) + 91c0: 00 01 + 91c2: 00 03 + 91c4: 04 9b + 91c6: 05 03 + 91c8: 00 09 + 91ca: 08 00 + 91cc: 01 00 + 91ce: 03 04 9f 05 lb s0, 89(t5) + 91d2: 03 00 09 0c lb zero, 192(s2) + 91d6: 00 01 + 91d8: 00 03 + 91da: 04 a2 + 91dc: 05 06 + 91de: 03 00 09 08 lb zero, 128(s2) + 91e2: 00 01 + 91e4: 00 03 + 91e6: 04 a2 + 91e8: 05 06 + 91ea: 03 00 09 1c lb zero, 448(s2) + 91ee: 00 01 + 91f0: 00 03 + 91f2: 04 a4 + 91f4: 05 06 + 91f6: 03 00 09 04 lb zero, 64(s2) + 91fa: 00 01 + 91fc: 00 03 + 91fe: 04 a1 + 9200: 05 06 + 9202: 03 00 09 08 lb zero, 128(s2) + 9206: 00 01 + 9208: 00 03 + 920a: 04 a1 + 920c: 05 03 + 920e: 00 09 + 9210: 28 00 + 9212: 01 00 + 9214: 03 04 a5 05 lb s0, 90(a0) + 9218: 03 00 09 04 lb zero, 64(s2) + 921c: 00 01 + 921e: 00 03 + 9220: 04 a5 + 9222: 05 03 + 9224: 00 09 + 9226: 10 00 + 9228: 01 00 + 922a: 03 04 a4 05 lb s0, 90(s0) + 922e: 03 00 09 04 lb zero, 64(s2) + 9232: 00 01 + 9234: 00 03 + 9236: 04 a6 + 9238: 05 03 + 923a: 00 09 + 923c: 04 00 + 923e: 01 00 + 9240: 03 04 a6 05 lb s0, 90(a2) + 9244: 03 00 09 00 lb zero, 0(s2) + 9248: 00 01 + 924a: 00 03 + 924c: 04 a6 + 924e: 05 03 + 9250: 00 09 + 9252: 00 00 + 9254: 01 00 + 9256: 03 04 95 05 lb s0, 89(a0) + 925a: 03 00 09 14 lb zero, 320(s2) + 925e: 00 01 + 9260: 00 03 + 9262: 04 95 + 9264: 05 03 + 9266: 00 09 + 9268: 14 00 + 926a: 01 06 + 926c: 03 00 09 04 lb zero, 64(s2) + 9270: 00 01 + 9272: 00 02 + 9274: 04 1c + 9276: 06 03 + 9278: 01 09 + 927a: 08 00 + 927c: 01 00 + 927e: 02 04 + 9280: 1c 03 + 9282: 00 09 + 9284: 00 00 + 9286: 01 00 + 9288: 02 04 + 928a: 28 03 + 928c: 00 09 + 928e: 04 00 + 9290: 01 00 + 9292: 02 04 + 9294: 28 03 + 9296: 00 09 + 9298: 00 00 + 929a: 01 00 + 929c: 02 04 + 929e: 28 03 + 92a0: 00 09 + 92a2: 00 00 + 92a4: 01 00 + 92a6: 02 04 + 92a8: 1b 03 00 09 + 92ac: 0c 00 + 92ae: 01 00 + 92b0: 02 04 + 92b2: 1b 03 00 09 + 92b6: 00 00 + 92b8: 01 00 + 92ba: 02 04 + 92bc: 20 03 + 92be: 00 09 + 92c0: 04 00 + 92c2: 01 00 + 92c4: 02 04 + 92c6: 20 03 + 92c8: 00 09 + 92ca: 00 00 + 92cc: 01 00 + 92ce: 02 04 + 92d0: 32 03 + 92d2: 00 09 + 92d4: 20 00 + 92d6: 01 00 + 92d8: 02 04 + 92da: 32 03 + 92dc: 00 09 + 92de: 00 00 + 92e0: 01 00 + 92e2: 02 04 + 92e4: 39 03 + 92e6: 00 09 + 92e8: 04 00 + 92ea: 01 00 + 92ec: 02 04 + 92ee: 39 03 + 92f0: 00 09 + 92f2: 00 00 + 92f4: 01 00 + 92f6: 02 04 + 92f8: 39 03 + 92fa: 00 09 + 92fc: 00 00 + 92fe: 01 00 + 9300: 02 04 + 9302: 39 03 + 9304: 00 09 + 9306: 10 00 + 9308: 01 00 + 930a: 02 04 + 930c: 39 03 + 930e: 00 09 + 9310: 0c 00 + 9312: 01 00 + 9314: 02 04 + 9316: 39 03 + 9318: 00 09 + 931a: 00 00 + 931c: 01 00 + 931e: 02 04 + 9320: 39 03 + 9322: 00 09 + 9324: 0c 00 + 9326: 01 00 + 9328: 02 04 + 932a: 39 03 + 932c: 00 09 + 932e: 04 00 + 9330: 01 00 + 9332: 02 04 + 9334: 31 03 + 9336: 00 09 + 9338: 08 00 + 933a: 01 00 + 933c: 02 04 + 933e: 31 03 + 9340: 00 09 + 9342: 00 00 + 9344: 01 00 + 9346: 02 04 + 9348: 3e 03 + 934a: 00 09 + 934c: 04 00 + 934e: 01 00 + 9350: 02 04 + 9352: 3e 03 + 9354: 00 09 + 9356: 00 00 + 9358: 01 00 + 935a: 02 04 + 935c: 3e 03 + 935e: 00 09 + 9360: 00 00 + 9362: 01 00 + 9364: 02 04 + 9366: 3e 03 + 9368: 00 09 + 936a: 14 00 + 936c: 01 00 + 936e: 02 04 + 9370: 3e 03 + 9372: 00 09 + 9374: 0c 00 + 9376: 01 00 + 9378: 02 04 + 937a: 3e 03 + 937c: 00 09 + 937e: 00 00 + 9380: 01 00 + 9382: 02 04 + 9384: 3e 03 + 9386: 00 09 + 9388: 08 00 + 938a: 01 00 + 938c: 02 04 + 938e: 3e 03 + 9390: 00 09 + 9392: 04 00 + 9394: 01 00 + 9396: 02 04 + 9398: 48 03 + 939a: 00 09 + 939c: 08 00 + 939e: 01 00 + 93a0: 02 04 + 93a2: 48 03 + 93a4: 00 09 + 93a6: 00 00 + 93a8: 01 00 + 93aa: 02 04 + 93ac: 4b 06 03 00 fnmsub.s fa2, ft6, ft0, ft0, rne + 93b0: 09 04 + 93b2: 00 01 + 93b4: 00 02 + 93b6: 04 4c + 93b8: 03 00 09 08 lb zero, 128(s2) + 93bc: 00 01 + 93be: 00 02 + 93c0: 04 53 + 93c2: 06 03 + 93c4: 00 09 + 93c6: 04 00 + 93c8: 01 00 + 93ca: 02 04 + 93cc: 53 03 00 09 fsub.s ft6, ft0, fa6, rne + 93d0: 00 00 + 93d2: 01 00 + 93d4: 02 04 + 93d6: 4f 06 03 00 fnmadd.s fa2, ft6, ft0, ft0, rne + 93da: 09 20 + 93dc: 00 01 + 93de: 00 02 + 93e0: 04 50 + 93e2: 03 00 09 08 lb zero, 128(s2) + 93e6: 00 01 + 93e8: 00 02 + 93ea: 04 52 + 93ec: 06 03 + 93ee: 00 09 + 93f0: 04 00 + 93f2: 01 00 + 93f4: 02 04 + 93f6: 52 03 + 93f8: 00 09 + 93fa: 00 00 + 93fc: 01 00 + 93fe: 02 04 + 9400: 55 03 + 9402: 00 09 + 9404: 10 00 + 9406: 01 00 + 9408: 02 04 + 940a: 55 03 + 940c: 00 09 + 940e: 00 00 + 9410: 01 03 + 9412: 7f 09 08 00 + 9416: 01 03 + 9418: 00 09 + 941a: 0c 00 + 941c: 01 03 + 941e: 00 09 + 9420: 14 00 + 9422: 01 03 + 9424: 00 09 + 9426: 0c 00 + 9428: 01 03 + 942a: 00 09 + 942c: 14 00 + 942e: 01 03 + 9430: 00 09 + 9432: 08 00 + 9434: 01 03 + 9436: 00 09 + 9438: 14 00 + 943a: 01 03 + 943c: 00 09 + 943e: 10 00 + 9440: 01 03 + 9442: 00 09 + 9444: 00 00 + 9446: 01 03 + 9448: 00 09 + 944a: 00 00 + 944c: 01 03 + 944e: 00 09 + 9450: 10 00 + 9452: 01 03 + 9454: 00 09 + 9456: 00 00 + 9458: 01 03 + 945a: 00 09 + 945c: 00 00 + 945e: 01 06 + 9460: 03 77 09 04 + 9464: 00 01 + 9466: 06 03 + 9468: 09 09 + 946a: 08 00 + 946c: 01 03 + 946e: 00 09 + 9470: 00 00 + 9472: 01 03 + 9474: 00 09 + 9476: 00 00 + 9478: 01 03 + 947a: 00 09 + 947c: 10 00 + 947e: 01 03 + 9480: 00 09 + 9482: 00 00 + 9484: 01 03 + 9486: 00 09 + 9488: 00 00 + 948a: 01 09 + 948c: 08 00 + 948e: 00 01 + 9490: 01 57 + 9492: 04 00 + 9494: 00 03 + 9496: 00 92 + 9498: 00 00 + 949a: 00 01 + 949c: 01 fb + 949e: 0e 0d + 94a0: 00 01 + 94a2: 01 01 + 94a4: 01 00 + 94a6: 00 00 + 94a8: 01 00 + 94aa: 00 01 + 94ac: 2e 2e + 94ae: 2f 2e 2e 2f + 94b2: 2e 2e + 94b4: 2f 2e 2e 2f + 94b8: 72 69 + 94ba: 73 63 76 2d csrrsi t1, 727, 12 + 94be: 67 63 63 2f + 94c2: 6c 69 + 94c4: 62 67 + 94c6: 63 63 2f 73 bltu t5, s2, 1830 + 94ca: 6f 66 74 2d jal a2, 289494 + 94ce: 66 70 + 94d0: 00 2e + 94d2: 2e 2f + 94d4: 2e 2e + 94d6: 2f 2e 2e 2f + 94da: 2e 2e + 94dc: 2f 72 69 73 + 94e0: 63 76 2d 67 bgeu s10, s2, 1644 + 94e4: 63 63 2f 6c bltu t5, sp, 1734 + 94e8: 69 62 + 94ea: 67 63 63 2f + 94ee: 2e 2e + 94f0: 2f 69 6e 63 + 94f4: 6c 75 + 94f6: 64 65 + 94f8: 00 00 + 94fa: 66 69 + 94fc: 78 74 + 94fe: 66 73 + 9500: 69 2e + 9502: 63 00 01 00 beqz sp, 0 + 9506: 00 73 + 9508: 6f 66 74 2d jal a2, 289494 + 950c: 66 70 + 950e: 2e 68 + 9510: 00 01 + 9512: 00 00 + 9514: 71 75 + 9516: 61 64 + 9518: 2e 68 + 951a: 00 01 + 951c: 00 00 + 951e: 6c 6f + 9520: 6e 67 + 9522: 6c 6f + 9524: 6e 67 + 9526: 2e 68 + 9528: 00 02 + 952a: 00 00 + 952c: 00 05 + 952e: 01 00 + 9530: 05 02 + 9532: bc 49 + 9534: 01 80 + 9536: 03 23 01 05 lw t1, 80(sp) + 953a: 03 03 01 09 lb t1, 144(sp) + 953e: 00 00 + 9540: 01 03 + 9542: 00 09 + 9544: 00 00 + 9546: 01 05 + 9548: 0d 03 + 954a: 00 09 + 954c: 00 00 + 954e: 01 05 + 9550: 03 03 01 09 lb t1, 144(sp) + 9554: 00 00 + 9556: 01 03 + 9558: 00 09 + 955a: 00 00 + 955c: 01 03 + 955e: 00 09 + 9560: 00 00 + 9562: 01 03 + 9564: 00 09 + 9566: 00 00 + 9568: 01 03 + 956a: 01 09 + 956c: 00 00 + 956e: 01 03 + 9570: 02 09 + 9572: 00 00 + 9574: 01 03 + 9576: 00 09 + 9578: 00 00 + 957a: 01 05 + 957c: 01 06 + 957e: 03 7b 09 00 + 9582: 00 01 + 9584: 05 03 + 9586: 03 05 09 14 lb a0, 320(s2) + 958a: 00 01 + 958c: 06 03 + 958e: 00 09 + 9590: 04 00 + 9592: 01 03 + 9594: 01 09 + 9596: 00 00 + 9598: 01 03 + 959a: 00 09 + 959c: 00 00 + 959e: 01 03 + 95a0: 00 09 + 95a2: 00 00 + 95a4: 01 06 + 95a6: 03 01 09 08 lb sp, 128(s2) + 95aa: 00 01 + 95ac: 03 7f 09 04 + 95b0: 00 01 + 95b2: 06 03 + 95b4: 00 09 + 95b6: 14 00 + 95b8: 01 03 + 95ba: 00 09 + 95bc: 04 00 + 95be: 01 03 + 95c0: 00 09 + 95c2: 04 00 + 95c4: 01 03 + 95c6: 00 09 + 95c8: 04 00 + 95ca: 01 06 + 95cc: 03 01 09 00 lb sp, 0(s2) + 95d0: 00 01 + 95d2: 03 7f 09 04 + 95d6: 00 01 + 95d8: 06 03 + 95da: 00 09 + 95dc: 04 00 + 95de: 01 03 + 95e0: 00 09 + 95e2: 00 00 + 95e4: 01 03 + 95e6: 00 09 + 95e8: 00 00 + 95ea: 01 03 + 95ec: 01 09 + 95ee: 00 00 + 95f0: 01 03 + 95f2: 00 09 + 95f4: 00 00 + 95f6: 01 00 + 95f8: 02 04 + 95fa: 01 03 + 95fc: 00 09 + 95fe: 04 00 + 9600: 01 00 + 9602: 02 04 + 9604: 01 03 + 9606: 00 09 + 9608: 00 00 + 960a: 01 00 + 960c: 02 04 + 960e: 03 03 00 09 lb t1, 144(zero) + 9612: 04 00 + 9614: 01 00 + 9616: 02 04 + 9618: 03 03 01 09 lb t1, 144(sp) + 961c: 10 00 + 961e: 01 00 + 9620: 02 04 + 9622: 03 03 02 09 lb t1, 144(tp) + 9626: 00 00 + 9628: 01 05 + 962a: 01 00 + 962c: 02 04 + 962e: 03 06 03 01 lb a2, 16(t1) + 9632: 09 00 + 9634: 00 01 + 9636: 05 03 + 9638: 00 02 + 963a: 04 0a + 963c: 03 7c 09 0c + 9640: 00 01 + 9642: 00 02 + 9644: 04 0a + 9646: 03 7f 09 04 + 964a: 00 01 + 964c: 00 02 + 964e: 04 0a + 9650: 06 03 + 9652: 01 09 + 9654: 04 00 + 9656: 01 00 + 9658: 02 04 + 965a: 0a 03 + 965c: 00 09 + 965e: 00 00 + 9660: 01 00 + 9662: 02 04 + 9664: 0e 03 + 9666: 00 09 + 9668: 04 00 + 966a: 01 00 + 966c: 02 04 + 966e: 0e 03 + 9670: 00 09 + 9672: 00 00 + 9674: 01 00 + 9676: 02 04 + 9678: 0e 03 + 967a: 00 09 + 967c: 00 00 + 967e: 01 00 + 9680: 02 04 + 9682: 0e 03 + 9684: 00 09 + 9686: 00 00 + 9688: 01 00 + 968a: 02 04 + 968c: 0e 03 + 968e: 00 09 + 9690: 0c 00 + 9692: 01 00 + 9694: 02 04 + 9696: 14 06 + 9698: 03 00 09 04 lb zero, 64(s2) + 969c: 00 01 + 969e: 06 03 + 96a0: 00 09 + 96a2: 08 00 + 96a4: 01 03 + 96a6: 00 09 + 96a8: 00 00 + 96aa: 01 03 + 96ac: 00 09 + 96ae: 00 00 + 96b0: 01 03 + 96b2: 00 09 + 96b4: 00 00 + 96b6: 01 03 + 96b8: 00 09 + 96ba: 00 00 + 96bc: 01 03 + 96be: 00 09 + 96c0: 00 00 + 96c2: 01 03 + 96c4: 00 09 + 96c6: 00 00 + 96c8: 01 03 + 96ca: 00 09 + 96cc: 00 00 + 96ce: 01 03 + 96d0: 00 09 + 96d2: 00 00 + 96d4: 01 03 + 96d6: 00 09 + 96d8: 00 00 + 96da: 01 03 + 96dc: 00 09 + 96de: 00 00 + 96e0: 01 03 + 96e2: 00 09 + 96e4: 00 00 + 96e6: 01 03 + 96e8: 00 09 + 96ea: 00 00 + 96ec: 01 03 + 96ee: 00 09 + 96f0: 00 00 + 96f2: 01 03 + 96f4: 00 09 + 96f6: 00 00 + 96f8: 01 03 + 96fa: 00 09 + 96fc: 00 00 + 96fe: 01 03 + 9700: 00 09 + 9702: 00 00 + 9704: 01 03 + 9706: 00 09 + 9708: 00 00 + 970a: 01 03 + 970c: 00 09 + 970e: 00 00 + 9710: 01 03 + 9712: 00 09 + 9714: 00 00 + 9716: 01 03 + 9718: 00 09 + 971a: 00 00 + 971c: 01 03 + 971e: 00 09 + 9720: 00 00 + 9722: 01 03 + 9724: 00 09 + 9726: 00 00 + 9728: 01 03 + 972a: 00 09 + 972c: 00 00 + 972e: 01 03 + 9730: 00 09 + 9732: 00 00 + 9734: 01 03 + 9736: 00 09 + 9738: 00 00 + 973a: 01 00 + 973c: 02 04 + 973e: 2a 03 + 9740: 00 09 + 9742: 10 00 + 9744: 01 00 + 9746: 02 04 + 9748: 01 03 + 974a: 01 09 + 974c: 10 00 + 974e: 01 00 + 9750: 02 04 + 9752: 0d 03 + 9754: 7f 09 0c 00 + 9758: 01 00 + 975a: 02 04 + 975c: 0d 03 + 975e: 00 09 + 9760: 00 00 + 9762: 01 00 + 9764: 02 04 + 9766: 0d 03 + 9768: 00 09 + 976a: 14 00 + 976c: 01 00 + 976e: 02 04 + 9770: 0d 03 + 9772: 00 09 + 9774: 00 00 + 9776: 01 00 + 9778: 02 04 + 977a: 0d 03 + 977c: 00 09 + 977e: 00 00 + 9780: 01 00 + 9782: 02 04 + 9784: 0d 03 + 9786: 00 09 + 9788: 00 00 + 978a: 01 00 + 978c: 02 04 + 978e: 0d 03 + 9790: 00 09 + 9792: 00 00 + 9794: 01 00 + 9796: 02 04 + 9798: 0d 03 + 979a: 00 09 + 979c: 00 00 + 979e: 01 00 + 97a0: 02 04 + 97a2: 0d 03 + 97a4: 00 09 + 97a6: 04 00 + 97a8: 01 00 + 97aa: 02 04 + 97ac: 0d 03 + 97ae: 00 09 + 97b0: 00 00 + 97b2: 01 00 + 97b4: 02 04 + 97b6: 0d 03 + 97b8: 00 09 + 97ba: 00 00 + 97bc: 01 00 + 97be: 02 04 + 97c0: 0d 03 + 97c2: 00 09 + 97c4: 00 00 + 97c6: 01 00 + 97c8: 02 04 + 97ca: 38 03 + 97cc: 00 09 + 97ce: 0c 00 + 97d0: 01 00 + 97d2: 02 04 + 97d4: 38 03 + 97d6: 00 09 + 97d8: 10 00 + 97da: 01 00 + 97dc: 02 04 + 97de: 38 03 + 97e0: 00 09 + 97e2: 00 00 + 97e4: 01 00 + 97e6: 02 04 + 97e8: 39 03 + 97ea: 00 09 + 97ec: 04 00 + 97ee: 01 03 + 97f0: 00 09 + 97f2: 0c 00 + 97f4: 01 03 + 97f6: 00 09 + 97f8: 10 00 + 97fa: 01 03 + 97fc: 00 09 + 97fe: 00 00 + 9800: 01 00 + 9802: 02 04 + 9804: 44 03 + 9806: 00 09 + 9808: 00 00 + 980a: 01 00 + 980c: 02 04 + 980e: 44 03 + 9810: 00 09 + 9812: 00 00 + 9814: 01 00 + 9816: 02 04 + 9818: 44 03 + 981a: 00 09 + 981c: 00 00 + 981e: 01 00 + 9820: 02 04 + 9822: 44 03 + 9824: 00 09 + 9826: 00 00 + 9828: 01 00 + 982a: 02 04 + 982c: 44 03 + 982e: 00 09 + 9830: 00 00 + 9832: 01 00 + 9834: 02 04 + 9836: 44 03 + 9838: 00 09 + 983a: 00 00 + 983c: 01 00 + 983e: 02 04 + 9840: 44 03 + 9842: 00 09 + 9844: 00 00 + 9846: 01 00 + 9848: 02 04 + 984a: 44 03 + 984c: 00 09 + 984e: 00 00 + 9850: 01 00 + 9852: 02 04 + 9854: 44 03 + 9856: 00 09 + 9858: 00 00 + 985a: 01 00 + 985c: 02 04 + 985e: 44 03 + 9860: 00 09 + 9862: 04 00 + 9864: 01 00 + 9866: 02 04 + 9868: 44 03 + 986a: 00 09 + 986c: 00 00 + 986e: 01 00 + 9870: 02 04 + 9872: 4e 03 + 9874: 00 09 + 9876: 04 00 + 9878: 01 00 + 987a: 02 04 + 987c: 5c 03 + 987e: 00 09 + 9880: 04 00 + 9882: 01 00 + 9884: 02 04 + 9886: 5c 03 + 9888: 01 09 + 988a: 00 00 + 988c: 01 00 + 988e: 02 04 + 9890: 5c 03 + 9892: 00 09 + 9894: 00 00 + 9896: 01 00 + 9898: 02 04 + 989a: 3b 06 03 7f + 989e: 09 0c + 98a0: 00 01 + 98a2: 00 02 + 98a4: 04 3b + 98a6: 06 03 + 98a8: 00 09 + 98aa: 14 00 + 98ac: 01 00 + 98ae: 02 04 + 98b0: 3b 03 00 09 + 98b4: 08 00 + 98b6: 01 00 + 98b8: 02 04 + 98ba: 3f 03 00 09 + 98be: 1c 00 + 98c0: 01 00 + 98c2: 02 04 + 98c4: 42 03 + 98c6: 00 09 + 98c8: 0c 00 + 98ca: 01 00 + 98cc: 02 04 + 98ce: 41 03 + 98d0: 00 09 + 98d2: 18 00 + 98d4: 01 00 + 98d6: 02 04 + 98d8: 41 03 + 98da: 00 09 + 98dc: 04 00 + 98de: 01 06 + 98e0: 03 00 09 0c lb zero, 192(s2) + 98e4: 00 01 + 98e6: 09 14 + 98e8: 00 00 + 98ea: 01 01 + 98ec: 99 03 + 98ee: 00 00 + 98f0: 03 00 94 00 lb zero, 9(s0) + 98f4: 00 00 + 98f6: 01 01 + 98f8: fb 0e 0d 00 + 98fc: 01 01 + 98fe: 01 01 + 9900: 00 00 + 9902: 00 01 + 9904: 00 00 + 9906: 01 2e + 9908: 2e 2f + 990a: 2e 2e + 990c: 2f 2e 2e 2f + 9910: 2e 2e + 9912: 2f 72 69 73 + 9916: 63 76 2d 67 bgeu s10, s2, 1644 + 991a: 63 63 2f 6c bltu t5, sp, 1734 + 991e: 69 62 + 9920: 67 63 63 2f + 9924: 73 6f 66 74 csrrsi t5, 1862, 12 + 9928: 2d 66 + 992a: 70 00 + 992c: 2e 2e + 992e: 2f 2e 2e 2f + 9932: 2e 2e + 9934: 2f 2e 2e 2f + 9938: 72 69 + 993a: 73 63 76 2d csrrsi t1, 727, 12 + 993e: 67 63 63 2f + 9942: 6c 69 + 9944: 62 67 + 9946: 63 63 2f 2e bltu t5, sp, 742 + 994a: 2e 2f + 994c: 69 6e + 994e: 63 6c 75 64 bltu a0, t2, 1624 + 9952: 65 00 + 9954: 00 66 + 9956: 6c 6f + 9958: 61 74 + 995a: 73 69 74 66 csrrsi s2, 1639, 8 + 995e: 2e 63 + 9960: 00 01 + 9962: 00 00 + 9964: 73 6f 66 74 csrrsi t5, 1862, 12 + 9968: 2d 66 + 996a: 70 2e + 996c: 68 00 + 996e: 01 00 + 9970: 00 71 + 9972: 75 61 + 9974: 64 2e + 9976: 68 00 + 9978: 01 00 + 997a: 00 6c + 997c: 6f 6e 67 6c jal t3, 485062 + 9980: 6f 6e 67 2e jal t3, 484070 + 9984: 68 00 + 9986: 02 00 + 9988: 00 00 + 998a: 05 01 + 998c: 00 05 + 998e: 02 68 + 9990: 4b 01 80 03 + 9994: 24 01 + 9996: 05 03 + 9998: 03 01 09 00 lb sp, 0(s2) + 999c: 00 01 + 999e: 03 00 09 00 lb zero, 0(s2) + 99a2: 00 01 + 99a4: 03 00 09 00 lb zero, 0(s2) + 99a8: 00 01 + 99aa: 03 00 09 00 lb zero, 0(s2) + 99ae: 00 01 + 99b0: 03 01 09 00 lb sp, 0(s2) + 99b4: 00 01 + 99b6: 03 02 09 00 lb tp, 0(s2) + 99ba: 00 01 + 99bc: 03 00 09 00 lb zero, 0(s2) + 99c0: 00 01 + 99c2: 05 01 + 99c4: 06 03 + 99c6: 7c 09 + 99c8: 00 00 + 99ca: 01 03 + 99cc: 00 09 + 99ce: 14 00 + 99d0: 01 05 + 99d2: 03 03 04 09 lb t1, 144(s0) + 99d6: 04 00 + 99d8: 01 00 + 99da: 02 04 + 99dc: 01 06 + 99de: 03 00 09 04 lb zero, 64(s2) + 99e2: 00 01 + 99e4: 00 02 + 99e6: 04 01 + 99e8: 03 00 09 00 lb zero, 0(s2) + 99ec: 00 01 + 99ee: 00 02 + 99f0: 04 01 + 99f2: 03 00 09 14 lb zero, 320(s2) + 99f6: 00 01 + 99f8: 00 02 + 99fa: 04 01 + 99fc: 03 00 09 00 lb zero, 0(s2) + 9a00: 00 01 + 9a02: 00 02 + 9a04: 04 01 + 9a06: 03 00 09 00 lb zero, 0(s2) + 9a0a: 00 01 + 9a0c: 00 02 + 9a0e: 04 01 + 9a10: 03 00 09 00 lb zero, 0(s2) + 9a14: 00 01 + 9a16: 00 02 + 9a18: 04 01 + 9a1a: 03 00 09 00 lb zero, 0(s2) + 9a1e: 00 01 + 9a20: 00 02 + 9a22: 04 01 + 9a24: 03 00 09 00 lb zero, 0(s2) + 9a28: 00 01 + 9a2a: 00 02 + 9a2c: 04 01 + 9a2e: 03 00 09 00 lb zero, 0(s2) + 9a32: 00 01 + 9a34: 00 02 + 9a36: 04 01 + 9a38: 03 00 09 04 lb zero, 64(s2) + 9a3c: 00 01 + 9a3e: 00 02 + 9a40: 04 01 + 9a42: 03 00 09 00 lb zero, 0(s2) + 9a46: 00 01 + 9a48: 00 02 + 9a4a: 04 01 + 9a4c: 03 00 09 10 lb zero, 256(s2) + 9a50: 00 01 + 9a52: 00 02 + 9a54: 04 01 + 9a56: 03 00 09 00 lb zero, 0(s2) + 9a5a: 00 01 + 9a5c: 00 02 + 9a5e: 04 01 + 9a60: 03 00 09 00 lb zero, 0(s2) + 9a64: 00 01 + 9a66: 00 02 + 9a68: 04 01 + 9a6a: 03 00 09 00 lb zero, 0(s2) + 9a6e: 00 01 + 9a70: 00 02 + 9a72: 04 01 + 9a74: 03 00 09 04 lb zero, 64(s2) + 9a78: 00 01 + 9a7a: 00 02 + 9a7c: 04 01 + 9a7e: 03 00 09 08 lb zero, 128(s2) + 9a82: 00 01 + 9a84: 00 02 + 9a86: 04 01 + 9a88: 03 00 09 04 lb zero, 64(s2) + 9a8c: 00 01 + 9a8e: 00 02 + 9a90: 04 01 + 9a92: 03 00 09 04 lb zero, 64(s2) + 9a96: 00 01 + 9a98: 00 02 + 9a9a: 04 01 + 9a9c: 03 00 09 00 lb zero, 0(s2) + 9aa0: 00 01 + 9aa2: 00 02 + 9aa4: 04 01 + 9aa6: 03 00 09 00 lb zero, 0(s2) + 9aaa: 00 01 + 9aac: 00 02 + 9aae: 04 01 + 9ab0: 03 00 09 00 lb zero, 0(s2) + 9ab4: 00 01 + 9ab6: 00 02 + 9ab8: 04 01 + 9aba: 03 00 09 00 lb zero, 0(s2) + 9abe: 00 01 + 9ac0: 00 02 + 9ac2: 04 01 + 9ac4: 03 00 09 00 lb zero, 0(s2) + 9ac8: 00 01 + 9aca: 00 02 + 9acc: 04 01 + 9ace: 03 00 09 00 lb zero, 0(s2) + 9ad2: 00 01 + 9ad4: 00 02 + 9ad6: 04 01 + 9ad8: 03 00 09 00 lb zero, 0(s2) + 9adc: 00 01 + 9ade: 00 02 + 9ae0: 04 01 + 9ae2: 03 00 09 00 lb zero, 0(s2) + 9ae6: 00 01 + 9ae8: 03 00 09 08 lb zero, 128(s2) + 9aec: 00 01 + 9aee: 03 00 09 08 lb zero, 128(s2) + 9af2: 00 01 + 9af4: 03 00 09 10 lb zero, 256(s2) + 9af8: 00 01 + 9afa: 03 00 09 00 lb zero, 0(s2) + 9afe: 00 01 + 9b00: 00 02 + 9b02: 04 20 + 9b04: 03 00 09 00 lb zero, 0(s2) + 9b08: 00 01 + 9b0a: 03 00 09 1c lb zero, 448(s2) + 9b0e: 00 01 + 9b10: 03 00 09 00 lb zero, 0(s2) + 9b14: 00 01 + 9b16: 03 00 09 20 lb zero, 512(s2) + 9b1a: 00 01 + 9b1c: 03 00 09 00 lb zero, 0(s2) + 9b20: 00 01 + 9b22: 03 00 09 08 lb zero, 128(s2) + 9b26: 00 01 + 9b28: 03 00 09 04 lb zero, 64(s2) + 9b2c: 00 01 + 9b2e: 03 00 09 00 lb zero, 0(s2) + 9b32: 00 01 + 9b34: 00 02 + 9b36: 04 23 + 9b38: 06 03 + 9b3a: 00 09 + 9b3c: 04 00 + 9b3e: 01 00 + 9b40: 02 04 + 9b42: 23 06 03 00 sb zero, 12(t1) + 9b46: 09 04 + 9b48: 00 01 + 9b4a: 00 02 + 9b4c: 04 23 + 9b4e: 03 00 09 10 lb zero, 256(s2) + 9b52: 00 01 + 9b54: 00 02 + 9b56: 04 23 + 9b58: 03 00 09 04 lb zero, 64(s2) + 9b5c: 00 01 + 9b5e: 00 03 + 9b60: 04 9b + 9b62: 01 03 + 9b64: 00 09 + 9b66: 04 00 + 9b68: 01 00 + 9b6a: 03 04 9b 01 lb s0, 25(s6) + 9b6e: 03 01 09 00 lb sp, 0(s2) + 9b72: 00 01 + 9b74: 00 03 + 9b76: 04 9b + 9b78: 01 03 + 9b7a: 00 09 + 9b7c: 00 00 + 9b7e: 01 00 + 9b80: 03 04 9b 01 lb s0, 25(s6) + 9b84: 03 00 09 00 lb zero, 0(s2) + 9b88: 00 01 + 9b8a: 00 03 + 9b8c: 04 9b + 9b8e: 01 03 + 9b90: 00 09 + 9b92: 00 00 + 9b94: 01 00 + 9b96: 03 04 9b 01 lb s0, 25(s6) + 9b9a: 03 00 09 00 lb zero, 0(s2) + 9b9e: 00 01 + 9ba0: 00 03 + 9ba2: 04 9b + 9ba4: 01 03 + 9ba6: 00 09 + 9ba8: 00 00 + 9baa: 01 05 + 9bac: 01 00 + 9bae: 03 04 9b 01 lb s0, 25(s6) + 9bb2: 06 03 + 9bb4: 03 09 04 00 lb s2, 0(s0) + 9bb8: 01 05 + 9bba: 03 00 03 04 lb zero, 64(t1) + 9bbe: 9b 01 03 7d + 9bc2: 09 08 + 9bc4: 00 01 + 9bc6: 00 03 + 9bc8: 04 9b + 9bca: 01 06 + 9bcc: 03 00 09 04 lb zero, 64(s2) + 9bd0: 00 01 + 9bd2: 00 03 + 9bd4: 04 9b + 9bd6: 01 03 + 9bd8: 00 09 + 9bda: 00 00 + 9bdc: 01 05 + 9bde: 0a 00 + 9be0: 03 04 9b 01 lb s0, 25(s6) + 9be4: 06 03 + 9be6: 02 09 + 9be8: 08 00 + 9bea: 01 05 + 9bec: 03 00 03 04 lb zero, 64(t1) + 9bf0: 9b 01 03 7e + 9bf4: 09 04 + 9bf6: 00 01 + 9bf8: 00 03 + 9bfa: 04 9b + 9bfc: 01 06 + 9bfe: 03 00 09 04 lb zero, 64(s2) + 9c02: 00 01 + 9c04: 00 03 + 9c06: 04 9b + 9c08: 01 03 + 9c0a: 00 09 + 9c0c: 00 00 + 9c0e: 01 00 + 9c10: 03 04 9b 01 lb s0, 25(s6) + 9c14: 03 02 09 00 lb tp, 0(s2) + 9c18: 00 01 + 9c1a: 05 01 + 9c1c: 00 03 + 9c1e: 04 9b + 9c20: 01 06 + 9c22: 03 01 09 00 lb sp, 0(s2) + 9c26: 00 01 + 9c28: 05 0a + 9c2a: 00 03 + 9c2c: 04 9b + 9c2e: 01 03 + 9c30: 7f 09 04 00 + 9c34: 01 05 + 9c36: 01 00 + 9c38: 03 04 9b 01 lb s0, 25(s6) + 9c3c: 03 01 09 08 lb sp, 128(s2) + 9c40: 00 01 + 9c42: 05 0a + 9c44: 00 03 + 9c46: 04 9b + 9c48: 01 03 + 9c4a: 7f 09 04 00 + 9c4e: 01 05 + 9c50: 01 00 + 9c52: 03 04 9b 01 lb s0, 25(s6) + 9c56: 03 01 09 14 lb sp, 320(s2) + 9c5a: 00 01 + 9c5c: 05 03 + 9c5e: 03 7c 09 0c + 9c62: 00 01 + 9c64: 00 02 + 9c66: 04 02 + 9c68: 06 03 + 9c6a: 00 09 + 9c6c: 08 00 + 9c6e: 01 00 + 9c70: 02 04 + 9c72: 02 03 + 9c74: 00 09 + 9c76: 00 00 + 9c78: 01 00 + 9c7a: 02 04 + 9c7c: 02 03 + 9c7e: 00 09 + 9c80: 00 00 + 9c82: 01 09 + 9c84: 18 00 + 9c86: 00 01 + 9c88: 01 df + 9c8a: 03 00 00 03 lb zero, 48(zero) + 9c8e: 00 a4 + 9c90: 00 00 + 9c92: 00 01 + 9c94: 01 fb + 9c96: 0e 0d + 9c98: 00 01 + 9c9a: 01 01 + 9c9c: 01 00 + 9c9e: 00 00 + 9ca0: 01 00 + 9ca2: 00 01 + 9ca4: 2e 2e + 9ca6: 2f 2e 2e 2f + 9caa: 2e 2e + 9cac: 2f 2e 2e 2f + 9cb0: 72 69 + 9cb2: 73 63 76 2d csrrsi t1, 727, 12 + 9cb6: 67 63 63 2f + 9cba: 6c 69 + 9cbc: 62 67 + 9cbe: 63 63 2f 73 bltu t5, s2, 1830 + 9cc2: 6f 66 74 2d jal a2, 289494 + 9cc6: 66 70 + 9cc8: 00 2e + 9cca: 2e 2f + 9ccc: 2e 2e + 9cce: 2f 2e 2e 2f + 9cd2: 2e 2e + 9cd4: 2f 72 69 73 + 9cd8: 63 76 2d 67 bgeu s10, s2, 1644 + 9cdc: 63 63 2f 6c bltu t5, sp, 1734 + 9ce0: 69 62 + 9ce2: 67 63 63 2f + 9ce6: 2e 2e + 9ce8: 2f 69 6e 63 + 9cec: 6c 75 + 9cee: 64 65 + 9cf0: 00 00 + 9cf2: 65 78 + 9cf4: 74 65 + 9cf6: 6e 64 + 9cf8: 73 66 64 66 csrrsi a2, 1638, 8 + 9cfc: 32 2e + 9cfe: 63 00 01 00 beqz sp, 0 + 9d02: 00 73 + 9d04: 6f 66 74 2d jal a2, 289494 + 9d08: 66 70 + 9d0a: 2e 68 + 9d0c: 00 01 + 9d0e: 00 00 + 9d10: 73 69 6e 67 csrrsi s2, 1654, 28 + 9d14: 6c 65 + 9d16: 2e 68 + 9d18: 00 01 + 9d1a: 00 00 + 9d1c: 64 6f + 9d1e: 75 62 + 9d20: 6c 65 + 9d22: 2e 68 + 9d24: 00 01 + 9d26: 00 00 + 9d28: 6c 6f + 9d2a: 6e 67 + 9d2c: 6c 6f + 9d2e: 6e 67 + 9d30: 2e 68 + 9d32: 00 02 + 9d34: 00 00 + 9d36: 00 05 + 9d38: 01 00 + 9d3a: 05 02 + 9d3c: b8 4c + 9d3e: 01 80 + 9d40: 03 25 01 05 lw a0, 80(sp) + 9d44: 03 03 01 09 lb t1, 144(sp) + 9d48: 00 00 + 9d4a: 01 03 + 9d4c: 00 09 + 9d4e: 00 00 + 9d50: 01 05 + 9d52: 0d 03 + 9d54: 00 09 + 9d56: 00 00 + 9d58: 01 05 + 9d5a: 03 03 01 09 lb t1, 144(sp) + 9d5e: 00 00 + 9d60: 01 03 + 9d62: 00 09 + 9d64: 00 00 + 9d66: 01 03 + 9d68: 00 09 + 9d6a: 00 00 + 9d6c: 01 03 + 9d6e: 00 09 + 9d70: 00 00 + 9d72: 01 03 + 9d74: 01 09 + 9d76: 00 00 + 9d78: 01 03 + 9d7a: 00 09 + 9d7c: 00 00 + 9d7e: 01 03 + 9d80: 00 09 + 9d82: 00 00 + 9d84: 01 03 + 9d86: 00 09 + 9d88: 00 00 + 9d8a: 01 03 + 9d8c: 01 09 + 9d8e: 00 00 + 9d90: 01 03 + 9d92: 02 09 + 9d94: 00 00 + 9d96: 01 03 + 9d98: 00 09 + 9d9a: 00 00 + 9d9c: 01 05 + 9d9e: 01 06 + 9da0: 03 7a 09 00 + 9da4: 00 01 + 9da6: 05 03 + 9da8: 03 06 09 18 lb a2, 384(s2) + 9dac: 00 01 + 9dae: 06 03 + 9db0: 00 09 + 9db2: 04 00 + 9db4: 01 03 + 9db6: 01 09 + 9db8: 00 00 + 9dba: 01 03 + 9dbc: 00 09 + 9dbe: 00 00 + 9dc0: 01 03 + 9dc2: 00 09 + 9dc4: 00 00 + 9dc6: 01 03 + 9dc8: 00 09 + 9dca: 00 00 + 9dcc: 01 06 + 9dce: 03 02 09 08 lb tp, 128(s2) + 9dd2: 00 01 + 9dd4: 03 7e 09 04 + 9dd8: 00 01 + 9dda: 03 02 09 04 lb tp, 64(s2) + 9dde: 00 01 + 9de0: 03 7e 09 04 + 9de4: 00 01 + 9de6: 06 03 + 9de8: 00 09 + 9dea: 04 00 + 9dec: 01 03 + 9dee: 00 09 + 9df0: 00 00 + 9df2: 01 03 + 9df4: 00 09 + 9df6: 04 00 + 9df8: 01 03 + 9dfa: 02 09 + 9dfc: 00 00 + 9dfe: 01 03 + 9e00: 00 09 + 9e02: 00 00 + 9e04: 01 03 + 9e06: 00 09 + 9e08: 00 00 + 9e0a: 01 03 + 9e0c: 00 09 + 9e0e: 00 00 + 9e10: 01 03 + 9e12: 00 09 + 9e14: 00 00 + 9e16: 01 03 + 9e18: 00 09 + 9e1a: 00 00 + 9e1c: 01 03 + 9e1e: 00 09 + 9e20: 00 00 + 9e22: 01 00 + 9e24: 02 04 + 9e26: 01 03 + 9e28: 00 09 + 9e2a: 04 00 + 9e2c: 01 00 + 9e2e: 02 04 + 9e30: 01 03 + 9e32: 00 09 + 9e34: 08 00 + 9e36: 01 00 + 9e38: 02 04 + 9e3a: 01 03 + 9e3c: 00 09 + 9e3e: 00 00 + 9e40: 01 00 + 9e42: 02 04 + 9e44: 01 03 + 9e46: 00 09 + 9e48: 00 00 + 9e4a: 01 00 + 9e4c: 02 04 + 9e4e: 01 03 + 9e50: 00 09 + 9e52: 00 00 + 9e54: 01 00 + 9e56: 02 04 + 9e58: 01 03 + 9e5a: 00 09 + 9e5c: 04 00 + 9e5e: 01 00 + 9e60: 02 04 + 9e62: 01 06 + 9e64: 03 78 09 00 + 9e68: 00 01 + 9e6a: 00 02 + 9e6c: 04 35 + 9e6e: 06 03 + 9e70: 08 09 + 9e72: 04 00 + 9e74: 01 00 + 9e76: 02 04 + 9e78: 35 03 + 9e7a: 00 09 + 9e7c: 00 00 + 9e7e: 01 00 + 9e80: 02 04 + 9e82: 35 03 + 9e84: 04 09 + 9e86: 00 00 + 9e88: 01 00 + 9e8a: 02 04 + 9e8c: 35 03 + 9e8e: 00 09 + 9e90: 00 00 + 9e92: 01 00 + 9e94: 02 04 + 9e96: 35 03 + 9e98: 00 09 + 9e9a: 00 00 + 9e9c: 01 00 + 9e9e: 02 04 + 9ea0: 35 03 + 9ea2: 00 09 + 9ea4: 00 00 + 9ea6: 01 00 + 9ea8: 02 04 + 9eaa: 35 03 + 9eac: 00 09 + 9eae: 00 00 + 9eb0: 01 00 + 9eb2: 02 04 + 9eb4: 35 03 + 9eb6: 00 09 + 9eb8: 00 00 + 9eba: 01 00 + 9ebc: 02 04 + 9ebe: 35 03 + 9ec0: 00 09 + 9ec2: 00 00 + 9ec4: 01 00 + 9ec6: 02 04 + 9ec8: 35 03 + 9eca: 00 09 + 9ecc: 20 00 + 9ece: 01 00 + 9ed0: 02 04 + 9ed2: 35 03 + 9ed4: 01 09 + 9ed6: 00 00 + 9ed8: 01 00 + 9eda: 02 04 + 9edc: 35 03 + 9ede: 00 09 + 9ee0: 00 00 + 9ee2: 01 00 + 9ee4: 02 04 + 9ee6: 01 03 + 9ee8: 00 09 + 9eea: 04 00 + 9eec: 01 00 + 9eee: 02 04 + 9ef0: 01 03 + 9ef2: 00 09 + 9ef4: 04 00 + 9ef6: 01 00 + 9ef8: 02 04 + 9efa: 01 03 + 9efc: 02 09 + 9efe: 00 00 + 9f00: 01 05 + 9f02: 01 06 + 9f04: 03 01 09 00 lb sp, 0(s2) + 9f08: 00 01 + 9f0a: 05 03 + 9f0c: 00 02 + 9f0e: 04 02 + 9f10: 06 03 + 9f12: 78 09 + 9f14: 18 00 + 9f16: 01 00 + 9f18: 02 04 + 9f1a: 0c 03 + 9f1c: 00 09 + 9f1e: 04 00 + 9f20: 01 00 + 9f22: 02 04 + 9f24: 0c 03 + 9f26: 00 09 + 9f28: 00 00 + 9f2a: 01 00 + 9f2c: 02 04 + 9f2e: 0c 03 + 9f30: 00 09 + 9f32: 00 00 + 9f34: 01 00 + 9f36: 02 04 + 9f38: 0c 03 + 9f3a: 00 09 + 9f3c: 00 00 + 9f3e: 01 00 + 9f40: 02 04 + 9f42: 10 03 + 9f44: 00 09 + 9f46: 04 00 + 9f48: 01 00 + 9f4a: 02 04 + 9f4c: 10 03 + 9f4e: 00 09 + 9f50: 00 00 + 9f52: 01 00 + 9f54: 02 04 + 9f56: 10 03 + 9f58: 00 09 + 9f5a: 00 00 + 9f5c: 01 00 + 9f5e: 02 04 + 9f60: 10 03 + 9f62: 00 09 + 9f64: 00 00 + 9f66: 01 00 + 9f68: 02 04 + 9f6a: 10 03 + 9f6c: 00 09 + 9f6e: 00 00 + 9f70: 01 00 + 9f72: 02 04 + 9f74: 10 03 + 9f76: 00 09 + 9f78: 00 00 + 9f7a: 01 00 + 9f7c: 02 04 + 9f7e: 10 03 + 9f80: 00 09 + 9f82: 00 00 + 9f84: 01 00 + 9f86: 02 04 + 9f88: 10 03 + 9f8a: 00 09 + 9f8c: 08 00 + 9f8e: 01 00 + 9f90: 02 04 + 9f92: 10 03 + 9f94: 00 09 + 9f96: 00 00 + 9f98: 01 00 + 9f9a: 02 04 + 9f9c: 1d 03 + 9f9e: 00 09 + 9fa0: 08 00 + 9fa2: 01 00 + 9fa4: 02 04 + 9fa6: 1d 03 + 9fa8: 00 09 + 9faa: 00 00 + 9fac: 01 00 + 9fae: 02 04 + 9fb0: 1d 03 + 9fb2: 00 09 + 9fb4: 10 00 + 9fb6: 01 00 + 9fb8: 02 04 + 9fba: 1d 03 + 9fbc: 00 09 + 9fbe: 04 00 + 9fc0: 01 00 + 9fc2: 02 04 + 9fc4: 26 03 + 9fc6: 00 09 + 9fc8: 00 00 + 9fca: 01 00 + 9fcc: 02 04 + 9fce: 1e 03 + 9fd0: 00 09 + 9fd2: 0c 00 + 9fd4: 01 00 + 9fd6: 02 04 + 9fd8: 1e 03 + 9fda: 00 09 + 9fdc: 08 00 + 9fde: 01 00 + 9fe0: 02 04 + 9fe2: 09 03 + 9fe4: 00 09 + 9fe6: 08 00 + 9fe8: 01 00 + 9fea: 02 04 + 9fec: 09 03 + 9fee: 00 09 + 9ff0: 00 00 + 9ff2: 01 00 + 9ff4: 02 04 + 9ff6: 27 03 00 09 + 9ffa: 08 00 + 9ffc: 01 06 + 9ffe: 03 00 09 08 lb zero, 128(s2) + a002: 00 01 + a004: 00 02 + a006: 04 2d + a008: 06 03 + a00a: 00 09 + a00c: 04 00 + a00e: 01 00 + a010: 02 04 + a012: 2d 03 + a014: 00 09 + a016: 00 00 + a018: 01 00 + a01a: 02 04 + a01c: 2d 03 + a01e: 00 09 + a020: 00 00 + a022: 01 00 + a024: 02 04 + a026: 2d 03 + a028: 00 09 + a02a: 04 00 + a02c: 01 00 + a02e: 02 04 + a030: 2d 03 + a032: 00 09 + a034: 08 00 + a036: 01 00 + a038: 02 04 + a03a: 2d 03 + a03c: 00 09 + a03e: 00 00 + a040: 01 00 + a042: 02 04 + a044: 2d 03 + a046: 00 09 + a048: 00 00 + a04a: 01 00 + a04c: 02 04 + a04e: 2d 03 + a050: 00 09 + a052: 00 00 + a054: 01 00 + a056: 02 04 + a058: 2d 03 + a05a: 00 09 + a05c: 00 00 + a05e: 01 06 + a060: 03 00 09 04 lb zero, 64(s2) + a064: 00 01 + a066: 09 14 + a068: 00 00 + a06a: 01 01 + a06c: 57 06 00 00 + a070: 03 00 a2 00 lb zero, 10(tp) + a074: 00 00 + a076: 01 01 + a078: fb 0e 0d 00 + a07c: 01 01 + a07e: 01 01 + a080: 00 00 + a082: 00 01 + a084: 00 00 + a086: 01 2e + a088: 2e 2f + a08a: 2e 2e + a08c: 2f 2e 2e 2f + a090: 2e 2e + a092: 2f 72 69 73 + a096: 63 76 2d 67 bgeu s10, s2, 1644 + a09a: 63 63 2f 6c bltu t5, sp, 1734 + a09e: 69 62 + a0a0: 67 63 63 2f + a0a4: 73 6f 66 74 csrrsi t5, 1862, 12 + a0a8: 2d 66 + a0aa: 70 00 + a0ac: 2e 2e + a0ae: 2f 2e 2e 2f + a0b2: 2e 2e + a0b4: 2f 2e 2e 2f + a0b8: 72 69 + a0ba: 73 63 76 2d csrrsi t1, 727, 12 + a0be: 67 63 63 2f + a0c2: 6c 69 + a0c4: 62 67 + a0c6: 63 63 2f 2e bltu t5, sp, 742 + a0ca: 2e 2f + a0cc: 69 6e + a0ce: 63 6c 75 64 bltu a0, t2, 1624 + a0d2: 65 00 + a0d4: 00 65 + a0d6: 78 74 + a0d8: 65 6e + a0da: 64 64 + a0dc: 66 74 + a0de: 66 32 + a0e0: 2e 63 + a0e2: 00 01 + a0e4: 00 00 + a0e6: 73 6f 66 74 csrrsi t5, 1862, 12 + a0ea: 2d 66 + a0ec: 70 2e + a0ee: 68 00 + a0f0: 01 00 + a0f2: 00 64 + a0f4: 6f 75 62 6c jal a0, 161478 + a0f8: 65 2e + a0fa: 68 00 + a0fc: 01 00 + a0fe: 00 71 + a100: 75 61 + a102: 64 2e + a104: 68 00 + a106: 01 00 + a108: 00 6c + a10a: 6f 6e 67 6c jal t3, 485062 + a10e: 6f 6e 67 2e jal t3, 484070 + a112: 68 00 + a114: 02 00 + a116: 00 00 + a118: 05 01 + a11a: 00 05 + a11c: 02 c4 + a11e: 4d 01 + a120: 80 03 + a122: 25 01 + a124: 05 03 + a126: 03 01 09 00 lb sp, 0(s2) + a12a: 00 01 + a12c: 03 00 09 00 lb zero, 0(s2) + a130: 00 01 + a132: 05 0d + a134: 03 00 09 00 lb zero, 0(s2) + a138: 00 01 + a13a: 05 03 + a13c: 03 01 09 00 lb sp, 0(s2) + a140: 00 01 + a142: 03 00 09 00 lb zero, 0(s2) + a146: 00 01 + a148: 03 00 09 00 lb zero, 0(s2) + a14c: 00 01 + a14e: 03 00 09 00 lb zero, 0(s2) + a152: 00 01 + a154: 03 01 09 00 lb sp, 0(s2) + a158: 00 01 + a15a: 03 00 09 00 lb zero, 0(s2) + a15e: 00 01 + a160: 03 00 09 00 lb zero, 0(s2) + a164: 00 01 + a166: 03 00 09 00 lb zero, 0(s2) + a16a: 00 01 + a16c: 03 01 09 00 lb sp, 0(s2) + a170: 00 01 + a172: 03 02 09 00 lb tp, 0(s2) + a176: 00 01 + a178: 03 00 09 00 lb zero, 0(s2) + a17c: 00 01 + a17e: 05 01 + a180: 06 03 + a182: 7a 09 + a184: 00 00 + a186: 01 03 + a188: 00 09 + a18a: 18 00 + a18c: 01 05 + a18e: 03 03 06 09 lb t1, 144(a2) + a192: 08 00 + a194: 01 06 + a196: 03 00 09 04 lb zero, 64(s2) + a19a: 00 01 + a19c: 03 01 09 00 lb sp, 0(s2) + a1a0: 00 01 + a1a2: 03 00 09 00 lb zero, 0(s2) + a1a6: 00 01 + a1a8: 03 00 09 00 lb zero, 0(s2) + a1ac: 00 01 + a1ae: 03 00 09 00 lb zero, 0(s2) + a1b2: 00 01 + a1b4: 03 00 09 00 lb zero, 0(s2) + a1b8: 00 01 + a1ba: 03 00 09 10 lb zero, 256(s2) + a1be: 00 01 + a1c0: 03 00 09 00 lb zero, 0(s2) + a1c4: 00 01 + a1c6: 06 03 + a1c8: 02 09 + a1ca: 00 00 + a1cc: 01 03 + a1ce: 7e 09 + a1d0: 18 00 + a1d2: 01 06 + a1d4: 03 00 09 04 lb zero, 64(s2) + a1d8: 00 01 + a1da: 03 02 09 00 lb tp, 0(s2) + a1de: 00 01 + a1e0: 03 00 09 00 lb zero, 0(s2) + a1e4: 00 01 + a1e6: 03 00 09 00 lb zero, 0(s2) + a1ea: 00 01 + a1ec: 03 00 09 00 lb zero, 0(s2) + a1f0: 00 01 + a1f2: 03 00 09 00 lb zero, 0(s2) + a1f6: 00 01 + a1f8: 03 00 09 00 lb zero, 0(s2) + a1fc: 00 01 + a1fe: 03 00 09 00 lb zero, 0(s2) + a202: 00 01 + a204: 03 00 09 00 lb zero, 0(s2) + a208: 00 01 + a20a: 03 00 09 00 lb zero, 0(s2) + a20e: 00 01 + a210: 03 00 09 00 lb zero, 0(s2) + a214: 00 01 + a216: 03 00 09 00 lb zero, 0(s2) + a21a: 00 01 + a21c: 00 02 + a21e: 04 01 + a220: 03 00 09 04 lb zero, 64(s2) + a224: 00 01 + a226: 00 02 + a228: 04 01 + a22a: 03 00 09 20 lb zero, 512(s2) + a22e: 00 01 + a230: 00 02 + a232: 04 01 + a234: 03 00 09 00 lb zero, 0(s2) + a238: 00 01 + a23a: 00 02 + a23c: 04 01 + a23e: 03 00 09 00 lb zero, 0(s2) + a242: 00 01 + a244: 00 02 + a246: 04 01 + a248: 03 00 09 00 lb zero, 0(s2) + a24c: 00 01 + a24e: 00 02 + a250: 04 01 + a252: 03 00 09 00 lb zero, 0(s2) + a256: 00 01 + a258: 00 02 + a25a: 04 01 + a25c: 03 00 09 00 lb zero, 0(s2) + a260: 00 01 + a262: 00 02 + a264: 04 01 + a266: 03 00 09 00 lb zero, 0(s2) + a26a: 00 01 + a26c: 00 02 + a26e: 04 01 + a270: 03 00 09 00 lb zero, 0(s2) + a274: 00 01 + a276: 00 02 + a278: 04 01 + a27a: 03 00 09 00 lb zero, 0(s2) + a27e: 00 01 + a280: 00 02 + a282: 04 01 + a284: 03 00 09 00 lb zero, 0(s2) + a288: 00 01 + a28a: 00 02 + a28c: 04 01 + a28e: 03 00 09 04 lb zero, 64(s2) + a292: 00 01 + a294: 00 02 + a296: 04 01 + a298: 03 00 09 00 lb zero, 0(s2) + a29c: 00 01 + a29e: 00 02 + a2a0: 04 01 + a2a2: 03 00 09 00 lb zero, 0(s2) + a2a6: 00 01 + a2a8: 00 02 + a2aa: 04 01 + a2ac: 03 00 09 04 lb zero, 64(s2) + a2b0: 00 01 + a2b2: 00 02 + a2b4: 04 01 + a2b6: 03 00 09 00 lb zero, 0(s2) + a2ba: 00 01 + a2bc: 00 02 + a2be: 04 01 + a2c0: 03 00 09 00 lb zero, 0(s2) + a2c4: 00 01 + a2c6: 00 02 + a2c8: 04 01 + a2ca: 03 00 09 04 lb zero, 64(s2) + a2ce: 00 01 + a2d0: 00 02 + a2d2: 04 01 + a2d4: 03 00 09 00 lb zero, 0(s2) + a2d8: 00 01 + a2da: 00 02 + a2dc: 04 01 + a2de: 03 00 09 04 lb zero, 64(s2) + a2e2: 00 01 + a2e4: 00 02 + a2e6: 04 01 + a2e8: 03 00 09 00 lb zero, 0(s2) + a2ec: 00 01 + a2ee: 00 02 + a2f0: 04 01 + a2f2: 06 03 + a2f4: 78 09 + a2f6: 00 00 + a2f8: 01 00 + a2fa: 02 04 + a2fc: 5c 06 + a2fe: 03 08 09 04 lb a6, 64(s2) + a302: 00 01 + a304: 00 02 + a306: 04 5c + a308: 03 00 09 00 lb zero, 0(s2) + a30c: 00 01 + a30e: 00 02 + a310: 04 5c + a312: 03 04 09 00 lb s0, 0(s2) + a316: 00 01 + a318: 00 02 + a31a: 04 5c + a31c: 03 00 09 00 lb zero, 0(s2) + a320: 00 01 + a322: 00 02 + a324: 04 5c + a326: 03 00 09 00 lb zero, 0(s2) + a32a: 00 01 + a32c: 00 02 + a32e: 04 5c + a330: 03 00 09 18 lb zero, 384(s2) + a334: 00 01 + a336: 00 02 + a338: 04 5c + a33a: 03 00 09 04 lb zero, 64(s2) + a33e: 00 01 + a340: 00 02 + a342: 04 5c + a344: 03 00 09 04 lb zero, 64(s2) + a348: 00 01 + a34a: 00 02 + a34c: 04 5c + a34e: 03 00 09 00 lb zero, 0(s2) + a352: 00 01 + a354: 00 02 + a356: 04 5c + a358: 03 00 09 00 lb zero, 0(s2) + a35c: 00 01 + a35e: 00 02 + a360: 04 5c + a362: 03 00 09 00 lb zero, 0(s2) + a366: 00 01 + a368: 00 02 + a36a: 04 5c + a36c: 03 00 09 04 lb zero, 64(s2) + a370: 00 01 + a372: 00 02 + a374: 04 5c + a376: 03 01 09 00 lb sp, 0(s2) + a37a: 00 01 + a37c: 00 02 + a37e: 04 5c + a380: 03 00 09 00 lb zero, 0(s2) + a384: 00 01 + a386: 00 02 + a388: 04 01 + a38a: 03 00 09 04 lb zero, 64(s2) + a38e: 00 01 + a390: 00 02 + a392: 04 03 + a394: 03 00 09 04 lb zero, 64(s2) + a398: 00 01 + a39a: 00 02 + a39c: 04 03 + a39e: 03 02 09 00 lb tp, 0(s2) + a3a2: 00 01 + a3a4: 05 01 + a3a6: 00 02 + a3a8: 04 03 + a3aa: 06 03 + a3ac: 01 09 + a3ae: 00 00 + a3b0: 01 05 + a3b2: 0a 00 + a3b4: 02 04 + a3b6: 03 03 7f 09 lb t1, 151(t5) + a3ba: 08 00 + a3bc: 01 05 + a3be: 01 00 + a3c0: 02 04 + a3c2: 03 03 01 09 lb t1, 144(sp) + a3c6: 10 00 + a3c8: 01 05 + a3ca: 03 00 02 04 lb zero, 64(tp) + a3ce: 02 06 + a3d0: 03 78 09 18 + a3d4: 00 01 + a3d6: 00 02 + a3d8: 04 14 + a3da: 03 00 09 08 lb zero, 128(s2) + a3de: 00 01 + a3e0: 00 02 + a3e2: 04 14 + a3e4: 03 00 09 00 lb zero, 0(s2) + a3e8: 00 01 + a3ea: 00 02 + a3ec: 04 14 + a3ee: 03 00 09 00 lb zero, 0(s2) + a3f2: 00 01 + a3f4: 00 02 + a3f6: 04 14 + a3f8: 03 00 09 00 lb zero, 0(s2) + a3fc: 00 01 + a3fe: 00 02 + a400: 04 18 + a402: 03 00 09 08 lb zero, 128(s2) + a406: 00 01 + a408: 00 02 + a40a: 04 18 + a40c: 03 00 09 00 lb zero, 0(s2) + a410: 00 01 + a412: 00 02 + a414: 04 18 + a416: 03 00 09 00 lb zero, 0(s2) + a41a: 00 01 + a41c: 00 02 + a41e: 04 18 + a420: 03 00 09 00 lb zero, 0(s2) + a424: 00 01 + a426: 00 02 + a428: 04 18 + a42a: 03 00 09 00 lb zero, 0(s2) + a42e: 00 01 + a430: 00 02 + a432: 04 29 + a434: 03 00 09 04 lb zero, 64(s2) + a438: 00 01 + a43a: 00 02 + a43c: 04 29 + a43e: 03 00 09 00 lb zero, 0(s2) + a442: 00 01 + a444: 00 02 + a446: 04 29 + a448: 03 00 09 00 lb zero, 0(s2) + a44c: 00 01 + a44e: 00 02 + a450: 04 29 + a452: 03 00 09 00 lb zero, 0(s2) + a456: 00 01 + a458: 00 02 + a45a: 04 29 + a45c: 03 00 09 08 lb zero, 128(s2) + a460: 00 01 + a462: 00 02 + a464: 04 37 + a466: 03 00 09 00 lb zero, 0(s2) + a46a: 00 01 + a46c: 00 02 + a46e: 04 37 + a470: 03 00 09 00 lb zero, 0(s2) + a474: 00 01 + a476: 00 02 + a478: 04 37 + a47a: 03 00 09 00 lb zero, 0(s2) + a47e: 00 01 + a480: 00 02 + a482: 04 37 + a484: 03 00 09 00 lb zero, 0(s2) + a488: 00 01 + a48a: 00 02 + a48c: 04 37 + a48e: 03 00 09 00 lb zero, 0(s2) + a492: 00 01 + a494: 00 02 + a496: 04 37 + a498: 03 00 09 08 lb zero, 128(s2) + a49c: 00 01 + a49e: 00 02 + a4a0: 04 37 + a4a2: 03 00 09 00 lb zero, 0(s2) + a4a6: 00 01 + a4a8: 00 02 + a4aa: 04 37 + a4ac: 03 00 09 00 lb zero, 0(s2) + a4b0: 00 01 + a4b2: 06 03 + a4b4: 00 09 + a4b6: 14 00 + a4b8: 01 00 + a4ba: 02 04 + a4bc: 3d 06 + a4be: 03 00 09 14 lb zero, 320(s2) + a4c2: 00 01 + a4c4: 00 02 + a4c6: 04 40 + a4c8: 06 03 + a4ca: 00 09 + a4cc: 04 00 + a4ce: 01 00 + a4d0: 02 04 + a4d2: 40 06 + a4d4: 03 00 09 10 lb zero, 256(s2) + a4d8: 00 01 + a4da: 00 02 + a4dc: 04 30 + a4de: 03 00 09 08 lb zero, 128(s2) + a4e2: 00 01 + a4e4: 00 02 + a4e6: 04 30 + a4e8: 03 00 09 00 lb zero, 0(s2) + a4ec: 00 01 + a4ee: 00 02 + a4f0: 04 30 + a4f2: 03 00 09 00 lb zero, 0(s2) + a4f6: 00 01 + a4f8: 00 02 + a4fa: 04 30 + a4fc: 03 00 09 00 lb zero, 0(s2) + a500: 00 01 + a502: 00 02 + a504: 04 30 + a506: 03 00 09 04 lb zero, 64(s2) + a50a: 00 01 + a50c: 00 02 + a50e: 04 30 + a510: 03 00 09 00 lb zero, 0(s2) + a514: 00 01 + a516: 06 03 + a518: 00 09 + a51a: 14 00 + a51c: 01 00 + a51e: 02 04 + a520: 3c 06 + a522: 03 00 09 04 lb zero, 64(s2) + a526: 00 01 + a528: 00 02 + a52a: 04 3c + a52c: 03 00 09 14 lb zero, 320(s2) + a530: 00 01 + a532: 00 02 + a534: 04 3c + a536: 03 00 09 00 lb zero, 0(s2) + a53a: 00 01 + a53c: 00 02 + a53e: 04 43 + a540: 06 03 + a542: 00 09 + a544: 08 00 + a546: 01 00 + a548: 02 04 + a54a: 43 06 03 00 fmadd.s fa2, ft6, ft0, ft0, rne + a54e: 09 04 + a550: 00 01 + a552: 00 02 + a554: 04 43 + a556: 03 00 09 10 lb zero, 256(s2) + a55a: 00 01 + a55c: 00 02 + a55e: 04 43 + a560: 03 00 09 04 lb zero, 64(s2) + a564: 00 01 + a566: 00 02 + a568: 04 44 + a56a: 03 00 09 04 lb zero, 64(s2) + a56e: 00 01 + a570: 00 02 + a572: 04 44 + a574: 03 00 09 00 lb zero, 0(s2) + a578: 00 01 + a57a: 00 02 + a57c: 04 3f + a57e: 03 00 09 10 lb zero, 256(s2) + a582: 00 01 + a584: 00 02 + a586: 04 3f + a588: 03 00 09 1c lb zero, 448(s2) + a58c: 00 01 + a58e: 00 02 + a590: 04 11 + a592: 03 00 09 08 lb zero, 128(s2) + a596: 00 01 + a598: 00 02 + a59a: 04 11 + a59c: 03 00 09 00 lb zero, 0(s2) + a5a0: 00 01 + a5a2: 00 02 + a5a4: 04 45 + a5a6: 03 00 09 04 lb zero, 64(s2) + a5aa: 00 01 + a5ac: 06 03 + a5ae: 00 09 + a5b0: 08 00 + a5b2: 01 00 + a5b4: 02 04 + a5b6: 49 06 + a5b8: 03 00 09 04 lb zero, 64(s2) + a5bc: 00 01 + a5be: 00 02 + a5c0: 04 49 + a5c2: 03 00 09 00 lb zero, 0(s2) + a5c6: 00 01 + a5c8: 00 02 + a5ca: 04 49 + a5cc: 03 00 09 00 lb zero, 0(s2) + a5d0: 00 01 + a5d2: 00 02 + a5d4: 04 49 + a5d6: 03 00 09 00 lb zero, 0(s2) + a5da: 00 01 + a5dc: 00 02 + a5de: 04 49 + a5e0: 03 00 09 00 lb zero, 0(s2) + a5e4: 00 01 + a5e6: 00 02 + a5e8: 04 49 + a5ea: 03 00 09 00 lb zero, 0(s2) + a5ee: 00 01 + a5f0: 00 02 + a5f2: 04 49 + a5f4: 03 00 09 00 lb zero, 0(s2) + a5f8: 00 01 + a5fa: 00 02 + a5fc: 04 49 + a5fe: 03 00 09 00 lb zero, 0(s2) + a602: 00 01 + a604: 00 02 + a606: 04 49 + a608: 03 00 09 00 lb zero, 0(s2) + a60c: 00 01 + a60e: 00 02 + a610: 04 49 + a612: 03 00 09 00 lb zero, 0(s2) + a616: 00 01 + a618: 00 02 + a61a: 04 49 + a61c: 03 00 09 00 lb zero, 0(s2) + a620: 00 01 + a622: 00 02 + a624: 04 49 + a626: 03 00 09 00 lb zero, 0(s2) + a62a: 00 01 + a62c: 00 02 + a62e: 04 49 + a630: 03 00 09 00 lb zero, 0(s2) + a634: 00 01 + a636: 00 02 + a638: 04 49 + a63a: 03 00 09 10 lb zero, 256(s2) + a63e: 00 01 + a640: 00 02 + a642: 04 49 + a644: 03 00 09 00 lb zero, 0(s2) + a648: 00 01 + a64a: 00 02 + a64c: 04 49 + a64e: 03 00 09 00 lb zero, 0(s2) + a652: 00 01 + a654: 00 02 + a656: 04 49 + a658: 03 00 09 14 lb zero, 320(s2) + a65c: 00 01 + a65e: 00 02 + a660: 04 49 + a662: 03 00 09 00 lb zero, 0(s2) + a666: 00 01 + a668: 00 02 + a66a: 04 49 + a66c: 03 00 09 04 lb zero, 64(s2) + a670: 00 01 + a672: 00 02 + a674: 04 49 + a676: 03 00 09 00 lb zero, 0(s2) + a67a: 00 01 + a67c: 00 02 + a67e: 04 49 + a680: 03 00 09 00 lb zero, 0(s2) + a684: 00 01 + a686: 00 02 + a688: 04 49 + a68a: 03 00 09 00 lb zero, 0(s2) + a68e: 00 01 + a690: 00 02 + a692: 04 49 + a694: 03 00 09 00 lb zero, 0(s2) + a698: 00 01 + a69a: 00 02 + a69c: 04 49 + a69e: 03 00 09 00 lb zero, 0(s2) + a6a2: 00 01 + a6a4: 00 02 + a6a6: 04 49 + a6a8: 03 00 09 00 lb zero, 0(s2) + a6ac: 00 01 + a6ae: 06 03 + a6b0: 00 09 + a6b2: 08 00 + a6b4: 01 03 + a6b6: 78 09 + a6b8: 08 00 + a6ba: 01 03 + a6bc: 08 09 + a6be: 04 00 + a6c0: 01 09 + a6c2: 08 00 + a6c4: 00 01 + a6c6: 01 b5 + a6c8: 0a 00 + a6ca: 00 03 + a6cc: 00 a1 + a6ce: 00 00 + a6d0: 00 01 + a6d2: 01 fb + a6d4: 0e 0d + a6d6: 00 01 + a6d8: 01 01 + a6da: 01 00 + a6dc: 00 00 + a6de: 01 00 + a6e0: 00 01 + a6e2: 2e 2e + a6e4: 2f 2e 2e 2f + a6e8: 2e 2e + a6ea: 2f 2e 2e 2f + a6ee: 72 69 + a6f0: 73 63 76 2d csrrsi t1, 727, 12 + a6f4: 67 63 63 2f + a6f8: 6c 69 + a6fa: 62 67 + a6fc: 63 63 2f 73 bltu t5, s2, 1830 + a700: 6f 66 74 2d jal a2, 289494 + a704: 66 70 + a706: 00 2e + a708: 2e 2f + a70a: 2e 2e + a70c: 2f 2e 2e 2f + a710: 2e 2e + a712: 2f 72 69 73 + a716: 63 76 2d 67 bgeu s10, s2, 1644 + a71a: 63 63 2f 6c bltu t5, sp, 1734 + a71e: 69 62 + a720: 67 63 63 2f + a724: 2e 2e + a726: 2f 69 6e 63 + a72a: 6c 75 + a72c: 64 65 + a72e: 00 00 + a730: 74 72 + a732: 75 6e + a734: 63 74 66 64 bgeu a2, t1, 1608 + a738: 66 32 + a73a: 2e 63 + a73c: 00 01 + a73e: 00 00 + a740: 73 6f 66 74 csrrsi t5, 1862, 12 + a744: 2d 66 + a746: 70 2e + a748: 68 00 + a74a: 01 00 + a74c: 00 64 + a74e: 6f 75 62 6c jal a0, 161478 + a752: 65 2e + a754: 68 00 + a756: 01 00 + a758: 00 71 + a75a: 75 61 + a75c: 64 2e + a75e: 68 00 + a760: 01 00 + a762: 00 6c + a764: 6f 6e 67 6c jal t3, 485062 + a768: 6f 6e 67 2e jal t3, 484070 + a76c: 68 00 + a76e: 02 00 + a770: 00 00 + a772: 05 01 + a774: 00 05 + a776: 02 ec + a778: 4f 01 80 03 + a77c: 24 01 + a77e: 05 03 + a780: 03 01 09 00 lb sp, 0(s2) + a784: 00 01 + a786: 03 00 09 00 lb zero, 0(s2) + a78a: 00 01 + a78c: 05 0d + a78e: 03 00 09 00 lb zero, 0(s2) + a792: 00 01 + a794: 05 03 + a796: 03 01 09 00 lb sp, 0(s2) + a79a: 00 01 + a79c: 03 00 09 00 lb zero, 0(s2) + a7a0: 00 01 + a7a2: 03 00 09 00 lb zero, 0(s2) + a7a6: 00 01 + a7a8: 03 00 09 00 lb zero, 0(s2) + a7ac: 00 01 + a7ae: 03 01 09 00 lb sp, 0(s2) + a7b2: 00 01 + a7b4: 03 00 09 00 lb zero, 0(s2) + a7b8: 00 01 + a7ba: 03 00 09 00 lb zero, 0(s2) + a7be: 00 01 + a7c0: 03 00 09 00 lb zero, 0(s2) + a7c4: 00 01 + a7c6: 03 01 09 00 lb sp, 0(s2) + a7ca: 00 01 + a7cc: 03 02 09 00 lb tp, 0(s2) + a7d0: 00 01 + a7d2: 03 00 09 00 lb zero, 0(s2) + a7d6: 00 01 + a7d8: 05 01 + a7da: 06 03 + a7dc: 7a 09 + a7de: 00 00 + a7e0: 01 03 + a7e2: 00 09 + a7e4: 04 00 + a7e6: 01 05 + a7e8: 03 03 06 09 lb t1, 144(a2) + a7ec: 10 00 + a7ee: 01 06 + a7f0: 03 00 09 04 lb zero, 64(s2) + a7f4: 00 01 + a7f6: 03 01 09 00 lb sp, 0(s2) + a7fa: 00 01 + a7fc: 03 00 09 00 lb zero, 0(s2) + a800: 00 01 + a802: 03 00 09 00 lb zero, 0(s2) + a806: 00 01 + a808: 03 00 09 00 lb zero, 0(s2) + a80c: 00 01 + a80e: 03 00 09 14 lb zero, 320(s2) + a812: 00 01 + a814: 03 00 09 10 lb zero, 256(s2) + a818: 00 01 + a81a: 03 00 09 08 lb zero, 128(s2) + a81e: 00 01 + a820: 03 00 09 00 lb zero, 0(s2) + a824: 00 01 + a826: 03 00 09 04 lb zero, 64(s2) + a82a: 00 01 + a82c: 03 00 09 04 lb zero, 64(s2) + a830: 00 01 + a832: 03 00 09 04 lb zero, 64(s2) + a836: 00 01 + a838: 03 00 09 00 lb zero, 0(s2) + a83c: 00 01 + a83e: 03 00 09 00 lb zero, 0(s2) + a842: 00 01 + a844: 03 00 09 00 lb zero, 0(s2) + a848: 00 01 + a84a: 03 00 09 00 lb zero, 0(s2) + a84e: 00 01 + a850: 03 00 09 00 lb zero, 0(s2) + a854: 00 01 + a856: 03 00 09 00 lb zero, 0(s2) + a85a: 00 01 + a85c: 03 00 09 00 lb zero, 0(s2) + a860: 00 01 + a862: 03 00 09 00 lb zero, 0(s2) + a866: 00 01 + a868: 03 00 09 00 lb zero, 0(s2) + a86c: 00 01 + a86e: 00 02 + a870: 04 08 + a872: 03 00 09 08 lb zero, 128(s2) + a876: 00 01 + a878: 00 02 + a87a: 04 08 + a87c: 03 00 09 1c lb zero, 448(s2) + a880: 00 01 + a882: 00 02 + a884: 04 08 + a886: 03 00 09 00 lb zero, 0(s2) + a88a: 00 01 + a88c: 00 02 + a88e: 04 09 + a890: 03 00 09 04 lb zero, 64(s2) + a894: 00 01 + a896: 00 02 + a898: 04 09 + a89a: 06 03 + a89c: 02 09 + a89e: 04 00 + a8a0: 01 00 + a8a2: 02 04 + a8a4: 09 03 + a8a6: 7e 09 + a8a8: 08 00 + a8aa: 01 00 + a8ac: 02 04 + a8ae: 09 03 + a8b0: 02 09 + a8b2: 04 00 + a8b4: 01 00 + a8b6: 02 04 + a8b8: 09 03 + a8ba: 7e 09 + a8bc: 04 00 + a8be: 01 00 + a8c0: 02 04 + a8c2: 09 06 + a8c4: 03 00 09 04 lb zero, 64(s2) + a8c8: 00 01 + a8ca: 00 02 + a8cc: 04 09 + a8ce: 03 00 09 00 lb zero, 0(s2) + a8d2: 00 01 + a8d4: 00 02 + a8d6: 04 09 + a8d8: 03 00 09 00 lb zero, 0(s2) + a8dc: 00 01 + a8de: 00 02 + a8e0: 04 09 + a8e2: 03 02 09 00 lb tp, 0(s2) + a8e6: 00 01 + a8e8: 00 02 + a8ea: 04 09 + a8ec: 03 00 09 00 lb zero, 0(s2) + a8f0: 00 01 + a8f2: 00 02 + a8f4: 04 09 + a8f6: 03 00 09 00 lb zero, 0(s2) + a8fa: 00 01 + a8fc: 00 02 + a8fe: 04 09 + a900: 03 00 09 00 lb zero, 0(s2) + a904: 00 01 + a906: 00 02 + a908: 04 09 + a90a: 03 00 09 00 lb zero, 0(s2) + a90e: 00 01 + a910: 00 02 + a912: 04 01 + a914: 03 00 09 08 lb zero, 128(s2) + a918: 00 01 + a91a: 00 02 + a91c: 04 01 + a91e: 03 00 09 0c lb zero, 192(s2) + a922: 00 01 + a924: 00 02 + a926: 04 03 + a928: 03 00 09 08 lb zero, 128(s2) + a92c: 00 01 + a92e: 00 02 + a930: 04 03 + a932: 03 00 09 00 lb zero, 0(s2) + a936: 00 01 + a938: 00 02 + a93a: 04 06 + a93c: 06 03 + a93e: 00 09 + a940: 04 00 + a942: 01 00 + a944: 02 04 + a946: 07 03 00 09 + a94a: 08 00 + a94c: 01 03 + a94e: 00 09 + a950: 04 00 + a952: 01 03 + a954: 04 09 + a956: 0c 00 + a958: 01 03 + a95a: 7c 09 + a95c: 04 00 + a95e: 01 00 + a960: 02 04 + a962: 25 06 + a964: 03 04 09 04 lb s0, 64(s2) + a968: 00 01 + a96a: 00 02 + a96c: 04 25 + a96e: 03 00 09 08 lb zero, 128(s2) + a972: 00 01 + a974: 06 03 + a976: 00 09 + a978: 04 00 + a97a: 01 00 + a97c: 02 04 + a97e: 28 06 + a980: 03 00 09 0c lb zero, 192(s2) + a984: 00 01 + a986: 00 02 + a988: 04 28 + a98a: 03 00 09 00 lb zero, 0(s2) + a98e: 00 01 + a990: 00 02 + a992: 04 2c + a994: 03 00 09 0c lb zero, 192(s2) + a998: 00 01 + a99a: 00 02 + a99c: 04 2c + a99e: 03 00 09 00 lb zero, 0(s2) + a9a2: 00 01 + a9a4: 00 02 + a9a6: 04 2c + a9a8: 03 00 09 00 lb zero, 0(s2) + a9ac: 00 01 + a9ae: 00 02 + a9b0: 04 2c + a9b2: 03 00 09 04 lb zero, 64(s2) + a9b6: 00 01 + a9b8: 00 02 + a9ba: 04 37 + a9bc: 03 00 09 00 lb zero, 0(s2) + a9c0: 00 01 + a9c2: 00 02 + a9c4: 04 37 + a9c6: 03 00 09 08 lb zero, 128(s2) + a9ca: 00 01 + a9cc: 00 02 + a9ce: 04 0a + a9d0: 06 03 + a9d2: 7c 09 + a9d4: 08 00 + a9d6: 01 00 + a9d8: 02 04 + a9da: 0b 03 00 09 + a9de: 08 00 + a9e0: 01 03 + a9e2: 00 09 + a9e4: 04 00 + a9e6: 01 00 + a9e8: 02 04 + a9ea: 3e 06 + a9ec: 03 04 09 10 lb s0, 256(s2) + a9f0: 00 01 + a9f2: 00 02 + a9f4: 04 3f + a9f6: 03 00 09 08 lb zero, 128(s2) + a9fa: 00 01 + a9fc: 00 02 + a9fe: 04 3f + aa00: 03 00 09 00 lb zero, 0(s2) + aa04: 00 01 + aa06: 00 02 + aa08: 04 3f + aa0a: 03 00 09 04 lb zero, 64(s2) + aa0e: 00 01 + aa10: 06 03 + aa12: 00 09 + aa14: 08 00 + aa16: 01 00 + aa18: 02 04 + aa1a: 4f 06 03 00 fnmadd.s fa2, ft6, ft0, ft0, rne + aa1e: 09 0c + aa20: 00 01 + aa22: 00 02 + aa24: 04 4f + aa26: 03 00 09 00 lb zero, 0(s2) + aa2a: 00 01 + aa2c: 00 02 + aa2e: 04 4f + aa30: 03 00 09 00 lb zero, 0(s2) + aa34: 00 01 + aa36: 00 02 + aa38: 04 4f + aa3a: 03 00 09 0c lb zero, 192(s2) + aa3e: 00 01 + aa40: 00 02 + aa42: 04 4f + aa44: 03 00 09 08 lb zero, 128(s2) + aa48: 00 01 + aa4a: 00 02 + aa4c: 04 50 + aa4e: 06 03 + aa50: 00 09 + aa52: 04 00 + aa54: 01 03 + aa56: 00 09 + aa58: 0c 00 + aa5a: 01 00 + aa5c: 02 04 + aa5e: 5a 06 + aa60: 03 00 09 0c lb zero, 192(s2) + aa64: 00 01 + aa66: 00 02 + aa68: 04 5a + aa6a: 03 00 09 00 lb zero, 0(s2) + aa6e: 00 01 + aa70: 00 02 + aa72: 04 5a + aa74: 03 00 09 00 lb zero, 0(s2) + aa78: 00 01 + aa7a: 00 02 + aa7c: 04 5a + aa7e: 03 00 09 00 lb zero, 0(s2) + aa82: 00 01 + aa84: 00 02 + aa86: 04 5a + aa88: 03 00 09 00 lb zero, 0(s2) + aa8c: 00 01 + aa8e: 00 02 + aa90: 04 5a + aa92: 03 00 09 00 lb zero, 0(s2) + aa96: 00 01 + aa98: 00 02 + aa9a: 04 5a + aa9c: 03 00 09 00 lb zero, 0(s2) + aaa0: 00 01 + aaa2: 00 02 + aaa4: 04 5a + aaa6: 03 00 09 00 lb zero, 0(s2) + aaaa: 00 01 + aaac: 00 02 + aaae: 04 5a + aab0: 03 00 09 00 lb zero, 0(s2) + aab4: 00 01 + aab6: 00 02 + aab8: 04 5a + aaba: 03 00 09 24 lb zero, 576(s2) + aabe: 00 01 + aac0: 00 02 + aac2: 04 5a + aac4: 03 00 09 00 lb zero, 0(s2) + aac8: 00 01 + aaca: 00 02 + aacc: 04 5a + aace: 03 01 09 00 lb sp, 0(s2) + aad2: 00 01 + aad4: 00 02 + aad6: 04 5a + aad8: 03 00 09 00 lb zero, 0(s2) + aadc: 00 01 + aade: 00 02 + aae0: 04 5a + aae2: 06 03 + aae4: 7f 09 00 00 + aae8: 01 00 + aaea: 02 04 + aaec: 5a 03 + aaee: 01 09 + aaf0: 04 00 + aaf2: 01 00 + aaf4: 02 04 + aaf6: 01 06 + aaf8: 03 00 09 04 lb zero, 64(s2) + aafc: 00 01 + aafe: 00 02 + ab00: 04 01 + ab02: 03 00 09 04 lb zero, 64(s2) + ab06: 00 01 + ab08: 00 02 + ab0a: 04 01 + ab0c: 03 02 09 00 lb tp, 0(s2) + ab10: 00 01 + ab12: 05 01 + ab14: 06 03 + ab16: 01 09 + ab18: 00 00 + ab1a: 01 05 + ab1c: 03 00 02 04 lb zero, 64(tp) + ab20: 04 06 + ab22: 03 78 09 08 + ab26: 00 01 + ab28: 03 00 09 04 lb zero, 64(s2) + ab2c: 00 01 + ab2e: 03 00 09 00 lb zero, 0(s2) + ab32: 00 01 + ab34: 03 00 09 00 lb zero, 0(s2) + ab38: 00 01 + ab3a: 03 00 09 00 lb zero, 0(s2) + ab3e: 00 01 + ab40: 03 00 09 00 lb zero, 0(s2) + ab44: 00 01 + ab46: 03 00 09 00 lb zero, 0(s2) + ab4a: 00 01 + ab4c: 03 00 09 0c lb zero, 192(s2) + ab50: 00 01 + ab52: 03 00 09 00 lb zero, 0(s2) + ab56: 00 01 + ab58: 03 00 09 00 lb zero, 0(s2) + ab5c: 00 01 + ab5e: 03 00 09 00 lb zero, 0(s2) + ab62: 00 01 + ab64: 03 00 09 00 lb zero, 0(s2) + ab68: 00 01 + ab6a: 03 00 09 00 lb zero, 0(s2) + ab6e: 00 01 + ab70: 03 00 09 2c lb zero, 704(s2) + ab74: 00 01 + ab76: 03 00 09 00 lb zero, 0(s2) + ab7a: 00 01 + ab7c: 03 00 09 00 lb zero, 0(s2) + ab80: 00 01 + ab82: 03 00 09 00 lb zero, 0(s2) + ab86: 00 01 + ab88: 03 00 09 00 lb zero, 0(s2) + ab8c: 00 01 + ab8e: 03 00 09 00 lb zero, 0(s2) + ab92: 00 01 + ab94: 03 00 09 00 lb zero, 0(s2) + ab98: 00 01 + ab9a: 00 02 + ab9c: 04 3b + ab9e: 03 00 09 04 lb zero, 64(s2) + aba2: 00 01 + aba4: 00 02 + aba6: 04 3b + aba8: 03 00 09 00 lb zero, 0(s2) + abac: 00 01 + abae: 00 02 + abb0: 04 3b + abb2: 03 00 09 00 lb zero, 0(s2) + abb6: 00 01 + abb8: 00 02 + abba: 04 3b + abbc: 03 00 09 04 lb zero, 64(s2) + abc0: 00 01 + abc2: 00 02 + abc4: 04 3b + abc6: 03 00 09 04 lb zero, 64(s2) + abca: 00 01 + abcc: 00 02 + abce: 04 3b + abd0: 03 00 09 00 lb zero, 0(s2) + abd4: 00 01 + abd6: 00 02 + abd8: 04 3b + abda: 03 04 09 00 lb s0, 0(s2) + abde: 00 01 + abe0: 00 02 + abe2: 04 3b + abe4: 03 00 09 00 lb zero, 0(s2) + abe8: 00 01 + abea: 00 02 + abec: 04 3b + abee: 03 00 09 00 lb zero, 0(s2) + abf2: 00 01 + abf4: 06 03 + abf6: 00 09 + abf8: 04 00 + abfa: 01 03 + abfc: 74 09 + abfe: 04 00 + ac00: 01 00 + ac02: 02 04 + ac04: 24 06 + ac06: 03 0c 09 04 lb s8, 64(s2) + ac0a: 00 01 + ac0c: 00 02 + ac0e: 04 24 + ac10: 03 00 09 00 lb zero, 0(s2) + ac14: 00 01 + ac16: 00 02 + ac18: 04 2f + ac1a: 03 00 09 08 lb zero, 128(s2) + ac1e: 00 01 + ac20: 00 02 + ac22: 04 2f + ac24: 03 00 09 00 lb zero, 0(s2) + ac28: 00 01 + ac2a: 00 02 + ac2c: 04 3a + ac2e: 03 00 09 04 lb zero, 64(s2) + ac32: 00 01 + ac34: 00 02 + ac36: 04 12 + ac38: 03 7c 09 08 + ac3c: 00 01 + ac3e: 00 02 + ac40: 04 14 + ac42: 03 00 09 08 lb zero, 128(s2) + ac46: 00 01 + ac48: 00 02 + ac4a: 04 14 + ac4c: 03 00 09 04 lb zero, 64(s2) + ac50: 00 01 + ac52: 00 02 + ac54: 04 27 + ac56: 06 03 + ac58: 00 09 + ac5a: 04 00 + ac5c: 01 00 + ac5e: 02 04 + ac60: 15 06 + ac62: 03 00 09 0c lb zero, 192(s2) + ac66: 00 01 + ac68: 00 02 + ac6a: 04 15 + ac6c: 03 00 09 1c lb zero, 448(s2) + ac70: 00 01 + ac72: 00 02 + ac74: 04 15 + ac76: 03 00 09 00 lb zero, 0(s2) + ac7a: 00 01 + ac7c: 00 02 + ac7e: 04 15 + ac80: 03 00 09 00 lb zero, 0(s2) + ac84: 00 01 + ac86: 00 02 + ac88: 04 15 + ac8a: 03 00 09 00 lb zero, 0(s2) + ac8e: 00 01 + ac90: 00 02 + ac92: 04 15 + ac94: 03 00 09 00 lb zero, 0(s2) + ac98: 00 01 + ac9a: 00 02 + ac9c: 04 15 + ac9e: 03 00 09 00 lb zero, 0(s2) + aca2: 00 01 + aca4: 00 02 + aca6: 04 15 + aca8: 03 00 09 00 lb zero, 0(s2) + acac: 00 01 + acae: 00 02 + acb0: 04 15 + acb2: 03 00 09 04 lb zero, 64(s2) + acb6: 00 01 + acb8: 00 02 + acba: 04 15 + acbc: 03 00 09 00 lb zero, 0(s2) + acc0: 00 01 + acc2: 00 02 + acc4: 04 15 + acc6: 03 00 09 00 lb zero, 0(s2) + acca: 00 01 + accc: 00 02 + acce: 04 15 + acd0: 03 00 09 00 lb zero, 0(s2) + acd4: 00 01 + acd6: 00 02 + acd8: 04 19 + acda: 03 00 09 08 lb zero, 128(s2) + acde: 00 01 + ace0: 00 02 + ace2: 04 19 + ace4: 03 00 09 10 lb zero, 256(s2) + ace8: 00 01 + acea: 00 02 + acec: 04 19 + acee: 03 00 09 00 lb zero, 0(s2) + acf2: 00 01 + acf4: 00 02 + acf6: 04 1a + acf8: 03 00 09 04 lb zero, 64(s2) + acfc: 00 01 + acfe: 06 03 + ad00: 00 09 + ad02: 0c 00 + ad04: 01 00 + ad06: 02 04 + ad08: 1f 06 03 00 + ad0c: 09 0c + ad0e: 00 01 + ad10: 00 02 + ad12: 04 1f + ad14: 03 00 09 14 lb zero, 320(s2) + ad18: 00 01 + ad1a: 00 02 + ad1c: 04 1f + ad1e: 03 00 09 00 lb zero, 0(s2) + ad22: 00 01 + ad24: 00 02 + ad26: 04 1c + ad28: 06 03 + ad2a: 00 09 + ad2c: 1c 00 + ad2e: 01 00 + ad30: 02 04 + ad32: 1c 06 + ad34: 03 00 09 14 lb zero, 320(s2) + ad38: 00 01 + ad3a: 00 02 + ad3c: 04 1c + ad3e: 03 00 09 0c lb zero, 192(s2) + ad42: 00 01 + ad44: 00 02 + ad46: 04 20 + ad48: 03 00 09 0c lb zero, 192(s2) + ad4c: 00 01 + ad4e: 00 02 + ad50: 04 23 + ad52: 06 03 + ad54: 00 09 + ad56: 08 00 + ad58: 01 00 + ad5a: 02 04 + ad5c: 23 06 03 00 sb zero, 12(t1) + ad60: 09 18 + ad62: 00 01 + ad64: 00 02 + ad66: 04 25 + ad68: 03 00 09 04 lb zero, 64(s2) + ad6c: 00 01 + ad6e: 00 02 + ad70: 04 26 + ad72: 03 00 09 04 lb zero, 64(s2) + ad76: 00 01 + ad78: 00 02 + ad7a: 04 26 + ad7c: 03 00 09 0c lb zero, 192(s2) + ad80: 00 01 + ad82: 00 02 + ad84: 04 26 + ad86: 03 00 09 04 lb zero, 64(s2) + ad8a: 00 01 + ad8c: 00 02 + ad8e: 04 27 + ad90: 03 00 09 04 lb zero, 64(s2) + ad94: 00 01 + ad96: 00 02 + ad98: 04 27 + ad9a: 03 00 09 00 lb zero, 0(s2) + ad9e: 00 01 + ada0: 00 02 + ada2: 04 27 + ada4: 03 00 09 00 lb zero, 0(s2) + ada8: 00 01 + adaa: 00 02 + adac: 04 22 + adae: 03 00 09 10 lb zero, 256(s2) + adb2: 00 01 + adb4: 00 02 + adb6: 04 22 + adb8: 03 00 09 20 lb zero, 512(s2) + adbc: 00 01 + adbe: 00 02 + adc0: 04 02 + adc2: 03 00 09 08 lb zero, 128(s2) + adc6: 00 01 + adc8: 00 02 + adca: 04 41 + adcc: 03 00 09 1c lb zero, 448(s2) + add0: 00 01 + add2: 00 02 + add4: 04 41 + add6: 03 00 09 00 lb zero, 0(s2) + adda: 00 01 + addc: 00 02 + adde: 04 41 + ade0: 03 00 09 00 lb zero, 0(s2) + ade4: 00 01 + ade6: 00 02 + ade8: 04 41 + adea: 03 00 09 00 lb zero, 0(s2) + adee: 00 01 + adf0: 00 02 + adf2: 04 41 + adf4: 03 00 09 00 lb zero, 0(s2) + adf8: 00 01 + adfa: 00 02 + adfc: 04 01 + adfe: 06 03 + ae00: 04 09 + ae02: 08 00 + ae04: 01 06 + ae06: 03 00 09 08 lb zero, 128(s2) + ae0a: 00 01 + ae0c: 03 00 09 00 lb zero, 0(s2) + ae10: 00 01 + ae12: 03 00 09 00 lb zero, 0(s2) + ae16: 00 01 + ae18: 03 00 09 00 lb zero, 0(s2) + ae1c: 00 01 + ae1e: 03 00 09 00 lb zero, 0(s2) + ae22: 00 01 + ae24: 03 00 09 00 lb zero, 0(s2) + ae28: 00 01 + ae2a: 03 00 09 00 lb zero, 0(s2) + ae2e: 00 01 + ae30: 03 00 09 00 lb zero, 0(s2) + ae34: 00 01 + ae36: 03 00 09 00 lb zero, 0(s2) + ae3a: 00 01 + ae3c: 03 00 09 00 lb zero, 0(s2) + ae40: 00 01 + ae42: 03 00 09 00 lb zero, 0(s2) + ae46: 00 01 + ae48: 03 00 09 0c lb zero, 192(s2) + ae4c: 00 01 + ae4e: 03 00 09 04 lb zero, 64(s2) + ae52: 00 01 + ae54: 03 00 09 00 lb zero, 0(s2) + ae58: 00 01 + ae5a: 03 00 09 00 lb zero, 0(s2) + ae5e: 00 01 + ae60: 03 00 09 0c lb zero, 192(s2) + ae64: 00 01 + ae66: 03 00 09 00 lb zero, 0(s2) + ae6a: 00 01 + ae6c: 00 02 + ae6e: 04 10 + ae70: 03 00 09 18 lb zero, 384(s2) + ae74: 00 01 + ae76: 00 02 + ae78: 04 10 + ae7a: 03 00 09 00 lb zero, 0(s2) + ae7e: 00 01 + ae80: 00 02 + ae82: 04 14 + ae84: 03 00 09 0c lb zero, 192(s2) + ae88: 00 01 + ae8a: 00 02 + ae8c: 04 14 + ae8e: 03 00 09 00 lb zero, 0(s2) + ae92: 00 01 + ae94: 00 02 + ae96: 04 14 + ae98: 03 00 09 00 lb zero, 0(s2) + ae9c: 00 01 + ae9e: 00 02 + aea0: 04 14 + aea2: 03 00 09 00 lb zero, 0(s2) + aea6: 00 01 + aea8: 00 02 + aeaa: 04 14 + aeac: 03 00 09 0c lb zero, 192(s2) + aeb0: 00 01 + aeb2: 00 02 + aeb4: 04 17 + aeb6: 03 00 09 00 lb zero, 0(s2) + aeba: 00 01 + aebc: 00 02 + aebe: 04 17 + aec0: 03 00 09 00 lb zero, 0(s2) + aec4: 00 01 + aec6: 00 02 + aec8: 04 3e + aeca: 03 7c 09 14 + aece: 00 01 + aed0: 00 02 + aed2: 04 3e + aed4: 03 00 09 00 lb zero, 0(s2) + aed8: 00 01 + aeda: 00 02 + aedc: 04 58 + aede: 03 00 09 04 lb zero, 64(s2) + aee2: 00 01 + aee4: 00 02 + aee6: 04 58 + aee8: 03 00 09 00 lb zero, 0(s2) + aeec: 00 01 + aeee: 00 02 + aef0: 04 58 + aef2: 06 03 + aef4: 78 09 + aef6: 04 00 + aef8: 01 00 + aefa: 02 04 + aefc: 58 03 + aefe: 08 09 + af00: 04 00 + af02: 01 00 + af04: 02 04 + af06: 5c 03 + af08: 00 09 + af0a: 04 00 + af0c: 01 00 + af0e: 02 04 + af10: 5c 03 + af12: 78 09 + af14: 08 00 + af16: 01 00 + af18: 02 04 + af1a: 60 06 + af1c: 03 08 09 08 lb a6, 128(s2) + af20: 00 01 + af22: 00 02 + af24: 04 60 + af26: 03 00 09 00 lb zero, 0(s2) + af2a: 00 01 + af2c: 00 02 + af2e: 04 60 + af30: 03 00 09 00 lb zero, 0(s2) + af34: 00 01 + af36: 00 02 + af38: 04 60 + af3a: 03 00 09 00 lb zero, 0(s2) + af3e: 00 01 + af40: 00 02 + af42: 04 60 + af44: 03 00 09 00 lb zero, 0(s2) + af48: 00 01 + af4a: 00 02 + af4c: 04 60 + af4e: 03 00 09 00 lb zero, 0(s2) + af52: 00 01 + af54: 00 02 + af56: 04 60 + af58: 03 00 09 00 lb zero, 0(s2) + af5c: 00 01 + af5e: 00 02 + af60: 04 60 + af62: 03 00 09 00 lb zero, 0(s2) + af66: 00 01 + af68: 00 02 + af6a: 04 60 + af6c: 03 00 09 00 lb zero, 0(s2) + af70: 00 01 + af72: 00 02 + af74: 04 60 + af76: 03 00 09 00 lb zero, 0(s2) + af7a: 00 01 + af7c: 00 02 + af7e: 04 60 + af80: 03 00 09 00 lb zero, 0(s2) + af84: 00 01 + af86: 00 02 + af88: 04 60 + af8a: 03 00 09 00 lb zero, 0(s2) + af8e: 00 01 + af90: 00 02 + af92: 04 60 + af94: 03 00 09 00 lb zero, 0(s2) + af98: 00 01 + af9a: 00 02 + af9c: 04 60 + af9e: 03 00 09 00 lb zero, 0(s2) + afa2: 00 01 + afa4: 00 02 + afa6: 04 60 + afa8: 03 00 09 00 lb zero, 0(s2) + afac: 00 01 + afae: 00 02 + afb0: 04 60 + afb2: 03 00 09 00 lb zero, 0(s2) + afb6: 00 01 + afb8: 00 02 + afba: 04 60 + afbc: 03 00 09 00 lb zero, 0(s2) + afc0: 00 01 + afc2: 00 02 + afc4: 04 60 + afc6: 03 00 09 00 lb zero, 0(s2) + afca: 00 01 + afcc: 00 02 + afce: 04 60 + afd0: 03 00 09 00 lb zero, 0(s2) + afd4: 00 01 + afd6: 00 02 + afd8: 04 60 + afda: 03 00 09 00 lb zero, 0(s2) + afde: 00 01 + afe0: 00 02 + afe2: 04 60 + afe4: 03 00 09 00 lb zero, 0(s2) + afe8: 00 01 + afea: 00 02 + afec: 04 60 + afee: 03 00 09 00 lb zero, 0(s2) + aff2: 00 01 + aff4: 00 02 + aff6: 04 60 + aff8: 03 00 09 00 lb zero, 0(s2) + affc: 00 01 + affe: 00 02 + b000: 04 60 + b002: 03 00 09 00 lb zero, 0(s2) + b006: 00 01 + b008: 00 02 + b00a: 04 60 + b00c: 03 00 09 20 lb zero, 512(s2) + b010: 00 01 + b012: 00 02 + b014: 04 60 + b016: 03 00 09 00 lb zero, 0(s2) + b01a: 00 01 + b01c: 00 02 + b01e: 04 60 + b020: 03 00 09 00 lb zero, 0(s2) + b024: 00 01 + b026: 00 02 + b028: 04 13 + b02a: 03 04 09 0c lb s0, 192(s2) + b02e: 00 01 + b030: 00 02 + b032: 04 13 + b034: 03 00 09 00 lb zero, 0(s2) + b038: 00 01 + b03a: 00 02 + b03c: 04 1a + b03e: 03 00 09 08 lb zero, 128(s2) + b042: 00 01 + b044: 00 02 + b046: 04 1a + b048: 03 00 09 00 lb zero, 0(s2) + b04c: 00 01 + b04e: 00 02 + b050: 04 1a + b052: 03 00 09 00 lb zero, 0(s2) + b056: 00 01 + b058: 00 02 + b05a: 04 1a + b05c: 03 00 09 00 lb zero, 0(s2) + b060: 00 01 + b062: 00 02 + b064: 04 1a + b066: 03 00 09 0c lb zero, 192(s2) + b06a: 00 01 + b06c: 00 02 + b06e: 04 12 + b070: 03 00 09 08 lb zero, 128(s2) + b074: 00 01 + b076: 00 02 + b078: 04 12 + b07a: 03 00 09 00 lb zero, 0(s2) + b07e: 00 01 + b080: 00 02 + b082: 04 1f + b084: 03 00 09 08 lb zero, 128(s2) + b088: 00 01 + b08a: 00 02 + b08c: 04 1f + b08e: 03 00 09 00 lb zero, 0(s2) + b092: 00 01 + b094: 00 02 + b096: 04 1f + b098: 03 00 09 00 lb zero, 0(s2) + b09c: 00 01 + b09e: 00 02 + b0a0: 04 1f + b0a2: 03 00 09 00 lb zero, 0(s2) + b0a6: 00 01 + b0a8: 00 02 + b0aa: 04 1f + b0ac: 03 00 09 0c lb zero, 192(s2) + b0b0: 00 01 + b0b2: 06 03 + b0b4: 7c 09 + b0b6: 08 00 + b0b8: 01 03 + b0ba: 78 09 + b0bc: 04 00 + b0be: 01 03 + b0c0: 08 09 + b0c2: 04 00 + b0c4: 01 00 + b0c6: 02 04 + b0c8: 2b 06 03 04 + b0cc: 09 1c + b0ce: 00 01 + b0d0: 00 02 + b0d2: 04 2b + b0d4: 03 00 09 00 lb zero, 0(s2) + b0d8: 00 01 + b0da: 00 02 + b0dc: 04 37 + b0de: 03 00 09 04 lb zero, 64(s2) + b0e2: 00 01 + b0e4: 00 02 + b0e6: 04 37 + b0e8: 03 00 09 00 lb zero, 0(s2) + b0ec: 00 01 + b0ee: 00 02 + b0f0: 04 37 + b0f2: 03 00 09 00 lb zero, 0(s2) + b0f6: 00 01 + b0f8: 00 02 + b0fa: 04 2a + b0fc: 03 00 09 08 lb zero, 128(s2) + b100: 00 01 + b102: 00 02 + b104: 04 2a + b106: 03 00 09 00 lb zero, 0(s2) + b10a: 00 01 + b10c: 00 02 + b10e: 04 3a + b110: 06 03 + b112: 00 09 + b114: 04 00 + b116: 01 00 + b118: 02 04 + b11a: 3c 06 + b11c: 03 00 09 04 lb zero, 64(s2) + b120: 00 01 + b122: 00 02 + b124: 04 41 + b126: 03 00 09 08 lb zero, 128(s2) + b12a: 00 01 + b12c: 00 02 + b12e: 04 41 + b130: 03 00 09 00 lb zero, 0(s2) + b134: 00 01 + b136: 00 02 + b138: 04 44 + b13a: 06 03 + b13c: 00 09 + b13e: 08 00 + b140: 01 00 + b142: 02 04 + b144: 45 03 + b146: 00 09 + b148: 08 00 + b14a: 01 03 + b14c: 00 09 + b14e: 04 00 + b150: 01 00 + b152: 02 04 + b154: 48 03 + b156: 00 09 + b158: 0c 00 + b15a: 01 00 + b15c: 02 04 + b15e: 49 03 + b160: 00 09 + b162: 08 00 + b164: 01 00 + b166: 02 04 + b168: 4e 06 + b16a: 03 00 09 04 lb zero, 64(s2) + b16e: 00 01 + b170: 00 02 + b172: 04 4e + b174: 03 00 09 00 lb zero, 0(s2) + b178: 00 01 + b17a: 09 0c + b17c: 00 00 + b17e: 01 01 + b180: 21 02 + b182: 00 00 + b184: 03 00 1b 02 lb zero, 33(s6) + b188: 00 00 + b18a: 01 01 + b18c: fb 0e 0d 00 + b190: 01 01 + b192: 01 01 + b194: 00 00 + b196: 00 01 + b198: 00 00 + b19a: 01 2f + b19c: 68 6f + b19e: 6d 65 + b1a0: 2f 62 6c 61 + b1a4: 69 73 + b1a6: 65 2f + b1a8: 64 65 + b1aa: 76 2f + b1ac: 72 69 + b1ae: 73 63 76 2d csrrsi t1, 727, 12 + b1b2: 67 6e 75 2d + b1b6: 74 6f + b1b8: 6f 6c 63 68 jal s8, 222854 + b1bc: 61 69 + b1be: 6e 2f + b1c0: 62 75 + b1c2: 69 6c + b1c4: 64 2f + b1c6: 62 75 + b1c8: 69 6c + b1ca: 64 2d + b1cc: 67 63 63 2d + b1d0: 6e 65 + b1d2: 77 6c 69 62 + b1d6: 2d 73 + b1d8: 74 61 + b1da: 67 65 32 2f + b1de: 67 63 63 2f + b1e2: 69 6e + b1e4: 63 6c 75 64 bltu a0, t2, 1624 + b1e8: 65 00 + b1ea: 2f 68 6f 6d + b1ee: 65 2f + b1f0: 62 6c + b1f2: 61 69 + b1f4: 73 65 2f 64 csrrsi a0, 1602, 30 + b1f8: 65 76 + b1fa: 2f 72 69 73 + b1fe: 63 76 2d 67 bgeu s10, s2, 1644 + b202: 6e 75 + b204: 2d 74 + b206: 6f 6f 6c 63 jal t5, 812598 + b20a: 68 61 + b20c: 69 6e + b20e: 2f 64 72 6f + b212: 70 73 + b214: 2f 72 69 73 + b218: 63 76 33 32 bgeu t1, gp, 812 + b21c: 2d 75 + b21e: 6e 6b + b220: 6e 6f + b222: 77 6e 2d 65 + b226: 6c 66 + b228: 2f 69 6e 63 + b22c: 6c 75 + b22e: 64 65 + b230: 2f 73 79 73 + b234: 00 2f + b236: 68 6f + b238: 6d 65 + b23a: 2f 62 6c 61 + b23e: 69 73 + b240: 65 2f + b242: 64 65 + b244: 76 2f + b246: 72 69 + b248: 73 63 76 2d csrrsi t1, 727, 12 + b24c: 67 6e 75 2d + b250: 74 6f + b252: 6f 6c 63 68 jal s8, 222854 + b256: 61 69 + b258: 6e 2f + b25a: 64 72 + b25c: 6f 70 73 2f j 228086 + b260: 72 69 + b262: 73 63 76 33 csrrsi t1, mhpmevent23, 12 + b266: 32 2d + b268: 75 6e + b26a: 6b 6e 6f 77 + b26e: 6e 2d + b270: 65 6c + b272: 66 2f + b274: 69 6e + b276: 63 6c 75 64 bltu a0, t2, 1624 + b27a: 65 00 + b27c: 2e 2e + b27e: 2f 2e 2e 2f + b282: 2e 2e + b284: 2f 2e 2e 2f + b288: 72 69 + b28a: 73 63 76 2d csrrsi t1, 727, 12 + b28e: 67 63 63 2f + b292: 6c 69 + b294: 62 67 + b296: 63 63 2f 2e bltu t5, sp, 742 + b29a: 2e 2f + b29c: 69 6e + b29e: 63 6c 75 64 bltu a0, t2, 1624 + b2a2: 65 00 + b2a4: 2e 2e + b2a6: 2f 2e 2e 2f + b2aa: 2e 2e + b2ac: 2f 2e 2e 2f + b2b0: 72 69 + b2b2: 73 63 76 2d csrrsi t1, 727, 12 + b2b6: 67 63 63 2f + b2ba: 6c 69 + b2bc: 62 67 + b2be: 63 63 2f 2e bltu t5, sp, 742 + b2c2: 2e 2f + b2c4: 67 63 63 2f + b2c8: 63 6f 6e 66 bltu t3, t1, 1662 + b2cc: 69 67 + b2ce: 2f 72 69 73 + b2d2: 63 76 00 2e bgeu zero, zero, 748 + b2d6: 2e 2f + b2d8: 2e 2e + b2da: 2f 2e 2f 67 + b2de: 63 63 00 2e bltu zero, zero, 742 + b2e2: 2e 2f + b2e4: 2e 2e + b2e6: 2f 2e 2e 2f + b2ea: 2e 2e + b2ec: 2f 72 69 73 + b2f0: 63 76 2d 67 bgeu s10, s2, 1644 + b2f4: 63 63 2f 6c bltu t5, sp, 1734 + b2f8: 69 62 + b2fa: 67 63 63 00 + b2fe: 00 73 + b300: 74 64 + b302: 64 65 + b304: 66 2e + b306: 68 00 + b308: 01 00 + b30a: 00 5f + b30c: 74 79 + b30e: 70 65 + b310: 73 2e 68 00 csrrs t3, 6, a6 + b314: 02 00 + b316: 00 72 + b318: 65 65 + b31a: 6e 74 + b31c: 2e 68 + b31e: 00 02 + b320: 00 00 + b322: 6c 6f + b324: 63 6b 2e 68 bltu t3, sp, 1686 + b328: 00 02 + b32a: 00 00 + b32c: 65 72 + b32e: 72 6e + b330: 6f 2e 68 00 jal t3, 532486 + b334: 02 00 + b336: 00 73 + b338: 74 64 + b33a: 6c 69 + b33c: 62 2e + b33e: 68 00 + b340: 03 00 00 75 lb zero, 1872(zero) + b344: 6e 69 + b346: 73 74 64 2e csrrci s0, 742, 8 + b34a: 68 00 + b34c: 02 00 + b34e: 00 74 + b350: 69 6d + b352: 65 2e + b354: 68 00 + b356: 03 00 00 68 lb zero, 1664(zero) + b35a: 61 73 + b35c: 68 74 + b35e: 61 62 + b360: 2e 68 + b362: 00 04 + b364: 00 00 + b366: 72 69 + b368: 73 63 76 2d csrrsi t1, 727, 12 + b36c: 6f 70 74 73 j 294710 + b370: 2e 68 + b372: 00 05 + b374: 00 00 + b376: 69 6e + b378: 73 6e 2d 63 csrrsi t3, 1586, 26 + b37c: 6f 6e 73 74 jal t3, 225094 + b380: 61 6e + b382: 74 73 + b384: 2e 68 + b386: 00 06 + b388: 00 00 + b38a: 6c 69 + b38c: 62 67 + b38e: 63 63 32 2e bltu tp, gp, 742 + b392: 68 00 + b394: 07 00 00 6c + b398: 69 62 + b39a: 67 63 63 32 + b39e: 2e 63 + b3a0: 00 07 + b3a2: 00 00 + b3a4: 00 ad + b3a6: 02 00 + b3a8: 00 03 + b3aa: 00 1b + b3ac: 02 00 + b3ae: 00 01 + b3b0: 01 fb + b3b2: 0e 0d + b3b4: 00 01 + b3b6: 01 01 + b3b8: 01 00 + b3ba: 00 00 + b3bc: 01 00 + b3be: 00 01 + b3c0: 2e 2e + b3c2: 2f 2e 2e 2f + b3c6: 2e 2e + b3c8: 2f 2e 2e 2f + b3cc: 72 69 + b3ce: 73 63 76 2d csrrsi t1, 727, 12 + b3d2: 67 63 63 2f + b3d6: 6c 69 + b3d8: 62 67 + b3da: 63 63 00 2f bltu zero, a6, 742 + b3de: 68 6f + b3e0: 6d 65 + b3e2: 2f 62 6c 61 + b3e6: 69 73 + b3e8: 65 2f + b3ea: 64 65 + b3ec: 76 2f + b3ee: 72 69 + b3f0: 73 63 76 2d csrrsi t1, 727, 12 + b3f4: 67 6e 75 2d + b3f8: 74 6f + b3fa: 6f 6c 63 68 jal s8, 222854 + b3fe: 61 69 + b400: 6e 2f + b402: 62 75 + b404: 69 6c + b406: 64 2f + b408: 62 75 + b40a: 69 6c + b40c: 64 2d + b40e: 67 63 63 2d + b412: 6e 65 + b414: 77 6c 69 62 + b418: 2d 73 + b41a: 74 61 + b41c: 67 65 32 2f + b420: 67 63 63 2f + b424: 69 6e + b426: 63 6c 75 64 bltu a0, t2, 1624 + b42a: 65 00 + b42c: 2f 68 6f 6d + b430: 65 2f + b432: 62 6c + b434: 61 69 + b436: 73 65 2f 64 csrrsi a0, 1602, 30 + b43a: 65 76 + b43c: 2f 72 69 73 + b440: 63 76 2d 67 bgeu s10, s2, 1644 + b444: 6e 75 + b446: 2d 74 + b448: 6f 6f 6c 63 jal t5, 812598 + b44c: 68 61 + b44e: 69 6e + b450: 2f 64 72 6f + b454: 70 73 + b456: 2f 72 69 73 + b45a: 63 76 33 32 bgeu t1, gp, 812 + b45e: 2d 75 + b460: 6e 6b + b462: 6e 6f + b464: 77 6e 2d 65 + b468: 6c 66 + b46a: 2f 69 6e 63 + b46e: 6c 75 + b470: 64 65 + b472: 2f 73 79 73 + b476: 00 2f + b478: 68 6f + b47a: 6d 65 + b47c: 2f 62 6c 61 + b480: 69 73 + b482: 65 2f + b484: 64 65 + b486: 76 2f + b488: 72 69 + b48a: 73 63 76 2d csrrsi t1, 727, 12 + b48e: 67 6e 75 2d + b492: 74 6f + b494: 6f 6c 63 68 jal s8, 222854 + b498: 61 69 + b49a: 6e 2f + b49c: 64 72 + b49e: 6f 70 73 2f j 228086 + b4a2: 72 69 + b4a4: 73 63 76 33 csrrsi t1, mhpmevent23, 12 + b4a8: 32 2d + b4aa: 75 6e + b4ac: 6b 6e 6f 77 + b4b0: 6e 2d + b4b2: 65 6c + b4b4: 66 2f + b4b6: 69 6e + b4b8: 63 6c 75 64 bltu a0, t2, 1624 + b4bc: 65 00 + b4be: 2e 2e + b4c0: 2f 2e 2e 2f + b4c4: 2e 2e + b4c6: 2f 2e 2e 2f + b4ca: 72 69 + b4cc: 73 63 76 2d csrrsi t1, 727, 12 + b4d0: 67 63 63 2f + b4d4: 6c 69 + b4d6: 62 67 + b4d8: 63 63 2f 2e bltu t5, sp, 742 + b4dc: 2e 2f + b4de: 69 6e + b4e0: 63 6c 75 64 bltu a0, t2, 1624 + b4e4: 65 00 + b4e6: 2e 2e + b4e8: 2f 2e 2e 2f + b4ec: 2e 2e + b4ee: 2f 2e 2e 2f + b4f2: 72 69 + b4f4: 73 63 76 2d csrrsi t1, 727, 12 + b4f8: 67 63 63 2f + b4fc: 6c 69 + b4fe: 62 67 + b500: 63 63 2f 2e bltu t5, sp, 742 + b504: 2e 2f + b506: 67 63 63 2f + b50a: 63 6f 6e 66 bltu t3, t1, 1662 + b50e: 69 67 + b510: 2f 72 69 73 + b514: 63 76 00 2e bgeu zero, zero, 748 + b518: 2e 2f + b51a: 2e 2e + b51c: 2f 2e 2f 67 + b520: 63 63 00 00 bltu zero, zero, 6 + b524: 6c 69 + b526: 62 67 + b528: 63 63 32 2e bltu tp, gp, 742 + b52c: 63 00 01 00 beqz sp, 0 + b530: 00 73 + b532: 74 64 + b534: 64 65 + b536: 66 2e + b538: 68 00 + b53a: 02 00 + b53c: 00 5f + b53e: 74 79 + b540: 70 65 + b542: 73 2e 68 00 csrrs t3, 6, a6 + b546: 03 00 00 72 lb zero, 1824(zero) + b54a: 65 65 + b54c: 6e 74 + b54e: 2e 68 + b550: 00 03 + b552: 00 00 + b554: 6c 6f + b556: 63 6b 2e 68 bltu t3, sp, 1686 + b55a: 00 03 + b55c: 00 00 + b55e: 65 72 + b560: 72 6e + b562: 6f 2e 68 00 jal t3, 532486 + b566: 03 00 00 73 lb zero, 1840(zero) + b56a: 74 64 + b56c: 6c 69 + b56e: 62 2e + b570: 68 00 + b572: 04 00 + b574: 00 75 + b576: 6e 69 + b578: 73 74 64 2e csrrci s0, 742, 8 + b57c: 68 00 + b57e: 03 00 00 74 lb zero, 1856(zero) + b582: 69 6d + b584: 65 2e + b586: 68 00 + b588: 04 00 + b58a: 00 68 + b58c: 61 73 + b58e: 68 74 + b590: 61 62 + b592: 2e 68 + b594: 00 05 + b596: 00 00 + b598: 72 69 + b59a: 73 63 76 2d csrrsi t1, 727, 12 + b59e: 6f 70 74 73 j 294710 + b5a2: 2e 68 + b5a4: 00 06 + b5a6: 00 00 + b5a8: 69 6e + b5aa: 73 6e 2d 63 csrrsi t3, 1586, 26 + b5ae: 6f 6e 73 74 jal t3, 225094 + b5b2: 61 6e + b5b4: 74 73 + b5b6: 2e 68 + b5b8: 00 07 + b5ba: 00 00 + b5bc: 6c 69 + b5be: 62 67 + b5c0: 63 63 32 2e bltu tp, gp, 742 + b5c4: 68 00 + b5c6: 01 00 + b5c8: 00 00 + b5ca: 05 01 + b5cc: 00 05 + b5ce: 02 c8 + b5d0: 54 01 + b5d2: 80 03 + b5d4: c2 05 + b5d6: 01 05 + b5d8: 03 03 01 09 lb t1, 144(sp) + b5dc: 00 00 + b5de: 01 03 + b5e0: 02 09 + b5e2: 00 00 + b5e4: 01 03 + b5e6: 00 09 + b5e8: 00 00 + b5ea: 01 03 + b5ec: 00 09 + b5ee: 00 00 + b5f0: 01 03 + b5f2: 00 09 + b5f4: 00 00 + b5f6: 01 03 + b5f8: 00 09 + b5fa: 00 00 + b5fc: 01 00 + b5fe: 02 04 + b600: 03 06 03 00 lb a2, 0(t1) + b604: 09 08 + b606: 00 01 + b608: 00 02 + b60a: 04 0e + b60c: 06 03 + b60e: 00 09 + b610: 0c 00 + b612: 01 00 + b614: 02 04 + b616: 0e 03 + b618: 00 09 + b61a: 00 00 + b61c: 01 00 + b61e: 02 04 + b620: 0e 03 + b622: 02 09 + b624: 00 00 + b626: 01 00 + b628: 02 04 + b62a: 0e 06 + b62c: 03 7e 09 00 + b630: 00 01 + b632: 05 01 + b634: 00 02 + b636: 04 0e + b638: 03 03 09 1c lb t1, 448(s2) + b63c: 00 01 + b63e: 05 03 + b640: 00 02 + b642: 04 04 + b644: 03 7d 09 08 + b648: 00 01 + b64a: 03 00 09 0c lb zero, 192(s2) + b64e: 00 01 + b650: 09 08 + b652: 00 00 + b654: 01 01 + +Disassembly of section .debug_frame: + +00000000 .debug_frame: + 0: 0c 00 + 2: 00 00 + 4: ff ff ff ff + 8: 03 00 01 7c lb zero, 1984(sp) + c: 01 0d + e: 02 00 + 10: 44 00 + 12: 00 00 + 14: 00 00 + 16: 00 00 + 18: f0 07 + 1a: 01 80 + 1c: c0 08 + 1e: 00 00 + 20: 44 0e + 22: 30 6c + 24: 88 02 + 26: 95 07 + 28: 98 0a + 2a: 81 01 + 2c: 89 03 + 2e: 92 04 + 30: 93 05 94 06 addi a1, s0, 105 + 34: 96 08 + 36: 97 09 99 0b auipc s3, 47504 + 3a: 03 10 06 0a lh zero, 160(a2) + 3e: c1 44 + 40: c8 44 + 42: c9 44 + 44: d2 44 + 46: d3 44 d4 44 + 4a: d5 44 + 4c: d6 44 + 4e: d7 44 d8 44 + 52: d9 44 + 54: 0e 00 + 56: 44 0b + 58: 0c 00 + 5a: 00 00 + 5c: ff ff ff ff + 60: 03 00 01 7c lb zero, 1984(sp) + 64: 01 0d + 66: 02 00 + 68: 44 00 + 6a: 00 00 + 6c: 58 00 + 6e: 00 00 + 70: b0 10 + 72: 01 80 + 74: a8 07 + 76: 00 00 + 78: 44 0e + 7a: 30 6c + 7c: 88 02 + 7e: 96 08 + 80: 99 0b + 82: 81 01 + 84: 89 03 + 86: 92 04 + 88: 93 05 94 06 addi a1, s0, 105 + 8c: 95 07 + 8e: 97 09 98 0a auipc s3, 43392 + 92: 03 88 02 0a lb a6, 160(t0) + 96: c1 44 + 98: c8 44 + 9a: c9 44 + 9c: d2 44 + 9e: d3 44 d4 44 + a2: d5 44 + a4: d6 44 + a6: d7 44 d8 44 + aa: d9 44 + ac: 0e 00 + ae: 44 0b + b0: 0c 00 + b2: 00 00 + b4: ff ff ff ff + b8: 03 00 01 7c lb zero, 1984(sp) + bc: 01 0d + be: 02 00 + c0: 18 00 + c2: 00 00 + c4: b0 00 + c6: 00 00 + c8: 58 18 + ca: 01 80 + cc: 2c 01 + ce: 00 00 + d0: 64 0e + d2: 10 02 + d4: 98 0a + d6: 0e 00 + d8: 44 0b + da: 00 00 + dc: 0c 00 + de: 00 00 + e0: ff ff ff ff + e4: 03 00 01 7c lb zero, 1984(sp) + e8: 01 0d + ea: 02 00 + ec: 18 00 + ee: 00 00 + f0: dc 00 + f2: 00 00 + f4: 84 19 + f6: 01 80 + f8: 4c 01 + fa: 00 00 + fc: 64 0e + fe: 10 02 + 100: a4 0a + 102: 0e 00 + 104: 44 0b + 106: 00 00 + 108: 0c 00 + 10a: 00 00 + 10c: ff ff ff ff + 110: 03 00 01 7c lb zero, 1984(sp) + 114: 01 0d + 116: 02 00 + 118: 18 00 + 11a: 00 00 + 11c: 08 01 + 11e: 00 00 + 120: d0 1a + 122: 01 80 + 124: 4c 01 + 126: 00 00 + 128: 64 0e + 12a: 10 02 + 12c: a4 0a + 12e: 0e 00 + 130: 44 0b + 132: 00 00 + 134: 0c 00 + 136: 00 00 + 138: ff ff ff ff + 13c: 03 00 01 7c lb zero, 1984(sp) + 140: 01 0d + 142: 02 00 + 144: 50 00 + 146: 00 00 + 148: 34 01 + 14a: 00 00 + 14c: 1c 1c + 14e: 01 80 + 150: d8 12 + 152: 00 00 + 154: 44 0e + 156: c0 01 + 158: 58 92 + 15a: 04 94 + 15c: 06 95 + 15e: 07 96 08 98 + 162: 0a 99 + 164: 0b 02 40 81 + 168: 01 88 + 16a: 02 89 + 16c: 03 93 05 97 lh t1, -1680(a1) + 170: 09 9a + 172: 0c 9b + 174: 0d 03 + 176: 30 0e + 178: 0a c1 + 17a: 44 c8 + 17c: 54 c9 + 17e: 44 d3 + 180: 44 d4 + 182: 44 d5 + 184: 44 d6 + 186: 44 d7 + 188: 44 d8 + 18a: 44 d9 + 18c: 44 da + 18e: 44 db + 190: 48 d2 + 192: 44 0e + 194: 00 44 + 196: 0b 00 0c 00 + 19a: 00 00 + 19c: ff ff ff ff + 1a0: 03 00 01 7c lb zero, 1984(sp) + 1a4: 01 0d + 1a6: 02 00 + 1a8: 40 00 + 1aa: 00 00 + 1ac: 98 01 + 1ae: 00 00 + 1b0: f4 2e + 1b2: 01 80 + 1b4: c8 1a + 1b6: 00 00 + 1b8: 44 0e + 1ba: 70 54 + 1bc: 89 03 + 1be: 92 04 + 1c0: 64 81 + 1c2: 01 88 + 1c4: 02 93 + 1c6: 05 94 + 1c8: 06 95 + 1ca: 07 96 08 97 + 1ce: 09 03 + 1d0: b4 0a + 1d2: 0a c1 + 1d4: 44 c8 + 1d6: 54 c9 + 1d8: 44 d3 + 1da: 44 d4 + 1dc: 44 d5 + 1de: 44 d6 + 1e0: 44 d7 + 1e2: 48 d2 + 1e4: 44 0e + 1e6: 00 44 + 1e8: 0b 00 00 00 + 1ec: 0c 00 + 1ee: 00 00 + 1f0: ff ff ff ff + 1f4: 03 00 01 7c lb zero, 1984(sp) + 1f8: 01 0d + 1fa: 02 00 + 1fc: 18 00 + 1fe: 00 00 + 200: ec 01 + 202: 00 00 + 204: bc 49 + 206: 01 80 + 208: ac 01 + 20a: 00 00 + 20c: 54 0e + 20e: 20 02 + 210: 54 0a + 212: 0e 00 + 214: 44 0b + 216: 00 00 + 218: 0c 00 + 21a: 00 00 + 21c: ff ff ff ff + 220: 03 00 01 7c lb zero, 1984(sp) + 224: 01 0d + 226: 02 00 + 228: 28 00 + 22a: 00 00 + 22c: 18 02 + 22e: 00 00 + 230: 68 4b + 232: 01 80 + 234: 50 01 + 236: 00 00 + 238: 44 0e + 23a: 30 50 + 23c: 89 03 + 23e: 81 01 + 240: 88 02 + 242: 92 04 + 244: 02 d4 + 246: 0a c1 + 248: 44 c8 + 24a: 58 d2 + 24c: 64 c9 + 24e: 44 0e + 250: 00 44 + 252: 0b 00 0c 00 + 256: 00 00 + 258: ff ff ff ff + 25c: 03 00 01 7c lb zero, 1984(sp) + 260: 01 0d + 262: 02 00 + 264: 28 00 + 266: 00 00 + 268: 54 02 + 26a: 00 00 + 26c: b8 4c + 26e: 01 80 + 270: 0c 01 + 272: 00 00 + 274: 44 0e + 276: 10 54 + 278: 81 01 + 27a: 88 02 + 27c: 89 03 + 27e: 92 04 + 280: 02 60 + 282: 0a c1 + 284: 44 c8 + 286: 44 c9 + 288: 44 d2 + 28a: 44 0e + 28c: 00 44 + 28e: 0b 00 0c 00 + 292: 00 00 + 294: ff ff ff ff + 298: 03 00 01 7c lb zero, 1984(sp) + 29c: 01 0d + 29e: 02 00 + 2a0: 2c 00 + 2a2: 00 00 + 2a4: 90 02 + 2a6: 00 00 + 2a8: c4 4d + 2aa: 01 80 + 2ac: 28 02 + 2ae: 00 00 + 2b0: 44 0e + 2b2: 40 54 + 2b4: 89 03 + 2b6: 93 05 81 01 addi a1, sp, 24 + 2ba: 88 02 + 2bc: 92 04 + 2be: 02 a0 + 2c0: 0a c1 + 2c2: 44 c8 + 2c4: 54 c9 + 2c6: 44 d2 + 2c8: 48 d3 + 2ca: 44 0e + 2cc: 00 44 + 2ce: 0b 00 0c 00 + 2d2: 00 00 + 2d4: ff ff ff ff + 2d8: 03 00 01 7c lb zero, 1984(sp) + 2dc: 01 0d + 2de: 02 00 + 2e0: 18 00 + 2e2: 00 00 + 2e4: d0 02 + 2e6: 00 00 + 2e8: ec 4f + 2ea: 01 80 + 2ec: dc 04 + 2ee: 00 00 + 2f0: 44 0e + 2f2: 20 03 + 2f4: a4 01 + 2f6: 0a 0e + 2f8: 00 44 + 2fa: 0b 00 0c 00 + 2fe: 00 00 + 300: ff ff ff ff + 304: 03 00 01 7c lb zero, 1984(sp) + 308: 01 0d + 30a: 02 00 + 30c: 0c 00 + 30e: 00 00 + 310: fc 02 + 312: 00 00 + 314: c8 54 + 316: 01 80 + 318: 4c 00 + 31a: 00 00 + +Disassembly of section .debug_str: + +00000000 .debug_str: + 0: 73 68 6f 72 csrrsi a6, 1830, 30 + 4: 74 20 + 6: 69 6e + 8: 74 00 + a: 68 74 + c: 61 62 + e: 5f 68 61 73 + 12: 68 5f + 14: 70 6f + 16: 69 6e + 18: 74 65 + 1a: 72 00 + 1c: 5f 73 69 7a + 20: 65 00 + 22: 5f 72 61 6e + 26: 64 34 + 28: 38 00 + 2a: 5f 65 6d 65 + 2e: 72 67 + 30: 65 6e + 32: 63 79 00 5f bgeu zero, a6, 1522 + 36: 64 61 + 38: 79 6c + 3a: 69 67 + 3c: 68 74 + 3e: 00 63 + 40: 6f 6d 70 6c jal s10, 28358 + 44: 65 78 + 46: 20 64 + 48: 6f 75 62 6c jal a0, 161478 + 4c: 65 00 + 4e: 5f 67 65 74 + 52: 64 61 + 54: 74 65 + 56: 5f 65 72 72 + 5a: 00 5f + 5c: 64 61 + 5e: 74 61 + 60: 00 5f + 62: 77 63 72 74 + 66: 6f 6d 62 5f jal s10, 157174 + 6a: 73 74 61 74 csrrci s0, 1862, 2 + 6e: 65 00 + 70: 72 69 + 72: 73 63 76 5f csrrsi t1, 1527, 12 + 76: 6d 69 + 78: 63 72 6f 61 bgeu t5, s6, 1540 + 7c: 72 63 + 7e: 68 69 + 80: 74 65 + 82: 63 74 75 72 bgeu a0, t2, 1832 + 86: 65 5f + 88: 74 79 + 8a: 70 65 + 8c: 00 5f + 8e: 77 63 73 72 + 92: 74 6f + 94: 6d 62 + 96: 73 5f 73 74 csrrwi t5, 1863, 6 + 9a: 61 74 + 9c: 65 00 + 9e: 5f 5f 64 30 + a2: 00 5f + a4: 5f 64 31 00 + a8: 5f 6c 62 66 + ac: 73 69 7a 65 csrrsi s2, 1623, 20 + b0: 00 6f + b2: 70 74 + b4: 69 6e + b6: 64 00 + b8: 63 6f 6d 70 bltu s10, t1, 1822 + bc: 6c 65 + be: 78 20 + c0: 6c 6f + c2: 6e 67 + c4: 20 64 + c6: 6f 75 62 6c jal a0, 161478 + ca: 65 00 + cc: 72 69 + ce: 73 63 76 5f csrrsi t1, 1527, 12 + d2: 61 62 + d4: 69 00 + d6: 5f 5f 6c 6f + da: 63 61 6c 65 bltu s8, s6, 1602 + de: 5f 74 00 5f + e2: 6d 62 + e4: 72 74 + e6: 6f 77 63 5f jal a4, 226806 + ea: 73 74 61 74 csrrci s0, 1862, 2 + ee: 65 00 + f0: 5f 74 7a 6e + f4: 61 6d + f6: 65 00 + f8: 5f 5f 74 6d + fc: 5f 73 65 63 + 100: 00 5f + 102: 63 6c 6f 73 bltu t5, s6, 1848 + 106: 65 00 + 108: 5f 75 62 75 + 10c: 66 00 + 10e: 5f 62 61 73 + 112: 65 00 + 114: 5f 5f 74 6d + 118: 5f 68 6f 75 + 11c: 72 00 + 11e: 5f 77 63 74 + 122: 6f 6d 62 5f jal s10, 157174 + 126: 73 74 61 74 csrrci s0, 1862, 2 + 12a: 65 00 + 12c: 5f 5f 73 66 + 130: 00 5f + 132: 6f 6e 5f 65 jal t3, 1011284 + 136: 78 69 + 138: 74 5f + 13a: 61 72 + 13c: 67 73 00 5f + 140: 63 6f 6f 6b bltu t5, s6, 1726 + 144: 69 65 + 146: 00 5f + 148: 5f 73 67 6c + 14c: 75 65 + 14e: 00 72 + 150: 69 73 + 152: 63 76 5f 63 bgeu t5, s5, 1580 + 156: 6d 6f + 158: 64 65 + 15a: 6c 00 + 15c: 5f 66 6c 61 + 160: 67 73 00 5f + 164: 69 73 + 166: 5f 63 78 61 + 16a: 00 5f + 16c: 77 64 73 00 + 170: 5f 5f 46 49 + 174: 4c 45 + 176: 00 5f + 178: 72 65 + 17a: 73 75 6c 74 csrrci a0, 1862, 24 + 17e: 5f 6b 00 55 + 182: 53 49 74 79 + 186: 70 65 + 188: 00 72 + 18a: 69 73 + 18c: 63 76 5f 6d bgeu t5, s5, 1740 + 190: 69 63 + 192: 72 6f + 194: 61 72 + 196: 63 68 69 74 bltu s2, t1, 1872 + 19a: 65 63 + 19c: 74 75 + 19e: 72 65 + 1a0: 00 5f + 1a2: 73 79 73 5f csrrci s2, 1527, 6 + 1a6: 65 72 + 1a8: 72 6c + 1aa: 69 73 + 1ac: 74 00 + 1ae: 5f 63 76 74 + 1b2: 62 75 + 1b4: 66 00 + 1b6: 5f 6d 62 73 + 1ba: 72 74 + 1bc: 6f 77 63 73 jal a4, 227126 + 1c0: 5f 73 74 61 + 1c4: 74 65 + 1c6: 00 5f + 1c8: 6d 62 + 1ca: 72 6c + 1cc: 65 6e + 1ce: 5f 73 74 61 + 1d2: 74 65 + 1d4: 00 2f + 1d6: 68 6f + 1d8: 6d 65 + 1da: 2f 62 6c 61 + 1de: 69 73 + 1e0: 65 2f + 1e2: 64 65 + 1e4: 76 2f + 1e6: 72 69 + 1e8: 73 63 76 2d csrrsi t1, 727, 12 + 1ec: 67 6e 75 2d + 1f0: 74 6f + 1f2: 6f 6c 63 68 jal s8, 222854 + 1f6: 61 69 + 1f8: 6e 2f + 1fa: 62 75 + 1fc: 69 6c + 1fe: 64 2f + 200: 62 75 + 202: 69 6c + 204: 64 2d + 206: 67 63 63 2d + 20a: 6e 65 + 20c: 77 6c 69 62 + 210: 2d 73 + 212: 74 61 + 214: 67 65 32 2f + 218: 72 69 + 21a: 73 63 76 33 csrrsi t1, mhpmevent23, 12 + 21e: 32 2d + 220: 75 6e + 222: 6b 6e 6f 77 + 226: 6e 2d + 228: 65 6c + 22a: 66 2f + 22c: 6c 69 + 22e: 62 67 + 230: 63 63 00 5f bltu zero, a6, 1510 + 234: 66 6e + 236: 61 72 + 238: 67 73 00 5f + 23c: 66 6e + 23e: 73 00 5f 73 + 242: 69 67 + 244: 6e 00 + 246: 5f 73 74 64 + 24a: 65 72 + 24c: 72 00 + 24e: 5f 67 61 6d + 252: 6d 61 + 254: 5f 73 69 67 + 258: 6e 67 + 25a: 61 6d + 25c: 00 5f + 25e: 6e 6d + 260: 61 6c + 262: 6c 6f + 264: 63 00 5f 75 beq t5, s5, 1856 + 268: 6e 73 + 26a: 70 65 + 26c: 63 69 66 69 bltu a2, s6, 1682 + 270: 65 64 + 272: 5f 6c 6f 63 + 276: 61 6c + 278: 65 5f + 27a: 69 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beq t5, t0, 1120 + 12d6: 50 5f + 12d8: 50 41 + 12da: 43 4b 5f 53 + 12de: 45 4d + 12e0: 49 52 + 12e2: 41 57 + 12e4: 5f 54 5f 66 + 12e8: 30 00 + 12ea: 5f 46 50 5f + 12ee: 50 41 + 12f0: 43 4b 5f 53 + 12f4: 45 4d + 12f6: 49 52 + 12f8: 41 57 + 12fa: 5f 54 5f 66 + 12fe: 31 00 + 1300: 5f 5f 74 72 + 1304: 75 6e + 1306: 63 74 66 64 bgeu a2, t1, 1608 + 130a: 66 32 + 130c: 00 5f + 130e: 5f 63 6c 7a + 1312: 73 69 32 00 csrrsi s2, fcsr, 4 + +Disassembly of section .debug_loc: + +00000000 .debug_loc: + 0: 00 00 + 2: 00 00 + 4: 10 00 + 6: 00 00 + 8: 06 00 + a: 5a 93 + c: 04 5b + e: 93 04 10 00 addi s1, zero, 1 + 12: 00 00 + 14: 34 04 + 16: 00 00 + 18: 06 00 + 1a: f3 03 f5 0a + 1e: 25 9f + ... + 2c: 74 00 + 2e: 00 00 + 30: 06 00 + 32: 5c 93 + 34: 04 5d + 36: 93 04 74 00 addi s1, s0, 7 + 3a: 00 00 + 3c: f8 00 + 3e: 00 00 + 40: 06 00 + 42: f3 03 f5 0c + 46: 25 9f + 48: f8 00 + 4a: 00 00 + 4c: 3c 01 + 4e: 00 00 + 50: 06 00 + 52: 5c 93 + 54: 04 5d + 56: 93 04 3c 01 addi s1, s8, 19 + 5a: 00 00 + 5c: dc 01 + 5e: 00 00 + 60: 06 00 + 62: f3 03 f5 0c + 66: 25 9f + 68: dc 01 + 6a: 00 00 + 6c: f0 01 + 6e: 00 00 + 70: 06 00 + 72: 5c 93 + 74: 04 5d + 76: 93 04 f0 01 addi s1, zero, 31 + 7a: 00 00 + 7c: 9c 02 + 7e: 00 00 + 80: 06 00 + 82: f3 03 f5 0c + 86: 25 9f + 88: 9c 02 + 8a: 00 00 + 8c: 18 03 + 8e: 00 00 + 90: 06 00 + 92: 5c 93 + 94: 04 5d + 96: 93 04 18 03 addi s1, a6, 49 + 9a: 00 00 + 9c: 28 04 + 9e: 00 00 + a0: 06 00 + a2: f3 03 f5 0c + a6: 25 9f + a8: 28 04 + aa: 00 00 + ac: 34 04 + ae: 00 00 + b0: 06 00 + b2: 5c 93 + b4: 04 5d + b6: 93 04 00 00 mv s1, zero + ba: 00 00 + bc: 00 00 + be: 00 00 + c0: 04 00 + c2: 00 00 + c4: d8 01 + c6: 00 00 + c8: 02 00 + ca: 30 9f + cc: dc 01 + ce: 00 00 + d0: 34 04 + d2: 00 00 + d4: 02 00 + d6: 30 9f + ... + e0: 04 00 + e2: 00 00 + e4: 1c 00 + e6: 00 00 + e8: 06 00 + ea: 5c 93 + ec: 04 5d + ee: 93 04 1c 00 addi s1, s8, 1 + f2: 00 00 + f4: 38 00 + f6: 00 00 + f8: 06 00 + fa: 5c 93 + fc: 04 5a + fe: 93 04 f8 00 addi s1, a6, 15 + 102: 00 00 + 104: fc 00 + 106: 00 00 + 108: 06 00 + 10a: 5c 93 + 10c: 04 5a + 10e: 93 04 0c 01 addi s1, s8, 16 + 112: 00 00 + 114: 2c 01 + 116: 00 00 + 118: 06 00 + 11a: 5c 93 + 11c: 04 5a + 11e: 93 04 dc 01 addi s1, s8, 29 + 122: 00 00 + 124: e4 01 + 126: 00 00 + 128: 06 00 + 12a: 5c 93 + 12c: 04 5a + 12e: 93 04 9c 02 addi s1, s8, 41 + 132: 00 00 + 134: bc 02 + 136: 00 00 + 138: 06 00 + 13a: 5c 93 + 13c: 04 5a + 13e: 93 04 bc 02 addi s1, s8, 43 + 142: 00 00 + 144: ec 02 + 146: 00 00 + 148: 06 00 + 14a: 5c 93 + 14c: 04 5d + 14e: 93 04 ec 02 addi s1, s8, 46 + 152: 00 00 + 154: 00 03 + 156: 00 00 + 158: 06 00 + 15a: 5c 93 + 15c: 04 5a + 15e: 93 04 00 03 addi s1, zero, 48 + 162: 00 00 + 164: 08 03 + 166: 00 00 + 168: 06 00 + 16a: 5c 93 + 16c: 04 5d + 16e: 93 04 28 04 addi s1, a6, 66 + 172: 00 00 + 174: 30 04 + 176: 00 00 + 178: 06 00 + 17a: 5c 93 + 17c: 04 5a + 17e: 93 04 30 04 addi s1, zero, 67 + 182: 00 00 + 184: 34 04 + 186: 00 00 + 188: 06 00 + 18a: 5c 93 + 18c: 04 5d + 18e: 93 04 00 00 mv s1, zero + 192: 00 00 + 194: 00 00 + 196: 00 00 + 198: 04 00 + 19a: 00 00 + 19c: 10 00 + 19e: 00 00 + 1a0: 06 00 + 1a2: 5a 93 + 1a4: 04 5b + 1a6: 93 04 10 00 addi s1, zero, 1 + 1aa: 00 00 + 1ac: 64 00 + 1ae: 00 00 + 1b0: 06 00 + 1b2: 61 93 + 1b4: 04 5b + 1b6: 93 04 f8 00 addi s1, a6, 15 + 1ba: 00 00 + 1bc: 50 01 + 1be: 00 00 + 1c0: 06 00 + 1c2: 56 93 + 1c4: 04 5b + 1c6: 93 04 dc 01 addi s1, s8, 29 + 1ca: 00 00 + 1cc: f8 01 + 1ce: 00 00 + 1d0: 06 00 + 1d2: 56 93 + 1d4: 04 5b + 1d6: 93 04 f8 01 addi s1, a6, 31 + 1da: 00 00 + 1dc: fc 01 + 1de: 00 00 + 1e0: 06 00 + 1e2: 56 93 + 1e4: 04 5f + 1e6: 93 04 fc 01 addi s1, s8, 31 + 1ea: 00 00 + 1ec: 00 02 + 1ee: 00 00 + 1f0: 06 00 + 1f2: 61 93 + 1f4: 04 5f + 1f6: 93 04 9c 02 addi s1, s8, 41 + 1fa: 00 00 + 1fc: b0 02 + 1fe: 00 00 + 200: 06 00 + 202: 56 93 + 204: 04 5b + 206: 93 04 b0 02 addi s1, zero, 43 + 20a: 00 00 + 20c: ec 02 + 20e: 00 00 + 210: 06 00 + 212: 56 93 + 214: 04 5f + 216: 93 04 ec 02 addi s1, s8, 46 + 21a: 00 00 + 21c: f4 02 + 21e: 00 00 + 220: 06 00 + 222: 56 93 + 224: 04 5b + 226: 93 04 f4 02 addi s1, s0, 47 + 22a: 00 00 + 22c: 04 03 + 22e: 00 00 + 230: 06 00 + 232: 56 93 + 234: 04 5f + 236: 93 04 04 03 addi s1, s0, 48 + 23a: 00 00 + 23c: 20 03 + 23e: 00 00 + 240: 06 00 + 242: 61 93 + 244: 04 5f + 246: 93 04 28 04 addi s1, a6, 66 + 24a: 00 00 + 24c: 2c 04 + 24e: 00 00 + 250: 06 00 + 252: 56 93 + 254: 04 5b + 256: 93 04 2c 04 addi s1, s8, 66 + 25a: 00 00 + 25c: 34 04 + 25e: 00 00 + 260: 06 00 + 262: 56 93 + 264: 04 5f + 266: 93 04 00 00 mv s1, zero + 26a: 00 00 + 26c: 00 00 + 26e: 00 00 + 270: 0c 00 + 272: 00 00 + 274: 54 00 + 276: 00 00 + 278: 01 00 + 27a: 5c 54 + 27c: 00 00 + 27e: 00 60 + 280: 00 00 + 282: 00 09 + 284: 00 7c + 286: 00 7d + 288: 00 08 + 28a: ff 1a 24 9f + 28e: 60 00 + 290: 00 00 + 292: f0 00 + 294: 00 00 + 296: 01 00 + 298: 60 f8 + 29a: 00 00 + 29c: 00 14 + 29e: 01 00 + 2a0: 00 01 + 2a2: 00 5c + 2a4: 14 01 + 2a6: 00 00 + 2a8: 18 01 + 2aa: 00 00 + 2ac: 0b 00 31 f7 + 2b0: 2c 7c + 2b2: 00 f7 + 2b4: 2c 1b + 2b6: f7 00 9f 18 + 2ba: 01 00 + 2bc: 00 d8 + 2be: 01 00 + 2c0: 00 01 + 2c2: 00 60 + 2c4: dc 01 + 2c6: 00 00 + 2c8: f0 01 + 2ca: 00 00 + 2cc: 01 00 + 2ce: 60 f0 + 2d0: 01 00 + 2d2: 00 f4 + 2d4: 01 00 + 2d6: 00 09 + 2d8: 00 80 + 2da: 00 7d + 2dc: 00 08 + 2de: ff 1a 24 9f + 2e2: f4 01 + 2e4: 00 00 + 2e6: 9c 02 + 2e8: 00 00 + 2ea: 01 00 + 2ec: 60 9c + 2ee: 02 00 + 2f0: 00 14 + 2f2: 03 00 00 01 lb zero, 16(zero) + 2f6: 00 5c + 2f8: 14 03 + 2fa: 00 00 + 2fc: c8 03 + 2fe: 00 00 + 300: 01 00 + 302: 6d 28 + 304: 04 00 + 306: 00 34 + 308: 04 00 + 30a: 00 01 + 30c: 00 5c + ... + 316: 10 00 + 318: 00 00 + 31a: 1c 00 + 31c: 00 00 + 31e: 01 00 + 320: 5d 1c + 322: 00 00 + 324: 00 38 + 326: 00 00 + 328: 00 01 + 32a: 00 5a + 32c: f8 00 + 32e: 00 00 + 330: fc 00 + 332: 00 00 + 334: 01 00 + 336: 5a 0c + 338: 01 00 + 33a: 00 2c + 33c: 01 00 + 33e: 00 01 + 340: 00 5a + 342: dc 01 + 344: 00 00 + 346: e4 01 + 348: 00 00 + 34a: 01 00 + 34c: 5a 9c + 34e: 02 00 + 350: 00 bc + 352: 02 00 + 354: 00 01 + 356: 00 5a + 358: bc 02 + 35a: 00 00 + 35c: ec 02 + 35e: 00 00 + 360: 01 00 + 362: 5d ec + 364: 02 00 + 366: 00 00 + 368: 03 00 00 01 lb zero, 16(zero) + 36c: 00 5a + 36e: 00 03 + 370: 00 00 + 372: 08 03 + 374: 00 00 + 376: 01 00 + 378: 5d 0c + 37a: 03 00 00 cc lb zero, -832(zero) + 37e: 03 00 00 01 lb zero, 16(zero) + 382: 00 56 + 384: 28 04 + 386: 00 00 + 388: 30 04 + 38a: 00 00 + 38c: 01 00 + 38e: 5a 30 + 390: 04 00 + 392: 00 34 + 394: 04 00 + 396: 00 01 + 398: 00 5d + ... + 3a2: 14 00 + 3a4: 00 00 + 3a6: 68 00 + 3a8: 00 00 + 3aa: 01 00 + 3ac: 61 68 + 3ae: 00 00 + 3b0: 00 b8 + 3b2: 00 00 + 3b4: 00 01 + 3b6: 00 56 + 3b8: f8 00 + 3ba: 00 00 + 3bc: a0 01 + 3be: 00 00 + 3c0: 01 00 + 3c2: 56 dc + 3c4: 01 00 + 3c6: 00 fc + 3c8: 01 00 + 3ca: 00 01 + 3cc: 00 56 + 3ce: fc 01 + 3d0: 00 00 + 3d2: 08 02 + 3d4: 00 00 + 3d6: 01 00 + 3d8: 61 0c + 3da: 02 00 + 3dc: 00 04 + 3de: 03 00 00 01 lb zero, 16(zero) + 3e2: 00 56 + 3e4: 04 03 + 3e6: 00 00 + 3e8: 28 03 + 3ea: 00 00 + 3ec: 01 00 + 3ee: 61 28 + 3f0: 03 00 00 14 lb zero, 320(zero) + 3f4: 04 00 + 3f6: 00 06 + 3f8: 00 81 + 3fa: 00 7b + 3fc: 00 24 + 3fe: 9f 28 04 00 + 402: 00 34 + 404: 04 00 + 406: 00 01 + 408: 00 56 + ... + 412: 14 00 + 414: 00 00 + 416: 88 00 + 418: 00 00 + 41a: 01 00 + 41c: 5b f8 00 00 + 420: 00 4c + 422: 01 00 + 424: 00 01 + 426: 00 5b + 428: 4c 01 + 42a: 00 00 + 42c: 68 01 + 42e: 00 00 + 430: 01 00 + 432: 5f dc 01 00 + 436: 00 f8 + 438: 01 00 + 43a: 00 01 + 43c: 00 5b + 43e: f8 01 + 440: 00 00 + 442: 00 02 + 444: 00 00 + 446: 01 00 + 448: 5f 0c 02 00 + 44c: 00 58 + 44e: 02 00 + 450: 00 01 + 452: 00 5c + 454: 98 02 + 456: 00 00 + 458: 9c 02 + 45a: 00 00 + 45c: 01 00 + 45e: 5f 9c 02 00 + 462: 00 b0 + 464: 02 00 + 466: 00 01 + 468: 00 5b + 46a: b0 02 + 46c: 00 00 + 46e: ec 02 + 470: 00 00 + 472: 01 00 + 474: 5f ec 02 00 + 478: 00 f4 + 47a: 02 00 + 47c: 00 01 + 47e: 00 5b + 480: f4 02 + 482: 00 00 + 484: 20 03 + 486: 00 00 + 488: 01 00 + 48a: 5f 28 03 00 + 48e: 00 b8 + 490: 03 00 00 01 lb zero, 16(zero) + 494: 00 60 + 496: bc 03 + 498: 00 00 + 49a: 00 04 + 49c: 00 00 + 49e: 01 00 + 4a0: 5f 28 04 00 + 4a4: 00 2c + 4a6: 04 00 + 4a8: 00 01 + 4aa: 00 5b + 4ac: 2c 04 + 4ae: 00 00 + 4b0: 34 04 + 4b2: 00 00 + 4b4: 01 00 + 4b6: 5f 00 00 00 + 4ba: 00 00 + 4bc: 00 00 + 4be: 00 f8 + 4c0: 01 00 + 4c2: 00 20 + 4c4: 02 00 + 4c6: 00 01 + 4c8: 00 5b + 4ca: 18 03 + 4cc: 00 00 + 4ce: 38 03 + 4d0: 00 00 + 4d2: 01 00 + 4d4: 5c 00 + 4d6: 00 00 + 4d8: 00 00 + 4da: 00 00 + 4dc: 00 f0 + 4de: 00 00 + 4e0: 00 f8 + 4e2: 00 00 + 4e4: 00 01 + 4e6: 00 5a + 4e8: bc 03 + 4ea: 00 00 + 4ec: 28 04 + 4ee: 00 00 + 4f0: 01 00 + 4f2: 5a 00 + 4f4: 00 00 + 4f6: 00 00 + 4f8: 00 00 + 4fa: 00 4c + 4fc: 01 00 + 4fe: 00 50 + 500: 01 00 + 502: 00 02 + 504: 00 31 + 506: 9f 50 01 00 + 50a: 00 d8 + 50c: 01 00 + 50e: 00 01 + 510: 00 5b + 512: 98 02 + 514: 00 00 + 516: 9c 02 + 518: 00 00 + 51a: 01 00 + 51c: 5b 00 00 00 + 520: 00 00 + 522: 00 00 + 524: 00 f0 + 526: 01 00 + 528: 00 04 + 52a: 02 00 + 52c: 00 01 + 52e: 00 5e + 530: 00 03 + 532: 00 00 + 534: 24 03 + 536: 00 00 + 538: 01 00 + 53a: 5e 00 + 53c: 00 00 + 53e: 00 00 + 540: 00 00 + 542: 00 50 + 544: 00 00 + 546: 00 80 + 548: 00 00 + 54a: 00 01 + 54c: 00 5d + 54e: 44 01 + 550: 00 00 + 552: 50 01 + 554: 00 00 + 556: 01 00 + 558: 5d f0 + 55a: 01 00 + 55c: 00 2c + 55e: 02 00 + 560: 00 01 + 562: 00 5d + 564: d4 02 + 566: 00 00 + 568: ec 02 + 56a: 00 00 + 56c: 01 00 + 56e: 5b 00 03 00 + 572: 00 1c + 574: 04 00 + 576: 00 01 + 578: 00 5b + ... + 582: 24 00 + 584: 00 00 + 586: 54 00 + 588: 00 00 + 58a: 01 00 + 58c: 5c 54 + 58e: 00 00 + 590: 00 60 + 592: 00 00 + 594: 00 09 + 596: 00 7c + 598: 00 7d + 59a: 00 08 + 59c: ff 1a 24 9f + 5a0: 60 00 + 5a2: 00 00 + 5a4: f0 00 + 5a6: 00 00 + 5a8: 01 00 + 5aa: 60 f8 + 5ac: 00 00 + 5ae: 00 0c + 5b0: 01 00 + 5b2: 00 01 + 5b4: 00 5c + ... + 5be: 38 00 + 5c0: 00 00 + 5c2: 4c 00 + 5c4: 00 00 + 5c6: 01 00 + 5c8: 5e 00 + 5ca: 00 00 + 5cc: 00 00 + 5ce: 00 00 + 5d0: 00 6c + 5d2: 00 00 + 5d4: 00 f0 + 5d6: 00 00 + 5d8: 00 01 + 5da: 00 61 + ... + 5e4: 78 00 + 5e6: 00 00 + 5e8: d0 00 + 5ea: 00 00 + 5ec: 01 00 + 5ee: 5c d0 + 5f0: 00 00 + 5f2: 00 f0 + 5f4: 00 00 + 5f6: 00 07 + 5f8: 00 80 + 5fa: 00 40 + 5fc: 24 40 + 5fe: 25 9f + ... + 608: 80 00 + 60a: 00 00 + 60c: 9c 00 + 60e: 00 00 + 610: 01 00 + 612: 5f 9c 00 00 + 616: 00 ec + 618: 00 00 + 61a: 00 01 + 61c: 00 5a + ... + 626: c0 00 + 628: 00 00 + 62a: dc 00 + 62c: 00 00 + 62e: 01 00 + 630: 5e dc + 632: 00 00 + 634: 00 f0 + 636: 00 00 + 638: 00 01 + 63a: 00 5c + ... + 644: 80 00 + 646: 00 00 + 648: 8c 00 + 64a: 00 00 + 64c: 01 00 + 64e: 5d 90 + 650: 00 00 + 652: 00 98 + 654: 00 00 + 656: 00 01 + 658: 00 5e + 65a: 98 00 + 65c: 00 00 + 65e: 9c 00 + 660: 00 00 + 662: 08 00 + 664: 76 00 + 666: 40 25 + 668: 7d 00 + 66a: 21 9f + 66c: 9c 00 + 66e: 00 00 + 670: c0 00 + 672: 00 00 + 674: 01 00 + 676: 5e 00 + 678: 00 00 + 67a: 00 00 + 67c: 00 00 + 67e: 00 b4 + 680: 00 00 + 682: 00 c4 + 684: 00 00 + 686: 00 01 + 688: 00 5f + 68a: cc 00 + 68c: 00 00 + 68e: d8 00 + 690: 00 00 + 692: 01 00 + 694: 56 00 + 696: 00 00 + 698: 00 00 + 69a: 00 00 + 69c: 00 88 + 69e: 00 00 + 6a0: 00 cc + 6a2: 00 00 + 6a4: 00 01 + 6a6: 00 5b + 6a8: cc 00 + 6aa: 00 00 + 6ac: f0 00 + 6ae: 00 00 + 6b0: 01 00 + 6b2: 5d 00 + 6b4: 00 00 + 6b6: 00 00 + 6b8: 00 00 + 6ba: 00 f4 + 6bc: 03 00 00 24 lb zero, 576(zero) + 6c0: 04 00 + 6c2: 00 01 + 6c4: 00 5c + ... + 6ce: f4 03 + 6d0: 00 00 + 6d2: 08 04 + 6d4: 00 00 + 6d6: 10 00 + 6d8: 76 00 + 6da: 0a ff + 6dc: ff 1a 7e 00 + 6e0: 0a ff + 6e2: ff 1a 40 24 + 6e6: 22 9f + 6e8: 08 04 + 6ea: 00 00 + 6ec: 10 04 + 6ee: 00 00 + 6f0: 15 00 + 6f2: 76 00 + 6f4: 0a ff + 6f6: ff 1a 76 00 + 6fa: 40 25 + 6fc: 80 00 + 6fe: 22 0a + 700: ff ff 1a 40 + 704: 24 22 + 706: 9f 00 00 00 + 70a: 00 00 + 70c: 00 00 + 70e: 00 28 + 710: 03 00 00 a8 lb zero, -1408(zero) + 714: 03 00 00 01 lb zero, 16(zero) + 718: 00 5a + 71a: a8 03 + 71c: 00 00 + 71e: cc 03 + 720: 00 00 + 722: 05 00 + 724: 76 00 + 726: 40 25 + 728: 9f 00 00 00 + 72c: 00 00 + 72e: 00 00 + 730: 00 30 + 732: 03 00 00 7c lb zero, 1984(zero) + 736: 03 00 00 01 lb zero, 16(zero) + 73a: 00 5f + 73c: 7c 03 + 73e: 00 00 + 740: cc 03 + 742: 00 00 + 744: 07 00 76 00 + 748: 40 24 + 74a: 40 25 + 74c: 9f 00 00 00 + 750: 00 00 + 752: 00 00 + 754: 00 38 + 756: 03 00 00 54 lb zero, 1344(zero) + 75a: 03 00 00 01 lb zero, 16(zero) + 75e: 00 5c + 760: 54 03 + 762: 00 00 + 764: ac 03 + 766: 00 00 + 768: 01 00 + 76a: 6c 00 + 76c: 00 00 + 76e: 00 00 + 770: 00 00 + 772: 00 70 + 774: 03 00 00 94 lb zero, -1728(zero) + 778: 03 00 00 01 lb zero, 16(zero) + 77c: 00 5e + 77e: 94 03 + 780: 00 00 + 782: b4 03 + 784: 00 00 + 786: 01 00 + 788: 5d 00 + 78a: 00 00 + 78c: 00 00 + 78e: 00 00 + 790: 00 30 + 792: 03 00 00 3c lb zero, 960(zero) + 796: 03 00 00 01 lb zero, 16(zero) + 79a: 00 5d + 79c: 44 03 + 79e: 00 00 + 7a0: 50 03 + 7a2: 00 00 + 7a4: 01 00 + 7a6: 5e 50 + 7a8: 03 00 00 54 lb zero, 1344(zero) + 7ac: 03 00 00 08 lb zero, 128(zero) + 7b0: 00 80 + 7b2: 00 40 + 7b4: 25 7d + 7b6: 00 21 + 7b8: 9f 54 03 00 + 7bc: 00 70 + 7be: 03 00 00 01 lb zero, 16(zero) + 7c2: 00 5e + ... + 7cc: 6c 03 + 7ce: 00 00 + 7d0: 74 03 + 7d2: 00 00 + 7d4: 01 00 + 7d6: 5d 84 + 7d8: 03 00 00 90 lb zero, -1792(zero) + 7dc: 03 00 00 01 lb zero, 16(zero) + 7e0: 00 5f + 7e2: 94 03 + 7e4: 00 00 + 7e6: 00 04 + 7e8: 00 00 + 7ea: 01 00 + 7ec: 5f 00 00 00 + 7f0: 00 00 + 7f2: 00 00 + 7f4: 00 44 + 7f6: 03 00 00 78 lb zero, 1920(zero) + 7fa: 03 00 00 01 lb zero, 16(zero) + 7fe: 00 6e + 800: 78 03 + 802: 00 00 + 804: c4 03 + 806: 00 00 + 808: 01 00 + 80a: 5c c4 + 80c: 03 00 00 cc lb zero, -832(zero) + 810: 03 00 00 0a lb zero, 160(zero) + 814: 00 76 + 816: 00 40 + 818: 24 40 + 81a: 25 7e + 81c: 00 1e + 81e: 9f 00 00 00 + 822: 00 00 + 824: 00 00 + 826: 00 cc + 828: 03 00 00 10 lb zero, 256(zero) + 82c: 04 00 + 82e: 00 01 + 830: 00 56 + ... + 83a: cc 03 + 83c: 00 00 + 83e: d8 03 + 840: 00 00 + 842: 06 00 + 844: 80 00 + 846: 8d 00 + 848: 1e 9f + 84a: d8 03 + 84c: 00 00 + 84e: dc 03 + 850: 00 00 + 852: 01 00 + 854: 60 dc + 856: 03 00 00 e4 lb zero, -448(zero) + 85a: 03 00 00 09 lb zero, 144(zero) + 85e: 00 8c + 860: 7f 7a 00 1a + 864: 8d 00 + 866: 1e 9f + 868: e4 03 + 86a: 00 00 + 86c: 08 04 + 86e: 00 00 + 870: 01 00 + 872: 5e 08 + 874: 04 00 + 876: 00 10 + 878: 04 00 + 87a: 00 08 + 87c: 00 76 + 87e: 00 40 + 880: 25 80 + 882: 00 22 + 884: 9f 00 00 00 + 888: 00 00 + 88a: 00 00 + 88c: 00 d0 + 88e: 03 00 00 f0 lb zero, -256(zero) + 892: 03 00 00 01 lb zero, 16(zero) + 896: 00 5d + ... + 8a0: e4 03 + 8a2: 00 00 + 8a4: f4 03 + 8a6: 00 00 + 8a8: 01 00 + 8aa: 5c 00 + 8ac: 00 00 + 8ae: 00 00 + 8b0: 00 00 + 8b2: 00 bc + 8b4: 03 00 00 d8 lb zero, -640(zero) + 8b8: 03 00 00 01 lb zero, 16(zero) + 8bc: 00 60 + 8be: d8 03 + 8c0: 00 00 + 8c2: 04 04 + 8c4: 00 00 + 8c6: 06 00 + 8c8: 8c 7f + 8ca: 7a 00 + 8cc: 1a 9f + 8ce: 04 04 + 8d0: 00 00 + 8d2: 20 04 + 8d4: 00 00 + 8d6: 06 00 + 8d8: 7a 00 + 8da: 7f 00 1a 9f + 8de: 20 04 + 8e0: 00 00 + 8e2: 24 04 + 8e4: 00 00 + 8e6: 06 00 + 8e8: 8c 7f + 8ea: 7a 00 + 8ec: 1a 9f + 8ee: 24 04 + 8f0: 00 00 + 8f2: 28 04 + 8f4: 00 00 + 8f6: 06 00 + 8f8: 7a 01 + 8fa: 8c 7f + 8fc: 1a 9f + ... + 906: c4 03 + 908: 00 00 + 90a: d0 03 + 90c: 00 00 + 90e: 01 00 + 910: 5d 00 + 912: 00 00 + 914: 00 00 + 916: 00 00 + 918: 00 c4 + 91a: 03 00 00 e4 lb zero, -448(zero) + 91e: 03 00 00 01 lb zero, 16(zero) + 922: 00 5c + 924: e4 03 + 926: 00 00 + 928: 24 04 + 92a: 00 00 + 92c: 05 00 + 92e: 7a 00 + 930: 40 25 + 932: 9f 24 04 00 + 936: 00 28 + 938: 04 00 + 93a: 00 05 + 93c: 00 7a + 93e: 01 40 + 940: 25 9f + ... + 94a: c8 03 + 94c: 00 00 + 94e: 28 04 + 950: 00 00 + 952: 01 00 + 954: 6d 00 + 956: 00 00 + 958: 00 00 + 95a: 00 00 + 95c: 00 18 + 95e: 01 00 + 960: 00 d8 + 962: 01 00 + 964: 00 01 + 966: 00 60 + 968: dc 01 + 96a: 00 00 + 96c: f0 01 + 96e: 00 00 + 970: 01 00 + 972: 60 f0 + 974: 01 00 + 976: 00 f4 + 978: 01 00 + 97a: 00 09 + 97c: 00 80 + 97e: 00 7d + 980: 00 08 + 982: ff 1a 24 9f + 986: f4 01 + 988: 00 00 + 98a: 9c 02 + 98c: 00 00 + 98e: 01 00 + 990: 60 00 + 992: 00 00 + 994: 00 00 + 996: 00 00 + 998: 00 2c + 99a: 01 00 + 99c: 00 50 + 99e: 01 00 + 9a0: 00 01 + 9a2: 00 5a + 9a4: f0 01 + 9a6: 00 00 + 9a8: 1c 02 + 9aa: 00 00 + 9ac: 01 00 + 9ae: 5a 00 + 9b0: 00 00 + 9b2: 00 00 + 9b4: 00 00 + 9b6: 00 54 + 9b8: 01 00 + 9ba: 00 d8 + 9bc: 01 00 + 9be: 00 01 + 9c0: 00 61 + ... + 9ca: 5c 01 + 9cc: 00 00 + 9ce: b8 01 + 9d0: 00 00 + 9d2: 01 00 + 9d4: 5c b8 + 9d6: 01 00 + 9d8: 00 d8 + 9da: 01 00 + 9dc: 00 07 + 9de: 00 80 + 9e0: 00 40 + 9e2: 24 40 + 9e4: 25 9f + ... + 9ee: 68 01 + 9f0: 00 00 + 9f2: 84 01 + 9f4: 00 00 + 9f6: 01 00 + 9f8: 5f 84 01 00 + 9fc: 00 d4 + 9fe: 01 00 + a00: 00 01 + a02: 00 5a + ... + a0c: a8 01 + a0e: 00 00 + a10: c4 01 + a12: 00 00 + a14: 01 00 + a16: 5e c4 + a18: 01 00 + a1a: 00 d8 + a1c: 01 00 + a1e: 00 01 + a20: 00 5c + ... + a2a: 64 01 + a2c: 00 00 + a2e: 6c 01 + a30: 00 00 + a32: 01 00 + a34: 5d 74 + a36: 01 00 + a38: 00 80 + a3a: 01 00 + a3c: 00 01 + a3e: 00 5e + a40: 80 01 + a42: 00 00 + a44: 84 01 + a46: 00 00 + a48: 08 00 + a4a: 76 00 + a4c: 40 25 + a4e: 7d 00 + a50: 21 9f + a52: 84 01 + a54: 00 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af2: 3c 02 + af4: 00 00 + af6: 9c 02 + af8: 00 00 + afa: 01 00 + afc: 5a 00 + afe: 00 00 + b00: 00 00 + b02: 00 00 + b04: 00 60 + b06: 02 00 + b08: 00 7c + b0a: 02 00 + b0c: 00 01 + b0e: 00 5d + b10: 7c 02 + b12: 00 00 + b14: 9c 02 + b16: 00 00 + b18: 01 00 + b1a: 5e 00 + b1c: 00 00 + b1e: 00 00 + b20: 00 00 + b22: 00 18 + b24: 02 00 + b26: 00 24 + b28: 02 00 + b2a: 00 01 + b2c: 00 5e + b2e: 2c 02 + b30: 00 00 + b32: 38 02 + b34: 00 00 + b36: 01 00 + b38: 5e 3c + b3a: 02 00 + b3c: 00 50 + b3e: 02 00 + b40: 00 01 + b42: 00 5e + b44: 50 02 + b46: 00 00 + b48: 60 02 + b4a: 00 00 + b4c: 01 00 + b4e: 5d 00 + b50: 00 00 + b52: 00 00 + b54: 00 00 + b56: 00 54 + b58: 02 00 + b5a: 00 64 + b5c: 02 00 + b5e: 00 01 + b60: 00 5e + b62: 6c 02 + b64: 00 00 + b66: 78 02 + b68: 00 00 + b6a: 01 00 + b6c: 5f 7c 02 00 + b70: 00 9c + b72: 02 00 + b74: 00 01 + b76: 00 5f + ... + b80: 2c 02 + b82: 00 00 + b84: 50 02 + b86: 00 00 + b88: 01 00 + b8a: 5d 50 + b8c: 02 00 + b8e: 00 68 + b90: 02 00 + b92: 00 06 + b94: 00 7f + b96: 00 7b + b98: 00 1e + b9a: 9f 68 02 00 + b9e: 00 9c + ba0: 02 00 + ba2: 00 01 + ba4: 00 61 + ... + bae: a0 02 + bb0: 00 00 + bb2: bc 02 + bb4: 00 00 + bb6: 01 00 + bb8: 5a bc + bba: 02 00 + bbc: 00 ec + bbe: 02 00 + bc0: 00 01 + bc2: 00 5d + bc4: ec 02 + bc6: 00 00 + bc8: 00 03 + bca: 00 00 + bcc: 01 00 + bce: 5a 00 + bd0: 03 00 00 08 lb zero, 128(zero) + bd4: 03 00 00 01 lb zero, 16(zero) + bd8: 00 5d + ... + be2: b4 02 + be4: 00 00 + be6: d4 02 + be8: 00 00 + bea: 01 00 + bec: 5b 00 00 00 + ... + bf8: 00 70 + bfa: 00 00 + bfc: 00 06 + bfe: 00 5a + c00: 93 04 5b 93 addi s1, s6, -1739 + c04: 04 70 + c06: 00 00 + c08: 00 e0 + c0a: 00 00 + c0c: 00 06 + c0e: 00 f3 + c10: 03 f5 0a 25 + c14: 9f e0 00 00 + c18: 00 34 + c1a: 01 00 + c1c: 00 06 + c1e: 00 5a + c20: 93 04 5b 93 addi s1, s6, -1739 + c24: 04 34 + c26: 01 00 + c28: 00 a8 + c2a: 01 00 + c2c: 00 06 + c2e: 00 f3 + c30: 03 f5 0a 25 + c34: 9f a8 01 00 + c38: 00 d0 + c3a: 01 00 + c3c: 00 06 + c3e: 00 5a + c40: 93 04 5b 93 addi s1, s6, -1739 + c44: 04 d0 + c46: 01 00 + c48: 00 48 + c4a: 02 00 + c4c: 00 06 + c4e: 00 f3 + c50: 03 f5 0a 25 + c54: 9f 48 02 00 + c58: 00 98 + c5a: 02 00 + c5c: 00 06 + c5e: 00 5a + c60: 93 04 5b 93 addi s1, s6, -1739 + c64: 04 98 + c66: 02 00 + c68: 00 a8 + c6a: 02 00 + c6c: 00 06 + c6e: 00 f3 + c70: 03 f5 0a 25 + c74: 9f a8 02 00 + c78: 00 f4 + c7a: 02 00 + c7c: 00 06 + c7e: 00 5a + c80: 93 04 5b 93 addi s1, s6, -1739 + c84: 04 f4 + c86: 02 00 + c88: 00 10 + c8a: 04 00 + c8c: 00 06 + c8e: 00 f3 + c90: 03 f5 0a 25 + c94: 9f 00 00 00 + ... + ca0: 00 68 + ca2: 00 00 + ca4: 00 06 + ca6: 00 5c + ca8: 93 04 5d 93 addi s1, s10, -1739 + cac: 04 68 + cae: 00 00 + cb0: 00 e0 + cb2: 00 00 + cb4: 00 06 + cb6: 00 f3 + cb8: 03 f5 0c 25 + cbc: 9f e0 00 00 + cc0: 00 fc + cc2: 00 00 + cc4: 00 06 + cc6: 00 5c + cc8: 93 04 5d 93 addi s1, s10, -1739 + ccc: 04 fc + cce: 00 00 + cd0: 00 48 + cd2: 02 00 + cd4: 00 06 + cd6: 00 f3 + cd8: 03 f5 0c 25 + cdc: 9f 48 02 00 + ce0: 00 f0 + ce2: 02 00 + ce4: 00 06 + ce6: 00 5c + ce8: 93 04 5d 93 addi s1, s10, -1739 + cec: 04 f0 + cee: 02 00 + cf0: 00 10 + cf2: 04 00 + cf4: 00 06 + cf6: 00 f3 + cf8: 03 f5 0c 25 + cfc: 9f 00 00 00 + d00: 00 00 + d02: 00 00 + d04: 00 a4 + d06: 02 00 + d08: 00 a8 + d0a: 02 00 + d0c: 00 06 + d0e: 00 5f + d10: 93 04 60 93 addi s1, zero, -1738 + d14: 04 0c + d16: 04 00 + d18: 00 10 + d1a: 04 00 + d1c: 00 06 + d1e: 00 5a + d20: 93 04 5b 93 addi s1, s6, -1739 + d24: 04 00 + ... + d2e: 00 00 + d30: 00 dc + d32: 00 00 + d34: 00 06 + d36: 00 f2 + d38: 6f 1e 00 00 jal t3, 4096 + d3c: 00 e0 + d3e: 00 00 + d40: 00 10 + d42: 04 00 + d44: 00 06 + d46: 00 f2 + d48: 6f 1e 00 00 jal t3, 4096 + ... + d58: 00 18 + d5a: 00 00 + d5c: 00 06 + d5e: 00 5c + d60: 93 04 5d 93 addi s1, s10, -1739 + d64: 04 18 + d66: 00 00 + d68: 00 34 + d6a: 00 00 + d6c: 00 06 + d6e: 00 5c + d70: 93 04 5e 93 addi s1, t3, -1739 + d74: 04 e0 + d76: 00 00 + d78: 00 e8 + d7a: 00 00 + d7c: 00 06 + d7e: 00 5c + d80: 93 04 5e 93 addi s1, t3, -1739 + d84: 04 f4 + d86: 00 00 + d88: 00 fc + d8a: 00 00 + d8c: 00 06 + d8e: 00 5c + d90: 93 04 5e 93 addi s1, t3, -1739 + d94: 04 fc + d96: 00 00 + d98: 00 00 + d9a: 01 00 + d9c: 00 06 + d9e: 00 61 + da0: 93 04 5e 93 addi s1, t3, -1739 + da4: 04 48 + da6: 02 00 + da8: 00 c4 + daa: 02 00 + dac: 00 06 + dae: 00 5c + db0: 93 04 5d 93 addi s1, s10, -1739 + db4: 04 00 + ... + dbe: 00 00 + dc0: 00 54 + dc2: 00 00 + dc4: 00 06 + dc6: 00 5a + dc8: 93 04 5b 93 addi s1, s6, -1739 + dcc: 04 54 + dce: 00 00 + dd0: 00 60 + dd2: 00 00 + dd4: 00 06 + dd6: 00 5a + dd8: 93 04 60 93 addi s1, zero, -1738 + ddc: 04 e0 + dde: 00 00 + de0: 00 34 + de2: 01 00 + de4: 00 06 + de6: 00 5a + de8: 93 04 5b 93 addi s1, s6, -1739 + dec: 04 a8 + dee: 01 00 + df0: 00 d0 + df2: 01 00 + df4: 00 06 + df6: 00 5a + df8: 93 04 5b 93 addi s1, s6, -1739 + dfc: 04 48 + dfe: 02 00 + e00: 00 94 + e02: 02 00 + e04: 00 06 + e06: 00 5a + e08: 93 04 5b 93 addi s1, s6, -1739 + e0c: 04 94 + e0e: 02 00 + e10: 00 98 + e12: 02 00 + e14: 00 06 + e16: 00 5a + e18: 93 04 60 93 addi s1, zero, -1738 + e1c: 04 a8 + e1e: 02 00 + e20: 00 d8 + e22: 02 00 + e24: 00 06 + e26: 00 5a + e28: 93 04 5b 93 addi s1, s6, -1739 + e2c: 04 d8 + e2e: 02 00 + e30: 00 dc + e32: 02 00 + e34: 00 06 + e36: 00 5a + e38: 93 04 60 93 addi s1, zero, -1738 + e3c: 04 00 + e3e: 00 00 + e40: 00 00 + e42: 00 00 + e44: 00 04 + e46: 00 00 + e48: 00 5c + e4a: 00 00 + e4c: 00 01 + e4e: 00 5c + e50: 5c 00 + e52: 00 00 + e54: dc 00 + e56: 00 00 + e58: 01 00 + e5a: 61 e0 + e5c: 00 00 + e5e: 00 fc + e60: 00 00 + e62: 00 01 + e64: 00 5c + e66: fc 00 + e68: 00 00 + e6a: 48 02 + e6c: 00 00 + e6e: 01 00 + e70: 61 48 + e72: 02 00 + e74: 00 dc + e76: 03 00 00 01 lb zero, 16(zero) + e7a: 00 5c + ... + e84: 08 00 + e86: 00 00 + e88: 18 00 + e8a: 00 00 + e8c: 01 00 + e8e: 5d 18 + e90: 00 00 + e92: 00 34 + e94: 00 00 + e96: 00 01 + e98: 00 5e + e9a: e0 00 + e9c: 00 00 + e9e: e8 00 + ea0: 00 00 + ea2: 01 00 + ea4: 5e f4 + ea6: 00 00 + ea8: 00 14 + eaa: 01 00 + eac: 00 01 + eae: 00 5e + eb0: a8 01 + eb2: 00 00 + eb4: b0 01 + eb6: 00 00 + eb8: 01 00 + eba: 5e 48 + ebc: 02 00 + ebe: 00 c4 + ec0: 02 00 + ec2: 00 01 + ec4: 00 5d + ec6: c8 02 + ec8: 00 00 + eca: 10 04 + ecc: 00 00 + ece: 01 00 + ed0: 6e 00 + ed2: 00 00 + ed4: 00 00 + ed6: 00 00 + ed8: 00 0c + eda: 00 00 + edc: 00 64 + ede: 00 00 + ee0: 00 01 + ee2: 00 5a + ee4: 64 00 + ee6: 00 00 + ee8: a8 00 + eea: 00 00 + eec: 01 00 + eee: 5f d4 00 00 + ef2: 00 dc + ef4: 00 00 + ef6: 00 01 + ef8: 00 5f + efa: e0 00 + efc: 00 00 + efe: 34 01 + f00: 00 00 + f02: 01 00 + f04: 5a a4 + f06: 01 00 + f08: 00 a8 + f0a: 01 00 + f0c: 00 01 + f0e: 00 5f + f10: a8 01 + f12: 00 00 + f14: d0 01 + f16: 00 00 + f18: 01 00 + f1a: 5a 48 + f1c: 02 00 + f1e: 00 98 + f20: 02 00 + f22: 00 01 + f24: 00 5a + f26: 9c 02 + f28: 00 00 + f2a: a8 02 + f2c: 00 00 + f2e: 01 00 + f30: 5f a8 02 00 + f34: 00 f4 + f36: 03 00 00 01 lb zero, 16(zero) + f3a: 00 5a + f3c: fc 03 + f3e: 00 00 + f40: 04 04 + f42: 00 00 + f44: 01 00 + f46: 5e 00 + f48: 00 00 + f4a: 00 00 + f4c: 00 00 + f4e: 00 10 + f50: 00 00 + f52: 00 54 + f54: 00 00 + f56: 00 01 + f58: 00 5b + f5a: 54 00 + f5c: 00 00 + f5e: 7c 00 + f60: 00 00 + f62: 01 00 + f64: 60 e0 + f66: 00 00 + f68: 00 4c + f6a: 01 00 + f6c: 00 01 + f6e: 00 5b + f70: a8 01 + f72: 00 00 + f74: d8 01 + f76: 00 00 + f78: 01 00 + f7a: 5b d8 01 00 + f7e: 00 dc + f80: 01 00 + f82: 00 01 + f84: 00 60 + f86: dc 01 + f88: 00 00 + f8a: 18 02 + f8c: 00 00 + f8e: 01 00 + f90: 6c 44 + f92: 02 00 + f94: 00 94 + f96: 02 00 + f98: 00 01 + f9a: 00 5b + f9c: 94 02 + f9e: 00 00 + fa0: a8 02 + fa2: 00 00 + fa4: 01 00 + fa6: 60 a8 + fa8: 02 00 + faa: 00 d8 + fac: 02 00 + fae: 00 01 + fb0: 00 5b + fb2: d8 02 + fb4: 00 00 + fb6: dc 02 + fb8: 00 00 + fba: 01 00 + fbc: 60 f0 + fbe: 02 00 + fc0: 00 30 + fc2: 03 00 00 01 lb zero, 16(zero) + fc6: 00 60 + fc8: 74 03 + fca: 00 00 + fcc: f8 03 + fce: 00 00 + fd0: 01 00 + fd2: 5b fc 03 00 + fd6: 00 0c + fd8: 04 00 + fda: 00 01 + fdc: 00 5b + ... + fe6: c4 01 + fe8: 00 00 + fea: ec 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+ 132c: 00 00 + 132e: c4 02 + 1330: 00 00 + 1332: 01 00 + 1334: 5d 00 + 1336: 00 00 + 1338: 00 00 + 133a: 00 00 + 133c: 00 60 + 133e: 02 00 + 1340: 00 7c + 1342: 02 00 + 1344: 00 01 + 1346: 00 5e + ... + 1350: 90 02 + 1352: 00 00 + 1354: 9c 02 + 1356: 00 00 + 1358: 01 00 + 135a: 5f 00 00 00 + 135e: 00 00 + 1360: 00 00 + 1362: 00 cc + 1364: 03 00 00 e0 lb zero, -512(zero) + 1368: 03 00 00 01 lb zero, 16(zero) + 136c: 00 5e + 136e: e8 03 + 1370: 00 00 + 1372: ec 03 + 1374: 00 00 + 1376: 01 00 + 1378: 5c ec + 137a: 03 00 00 f0 lb zero, -256(zero) + 137e: 03 00 00 01 lb zero, 16(zero) + 1382: 00 5e + ... + 138c: f4 02 + 138e: 00 00 + 1390: 8c 03 + 1392: 00 00 + 1394: 01 00 + 1396: 5e 8c + 1398: 03 00 00 10 lb zero, 256(zero) + 139c: 04 00 + 139e: 00 05 + 13a0: 00 8e + 13a2: 00 40 + 13a4: 25 9f + ... + 13ae: f4 02 + 13b0: 00 00 + 13b2: 44 03 + 13b4: 00 00 + 13b6: 01 00 + 13b8: 5b 44 03 00 + 13bc: 00 10 + 13be: 04 00 + 13c0: 00 07 + 13c2: 00 8e + 13c4: 00 40 + 13c6: 24 40 + 13c8: 25 9f + ... + 13d2: f8 02 + 13d4: 00 00 + 13d6: 14 03 + 13d8: 00 00 + 13da: 01 00 + 13dc: 5f 14 03 00 + 13e0: 00 6c + 13e2: 03 00 00 01 lb zero, 16(zero) + 13e6: 00 61 + ... + 13f0: 38 03 + 13f2: 00 00 + 13f4: 54 03 + 13f6: 00 00 + 13f8: 01 00 + 13fa: 5d 54 + 13fc: 03 00 00 78 lb zero, 1920(zero) + 1400: 03 00 00 01 lb zero, 16(zero) + 1404: 00 5f + ... + 140e: f4 02 + 1410: 00 00 + 1412: fc 02 + 1414: 00 00 + 1416: 01 00 + 1418: 61 04 + 141a: 03 00 00 10 lb zero, 256(zero) + 141e: 03 00 00 01 lb zero, 16(zero) + 1422: 00 5d + 1424: 14 03 + 1426: 00 00 + 1428: 38 03 + 142a: 00 00 + 142c: 01 00 + 142e: 5d 00 + 1430: 00 00 + 1432: 00 00 + 1434: 00 00 + 1436: 00 2c + 1438: 03 00 00 3c lb zero, 960(zero) + 143c: 03 00 00 01 lb zero, 16(zero) + 1440: 00 6d + 1442: 44 03 + 1444: 00 00 + 1446: 50 03 + 1448: 00 00 + 144a: 01 00 + 144c: 6d 54 + 144e: 03 00 00 68 lb zero, 1664(zero) + 1452: 03 00 00 01 lb zero, 16(zero) + 1456: 00 6d + 1458: 68 03 + 145a: 00 00 + 145c: f8 03 + 145e: 00 00 + 1460: 01 00 + 1462: 5b 00 00 00 + 1466: 00 00 + 1468: 00 00 + 146a: 00 04 + 146c: 03 00 00 2c lb zero, 704(zero) + 1470: 03 00 00 01 lb zero, 16(zero) + 1474: 00 6d + 1476: 2c 03 + 1478: 00 00 + 147a: 44 03 + 147c: 00 00 + 147e: 06 00 + 1480: 7b 00 7f 00 + 1484: 1e 9f + 1486: 44 03 + 1488: 00 00 + 148a: 68 03 + 148c: 00 00 + 148e: 01 00 + 1490: 5b 68 03 00 + 1494: 00 80 + 1496: 03 00 00 0a lb zero, 160(zero) + 149a: 00 8e + 149c: 00 40 + 149e: 24 40 + 14a0: 25 7d + 14a2: 00 1e + 14a4: 9f 00 00 00 + 14a8: 00 00 + 14aa: 00 00 + 14ac: 00 8c + 14ae: 03 00 00 c4 lb zero, -960(zero) + 14b2: 03 00 00 01 lb zero, 16(zero) + 14b6: 00 5e + ... + 14c0: a4 03 + 14c2: 00 00 + 14c4: bc 03 + 14c6: 00 00 + 14c8: 01 00 + 14ca: 5d 00 + 14cc: 00 00 + 14ce: 00 00 + 14d0: 00 00 + 14d2: 00 90 + 14d4: 03 00 00 b0 lb zero, -1280(zero) + 14d8: 03 00 00 01 lb zero, 16(zero) + 14dc: 00 5f + ... + 14e6: 98 03 + 14e8: 00 00 + 14ea: c8 03 + 14ec: 00 00 + 14ee: 01 00 + 14f0: 61 00 + 14f2: 00 00 + 14f4: 00 00 + 14f6: 00 00 + 14f8: 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2210: 00 00 + 2212: 01 00 + 2214: 61 08 + 2216: 05 00 + 2218: 00 0c + 221a: 05 00 + 221c: 00 01 + 221e: 00 5d + 2220: 0c 05 + 2222: 00 00 + 2224: 14 05 + 2226: 00 00 + 2228: 01 00 + 222a: 61 b4 + 222c: 08 00 + 222e: 00 b8 + 2230: 08 00 + 2232: 00 01 + 2234: 00 61 + ... + 223e: 7c 03 + 2240: 00 00 + 2242: f8 03 + 2244: 00 00 + 2246: 01 00 + 2248: 55 b4 + 224a: 04 00 + 224c: 00 18 + 224e: 05 00 + 2250: 00 01 + 2252: 00 56 + 2254: b4 08 + 2256: 00 00 + 2258: c0 08 + 225a: 00 00 + 225c: 01 00 + 225e: 56 00 + 2260: 00 00 + 2262: 00 00 + 2264: 00 00 + 2266: 00 8c + 2268: 03 00 00 f0 lb zero, -256(zero) + 226c: 03 00 00 01 lb zero, 16(zero) + 2270: 00 5f + 2272: f0 03 + 2274: 00 00 + 2276: 08 04 + 2278: 00 00 + 227a: 28 00 + 227c: 8f 00 77 00 + 2280: 1a 76 + 2282: 00 1e + 2284: 77 00 1a 8f + 2288: 00 77 + 228a: 00 1a + 228c: 8d 00 + 228e: 1e 8f + 2290: 00 77 + 2292: 00 1a + 2294: 76 00 + 2296: 1e 40 + 2298: 25 22 + 229a: 83 00 22 77 lb ra, 1906(tp) + 229e: 00 1a + 22a0: 40 24 + 22a2: 22 9f + 22a4: cc 04 + 22a6: 00 00 + 22a8: 18 05 + 22aa: 00 00 + 22ac: 01 00 + 22ae: 5a b4 + 22b0: 08 00 + 22b2: 00 c0 + 22b4: 08 00 + 22b6: 00 01 + 22b8: 00 5a + ... + 22c2: b0 02 + 22c4: 00 00 + 22c6: a8 04 + 22c8: 00 00 + 22ca: 01 00 + 22cc: 5a 00 + 22ce: 00 00 + 22d0: 00 00 + 22d2: 00 00 + 22d4: 00 b0 + 22d6: 02 00 + 22d8: 00 44 + 22da: 04 00 + 22dc: 00 01 + 22de: 00 6c + 22e0: 44 04 + 22e2: 00 00 + 22e4: 04 05 + 22e6: 00 00 + 22e8: 07 00 80 00 + 22ec: 40 24 + 22ee: 40 25 + 22f0: 9f b4 08 00 + 22f4: 00 c0 + 22f6: 08 00 + 22f8: 00 07 + 22fa: 00 80 + 22fc: 00 40 + 22fe: 24 40 + 2300: 25 9f + ... + 230a: b0 02 + 230c: 00 00 + 230e: d4 02 + 2310: 00 00 + 2312: 01 00 + 2314: 56 d4 + 2316: 02 00 + 2318: 00 2c + 231a: 03 00 00 01 lb zero, 16(zero) + 231e: 00 6f + ... + 2328: ec 02 + 232a: 00 00 + 232c: 14 03 + 232e: 00 00 + 2330: 01 00 + 2332: 6d 14 + 2334: 03 00 00 38 lb zero, 896(zero) + 2338: 03 00 00 01 lb zero, 16(zero) + 233c: 00 56 + ... + 2346: b0 02 + 2348: 00 00 + 234a: b8 02 + 234c: 00 00 + 234e: 06 00 + 2350: 87 00 7a 00 + 2354: 1d 9f + 2356: b8 02 + 2358: 00 00 + 235a: c4 02 + 235c: 00 00 + 235e: 01 00 + 2360: 67 c8 02 00 + 2364: 00 d0 + 2366: 02 00 + 2368: 00 01 + 236a: 00 5f + 236c: d0 02 + 236e: 00 00 + 2370: d4 02 + 2372: 00 00 + 2374: 08 00 + 2376: 83 00 40 25 lb ra, 596(zero) + 237a: 87 00 21 9f + 237e: d4 02 + 2380: 00 00 + 2382: f8 02 + 2384: 00 00 + 2386: 01 00 + 2388: 5f 00 00 00 + 238c: 00 00 + 238e: 00 00 + 2390: 00 e8 + 2392: 02 00 + 2394: 00 f8 + 2396: 02 00 + 2398: 00 06 + 239a: 00 7f + 239c: 00 7a + 239e: 00 1d + 23a0: 9f f8 02 00 + 23a4: 00 04 + 23a6: 03 00 00 01 lb zero, 16(zero) + 23aa: 00 5f + 23ac: 08 03 + 23ae: 00 00 + 23b0: 10 03 + 23b2: 00 00 + 23b4: 01 00 + 23b6: 5f 14 03 00 + 23ba: 00 28 + 23bc: 03 00 00 01 lb zero, 16(zero) + 23c0: 00 5f + 23c2: 28 03 + 23c4: 00 00 + 23c6: ac 03 + 23c8: 00 00 + 23ca: 01 00 + 23cc: 5e 00 + 23ce: 00 00 + 23d0: 00 00 + 23d2: 00 00 + 23d4: 00 c0 + 23d6: 02 00 + 23d8: 00 28 + 23da: 03 00 00 01 lb zero, 16(zero) + 23de: 00 5e + 23e0: 28 03 + 23e2: 00 00 + 23e4: 44 03 + 23e6: 00 00 + 23e8: 06 00 + 23ea: 8c 00 + 23ec: 8d 00 + 23ee: 1e 9f + ... + 23f8: 4c 03 + 23fa: 00 00 + 23fc: 88 03 + 23fe: 00 00 + 2400: 01 00 + 2402: 58 88 + 2404: 03 00 00 98 lb zero, -1664(zero) + 2408: 03 00 00 09 lb zero, 144(zero) + 240c: 00 8f + 240e: 00 77 + 2410: 00 1a + 2412: 76 00 + 2414: 1e 9f + 2416: 98 03 + 2418: 00 00 + 241a: 9c 03 + 241c: 00 00 + 241e: 09 00 + 2420: 78 00 + 2422: 77 00 1a 76 + 2426: 00 1e + 2428: 9f 9c 03 00 + 242c: 00 08 + 242e: 04 00 + 2430: 00 09 + 2432: 00 8f + 2434: 00 77 + 2436: 00 1a + 2438: 76 00 + 243a: 1e 9f + ... + 2444: 4c 03 + 2446: 00 00 + 2448: 54 03 + 244a: 00 00 + 244c: 06 00 + 244e: 8d 00 + 2450: 8e 00 + 2452: 1e 9f + 2454: 54 03 + 2456: 00 00 + 2458: 5c 03 + 245a: 00 00 + 245c: 01 00 + 245e: 6e 5c + 2460: 03 00 00 64 lb zero, 1600(zero) + 2464: 03 00 00 09 lb zero, 144(zero) + 2468: 00 7f + 246a: 7f 8f 00 1a + 246e: 8d 00 + 2470: 1e 9f + 2472: 64 03 + 2474: 00 00 + 2476: a4 03 + 2478: 00 00 + 247a: 01 00 + 247c: 6e a4 + 247e: 03 00 00 08 lb zero, 128(zero) + 2482: 04 00 + 2484: 00 17 + 2486: 00 8f + 2488: 00 77 + 248a: 00 1a + 248c: 8d 00 + 248e: 1e 8f + 2490: 00 77 + 2492: 00 1a + 2494: 76 00 + 2496: 1e 40 + 2498: 25 22 + 249a: 83 00 22 9f lb ra, -1550(tp) + ... + 24a6: 50 03 + 24a8: 00 00 + 24aa: 18 05 + 24ac: 00 00 + 24ae: 01 00 + 24b0: 63 b4 08 00 + 24b4: 00 c0 + 24b6: 08 00 + 24b8: 00 01 + 24ba: 00 63 + ... + 24c4: 64 03 + 24c6: 00 00 + 24c8: 7c 03 + 24ca: 00 00 + 24cc: 01 00 + 24ce: 55 00 + 24d0: 00 00 + 24d2: 00 00 + 24d4: 00 00 + 24d6: 00 34 + 24d8: 03 00 00 08 lb zero, 128(zero) + 24dc: 04 00 + 24de: 00 01 + 24e0: 00 6f + ... + 24ea: 40 03 + 24ec: 00 00 + 24ee: 00 05 + 24f0: 00 00 + 24f2: 01 00 + 24f4: 61 b4 + 24f6: 08 00 + 24f8: 00 c0 + 24fa: 08 00 + 24fc: 00 01 + 24fe: 00 61 + ... + 2508: 40 03 + 250a: 00 00 + 250c: 64 03 + 250e: 00 00 + 2510: 01 00 + 2512: 55 64 + 2514: 03 00 00 98 lb zero, -1664(zero) + 2518: 03 00 00 05 lb zero, 80(zero) + 251c: 00 8f + 251e: 00 40 + 2520: 25 9f + 2522: 98 03 + 2524: 00 00 + 2526: 9c 03 + 2528: 00 00 + 252a: 05 00 + 252c: 78 00 + 252e: 40 25 + 2530: 9f 9c 03 00 + 2534: 00 08 + 2536: 04 00 + 2538: 00 05 + 253a: 00 8f + 253c: 00 40 + 253e: 25 9f + ... + 2548: 44 03 + 254a: 00 00 + 254c: 94 04 + 254e: 00 00 + 2550: 01 00 + 2552: 6d 94 + 2554: 04 00 + 2556: 00 00 + 2558: 05 00 + 255a: 00 05 + 255c: 00 81 + 255e: 00 40 + 2560: 25 9f + 2562: b4 08 + 2564: 00 00 + 2566: c0 08 + 2568: 00 00 + 256a: 05 00 + 256c: 81 00 + 256e: 40 25 + 2570: 9f 00 00 00 + 2574: 00 00 + 2576: 00 00 + 2578: 00 b0 + 257a: 03 00 00 cc lb zero, -832(zero) + 257e: 03 00 00 01 lb zero, 16(zero) + 2582: 00 5d + ... + 258c: d8 03 + 258e: 00 00 + 2590: dc 03 + 2592: 00 00 + 2594: 01 00 + 2596: 5d 00 + 2598: 00 00 + 259a: 00 00 + 259c: 00 00 + 259e: 00 e0 + 25a0: 03 00 00 88 lb zero, -1920(zero) + 25a4: 04 00 + 25a6: 00 01 + 25a8: 00 6e + ... + 25b2: f4 03 + 25b4: 00 00 + 25b6: a8 04 + 25b8: 00 00 + 25ba: 01 00 + 25bc: 5a 00 + 25be: 00 00 + 25c0: 00 00 + 25c2: 00 00 + 25c4: 00 f4 + 25c6: 03 00 00 44 lb zero, 1088(zero) + 25ca: 04 00 + 25cc: 00 01 + 25ce: 00 6c + 25d0: 44 04 + 25d2: 00 00 + 25d4: 04 05 + 25d6: 00 00 + 25d8: 07 00 80 00 + 25dc: 40 24 + 25de: 40 25 + 25e0: 9f b4 08 00 + 25e4: 00 c0 + 25e6: 08 00 + 25e8: 00 07 + 25ea: 00 80 + 25ec: 00 40 + 25ee: 24 40 + 25f0: 25 9f + ... + 25fa: f8 03 + 25fc: 00 00 + 25fe: 1c 04 + 2600: 00 00 + 2602: 01 00 + 2604: 55 1c + 2606: 04 00 + 2608: 00 70 + 260a: 04 00 + 260c: 00 01 + 260e: 00 5d + ... + 2618: 34 04 + 261a: 00 00 + 261c: 5c 04 + 261e: 00 00 + 2620: 01 00 + 2622: 6f 5c 04 00 jal s8, 282624 + 2626: 00 78 + 2628: 04 00 + 262a: 00 01 + 262c: 00 5f + ... + 2636: f4 03 + 2638: 00 00 + 263a: 00 04 + 263c: 00 00 + 263e: 06 00 + 2640: 7e 00 + 2642: 7a 00 + 2644: 1d 9f + 2646: 00 04 + 2648: 00 00 + 264a: 0c 04 + 264c: 00 00 + 264e: 01 00 + 2650: 5e 10 + 2652: 04 00 + 2654: 00 18 + 2656: 04 00 + 2658: 00 01 + 265a: 00 5e + 265c: 1c 04 + 265e: 00 00 + 2660: 40 04 + 2662: 00 00 + 2664: 01 00 + 2666: 5e 00 + 2668: 00 00 + 266a: 00 00 + 266c: 00 00 + 266e: 00 30 + 2670: 04 00 + 2672: 00 40 + 2674: 04 00 + 2676: 00 06 + 2678: 00 7e + 267a: 00 7a + 267c: 00 1d + 267e: 9f 40 04 00 + 2682: 00 48 + 2684: 04 00 + 2686: 00 01 + 2688: 00 5e + 268a: 4c 04 + 268c: 00 00 + 268e: 58 04 + 2690: 00 00 + 2692: 01 00 + 2694: 5e 5c + 2696: 04 00 + 2698: 00 e0 + 269a: 04 00 + 269c: 00 01 + 269e: 00 5e + ... + 26a8: 08 04 + 26aa: 00 00 + 26ac: 34 04 + 26ae: 00 00 + 26b0: 01 00 + 26b2: 6f 34 04 00 jal s0, 274432 + 26b6: 00 44 + 26b8: 04 00 + 26ba: 00 06 + 26bc: 00 8c + 26be: 00 75 + 26c0: 00 1e + 26c2: 9f 44 04 00 + 26c6: 00 84 + 26c8: 04 00 + 26ca: 00 01 + 26cc: 00 6c + 26ce: 84 04 + 26d0: 00 00 + 26d2: 04 05 + 26d4: 00 00 + 26d6: 0a 00 + 26d8: 80 00 + 26da: 40 24 + 26dc: 40 25 + 26de: 8f 00 1e 9f + 26e2: b4 08 + 26e4: 00 00 + 26e6: c0 08 + 26e8: 00 00 + 26ea: 0a 00 + 26ec: 80 00 + 26ee: 40 24 + 26f0: 40 25 + 26f2: 8f 00 1e 9f + ... + 26fe: 88 04 + 2700: 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2974: 00 00 + 2976: 05 00 + 2978: 79 00 + 297a: 31 1a + 297c: 9f 14 08 00 + 2980: 00 18 + 2982: 08 00 + 2984: 00 01 + 2986: 00 5e + 2988: 18 08 + 298a: 00 00 + 298c: 1c 08 + 298e: 00 00 + 2990: 02 00 + 2992: 30 9f + ... + 299c: b8 06 + 299e: 00 00 + 29a0: 20 07 + 29a2: 00 00 + 29a4: 02 00 + 29a6: 30 9f + ... + 29b0: b8 06 + 29b2: 00 00 + 29b4: f8 06 + 29b6: 00 00 + 29b8: 01 00 + 29ba: 5f fc 06 00 + 29be: 00 14 + 29c0: 07 00 00 01 + 29c4: 00 5f + ... + 29ce: b8 06 + 29d0: 00 00 + 29d2: f8 06 + 29d4: 00 00 + 29d6: 01 00 + 29d8: 58 f8 + 29da: 06 00 + 29dc: 00 fc + 29de: 06 00 + 29e0: 00 01 + 29e2: 00 5e + 29e4: fc 06 + 29e6: 00 00 + 29e8: 14 07 + 29ea: 00 00 + 29ec: 01 00 + 29ee: 58 14 + 29f0: 07 00 00 18 + 29f4: 07 00 00 01 + 29f8: 00 5e + ... + 2a02: ec 06 + 2a04: 00 00 + 2a06: f0 06 + 2a08: 00 00 + 2a0a: 03 00 7f 04 lb zero, 71(t5) + 2a0e: 9f 00 00 00 + 2a12: 00 00 + 2a14: 00 00 + 2a16: 00 04 + 2a18: 07 00 00 0c + 2a1c: 07 00 00 03 + 2a20: 00 7f + 2a22: 08 9f + ... + 2a2c: 88 07 + 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00 00 + 3456: 04 07 + 3458: 00 00 + 345a: 02 00 + 345c: 30 9f + 345e: 04 07 + 3460: 00 00 + 3462: 24 07 + 3464: 00 00 + 3466: 01 00 + 3468: 58 2c + 346a: 07 00 00 34 + 346e: 07 00 00 01 + 3472: 00 58 + 3474: 34 07 + 3476: 00 00 + 3478: 60 07 + 347a: 00 00 + 347c: 02 00 + 347e: 30 9f + 3480: 68 07 + 3482: 00 00 + 3484: 84 07 + 3486: 00 00 + 3488: 02 00 + 348a: 30 9f + 348c: 84 07 + 348e: 00 00 + 3490: 88 07 + 3492: 00 00 + 3494: 01 00 + 3496: 58 00 + 3498: 00 00 + 349a: 00 00 + 349c: 00 00 + 349e: 00 a0 + 34a0: 00 00 + 34a2: 00 a4 + 34a4: 00 00 + 34a6: 00 01 + 34a8: 00 5a + 34aa: a4 00 + 34ac: 00 00 + 34ae: d4 00 + 34b0: 00 00 + 34b2: 01 00 + 34b4: 5e d8 + 34b6: 00 00 + 34b8: 00 e0 + 34ba: 00 00 + 34bc: 00 01 + 34be: 00 5a + 34c0: e0 00 + 34c2: 00 00 + 34c4: f0 00 + 34c6: 00 00 + 34c8: 01 00 + 34ca: 5e 00 + 34cc: 00 00 + 34ce: 00 00 + 34d0: 00 00 + 34d2: 00 cc + 34d4: 01 00 + 34d6: 00 d0 + 34d8: 01 00 + 34da: 00 01 + 34dc: 00 5a + 34de: d0 01 + 34e0: 00 00 + 34e2: 00 02 + 34e4: 00 00 + 34e6: 01 00 + 34e8: 5d 08 + 34ea: 02 00 + 34ec: 00 10 + 34ee: 02 00 + 34f0: 00 01 + 34f2: 00 5a + 34f4: 10 02 + 34f6: 00 00 + 34f8: 20 02 + 34fa: 00 00 + 34fc: 01 00 + 34fe: 5d 00 + 3500: 00 00 + 3502: 00 00 + 3504: 00 00 + 3506: 00 98 + 3508: 03 00 00 1c lb zero, 448(zero) + 350c: 04 00 + 350e: 00 01 + 3510: 00 64 + ... + 351a: 70 03 + 351c: 00 00 + 351e: a4 04 + 3520: 00 00 + 3522: 01 00 + 3524: 6d 28 + 3526: 05 00 + 3528: 00 30 + 352a: 05 00 + 352c: 00 01 + 352e: 00 6d + ... + 3538: dc 03 + 353a: 00 00 + 353c: 2c 04 + 353e: 00 00 + 3540: 01 00 + 3542: 5c 00 + 3544: 00 00 + 3546: 00 00 + 3548: 00 00 + 354a: 00 dc + 354c: 03 00 00 4c lb zero, 1216(zero) + 3550: 04 00 + 3552: 00 01 + 3554: 00 6c + ... + 355e: 08 03 + 3560: 00 00 + 3562: 2c 03 + 3564: 00 00 + 3566: 01 00 + 3568: 6d 2c + 356a: 03 00 00 4c lb zero, 1216(zero) + 356e: 03 00 00 06 lb zero, 96(zero) + 3572: 00 7f + 3574: 00 84 + 3576: 00 1e + 3578: 9f 00 00 00 + 357c: 00 00 + 357e: 00 00 + 3580: 00 08 + 3582: 03 00 00 14 lb zero, 320(zero) + 3586: 03 00 00 01 lb zero, 16(zero) + 358a: 00 56 + 358c: 14 03 + 358e: 00 00 + 3590: 1c 03 + 3592: 00 00 + 3594: 06 00 + 3596: 8c 00 + 3598: 84 00 + 359a: 1e 9f + 359c: 1c 03 + 359e: 00 00 + 35a0: 38 03 + 35a2: 00 00 + 35a4: 01 00 + 35a6: 56 38 + 35a8: 03 00 00 44 lb zero, 1088(zero) + 35ac: 03 00 00 11 lb zero, 272(zero) + 35b0: 00 8c + 35b2: 00 84 + 35b4: 00 1e + 35b6: 7f 00 84 00 + 35ba: 1e 40 + 35bc: 25 22 + 35be: 8e 00 + 35c0: 22 9f + 35c2: 44 03 + 35c4: 00 00 + 35c6: 4c 03 + 35c8: 00 00 + 35ca: 14 00 + 35cc: 8c 00 + 35ce: 84 00 + 35d0: 1e 7d + 35d2: 00 7f + 35d4: 00 1e + 35d6: 22 7f + 35d8: 00 84 + 35da: 00 1e + 35dc: 40 25 + 35de: 22 9f + ... + 35e8: 0c 03 + 35ea: 00 00 + 35ec: 44 03 + 35ee: 00 00 + 35f0: 01 00 + 35f2: 6e 44 + 35f4: 03 00 00 5c lb zero, 1472(zero) + 35f8: 03 00 00 06 lb zero, 96(zero) + 35fc: 00 7d + 35fe: 00 7f + 3600: 00 1e + 3602: 9f 00 00 00 + 3606: 00 00 + 3608: 00 00 + 360a: 00 1c + 360c: 03 00 00 14 lb zero, 320(zero) + 3610: 04 00 + 3612: 00 01 + 3614: 00 61 + ... + 361e: e8 02 + 3620: 00 00 + 3622: fc 02 + 3624: 00 00 + 3626: 01 00 + 3628: 64 00 + 362a: 00 00 + 362c: 00 00 + 362e: 00 00 + 3630: 00 f4 + 3632: 02 00 + 3634: 00 00 + 3636: 03 00 00 01 lb zero, 16(zero) + 363a: 00 5f + ... + 3644: f4 02 + 3646: 00 00 + 3648: 5c 03 + 364a: 00 00 + 364c: 01 00 + 364e: 5d 00 + 3650: 00 00 + 3652: 00 00 + 3654: 00 00 + 3656: 00 f8 + 3658: 02 00 + 365a: 00 a0 + 365c: 03 00 00 01 lb zero, 16(zero) + 3660: 00 6c + ... + 366a: 44 03 + 366c: 00 00 + 366e: 80 03 + 3670: 00 00 + 3672: 01 00 + 3674: 6e 00 + 3676: 00 00 + 3678: 00 00 + 367a: 00 00 + 367c: 00 44 + 367e: 03 00 00 4c lb zero, 1216(zero) + 3682: 03 00 00 06 lb zero, 96(zero) + 3686: 00 76 + 3688: 00 84 + 368a: 00 1e + 368c: 9f 4c 03 00 + 3690: 00 54 + 3692: 03 00 00 01 lb zero, 16(zero) + 3696: 00 64 + 3698: 5c 03 + 369a: 00 00 + 369c: 7c 03 + 369e: 00 00 + 36a0: 01 00 + 36a2: 64 00 + 36a4: 00 00 + 36a6: 00 00 + 36a8: 00 00 + 36aa: 00 48 + 36ac: 03 00 00 6c lb zero, 1728(zero) + 36b0: 03 00 00 01 lb zero, 16(zero) + 36b4: 00 6d + ... + 36be: 5c 03 + 36c0: 00 00 + 36c2: 74 03 + 36c4: 00 00 + 36c6: 01 00 + 36c8: 5d 00 + 36ca: 00 00 + 36cc: 00 00 + 36ce: 00 00 + 36d0: 00 40 + 36d2: 03 00 00 5c lb zero, 1472(zero) + 36d6: 03 00 00 01 lb zero, 16(zero) + 36da: 00 5d + ... + 36e4: 40 03 + 36e6: 00 00 + 36e8: ec 03 + 36ea: 00 00 + 36ec: 01 00 + 36ee: 56 00 + 36f0: 00 00 + 36f2: 00 00 + 36f4: 00 00 + 36f6: 00 9c + 36f8: 03 00 00 cc lb zero, -832(zero) + 36fc: 03 00 00 01 lb zero, 16(zero) + 3700: 00 6e + ... + 370a: 9c 03 + 370c: 00 00 + 370e: a0 03 + 3710: 00 00 + 3712: 06 00 + 3714: 8c 00 + 3716: 83 00 1e 9f lb ra, -1551(t3) + 371a: a0 03 + 371c: 00 00 + 371e: ac 03 + 3720: 00 00 + 3722: 01 00 + 3724: 6c b0 + 3726: 03 00 00 c8 lb zero, -896(zero) + 372a: 03 00 00 01 lb zero, 16(zero) + 372e: 00 5c + ... + 3738: a8 03 + 373a: 00 00 + 373c: c0 03 + 373e: 00 00 + 3740: 01 00 + 3742: 5f 00 00 00 + 3746: 00 00 + 3748: 00 00 + 374a: 00 a8 + 374c: 03 00 00 34 lb zero, 832(zero) + 3750: 04 00 + 3752: 00 01 + 3754: 00 55 + ... + 375e: 98 03 + 3760: 00 00 + 3762: e8 03 + 3764: 00 00 + 3766: 01 00 + 3768: 5e 00 + 376a: 00 00 + 376c: 00 00 + 376e: 00 00 + 3770: 00 98 + 3772: 03 00 00 a0 lb zero, -1536(zero) + 3776: 03 00 00 01 lb zero, 16(zero) + 377a: 00 6c + ... + 3784: dc 03 + 3786: 00 00 + 3788: 0c 04 + 378a: 00 00 + 378c: 01 00 + 378e: 5f 00 00 00 + 3792: 00 00 + 3794: 00 00 + 3796: 00 dc + 3798: 03 00 00 ec lb zero, -320(zero) + 379c: 03 00 00 06 lb zero, 96(zero) + 37a0: 00 76 + 37a2: 00 83 + 37a4: 00 1e + 37a6: 9f ec 03 00 + 37aa: 00 f0 + 37ac: 03 00 00 01 lb zero, 16(zero) + 37b0: 00 56 + 37b2: f4 03 + 37b4: 00 00 + 37b6: 48 04 + 37b8: 00 00 + 37ba: 01 00 + 37bc: 56 00 + 37be: 00 00 + 37c0: 00 00 + 37c2: 00 00 + 37c4: 00 e0 + 37c6: 03 00 00 74 lb zero, 1856(zero) + 37ca: 04 00 + 37cc: 00 01 + 37ce: 00 58 + ... + 37d8: e4 03 + 37da: 00 00 + 37dc: a4 04 + 37de: 00 00 + 37e0: 01 00 + 37e2: 6e 28 + 37e4: 05 00 + 37e6: 00 30 + 37e8: 05 00 + 37ea: 00 01 + 37ec: 00 6e + ... + 37f6: dc 03 + 37f8: 00 00 + 37fa: e8 03 + 37fc: 00 00 + 37fe: 01 00 + 3800: 5e 00 + 3802: 00 00 + 3804: 00 00 + 3806: 00 00 + 3808: 00 dc + 380a: 03 00 00 ec lb zero, -320(zero) + 380e: 03 00 00 01 lb zero, 16(zero) + 3812: 00 56 + ... + 381c: 1c 04 + 381e: 00 00 + 3820: a4 04 + 3822: 00 00 + 3824: 01 00 + 3826: 64 28 + 3828: 05 00 + 382a: 00 30 + 382c: 05 00 + 382e: 00 01 + 3830: 00 64 + ... + 383a: 20 04 + 383c: 00 00 + 383e: 24 04 + 3840: 00 00 + 3842: 11 00 + 3844: 7d 00 + 3846: 40 4b + 3848: 24 22 + 384a: 8d 00 + 384c: 40 4b + 384e: 24 22 + 3850: 2d 08 + 3852: ff 1a 9f 24 + 3856: 04 00 + 3858: 00 38 + 385a: 04 00 + 385c: 00 1f + 385e: 00 7d + 3860: 00 40 + 3862: 4b 24 22 8d + 3866: 00 40 + 3868: 4b 24 22 2d + 386c: 7e 00 + 386e: 40 4b + 3870: 24 22 + 3872: 84 00 + 3874: 40 4b + 3876: 24 22 + 3878: 2d 21 + 387a: 08 ff + 387c: 1a 9f + 387e: 38 04 + 3880: 00 00 + 3882: 3c 04 + 3884: 00 00 + 3886: 34 00 + 3888: 76 00 + 388a: 0a ff + 388c: ff 1a 40 24 + 3890: 7f 00 22 8d + 3894: 00 22 + 3896: 40 4b + 3898: 24 22 + 389a: 76 00 + 389c: 0a ff + 389e: ff 1a 40 24 + 38a2: 7f 00 22 40 + 38a6: 4b 24 22 2d + 38aa: 7e 00 + 38ac: 40 4b + 38ae: 24 22 + 38b0: 84 00 + 38b2: 40 4b + 38b4: 24 22 + 38b6: 2d 21 + 38b8: 08 ff + 38ba: 1a 9f + 38bc: 3c 04 + 38be: 00 00 + 38c0: 48 04 + 38c2: 00 00 + 38c4: 43 00 76 00 fmadd.s ft0, fa2, ft7, ft0, rne + 38c8: 0a ff + 38ca: ff 1a 40 24 + 38ce: 7f 00 22 8d + 38d2: 00 22 + 38d4: 40 4b + 38d6: 24 22 + 38d8: 76 00 + 38da: 0a ff + 38dc: ff 1a 40 24 + 38e0: 7f 00 22 40 + 38e4: 4b 24 22 2d + 38e8: 76 00 + 38ea: 0a ff + 38ec: ff 1a 40 24 + 38f0: 7f 00 22 84 + 38f4: 00 22 + 38f6: 8d 00 + 38f8: 22 40 + 38fa: 4b 24 22 84 + 38fe: 00 40 + 3900: 4b 24 22 2d + 3904: 21 08 + 3906: ff 1a 9f 00 + 390a: 00 00 + 390c: 00 00 + 390e: 00 00 + 3910: 00 2c + 3912: 04 00 + 3914: 00 44 + 3916: 04 00 + 3918: 00 01 + 391a: 00 5c + ... + 3924: 30 04 + 3926: 00 00 + 3928: 34 04 + 392a: 00 00 + 392c: 11 00 + 392e: 8f 00 40 4b + 3932: 24 22 + 3934: 8c 00 + 3936: 40 4b + 3938: 24 22 + 393a: 2d 08 + 393c: ff 1a 9f 34 + 3940: 04 00 + 3942: 00 44 + 3944: 04 00 + 3946: 00 1f + 3948: 00 8f + 394a: 00 40 + 394c: 4b 24 22 8c + 3950: 00 40 + 3952: 4b 24 22 2d + 3956: 75 00 + 3958: 40 4b + 395a: 24 22 + 395c: 7c 00 + 395e: 40 4b + 3960: 24 22 + 3962: 2d 21 + 3964: 08 ff + 3966: 1a 9f + ... + 3970: 34 04 + 3972: 00 00 + 3974: a4 04 + 3976: 00 00 + 3978: 02 00 + 397a: 39 9f + 397c: 28 05 + 397e: 00 00 + 3980: 30 05 + 3982: 00 00 + 3984: 02 00 + 3986: 39 9f + ... + 3990: 34 04 + 3992: 00 00 + 3994: a4 04 + 3996: 00 00 + 3998: 02 00 + 399a: 47 9f 28 05 + 399e: 00 00 + 39a0: 30 05 + 39a2: 00 00 + 39a4: 02 00 + 39a6: 47 9f 00 00 fmsub.s ft10, ft1, ft0, ft0, rtz + 39aa: 00 00 + 39ac: 00 00 + 39ae: 00 00 + 39b0: 34 04 + 39b2: 00 00 + 39b4: a4 04 + 39b6: 00 00 + 39b8: 02 00 + 39ba: 31 9f + 39bc: 28 05 + 39be: 00 00 + 39c0: 30 05 + 39c2: 00 00 + 39c4: 02 00 + 39c6: 31 9f + ... + 39d0: 34 04 + 39d2: 00 00 + 39d4: 84 04 + 39d6: 00 00 + 39d8: 02 00 + 39da: 31 9f + ... + 39e4: 34 04 + 39e6: 00 00 + 39e8: 64 04 + 39ea: 00 00 + 39ec: 08 00 + 39ee: 81 00 + 39f0: 39 24 + 39f2: 80 00 + 39f4: 21 9f + 39f6: 64 04 + 39f8: 00 00 + 39fa: 6c 04 + 39fc: 00 00 + 39fe: 01 00 + 3a00: 5f 6c 04 00 + 3a04: 00 70 + 3a06: 04 00 + 3a08: 00 08 + 3a0a: 00 81 + 3a0c: 00 39 + 3a0e: 24 80 + 3a10: 00 21 + 3a12: 9f 00 00 00 + 3a16: 00 00 + 3a18: 00 00 + 3a1a: 00 dc + 3a1c: 04 00 + 3a1e: 00 ec + 3a20: 04 00 + 3a22: 00 01 + 3a24: 00 5e + ... + 3a2e: b8 05 + 3a30: 00 00 + 3a32: 28 06 + 3a34: 00 00 + 3a36: 02 00 + 3a38: 31 9f + 3a3a: fc 06 + 3a3c: 00 00 + 3a3e: 04 07 + 3a40: 00 00 + 3a42: 02 00 + 3a44: 31 9f + 3a46: 18 07 + 3a48: 00 00 + 3a4a: 1c 07 + 3a4c: 00 00 + 3a4e: 05 00 + 3a50: 79 00 + 3a52: 31 1a + 3a54: 9f 1c 07 00 + 3a58: 00 20 + 3a5a: 07 00 00 01 + 3a5e: 00 5e + 3a60: 20 07 + 3a62: 00 00 + 3a64: 24 07 + 3a66: 00 00 + 3a68: 02 00 + 3a6a: 30 9f + ... + 3a74: c0 05 + 3a76: 00 00 + 3a78: 28 06 + 3a7a: 00 00 + 3a7c: 02 00 + 3a7e: 30 9f + ... + 3a88: c0 05 + 3a8a: 00 00 + 3a8c: 00 06 + 3a8e: 00 00 + 3a90: 01 00 + 3a92: 5f 04 06 00 + 3a96: 00 1c + 3a98: 06 00 + 3a9a: 00 01 + 3a9c: 00 5f + ... + 3aa6: c0 05 + 3aa8: 00 00 + 3aaa: 00 06 + 3aac: 00 00 + 3aae: 01 00 + 3ab0: 58 00 + 3ab2: 06 00 + 3ab4: 00 04 + 3ab6: 06 00 + 3ab8: 00 01 + 3aba: 00 5e + 3abc: 04 06 + 3abe: 00 00 + 3ac0: 1c 06 + 3ac2: 00 00 + 3ac4: 01 00 + 3ac6: 58 1c + 3ac8: 06 00 + 3aca: 00 20 + 3acc: 06 00 + 3ace: 00 01 + 3ad0: 00 5e + ... + 3ada: f4 05 + 3adc: 00 00 + 3ade: f8 05 + 3ae0: 00 00 + 3ae2: 03 00 7f 04 lb zero, 71(t5) + 3ae6: 9f 00 00 00 + 3aea: 00 00 + 3aec: 00 00 + 3aee: 00 0c + 3af0: 06 00 + 3af2: 00 14 + 3af4: 06 00 + 3af6: 00 03 + 3af8: 00 7f + 3afa: 08 9f + ... + 3b04: 90 06 + 3b06: 00 00 + 3b08: a0 06 + 3b0a: 00 00 + 3b0c: 01 00 + 3b0e: 5d 00 + ... + 3b18: 00 00 + 3b1a: 00 b8 + 3b1c: 00 00 + 3b1e: 00 02 + 3b20: 00 30 + 3b22: 9f c8 00 00 + 3b26: 00 24 + 3b28: 01 00 + 3b2a: 00 02 + 3b2c: 00 30 + 3b2e: 9f 00 00 00 + 3b32: 00 00 + 3b34: 00 00 + 3b36: 00 28 + 3b38: 00 00 + 3b3a: 00 4c + 3b3c: 00 00 + 3b3e: 00 0b + 3b40: 00 5f + 3b42: 93 04 6d 93 addi s1, s10, -1738 + 3b46: 04 6e + 3b48: 93 04 93 04 addi s1, t1, 73 + 3b4c: 4c 00 + 3b4e: 00 00 + 3b50: b8 00 + 3b52: 00 00 + 3b54: 0c 00 + 3b56: 5f 93 04 6d + 3b5a: 93 04 6e 93 addi s1, t3, -1738 + 3b5e: 04 6c + 3b60: 93 04 b8 00 addi s1, a6, 11 + 3b64: 00 00 + 3b66: c8 00 + 3b68: 00 00 + 3b6a: 0b 00 93 04 + 3b6e: 6d 93 + 3b70: 04 6e + 3b72: 93 04 6c 93 addi s1, s8, -1738 + 3b76: 04 c8 + 3b78: 00 00 + 3b7a: 00 e0 + 3b7c: 00 00 + 3b7e: 00 0c + 3b80: 00 5f + 3b82: 93 04 6d 93 addi s1, s10, -1738 + 3b86: 04 6e + 3b88: 93 04 6c 93 addi s1, s8, -1738 + 3b8c: 04 e0 + 3b8e: 00 00 + 3b90: 00 2c + 3b92: 01 00 + 3b94: 00 0b + 3b96: 00 93 + 3b98: 04 6d + 3b9a: 93 04 6e 93 addi s1, t3, -1738 + 3b9e: 04 6c + 3ba0: 93 04 00 00 mv s1, zero + 3ba4: 00 00 + 3ba6: 00 00 + 3ba8: 00 00 + 3baa: 4c 00 + 3bac: 00 00 + 3bae: 50 00 + 3bb0: 00 00 + 3bb2: 0b 00 5e 93 + 3bb6: 04 55 + 3bb8: 93 04 6f 93 addi s1, t5, -1738 + 3bbc: 04 93 + 3bbe: 04 50 + 3bc0: 00 00 + 3bc2: 00 b8 + 3bc4: 00 00 + 3bc6: 00 0c + 3bc8: 00 5e + 3bca: 93 04 55 93 addi s1, a0, -1739 + 3bce: 04 6f + 3bd0: 93 04 5b 93 addi s1, s6, -1739 + 3bd4: 04 b8 + 3bd6: 00 00 + 3bd8: 00 c8 + 3bda: 00 00 + 3bdc: 00 0a + 3bde: 00 93 + 3be0: 04 55 + 3be2: 93 04 6f 93 addi s1, t5, -1738 + 3be6: 04 93 + 3be8: 04 c8 + 3bea: 00 00 + 3bec: 00 0c + 3bee: 01 00 + 3bf0: 00 0c + 3bf2: 00 5e + 3bf4: 93 04 55 93 addi s1, a0, -1739 + 3bf8: 04 6f + 3bfa: 93 04 5b 93 addi s1, s6, -1739 + 3bfe: 04 0c + 3c00: 01 00 + 3c02: 00 1c + 3c04: 01 00 + 3c06: 00 0b + 3c08: 00 93 + 3c0a: 04 55 + 3c0c: 93 04 6f 93 addi s1, t5, -1738 + 3c10: 04 5b + 3c12: 93 04 1c 01 addi s1, s8, 17 + 3c16: 00 00 + 3c18: 2c 01 + 3c1a: 00 00 + 3c1c: 0a 00 + 3c1e: 93 04 55 93 addi s1, a0, -1739 + 3c22: 04 6f + 3c24: 93 04 93 04 addi s1, t1, 73 + ... + 3c30: d0 00 + 3c32: 00 00 + 3c34: 24 01 + 3c36: 00 00 + 3c38: 02 00 + 3c3a: 31 9f + ... + 3c44: d0 00 + 3c46: 00 00 + 3c48: f8 00 + 3c4a: 00 00 + 3c4c: 02 00 + 3c4e: 30 9f + ... + 3c58: f8 00 + 3c5a: 00 00 + 3c5c: 24 01 + 3c5e: 00 00 + 3c60: 02 00 + 3c62: 30 9f + ... + 3c70: 6c 00 + 3c72: 00 00 + 3c74: 02 00 + 3c76: 30 9f + 3c78: 78 00 + 3c7a: 00 00 + 3c7c: c4 00 + 3c7e: 00 00 + 3c80: 02 00 + 3c82: 30 9f + 3c84: cc 00 + 3c86: 00 00 + 3c88: 4c 01 + 3c8a: 00 00 + 3c8c: 02 00 + 3c8e: 30 9f + ... + 3c98: 4c 00 + 3c9a: 00 00 + 3c9c: 74 00 + 3c9e: 00 00 + 3ca0: 01 00 + 3ca2: 5a 78 + 3ca4: 00 00 + 3ca6: 00 bc + 3ca8: 00 00 + 3caa: 00 01 + 3cac: 00 5a + 3cae: cc 00 + 3cb0: 00 00 + 3cb2: 0c 01 + 3cb4: 00 00 + 3cb6: 01 00 + 3cb8: 5a 10 + 3cba: 01 00 + 3cbc: 00 14 + 3cbe: 01 00 + 3cc0: 00 01 + 3cc2: 00 5a + 3cc4: 18 01 + 3cc6: 00 00 + 3cc8: 48 01 + 3cca: 00 00 + 3ccc: 01 00 + 3cce: 5a 00 + 3cd0: 00 00 + 3cd2: 00 00 + 3cd4: 00 00 + 3cd6: 00 28 + 3cd8: 00 00 + 3cda: 00 48 + 3cdc: 00 00 + 3cde: 00 0b + 3ce0: 00 6f + 3ce2: 93 04 60 93 addi s1, zero, -1738 + 3ce6: 04 6c + 3ce8: 93 04 93 04 addi s1, t1, 73 + 3cec: 48 00 + 3cee: 00 00 + 3cf0: 4c 01 + 3cf2: 00 00 + 3cf4: 0c 00 + 3cf6: 6f 93 04 60 jal t1, 300544 + 3cfa: 93 04 6c 93 addi s1, s8, -1738 + 3cfe: 04 5b + 3d00: 93 04 00 00 mv s1, zero + 3d04: 00 00 + 3d06: 00 00 + 3d08: 00 00 + 3d0a: 4c 00 + 3d0c: 00 00 + 3d0e: 50 00 + 3d10: 00 00 + 3d12: 0b 00 55 93 + 3d16: 04 61 + 3d18: 93 04 6d 93 addi s1, s10, -1738 + 3d1c: 04 93 + 3d1e: 04 50 + 3d20: 00 00 + 3d22: 00 4c + 3d24: 01 00 + 3d26: 00 0c + 3d28: 00 55 + 3d2a: 93 04 61 93 addi s1, sp, -1738 + 3d2e: 04 6d + 3d30: 93 04 56 93 addi s1, a2, -1739 + 3d34: 04 00 + 3d36: 00 00 + 3d38: 00 00 + 3d3a: 00 00 + 3d3c: 00 a0 + 3d3e: 00 00 + 3d40: 00 a4 + 3d42: 00 00 + 3d44: 00 01 + 3d46: 00 5f + 3d48: cc 00 + 3d4a: 00 00 + 3d4c: d4 00 + 3d4e: 00 00 + 3d50: 02 00 + 3d52: 30 9f + 3d54: 34 01 + 3d56: 00 00 + 3d58: 38 01 + 3d5a: 00 00 + 3d5c: 02 00 + 3d5e: 30 9f + ... + 3d68: b4 00 + 3d6a: 00 00 + 3d6c: c4 00 + 3d6e: 00 00 + 3d70: 02 00 + 3d72: 30 9f + 3d74: d4 00 + 3d76: 00 00 + 3d78: 08 01 + 3d7a: 00 00 + 3d7c: 02 00 + 3d7e: 30 9f + 3d80: 18 01 + 3d82: 00 00 + 3d84: 20 01 + 3d86: 00 00 + 3d88: 02 00 + 3d8a: 31 9f + 3d8c: 20 01 + 3d8e: 00 00 + 3d90: 30 01 + 3d92: 00 00 + 3d94: 02 00 + 3d96: 30 9f + 3d98: 38 01 + 3d9a: 00 00 + 3d9c: 40 01 + 3d9e: 00 00 + 3da0: 02 00 + 3da2: 30 9f + ... + 3db0: 6c 00 + 3db2: 00 00 + 3db4: 02 00 + 3db6: 30 9f + 3db8: 78 00 + 3dba: 00 00 + 3dbc: c4 00 + 3dbe: 00 00 + 3dc0: 02 00 + 3dc2: 30 9f + 3dc4: cc 00 + 3dc6: 00 00 + 3dc8: 4c 01 + 3dca: 00 00 + 3dcc: 02 00 + 3dce: 30 9f + ... + 3dd8: 4c 00 + 3dda: 00 00 + 3ddc: 74 00 + 3dde: 00 00 + 3de0: 01 00 + 3de2: 5a 78 + 3de4: 00 00 + 3de6: 00 bc + 3de8: 00 00 + 3dea: 00 01 + 3dec: 00 5a + 3dee: cc 00 + 3df0: 00 00 + 3df2: 0c 01 + 3df4: 00 00 + 3df6: 01 00 + 3df8: 5a 10 + 3dfa: 01 00 + 3dfc: 00 14 + 3dfe: 01 00 + 3e00: 00 01 + 3e02: 00 5a + 3e04: 18 01 + 3e06: 00 00 + 3e08: 48 01 + 3e0a: 00 00 + 3e0c: 01 00 + 3e0e: 5a 00 + 3e10: 00 00 + 3e12: 00 00 + 3e14: 00 00 + 3e16: 00 28 + 3e18: 00 00 + 3e1a: 00 48 + 3e1c: 00 00 + 3e1e: 00 0b + 3e20: 00 6f + 3e22: 93 04 60 93 addi s1, zero, -1738 + 3e26: 04 6c + 3e28: 93 04 93 04 addi s1, t1, 73 + 3e2c: 48 00 + 3e2e: 00 00 + 3e30: 4c 01 + 3e32: 00 00 + 3e34: 0c 00 + 3e36: 6f 93 04 60 jal t1, 300544 + 3e3a: 93 04 6c 93 addi s1, s8, -1738 + 3e3e: 04 5b + 3e40: 93 04 00 00 mv s1, zero + 3e44: 00 00 + 3e46: 00 00 + 3e48: 00 00 + 3e4a: 4c 00 + 3e4c: 00 00 + 3e4e: 50 00 + 3e50: 00 00 + 3e52: 0b 00 55 93 + 3e56: 04 61 + 3e58: 93 04 6d 93 addi s1, s10, -1738 + 3e5c: 04 93 + 3e5e: 04 50 + 3e60: 00 00 + 3e62: 00 4c + 3e64: 01 00 + 3e66: 00 0c + 3e68: 00 55 + 3e6a: 93 04 61 93 addi s1, sp, -1738 + 3e6e: 04 6d + 3e70: 93 04 56 93 addi s1, a2, -1739 + 3e74: 04 00 + 3e76: 00 00 + 3e78: 00 00 + 3e7a: 00 00 + 3e7c: 00 a0 + 3e7e: 00 00 + 3e80: 00 a4 + 3e82: 00 00 + 3e84: 00 01 + 3e86: 00 5f + 3e88: cc 00 + 3e8a: 00 00 + 3e8c: d4 00 + 3e8e: 00 00 + 3e90: 02 00 + 3e92: 30 9f + 3e94: 34 01 + 3e96: 00 00 + 3e98: 38 01 + 3e9a: 00 00 + 3e9c: 02 00 + 3e9e: 30 9f + ... + 3ea8: b4 00 + 3eaa: 00 00 + 3eac: c4 00 + 3eae: 00 00 + 3eb0: 02 00 + 3eb2: 30 9f + 3eb4: d4 00 + 3eb6: 00 00 + 3eb8: 08 01 + 3eba: 00 00 + 3ebc: 02 00 + 3ebe: 30 9f + 3ec0: 18 01 + 3ec2: 00 00 + 3ec4: 20 01 + 3ec6: 00 00 + 3ec8: 02 00 + 3eca: 31 9f + 3ecc: 20 01 + 3ece: 00 00 + 3ed0: 30 01 + 3ed2: 00 00 + 3ed4: 02 00 + 3ed6: 30 9f + 3ed8: 38 01 + 3eda: 00 00 + 3edc: 40 01 + 3ede: 00 00 + 3ee0: 02 00 + 3ee2: 30 9f + ... + 3ef0: 40 02 + 3ef2: 00 00 + 3ef4: 02 00 + 3ef6: 30 9f + 3ef8: 40 02 + 3efa: 00 00 + 3efc: 14 03 + 3efe: 00 00 + 3f00: 01 00 + 3f02: 58 14 + 3f04: 03 00 00 28 lb zero, 640(zero) + 3f08: 03 00 00 02 lb zero, 32(zero) + 3f0c: 00 30 + 3f0e: 9f 28 03 00 + 3f12: 00 70 + 3f14: 04 00 + 3f16: 00 01 + 3f18: 00 58 + 3f1a: 74 04 + 3f1c: 00 00 + 3f1e: 90 0e + 3f20: 00 00 + 3f22: 01 00 + 3f24: 58 d8 + 3f26: 0e 00 + 3f28: 00 04 + 3f2a: 0f 00 00 01 fence w, unknown + 3f2e: 00 58 + 3f30: 04 0f + 3f32: 00 00 + 3f34: 08 0f + 3f36: 00 00 + 3f38: 05 00 + 3f3a: 78 00 + 3f3c: 34 21 + 3f3e: 9f 08 0f 00 + 3f42: 00 d8 + 3f44: 12 00 + 3f46: 00 01 + 3f48: 00 58 + ... + 3f52: 60 00 + 3f54: 00 00 + 3f56: a4 0e + 3f58: 00 00 + 3f5a: 01 00 + 3f5c: 59 d8 + 3f5e: 0e 00 + 3f60: 00 d8 + 3f62: 12 00 + 3f64: 00 01 + 3f66: 00 59 + ... + 3f70: f0 00 + 3f72: 00 00 + 3f74: f4 00 + 3f76: 00 00 + 3f78: 02 00 + 3f7a: 30 9f + 3f7c: 2c 02 + 3f7e: 00 00 + 3f80: 40 02 + 3f82: 00 00 + 3f84: 02 00 + 3f86: 33 9f 40 02 mulh t5, ra, tp + 3f8a: 00 00 + 3f8c: 14 03 + 3f8e: 00 00 + 3f90: 01 00 + 3f92: 67 28 03 00 + 3f96: 00 9c + 3f98: 04 00 + 3f9a: 00 01 + 3f9c: 00 67 + 3f9e: bc 04 + 3fa0: 00 00 + 3fa2: 44 05 + 3fa4: 00 00 + 3fa6: 01 00 + 3fa8: 67 48 0d 00 + 3fac: 00 6c + 3fae: 0d 00 + 3fb0: 00 01 + 3fb2: 00 67 + 3fb4: 98 0d + 3fb6: 00 00 + 3fb8: a4 0d + 3fba: 00 00 + 3fbc: 01 00 + 3fbe: 67 00 00 00 jr zero + 3fc2: 00 00 + 3fc4: 00 00 + 3fc6: 00 9c + 3fc8: 00 00 + 3fca: 00 d8 + 3fcc: 05 00 + 3fce: 00 06 + 3fd0: 00 85 + 3fd2: 00 08 + 3fd4: ff 1a 9f 48 + 3fd8: 0d 00 + 3fda: 00 c4 + 3fdc: 0d 00 + 3fde: 00 06 + 3fe0: 00 85 + 3fe2: 00 08 + 3fe4: ff 1a 9f bc + 3fe8: 12 00 + 3fea: 00 d8 + 3fec: 12 00 + 3fee: 00 06 + 3ff0: 00 85 + 3ff2: 00 08 + 3ff4: ff 1a 9f 00 + 3ff8: 00 00 + 3ffa: 00 00 + 3ffc: 00 00 + 3ffe: 00 98 + 4000: 00 00 + 4002: 00 f0 + 4004: 00 00 + 4006: 00 07 + 4008: 00 83 + 400a: 00 0a + 400c: ff ff 1a 9f + 4010: f0 00 + 4012: 00 00 + 4014: f4 00 + 4016: 00 00 + 4018: 01 00 + 401a: 63 fc 00 00 bgeu ra, zero, 24 + 401e: 00 10 + 4020: 02 00 + 4022: 00 07 + 4024: 00 83 + 4026: 00 0a + 4028: ff ff 1a 9f + 402c: 10 02 + 402e: 00 00 + 4030: 1c 02 + 4032: 00 00 + 4034: 0b 00 91 ac + 4038: 7f 06 40 25 + 403c: 0a ff + 403e: 7f 1a 9f 1c + 4042: 02 00 + 4044: 00 40 + 4046: 02 00 + 4048: 00 07 + 404a: 00 83 + 404c: 00 0a + 404e: ff ff 1a 9f + 4052: 40 02 + 4054: 00 00 + 4056: 14 03 + 4058: 00 00 + 405a: 01 00 + 405c: 63 14 03 00 bnez t1, 8 + 4060: 00 18 + 4062: 03 00 00 07 lb zero, 112(zero) + 4066: 00 83 + 4068: 00 0a + 406a: ff ff 1a 9f + 406e: 18 03 + 4070: 00 00 + 4072: 20 03 + 4074: 00 00 + 4076: 0b 00 91 ac + 407a: 7f 06 40 25 + 407e: 0a ff + 4080: 7f 1a 9f 20 + 4084: 03 00 00 28 lb zero, 640(zero) + 4088: 03 00 00 07 lb zero, 112(zero) + 408c: 00 83 + 408e: 00 0a + 4090: ff ff 1a 9f + 4094: 28 03 + 4096: 00 00 + 4098: f8 04 + 409a: 00 00 + 409c: 01 00 + 409e: 63 48 0d 00 bltz s10, 16 + 40a2: 00 c4 + 40a4: 0d 00 + 40a6: 00 01 + 40a8: 00 63 + 40aa: bc 12 + 40ac: 00 00 + 40ae: d8 12 + 40b0: 00 00 + 40b2: 01 00 + 40b4: 63 00 00 00 beqz zero, 0 + 40b8: 00 00 + 40ba: 00 00 + 40bc: 00 d0 + 40be: 02 00 + 40c0: 00 d4 + 40c2: 02 00 + 40c4: 00 02 + 40c6: 00 30 + 40c8: 9f d4 02 00 + 40cc: 00 14 + 40ce: 03 00 00 01 lb zero, 16(zero) + 40d2: 00 5d + 40d4: 58 04 + 40d6: 00 00 + 40d8: 74 04 + 40da: 00 00 + 40dc: 02 00 + 40de: 33 9f 8c 04 + 40e2: 00 00 + 40e4: 98 04 + 40e6: 00 00 + 40e8: 02 00 + 40ea: 33 9f 98 04 + 40ee: 00 00 + 40f0: e0 04 + 40f2: 00 00 + 40f4: 01 00 + 40f6: 5d 48 + 40f8: 0d 00 + 40fa: 00 c4 + 40fc: 0d 00 + 40fe: 00 01 + 4100: 00 5d + 4102: bc 12 + 4104: 00 00 + 4106: d8 12 + 4108: 00 00 + 410a: 01 00 + 410c: 5d 00 + 410e: 00 00 + 4110: 00 00 + 4112: 00 00 + 4114: 00 7c + 4116: 02 00 + 4118: 00 14 + 411a: 03 00 00 06 lb zero, 96(zero) + 411e: 00 84 + 4120: 00 08 + 4122: ff 1a 9f 28 + 4126: 03 00 00 e4 lb zero, -448(zero) + 412a: 04 00 + 412c: 00 06 + 412e: 00 84 + 4130: 00 08 + 4132: ff 1a 9f e4 + 4136: 04 00 + 4138: 00 60 + 413a: 09 00 + 413c: 00 07 + 413e: 00 91 + 4140: ac 7f + 4142: 06 4f + 4144: 25 9f + 4146: 48 0d + 4148: 00 00 + 414a: c4 0d + 414c: 00 00 + 414e: 06 00 + 4150: 84 00 + 4152: 08 ff + 4154: 1a 9f + 4156: bc 12 + 4158: 00 00 + 415a: d8 12 + 415c: 00 00 + 415e: 06 00 + 4160: 84 00 + 4162: 08 ff + 4164: 1a 9f + ... + 416e: 78 02 + 4170: 00 00 + 4172: d0 02 + 4174: 00 00 + 4176: 07 00 7f 00 + 417a: 0a ff + 417c: ff 1a 9f d0 + 4180: 02 00 + 4182: 00 14 + 4184: 03 00 00 01 lb zero, 16(zero) + 4188: 00 5a + 418a: 28 03 + 418c: 00 00 + 418e: 2c 03 + 4190: 00 00 + 4192: 07 00 7f 00 + 4196: 0a ff + 4198: ff 1a 9f 2c + 419c: 03 00 00 3f lb zero, 1008(zero) + 41a0: 03 00 00 0a lb zero, 160(zero) + 41a4: 00 91 + 41a6: ac 7f + 41a8: 06 40 + 41aa: 25 7e + 41ac: 00 1a + 41ae: 9f 3f 03 00 + 41b2: 00 94 + 41b4: 03 00 00 0b lb zero, 176(zero) + 41b8: 00 91 + 41ba: ac 7f + 41bc: 06 40 + 41be: 25 0a + 41c0: ff 7f 1a 9f + 41c4: 94 03 + 41c6: 00 00 + 41c8: 9f 03 00 00 + 41cc: 0a 00 + 41ce: 91 ac + 41d0: 7f 06 40 25 + 41d4: 7e 00 + 41d6: 1a 9f + 41d8: 9f 03 00 00 + 41dc: a8 03 + 41de: 00 00 + 41e0: 0b 00 91 ac + 41e4: 7f 06 40 25 + 41e8: 0a ff + 41ea: 7f 1a 9f a8 + 41ee: 03 00 00 b3 lb zero, -1232(zero) + 41f2: 03 00 00 0a lb zero, 160(zero) + 41f6: 00 91 + 41f8: ac 7f + 41fa: 06 40 + 41fc: 25 7e + 41fe: 00 1a + 4200: 9f b3 03 00 + 4204: 00 bc + 4206: 03 00 00 0b lb zero, 176(zero) + 420a: 00 91 + 420c: ac 7f + 420e: 06 40 + 4210: 25 0a + 4212: ff 7f 1a 9f + 4216: bc 03 + 4218: 00 00 + 421a: c3 03 00 00 fmadd.s ft7, ft0, ft0, ft0, rne + 421e: 0a 00 + 4220: 91 ac + 4222: 7f 06 40 25 + 4226: 7e 00 + 4228: 1a 9f + 422a: c3 03 00 00 fmadd.s ft7, ft0, ft0, ft0, rne + 422e: 48 04 + 4230: 00 00 + 4232: 0b 00 91 ac + 4236: 7f 06 40 25 + 423a: 0a ff + 423c: 7f 1a 9f 48 + 4240: 04 00 + 4242: 00 74 + 4244: 04 00 + 4246: 00 07 + 4248: 00 7f + 424a: 00 0a + 424c: ff ff 1a 9f + 4250: 74 04 + 4252: 00 00 + 4254: 80 04 + 4256: 00 00 + 4258: 0a 00 + 425a: 91 ac + 425c: 7f 06 40 25 + 4260: 7e 00 + 4262: 1a 9f + 4264: 80 04 + 4266: 00 00 + 4268: 98 04 + 426a: 00 00 + 426c: 07 00 7f 00 + 4270: 0a ff + 4272: ff 1a 9f 98 + 4276: 04 00 + 4278: 00 c4 + 427a: 04 00 + 427c: 00 01 + 427e: 00 5a + 4280: 48 0d + 4282: 00 00 + 4284: c4 0d + 4286: 00 00 + 4288: 01 00 + 428a: 5a bc + 428c: 12 00 + 428e: 00 d8 + 4290: 12 00 + 4292: 00 01 + 4294: 00 5a + ... + 429e: bc 04 + 42a0: 00 00 + 42a2: c8 0c + 42a4: 00 00 + 42a6: 02 00 + 42a8: 30 9f + 42aa: 6c 0d + 42ac: 00 00 + 42ae: 98 0d + 42b0: 00 00 + 42b2: 01 00 + 42b4: 67 c0 0d 00 + 42b8: 00 c4 + 42ba: 0d 00 + 42bc: 00 01 + 42be: 00 67 + 42c0: c4 0d + 42c2: 00 00 + 42c4: d0 0d + 42c6: 00 00 + 42c8: 02 00 + 42ca: 30 9f + 42cc: 10 0f + 42ce: 00 00 + 42d0: 30 0f + 42d2: 00 00 + 42d4: 02 00 + 42d6: 30 9f + 42d8: bc 12 + 42da: 00 00 + 42dc: d8 12 + 42de: 00 00 + 42e0: 01 00 + 42e2: 67 00 00 00 jr zero + 42e6: 00 00 + 42e8: 00 00 + 42ea: 00 f8 + 42ec: 02 00 + 42ee: 00 14 + 42f0: 03 00 00 01 lb zero, 16(zero) + 42f4: 00 5f + 42f6: 98 04 + 42f8: 00 00 + 42fa: 9c 04 + 42fc: 00 00 + 42fe: 01 00 + 4300: 5f b0 04 00 + 4304: 00 bc + 4306: 04 00 + 4308: 00 02 + 430a: 00 30 + 430c: 9f bc 04 00 + 4310: 00 60 + 4312: 0e 00 + 4314: 00 01 + 4316: 00 5f + 4318: d8 0e + 431a: 00 00 + 431c: d8 12 + 431e: 00 00 + 4320: 01 00 + 4322: 5f 00 00 00 + 4326: 00 00 + 4328: 00 00 + 432a: 00 f8 + 432c: 02 00 + 432e: 00 14 + 4330: 03 00 00 03 lb zero, 48(zero) + 4334: 00 91 + 4336: c4 7e + 4338: 98 04 + 433a: 00 00 + 433c: 9c 04 + 433e: 00 00 + 4340: 03 00 91 c4 lb zero, -951(sp) + 4344: 7e 9c + 4346: 04 00 + 4348: 00 bc + 434a: 04 00 + 434c: 00 04 + 434e: 00 0a + 4350: ff 7f 9f bc + 4354: 04 00 + 4356: 00 d8 + 4358: 0c 00 + 435a: 00 03 + 435c: 00 91 + 435e: c4 7e + 4360: d8 0c + 4362: 00 00 + 4364: 48 0d + 4366: 00 00 + 4368: 01 00 + 436a: 5d 48 + 436c: 0d 00 + 436e: 00 84 + 4370: 0d 00 + 4372: 00 03 + 4374: 00 91 + 4376: c4 7e + 4378: 84 0d + 437a: 00 00 + 437c: 98 0d + 437e: 00 00 + 4380: 02 00 + 4382: 30 9f + 4384: 98 0d + 4386: 00 00 + 4388: cc 0d + 438a: 00 00 + 438c: 03 00 91 c4 lb zero, -951(sp) + 4390: 7e cc + 4392: 0d 00 + 4394: 00 d0 + 4396: 0d 00 + 4398: 00 07 + 439a: 00 91 + 439c: c8 7e + 439e: 06 23 + 43a0: 01 9f + 43a2: d0 0d + 43a4: 00 00 + 43a6: f8 0d + 43a8: 00 00 + 43aa: 01 00 + 43ac: 5d f8 + 43ae: 0d 00 + 43b0: 00 0c + 43b2: 0e 00 + 43b4: 00 08 + 43b6: 00 91 + 43b8: c4 7e + 43ba: 06 23 + 43bc: ff 7f 9f 0c + 43c0: 0e 00 + 43c2: 00 10 + 43c4: 0e 00 + 43c6: 00 0a + 43c8: 00 7d + 43ca: 00 91 + 43cc: c4 7e + 43ce: 06 22 + 43d0: 31 1c + 43d2: 9f 10 0e 00 + 43d6: 00 54 + 43d8: 0e 00 + 43da: 00 01 + 43dc: 00 5d + 43de: 54 0e + 43e0: 00 00 + 43e2: 5c 0e + 43e4: 00 00 + 43e6: 01 00 + 43e8: 5e d8 + 43ea: 0e 00 + 43ec: 00 ec + 43ee: 0e 00 + 43f0: 00 01 + 43f2: 00 5d + 43f4: ec 0e + 43f6: 00 00 + 43f8: 04 0f + 43fa: 00 00 + 43fc: 04 00 + 43fe: 0a ff + 4400: 7f 9f 04 0f + 4404: 00 00 + 4406: 0c 0f + 4408: 00 00 + 440a: 01 00 + 440c: 5e 0c + 440e: 0f 00 00 10 + 4412: 0f 00 00 01 fence w, unknown + 4416: 00 5d + 4418: 10 0f + 441a: 00 00 + 441c: 30 0f + 441e: 00 00 + 4420: 04 00 + 4422: 0a fe + 4424: 7f 9f 30 0f + 4428: 00 00 + 442a: c4 0f + 442c: 00 00 + 442e: 01 00 + 4430: 5d c4 + 4432: 0f 00 00 e0 + 4436: 0f 00 00 01 fence w, unknown + 443a: 00 5c + 443c: e0 0f + 443e: 00 00 + 4440: 1c 10 + 4442: 00 00 + 4444: 09 00 + 4446: 0b 02 c0 91 + 444a: c4 7e + 444c: 06 1c + 444e: 9f 1c 10 00 + 4452: 00 24 + 4454: 10 00 + 4456: 00 0c + 4458: 00 7b + 445a: 00 91 + 445c: c4 7e + 445e: 06 1c + 4460: 0a ff + 4462: 3f 1c 9f 24 + 4466: 10 00 + 4468: 00 28 + 446a: 10 00 + 446c: 00 09 + 446e: 00 0b + 4470: 02 c0 + 4472: 91 c4 + 4474: 7e 06 + 4476: 1c 9f + 4478: 28 10 + 447a: 00 00 + 447c: 44 10 + 447e: 00 00 + 4480: 01 00 + 4482: 5c 44 + 4484: 10 00 + 4486: 00 64 + 4488: 11 00 + 448a: 00 09 + 448c: 00 0b + 448e: 02 c0 + 4490: 91 c4 + 4492: 7e 06 + 4494: 1c 9f + 4496: 64 11 + 4498: 00 00 + 449a: 84 11 + 449c: 00 00 + 449e: 02 00 + 44a0: 31 9f + 44a2: 84 11 + 44a4: 00 00 + 44a6: fc 11 + 44a8: 00 00 + 44aa: 09 00 + 44ac: 0b 02 c0 91 + 44b0: c4 7e + 44b2: 06 1c + 44b4: 9f 28 12 00 + 44b8: 00 38 + 44ba: 12 00 + 44bc: 00 02 + 44be: 00 30 + 44c0: 9f 40 12 00 + 44c4: 00 bc + 44c6: 12 00 + 44c8: 00 02 + 44ca: 00 30 + 44cc: 9f bc 12 00 + 44d0: 00 d8 + 44d2: 12 00 + 44d4: 00 04 + 44d6: 00 0a + 44d8: ff 7f 9f 00 + 44dc: 00 00 + 44de: 00 00 + 44e0: 00 00 + 44e2: 00 80 + 44e4: 0e 00 + 44e6: 00 d8 + 44e8: 0e 00 + 44ea: 00 0c + 44ec: 00 5b + 44ee: 93 04 5c 93 addi s1, s8, -1739 + 44f2: 04 5d + 44f4: 93 04 5f 93 addi s1, t5, -1739 + 44f8: 04 00 + 44fa: 00 00 + 44fc: 00 00 + 44fe: 00 00 + 4500: 00 b0 + 4502: 00 00 + 4504: 00 f0 + 4506: 00 00 + 4508: 00 02 + 450a: 00 33 + 450c: 9f 00 00 00 + 4510: 00 00 + 4512: 00 00 + 4514: 00 b0 + 4516: 00 00 + 4518: 00 f0 + 451a: 00 00 + 451c: 00 02 + 451e: 00 4d + 4520: 9f 00 00 00 + 4524: 00 00 + 4526: 00 00 + 4528: 00 b0 + 452a: 00 00 + 452c: 00 f0 + 452e: 00 00 + 4530: 00 02 + 4532: 00 30 + 4534: 9f 00 00 00 + 4538: 00 00 + 453a: 00 00 + 453c: 00 b0 + 453e: 00 00 + 4540: 00 b8 + 4542: 00 00 + 4544: 00 02 + 4546: 00 33 + 4548: 9f d8 00 00 + 454c: 00 f0 + 454e: 00 00 + 4550: 00 03 + 4552: 00 09 + 4554: ff 9f 00 00 + 4558: 00 00 + 455a: 00 00 + 455c: 00 00 + 455e: 18 01 + 4560: 00 00 + 4562: 6c 01 + 4564: 00 00 + 4566: 03 00 7a 71 lb zero, 1815(s4) + 456a: 9f 74 01 00 + 456e: 00 7c + 4570: 01 00 + 4572: 00 01 + 4574: 00 5a + 4576: 88 01 + 4578: 00 00 + 457a: 90 01 + 457c: 00 00 + 457e: 01 00 + 4580: 5a 98 + 4582: 01 00 + 4584: 00 a0 + 4586: 01 00 + 4588: 00 01 + 458a: 00 5a + 458c: a0 01 + 458e: 00 00 + 4590: 1c 02 + 4592: 00 00 + 4594: 03 00 7a 71 lb zero, 1815(s4) + 4598: 9f 00 00 00 + 459c: 00 00 + 459e: 00 00 + 45a0: 00 20 + 45a2: 01 00 + 45a4: 00 24 + 45a6: 01 00 + 45a8: 00 05 + 45aa: 00 7d + 45ac: 00 4f + 45ae: 1a 9f + 45b0: 24 01 + 45b2: 00 00 + 45b4: 28 01 + 45b6: 00 00 + 45b8: 01 00 + 45ba: 5d a0 + 45bc: 01 00 + 45be: 00 b0 + 45c0: 01 00 + 45c2: 00 01 + 45c4: 00 5d + 45c6: b0 01 + 45c8: 00 00 + 45ca: d0 01 + 45cc: 00 00 + 45ce: 05 00 + 45d0: 7a 74 + 45d2: 4f 1a 9f 00 fnmadd.s fs4, ft10, fs1, ft0, rtz + 45d6: 00 00 + 45d8: 00 00 + 45da: 00 00 + 45dc: 00 20 + 45de: 01 00 + 45e0: 00 24 + 45e2: 01 00 + 45e4: 00 08 + 45e6: 00 08 + 45e8: 20 7d + 45ea: 00 4f + 45ec: 1a 1c + 45ee: 9f 24 01 00 + 45f2: 00 28 + 45f4: 01 00 + 45f6: 00 06 + 45f8: 00 08 + 45fa: 20 7d + 45fc: 00 1c + 45fe: 9f a0 01 00 + 4602: 00 b0 + 4604: 01 00 + 4606: 00 06 + 4608: 00 08 + 460a: 20 7d + 460c: 00 1c + 460e: 9f b0 01 00 + 4612: 00 d0 + 4614: 01 00 + 4616: 00 08 + 4618: 00 08 + 461a: 20 7a + 461c: 74 4f + 461e: 1a 1c + 4620: 9f 00 00 00 + 4624: 00 00 + 4626: 00 00 + 4628: 00 20 + 462a: 01 00 + 462c: 00 5c + 462e: 01 00 + 4630: 00 01 + 4632: 00 5f + 4634: 5c 01 + 4636: 00 00 + 4638: 64 01 + 463a: 00 00 + 463c: 03 00 7f 01 lb zero, 23(t5) + 4640: 9f 64 01 00 + 4644: 00 6c + 4646: 01 00 + 4648: 00 05 + 464a: 00 7a + 464c: 74 35 + 464e: 26 9f + 4650: a0 01 + 4652: 00 00 + 4654: cc 01 + 4656: 00 00 + 4658: 01 00 + 465a: 5f cc 01 00 + 465e: 00 d0 + 4660: 01 00 + 4662: 00 03 + 4664: 00 7f + 4666: 01 9f + 4668: d0 01 + 466a: 00 00 + 466c: f4 01 + 466e: 00 00 + 4670: 01 00 + 4672: 5f f4 01 00 + 4676: 00 1c + 4678: 02 00 + 467a: 00 05 + 467c: 00 7a + 467e: 74 35 + 4680: 26 9f + ... + 468a: 5c 01 + 468c: 00 00 + 468e: 64 01 + 4690: 00 00 + 4692: 01 00 + 4694: 5f b0 01 00 + 4698: 00 bc + 469a: 01 00 + 469c: 00 01 + 469e: 00 5d + 46a0: bc 01 + 46a2: 00 00 + 46a4: c4 01 + 46a6: 00 00 + 46a8: 03 00 7d 01 lb zero, 23(s10) + 46ac: 9f c4 01 00 + 46b0: 00 d0 + 46b2: 01 00 + 46b4: 00 01 + 46b6: 00 5d + 46b8: f4 01 + 46ba: 00 00 + 46bc: 1c 02 + 46be: 00 00 + 46c0: 01 00 + 46c2: 5f 00 00 00 + 46c6: 00 00 + 46c8: 00 00 + 46ca: 00 90 + 46cc: 02 00 + 46ce: 00 d0 + 46d0: 02 00 + 46d2: 00 02 + 46d4: 00 33 + 46d6: 9f 00 00 00 + 46da: 00 00 + 46dc: 00 00 + 46de: 00 90 + 46e0: 02 00 + 46e2: 00 d0 + 46e4: 02 00 + 46e6: 00 02 + 46e8: 00 4d + 46ea: 9f 00 00 00 + 46ee: 00 00 + 46f0: 00 00 + 46f2: 00 90 + 46f4: 02 00 + 46f6: 00 d0 + 46f8: 02 00 + 46fa: 00 02 + 46fc: 00 30 + 46fe: 9f 00 00 00 + 4702: 00 00 + 4704: 00 00 + 4706: 00 90 + 4708: 02 00 + 470a: 00 98 + 470c: 02 00 + 470e: 00 02 + 4710: 00 33 + 4712: 9f b8 02 00 + 4716: 00 d0 + 4718: 02 00 + 471a: 00 03 + 471c: 00 09 + 471e: ff 9f 00 00 + 4722: 00 00 + 4724: 00 00 + 4726: 00 00 + 4728: 40 03 + 472a: 00 00 + 472c: 94 03 + 472e: 00 00 + 4730: 03 00 7a 71 lb zero, 1815(s4) + 4734: 9f a0 03 00 + 4738: 00 a8 + 473a: 03 00 00 01 lb zero, 16(zero) + 473e: 00 5a + 4740: b4 03 + 4742: 00 00 + 4744: bc 03 + 4746: 00 00 + 4748: 01 00 + 474a: 5a c4 + 474c: 03 00 00 cc lb zero, -832(zero) + 4750: 03 00 00 01 lb zero, 16(zero) + 4754: 00 5a + 4756: cc 03 + 4758: 00 00 + 475a: 44 04 + 475c: 00 00 + 475e: 03 00 7a 71 lb zero, 1815(s4) + 4762: 9f 00 00 00 + 4766: 00 00 + 4768: 00 00 + 476a: 00 48 + 476c: 03 00 00 4c lb zero, 1216(zero) + 4770: 03 00 00 05 lb zero, 80(zero) + 4774: 00 7d + 4776: 00 4f + 4778: 1a 9f + 477a: 4c 03 + 477c: 00 00 + 477e: 50 03 + 4780: 00 00 + 4782: 01 00 + 4784: 5d cc + 4786: 03 00 00 dc lb zero, -576(zero) + 478a: 03 00 00 01 lb zero, 16(zero) + 478e: 00 5d + 4790: dc 03 + 4792: 00 00 + 4794: fc 03 + 4796: 00 00 + 4798: 05 00 + 479a: 7a 74 + 479c: 4f 1a 9f 00 fnmadd.s fs4, ft10, fs1, ft0, rtz + 47a0: 00 00 + 47a2: 00 00 + 47a4: 00 00 + 47a6: 00 48 + 47a8: 03 00 00 4c lb zero, 1216(zero) + 47ac: 03 00 00 08 lb zero, 128(zero) + 47b0: 00 08 + 47b2: 20 7d + 47b4: 00 4f + 47b6: 1a 1c + 47b8: 9f 4c 03 00 + 47bc: 00 50 + 47be: 03 00 00 06 lb zero, 96(zero) + 47c2: 00 08 + 47c4: 20 7d + 47c6: 00 1c + 47c8: 9f cc 03 00 + 47cc: 00 dc + 47ce: 03 00 00 06 lb zero, 96(zero) + 47d2: 00 08 + 47d4: 20 7d + 47d6: 00 1c + 47d8: 9f dc 03 00 + 47dc: 00 fc + 47de: 03 00 00 08 lb zero, 128(zero) + 47e2: 00 08 + 47e4: 20 7a + 47e6: 74 4f + 47e8: 1a 1c + 47ea: 9f 00 00 00 + 47ee: 00 00 + 47f0: 00 00 + 47f2: 00 48 + 47f4: 03 00 00 84 lb zero, -1984(zero) + 47f8: 03 00 00 01 lb zero, 16(zero) + 47fc: 00 5f + 47fe: 84 03 + 4800: 00 00 + 4802: 8c 03 + 4804: 00 00 + 4806: 03 00 7f 01 lb zero, 23(t5) + 480a: 9f 8c 03 00 + 480e: 00 94 + 4810: 03 00 00 05 lb zero, 80(zero) + 4814: 00 7a + 4816: 74 35 + 4818: 26 9f + 481a: cc 03 + 481c: 00 00 + 481e: f8 03 + 4820: 00 00 + 4822: 01 00 + 4824: 5f f8 03 00 + 4828: 00 fc + 482a: 03 00 00 03 lb zero, 48(zero) + 482e: 00 7f + 4830: 01 9f + 4832: fc 03 + 4834: 00 00 + 4836: 20 04 + 4838: 00 00 + 483a: 01 00 + 483c: 5f 20 04 00 + 4840: 00 44 + 4842: 04 00 + 4844: 00 05 + 4846: 00 7a + 4848: 74 35 + 484a: 26 9f + ... + 4854: 84 03 + 4856: 00 00 + 4858: 8c 03 + 485a: 00 00 + 485c: 01 00 + 485e: 5f dc 03 00 + 4862: 00 e8 + 4864: 03 00 00 01 lb zero, 16(zero) + 4868: 00 5d + 486a: e8 03 + 486c: 00 00 + 486e: f0 03 + 4870: 00 00 + 4872: 03 00 7d 01 lb zero, 23(s10) + 4876: 9f f0 03 00 + 487a: 00 fc + 487c: 03 00 00 01 lb zero, 16(zero) + 4880: 00 5d + 4882: 20 04 + 4884: 00 00 + 4886: 3c 04 + 4888: 00 00 + 488a: 01 00 + 488c: 5f 00 00 00 + 4890: 00 00 + 4892: 00 00 + 4894: 00 78 + 4896: 05 00 + 4898: 00 d4 + 489a: 06 00 + 489c: 00 01 + 489e: 00 60 + 48a0: d4 06 + 48a2: 00 00 + 48a4: a4 07 + 48a6: 00 00 + 48a8: 22 00 + 48aa: 8c 00 + 48ac: 7b 00 1e 8a + 48b0: 00 1a + 48b2: 8f 00 7b 00 + 48b6: 1e 77 + 48b8: 00 8c + 48ba: 00 1e + 48bc: 22 8c + 48be: 00 7b + 48c0: 00 1e + 48c2: 40 25 + 48c4: 22 8a + 48c6: 00 1a + 48c8: 40 24 + 48ca: 22 9f + 48cc: a4 07 + 48ce: 00 00 + 48d0: b4 07 + 48d2: 00 00 + 48d4: 24 00 + 48d6: 8c 00 + 48d8: 7b 00 1e 0a + 48dc: ff ff 1a 8f + 48e0: 00 7b + 48e2: 00 1e + 48e4: 77 00 8c 00 + 48e8: 1e 22 + 48ea: 8c 00 + 48ec: 7b 00 1e 40 + 48f0: 25 22 + 48f2: 0a ff + 48f4: ff 1a 40 24 + 48f8: 22 9f + 48fa: b4 07 + 48fc: 00 00 + 48fe: c0 07 + 4900: 00 00 + 4902: 36 00 + 4904: 91 f0 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00 07 + 4d5e: 00 72 + 4d60: 00 06 + 4d62: 87 00 22 9f + 4d66: e0 07 + 4d68: 00 00 + 4d6a: e4 07 + 4d6c: 00 00 + 4d6e: 01 00 + 4d70: 57 e4 07 00 + 4d74: 00 dc + 4d76: 09 00 + 4d78: 00 03 + 4d7a: 00 91 + 4d7c: dc 7e + 4d7e: dc 09 + 4d80: 00 00 + 4d82: 54 0b + 4d84: 00 00 + 4d86: 01 00 + 4d88: 67 dc 0b 00 + 4d8c: 00 ec + 4d8e: 0b 00 00 08 + 4d92: 00 81 + 4d94: 00 40 + 4d96: 25 80 + 4d98: 00 22 + 4d9a: 9f ec 0b 00 + 4d9e: 00 f4 + 4da0: 0b 00 00 06 + 4da4: 00 81 + 4da6: 00 80 + 4da8: 00 22 + 4daa: 9f f4 0b 00 + 4dae: 00 14 + 4db0: 0c 00 + 4db2: 00 0d + 4db4: 00 7b + 4db6: 00 40 + 4db8: 25 77 + 4dba: 00 22 + 4dbc: 40 25 + 4dbe: 80 00 + 4dc0: 22 9f + ... + 4dca: d0 05 + 4dcc: 00 00 + 4dce: e8 06 + 4dd0: 00 00 + 4dd2: 01 00 + 4dd4: 61 e8 + 4dd6: 06 00 + 4dd8: 00 a4 + 4dda: 07 00 00 22 + 4dde: 00 7c + 4de0: 00 7a + 4de2: 00 1e + 4de4: 8a 00 + 4de6: 1a 7e + 4de8: 00 7c + 4dea: 00 1e + 4dec: 75 00 + 4dee: 7a 00 + 4df0: 1e 22 + 4df2: 7c 00 + 4df4: 7a 00 + 4df6: 1e 40 + 4df8: 25 22 + 4dfa: 8a 00 + 4dfc: 1a 40 + 4dfe: 24 22 + 4e00: 9f a4 07 00 + 4e04: 00 c8 + 4e06: 07 00 00 24 + 4e0a: 00 7c + 4e0c: 00 7a + 4e0e: 00 1e + 4e10: 0a ff + 4e12: ff 1a 7e 00 + 4e16: 7c 00 + 4e18: 1e 75 + 4e1a: 00 7a + 4e1c: 00 1e + 4e1e: 22 7c + 4e20: 00 7a + 4e22: 00 1e + 4e24: 40 25 + 4e26: 22 0a + 4e28: ff ff 1a 40 + 4e2c: 24 22 + 4e2e: 9f c8 07 00 + 4e32: 00 cc + 4e34: 07 00 00 22 + 4e38: 00 7c + 4e3a: 00 7a + 4e3c: 00 1e + 4e3e: 88 7f + 4e40: 1a 7e + 4e42: 00 7c + 4e44: 00 1e + 4e46: 75 00 + 4e48: 7a 00 + 4e4a: 1e 22 + 4e4c: 7c 00 + 4e4e: 7a 00 + 4e50: 1e 40 + 4e52: 25 22 + 4e54: 88 7f + 4e56: 1a 40 + 4e58: 24 22 + 4e5a: 9f cc 07 00 + 4e5e: 00 d8 + 4e60: 07 00 00 24 + 4e64: 00 7c + 4e66: 00 7a + 4e68: 00 1e + 4e6a: 0a ff + 4e6c: ff 1a 7e 00 + 4e70: 7c 00 + 4e72: 1e 75 + 4e74: 00 7a + 4e76: 00 1e + 4e78: 22 7c + 4e7a: 00 7a + 4e7c: 00 1e + 4e7e: 40 25 + 4e80: 22 0a + 4e82: ff ff 1a 40 + 4e86: 24 22 + 4e88: 9f d8 07 00 + 4e8c: 00 08 + 4e8e: 08 00 + 4e90: 00 22 + 4e92: 00 7c + 4e94: 00 7a + 4e96: 00 1e + 4e98: 88 7f + 4e9a: 1a 7e + 4e9c: 00 7c + 4e9e: 00 1e + 4ea0: 75 00 + 4ea2: 7a 00 + 4ea4: 1e 22 + 4ea6: 7c 00 + 4ea8: 7a 00 + 4eaa: 1e 40 + 4eac: 25 22 + 4eae: 88 7f + 4eb0: 1a 40 + 4eb2: 24 22 + 4eb4: 9f 08 08 00 + 4eb8: 00 10 + 4eba: 08 00 + 4ebc: 00 26 + 4ebe: 00 7c + 4ec0: 00 7a + 4ec2: 00 1e + 4ec4: 88 7f + 4ec6: 1a 91 + 4ec8: 80 7f + 4eca: 06 40 + 4ecc: 25 7c + 4ece: 00 1e + 4ed0: 75 00 + 4ed2: 7a 00 + 4ed4: 1e 22 + 4ed6: 7c 00 + 4ed8: 7a 00 + 4eda: 1e 40 + 4edc: 25 22 + 4ede: 88 7f + 4ee0: 1a 40 + 4ee2: 24 22 + 4ee4: 9f 10 08 00 + 4ee8: 00 48 + 4eea: 08 00 + 4eec: 00 35 + 4eee: 00 88 + 4ef0: 7f 91 80 7f + 4ef4: 06 1a + 4ef6: 7c 00 + 4ef8: 1e 88 + 4efa: 7f 1a 91 80 + 4efe: 7f 06 40 25 + 4f02: 7c 00 + 4f04: 1e 88 + 4f06: 7f 91 80 7f + 4f0a: 06 1a + 4f0c: 75 00 + 4f0e: 1e 22 + 4f10: 88 7f + 4f12: 91 80 + 4f14: 7f 06 1a 7c + 4f18: 00 1e + 4f1a: 40 25 + 4f1c: 22 88 + 4f1e: 7f 1a 40 24 + 4f22: 22 9f + 4f24: 48 08 + 4f26: 00 00 + 4f28: f8 08 + 4f2a: 00 00 + 4f2c: 01 00 + 4f2e: 6b f8 08 00 vx_tex a6, a7, zero, zero, dyn + 4f32: 00 fc + 4f34: 08 00 + 4f36: 00 35 + 4f38: 00 87 + 4f3a: 7f 91 80 7f + 4f3e: 06 1a + 4f40: 77 00 1e 87 + 4f44: 7f 1a 91 80 + 4f48: 7f 06 40 25 + 4f4c: 77 00 1e 87 + 4f50: 7f 91 80 7f + 4f54: 06 1a + 4f56: 80 00 + 4f58: 1e 22 + 4f5a: 87 7f 91 80 + 4f5e: 7f 06 1a 77 + 4f62: 00 1e + 4f64: 40 25 + 4f66: 22 87 + 4f68: 7f 1a 40 24 + 4f6c: 22 9f + 4f6e: fc 08 + 4f70: 00 00 + 4f72: cc 09 + 4f74: 00 00 + 4f76: 3a 00 + 4f78: 91 80 + 4f7a: 7f 06 0a ff + 4f7e: ff 1a 77 00 + 4f82: 1e 0a + 4f84: ff ff 1a 91 + 4f88: 80 7f + 4f8a: 06 40 + 4f8c: 25 77 + 4f8e: 00 1e + 4f90: 91 80 + 4f92: 7f 06 0a ff + 4f96: ff 1a 80 00 + 4f9a: 1e 22 + 4f9c: 91 80 + 4f9e: 7f 06 0a ff + 4fa2: ff 1a 77 00 + 4fa6: 1e 40 + 4fa8: 25 22 + 4faa: 0a ff + 4fac: ff 1a 40 24 + 4fb0: 22 9f + 4fb2: cc 09 + 4fb4: 00 00 + 4fb6: d0 09 + 4fb8: 00 00 + 4fba: 35 00 + 4fbc: 7b 7f 91 80 + 4fc0: 7f 06 1a 77 + 4fc4: 00 1e + 4fc6: 7b 7f 1a 91 + 4fca: 80 7f + 4fcc: 06 40 + 4fce: 25 77 + 4fd0: 00 1e + 4fd2: 7b 7f 91 80 + 4fd6: 7f 06 1a 80 + 4fda: 00 1e + 4fdc: 22 7b + 4fde: 7f 91 80 7f + 4fe2: 06 1a + 4fe4: 77 00 1e 40 + 4fe8: 25 22 + 4fea: 7b 7f 1a 40 + 4fee: 24 22 + 4ff0: 9f d0 09 00 + 4ff4: 00 d8 + 4ff6: 09 00 + 4ff8: 00 3a + 4ffa: 00 91 + 4ffc: 80 7f + 4ffe: 06 0a + 5000: ff ff 1a 77 + 5004: 00 1e + 5006: 0a ff + 5008: ff 1a 91 80 + 500c: 7f 06 40 25 + 5010: 77 00 1e 91 + 5014: 80 7f + 5016: 06 0a + 5018: ff ff 1a 80 + 501c: 00 1e + 501e: 22 91 + 5020: 80 7f + 5022: 06 0a + 5024: ff ff 1a 77 + 5028: 00 1e + 502a: 40 25 + 502c: 22 0a + 502e: ff ff 1a 40 + 5032: 24 22 + 5034: 9f d8 09 00 + 5038: 00 34 + 503a: 0a 00 + 503c: 00 35 + 503e: 00 88 + 5040: 7f 91 80 7f + 5044: 06 1a + 5046: 77 00 1e 88 + 504a: 7f 1a 91 80 + 504e: 7f 06 40 25 + 5052: 77 00 1e 88 + 5056: 7f 91 80 7f + 505a: 06 1a + 505c: 80 00 + 505e: 1e 22 + 5060: 88 7f + 5062: 91 80 + 5064: 7f 06 1a 77 + 5068: 00 1e + 506a: 40 25 + 506c: 22 88 + 506e: 7f 1a 40 24 + 5072: 22 9f + 5074: 34 0a + 5076: 00 00 + 5078: 38 0a + 507a: 00 00 + 507c: 35 00 + 507e: 89 7f + 5080: 91 80 + 5082: 7f 06 1a 77 + 5086: 00 1e + 5088: 89 7f + 508a: 1a 91 + 508c: 80 7f + 508e: 06 40 + 5090: 25 77 + 5092: 00 1e + 5094: 89 7f + 5096: 91 80 + 5098: 7f 06 1a 80 + 509c: 00 1e + 509e: 22 89 + 50a0: 7f 91 80 7f + 50a4: 06 1a + 50a6: 77 00 1e 40 + 50aa: 25 22 + 50ac: 89 7f + 50ae: 1a 40 + 50b0: 24 22 + 50b2: 9f 38 0a 00 + 50b6: 00 1c + 50b8: 0b 00 00 01 + 50bc: 00 5c + 50be: 1c 0b + 50c0: 00 00 + 50c2: 20 0b + 50c4: 00 00 + 50c6: 35 00 + 50c8: 88 7f + 50ca: 91 f4 + 50cc: 7e 06 + 50ce: 1a 8a + 50d0: 00 1e + 50d2: 88 7f + 50d4: 1a 88 + 50d6: 7f 91 f4 7e + 50da: 06 1a + 50dc: 81 00 + 50de: 1e 91 + 50e0: f4 7e + 50e2: 06 40 + 50e4: 25 8a + 50e6: 00 1e + 50e8: 22 88 + 50ea: 7f 91 f4 7e + 50ee: 06 1a + 50f0: 8a 00 + 50f2: 1e 40 + 50f4: 25 22 + 50f6: 88 7f + 50f8: 1a 40 + 50fa: 24 22 + 50fc: 9f 20 0b 00 + 5100: 00 bc + 5102: 0b 00 00 35 + 5106: 00 91 + 5108: f4 7e + 510a: 06 76 + 510c: 00 1a + 510e: 8a 00 + 5110: 1e 76 + 5112: 00 1a + 5114: 91 f4 + 5116: 7e 06 + 5118: 76 00 + 511a: 1a 81 + 511c: 00 1e + 511e: 91 f4 + 5120: 7e 06 + 5122: 40 25 + 5124: 8a 00 + 5126: 1e 22 + 5128: 91 f4 + 512a: 7e 06 + 512c: 76 00 + 512e: 1a 8a + 5130: 00 1e + 5132: 40 25 + 5134: 22 76 + 5136: 00 1a + 5138: 40 24 + 513a: 22 9f + 513c: bc 0b + 513e: 00 00 + 5140: d0 0b + 5142: 00 00 + 5144: 44 00 + 5146: 91 8c + 5148: 7f 06 76 00 + 514c: 1a 91 + 514e: f4 7e + 5150: 06 76 + 5152: 00 1a + 5154: 1e 76 + 5156: 00 1a + 5158: 91 f4 + 515a: 7e 06 + 515c: 76 00 + 515e: 1a 81 + 5160: 00 1e + 5162: 91 8c + 5164: 7f 06 76 00 + 5168: 1a 91 + 516a: f4 7e + 516c: 06 40 + 516e: 25 1e + 5170: 22 91 + 5172: 8c 7f + 5174: 06 76 + 5176: 00 1a + 5178: 91 f4 + 517a: 7e 06 + 517c: 76 00 + 517e: 1a 1e + 5180: 40 25 + 5182: 22 76 + 5184: 00 1a + 5186: 40 24 + 5188: 22 9f + 518a: d0 0b + 518c: 00 00 + 518e: e8 0b + 5190: 00 00 + 5192: 48 00 + 5194: 91 8c + 5196: 7f 06 76 00 + 519a: 1a 91 + 519c: f4 7e + 519e: 06 76 + 51a0: 00 1a + 51a2: 1e 76 + 51a4: 00 1a + 51a6: 91 f4 + 51a8: 7e 06 + 51aa: 76 00 + 51ac: 1a 91 + 51ae: 8c 7f + 51b0: 06 40 + 51b2: 25 1e + 51b4: 91 8c + 51b6: 7f 06 76 00 + 51ba: 1a 91 + 51bc: f4 7e + 51be: 06 40 + 51c0: 25 1e + 51c2: 22 91 + 51c4: 8c 7f + 51c6: 06 76 + 51c8: 00 1a + 51ca: 91 f4 + 51cc: 7e 06 + 51ce: 76 00 + 51d0: 1a 1e + 51d2: 40 25 + 51d4: 22 76 + 51d6: 00 1a + 51d8: 40 24 + 51da: 22 9f + 51dc: e8 0b + 51de: 00 00 + 51e0: c8 0c + 51e2: 00 00 + 51e4: 50 00 + 51e6: 91 8c + 51e8: 7f 06 0a ff + 51ec: ff 1a 91 f4 + 51f0: 7e 06 + 51f2: 0a ff + 51f4: ff 1a 1e 0a + 51f8: ff ff 1a 91 + 51fc: f4 7e + 51fe: 06 0a + 5200: ff ff 1a 91 + 5204: 8c 7f + 5206: 06 40 + 5208: 25 1e + 520a: 91 8c + 520c: 7f 06 0a ff + 5210: ff 1a 91 f4 + 5214: 7e 06 + 5216: 40 25 + 5218: 1e 22 + 521a: 91 8c + 521c: 7f 06 0a ff + 5220: ff 1a 91 f4 + 5224: 7e 06 + 5226: 0a ff + 5228: ff 1a 1e 40 + 522c: 25 22 + 522e: 0a ff + 5230: ff 1a 40 24 + 5234: 22 9f + 5236: c4 0d + 5238: 00 00 + 523a: d0 0d + 523c: 00 00 + 523e: 50 00 + 5240: 91 8c + 5242: 7f 06 0a ff + 5246: ff 1a 91 f4 + 524a: 7e 06 + 524c: 0a ff + 524e: ff 1a 1e 0a + 5252: ff ff 1a 91 + 5256: f4 7e + 5258: 06 0a + 525a: ff ff 1a 91 + 525e: 8c 7f + 5260: 06 40 + 5262: 25 1e + 5264: 91 8c + 5266: 7f 06 0a ff + 526a: ff 1a 91 f4 + 526e: 7e 06 + 5270: 40 25 + 5272: 1e 22 + 5274: 91 8c + 5276: 7f 06 0a ff + 527a: ff 1a 91 f4 + 527e: 7e 06 + 5280: 0a ff + 5282: ff 1a 1e 40 + 5286: 25 22 + 5288: 0a ff + 528a: ff 1a 40 24 + 528e: 22 9f + ... + 5298: bc 05 + 529a: 00 00 + 529c: c0 05 + 529e: 00 00 + 52a0: 01 00 + 52a2: 61 c0 + 52a4: 05 00 + 52a6: 00 64 + 52a8: 07 00 00 01 + 52ac: 00 66 + 52ae: 40 08 + 52b0: 00 00 + 52b2: 4c 08 + 52b4: 00 00 + 52b6: 01 00 + 52b8: 5a 4c + 52ba: 08 00 + 52bc: 00 20 + 52be: 0a 00 + 52c0: 00 03 + 52c2: 00 91 + 52c4: e0 7e + 52c6: 20 0a + 52c8: 00 00 + 52ca: 60 0b + 52cc: 00 00 + 52ce: 01 00 + 52d0: 55 00 + 52d2: 00 00 + 52d4: 00 00 + 52d6: 00 00 + 52d8: 00 14 + 52da: 06 00 + 52dc: 00 0c + 52de: 07 00 00 01 + 52e2: 00 6b + 52e4: 0c 07 + 52e6: 00 00 + 52e8: a4 07 + 52ea: 00 00 + 52ec: 22 00 + 52ee: 7c 00 + 52f0: 8c 00 + 52f2: 1e 8a + 52f4: 00 1a + 52f6: 8f 00 7c 00 + 52fa: 1e 75 + 52fc: 00 8c + 52fe: 00 1e + 5300: 22 7c + 5302: 00 8c + 5304: 00 1e + 5306: 40 25 + 5308: 22 8a + 530a: 00 1a + 530c: 40 24 + 530e: 22 9f + 5310: a4 07 + 5312: 00 00 + 5314: c8 07 + 5316: 00 00 + 5318: 24 00 + 531a: 7c 00 + 531c: 8c 00 + 531e: 1e 0a + 5320: ff ff 1a 8f + 5324: 00 7c + 5326: 00 1e + 5328: 75 00 + 532a: 8c 00 + 532c: 1e 22 + 532e: 7c 00 + 5330: 8c 00 + 5332: 1e 40 + 5334: 25 22 + 5336: 0a ff + 5338: ff 1a 40 24 + 533c: 22 9f + 533e: c8 07 + 5340: 00 00 + 5342: cc 07 + 5344: 00 00 + 5346: 22 00 + 5348: 7c 00 + 534a: 8c 00 + 534c: 1e 88 + 534e: 7f 1a 8f 00 + 5352: 7c 00 + 5354: 1e 75 + 5356: 00 8c + 5358: 00 1e + 535a: 22 7c + 535c: 00 8c + 535e: 00 1e + 5360: 40 25 + 5362: 22 88 + 5364: 7f 1a 40 24 + 5368: 22 9f + 536a: cc 07 + 536c: 00 00 + 536e: d8 07 + 5370: 00 00 + 5372: 24 00 + 5374: 7c 00 + 5376: 8c 00 + 5378: 1e 0a + 537a: ff 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0d + 88ee: 00 00 + 88f0: d0 0d + 88f2: 00 00 + 88f4: 03 00 91 f8 lb zero, -119(sp) + 88f8: 7e 00 + 88fa: 00 00 + 88fc: 00 00 + 88fe: 00 00 + 8900: 00 78 + 8902: 06 00 + 8904: 00 c8 + 8906: 0c 00 + 8908: 00 03 + 890a: 00 91 + 890c: 80 7f + 890e: c4 0d + 8910: 00 00 + 8912: d0 0d + 8914: 00 00 + 8916: 03 00 91 80 lb zero, -2039(sp) + 891a: 7f 00 00 00 + 891e: 00 00 + 8920: 00 00 + 8922: 00 78 + 8924: 06 00 + 8926: 00 94 + 8928: 0a 00 + 892a: 00 01 + 892c: 00 6e + 892e: 94 0a + 8930: 00 00 + 8932: c8 0c + 8934: 00 00 + 8936: 03 00 91 fa lb zero, -87(sp) + 893a: 7e c4 + 893c: 0d 00 + 893e: 00 d0 + 8940: 0d 00 + 8942: 00 03 + 8944: 00 91 + 8946: fa 7e + ... + 8950: 78 06 + 8952: 00 00 + 8954: 08 08 + 8956: 00 00 + 8958: 01 00 + 895a: 5e 08 + 895c: 08 00 + 895e: 00 c8 + 8960: 0c 00 + 8962: 00 03 + 8964: 00 91 + 8966: 82 7f + 8968: c4 0d + 896a: 00 00 + 896c: d0 0d + 896e: 00 00 + 8970: 03 00 91 82 lb zero, -2007(sp) + 8974: 7f 00 00 00 + 8978: 00 00 + 897a: 00 00 + 897c: 00 d4 + 897e: 06 00 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00 5d + cb28: 00 91 + cb2a: d4 7e + cb2c: 06 40 + cb2e: 4b 24 22 91 fnmsub.s fs0, ft4, fs2, fs2, rdn + cb32: f8 7e + cb34: 06 0a + cb36: ff ff 1a 91 + cb3a: 8c 7f + cb3c: 06 0a + cb3e: ff ff 1a 1e + cb42: 0a ff + cb44: ff 1a 91 f8 + cb48: 7e 06 + cb4a: 0a ff + cb4c: ff 1a 91 8c + cb50: 7f 06 40 25 + cb54: 1e 91 + cb56: 8c 7f + cb58: 06 0a + cb5a: ff ff 1a 91 + cb5e: f8 7e + cb60: 06 40 + cb62: 25 1e + cb64: 22 91 + cb66: f8 7e + cb68: 06 0a + cb6a: ff ff 1a 91 + cb6e: 8c 7f + cb70: 06 0a + cb72: ff ff 1a 1e + cb76: 40 25 + cb78: 22 0a + cb7a: ff ff 1a 40 + cb7e: 24 22 + cb80: 40 4b + cb82: 24 22 + cb84: 2d 9f + ... + cb8e: 80 0b + cb90: 00 00 + cb92: 88 0b + cb94: 00 00 + cb96: 11 00 + cb98: 7b 00 40 4b + cb9c: 24 22 + cb9e: 8e 00 + cba0: 40 4b + cba2: 24 22 + cba4: 2d 08 + cba6: ff 1a 9f 94 + cbaa: 0b 00 00 fc + cbae: 0b 00 00 01 + cbb2: 00 5d + ... + cbbc: a8 0b + cbbe: 00 00 + cbc0: b0 0b + cbc2: 00 00 + cbc4: 01 00 + cbc6: 5e b0 + cbc8: 0b 00 00 30 + cbcc: 0c 00 + cbce: 00 10 + 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cc6e: 00 c8 + cc70: 0c 00 + cc72: 00 12 + cc74: 00 91 + cc76: fc 7e + cc78: 06 0a + cc7a: ff ff 1a 91 + cc7e: 8c 7f + cc80: 06 0a + cc82: ff ff 1a 1e + cc86: 9f c4 0d 00 + cc8a: 00 d0 + cc8c: 0d 00 + cc8e: 00 12 + cc90: 00 91 + cc92: fc 7e + cc94: 06 0a + cc96: ff ff 1a 91 + cc9a: 8c 7f + cc9c: 06 0a + cc9e: ff ff 1a 1e + cca2: 9f 00 00 00 + cca6: 00 00 + cca8: 00 00 + ccaa: 00 b8 + ccac: 0b 00 00 c4 + ccb0: 0b 00 00 06 + ccb4: 00 81 + ccb6: 00 77 + ccb8: 00 1e + ccba: 9f c4 0b 00 + ccbe: 00 c8 + ccc0: 0b 00 00 01 + ccc4: 00 57 + ccc6: c8 0b + ccc8: 00 00 + ccca: cc 0b + cccc: 00 00 + ccce: 0b 00 91 fc + ccd2: 7e 06 + ccd4: 76 00 + ccd6: 1a 81 + ccd8: 00 1e + ccda: 9f d0 0b 00 + ccde: 00 ec + cce0: 0b 00 00 01 + cce4: 00 61 + cce6: ec 0b + cce8: 00 00 + ccea: 30 0c + ccec: 00 00 + ccee: 08 00 + ccf0: 7b 00 40 25 + ccf4: 77 00 22 9f + ccf8: 30 0c + ccfa: 00 00 + ccfc: c8 0c + ccfe: 00 00 + cd00: 17 00 91 fc auipc zero, 1034512 + cd04: 7e 06 + cd06: 0a ff + cd08: ff 1a 91 8c + cd0c: 7f 06 0a ff + cd10: ff 1a 1e 40 + cd14: 25 77 + cd16: 00 22 + cd18: 9f c4 0d 00 + cd1c: 00 d0 + cd1e: 0d 00 + cd20: 00 17 + cd22: 00 91 + cd24: fc 7e + cd26: 06 0a + cd28: ff ff 1a 91 + cd2c: 8c 7f + cd2e: 06 0a + cd30: ff ff 1a 1e + cd34: 40 25 + cd36: 77 00 22 9f + ... + cd42: bc 0b + cd44: 00 00 + cd46: c8 0c + cd48: 00 00 + cd4a: 01 00 + cd4c: 6a c4 + cd4e: 0d 00 + cd50: 00 d0 + cd52: 0d 00 + cd54: 00 01 + cd56: 00 6a + ... + cd60: cc 0b + cd62: 00 00 + cd64: 14 0c + cd66: 00 00 + cd68: 01 00 + cd6a: 60 00 + cd6c: 00 00 + cd6e: 00 00 + cd70: 00 00 + cd72: 00 b8 + cd74: 0b 00 00 c8 + cd78: 0c 00 + cd7a: 00 03 + cd7c: 00 91 + cd7e: fc 7e + cd80: c4 0d + cd82: 00 00 + cd84: d0 0d + cd86: 00 00 + cd88: 03 00 91 fc lb zero, -55(sp) + cd8c: 7e 00 + cd8e: 00 00 + cd90: 00 00 + cd92: 00 00 + cd94: 00 b8 + cd96: 0b 00 00 c8 + cd9a: 0c 00 + cd9c: 00 03 + cd9e: 00 91 + cda0: 8c 7f + cda2: c4 0d + cda4: 00 00 + cda6: d0 0d + cda8: 00 00 + cdaa: 03 00 91 8c lb zero, -1847(sp) + cdae: 7f 00 00 00 + cdb2: 00 00 + cdb4: 00 00 + cdb6: 00 b8 + cdb8: 0b 00 00 cc + cdbc: 0b 00 00 01 + cdc0: 00 60 + cdc2: cc 0b + cdc4: 00 00 + cdc6: c8 0c + cdc8: 00 00 + cdca: 03 00 91 fe lb zero, -23(sp) + cdce: 7e c4 + cdd0: 0d 00 + cdd2: 00 d0 + cdd4: 0d 00 + cdd6: 00 03 + cdd8: 00 91 + cdda: fe 7e + ... + cde4: b8 0b + cde6: 00 00 + cde8: d0 0b + cdea: 00 00 + cdec: 01 00 + cdee: 61 d0 + cdf0: 0b 00 00 c8 + cdf4: 0c 00 + cdf6: 00 03 + cdf8: 00 91 + cdfa: 8e 7f + cdfc: c4 0d + cdfe: 00 00 + ce00: d0 0d + ce02: 00 00 + ce04: 03 00 91 8e lb zero, -1815(sp) + ce08: 7f 00 00 00 + ce0c: 00 00 + ce0e: 00 00 + ce10: 00 00 + ce12: 0c 00 + ce14: 00 30 + ce16: 0c 00 + ce18: 00 01 + ce1a: 00 5c + ... + ce24: 24 0c + ce26: 00 00 + ce28: c8 0c + ce2a: 00 00 + ce2c: 02 00 + ce2e: 3d 9f + ce30: c4 0d + ce32: 00 00 + ce34: d0 0d + ce36: 00 00 + ce38: 02 00 + ce3a: 3d 9f + ... + ce44: 24 0c + ce46: 00 00 + ce48: c8 0c + ce4a: 00 00 + ce4c: 02 00 + ce4e: 43 9f c4 0d + ce52: 00 00 + ce54: d0 0d + ce56: 00 00 + ce58: 02 00 + ce5a: 43 9f 00 00 fmadd.s ft10, ft1, ft0, ft0, rtz + ce5e: 00 00 + ce60: 00 00 + ce62: 00 00 + ce64: 24 0c + ce66: 00 00 + ce68: c8 0c + ce6a: 00 00 + ce6c: 02 00 + ce6e: 33 9f c4 0d + ce72: 00 00 + ce74: d0 0d + ce76: 00 00 + ce78: 02 00 + ce7a: 33 9f 00 00 sll t5, ra, zero + ce7e: 00 00 + ce80: 00 00 + ce82: 00 00 + ce84: 24 0c + ce86: 00 00 + ce88: 28 0c + ce8a: 00 00 + ce8c: 02 00 + ce8e: 33 9f 28 0c + ce92: 00 00 + ce94: 30 0c + ce96: 00 00 + ce98: 02 00 + ce9a: 30 9f + ... + cea4: 24 0c + cea6: 00 00 + cea8: 68 0c + ceaa: 00 00 + ceac: 01 00 + ceae: 64 00 + ceb0: 00 00 + ceb2: 00 00 + ceb4: 00 00 + ceb6: 00 80 + ceb8: 0c 00 + ceba: 00 c8 + cebc: 0c 00 + cebe: 00 02 + cec0: 00 4f + cec2: 9f 00 00 00 + cec6: 00 00 + cec8: 00 00 + ceca: 00 80 + cecc: 0c 00 + cece: 00 c8 + ced0: 0c 00 + ced2: 00 02 + ced4: 00 31 + ced6: 9f 00 00 00 + ceda: 00 00 + cedc: 00 00 + cede: 00 80 + cee0: 0c 00 + cee2: 00 c8 + cee4: 0c 00 + cee6: 00 02 + cee8: 00 30 + ceea: 9f 00 00 00 + ceee: 00 00 + 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00 00 + e292: 07 00 8c 00 + e296: 20 7f + e298: 00 22 + e29a: 9f b8 0b 00 + e29e: 00 c0 + e2a0: 0b 00 00 06 + e2a4: 00 78 + e2a6: 00 8c + e2a8: 00 1c + e2aa: 9f c0 0b 00 + e2ae: 00 c4 + e2b0: 0b 00 00 07 + e2b4: 00 8c + e2b6: 00 20 + e2b8: 7f 00 22 9f + e2bc: c4 0b + e2be: 00 00 + e2c0: c8 0b + e2c2: 00 00 + e2c4: 06 00 + e2c6: 78 00 + e2c8: 8c 00 + e2ca: 1c 9f + e2cc: c8 0b + e2ce: 00 00 + e2d0: cc 0b + e2d2: 00 00 + e2d4: 07 00 8c 00 + e2d8: 20 7f + e2da: 00 22 + e2dc: 9f e8 0b 00 + e2e0: 00 f8 + e2e2: 0b 00 00 07 + e2e6: 00 8c + e2e8: 00 20 + e2ea: 7f 00 22 9f + e2ee: 0c 0c + e2f0: 00 00 + e2f2: 94 0c + e2f4: 00 00 + e2f6: 06 00 + e2f8: 78 00 + e2fa: 8c 00 + e2fc: 1c 9f + e2fe: a0 0c + e300: 00 00 + e302: d0 0c + e304: 00 00 + e306: 06 00 + e308: 78 00 + e30a: 8c 00 + e30c: 1c 9f + e30e: d8 0c + e310: 00 00 + e312: e4 0c + e314: 00 00 + e316: 06 00 + e318: 78 00 + e31a: 8c 00 + e31c: 1c 9f + e31e: 28 1a + e320: 00 00 + e322: 34 1a + e324: 00 00 + e326: 01 00 + e328: 56 48 + e32a: 1a 00 + e32c: 00 54 + e32e: 1a 00 + e330: 00 01 + e332: 00 6d + e334: a4 1a + e336: 00 00 + e338: ac 1a + e33a: 00 00 + e33c: 06 00 + e33e: 78 00 + e340: 8c 00 + e342: 1c 9f + e344: ac 1a + e346: 00 00 + e348: b0 1a + e34a: 00 00 + e34c: 07 00 8c 00 + e350: 20 7f + e352: 00 22 + e354: 9f 00 00 00 + e358: 00 00 + e35a: 00 00 + e35c: 00 f4 + e35e: 01 00 + e360: 00 fc + e362: 01 00 + e364: 00 01 + e366: 00 60 + e368: fc 01 + e36a: 00 00 + e36c: 14 02 + e36e: 00 00 + e370: 13 00 7c 00 addi zero, s8, 7 + e374: 40 4b + e376: 24 22 + e378: 91 94 + e37a: 7f 06 40 4b + e37e: 24 22 + e380: 2d 7d + e382: 00 21 + e384: 9f 00 00 00 + e388: 00 00 + e38a: 00 00 + e38c: 00 f4 + e38e: 01 00 + e390: 00 00 + e392: 02 00 + e394: 00 11 + e396: 00 7f + e398: 00 40 + e39a: 4b 24 22 81 fnmsub.s fs0, ft4, fs2, fa6, rdn + e39e: 00 40 + e3a0: 4b 24 22 2d + e3a4: 08 ff + e3a6: 1a 9f + e3a8: 00 02 + e3aa: 00 00 + e3ac: 10 02 + e3ae: 00 00 + e3b0: 14 00 + e3b2: 7a 00 + e3b4: 81 00 + e3b6: 22 40 + e3b8: 4b 24 22 7a + e3bc: 00 40 + e3be: 4b 24 22 2d + e3c2: 08 ff + e3c4: 1a 9f + ... + e3ce: dc 03 + e3d0: 00 00 + e3d2: e8 03 + e3d4: 00 00 + e3d6: 08 00 + e3d8: 8c 00 + e3da: 30 2e + e3dc: 08 ff + e3de: 1a 9f + ... + e3e8: d8 02 + e3ea: 00 00 + e3ec: e8 02 + e3ee: 00 00 + e3f0: 08 00 + e3f2: 08 20 + e3f4: 76 00 + e3f6: 4f 1a 1c 9f + e3fa: 2c 03 + e3fc: 00 00 + e3fe: 44 03 + e400: 00 00 + e402: 08 00 + e404: 08 20 + e406: 76 00 + e408: 4f 1a 1c 9f + ... + e414: d8 02 + e416: 00 00 + e418: e8 02 + e41a: 00 00 + e41c: 05 00 + e41e: 76 00 + e420: 4f 1a 9f 2c + e424: 03 00 00 44 lb zero, 1088(zero) + e428: 03 00 00 05 lb zero, 80(zero) + e42c: 00 76 + e42e: 00 4f + e430: 1a 9f + ... + e43a: d8 02 + e43c: 00 00 + e43e: 1c 03 + e440: 00 00 + e442: 01 00 + e444: 5a 2c + e446: 03 00 00 98 lb zero, -1664(zero) + e44a: 03 00 00 01 lb zero, 16(zero) + e44e: 00 5a + e450: a0 03 + e452: 00 00 + e454: c8 03 + e456: 00 00 + e458: 01 00 + e45a: 5a 00 + e45c: 00 00 + e45e: 00 00 + e460: 00 00 + e462: 00 d8 + e464: 02 00 + e466: 00 e0 + e468: 02 00 + e46a: 00 02 + e46c: 00 30 + e46e: 9f e0 02 00 + e472: 00 f8 + e474: 02 00 + e476: 00 01 + e478: 00 5f + e47a: fc 02 + e47c: 00 00 + e47e: 08 03 + e480: 00 00 + e482: 01 00 + e484: 5f 08 03 00 + e488: 00 10 + e48a: 03 00 00 03 lb zero, 48(zero) + e48e: 00 7f + e490: 7f 9f 10 03 + e494: 00 00 + e496: 18 03 + e498: 00 00 + e49a: 01 00 + e49c: 5f 2c 03 00 + e4a0: 00 3c + e4a2: 03 00 00 01 lb zero, 16(zero) + e4a6: 00 5f + e4a8: 3c 03 + e4aa: 00 00 + e4ac: 40 03 + e4ae: 00 00 + e4b0: 03 00 7f 7f lb zero, 2039(t5) + e4b4: 9f 40 03 00 + e4b8: 00 48 + e4ba: 03 00 00 01 lb zero, 16(zero) + e4be: 00 5f + e4c0: 68 03 + e4c2: 00 00 + e4c4: 70 03 + e4c6: 00 00 + e4c8: 02 00 + e4ca: 30 9f + e4cc: 70 03 + e4ce: 00 00 + e4d0: 90 03 + e4d2: 00 00 + e4d4: 01 00 + e4d6: 6d a0 + e4d8: 03 00 00 c0 lb zero, -1024(zero) + e4dc: 03 00 00 01 lb zero, 16(zero) + e4e0: 00 6d + e4e2: c0 03 + e4e4: 00 00 + e4e6: c4 03 + e4e8: 00 00 + e4ea: 03 00 8d 01 lb zero, 24(s10) + e4ee: 9f c4 03 00 + e4f2: 00 c8 + e4f4: 03 00 00 01 lb zero, 16(zero) + e4f8: 00 6d + e4fa: c8 03 + e4fc: 00 00 + e4fe: e4 03 + e500: 00 00 + e502: 01 00 + e504: 5f 00 00 00 + e508: 00 00 + e50a: 00 00 + e50c: 00 d8 + e50e: 02 00 + e510: 00 e0 + e512: 02 00 + e514: 00 02 + e516: 00 30 + e518: 9f e0 02 00 + e51c: 00 e8 + e51e: 03 00 00 01 lb zero, 16(zero) + e522: 00 6c + ... + e52c: 04 04 + e52e: 00 00 + e530: 0c 04 + e532: 00 00 + e534: 01 00 + e536: 5d 0c + e538: 04 00 + e53a: 00 48 + e53c: 04 00 + e53e: 00 11 + e540: 00 72 + e542: 00 06 + e544: 40 4b + e546: 24 22 + e548: 91 b0 + e54a: 7f 06 40 4b + e54e: 24 22 + e550: 2b 9f 00 00 + e554: 00 00 + e556: 00 00 + e558: 00 00 + e55a: 04 04 + e55c: 00 00 + e55e: 18 04 + e560: 00 00 + e562: 11 00 + e564: 7c 00 + e566: 40 4b + e568: 24 22 + e56a: 80 00 + e56c: 40 4b + e56e: 24 22 + e570: 2d 08 + e572: ff 1a 9f 18 + e576: 04 00 + e578: 00 1c + e57a: 04 00 + e57c: 00 13 + e57e: 00 7c + e580: 00 40 + e582: 4b 24 22 91 fnmsub.s fs0, ft4, fs2, fs2, rdn + e586: 94 7f + e588: 06 40 + e58a: 4b 24 22 2d + e58e: 08 ff + e590: 1a 9f + e592: 1c 04 + e594: 00 00 + e596: 30 04 + e598: 00 00 + e59a: 01 00 + e59c: 60 30 + e59e: 04 00 + e5a0: 00 48 + e5a2: 04 00 + e5a4: 00 13 + e5a6: 00 7c + e5a8: 00 40 + e5aa: 4b 24 22 91 fnmsub.s fs0, ft4, fs2, fs2, rdn + e5ae: 94 7f + e5b0: 06 40 + e5b2: 4b 24 22 2d + e5b6: 7d 00 + e5b8: 21 9f + ... + e5c2: 20 04 + e5c4: 00 00 + e5c6: 28 04 + e5c8: 00 00 + e5ca: 11 00 + e5cc: 7f 00 40 4b + e5d0: 24 22 + e5d2: 81 00 + e5d4: 40 4b + e5d6: 24 22 + e5d8: 2d 08 + e5da: ff 1a 9f 28 + e5de: 04 00 + e5e0: 00 2c + e5e2: 04 00 + e5e4: 00 16 + e5e6: 00 81 + e5e8: 00 91 + e5ea: a8 7f + e5ec: 06 22 + e5ee: 40 4b + e5f0: 24 22 + e5f2: 81 00 + e5f4: 40 4b + e5f6: 24 22 + e5f8: 2d 08 + e5fa: ff 1a 9f 2c + e5fe: 04 00 + e600: 00 40 + e602: 04 00 + e604: 00 1a + e606: 00 91 + e608: 98 7f + e60a: 06 91 + e60c: a8 7f + e60e: 06 22 + e610: 40 4b + e612: 24 22 + e614: 91 98 + e616: 7f 06 40 4b + e61a: 24 22 + e61c: 2d 08 + e61e: ff 1a 9f 00 + e622: 00 00 + e624: 00 00 + e626: 00 00 + e628: 00 8c + e62a: 07 00 00 98 + e62e: 07 00 00 08 + e632: 00 8e + e634: 00 30 + e636: 2e 08 + e638: ff 1a 9f 00 + e63c: 00 00 + e63e: 00 00 + e640: 00 00 + e642: 00 78 + e644: 06 00 + e646: 00 a4 + e648: 06 00 + e64a: 00 0d + e64c: 00 08 + e64e: 20 8d + e650: 00 08 + e652: 20 14 + e654: 14 1b + e656: 1e 1c + e658: 1c 9f + e65a: d4 06 + e65c: 00 00 + e65e: f4 06 + e660: 00 00 + e662: 0d 00 + e664: 08 20 + e666: 8d 00 + e668: 08 20 + e66a: 14 14 + e66c: 1b 1e 1c 1c + e670: 9f 00 00 00 + e674: 00 00 + e676: 00 00 + e678: 00 78 + e67a: 06 00 + e67c: 00 a4 + e67e: 06 00 + e680: 00 0a + e682: 00 8d + e684: 00 08 + e686: 20 14 + e688: 14 1b + e68a: 1e 1c + e68c: 9f d4 06 00 + e690: 00 f4 + e692: 06 00 + e694: 00 0a + e696: 00 8d + e698: 00 08 + e69a: 20 14 + e69c: 14 1b + e69e: 1e 1c + e6a0: 9f 00 00 00 + e6a4: 00 00 + e6a6: 00 00 + e6a8: 00 78 + e6aa: 06 00 + e6ac: 00 c4 + e6ae: 06 00 + e6b0: 00 01 + e6b2: 00 56 + e6b4: d4 06 + e6b6: 00 00 + e6b8: 48 07 + e6ba: 00 00 + e6bc: 01 00 + e6be: 56 50 + e6c0: 07 00 00 78 + e6c4: 07 00 00 01 + e6c8: 00 56 + ... + e6d2: 78 06 + e6d4: 00 00 + e6d6: 80 06 + e6d8: 00 00 + e6da: 02 00 + e6dc: 30 9f + e6de: 80 06 + e6e0: 00 00 + e6e2: 94 06 + e6e4: 00 00 + e6e6: 01 00 + e6e8: 5f a4 06 00 + e6ec: 00 b0 + e6ee: 06 00 + e6f0: 00 01 + e6f2: 00 5f + e6f4: b0 06 + e6f6: 00 00 + e6f8: b8 06 + e6fa: 00 00 + e6fc: 03 00 7f 7f lb zero, 2039(t5) + e700: 9f b8 06 00 + e704: 00 c0 + e706: 06 00 + e708: 00 01 + e70a: 00 5f + e70c: d4 06 + e70e: 00 00 + e710: e4 06 + e712: 00 00 + e714: 01 00 + e716: 5f e4 06 00 + e71a: 00 e8 + e71c: 06 00 + e71e: 00 03 + e720: 00 7f + e722: 7f 9f e8 06 + e726: 00 00 + e728: ec 06 + e72a: 00 00 + e72c: 01 00 + e72e: 5f 18 07 00 + e732: 00 20 + e734: 07 00 00 02 + e738: 00 30 + e73a: 9f 20 07 00 + e73e: 00 40 + e740: 07 00 00 01 + e744: 00 55 + e746: 50 07 + e748: 00 00 + e74a: 70 07 + e74c: 00 00 + e74e: 01 00 + e750: 55 70 + e752: 07 00 00 74 + e756: 07 00 00 03 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+ e7f8: 06 40 + e7fa: 4b 24 22 2d + e7fe: 08 ff + e800: 1a 9f + e802: cc 07 + e804: 00 00 + e806: e0 07 + e808: 00 00 + e80a: 01 00 + e80c: 5c e0 + e80e: 07 00 00 fc + e812: 07 00 00 2f + e816: 00 7d + e818: 00 40 + e81a: 4b 24 22 91 fnmsub.s fs0, ft4, fs2, fs2, rdn + e81e: a4 7f + e820: 06 40 + e822: 4b 24 22 2d + e826: 91 b4 + e828: 7f 06 40 4b + e82c: 24 22 + e82e: 91 a0 + e830: 7f 06 40 4b + e834: 24 22 + e836: 91 b0 + e838: 7f 06 40 4b + e83c: 24 22 + e83e: 2b 40 4b 24 + e842: 22 2d + e844: 21 9f + ... + e84e: d0 07 + e850: 00 00 + e852: d8 07 + e854: 00 00 + e856: 11 00 + e858: 7f 00 40 4b + e85c: 24 22 + e85e: 7b 00 40 4b + e862: 24 22 + e864: 2d 08 + e866: ff 1a 9f d8 + e86a: 07 00 00 dc + e86e: 07 00 00 16 + e872: 00 7b + e874: 00 91 + e876: 98 7f + e878: 06 22 + e87a: 40 4b + e87c: 24 22 + e87e: 7b 00 40 4b + e882: 24 22 + e884: 2d 08 + e886: ff 1a 9f dc + e88a: 07 00 00 f0 + e88e: 07 00 00 1a + e892: 00 91 + e894: a8 7f + e896: 06 91 + e898: 98 7f + e89a: 06 22 + e89c: 40 4b + e89e: 24 22 + e8a0: 91 a8 + e8a2: 7f 06 40 4b + e8a6: 24 22 + e8a8: 2d 08 + e8aa: ff 1a 9f 00 + e8ae: 00 00 + e8b0: 00 00 + e8b2: 00 00 + e8b4: 00 48 + e8b6: 09 00 + e8b8: 00 54 + e8ba: 09 00 + e8bc: 00 01 + e8be: 00 5d + e8c0: 54 09 + e8c2: 00 00 + e8c4: a4 09 + e8c6: 00 00 + e8c8: 11 00 + e8ca: 72 00 + e8cc: 06 40 + e8ce: 4b 24 22 91 fnmsub.s fs0, ft4, fs2, fs2, rdn + e8d2: b0 7f + e8d4: 06 40 + e8d6: 4b 24 22 2b + e8da: 9f 00 00 00 + e8de: 00 00 + e8e0: 00 00 + e8e2: 00 48 + e8e4: 09 00 + e8e6: 00 78 + e8e8: 09 00 + e8ea: 00 11 + e8ec: 00 7f + e8ee: 00 40 + e8f0: 4b 24 22 8e + e8f4: 00 40 + e8f6: 4b 24 22 2d + e8fa: 08 ff + e8fc: 1a 9f + ... + e906: 7c 0b + e908: 00 00 + e90a: a4 0b + e90c: 00 00 + e90e: 02 00 + e910: 33 9f 00 00 sll t5, ra, zero + e914: 00 00 + e916: 00 00 + e918: 00 00 + e91a: 7c 0b + e91c: 00 00 + e91e: a4 0b + e920: 00 00 + e922: 02 00 + e924: 4d 9f + ... + e92e: 7c 0b + e930: 00 00 + e932: a4 0b + e934: 00 00 + e936: 02 00 + e938: 30 9f + ... + e942: 7c 0b + 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00 56 + f22a: cc 0f + f22c: 00 00 + f22e: e4 0f + f230: 00 00 + f232: 01 00 + f234: 5a e4 + f236: 0f 00 00 ec + f23a: 0f 00 00 02 fence r, unknown + f23e: 00 31 + f240: 9f 00 00 00 + f244: 00 00 + f246: 00 00 + f248: 00 dc + f24a: 0f 00 00 ec + f24e: 0f 00 00 01 fence w, unknown + f252: 00 6c + f254: ec 0f + f256: 00 00 + f258: f4 0f + f25a: 00 00 + f25c: 06 00 + f25e: 7b 00 8c 00 + f262: 21 9f + f264: f4 0f + f266: 00 00 + f268: 10 10 + f26a: 00 00 + f26c: 01 00 + f26e: 5b 00 00 00 + f272: 00 00 + f274: 00 00 + f276: 00 b4 + f278: 10 00 + f27a: 00 b8 + f27c: 10 00 + f27e: 00 05 + f280: 00 5d + f282: 93 04 93 08 addi s1, t1, 137 + f286: b8 10 + f288: 00 00 + f28a: c4 10 + f28c: 00 00 + f28e: 08 00 + f290: 5d 93 + f292: 04 5f + f294: 93 04 93 04 addi s1, t1, 73 + f298: c4 10 + f29a: 00 00 + f29c: dc 10 + f29e: 00 00 + f2a0: 08 00 + f2a2: 5d 93 + f2a4: 04 60 + f2a6: 93 04 93 04 addi s1, t1, 73 + f2aa: dc 10 + f2ac: 00 00 + f2ae: e4 10 + f2b0: 00 00 + f2b2: 09 00 + f2b4: 5d 93 + f2b6: 04 60 + f2b8: 93 04 5f 93 addi s1, t5, -1739 + f2bc: 04 e4 + f2be: 10 00 + f2c0: 00 14 + f2c2: 11 00 + f2c4: 00 09 + f2c6: 00 5d + f2c8: 93 04 60 93 addi s1, zero, -1738 + f2cc: 04 5f + f2ce: 93 04 00 00 mv s1, zero + f2d2: 00 00 + f2d4: 00 00 + f2d6: 00 00 + f2d8: b4 10 + f2da: 00 00 + f2dc: e0 10 + f2de: 00 00 + f2e0: 11 00 + f2e2: 7e 00 + f2e4: 40 4b + f2e6: 24 22 + f2e8: 7d 00 + f2ea: 40 4b + f2ec: 24 22 + f2ee: 2d 08 + f2f0: ff 1a 9f e0 + f2f4: 10 00 + f2f6: 00 14 + f2f8: 11 00 + f2fa: 00 13 + f2fc: 00 91 + f2fe: a0 7f + f300: 06 40 + f302: 4b 24 22 7d + f306: 00 40 + f308: 4b 24 22 2d + f30c: 08 ff + f30e: 1a 9f + ... + f318: c0 10 + f31a: 00 00 + f31c: d8 10 + f31e: 00 00 + f320: 01 00 + f322: 6c d8 + f324: 10 00 + f326: 00 e8 + f328: 10 00 + f32a: 00 01 + f32c: 00 56 + f32e: e8 10 + f330: 00 00 + f332: f0 10 + f334: 00 00 + f336: 02 00 + f338: 31 9f + ... + f342: e0 10 + f344: 00 00 + f346: f0 10 + f348: 00 00 + f34a: 01 00 + f34c: 5e f0 + f34e: 10 00 + f350: 00 f8 + f352: 10 00 + f354: 00 06 + f356: 00 7c + f358: 00 7e + f35a: 00 21 + f35c: 9f f8 10 00 + f360: 00 14 + f362: 11 00 + f364: 00 01 + f366: 00 5c + ... + f370: dc 12 + f372: 00 00 + f374: e8 12 + f376: 00 00 + f378: 08 00 + f37a: 77 00 30 2e + f37e: 08 ff + f380: 1a 9f + ... + f38a: c4 11 + f38c: 00 00 + f38e: f0 11 + f390: 00 00 + f392: 0d 00 + f394: 08 20 + f396: 7f 00 08 20 + f39a: 14 14 + f39c: 1b 1e 1c 1c + f3a0: 9f 24 12 00 + f3a4: 00 44 + f3a6: 12 00 + f3a8: 00 0d + f3aa: 00 08 + f3ac: 20 7f + f3ae: 00 08 + f3b0: 20 14 + f3b2: 14 1b + f3b4: 1e 1c + f3b6: 1c 9f + ... + f3c0: c4 11 + f3c2: 00 00 + f3c4: f0 11 + f3c6: 00 00 + f3c8: 0a 00 + f3ca: 7f 00 08 20 + f3ce: 14 14 + f3d0: 1b 1e 1c 9f + f3d4: 24 12 + f3d6: 00 00 + f3d8: 44 12 + f3da: 00 00 + f3dc: 0a 00 + f3de: 7f 00 08 20 + f3e2: 14 14 + f3e4: 1b 1e 1c 9f + ... + f3f0: c4 11 + f3f2: 00 00 + f3f4: 14 12 + f3f6: 00 00 + f3f8: 01 00 + f3fa: 55 24 + f3fc: 12 00 + f3fe: 00 98 + f400: 12 00 + f402: 00 01 + f404: 00 55 + f406: a0 12 + f408: 00 00 + f40a: c8 12 + f40c: 00 00 + f40e: 01 00 + f410: 55 00 + f412: 00 00 + f414: 00 00 + f416: 00 00 + f418: 00 c4 + f41a: 11 00 + f41c: 00 cc + f41e: 11 00 + f420: 00 02 + f422: 00 30 + f424: 9f cc 11 00 + f428: 00 e0 + f42a: 11 00 + f42c: 00 01 + f42e: 00 5d + f430: f4 11 + f432: 00 00 + f434: 00 12 + f436: 00 00 + f438: 01 00 + f43a: 5f 00 12 00 + f43e: 00 08 + f440: 12 00 + f442: 00 03 + f444: 00 7f + f446: 7f 9f 08 12 + f44a: 00 00 + f44c: 24 12 + f44e: 00 00 + f450: 01 00 + f452: 5f 24 12 00 + f456: 00 34 + f458: 12 00 + f45a: 00 01 + f45c: 00 5d + f45e: 34 12 + f460: 00 00 + f462: 38 12 + f464: 00 00 + f466: 03 00 7d 7f lb zero, 2039(s10) + f46a: 9f 38 12 00 + f46e: 00 3c + f470: 12 00 + f472: 00 01 + f474: 00 5d + f476: 68 12 + f478: 00 00 + f47a: 70 12 + f47c: 00 00 + f47e: 02 00 + f480: 30 9f + f482: 70 12 + f484: 00 00 + f486: 90 12 + f488: 00 00 + f48a: 01 00 + f48c: 5a a0 + f48e: 12 00 + f490: 00 c0 + f492: 12 00 + f494: 00 01 + f496: 00 5a + f498: c0 12 + f49a: 00 00 + f49c: c4 12 + f49e: 00 00 + f4a0: 03 00 7a 01 lb zero, 23(s4) + f4a4: 9f c4 12 00 + f4a8: 00 c8 + f4aa: 12 00 + f4ac: 00 01 + f4ae: 00 5a + f4b0: c8 12 + f4b2: 00 00 + f4b4: e0 12 + f4b6: 00 00 + f4b8: 01 00 + f4ba: 5d 00 + f4bc: 00 00 + f4be: 00 00 + f4c0: 00 00 + f4c2: 00 c4 + f4c4: 11 00 + f4c6: 00 cc + f4c8: 11 00 + f4ca: 00 02 + f4cc: 00 30 + f4ce: 9f cc 11 00 + f4d2: 00 e8 + f4d4: 12 00 + f4d6: 00 01 + f4d8: 00 57 + ... + f4e2: f8 12 + f4e4: 00 00 + f4e6: fc 12 + f4e8: 00 00 + f4ea: 05 00 + f4ec: 5d 93 + f4ee: 04 93 + f4f0: 08 fc + f4f2: 12 00 + f4f4: 00 08 + f4f6: 13 00 00 08 addi zero, zero, 128 + f4fa: 00 5d + f4fc: 93 04 5c 93 addi s1, s8, -1739 + f500: 04 93 + f502: 04 08 + f504: 13 00 00 28 addi zero, zero, 640 + f508: 13 00 00 08 addi zero, zero, 128 + f50c: 00 5d + f50e: 93 04 5c 93 addi s1, s8, -1739 + f512: 04 93 + f514: 04 28 + f516: 13 00 00 30 addi zero, zero, 768 + f51a: 13 00 00 09 addi zero, zero, 144 + f51e: 00 5d + f520: 93 04 5c 93 addi s1, s8, -1739 + f524: 04 5e + f526: 93 04 30 13 addi s1, zero, 307 + f52a: 00 00 + f52c: 68 13 + f52e: 00 00 + f530: 09 00 + f532: 5d 93 + f534: 04 5c + f536: 93 04 5e 93 addi s1, t3, -1739 + f53a: 04 00 + f53c: 00 00 + f53e: 00 00 + f540: 00 00 + f542: 00 f8 + f544: 12 00 + f546: 00 28 + f548: 13 00 00 11 addi zero, zero, 272 + f54c: 00 7e + f54e: 00 40 + f550: 4b 24 22 7d + f554: 00 40 + f556: 4b 24 22 2d + f55a: 08 ff + f55c: 1a 9f + f55e: 28 13 + f560: 00 00 + f562: 68 13 + f564: 00 00 + f566: 13 00 91 a0 addi zero, sp, -1527 + f56a: 7f 06 40 4b + f56e: 24 22 + f570: 7d 00 + f572: 40 4b + f574: 24 22 + f576: 2d 08 + f578: ff 1a 9f 00 + f57c: 00 00 + f57e: 00 00 + f580: 00 00 + f582: 00 04 + f584: 13 00 00 20 addi zero, zero, 512 + f588: 13 00 00 01 addi zero, zero, 16 + f58c: 00 5a + f58e: 20 13 + f590: 00 00 + f592: 34 13 + f594: 00 00 + f596: 01 00 + f598: 56 34 + f59a: 13 00 00 3c addi zero, zero, 960 + f59e: 13 00 00 02 addi zero, zero, 32 + f5a2: 00 31 + f5a4: 9f 00 00 00 + f5a8: 00 00 + f5aa: 00 00 + f5ac: 00 2c + f5ae: 13 00 00 3c addi zero, zero, 960 + f5b2: 13 00 00 01 addi zero, zero, 16 + f5b6: 00 60 + f5b8: 3c 13 + f5ba: 00 00 + f5bc: 44 13 + f5be: 00 00 + f5c0: 06 00 + f5c2: 7f 00 80 00 + f5c6: 21 9f + f5c8: 44 13 + f5ca: 00 00 + f5cc: 60 13 + f5ce: 00 00 + f5d0: 01 00 + f5d2: 5f 00 00 00 + f5d6: 00 00 + f5d8: 00 00 + f5da: 00 fc + f5dc: 13 00 00 00 nop + f5e0: 14 00 + f5e2: 00 05 + f5e4: 00 5f + f5e6: 93 04 93 08 addi s1, t1, 137 + f5ea: 00 14 + f5ec: 00 00 + f5ee: 0c 14 + f5f0: 00 00 + f5f2: 08 00 + f5f4: 5f 93 04 57 + f5f8: 93 04 93 04 addi s1, t1, 73 + f5fc: 0c 14 + f5fe: 00 00 + f600: 20 14 + f602: 00 00 + f604: 08 00 + f606: 5f 93 04 6f + f60a: 93 04 93 04 addi s1, t1, 73 + f60e: 20 14 + f610: 00 00 + f612: 28 14 + f614: 00 00 + f616: 09 00 + f618: 5f 93 04 6f + f61c: 93 04 55 93 addi s1, a0, -1739 + f620: 04 28 + f622: 14 00 + f624: 00 64 + f626: 14 00 + f628: 00 09 + f62a: 00 5f + f62c: 93 04 6f 93 addi s1, t5, -1738 + f630: 04 65 + f632: 93 04 64 14 addi s1, s0, 326 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22 + f6c4: 2d 08 + f6c6: ff 1a 9f 64 + f6ca: 14 00 + f6cc: 00 b0 + f6ce: 14 00 + f6d0: 00 14 + f6d2: 00 72 + f6d4: 00 06 + f6d6: 40 4b + f6d8: 24 22 + f6da: 91 b0 + f6dc: 7f 06 40 4b + f6e0: 24 22 + f6e2: 2d 08 + f6e4: ff 1a 9f b0 + f6e8: 14 00 + f6ea: 00 b8 + f6ec: 14 00 + f6ee: 00 16 + f6f0: 00 72 + f6f2: 00 06 + f6f4: 40 4b + f6f6: 24 22 + f6f8: 72 00 + f6fa: 06 7e + f6fc: 00 1c + f6fe: 40 4b + f700: 24 22 + f702: 2d 08 + f704: ff 1a 9f b8 + f708: 14 00 + f70a: 00 bc + f70c: 14 00 + f70e: 00 11 + f710: 00 7d + f712: 00 40 + f714: 4b 24 22 7f + f718: 00 40 + f71a: 4b 24 22 2d + f71e: 08 ff + f720: 1a 9f + f722: bc 14 + f724: 00 00 + f726: cc 14 + f728: 00 00 + f72a: 13 00 7d 00 addi zero, s10, 7 + f72e: 40 4b + f730: 24 22 + f732: 91 b0 + f734: 7f 06 40 4b + f738: 24 22 + f73a: 2d 08 + f73c: ff 1a 9f 00 + f740: 00 00 + f742: 00 00 + f744: 00 00 + f746: 00 08 + f748: 14 00 + f74a: 00 20 + f74c: 14 00 + f74e: 00 01 + f750: 00 60 + f752: 20 14 + f754: 00 00 + f756: 30 14 + f758: 00 00 + f75a: 01 00 + f75c: 6c 30 + f75e: 14 00 + f760: 00 34 + f762: 14 00 + f764: 00 02 + f766: 00 31 + f768: 9f 00 00 00 + f76c: 00 00 + f76e: 00 00 + f770: 00 24 + f772: 14 00 + f774: 00 34 + f776: 14 00 + f778: 00 01 + f77a: 00 66 + f77c: 34 14 + f77e: 00 00 + f780: 3c 14 + f782: 00 00 + f784: 06 00 + f786: 84 00 + f788: 86 00 + f78a: 21 9f + f78c: 3c 14 + f78e: 00 00 + f790: cc 14 + f792: 00 00 + f794: 01 00 + f796: 64 00 + f798: 00 00 + f79a: 00 00 + f79c: 00 00 + f79e: 00 5c + f7a0: 14 00 + f7a2: 00 60 + f7a4: 14 00 + f7a6: 00 05 + f7a8: 00 5d + f7aa: 93 04 93 08 addi s1, t1, 137 + f7ae: 60 14 + f7b0: 00 00 + f7b2: 6c 14 + f7b4: 00 00 + f7b6: 08 00 + f7b8: 5d 93 + f7ba: 04 5c + f7bc: 93 04 93 04 addi s1, t1, 73 + f7c0: 6c 14 + f7c2: 00 00 + f7c4: 80 14 + f7c6: 00 00 + f7c8: 08 00 + f7ca: 5d 93 + f7cc: 04 5c + f7ce: 93 04 93 04 addi s1, t1, 73 + f7d2: 80 14 + f7d4: 00 00 + f7d6: 8c 14 + f7d8: 00 00 + f7da: 09 00 + f7dc: 5d 93 + f7de: 04 5c + f7e0: 93 04 5b 93 addi s1, s6, -1739 + f7e4: 04 8c + f7e6: 14 00 + f7e8: 00 b8 + f7ea: 14 00 + f7ec: 00 09 + f7ee: 00 5d + f7f0: 93 04 5c 93 addi s1, s8, -1739 + f7f4: 04 5b + f7f6: 93 04 00 00 mv s1, zero + f7fa: 00 00 + f7fc: 00 00 + f7fe: 00 00 + f800: 5c 14 + f802: 00 00 + f804: b8 14 + f806: 00 00 + f808: 11 00 + f80a: 7e 00 + f80c: 40 4b + f80e: 24 22 + f810: 7d 00 + f812: 40 4b + f814: 24 22 + f816: 2d 08 + f818: ff 1a 9f 00 + f81c: 00 00 + f81e: 00 00 + f820: 00 00 + f822: 00 68 + f824: 14 00 + f826: 00 90 + f828: 14 00 + f82a: 00 01 + f82c: 00 56 + f82e: 90 14 + f830: 00 00 + f832: 94 14 + f834: 00 00 + f836: 02 00 + f838: 31 9f + ... + f842: 84 14 + f844: 00 00 + f846: 94 14 + f848: 00 00 + f84a: 01 00 + f84c: 61 94 + f84e: 14 00 + f850: 00 9c + f852: 14 00 + f854: 00 06 + f856: 00 80 + f858: 00 81 + f85a: 00 21 + f85c: 9f 9c 14 00 + f860: 00 a0 + f862: 14 00 + f864: 00 01 + f866: 00 60 + ... + f870: 64 15 + f872: 00 00 + f874: a8 15 + f876: 00 00 + f878: 02 00 + f87a: 33 9f 00 00 sll t5, ra, zero + f87e: 00 00 + f880: 00 00 + f882: 00 00 + f884: 64 15 + f886: 00 00 + f888: a8 15 + f88a: 00 00 + f88c: 02 00 + f88e: 4d 9f + ... + f898: 64 15 + f89a: 00 00 + f89c: a8 15 + f89e: 00 00 + f8a0: 02 00 + f8a2: 30 9f + ... + f8ac: 64 15 + f8ae: 00 00 + f8b0: 68 15 + f8b2: 00 00 + f8b4: 02 00 + f8b6: 33 9f 88 15 + f8ba: 00 00 + f8bc: a8 15 + f8be: 00 00 + f8c0: 03 00 09 ff lb zero, -16(s2) + f8c4: 9f 00 00 00 + f8c8: 00 00 + f8ca: 00 00 + f8cc: 00 14 + f8ce: 15 00 + f8d0: 00 3c + f8d2: 15 00 + f8d4: 00 02 + f8d6: 00 33 + f8d8: 9f 00 00 00 + f8dc: 00 00 + f8de: 00 00 + f8e0: 00 14 + f8e2: 15 00 + f8e4: 00 3c + f8e6: 15 00 + f8e8: 00 02 + f8ea: 00 4d + f8ec: 9f 00 00 00 + f8f0: 00 00 + f8f2: 00 00 + f8f4: 00 14 + f8f6: 15 00 + f8f8: 00 3c + f8fa: 15 00 + f8fc: 00 02 + f8fe: 00 30 + f900: 9f 00 00 00 + f904: 00 00 + f906: 00 00 + f908: 00 a4 + f90a: 0b 00 00 b8 + f90e: 0b 00 00 03 + f912: 00 09 + f914: ff 9f 14 15 + f918: 00 00 + f91a: 18 15 + f91c: 00 00 + f91e: 02 00 + f920: 33 9f 00 00 sll t5, ra, zero + f924: 00 00 + f926: 00 00 + f928: 00 00 + f92a: e4 15 + f92c: 00 00 + f92e: e8 15 + f930: 00 00 + f932: 05 00 + f934: 60 93 + f936: 04 93 + f938: 08 e8 + f93a: 15 00 + f93c: 00 f4 + f93e: 15 00 + f940: 00 08 + f942: 00 60 + f944: 93 04 64 93 addi s1, s0, -1738 + f948: 04 93 + f94a: 04 f4 + f94c: 15 00 + f94e: 00 08 + f950: 16 00 + f952: 00 08 + f954: 00 60 + f956: 93 04 55 93 addi s1, a0, -1739 + f95a: 04 93 + f95c: 04 08 + f95e: 16 00 + f960: 00 10 + f962: 16 00 + f964: 00 09 + f966: 00 60 + f968: 93 04 55 93 addi s1, a0, -1739 + f96c: 04 57 + f96e: 93 04 10 16 addi s1, zero, 353 + f972: 00 00 + f974: 4c 16 + f976: 00 00 + f978: 09 00 + f97a: 60 93 + f97c: 04 55 + f97e: 93 04 66 93 addi s1, a2, -1738 + f982: 04 4c + f984: 16 00 + f986: 00 94 + f988: 16 00 + f98a: 00 0b + f98c: 00 91 + f98e: b0 7f + f990: 93 04 55 93 addi s1, a0, -1739 + f994: 04 66 + f996: 93 04 94 16 addi s1, s0, 361 + f99a: 00 00 + f99c: 98 16 + f99e: 00 00 + f9a0: 0f 00 72 00 + f9a4: 06 7e + f9a6: 00 1c + f9a8: 9f 93 04 55 + f9ac: 93 04 66 93 addi s1, a2, -1738 + f9b0: 04 fc + f9b2: 16 00 + f9b4: 00 00 + f9b6: 17 00 00 09 auipc zero, 36864 + f9ba: 00 60 + f9bc: 93 04 55 93 addi s1, a0, -1739 + f9c0: 04 66 + f9c2: 93 04 00 17 addi s1, zero, 368 + f9c6: 00 00 + f9c8: 14 17 + f9ca: 00 00 + f9cc: 0b 00 91 b0 + f9d0: 7f 93 04 55 + f9d4: 93 04 66 93 addi s1, a2, -1738 + f9d8: 04 00 + f9da: 00 00 + f9dc: 00 00 + f9de: 00 00 + f9e0: 00 e4 + f9e2: 15 00 + f9e4: 00 44 + f9e6: 16 00 + f9e8: 00 11 + f9ea: 00 7d + f9ec: 00 40 + f9ee: 4b 24 22 80 fnmsub.s fs0, ft4, ft2, fa6, rdn + f9f2: 00 40 + f9f4: 4b 24 22 2d + f9f8: 08 ff + f9fa: 1a 9f + f9fc: 44 16 + f9fe: 00 00 + fa00: 4c 16 + fa02: 00 00 + fa04: 12 00 + fa06: 72 00 + fa08: 06 40 + fa0a: 4b 24 22 80 fnmsub.s fs0, ft4, ft2, fa6, rdn + fa0e: 00 40 + fa10: 4b 24 22 2d + fa14: 08 ff + fa16: 1a 9f + fa18: 4c 16 + fa1a: 00 00 + fa1c: 94 16 + fa1e: 00 00 + fa20: 14 00 + fa22: 72 00 + fa24: 06 40 + fa26: 4b 24 22 91 fnmsub.s fs0, ft4, fs2, fs2, rdn + fa2a: b0 7f + fa2c: 06 40 + fa2e: 4b 24 22 2d + fa32: 08 ff + fa34: 1a 9f + fa36: 94 16 + fa38: 00 00 + fa3a: 98 16 + fa3c: 00 00 + fa3e: 16 00 + fa40: 72 00 + fa42: 06 40 + fa44: 4b 24 22 72 + fa48: 00 06 + fa4a: 7e 00 + fa4c: 1c 40 + fa4e: 4b 24 22 2d + fa52: 08 ff + fa54: 1a 9f + fa56: fc 16 + fa58: 00 00 + fa5a: 00 17 + fa5c: 00 00 + fa5e: 11 00 + fa60: 7d 00 + fa62: 40 4b + fa64: 24 22 + fa66: 80 00 + fa68: 40 4b + fa6a: 24 22 + fa6c: 2d 08 + fa6e: ff 1a 9f 00 + fa72: 17 00 00 14 auipc zero, 81920 + fa76: 17 00 00 13 auipc zero, 77824 + fa7a: 00 7d + fa7c: 00 40 + fa7e: 4b 24 22 91 fnmsub.s fs0, ft4, fs2, fs2, rdn + fa82: b0 7f + fa84: 06 40 + fa86: 4b 24 22 2d + fa8a: 08 ff + fa8c: 1a 9f + ... + fa96: f0 15 + fa98: 00 00 + fa9a: 08 16 + fa9c: 00 00 + fa9e: 01 00 + faa0: 6c 08 + faa2: 16 00 + faa4: 00 18 + faa6: 16 00 + faa8: 00 01 + faaa: 00 6f + faac: 18 16 + faae: 00 00 + fab0: 1c 16 + fab2: 00 00 + fab4: 02 00 + fab6: 31 9f + ... + fac0: 0c 16 + fac2: 00 00 + fac4: 1c 16 + fac6: 00 00 + fac8: 01 00 + faca: 67 1c 16 00 + face: 00 24 + fad0: 16 00 + fad2: 00 06 + fad4: 00 85 + fad6: 00 87 + fad8: 00 21 + fada: 9f 24 16 00 + fade: 00 98 + fae0: 16 00 + fae2: 00 01 + fae4: 00 65 + fae6: fc 16 + fae8: 00 00 + faea: 14 17 + faec: 00 00 + faee: 01 00 + faf0: 65 00 + faf2: 00 00 + faf4: 00 00 + faf6: 00 00 + faf8: 00 44 + fafa: 16 00 + fafc: 00 48 + fafe: 16 00 + fb00: 00 05 + fb02: 00 5d + fb04: 93 04 93 08 addi s1, t1, 137 + fb08: 48 16 + fb0a: 00 00 + fb0c: 54 16 + fb0e: 00 00 + fb10: 08 00 + fb12: 5d 93 + fb14: 04 5c + fb16: 93 04 93 04 addi s1, t1, 73 + fb1a: 54 16 + fb1c: 00 00 + fb1e: 68 16 + fb20: 00 00 + fb22: 08 00 + fb24: 5d 93 + fb26: 04 5c + fb28: 93 04 93 04 addi s1, t1, 73 + fb2c: 68 16 + fb2e: 00 00 + fb30: 70 16 + fb32: 00 00 + fb34: 09 00 + fb36: 5d 93 + fb38: 04 5c + fb3a: 93 04 5b 93 addi s1, s6, -1739 + fb3e: 04 70 + fb40: 16 00 + fb42: 00 98 + fb44: 16 00 + fb46: 00 09 + fb48: 00 5d + fb4a: 93 04 5c 93 addi s1, s8, -1739 + fb4e: 04 5b + fb50: 93 04 00 00 mv s1, zero + fb54: 00 00 + fb56: 00 00 + fb58: 00 00 + fb5a: 44 16 + fb5c: 00 00 + fb5e: 98 16 + fb60: 00 00 + fb62: 11 00 + fb64: 7e 00 + fb66: 40 4b + fb68: 24 22 + fb6a: 7d 00 + fb6c: 40 4b + fb6e: 24 22 + fb70: 2d 08 + fb72: ff 1a 9f 00 + fb76: 00 00 + fb78: 00 00 + fb7a: 00 00 + fb7c: 00 50 + fb7e: 16 00 + fb80: 00 74 + fb82: 16 00 + fb84: 00 01 + fb86: 00 56 + fb88: 74 16 + fb8a: 00 00 + fb8c: 78 16 + fb8e: 00 00 + fb90: 02 00 + fb92: 31 9f + ... + fb9c: 6c 16 + fb9e: 00 00 + fba0: 78 16 + fba2: 00 00 + fba4: 01 00 + fba6: 61 78 + fba8: 16 00 + fbaa: 00 80 + fbac: 16 00 + fbae: 00 06 + fbb0: 00 7f + fbb2: 00 81 + fbb4: 00 21 + fbb6: 9f 80 16 00 + fbba: 00 98 + fbbc: 16 00 + fbbe: 00 01 + fbc0: 00 5f + ... + fbca: a4 16 + fbcc: 00 00 + fbce: a8 16 + fbd0: 00 00 + fbd2: 01 00 + fbd4: 5a a8 + fbd6: 16 00 + fbd8: 00 fc + fbda: 16 00 + fbdc: 00 01 + fbde: 00 5f + fbe0: 28 17 + fbe2: 00 00 + fbe4: 30 17 + fbe6: 00 00 + fbe8: 01 00 + fbea: 5a 3c + fbec: 17 00 00 44 auipc zero, 278528 + fbf0: 17 00 00 01 auipc zero, 4096 + fbf4: 00 5a + fbf6: 4c 17 + fbf8: 00 00 + fbfa: 54 17 + fbfc: 00 00 + fbfe: 01 00 + fc00: 5a 54 + fc02: 17 00 00 c8 auipc zero, 819200 + fc06: 17 00 00 01 auipc zero, 4096 + fc0a: 00 5f + fc0c: d0 17 + fc0e: 00 00 + fc10: 00 18 + fc12: 00 00 + fc14: 01 00 + fc16: 5f 34 18 00 + fc1a: 00 58 + fc1c: 18 00 + fc1e: 00 01 + fc20: 00 5f + fc22: 10 19 + fc24: 00 00 + fc26: 24 19 + fc28: 00 00 + fc2a: 01 00 + fc2c: 5f 00 00 00 + fc30: 00 00 + fc32: 00 00 + fc34: 00 b4 + fc36: 16 00 + fc38: 00 c8 + fc3a: 16 00 + fc3c: 00 0a + fc3e: 00 7f + fc40: 00 08 + fc42: 20 14 + fc44: 14 1b + fc46: 1e 1c + fc48: 9f c8 16 00 + fc4c: 00 f4 + fc4e: 16 00 + fc50: 00 01 + fc52: 00 60 + fc54: f4 16 + fc56: 00 00 + fc58: fc 16 + fc5a: 00 00 + fc5c: 0a 00 + fc5e: 7f 00 08 20 + fc62: 14 14 + fc64: 1b 1e 1c 9f + fc68: 54 17 + fc6a: 00 00 + fc6c: 84 17 + fc6e: 00 00 + fc70: 0a 00 + fc72: 7f 00 08 20 + fc76: 14 14 + fc78: 1b 1e 1c 9f + fc7c: 84 17 + fc7e: 00 00 + fc80: a8 17 + fc82: 00 00 + fc84: 01 00 + fc86: 60 a8 + fc88: 17 00 00 c8 auipc zero, 819200 + fc8c: 17 00 00 0a auipc zero, 40960 + fc90: 00 7f + fc92: 00 08 + fc94: 20 14 + fc96: 14 1b + fc98: 1e 1c + fc9a: 9f 10 19 00 + fc9e: 00 24 + fca0: 19 00 + fca2: 00 0a + fca4: 00 7f + fca6: 00 08 + fca8: 20 14 + fcaa: 14 1b + fcac: 1e 1c + fcae: 9f 00 00 00 + fcb2: 00 00 + fcb4: 00 00 + fcb6: 00 b4 + fcb8: 16 00 + fcba: 00 c8 + fcbc: 16 00 + fcbe: 00 0d + fcc0: 00 08 + fcc2: 20 7f + fcc4: 00 08 + fcc6: 20 14 + fcc8: 14 1b + fcca: 1e 1c + fccc: 1c 9f + fcce: c8 16 + fcd0: 00 00 + fcd2: f4 16 + fcd4: 00 00 + fcd6: 06 00 + fcd8: 08 20 + fcda: 80 00 + fcdc: 1c 9f + fcde: f4 16 + fce0: 00 00 + fce2: fc 16 + fce4: 00 00 + fce6: 0d 00 + fce8: 08 20 + fcea: 7f 00 08 20 + fcee: 14 14 + fcf0: 1b 1e 1c 1c + fcf4: 9f 54 17 00 + fcf8: 00 84 + fcfa: 17 00 00 0d auipc zero, 53248 + fcfe: 00 08 + fd00: 20 7f + fd02: 00 08 + fd04: 20 14 + fd06: 14 1b + fd08: 1e 1c + fd0a: 1c 9f + fd0c: 84 17 + fd0e: 00 00 + fd10: a8 17 + fd12: 00 00 + fd14: 06 00 + fd16: 08 20 + fd18: 80 00 + fd1a: 1c 9f + fd1c: a8 17 + fd1e: 00 00 + fd20: c8 17 + fd22: 00 00 + fd24: 0d 00 + fd26: 08 20 + fd28: 7f 00 08 20 + fd2c: 14 14 + fd2e: 1b 1e 1c 1c + fd32: 9f 10 19 00 + fd36: 00 24 + fd38: 19 00 + fd3a: 00 0d + fd3c: 00 08 + fd3e: 20 7f + fd40: 00 08 + fd42: 20 14 + fd44: 14 1b + fd46: 1e 1c + fd48: 1c 9f + ... + fd52: b4 16 + fd54: 00 00 + fd56: ec 16 + fd58: 00 00 + fd5a: 01 00 + fd5c: 5e ec + fd5e: 16 00 + fd60: 00 f4 + fd62: 16 00 + fd64: 00 03 + fd66: 00 7e + fd68: 01 9f + fd6a: f4 16 + fd6c: 00 00 + fd6e: fc 16 + fd70: 00 00 + fd72: 06 00 + fd74: 7f 00 08 20 + fd78: 1b 9f 54 17 + fd7c: 00 00 + fd7e: 80 17 + fd80: 00 00 + fd82: 01 00 + fd84: 5e 80 + fd86: 17 00 00 84 auipc zero, 540672 + fd8a: 17 00 00 03 auipc zero, 12288 + fd8e: 00 7e + fd90: 01 9f + fd92: 84 17 + fd94: 00 00 + fd96: a8 17 + fd98: 00 00 + fd9a: 01 00 + fd9c: 5e a8 + fd9e: 17 00 00 c8 auipc zero, 819200 + fda2: 17 00 00 06 auipc zero, 24576 + fda6: 00 7f + fda8: 00 08 + fdaa: 20 1b + fdac: 9f 10 19 00 + fdb0: 00 24 + fdb2: 19 00 + fdb4: 00 06 + fdb6: 00 7f + fdb8: 00 08 + fdba: 20 1b + fdbc: 9f 00 00 00 + fdc0: 00 00 + fdc2: 00 00 + fdc4: 00 ec + fdc6: 16 00 + fdc8: 00 f4 + fdca: 16 00 + fdcc: 00 01 + fdce: 00 5e + fdd0: 64 17 + fdd2: 00 00 + fdd4: 70 17 + fdd6: 00 00 + fdd8: 01 00 + fdda: 5c 70 + fddc: 17 00 00 78 auipc zero, 491520 + fde0: 17 00 00 03 auipc zero, 12288 + fde4: 00 7c + fde6: 01 9f + fde8: 78 17 + fdea: 00 00 + fdec: 84 17 + fdee: 00 00 + fdf0: 01 00 + fdf2: 5c a8 + fdf4: 17 00 00 cc auipc zero, 835584 + fdf8: 17 00 00 01 auipc zero, 4096 + fdfc: 00 5e + fdfe: 10 19 + fe00: 00 00 + fe02: 14 19 + fe04: 00 00 + fe06: 01 00 + fe08: 5e 00 + fe0a: 00 00 + fe0c: 00 00 + fe0e: 00 00 + fe10: 00 fc + fe12: 18 00 + fe14: 00 10 + fe16: 19 00 + fe18: 00 08 + fe1a: 00 81 + fe1c: 00 30 + fe1e: 2e 08 + fe20: ff 1a 9f 00 + fe24: 00 00 + fe26: 00 00 + fe28: 00 00 + fe2a: 00 d4 + fe2c: 17 00 00 00 auipc zero, 0 + fe30: 18 00 + fe32: 00 0d + fe34: 00 08 + fe36: 20 7f + fe38: 00 08 + fe3a: 20 14 + fe3c: 14 1b + fe3e: 1e 1c + fe40: 1c 9f + fe42: 34 18 + fe44: 00 00 + fe46: 58 18 + fe48: 00 00 + fe4a: 0d 00 + fe4c: 08 20 + fe4e: 7f 00 08 20 + fe52: 14 14 + fe54: 1b 1e 1c 1c + fe58: 9f 00 00 00 + fe5c: 00 00 + fe5e: 00 00 + fe60: 00 d4 + fe62: 17 00 00 00 auipc zero, 0 + fe66: 18 00 + fe68: 00 0a + fe6a: 00 7f + fe6c: 00 08 + fe6e: 20 14 + fe70: 14 1b + fe72: 1e 1c + fe74: 9f 34 18 00 + fe78: 00 58 + fe7a: 18 00 + fe7c: 00 0a + fe7e: 00 7f + fe80: 00 08 + fe82: 20 14 + fe84: 14 1b + fe86: 1e 1c + fe88: 9f 00 00 00 + fe8c: 00 00 + fe8e: 00 00 + fe90: 00 d4 + fe92: 17 00 00 e8 auipc zero, 950272 + fe96: 17 00 00 01 auipc zero, 4096 + fe9a: 00 60 + fe9c: e8 17 + fe9e: 00 00 + fea0: ec 17 + fea2: 00 00 + fea4: 01 00 + fea6: 5d ec + fea8: 17 00 00 24 auipc zero, 147456 + feac: 18 00 + feae: 00 01 + feb0: 00 60 + feb2: 34 18 + feb4: 00 00 + feb6: b0 18 + feb8: 00 00 + feba: 01 00 + febc: 60 b8 + febe: 18 00 + fec0: 00 e4 + fec2: 18 00 + fec4: 00 01 + fec6: 00 60 + ... + fed0: d4 17 + fed2: 00 00 + fed4: dc 17 + fed6: 00 00 + fed8: 02 00 + feda: 30 9f + fedc: dc 17 + fede: 00 00 + fee0: f0 17 + fee2: 00 00 + fee4: 01 00 + fee6: 5e 04 + fee8: 18 00 + feea: 00 10 + feec: 18 00 + feee: 00 01 + fef0: 00 5e + fef2: 10 18 + fef4: 00 00 + fef6: 18 18 + fef8: 00 00 + fefa: 03 00 7e 7f lb zero, 2039(t3) + fefe: 9f 18 18 00 + ff02: 00 20 + ff04: 18 00 + ff06: 00 01 + ff08: 00 5e + ff0a: 34 18 + ff0c: 00 00 + ff0e: 48 18 + ff10: 00 00 + ff12: 01 00 + ff14: 5e 48 + ff16: 18 00 + ff18: 00 4c + ff1a: 18 00 + ff1c: 00 03 + ff1e: 00 7e + ff20: 7f 9f 4c 18 + ff24: 00 00 + ff26: 50 18 + ff28: 00 00 + ff2a: 01 00 + ff2c: 5e 7c + ff2e: 18 00 + ff30: 00 88 + ff32: 18 00 + ff34: 00 02 + ff36: 00 30 + ff38: 9f 88 18 00 + ff3c: 00 a0 + ff3e: 18 00 + ff40: 00 01 + ff42: 00 5e + ff44: b8 18 + ff46: 00 00 + ff48: d4 18 + ff4a: 00 00 + ff4c: 01 00 + ff4e: 5e d4 + ff50: 18 00 + ff52: 00 e0 + ff54: 18 00 + ff56: 00 03 + ff58: 00 7e + ff5a: 7f 9f e0 18 + ff5e: 00 00 + ff60: 00 19 + ff62: 00 00 + ff64: 01 00 + ff66: 5e 00 + ff68: 00 00 + ff6a: 00 00 + ff6c: 00 00 + ff6e: 00 d4 + ff70: 17 00 00 dc auipc zero, 901120 + ff74: 17 00 00 02 auipc zero, 8192 + ff78: 00 30 + ff7a: 9f dc 17 00 + ff7e: 00 10 + ff80: 19 00 + ff82: 00 01 + ff84: 00 61 + ... + ff8e: 64 08 + ff90: 00 00 + ff92: 14 09 + ff94: 00 00 + ff96: 02 00 + ff98: 31 9f + ff9a: a4 09 + ff9c: 00 00 + ff9e: 2c 0b + ffa0: 00 00 + ffa2: 01 00 + ffa4: 60 30 + ffa6: 19 00 + ffa8: 00 58 + ffaa: 19 00 + ffac: 00 02 + ffae: 00 31 + ffb0: 9f 58 19 00 + ffb4: 00 5c + ffb6: 19 00 + ffb8: 00 01 + ffba: 00 60 + ffbc: 64 19 + ffbe: 00 00 + ffc0: 28 1a + ffc2: 00 00 + ffc4: 01 00 + ffc6: 60 00 + ffc8: 00 00 + ffca: 00 00 + ffcc: 00 00 + ffce: 00 74 + ffd0: 08 00 + ffd2: 00 14 + ffd4: 09 00 + ffd6: 00 01 + ffd8: 00 59 + ffda: 30 19 + ffdc: 00 00 + ffde: 5c 19 + ffe0: 00 00 + ffe2: 01 00 + ffe4: 59 00 + ffe6: 00 00 + ffe8: 00 00 + ffea: 00 00 + ffec: 00 74 + ffee: 08 00 + fff0: 00 14 + fff2: 09 00 + fff4: 00 02 + fff6: 00 30 + fff8: 9f 30 19 00 + fffc: 00 5c + fffe: 19 00 + 10000: 00 02 + 10002: 00 30 + 10004: 9f 00 00 00 + 10008: 00 00 + 1000a: 00 00 + 1000c: 00 74 + 1000e: 08 00 + 10010: 00 14 + 10012: 09 00 + 10014: 00 02 + 10016: 00 31 + 10018: 9f 30 19 00 + 1001c: 00 5c + 1001e: 19 00 + 10020: 00 02 + 10022: 00 31 + 10024: 9f 00 00 00 + 10028: 00 00 + 1002a: 00 00 + 1002c: 00 74 + 1002e: 08 00 + 10030: 00 14 + 10032: 09 00 + 10034: 00 02 + 10036: 00 4f + 10038: 9f 30 19 00 + 1003c: 00 5c + 1003e: 19 00 + 10040: 00 02 + 10042: 00 4f + 10044: 9f 00 00 00 + 10048: 00 00 + 1004a: 00 00 + 1004c: 00 74 + 1004e: 08 00 + 10050: 00 7c + 10052: 08 00 + 10054: 00 02 + 10056: 00 33 + 10058: 9f 9c 08 00 + 1005c: 00 14 + 1005e: 09 00 + 10060: 00 03 + 10062: 00 09 + 10064: ff 9f 30 19 + 10068: 00 00 + 1006a: 5c 19 + 1006c: 00 00 + 1006e: 03 00 09 ff lb zero, -16(s2) + 10072: 9f 00 00 00 + 10076: 00 00 + 10078: 00 00 + 1007a: 00 f0 + 1007c: 08 00 + 1007e: 00 fc + 10080: 08 00 + 10082: 00 01 + 10084: 00 5f + 10086: fc 08 + 10088: 00 00 + 1008a: 08 09 + 1008c: 00 00 + 1008e: 01 00 + 10090: 5e 08 + 10092: 09 00 + 10094: 00 0c + 10096: 09 00 + 10098: 00 06 + 1009a: 00 7f + 1009c: 00 08 + 1009e: ff 1a 9f 0c + 100a2: 09 00 + 100a4: 00 14 + 100a6: 09 00 + 100a8: 00 12 + 100aa: 00 7e + 100ac: 00 91 + 100ae: 48 06 + 100b0: 22 40 + 100b2: 4b 24 22 7e + 100b6: 00 40 + 100b8: 4b 24 22 2d + 100bc: 9f 00 00 00 + 100c0: 00 00 + 100c2: 00 00 + 100c4: 00 e8 + 100c6: 09 00 + 100c8: 00 f0 + 100ca: 09 00 + 100cc: 00 01 + 100ce: 00 5e + 100d0: f0 09 + 100d2: 00 00 + 100d4: f4 09 + 100d6: 00 00 + 100d8: 0f 00 91 b0 + 100dc: 7f 06 40 4b + 100e0: 24 22 + 100e2: 0c 03 + 100e4: 00 00 + 100e6: 80 2c + 100e8: 9f f4 09 00 + 100ec: 00 04 + 100ee: 0a 00 + 100f0: 00 01 + 100f2: 00 5e + 100f4: 04 0a + 100f6: 00 00 + 100f8: 08 0a + 100fa: 00 00 + 100fc: 06 00 + 100fe: 7b 00 08 ff + 10102: 1a 9f + ... + 1010c: 78 19 + 1010e: 00 00 + 10110: 80 19 + 10112: 00 00 + 10114: 01 00 + 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11290: 00 5b + ... + 1129a: 50 00 + 1129c: 00 00 + 1129e: 74 01 + 112a0: 00 00 + 112a2: 01 00 + 112a4: 5a 74 + 112a6: 01 00 + 112a8: 00 ac + 112aa: 01 00 + 112ac: 00 01 + 112ae: 00 5c + 112b0: ac 01 + 112b2: 00 00 + 112b4: dc 04 + 112b6: 00 00 + 112b8: 01 00 + 112ba: 5a 00 + 112bc: 00 00 + 112be: 00 00 + 112c0: 00 00 + 112c2: 00 4c + 112c4: 00 00 + 112c6: 00 d0 + 112c8: 00 00 + 112ca: 00 01 + 112cc: 00 6c + 112ce: d0 00 + 112d0: 00 00 + 112d2: 08 01 + 112d4: 00 00 + 112d6: 08 00 + 112d8: 91 6c + 112da: 06 31 + 112dc: 24 41 + 112de: 25 9f + 112e0: 08 01 + 112e2: 00 00 + 112e4: 24 01 + 112e6: 00 00 + 112e8: 01 00 + 112ea: 6c 24 + 112ec: 01 00 + 112ee: 00 a8 + 112f0: 01 00 + 112f2: 00 08 + 112f4: 00 91 + 112f6: 6c 06 + 112f8: 31 24 + 112fa: 41 25 + 112fc: 9f a8 01 00 + 11300: 00 ac + 11302: 01 00 + 11304: 00 08 + 11306: 00 72 + 11308: 6c 06 + 1130a: 31 24 + 1130c: 41 25 + 1130e: 9f ac 01 00 + 11312: 00 ec + 11314: 01 00 + 11316: 00 01 + 11318: 00 6c + 1131a: ec 01 + 1131c: 00 00 + 1131e: 14 02 + 11320: 00 00 + 11322: 08 00 + 11324: 91 6c + 11326: 06 31 + 11328: 24 41 + 1132a: 25 9f + 1132c: 14 02 + 1132e: 00 00 + 11330: 24 02 + 11332: 00 00 + 11334: 01 00 + 11336: 6c 24 + 11338: 02 00 + 1133a: 00 30 + 1133c: 02 00 + 1133e: 00 08 + 11340: 00 91 + 11342: 6c 06 + 11344: 31 24 + 11346: 41 25 + 11348: 9f 30 02 00 + 1134c: 00 dc + 1134e: 02 00 + 11350: 00 01 + 11352: 00 6c + 11354: dc 02 + 11356: 00 00 + 11358: f0 02 + 1135a: 00 00 + 1135c: 08 00 + 1135e: 91 6c + 11360: 06 31 + 11362: 24 41 + 11364: 25 9f + 11366: f0 02 + 11368: 00 00 + 1136a: 04 03 + 1136c: 00 00 + 1136e: 08 00 + 11370: 80 6c + 11372: 06 31 + 11374: 24 41 + 11376: 25 9f + 11378: 04 03 + 1137a: 00 00 + 1137c: 54 03 + 1137e: 00 00 + 11380: 08 00 + 11382: 91 6c + 11384: 06 31 + 11386: 24 41 + 11388: 25 9f + 1138a: 54 03 + 1138c: 00 00 + 1138e: 78 03 + 11390: 00 00 + 11392: 01 00 + 11394: 6c 78 + 11396: 03 00 00 e0 lb zero, -512(zero) + 1139a: 03 00 00 08 lb zero, 128(zero) + 1139e: 00 91 + 113a0: 6c 06 + 113a2: 31 24 + 113a4: 41 25 + 113a6: 9f e0 03 00 + 113aa: 00 2c + 113ac: 04 00 + 113ae: 00 01 + 113b0: 00 6c + 113b2: 2c 04 + 113b4: 00 00 + 113b6: 64 04 + 113b8: 00 00 + 113ba: 08 00 + 113bc: 91 6c + 113be: 06 31 + 113c0: 24 41 + 113c2: 25 9f + 113c4: 64 04 + 113c6: 00 00 + 113c8: 74 04 + 113ca: 00 00 + 113cc: 01 00 + 113ce: 6c 74 + 113d0: 04 00 + 113d2: 00 dc + 113d4: 04 00 + 113d6: 00 08 + 113d8: 00 91 + 113da: 6c 06 + 113dc: 31 24 + 113de: 41 25 + 113e0: 9f 00 00 00 + 113e4: 00 00 + 113e6: 00 00 + 113e8: 00 90 + 113ea: 00 00 + 113ec: 00 8c + 113ee: 01 00 + 113f0: 00 01 + 113f2: 00 5a + 113f4: ac 01 + 113f6: 00 00 + 113f8: dc 04 + 113fa: 00 00 + 113fc: 01 00 + 113fe: 5a 00 + 11400: 00 00 + 11402: 00 00 + 11404: 00 00 + 11406: 00 a4 + 11408: 00 00 + 1140a: 00 c0 + 1140c: 00 00 + 1140e: 00 01 + 11410: 00 61 + 11412: c0 00 + 11414: 00 00 + 11416: d0 00 + 11418: 00 00 + 1141a: 05 00 + 1141c: 8c 80 + 1141e: 88 7f + 11420: 9f 08 01 00 + 11424: 00 18 + 11426: 01 00 + 11428: 00 01 + 1142a: 00 61 + 1142c: 18 01 + 1142e: 00 00 + 11430: 24 01 + 11432: 00 00 + 11434: 05 00 + 11436: 8c 80 + 11438: 88 7f + 1143a: 9f 30 01 00 + 1143e: 00 74 + 11440: 01 00 + 11442: 00 01 + 11444: 00 61 + 11446: ac 01 + 11448: 00 00 + 1144a: 00 02 + 1144c: 00 00 + 1144e: 01 00 + 11450: 61 14 + 11452: 02 00 + 11454: 00 24 + 11456: 02 00 + 11458: 00 01 + 1145a: 00 61 + 1145c: 24 02 + 1145e: 00 00 + 11460: 30 02 + 11462: 00 00 + 11464: 0c 00 + 11466: 91 6c + 11468: 06 31 + 1146a: 24 41 + 1146c: 25 0a + 1146e: 00 3c + 11470: 1c 9f + 11472: 30 02 + 11474: 00 00 + 11476: 48 02 + 11478: 00 00 + 1147a: 01 00 + 1147c: 61 48 + 1147e: 02 00 + 11480: 00 dc + 11482: 02 00 + 11484: 00 05 + 11486: 00 8c + 11488: 80 88 + 1148a: 7f 9f dc 02 + 1148e: 00 00 + 11490: f0 02 + 11492: 00 00 + 11494: 0c 00 + 11496: 91 6c + 11498: 06 31 + 1149a: 24 41 + 1149c: 25 0a + 1149e: 00 3c + 114a0: 1c 9f + 114a2: f0 02 + 114a4: 00 00 + 114a6: 04 03 + 114a8: 00 00 + 114aa: 0c 00 + 114ac: 80 6c + 114ae: 06 31 + 114b0: 24 41 + 114b2: 25 0a + 114b4: 00 3c + 114b6: 1c 9f + 114b8: 04 03 + 114ba: 00 00 + 114bc: 54 03 + 114be: 00 00 + 114c0: 0c 00 + 114c2: 91 6c + 114c4: 06 31 + 114c6: 24 41 + 114c8: 25 0a + 114ca: 00 3c + 114cc: 1c 9f + 114ce: 70 03 + 114d0: 00 00 + 114d2: e0 03 + 114d4: 00 00 + 114d6: 02 00 + 114d8: 30 9f + 114da: e0 03 + 114dc: 00 00 + 114de: 2c 04 + 114e0: 00 00 + 114e2: 04 00 + 114e4: 0a ff + 114e6: 07 9f 2c 04 + 114ea: 00 00 + 114ec: 64 04 + 114ee: 00 00 + 114f0: 02 00 + 114f2: 30 9f + 114f4: 64 04 + 114f6: 00 00 + 114f8: 74 04 + 114fa: 00 00 + 114fc: 04 00 + 114fe: 0a ff + 11500: 07 9f 74 04 + 11504: 00 00 + 11506: 88 04 + 11508: 00 00 + 1150a: 02 00 + 1150c: 30 9f + 1150e: a4 04 + 11510: 00 00 + 11512: c0 04 + 11514: 00 00 + 11516: 01 00 + 11518: 61 c4 + 1151a: 04 00 + 1151c: 00 dc + 1151e: 04 00 + 11520: 00 01 + 11522: 00 61 + ... + 1152c: 00 01 + 1152e: 00 00 + 11530: 08 01 + 11532: 00 00 + 11534: 01 00 + 11536: 5d 44 + 11538: 01 00 + 1153a: 00 4c + 1153c: 01 00 + 1153e: 00 01 + 11540: 00 5f + 11542: 50 01 + 11544: 00 00 + 11546: 60 01 + 11548: 00 00 + 1154a: 01 00 + 1154c: 5f 74 01 00 + 11550: 00 ac + 11552: 01 00 + 11554: 00 01 + 11556: 00 5f + 11558: f0 01 + 1155a: 00 00 + 1155c: 00 02 + 1155e: 00 00 + 11560: 01 00 + 11562: 5f 08 02 00 + 11566: 00 14 + 11568: 02 00 + 1156a: 00 01 + 1156c: 00 5f + 1156e: 78 03 + 11570: 00 00 + 11572: e0 03 + 11574: 00 00 + 11576: 01 00 + 11578: 5f 00 04 00 + 1157c: 00 0c + 1157e: 04 00 + 11580: 00 0a + 11582: 00 81 + 11584: 00 4c + 11586: 25 80 + 11588: 00 34 + 1158a: 24 21 + 1158c: 9f 0c 04 00 + 11590: 00 10 + 11592: 04 00 + 11594: 00 0b + 11596: 00 91 + 11598: 74 06 + 1159a: 4c 25 + 1159c: 80 00 + 1159e: 34 24 + 115a0: 21 9f + 115a2: 10 04 + 115a4: 00 00 + 115a6: 14 04 + 115a8: 00 00 + 115aa: 0c 00 + 115ac: 91 74 + 115ae: 06 4c + 115b0: 25 91 + 115b2: 78 06 + 115b4: 34 24 + 115b6: 21 9f + 115b8: 14 04 + 115ba: 00 00 + 115bc: 64 04 + 115be: 00 00 + 115c0: 01 00 + 115c2: 5f 74 04 00 + 115c6: 00 78 + 115c8: 04 00 + 115ca: 00 01 + 115cc: 00 5f + 115ce: d0 04 + 115d0: 00 00 + 115d2: dc 04 + 115d4: 00 00 + 115d6: 01 00 + 115d8: 5f 00 00 00 + 115dc: 00 00 + 115de: 00 00 + 115e0: 00 00 + 115e2: 01 00 + 115e4: 00 08 + 115e6: 01 00 + 115e8: 00 01 + 115ea: 00 56 + 115ec: 2c 01 + 115ee: 00 00 + 115f0: 44 01 + 115f2: 00 00 + 115f4: 09 00 + 115f6: 76 00 + 115f8: 11 ff + 115fa: ff ff 7b 1a + 115fe: 9f 44 01 00 + 11602: 00 58 + 11604: 01 00 + 11606: 00 01 + 11608: 00 56 + 1160a: 58 01 + 1160c: 00 00 + 1160e: 64 01 + 11610: 00 00 + 11612: 01 00 + 11614: 5d 64 + 11616: 01 00 + 11618: 00 74 + 1161a: 01 00 + 1161c: 00 05 + 1161e: 00 76 + 11620: 00 33 + 11622: 25 9f + 11624: 74 01 + 11626: 00 00 + 11628: 80 01 + 1162a: 00 00 + 1162c: 01 00 + 1162e: 5d f4 + 11630: 01 00 + 11632: 00 00 + 11634: 02 00 + 11636: 00 01 + 11638: 00 56 + 1163a: 08 02 + 1163c: 00 00 + 1163e: 14 02 + 11640: 00 00 + 11642: 01 00 + 11644: 56 78 + 11646: 03 00 00 e0 lb zero, -512(zero) + 1164a: 03 00 00 01 lb zero, 16(zero) + 1164e: 00 56 + 11650: 00 04 + 11652: 00 00 + 11654: 08 04 + 11656: 00 00 + 11658: 0a 00 + 1165a: 80 00 + 1165c: 4c 25 + 1165e: 8e 00 + 11660: 34 24 + 11662: 21 9f + 11664: 08 04 + 11666: 00 00 + 11668: 10 04 + 1166a: 00 00 + 1166c: 0b 00 80 00 + 11670: 4c 25 + 11672: 91 7c + 11674: 06 34 + 11676: 24 21 + 11678: 9f 10 04 00 + 1167c: 00 18 + 1167e: 04 00 + 11680: 00 0c + 11682: 00 91 + 11684: 78 06 + 11686: 4c 25 + 11688: 91 7c + 1168a: 06 34 + 1168c: 24 21 + 1168e: 9f 18 04 00 + 11692: 00 24 + 11694: 04 00 + 11696: 00 01 + 11698: 00 60 + 1169a: 24 04 + 1169c: 00 00 + 1169e: 64 04 + 116a0: 00 00 + 116a2: 01 00 + 116a4: 56 74 + 116a6: 04 00 + 116a8: 00 7c + 116aa: 04 00 + 116ac: 00 01 + 116ae: 00 56 + 116b0: a4 04 + 116b2: 00 00 + 116b4: d0 04 + 116b6: 00 00 + 116b8: 09 00 + 116ba: 76 00 + 116bc: 11 ff + 116be: ff ff 7b 1a + 116c2: 9f d0 04 00 + 116c6: 00 dc + 116c8: 04 00 + 116ca: 00 01 + 116cc: 00 5f + ... + 116d6: 50 00 + 116d8: 00 00 + 116da: 58 00 + 116dc: 00 00 + 116de: 02 00 + 116e0: 33 9f 78 00 sll t5, a7, t2 + 116e4: 00 00 + 116e6: dc 04 + 116e8: 00 00 + 116ea: 03 00 09 ff lb zero, -16(s2) + 116ee: 9f 00 00 00 + 116f2: 00 00 + 116f4: 00 00 + 116f6: 00 1c + 116f8: 03 00 00 2c lb zero, 704(zero) + 116fc: 03 00 00 08 lb zero, 128(zero) + 11700: 00 8f + 11702: 00 30 + 11704: 2e 08 + 11706: ff 1a 9f 00 + 1170a: 00 00 + 1170c: 00 00 + 1170e: 00 00 + 11710: 00 50 + 11712: 02 00 + 11714: 00 84 + 11716: 02 00 + 11718: 00 08 + 1171a: 00 08 + 1171c: 20 81 + 1171e: 00 4f + 11720: 1a 1c + 11722: 9f 84 02 00 + 11726: 00 b4 + 11728: 02 00 + 1172a: 00 0c + 1172c: 00 08 + 1172e: 20 0a + 11730: 3d 3c + 11732: 8c 00 + 11734: 1c 4f + 11736: 1a 1c + 11738: 9f b4 02 00 + 1173c: 00 e0 + 1173e: 02 00 + 11740: 00 08 + 11742: 00 08 + 11744: 20 81 + 11746: 00 4f + 11748: 1a 1c + 1174a: 9f e0 02 00 + 1174e: 00 f0 + 11750: 02 00 + 11752: 00 11 + 11754: 00 08 + 11756: 20 0a + 11758: 3d 3c + 1175a: 91 6c + 1175c: 06 31 + 1175e: 24 41 + 11760: 25 1c + 11762: 4f 1a 1c 9f + 11766: f0 02 + 11768: 00 00 + 1176a: 04 03 + 1176c: 00 00 + 1176e: 11 00 + 11770: 08 20 + 11772: 0a 3d + 11774: 3c 80 + 11776: 6c 06 + 11778: 31 24 + 1177a: 41 25 + 1177c: 1c 4f + 1177e: 1a 1c + 11780: 9f 04 03 00 + 11784: 00 54 + 11786: 03 00 00 11 lb zero, 272(zero) + 1178a: 00 08 + 1178c: 20 0a + 1178e: 3d 3c + 11790: 91 6c + 11792: 06 31 + 11794: 24 41 + 11796: 25 1c + 11798: 4f 1a 1c 9f + ... + 117a4: 50 02 + 117a6: 00 00 + 117a8: 84 02 + 117aa: 00 00 + 117ac: 05 00 + 117ae: 81 00 + 117b0: 4f 1a 9f 84 + 117b4: 02 00 + 117b6: 00 b4 + 117b8: 02 00 + 117ba: 00 09 + 117bc: 00 0a + 117be: 3d 3c + 117c0: 8c 00 + 117c2: 1c 4f + 117c4: 1a 9f + 117c6: b4 02 + 117c8: 00 00 + 117ca: e0 02 + 117cc: 00 00 + 117ce: 05 00 + 117d0: 81 00 + 117d2: 4f 1a 9f e0 fnmadd.s fs4, ft10, fs1, ft8, rtz + 117d6: 02 00 + 117d8: 00 f0 + 117da: 02 00 + 117dc: 00 0e + 117de: 00 0a + 117e0: 3d 3c + 117e2: 91 6c + 117e4: 06 31 + 117e6: 24 41 + 117e8: 25 1c + 117ea: 4f 1a 9f f0 fnmadd.s fs4, ft10, fs1, ft10, rtz + 117ee: 02 00 + 117f0: 00 04 + 117f2: 03 00 00 0e lb zero, 224(zero) + 117f6: 00 0a + 117f8: 3d 3c + 117fa: 80 6c + 117fc: 06 31 + 117fe: 24 41 + 11800: 25 1c + 11802: 4f 1a 9f 04 + 11806: 03 00 00 54 lb zero, 1344(zero) + 1180a: 03 00 00 0e lb zero, 224(zero) + 1180e: 00 0a + 11810: 3d 3c + 11812: 91 6c + 11814: 06 31 + 11816: 24 41 + 11818: 25 1c + 1181a: 4f 1a 9f 00 fnmadd.s fs4, ft10, fs1, ft0, rtz + 1181e: 00 00 + 11820: 00 00 + 11822: 00 00 + 11824: 00 50 + 11826: 02 00 + 11828: 00 a4 + 1182a: 02 00 + 1182c: 00 01 + 1182e: 00 56 + 11830: a4 02 + 11832: 00 00 + 11834: b4 02 + 11836: 00 00 + 11838: 09 00 + 1183a: 0a 3d + 1183c: 3c 8c + 1183e: 00 1c + 11840: 35 26 + 11842: 9f b4 02 00 + 11846: 00 04 + 11848: 03 00 00 01 lb zero, 16(zero) + 1184c: 00 56 + 1184e: 04 03 + 11850: 00 00 + 11852: 2c 03 + 11854: 00 00 + 11856: 0e 00 + 11858: 0a 3d + 1185a: 3c 91 + 1185c: 6c 06 + 1185e: 31 24 + 11860: 41 25 + 11862: 1c 35 + 11864: 26 9f + 11866: 2c 03 + 11868: 00 00 + 1186a: 54 03 + 1186c: 00 00 + 1186e: 01 00 + 11870: 56 00 + 11872: 00 00 + 11874: 00 00 + 11876: 00 00 + 11878: 00 50 + 1187a: 02 00 + 1187c: 00 58 + 1187e: 02 00 + 11880: 00 02 + 11882: 00 30 + 11884: 9f 58 02 00 + 11888: 00 60 + 1188a: 02 00 + 1188c: 00 01 + 1188e: 00 5f + 11890: 60 02 + 11892: 00 00 + 11894: 68 02 + 11896: 00 00 + 11898: 03 00 7f 7f lb zero, 2039(t5) + 1189c: 9f 68 02 00 + 118a0: 00 80 + 118a2: 02 00 + 118a4: 00 01 + 118a6: 00 5f + 118a8: 84 02 + 118aa: 00 00 + 118ac: 90 02 + 118ae: 00 00 + 118b0: 01 00 + 118b2: 5f 90 02 00 + 118b6: 00 98 + 118b8: 02 00 + 118ba: 00 03 + 118bc: 00 7f + 118be: 7f 9f 98 02 + 118c2: 00 00 + 118c4: a8 02 + 118c6: 00 00 + 118c8: 01 00 + 118ca: 5f b4 02 00 + 118ce: 00 b8 + 118d0: 02 00 + 118d2: 00 01 + 118d4: 00 5f + 118d6: d4 02 + 118d8: 00 00 + 118da: e0 02 + 118dc: 00 00 + 118de: 02 00 + 118e0: 30 9f + 118e2: e0 02 + 118e4: 00 00 + 118e6: 00 03 + 118e8: 00 00 + 118ea: 01 00 + 118ec: 6c 04 + 118ee: 03 00 00 24 lb zero, 576(zero) + 118f2: 03 00 00 01 lb zero, 16(zero) + 118f6: 00 5f + 118f8: 2c 03 + 118fa: 00 00 + 118fc: 4c 03 + 118fe: 00 00 + 11900: 01 00 + 11902: 6c 4c + 11904: 03 00 00 50 lb zero, 1280(zero) + 11908: 03 00 00 03 lb zero, 48(zero) + 1190c: 00 8c + 1190e: 01 9f + 11910: 50 03 + 11912: 00 00 + 11914: 54 03 + 11916: 00 00 + 11918: 01 00 + 1191a: 6c 00 + 1191c: 00 00 + 1191e: 00 00 + 11920: 00 00 + 11922: 00 50 + 11924: 02 00 + 11926: 00 58 + 11928: 02 00 + 1192a: 00 02 + 1192c: 00 30 + 1192e: 9f 58 02 00 + 11932: 00 54 + 11934: 03 00 00 01 lb zero, 16(zero) + 11938: 00 6f + ... + 11942: b0 01 + 11944: 00 00 + 11946: e8 01 + 11948: 00 00 + 1194a: 02 00 + 1194c: 31 9f + ... + 11956: b0 01 + 11958: 00 00 + 1195a: bc 01 + 1195c: 00 00 + 1195e: 01 00 + 11960: 6d bc + 11962: 01 00 + 11964: 00 d0 + 11966: 01 00 + 11968: 00 08 + 1196a: 00 7e + 1196c: 00 34 + 1196e: 24 8d + 11970: 00 21 + 11972: 9f d0 01 00 + 11976: 00 dc + 11978: 01 00 + 1197a: 00 01 + 1197c: 00 5f + 1197e: dc 01 + 11980: 00 00 + 11982: e8 01 + 11984: 00 00 + 11986: 09 00 + 11988: 91 74 + 1198a: 06 34 + 1198c: 24 8d + 1198e: 00 21 + 11990: 9f 00 00 00 + 11994: 00 00 + 11996: 00 00 + 11998: 00 00 + 1199a: 04 00 + 1199c: 00 2c + 1199e: 04 00 + 119a0: 00 02 + 119a2: 00 34 + 119a4: 9f 00 00 00 + 119a8: 00 00 + 119aa: 00 00 + 119ac: 00 00 + 119ae: 04 00 + 119b0: 00 2c + 119b2: 04 00 + 119b4: 00 02 + 119b6: 00 4c + 119b8: 9f 00 00 00 + 119bc: 00 00 + 119be: 00 00 + 119c0: 00 00 + 119c2: 04 00 + 119c4: 00 2c + 119c6: 04 00 + 119c8: 00 02 + 119ca: 00 31 + 119cc: 9f 00 00 00 + 119d0: 00 00 + 119d2: 00 00 + 119d4: 00 d0 + 119d6: 00 00 + 119d8: 00 08 + 119da: 01 00 + 119dc: 00 01 + 119de: 00 5e + 119e0: 00 02 + 119e2: 00 00 + 119e4: 10 02 + 119e6: 00 00 + 119e8: 01 00 + 119ea: 5e 80 + 119ec: 03 00 00 e0 lb zero, -512(zero) + 119f0: 03 00 00 02 lb zero, 32(zero) + 119f4: 00 31 + 119f6: 9f 2c 04 00 + 119fa: 00 64 + 119fc: 04 00 + 119fe: 00 02 + 11a00: 00 31 + 11a02: 9f 88 04 00 + 11a06: 00 98 + 11a08: 04 00 + 11a0a: 00 01 + 11a0c: 00 5e + ... + 11a16: 80 03 + 11a18: 00 00 + 11a1a: e0 03 + 11a1c: 00 00 + 11a1e: 01 00 + 11a20: 5a 2c + 11a22: 04 00 + 11a24: 00 64 + 11a26: 04 00 + 11a28: 00 01 + 11a2a: 00 5a + ... + 11a34: 80 03 + 11a36: 00 00 + 11a38: e0 03 + 11a3a: 00 00 + 11a3c: 02 00 + 11a3e: 30 9f + 11a40: 2c 04 + 11a42: 00 00 + 11a44: 64 04 + 11a46: 00 00 + 11a48: 02 00 + 11a4a: 30 9f + ... + 11a54: 80 03 + 11a56: 00 00 + 11a58: 90 03 + 11a5a: 00 00 + 11a5c: 01 00 + 11a5e: 5f 90 03 00 + 11a62: 00 c4 + 11a64: 03 00 00 01 lb zero, 16(zero) + 11a68: 00 5d + 11a6a: c4 03 + 11a6c: 00 00 + 11a6e: cc 03 + 11a70: 00 00 + 11a72: 05 00 + 11a74: 7f 00 31 24 + 11a78: 9f 2c 04 00 + 11a7c: 00 38 + 11a7e: 04 00 + 11a80: 00 01 + 11a82: 00 5d + 11a84: 38 04 + 11a86: 00 00 + 11a88: 40 04 + 11a8a: 00 00 + 11a8c: 05 00 + 11a8e: 7f 00 31 24 + 11a92: 9f 40 04 00 + 11a96: 00 48 + 11a98: 04 00 + 11a9a: 00 07 + 11a9c: 00 7f + 11a9e: 00 31 + 11aa0: 24 23 + 11aa2: 08 9f + 11aa4: 48 04 + 11aa6: 00 00 + 11aa8: 54 04 + 11aaa: 00 00 + 11aac: 01 00 + 11aae: 5d 54 + 11ab0: 04 00 + 11ab2: 00 5c + 11ab4: 04 00 + 11ab6: 00 05 + 11ab8: 00 7f + 11aba: 00 31 + 11abc: 24 9f + 11abe: 5c 04 + 11ac0: 00 00 + 11ac2: 64 04 + 11ac4: 00 00 + 11ac6: 07 00 7f 00 + 11aca: 31 24 + 11acc: 23 08 9f 00 sb s1, 16(t5) + 11ad0: 00 00 + 11ad2: 00 00 + 11ad4: 00 00 + 11ad6: 00 80 + 11ad8: 03 00 00 8c lb zero, -1856(zero) + 11adc: 03 00 00 01 lb zero, 16(zero) + 11ae0: 00 56 + 11ae2: 8c 03 + 11ae4: 00 00 + 11ae6: d0 03 + 11ae8: 00 00 + 11aea: 01 00 + 11aec: 5e 2c + 11aee: 04 00 + 11af0: 00 64 + 11af2: 04 00 + 11af4: 00 01 + 11af6: 00 5e + ... + 11b00: c0 03 + 11b02: 00 00 + 11b04: c4 03 + 11b06: 00 00 + 11b08: 03 00 7d 04 lb zero, 71(s10) + 11b0c: 9f c4 03 00 + 11b10: 00 cc + 11b12: 03 00 00 07 lb zero, 112(zero) + 11b16: 00 7f + 11b18: 00 31 + 11b1a: 24 23 + 11b1c: 04 9f + ... + 11b26: 34 04 + 11b28: 00 00 + 11b2a: 38 04 + 11b2c: 00 00 + 11b2e: 03 00 7d 08 lb zero, 135(s10) + 11b32: 9f 38 04 00 + 11b36: 00 48 + 11b38: 04 00 + 11b3a: 00 07 + 11b3c: 00 7f + 11b3e: 00 31 + 11b40: 24 23 + 11b42: 08 9f + ... + 11b4c: 50 04 + 11b4e: 00 00 + 11b50: 54 04 + 11b52: 00 00 + 11b54: 03 00 7d 08 lb zero, 135(s10) + 11b58: 9f 54 04 00 + 11b5c: 00 64 + 11b5e: 04 00 + 11b60: 00 07 + 11b62: 00 7f + 11b64: 00 31 + 11b66: 24 23 + 11b68: 08 9f + ... + 11b72: f8 00 + 11b74: 00 00 + 11b76: 08 01 + 11b78: 00 00 + 11b7a: 01 00 + 11b7c: 5d 00 + ... + 11b86: 00 00 + 11b88: 00 24 + 11b8a: 00 00 + 11b8c: 00 01 + 11b8e: 00 5a + 11b90: 24 00 + 11b92: 00 00 + 11b94: 38 00 + 11b96: 00 00 + 11b98: 04 00 + 11b9a: f3 01 5a 9f + 11b9e: 38 00 + 11ba0: 00 00 + 11ba2: 4c 00 + 11ba4: 00 00 + 11ba6: 01 00 + 11ba8: 5a 00 + ... + 11bb2: 00 00 + 11bb4: 00 24 + 11bb6: 00 00 + 11bb8: 00 01 + 11bba: 00 5a + 11bbc: 24 00 + 11bbe: 00 00 + 11bc0: 38 00 + 11bc2: 00 00 + 11bc4: 04 00 + 11bc6: f3 01 5a 9f + 11bca: 38 00 + 11bcc: 00 00 + 11bce: 4c 00 + 11bd0: 00 00 + 11bd2: 01 00 + 11bd4: 5a 00 + 11bd6: 00 00 + 11bd8: 00 00 + 11bda: 00 00 + 11bdc: 00 14 + 11bde: 00 00 + 11be0: 00 28 + 11be2: 00 00 + 11be4: 00 01 + 11be6: 00 5f + ... + +Disassembly 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03 + 1432: 00 00 + 1434: e0 03 + 1436: 00 00 + 1438: 2c 04 + 143a: 00 00 + 143c: 64 04 + ... + 1446: 00 00 + 1448: 74 01 + 144a: 00 00 + 144c: 98 01 + 144e: 00 00 + 1450: 98 01 + 1452: 00 00 + 1454: 9c 01 + ... + 145e: 00 00 + 1460: b0 01 + 1462: 00 00 + 1464: e0 01 + 1466: 00 00 + 1468: e4 01 + 146a: 00 00 + 146c: e8 01 + ... + 1476: 00 00 + 1478: 24 02 + 147a: 00 00 + 147c: 28 02 + 147e: 00 00 + 1480: 38 02 + 1482: 00 00 + 1484: 3c 02 + 1486: 00 00 + 1488: 40 02 + 148a: 00 00 + 148c: 48 02 + 148e: 00 00 + 1490: 4c 02 + 1492: 00 00 + 1494: 54 03 + ... + 149e: 00 00 + 14a0: 38 02 + 14a2: 00 00 + 14a4: 3c 02 + 14a6: 00 00 + 14a8: 40 02 + 14aa: 00 00 + 14ac: 48 02 + 14ae: 00 00 + 14b0: 4c 02 + 14b2: 00 00 + 14b4: 1c 03 + 14b6: 00 00 + 14b8: 20 03 + 14ba: 00 00 + 14bc: 24 03 + 14be: 00 00 + 14c0: 2c 03 + 14c2: 00 00 + 14c4: 54 03 + ... + 14ce: 00 00 + 14d0: 00 04 + 14d2: 00 00 + 14d4: 00 04 + 14d6: 00 00 + 14d8: 00 04 + 14da: 00 00 + 14dc: 18 04 + ... + 14ea: 00 00 + 14ec: 14 00 + 14ee: 00 00 + 14f0: 14 00 + 14f2: 00 00 + 14f4: 30 00 + 14f6: 00 00 + 14f8: 38 00 + 14fa: 00 00 + 14fc: 4c 00 + ... + 1506: 00 00 + +Disassembly of section .symtab: + +00000000 .symtab: + ... + 14: 00 00 + 16: 00 80 + 18: 00 00 + 1a: 00 00 + 1c: 03 00 01 00 lb zero, 0(sp) + 20: 00 00 + 22: 00 00 + 24: 50 00 + 26: 00 80 + 28: 00 00 + 2a: 00 00 + 2c: 03 00 02 00 lb zero, 0(tp) + 30: 00 00 + 32: 00 00 + 34: 18 55 + 36: 01 80 + 38: 00 00 + 3a: 00 00 + 3c: 03 00 03 00 lb zero, 0(t1) + 40: 00 00 + 42: 00 00 + 44: 98 61 + 46: 01 80 + 48: 00 00 + 4a: 00 00 + 4c: 03 00 04 00 lb zero, 0(s0) + 50: 00 00 + 52: 00 00 + 54: d4 71 + 56: 01 80 + 58: 00 00 + 5a: 00 00 + 5c: 03 00 05 00 lb zero, 0(a0) + 60: 00 00 + 62: 00 00 + 64: d8 71 + 66: 01 80 + 68: 00 00 + 6a: 00 00 + 6c: 03 00 06 00 lb zero, 0(a2) + 70: 00 00 + 72: 00 00 + 74: 78 7b + 76: 01 80 + 78: 00 00 + 7a: 00 00 + 7c: 03 00 07 00 lb zero, 0(a4) + 80: 00 00 + 82: 00 00 + 84: a8 7b + 86: 01 80 + 88: 00 00 + 8a: 00 00 + 8c: 03 00 08 00 lb zero, 0(a6) + 90: 00 00 + 92: 00 00 + 94: b4 7b + 96: 01 80 + 98: 00 00 + 9a: 00 00 + 9c: 03 00 09 00 lb zero, 0(s2) + ... + ac: 03 00 0a 00 lb zero, 0(s4) + ... + bc: 03 00 0b 00 lb zero, 0(s6) + ... + cc: 03 00 0c 00 lb zero, 0(s8) + ... + dc: 03 00 0d 00 lb zero, 0(s10) + ... + ec: 03 00 0e 00 lb zero, 0(t3) + ... + fc: 03 00 0f 00 lb zero, 0(t5) + ... + 10c: 03 00 10 00 lb zero, 1(zero) + ... + 11c: 03 00 11 00 lb zero, 1(sp) + ... + 12c: 03 00 12 00 lb zero, 1(tp) + ... + 13c: 03 00 13 00 lb zero, 1(t1) + 140: 01 00 + ... + 14a: 00 00 + 14c: 04 00 + 14e: f1 ff + 150: 0e 00 + 152: 00 00 + 154: ac 2c + 156: 00 80 + 158: 00 00 + 15a: 00 00 + 15c: 00 00 + 15e: 02 00 + 160: 1e 00 + 162: 00 00 + 164: e8 2c + 166: 00 80 + 168: 00 00 + 16a: 00 00 + 16c: 00 00 + 16e: 02 00 + 170: 25 00 + ... + 17a: 00 00 + 17c: 04 00 + 17e: f1 ff + 180: 35 00 + 182: 00 00 + 184: 50 00 + 186: 00 80 + 188: 18 00 + 18a: 00 00 + 18c: 02 00 + 18e: 02 00 + 190: 43 00 00 00 fmadd.s ft0, ft0, ft0, ft0, rne + ... + 19c: 04 00 + 19e: f1 ff + 1a0: 67 00 00 00 jr zero + ... + 1ac: 04 00 + 1ae: f1 ff + 1b0: 73 00 00 00 ecall + 1b4: 90 10 + 1b6: 00 80 + 1b8: 0c 02 + 1ba: 00 00 + 1bc: 02 00 + 1be: 02 00 + 1c0: 8d 00 + 1c2: 00 00 + 1c4: 78 06 + 1c6: 00 80 + 1c8: a8 02 + 1ca: 00 00 + 1cc: 02 00 + 1ce: 02 00 + 1d0: a5 00 + 1d2: 00 00 + 1d4: d8 0b + 1d6: 00 80 + 1d8: ac 02 + 1da: 00 00 + 1dc: 02 00 + 1de: 02 00 + 1e0: bc 00 + 1e2: 00 00 + 1e4: 20 09 + 1e6: 00 80 + 1e8: b8 02 + 1ea: 00 00 + 1ec: 02 00 + 1ee: 02 00 + 1f0: d5 00 + 1f2: 00 00 + 1f4: 48 29 + 1f6: 00 80 + 1f8: 80 00 + 1fa: 00 00 + 1fc: 02 00 + 1fe: 02 00 + 200: e3 00 00 00 beqz zero, 2048 + 204: 84 0e + 206: 00 80 + 208: 0c 02 + 20a: 00 00 + 20c: 02 00 + 20e: 02 00 + 210: fc 00 + 212: 00 00 + 214: 9c 12 + 216: 00 80 + 218: ac 16 + 21a: 00 00 + 21c: 02 00 + 21e: 02 00 + 220: 16 01 + 222: 00 00 + 224: 98 00 + 226: 00 80 + 228: e0 03 + 22a: 00 00 + 22c: 02 00 + 22e: 02 00 + 230: 2b 01 00 00 + 234: 78 04 + 236: 00 80 + 238: 00 02 + 23a: 00 00 + 23c: 02 00 + 23e: 02 00 + 240: 3f 01 00 00 + ... + 24c: 04 00 + 24e: f1 ff + 250: 4d 01 + ... + 25a: 00 00 + 25c: 04 00 + 25e: f1 ff + 260: 58 01 + 262: 00 00 + 264: 8c 2e + 266: 00 80 + 268: 3c 01 + 26a: 00 00 + 26c: 02 00 + 26e: 02 00 + 270: 6e 01 + 272: 00 00 + 274: c8 2f + 276: 00 80 + 278: a4 00 + 27a: 00 00 + 27c: 02 00 + 27e: 02 00 + 280: 84 01 + 282: 00 00 + 284: 6c 30 + 286: 00 80 + 288: 2c 00 + 28a: 00 00 + 28c: 02 00 + 28e: 02 00 + 290: 98 01 + ... + 29a: 00 00 + 29c: 04 00 + 29e: f1 ff + 2a0: d2 01 + ... + 2aa: 00 00 + 2ac: 04 00 + 2ae: f1 ff + 2b0: d4 01 + ... + 2ba: 00 00 + 2bc: 04 00 + 2be: f1 ff + 2c0: a2 01 + ... + 2ca: 00 00 + 2cc: 04 00 + 2ce: f1 ff + 2d0: ad 01 + ... + 2da: 00 00 + 2dc: 04 00 + 2de: f1 ff + 2e0: b8 01 + 2e2: 00 00 + 2e4: 48 57 + 2e6: 01 80 + 2e8: 10 00 + 2ea: 00 00 + 2ec: 01 00 + 2ee: 03 00 c4 01 lb zero, 28(s0) + 2f2: 00 00 + 2f4: 58 57 + 2f6: 01 80 + 2f8: 10 00 + 2fa: 00 00 + 2fc: 01 00 + 2fe: 03 00 d0 01 lb zero, 29(zero) + ... + 30a: 00 00 + 30c: 04 00 + 30e: f1 ff + 310: db 01 00 00 + ... + 31c: 04 00 + 31e: f1 ff + 320: e5 01 + ... + 32a: 00 00 + 32c: 04 00 + 32e: f1 ff + 330: ed 01 + 332: 00 00 + 334: 20 68 + 336: 00 80 + 338: 68 00 + 33a: 00 00 + 33c: 02 00 + 33e: 02 00 + 340: f4 01 + 342: 00 00 + 344: 88 68 + 346: 00 80 + 348: 70 00 + 34a: 00 00 + 34c: 02 00 + 34e: 02 00 + 350: fb 01 00 00 + 354: f8 68 + 356: 00 80 + 358: 98 00 + 35a: 00 00 + 35c: 02 00 + 35e: 02 00 + 360: 00 02 + 362: 00 00 + 364: 90 69 + 366: 00 80 + 368: 24 00 + 36a: 00 00 + 36c: 02 00 + 36e: 02 00 + 370: 0e 02 + 372: 00 00 + 374: b4 69 + 376: 00 80 + 378: 4c 00 + 37a: 00 00 + 37c: 02 00 + 37e: 02 00 + 380: 13 02 00 00 mv tp, zero + 384: 00 6a + 386: 00 80 + 388: 40 00 + 38a: 00 00 + 38c: 02 00 + 38e: 02 00 + 390: 1a 02 + 392: 00 00 + 394: 40 6a + 396: 00 80 + 398: f8 00 + 39a: 00 00 + 39c: 02 00 + 39e: 02 00 + 3a0: 20 02 + 3a2: 00 00 + 3a4: 38 6b + 3a6: 00 80 + 3a8: 1c 01 + 3aa: 00 00 + 3ac: 02 00 + 3ae: 02 00 + 3b0: 25 02 + 3b2: 00 00 + 3b4: 54 6c + 3b6: 00 80 + 3b8: 1c 00 + 3ba: 00 00 + 3bc: 02 00 + 3be: 02 00 + 3c0: 33 02 00 00 add tp, zero, zero + 3c4: 70 6c + 3c6: 00 80 + 3c8: 1c 02 + 3ca: 00 00 + 3cc: 02 00 + 3ce: 02 00 + 3d0: 41 02 + 3d2: 00 00 + 3d4: 8c 6e + 3d6: 00 80 + 3d8: 7c 01 + 3da: 00 00 + 3dc: 02 00 + 3de: 02 00 + 3e0: 49 02 + 3e2: 00 00 + 3e4: 08 70 + 3e6: 00 80 + 3e8: 0c 04 + 3ea: 00 00 + 3ec: 02 00 + 3ee: 02 00 + 3f0: 51 02 + 3f2: 00 00 + 3f4: 14 74 + 3f6: 00 80 + 3f8: 68 01 + 3fa: 00 00 + 3fc: 02 00 + 3fe: 02 00 + 400: 5a 02 + 402: 00 00 + 404: 7c 75 + 406: 00 80 + 408: b0 00 + 40a: 00 00 + 40c: 02 00 + 40e: 02 00 + 410: 67 02 00 00 jalr tp, zero + 414: 2c 76 + 416: 00 80 + 418: 18 04 + 41a: 00 00 + 41c: 02 00 + 41e: 02 00 + 420: 6c 02 + 422: 00 00 + 424: 44 7a + 426: 00 80 + 428: 10 05 + 42a: 00 00 + 42c: 02 00 + 42e: 02 00 + 430: 71 02 + 432: 00 00 + 434: 54 7f + 436: 00 80 + 438: 44 01 + 43a: 00 00 + 43c: 02 00 + 43e: 02 00 + 440: 80 02 + 442: 00 00 + 444: 90 57 + 446: 01 80 + 448: 14 00 + 44a: 00 00 + 44c: 01 00 + 44e: 03 00 86 02 lb zero, 40(a2) + 452: 00 00 + 454: a4 57 + 456: 01 80 + 458: 14 00 + 45a: 00 00 + 45c: 01 00 + 45e: 03 00 8b 02 lb zero, 40(s6) + 462: 00 00 + 464: b8 57 + 466: 01 80 + 468: 04 01 + 46a: 00 00 + 46c: 01 00 + 46e: 03 00 91 02 lb zero, 41(sp) + 472: 00 00 + 474: bc 58 + 476: 01 80 + 478: 04 01 + 47a: 00 00 + 47c: 01 00 + 47e: 03 00 98 02 lb zero, 41(a6) + 482: 00 00 + 484: c0 59 + 486: 01 80 + 488: 22 00 + 48a: 00 00 + 48c: 01 00 + 48e: 03 00 9e 02 lb zero, 41(t3) + ... + 49a: 00 00 + 49c: 04 00 + 49e: f1 ff + 4a0: db 01 00 00 + ... + 4ac: 04 00 + 4ae: f1 ff + 4b0: ab 02 00 00 + ... + 4bc: 04 00 + 4be: f1 ff + 4c0: b4 02 + ... + 4ca: 00 00 + 4cc: 04 00 + 4ce: f1 ff + 4d0: bc 02 + ... + 4da: 00 00 + 4dc: 04 00 + 4de: f1 ff + 4e0: c4 02 + 4e2: 00 00 + 4e4: 50 5a + 4e6: 01 80 + 4e8: 0c 00 + 4ea: 00 00 + 4ec: 01 00 + 4ee: 03 00 cd 02 lb zero, 44(s10) + ... + 4fa: 00 00 + 4fc: 04 00 + 4fe: f1 ff + 500: d7 02 00 00 + ... + 50c: 04 00 + 50e: f1 ff + 510: df 02 00 00 + ... + 51c: 04 00 + 51e: f1 ff + 520: e9 02 + ... + 52a: 00 00 + 52c: 04 00 + 52e: f1 ff + 530: f2 02 + ... + 53a: 00 00 + 53c: 04 00 + 53e: f1 ff + 540: fb 02 00 00 + ... + 54c: 04 00 + 54e: f1 ff + 550: ad 01 + ... + 55a: 00 00 + 55c: 04 00 + 55e: f1 ff + 560: 05 03 + 562: 00 00 + 564: e4 5c + 566: 01 80 + 568: 10 00 + 56a: 00 00 + 56c: 01 00 + 56e: 03 00 11 03 lb zero, 49(sp) + 572: 00 00 + 574: f4 5c + 576: 01 80 + 578: 10 00 + 57a: 00 00 + 57c: 01 00 + 57e: 03 00 1d 03 lb zero, 49(s10) + ... + 58a: 00 00 + 58c: 04 00 + 58e: f1 ff + 590: db 01 00 00 + ... + 59c: 04 00 + 59e: f1 ff + 5a0: 26 03 + ... + 5aa: 00 00 + 5ac: 04 00 + 5ae: f1 ff + 5b0: 31 03 + ... + 5ba: 00 00 + 5bc: 04 00 + 5be: f1 ff + 5c0: 3a 03 + ... + 5ca: 00 00 + 5cc: 04 00 + 5ce: f1 ff + 5d0: 45 03 + ... + 5da: 00 00 + 5dc: 04 00 + 5de: f1 ff + 5e0: 4e 03 + ... + 5ea: 00 00 + 5ec: 04 00 + 5ee: f1 ff + 5f0: db 01 00 00 + ... + 5fc: 04 00 + 5fe: f1 ff + 600: ad 01 + ... + 60a: 00 00 + 60c: 04 00 + 60e: f1 ff + 610: 5d 03 + 612: 00 00 + 614: 2c cf + 616: 00 80 + 618: f0 00 + 61a: 00 00 + 61c: 02 00 + 61e: 02 00 + 620: 6f 03 00 00 jal t1, 0 + 624: 50 e2 + 626: 00 80 + 628: c0 00 + 62a: 00 00 + 62c: 02 00 + 62e: 02 00 + 630: 7a 03 + 632: 00 00 + 634: c0 5e + 636: 01 80 + 638: 10 00 + 63a: 00 00 + 63c: 01 00 + 63e: 03 00 86 03 lb zero, 56(a2) + 642: 00 00 + 644: d0 5e + 646: 01 80 + 648: 10 00 + 64a: 00 00 + 64c: 01 00 + 64e: 03 00 92 03 lb zero, 57(tp) + ... + 65a: 00 00 + 65c: 04 00 + 65e: f1 ff + 660: 9d 03 + ... + 66a: 00 00 + 66c: 04 00 + 66e: f1 ff + 670: a6 03 + ... + 67a: 00 00 + 67c: 04 00 + 67e: f1 ff + 680: ae 03 + ... + 68a: 00 00 + 68c: 04 00 + 68e: f1 ff + 690: b7 03 00 00 lui t2, 0 + ... + 69c: 04 00 + 69e: f1 ff + 6a0: c0 03 + 6a2: 00 00 + 6a4: a8 e7 + 6a6: 00 80 + 6a8: 08 00 + 6aa: 00 00 + 6ac: 02 00 + 6ae: 02 00 + 6b0: ca 03 + 6b2: 00 00 + 6b4: bc e7 + 6b6: 00 80 + 6b8: 84 01 + 6ba: 00 00 + 6bc: 02 00 + 6be: 02 00 + 6c0: d9 03 + 6c2: 00 00 + 6c4: 40 e9 + 6c6: 00 80 + 6c8: 08 00 + 6ca: 00 00 + 6cc: 02 00 + 6ce: 02 00 + 6d0: e5 03 + ... + 6da: 00 00 + 6dc: 04 00 + 6de: f1 ff + 6e0: ee 03 + ... + 6ea: 00 00 + 6ec: 04 00 + 6ee: f1 ff + 6f0: f8 03 + ... + 6fa: 00 00 + 6fc: 04 00 + 6fe: f1 ff + 700: 00 04 + ... + 70a: 00 00 + 70c: 04 00 + 70e: f1 ff + 710: 0a 04 + ... + 71a: 00 00 + 71c: 04 00 + 71e: f1 ff + 720: 13 04 00 00 mv s0, zero + 724: dc f4 + 726: 00 80 + 728: 4c 00 + 72a: 00 00 + 72c: 02 00 + 72e: 02 00 + 730: 29 04 + ... + 73a: 00 00 + 73c: 04 00 + 73e: f1 ff + 740: 33 04 00 00 add s0, zero, zero + ... + 74c: 04 00 + 74e: f1 ff + 750: 3b 04 00 00 + ... + 75c: 04 00 + 75e: f1 ff + 760: 42 04 + ... + 76a: 00 00 + 76c: 04 00 + 76e: f1 ff + 770: 4c 04 + ... + 77a: 00 00 + 77c: 04 00 + 77e: f1 ff + 780: 55 04 + ... + 78a: 00 00 + 78c: 04 00 + 78e: f1 ff + 790: 5e 04 + ... + 79a: 00 00 + 79c: 04 00 + 79e: f1 ff + 7a0: 67 04 00 00 jalr s0, zero + ... + 7ac: 04 00 + 7ae: f1 ff + 7b0: 70 04 + ... + 7ba: 00 00 + 7bc: 04 00 + 7be: f1 ff + 7c0: 7a 04 + ... + 7ca: 00 00 + 7cc: 04 00 + 7ce: f1 ff + 7d0: 83 04 00 00 lb s1, 0(zero) + ... + 7dc: 04 00 + 7de: f1 ff + 7e0: 8b 04 00 00 + ... + 7ec: 04 00 + 7ee: f1 ff + 7f0: 8b 04 00 00 + ... + 7fc: 04 00 + 7fe: f1 ff + 800: 95 04 + ... + 80a: 00 00 + 80c: 04 00 + 80e: f1 ff + 810: 9e 04 + ... + 81a: 00 00 + 81c: 04 00 + 81e: f1 ff + 820: a7 04 00 00 + ... + 82c: 04 00 + 82e: f1 ff + 830: af 04 00 00 + ... + 83c: 04 00 + 83e: f1 ff + 840: b7 04 00 00 lui s1, 0 + ... + 84c: 04 00 + 84e: f1 ff + 850: bf 04 00 00 + ... + 85c: 04 00 + 85e: f1 ff + 860: c8 04 + ... + 86a: 00 00 + 86c: 04 00 + 86e: f1 ff + 870: d1 04 + ... + 87a: 00 00 + 87c: 04 00 + 87e: f1 ff + 880: db 04 00 00 + ... + 88c: 04 00 + 88e: f1 ff + 890: e7 04 00 00 jalr s1, zero + ... + 89c: 04 00 + 89e: f1 ff + 8a0: f5 04 + ... + 8aa: 00 00 + 8ac: 04 00 + 8ae: f1 ff + 8b0: 03 05 00 00 lb a0, 0(zero) + ... + 8bc: 04 00 + 8be: f1 ff + 8c0: 8b 04 00 00 + ... + 8cc: 04 00 + 8ce: f1 ff + 8d0: 10 05 + ... + 8da: 00 00 + 8dc: 04 00 + 8de: f1 ff + 8e0: 8b 04 00 00 + ... + 8ec: 04 00 + 8ee: f1 ff + 8f0: 19 05 + ... + 8fa: 00 00 + 8fc: 04 00 + 8fe: f1 ff + 900: 22 05 + 902: 00 00 + 904: d8 71 + 906: 01 80 + 908: 28 04 + 90a: 00 00 + 90c: 01 00 + 90e: 06 00 + ... + 91c: 04 00 + 91e: f1 ff + 920: 2e 05 + 922: 00 00 + 924: d8 71 + 926: 01 80 + 928: 00 00 + 92a: 00 00 + 92c: 00 00 + 92e: 06 00 + 930: 3f 05 00 00 + 934: d8 71 + 936: 01 80 + 938: 00 00 + 93a: 00 00 + 93c: 00 00 + 93e: 06 00 + 940: 52 05 + 942: 00 00 + 944: d8 71 + 946: 01 80 + 948: 00 00 + 94a: 00 00 + 94c: 00 00 + 94e: 05 00 + 950: 63 05 00 00 beqz zero, 10 + 954: d4 71 + 956: 01 80 + 958: 00 00 + 95a: 00 00 + 95c: 00 00 + 95e: 05 00 + 960: 77 05 00 00 + 964: d4 71 + 966: 01 80 + 968: 00 00 + 96a: 00 00 + 96c: 00 00 + 96e: 05 00 + 970: 8a 05 + 972: 00 00 + 974: d4 71 + 976: 01 80 + 978: 00 00 + 97a: 00 00 + 97c: 00 00 + 97e: 05 00 + 980: a0 05 + 982: 00 00 + 984: 58 ac + 986: 00 80 + 988: a4 00 + 98a: 00 00 + 98c: 12 00 + 98e: 02 00 + 990: ad 05 + 992: 00 00 + 994: 64 ad + 996: 00 80 + 998: 64 00 + 99a: 00 00 + 99c: 12 00 + 99e: 02 00 + 9a0: b6 05 + 9a2: 00 00 + 9a4: 74 fe + 9a6: 00 80 + 9a8: 60 00 + 9aa: 00 00 + 9ac: 12 00 + 9ae: 02 00 + 9b0: c0 05 + 9b2: 00 00 + 9b4: 28 5b + 9b6: 01 80 + 9b8: 28 00 + 9ba: 00 00 + 9bc: 11 00 + 9be: 03 00 d1 05 lb zero, 93(sp) + 9c2: 00 00 + 9c4: bc af + 9c6: 00 80 + 9c8: b0 00 + 9ca: 00 00 + 9cc: 12 00 + 9ce: 02 00 + 9d0: d8 05 + 9d2: 00 00 + 9d4: 74 2d + 9d6: 00 80 + 9d8: 08 00 + 9da: 00 00 + 9dc: 12 00 + 9de: 02 00 + 9e0: e0 05 + 9e2: 00 00 + 9e4: d4 fe + 9e6: 00 80 + 9e8: 6c 00 + 9ea: 00 00 + 9ec: 12 00 + 9ee: 02 00 + 9f0: e9 05 + 9f2: 00 00 + 9f4: 84 19 + 9f6: 01 80 + 9f8: 4c 01 + 9fa: 00 00 + 9fc: 12 02 + 9fe: 02 00 + a00: f1 05 + a02: 00 00 + a04: b0 f7 + a06: 00 80 + a08: 68 00 + a0a: 00 00 + a0c: 12 00 + a0e: 02 00 + a10: f9 05 + a12: 00 00 + a14: 58 18 + a16: 01 80 + a18: 2c 01 + a1a: 00 00 + a1c: 12 02 + a1e: 02 00 + a20: 01 06 + a22: 00 00 + a24: 14 fb + a26: 00 80 + a28: 78 00 + a2a: 00 00 + a2c: 12 00 + a2e: 02 00 + a30: a1 0c + a32: 00 00 + a34: 3c f5 + a36: 00 80 + a38: 8c 00 + a3a: 00 00 + a3c: 12 00 + a3e: 02 00 + a40: 0c 06 + a42: 00 00 + a44: 08 f9 + a46: 00 80 + a48: 68 00 + a4a: 00 00 + a4c: 12 00 + a4e: 02 00 + a50: 14 06 + a52: 00 00 + a54: cc ea + a56: 00 80 + a58: 10 00 + a5a: 00 00 + a5c: 12 00 + a5e: 02 00 + a60: 1c 06 + a62: 00 00 + a64: 78 f9 + a66: 00 80 + a68: 84 01 + a6a: 00 00 + a6c: 12 00 + a6e: 02 00 + a70: 26 06 + a72: 00 00 + a74: e8 c4 + a76: 00 80 + a78: 7c 00 + a7a: 00 00 + a7c: 12 00 + a7e: 02 00 + a80: 33 06 00 00 add a2, zero, zero + ... + a8c: 10 00 + a8e: f1 ff + a90: 41 06 + a92: 00 00 + a94: 48 e9 + a96: 00 80 + a98: 6c 00 + a9a: 00 00 + a9c: 12 00 + a9e: 02 00 + aa0: 4e 06 + aa2: 00 00 + aa4: 70 9c + aa6: 00 80 + aa8: 04 00 + aaa: 00 00 + aac: 12 00 + aae: 02 00 + ab0: 5e 06 + ab2: 00 00 + ab4: 68 4b + ab6: 01 80 + ab8: 50 01 + aba: 00 00 + abc: 12 02 + abe: 02 00 + ac0: 6a 06 + ac2: 00 00 + ac4: 18 c7 + ac6: 00 80 + ac8: 20 01 + aca: 00 00 + acc: 12 00 + ace: 02 00 + ad0: 72 06 + ad2: 00 00 + ad4: b8 ea + ad6: 00 80 + ad8: 14 00 + ada: 00 00 + adc: 12 00 + ade: 02 00 + ae0: 7b 06 00 00 + ae4: 60 36 + ae6: 00 80 + ae8: e4 00 + aea: 00 00 + aec: 12 00 + aee: 02 00 + af0: 84 06 + af2: 00 00 + af4: 74 9c + af6: 00 80 + af8: a8 00 + afa: 00 00 + afc: 12 00 + afe: 02 00 + b00: 8c 06 + b02: 00 00 + b04: c0 93 + b06: 00 80 + b08: 08 00 + b0a: 00 00 + b0c: 12 00 + b0e: 02 00 + b10: 9b 06 00 00 + b14: 0c fe + b16: 00 80 + b18: 68 00 + b1a: 00 00 + b1c: 12 00 + b1e: 02 00 + b20: a4 06 + b22: 00 00 + b24: 5c 7c + b26: 01 80 + b28: 04 00 + b2a: 00 00 + b2c: 11 00 + b2e: 09 00 + b30: aa 06 + b32: 00 00 + b34: 78 f8 + b36: 00 80 + b38: 08 00 + b3a: 00 00 + b3c: 12 00 + b3e: 02 00 + b40: b5 06 + b42: 00 00 + b44: 00 04 + b46: 00 00 + b48: 00 00 + b4a: 00 00 + b4c: 10 00 + b4e: f1 ff + b50: c2 06 + b52: 00 00 + b54: dc 7b + b56: 01 80 + b58: 80 00 + b5a: 00 00 + b5c: 11 00 + b5e: 09 00 + b60: d0 06 + b62: 00 00 + b64: 78 7b + b66: 01 80 + b68: 00 00 + b6a: 00 00 + b6c: 10 00 + b6e: 07 00 e0 06 + b72: 00 00 + b74: fc c5 + b76: 00 80 + b78: 1c 01 + b7a: 00 00 + b7c: 12 00 + b7e: 02 00 + b80: e7 06 00 00 jalr a3, zero + b84: b0 e7 + b86: 00 80 + b88: 0c 00 + b8a: 00 00 + b8c: 12 00 + b8e: 02 00 + b90: f2 06 + b92: 00 00 + b94: 44 37 + b96: 00 80 + b98: c8 2a + b9a: 00 00 + b9c: 12 00 + b9e: 02 00 + ba0: ff 06 00 00 + ba4: b0 ab + ba6: 00 80 + ba8: a8 00 + baa: 00 00 + bac: 12 00 + bae: 02 00 + bb0: 07 07 00 00 + bb4: d8 79 + bb6: 01 80 + bb8: 00 00 + bba: 00 00 + bbc: 10 00 + bbe: f1 ff + bc0: 18 07 + bc2: 00 00 + bc4: d0 1a + bc6: 01 80 + bc8: 4c 01 + bca: 00 00 + bcc: 12 02 + bce: 02 00 + bd0: 20 07 + bd2: 00 00 + bd4: c8 f5 + bd6: 00 80 + bd8: dc 00 + bda: 00 00 + bdc: 12 00 + bde: 02 00 + be0: 29 07 + be2: 00 00 + be4: f4 2c + be6: 00 80 + be8: 08 00 + bea: 00 00 + bec: 12 00 + bee: 02 00 + bf0: 30 07 + bf2: 00 00 + bf4: 44 c3 + bf6: 00 80 + bf8: 58 00 + bfa: 00 00 + bfc: 12 00 + bfe: 02 00 + c00: 3e 07 + c02: 00 00 + c04: 60 5a + c06: 01 80 + c08: c8 00 + c0a: 00 00 + c0c: 11 00 + c0e: 03 00 4b 07 lb zero, 116(s6) + c12: 00 00 + c14: b0 7b + c16: 01 80 + c18: 04 00 + c1a: 00 00 + c1c: 11 00 + c1e: 08 00 + c20: 5c 07 + c22: 00 00 + c24: 18 f8 + c26: 00 80 + c28: 04 00 + c2a: 00 00 + c2c: 12 00 + c2e: 02 00 + c30: 66 07 + c32: 00 00 + c34: c8 93 + c36: 00 80 + c38: 0c 00 + c3a: 00 00 + c3c: 12 00 + c3e: 02 00 + c40: 74 07 + c42: 00 00 + c44: ec ec + c46: 00 80 + c48: a8 04 + c4a: 00 00 + c4c: 12 00 + c4e: 02 00 + c50: 81 07 + c52: 00 00 + c54: e4 a0 + c56: 00 80 + c58: 54 00 + c5a: 00 00 + c5c: 12 00 + c5e: 02 00 + c60: 87 07 00 00 + c64: a4 f6 + c66: 00 80 + c68: b8 00 + c6a: 00 00 + c6c: 12 00 + c6e: 02 00 + c70: 94 07 + c72: 00 00 + c74: 74 ae + c76: 00 80 + c78: 60 00 + c7a: 00 00 + c7c: 12 00 + c7e: 02 00 + c80: 9c 07 + c82: 00 00 + c84: 40 ff + c86: 00 80 + c88: 6c 00 + c8a: 00 00 + c8c: 12 00 + c8e: 02 00 + c90: a4 07 + c92: 00 00 + c94: ec fc + c96: 00 80 + c98: 10 01 + c9a: 00 00 + c9c: 12 00 + c9e: 02 00 + ca0: ae 07 + ca2: 00 00 + ca4: c4 2a + ca6: 00 80 + ca8: f0 00 + caa: 00 00 + cac: 12 00 + cae: 02 00 + cb0: cf 07 00 00 fnmadd.s fa5, ft0, ft0, ft0, rne + cb4: 80 e7 + cb6: 00 80 + cb8: 28 00 + cba: 00 00 + cbc: 12 00 + cbe: 02 00 + cc0: d6 07 + cc2: 00 00 + cc4: ac 7b + cc6: 01 80 + cc8: 04 00 + cca: 00 00 + ccc: 11 00 + cce: 08 00 + cd0: ee 07 + cd2: 00 00 + cd4: b8 4c + cd6: 01 80 + cd8: 0c 01 + cda: 00 00 + cdc: 12 02 + cde: 02 00 + ce0: fc 07 + ce2: 00 00 + ce4: 30 a9 + ce6: 00 80 + ce8: 18 01 + cea: 00 00 + cec: 12 00 + cee: 02 00 + cf0: 02 08 + cf2: 00 00 + cf4: e0 03 + cf6: 01 80 + cf8: 10 04 + cfa: 00 00 + cfc: 12 02 + cfe: 02 00 + d00: 0c 08 + d02: 00 00 + d04: fc 2c + d06: 00 80 + d08: 08 00 + d0a: 00 00 + d0c: 12 00 + d0e: 02 00 + d10: 14 08 + d12: 00 00 + d14: 90 7b + d16: 01 80 + d18: 04 00 + d1a: 00 00 + d1c: 11 00 + d1e: 07 00 27 08 + d22: 00 00 + d24: 38 c8 + d26: 00 80 + d28: 78 05 + d2a: 00 00 + d2c: 12 00 + d2e: 02 00 + d30: 32 08 + d32: 00 00 + d34: 7c 2d + d36: 00 80 + d38: 9c 00 + d3a: 00 00 + d3c: 12 00 + d3e: 02 00 + d40: 44 08 + d42: 00 00 + d44: ac ff + d46: 00 80 + d48: 34 04 + d4a: 00 00 + d4c: 12 02 + d4e: 02 00 + d50: 4e 08 + d52: 00 00 + d54: 40 ec + d56: 00 80 + d58: 2c 00 + d5a: 00 00 + d5c: 12 00 + d5e: 02 00 + d60: 58 08 + d62: 00 00 + d64: 50 5b + d66: 01 80 + d68: 28 00 + d6a: 00 00 + d6c: 11 00 + d6e: 03 00 68 08 lb zero, 134(a6) + d72: 00 00 + d74: 8c 9e + d76: 00 80 + d78: 34 01 + d7a: 00 00 + d7c: 12 00 + d7e: 02 00 + d80: 6e 08 + d82: 00 00 + d84: ac e4 + d86: 00 80 + d88: 18 00 + d8a: 00 00 + d8c: 12 00 + d8e: 02 00 + d90: 74 08 + d92: 00 00 + d94: 14 2d + d96: 00 80 + d98: 08 00 + d9a: 00 00 + d9c: 12 00 + d9e: 02 00 + da0: 7a 08 + da2: 00 00 + da4: 30 a6 + da6: 00 80 + da8: 5c 00 + daa: 00 00 + dac: 12 00 + dae: 02 00 + db0: 81 08 + db2: 00 00 + db4: ec ea + db6: 00 80 + db8: 14 00 + dba: 00 00 + dbc: 12 00 + dbe: 02 00 + dc0: 8f 08 00 00 + dc4: 18 2e + dc6: 00 80 + dc8: 5c 00 + dca: 00 00 + dcc: 12 00 + dce: 02 00 + dd0: a1 08 + dd2: 00 00 + dd4: c0 9f + dd6: 00 80 + dd8: 74 00 + dda: 00 00 + ddc: 12 00 + dde: 02 00 + de0: ab 08 00 00 + de4: c8 29 + de6: 00 80 + de8: fc 00 + dea: 00 00 + dec: 12 00 + dee: 02 00 + df0: c2 08 + df2: 00 00 + df4: bc 49 + df6: 01 80 + df8: ac 01 + dfa: 00 00 + dfc: 12 02 + dfe: 02 00 + e00: cc 08 + e02: 00 00 + e04: 68 a3 + e06: 00 80 + e08: 38 01 + e0a: 00 00 + e0c: 12 00 + e0e: 02 00 + e10: d7 08 00 00 + e14: b8 2c + e16: 00 80 + e18: 00 00 + e1a: 00 00 + e1c: 12 00 + e1e: 02 00 + e20: e1 08 + e22: 00 00 + e24: c8 54 + e26: 01 80 + e28: 4c 00 + e2a: 00 00 + e2c: 12 02 + e2e: 02 00 + e30: ea 08 + e32: 00 00 + e34: 84 35 + e36: 00 80 + e38: dc 00 + e3a: 00 00 + e3c: 12 00 + e3e: 02 00 + e40: f6 08 + e42: 00 00 + e44: dc ea + e46: 00 80 + e48: 04 00 + e4a: 00 00 + e4c: 12 00 + e4e: 02 00 + e50: 09 09 + e52: 00 00 + e54: 98 9b + e56: 00 80 + e58: d4 00 + e5a: 00 00 + e5c: 12 00 + e5e: 02 00 + e60: 10 09 + e62: 00 00 + e64: d4 ae + e66: 00 80 + e68: 6c 00 + e6a: 00 00 + e6c: 12 00 + e6e: 02 00 + e70: 1b 09 00 00 + e74: 0c 65 + e76: 00 80 + e78: 14 03 + e7a: 00 00 + e7c: 12 00 + e7e: 02 00 + e80: 23 09 00 00 sb zero, 18(zero) + e84: 64 c5 + e86: 00 80 + e88: 0c 00 + e8a: 00 00 + e8c: 12 00 + e8e: 02 00 + e90: 37 09 00 00 lui s2, 0 + e94: a8 62 + e96: 00 80 + e98: 24 01 + e9a: 00 00 + e9c: 12 00 + e9e: 02 00 + ea0: 48 09 + ea2: 00 00 + ea4: a0 7b + ea6: 01 80 + ea8: 04 00 + eaa: 00 00 + eac: 11 00 + eae: 07 00 a0 0a + eb2: 00 00 + eb4: 00 00 + eb6: 00 80 + eb8: 50 00 + eba: 00 00 + ebc: 12 00 + ebe: 01 00 + ec0: 5b 09 00 00 + ec4: 04 2d + ec6: 00 80 + ec8: 08 00 + eca: 00 00 + ecc: 12 00 + ece: 02 00 + ed0: 62 09 + ed2: 00 00 + ed4: a0 a4 + ed6: 00 80 + ed8: 90 01 + eda: 00 00 + edc: 12 00 + ede: 02 00 + ee0: 6b 09 00 00 vx_tex s2, zero, zero, zero, rne + ee4: d0 1a + ee6: 01 80 + ee8: 4c 01 + eea: 00 00 + eec: 12 02 + eee: 02 00 + ef0: 08 0b + ef2: 00 00 + ef4: 6c f7 + ef6: 00 80 + ef8: 18 00 + efa: 00 00 + efc: 12 00 + efe: 02 00 + f00: 73 09 00 00 + f04: 58 18 + f06: 01 80 + f08: 2c 01 + f0a: 00 00 + f0c: 12 02 + f0e: 02 00 + f10: 7b 09 00 00 + f14: a0 b1 + f16: 00 80 + f18: bc 01 + f1a: 00 00 + f1c: 12 00 + f1e: 02 00 + f20: 87 09 00 00 + f24: 0c 62 + f26: 00 80 + f28: 9c 00 + f2a: 00 00 + f2c: 12 00 + f2e: 02 00 + f30: 9b 09 00 00 + f34: b4 2b + f36: 00 80 + f38: ec 00 + f3a: 00 00 + f3c: 12 00 + f3e: 02 00 + f40: c1 09 + f42: 00 00 + f44: 5c 93 + f46: 00 80 + f48: 64 00 + f4a: 00 00 + f4c: 12 00 + f4e: 02 00 + f50: ca 09 + f52: 00 00 + f54: 38 a1 + f56: 00 80 + f58: 30 02 + f5a: 00 00 + f5c: 12 00 + f5e: 02 00 + f60: d5 09 + f62: 00 00 + f64: f8 b0 + f66: 00 80 + f68: a8 00 + f6a: 00 00 + f6c: 12 00 + f6e: 02 00 + f70: dd 09 + f72: 00 00 + f74: b4 7b + f76: 01 80 + f78: 28 00 + f7a: 00 00 + f7c: 11 00 + f7e: 09 00 + f80: f7 09 00 00 + f84: 48 aa + f86: 00 80 + f88: 68 01 + f8a: 00 00 + f8c: 12 00 + f8e: 02 00 + f90: fd 09 + f92: 00 00 + f94: c4 4d + f96: 01 80 + f98: 28 02 + f9a: 00 00 + f9c: 12 02 + f9e: 02 00 + fa0: 0b 0a 00 00 + fa4: 8c fc + fa6: 00 80 + fa8: 60 00 + faa: 00 00 + fac: 12 00 + fae: 02 00 + fb0: 14 0a + fb2: 00 00 + fb4: 4c e3 + fb6: 00 80 + fb8: 60 01 + fba: 00 00 + fbc: 12 00 + fbe: 02 00 + fc0: 20 0a + fc2: 00 00 + fc4: f0 07 + fc6: 01 80 + fc8: c0 08 + fca: 00 00 + fcc: 12 02 + fce: 02 00 + fd0: 29 0a + fd2: 00 00 + fd4: b4 e9 + fd6: 00 80 + fd8: 04 01 + fda: 00 00 + fdc: 12 00 + fde: 02 00 + fe0: 2f 0a 00 00 + fe4: fc ac + fe6: 00 80 + fe8: 68 00 + fea: 00 00 + fec: 12 00 + fee: 02 00 + ff0: 3a 0a + ff2: 00 00 + ff4: 60 7c + ff6: 01 80 + ff8: 00 00 + ffa: 00 00 + ffc: 10 00 + ffe: 09 00 + 1000: 46 0a + 1002: 00 00 + 1004: 00 76 + 1006: 01 80 + 1008: 08 04 + 100a: 00 00 + 100c: 11 00 + 100e: 06 00 + 1010: 53 0a 00 00 fadd.s fs4, ft0, ft0, rne + 1014: e8 ea + 1016: 00 80 + 1018: 04 00 + 101a: 00 00 + 101c: 12 00 + 101e: 02 00 + 1020: 68 0a + 1022: 00 00 + 1024: b0 10 + 1026: 01 80 + 1028: a8 07 + 102a: 00 00 + 102c: 12 02 + 102e: 02 00 + 1030: 71 0a + 1032: 00 00 + 1034: 1c f8 + 1036: 00 80 + 1038: 5c 00 + 103a: 00 00 + 103c: 12 00 + 103e: 02 00 + 1040: 79 0a + 1042: 00 00 + 1044: 6c 9c + 1046: 00 80 + 1048: 04 00 + 104a: 00 00 + 104c: 12 00 + 104e: 02 00 + 1050: 87 0a 00 00 + 1054: 20 e7 + 1056: 00 80 + 1058: 60 00 + 105a: 00 00 + 105c: 12 00 + 105e: 02 00 + 1060: 91 0a + 1062: 00 00 + 1064: b0 c3 + 1066: 00 80 + 1068: b0 00 + 106a: 00 00 + 106c: 12 00 + 106e: 02 00 + 1070: 9b 0a 00 00 + 1074: a8 7b + 1076: 01 80 + 1078: 00 00 + 107a: 00 00 + 107c: 10 00 + 107e: 08 00 + 1080: a7 0a 00 00 + 1084: a8 34 + 1086: 00 80 + 1088: dc 00 + 108a: 00 00 + 108c: 12 00 + 108e: 02 00 + 1090: 55 02 + 1092: 00 00 + 1094: 68 00 + 1096: 00 80 + 1098: 30 00 + 109a: 00 00 + 109c: 12 00 + 109e: 02 00 + 10a0: ae 0a + 10a2: 00 00 + 10a4: a8 7b + 10a6: 01 80 + 10a8: 04 00 + 10aa: 00 00 + 10ac: 11 00 + 10ae: 08 00 + 10b0: c5 0a + 10b2: 00 00 + 10b4: fc fa + 10b6: 00 80 + 10b8: 18 00 + 10ba: 00 00 + 10bc: 12 00 + 10be: 02 00 + 10c0: cd 0a + 10c2: 00 00 + 10c4: 70 f9 + 10c6: 00 80 + 10c8: 08 00 + 10ca: 00 00 + 10cc: 12 00 + 10ce: 02 00 + 10d0: d6 0a + 10d2: 00 00 + 10d4: fc fd + 10d6: 00 80 + 10d8: 10 00 + 10da: 00 00 + 10dc: 12 00 + 10de: 02 00 + 10e0: dd 0a + 10e2: 00 00 + 10e4: e0 93 + 10e6: 00 80 + 10e8: b8 07 + 10ea: 00 00 + 10ec: 12 00 + 10ee: 02 00 + 10f0: e7 0a 00 00 jalr s5, zero + 10f4: 1c e3 + 10f6: 00 80 + 10f8: 30 00 + 10fa: 00 00 + 10fc: 12 00 + 10fe: 02 00 + 1100: f6 0a + 1102: 00 00 + 1104: 60 c4 + 1106: 00 80 + 1108: 38 00 + 110a: 00 00 + 110c: 12 00 + 110e: 02 00 + 1110: 02 0b + 1112: 00 00 + 1114: 84 f7 + 1116: 00 80 + 1118: 1c 00 + 111a: 00 00 + 111c: 12 00 + 111e: 02 00 + 1120: 0f 0b 00 00 + 1124: 94 f1 + 1126: 00 80 + 1128: a4 00 + 112a: 00 00 + 112c: 12 00 + 112e: 02 00 + 1130: 16 0b + 1132: 00 00 + 1134: 88 c5 + 1136: 00 80 + 1138: 0c 00 + 113a: 00 00 + 113c: 12 00 + 113e: 02 00 + 1140: 20 0b + 1142: 00 00 + 1144: cc 63 + 1146: 00 80 + 1148: 40 01 + 114a: 00 00 + 114c: 12 00 + 114e: 02 00 + 1150: 2f 0b 00 00 + 1154: b0 cd + 1156: 00 80 + 1158: 7c 01 + 115a: 00 00 + 115c: 12 00 + 115e: 02 00 + 1160: 36 0b + 1162: 00 00 + 1164: 34 e2 + 1166: 00 80 + 1168: 1c 00 + 116a: 00 00 + 116c: 12 00 + 116e: 02 00 + 1170: 40 0b + 1172: 00 00 + 1174: 1c 1c + 1176: 01 80 + 1178: d8 12 + 117a: 00 00 + 117c: 12 02 + 117e: 02 00 + 1180: 49 0b + 1182: 00 00 + 1184: 40 af + 1186: 00 80 + 1188: 7c 00 + 118a: 00 00 + 118c: 12 00 + 118e: 02 00 + 1190: 51 0b + 1192: 00 00 + 1194: 98 60 + 1196: 01 80 + 1198: 00 01 + 119a: 00 00 + 119c: 11 02 + 119e: 03 00 5b 0b lb zero, 181(s6) + 11a2: 00 00 + 11a4: 60 34 + 11a6: 00 80 + 11a8: 14 00 + 11aa: 00 00 + 11ac: 12 00 + 11ae: 02 00 + 11b0: 62 0b + 11b2: 00 00 + 11b4: 20 fc + 11b6: 00 80 + 11b8: 6c 00 + 11ba: 00 00 + 11bc: 12 00 + 11be: 02 00 + 11c0: 6b 0b 00 00 vx_tex s6, zero, zero, zero, rne + 11c4: 70 c5 + 11c6: 00 80 + 11c8: 18 00 + 11ca: 00 00 + 11cc: 12 00 + 11ce: 02 00 + 11d0: 1b 08 00 00 + 11d4: 9c 7b + 11d6: 01 80 + 11d8: 04 00 + 11da: 00 00 + 11dc: 11 00 + 11de: 07 00 75 0b + 11e2: 00 00 + 11e4: c4 e4 + 11e6: 00 80 + 11e8: 5c 02 + 11ea: 00 00 + 11ec: 12 00 + 11ee: 02 00 + 11f0: 80 0b + 11f2: 00 00 + 11f4: 84 19 + 11f6: 01 80 + 11f8: 4c 01 + 11fa: 00 00 + 11fc: 12 02 + 11fe: 02 00 + 1200: 88 0b + 1202: 00 00 + 1204: 5c b3 + 1206: 00 80 + 1208: e8 0f + 120a: 00 00 + 120c: 12 00 + 120e: 02 00 + 1210: 96 0b + 1212: 00 00 + 1214: 94 c5 + 1216: 00 80 + 1218: 68 00 + 121a: 00 00 + 121c: 12 00 + 121e: 02 00 + 1220: a5 0b + 1222: 00 00 + 1224: f4 2e + 1226: 01 80 + 1228: c8 1a + 122a: 00 00 + 122c: 12 02 + 122e: 02 00 + 1230: ae 0b + 1232: 00 00 + 1234: d0 a8 + 1236: 00 80 + 1238: 60 00 + 123a: 00 00 + 123c: 12 00 + 123e: 02 00 + 1240: b4 0b + 1242: 00 00 + 1244: 00 eb + 1246: 00 80 + 1248: 14 00 + 124a: 00 00 + 124c: 12 00 + 124e: 02 00 + 1250: c4 0b + 1252: 00 00 + 1254: d4 93 + 1256: 00 80 + 1258: 0c 00 + 125a: 00 00 + 125c: 12 00 + 125e: 02 00 + 1260: cf 0b 00 00 fnmadd.s fs7, ft0, ft0, ft0, rne + 1264: ec f2 + 1266: 00 80 + 1268: d0 00 + 126a: 00 00 + 126c: 12 00 + 126e: 02 00 + 1270: dc 0b + 1272: 00 00 + 1274: d8 71 + 1276: 01 80 + 1278: 00 00 + 127a: 00 00 + 127c: 10 00 + 127e: 06 00 + 1280: eb 0b 00 00 vx_tex s7, zero, zero, zero, rne + 1284: 1c 2d + 1286: 00 80 + 1288: 50 00 + 128a: 00 00 + 128c: 12 00 + 128e: 02 00 + 1290: f2 0b + 1292: 00 00 + 1294: a8 7b + 1296: 01 80 + 1298: 00 00 + 129a: 00 00 + 129c: 10 00 + 129e: 07 00 3a 05 + 12a2: 00 00 + 12a4: 60 7c + 12a6: 01 80 + 12a8: 00 00 + 12aa: 00 00 + 12ac: 10 00 + 12ae: 09 00 + 12b0: f9 0b + 12b2: 00 00 + 12b4: 14 eb + 12b6: 00 80 + 12b8: 2c 01 + 12ba: 00 00 + 12bc: 12 00 + 12be: 02 00 + 12c0: 02 0c + 12c2: 00 00 + 12c4: 80 f8 + 12c6: 00 80 + 12c8: 88 00 + 12ca: 00 00 + 12cc: 12 00 + 12ce: 02 00 + 12d0: 0b 0c 00 00 + 12d4: a4 7b + 12d6: 01 80 + 12d8: 04 00 + 12da: 00 00 + 12dc: 11 00 + 12de: 07 00 83 0c + 12e2: 00 00 + 12e4: 74 34 + 12e6: 00 80 + 12e8: 34 00 + 12ea: 00 00 + 12ec: 12 00 + 12ee: 02 00 + 12f0: 37 0b 00 00 lui s6, 0 + 12f4: 98 c4 + 12f6: 00 80 + 12f8: 50 00 + 12fa: 00 00 + 12fc: 12 00 + 12fe: 02 00 + 1300: 23 0c 00 00 sb zero, 24(zero) + 1304: 34 d0 + 1306: 00 80 + 1308: 00 12 + 130a: 00 00 + 130c: 12 00 + 130e: 02 00 + 1310: 30 0c + 1312: 00 00 + 1314: 38 f2 + 1316: 00 80 + 1318: b4 00 + 131a: 00 00 + 131c: 12 00 + 131e: 02 00 + 1320: 3d 0c + 1322: 00 00 + 1324: 8c a6 + 1326: 00 80 + 1328: 44 02 + 132a: 00 00 + 132c: 12 00 + 132e: 02 00 + 1330: 45 0c + 1332: 00 00 + 1334: 6c 2d + 1336: 00 80 + 1338: 08 00 + 133a: 00 00 + 133c: 12 00 + 133e: 02 00 + 1340: 4b 0c 00 00 fnmsub.s fs8, ft0, ft0, ft0, rne + 1344: e0 ea + 1346: 00 80 + 1348: 04 00 + 134a: 00 00 + 134c: 12 00 + 134e: 02 00 + 1350: 5e 0c + 1352: 00 00 + 1354: 98 80 + 1356: 00 80 + 1358: c4 12 + 135a: 00 00 + 135c: 12 00 + 135e: 02 00 + 1360: 67 0c 00 00 jalr s8, zero + 1364: 4c 32 + 1366: 00 80 + 1368: 14 02 + 136a: 00 00 + 136c: 12 00 + 136e: 02 00 + 1370: 74 0c + 1372: 00 00 + 1374: e0 5e + 1376: 01 80 + 1378: 01 01 + 137a: 00 00 + 137c: 11 00 + 137e: 03 00 7c 0c lb zero, 199(s8) + 1382: 00 00 + 1384: 0c 2d + 1386: 00 80 + 1388: 08 00 + 138a: 00 00 + 138c: 12 00 + 138e: 02 00 + 1390: 82 0c + 1392: 00 00 + 1394: a0 2c + 1396: 00 80 + 1398: 00 00 + 139a: 00 00 + 139c: 12 00 + 139e: 02 00 + 13a0: 88 0c + 13a2: 00 00 + 13a4: bc f3 + 13a6: 00 80 + 13a8: 20 01 + 13aa: 00 00 + 13ac: 12 00 + 13ae: 02 00 + 13b0: 95 0c + 13b2: 00 00 + 13b4: 6c b0 + 13b6: 00 80 + 13b8: 8c 00 + 13ba: 00 00 + 13bc: 12 00 + 13be: 02 00 + 13c0: 9c 0c + 13c2: 00 00 + 13c4: 28 f5 + 13c6: 00 80 + 13c8: 14 00 + 13ca: 00 00 + 13cc: 12 00 + 13ce: 02 00 + 13d0: ab 0c 00 00 + 13d4: 9c c3 + 13d6: 00 80 + 13d8: 14 00 + 13da: 00 00 + 13dc: 12 00 + 13de: 02 00 + 13e0: b4 0c + 13e2: 00 00 + 13e4: 1c d0 + 13e6: 00 80 + 13e8: 18 00 + 13ea: 00 00 + 13ec: 12 00 + 13ee: 02 00 + 13f0: bf 0c 00 00 + 13f4: 10 e3 + 13f6: 00 80 + 13f8: 0c 00 + 13fa: 00 00 + 13fc: 12 00 + 13fe: 02 00 + 1400: c9 0c + 1402: 00 00 + 1404: 34 a0 + 1406: 00 80 + 1408: b0 00 + 140a: 00 00 + 140c: 12 00 + 140e: 02 00 + 1410: d3 0c 00 00 fadd.s fs9, ft0, ft0, rne + 1414: 98 30 + 1416: 00 80 + 1418: b4 01 + 141a: 00 00 + 141c: 12 00 + 141e: 02 00 + 1420: e3 0c 00 00 beqz zero, 2072 + 1424: a0 f7 + 1426: 00 80 + 1428: 10 00 + 142a: 00 00 + 142c: 12 00 + 142e: 02 00 + 1430: ee 0c + 1432: 00 00 + 1434: 8c fb + 1436: 00 80 + 1438: 94 00 + 143a: 00 00 + 143c: 12 00 + 143e: 02 00 + 1440: f6 0c + 1442: 00 00 + 1444: c8 ad + 1446: 00 80 + 1448: ac 00 + 144a: 00 00 + 144c: 12 00 + 144e: 02 00 + 1450: fc 0c + 1452: 00 00 + 1454: 74 2e + 1456: 00 80 + 1458: 00 00 + 145a: 00 00 + 145c: 12 00 + 145e: 02 00 + 1460: 07 0d 00 00 + 1464: 08 7a + 1466: 01 80 + 1468: 6c 01 + 146a: 00 00 + 146c: 11 00 + 146e: 06 00 + 1470: 17 0d 00 00 auipc s10, 0 + 1474: ec 4f + 1476: 01 80 + 1478: dc 04 + 147a: 00 00 + 147c: 12 02 + 147e: 02 00 + 1480: fb 0b 00 00 + 1484: 6c ec + 1486: 00 80 + 1488: 80 00 + 148a: 00 00 + 148c: 12 00 + 148e: 02 00 + 1490: 24 0d + 1492: 00 00 + 1494: 5c f7 + 1496: 00 80 + 1498: 10 00 + 149a: 00 00 + 149c: 12 00 + 149e: 02 00 + 14a0: 2a 0d + 14a2: 00 00 + 14a4: ec 2c + 14a6: 00 80 + 14a8: 08 00 + 14aa: 00 00 + 14ac: 12 00 + 14ae: 02 00 + 14b0: 31 0d + 14b2: 00 00 + 14b4: e4 ea + 14b6: 00 80 + 14b8: 04 00 + 14ba: 00 00 + 14bc: 12 00 + 14be: 02 00 + 14c0: 46 0d + 14c2: 00 00 + 14c4: 40 9d + 14c6: 00 80 + 14c8: 4c 01 + 14ca: 00 00 + 14cc: 12 00 + 14ce: 02 00 + 14d0: 50 0d + 14d2: 00 00 + 14d4: 1c 9d + 14d6: 00 80 + 14d8: 24 00 + 14da: 00 00 + 14dc: 12 00 + 14de: 02 00 + +Disassembly of section .strtab: + +00000000 .strtab: + 0: 00 76 + 2: 78 5f + 4: 73 74 61 72 csrrci s0, 1830, 2 + 8: 74 2e + a: 53 2e 6f 00 fadd.s ft8, ft10, ft6, rdn + e: 6c 61 + 10: 62 65 + 12: 6c 5f + 14: 65 78 + 16: 69 74 + 18: 5f 6e 65 78 + 1c: 74 00 + 1e: 52 45 + 20: 54 55 + 22: 52 4e + 24: 00 5f + 26: 5f 63 61 6c + 2a: 6c 5f + 2c: 61 74 + 2e: 65 78 + 30: 69 74 + 32: 2e 63 + 34: 00 72 + 36: 65 67 + 38: 69 73 + 3a: 74 65 + 3c: 72 5f + 3e: 66 69 + 40: 6e 69 + 42: 00 70 + 44: 6f 63 6c 5f jal t1, 812534 + 48: 76 6f + 4a: 72 74 + 4c: 65 78 + 4e: 5f 6b 65 72 + 52: 6e 65 + 54: 6c 2d + 56: 31 38 + 58: 2d 36 + 5a: 32 2d + 5c: 32 36 + 5e: 2d 65 + 60: 32 2d + 62: 39 33 + 64: 2e 63 + 66: 00 70 + 68: 61 72 + 6a: 61 6c + 6c: 6c 65 + 6e: 6c 5f + 70: 62 63 + 72: 00 5f + 74: 5f 70 6f 63 + 78: 6c 5f + 7a: 70 72 + 7c: 69 6e + 7e: 74 5f + 80: 66 6c + 82: 6f 61 74 73 jal sp, 290614 + 86: 5f 66 6c 6f + 8a: 61 74 + 8c: 00 5f + 8e: 5f 70 6f 63 + 92: 6c 5f + 94: 70 72 + 96: 69 6e + 98: 74 5f + 9a: 69 6e + 9c: 74 73 + 9e: 5f 75 63 68 + a2: 61 72 + a4: 00 5f + a6: 5f 70 6f 63 + aa: 6c 5f + ac: 70 72 + ae: 69 6e + b0: 74 5f + b2: 69 6e + b4: 74 73 + b6: 5f 75 69 6e + ba: 74 00 + bc: 5f 5f 70 6f + c0: 63 6c 5f 70 bltu t5, t0, 1816 + c4: 72 69 + c6: 6e 74 + c8: 5f 69 6e 74 + cc: 73 5f 75 73 csrrwi t5, 1847, 10 + d0: 68 6f + d2: 72 74 + d4: 00 5f + d6: 5f 70 6f 63 + da: 6c 5f + dc: 70 72 + de: 69 6e + e0: 74 66 + e2: 00 5f + e4: 5f 70 6f 63 + e8: 6c 5f + ea: 70 72 + ec: 69 6e + ee: 74 66 + f0: 5f 66 6c 6f + f4: 61 74 + f6: 5f 6c 69 62 + fa: 63 00 5f 5f beq t5, s5, 1504 + fe: 70 6f + 100: 63 6c 5f 70 bltu t5, t0, 1816 + 104: 72 69 + 106: 6e 74 + 108: 66 5f + 10a: 66 6f + 10c: 72 6d + 10e: 61 74 + 110: 5f 66 75 6c + 114: 6c 00 + 116: 5f 5f 70 6f + 11a: 63 6c 5f 70 bltu t5, t0, 1816 + 11e: 72 69 + 120: 6e 74 + 122: 66 5f + 124: 70 75 + 126: 74 63 + 128: 68 77 + 12a: 00 5f + 12c: 5f 70 6f 63 + 130: 6c 5f + 132: 70 72 + 134: 69 6e + 136: 74 66 + 138: 5f 75 6c 6f + 13c: 6e 67 + 13e: 00 76 + 140: 78 5f + 142: 73 79 73 63 csrrci s2, 1591, 6 + 146: 61 6c + 148: 6c 73 + 14a: 2e 63 + 14c: 00 76 + 14e: 78 5f + 150: 73 70 61 77 csrci 1910, 2 + 154: 6e 2e + 156: 63 00 73 70 beq t1, t2, 1792 + 15a: 61 77 + 15c: 6e 5f + 15e: 6b 65 72 6e + 162: 65 6c + 164: 5f 61 6c 6c + 168: 5f 73 74 75 + 16c: 62 00 + 16e: 73 70 61 77 csrci 1910, 2 + 172: 6e 5f + 174: 6b 65 72 6e + 178: 65 6c + 17a: 5f 72 65 6d + 17e: 5f 73 74 75 + 182: 62 00 + 184: 73 70 61 77 csrci 1910, 2 + 188: 6e 5f + 18a: 6b 65 72 6e + 18e: 65 6c + 190: 5f 61 6c 6c + 194: 5f 63 62 00 + 198: 76 78 + 19a: 5f 70 65 72 + 19e: 66 2e + 1a0: 63 00 73 6e beq t1, t2, 1760 + 1a4: 70 72 + 1a6: 69 6e + 1a8: 74 66 + 1aa: 2e 63 + 1ac: 00 76 + 1ae: 66 70 + 1b0: 72 69 + 1b2: 6e 74 + 1b4: 66 2e + 1b6: 63 00 62 6c beq tp, t1, 1728 + 1ba: 61 6e + 1bc: 6b 73 2e 34 vx_tex t1, t3, sp, t1, dyn + 1c0: 34 37 + 1c2: 30 00 + 1c4: 7a 65 + 1c6: 72 6f + 1c8: 65 73 + 1ca: 2e 34 + 1cc: 34 37 + 1ce: 31 00 + 1d0: 5f 5f 61 74 + 1d4: 65 78 + 1d6: 69 74 + 1d8: 2e 63 + 1da: 00 6d + 1dc: 61 6c + 1de: 6c 6f + 1e0: 63 72 2e 63 bgeu t3, s2, 1572 + 1e4: 00 6c + 1e6: 64 74 + 1e8: 6f 61 2e 63 jal sp, 943666 + 1ec: 00 65 + 1ee: 73 68 64 6e csrrsi a6, 1766, 8 + 1f2: 31 00 + 1f4: 65 73 + 1f6: 68 75 + 1f8: 70 31 + 1fa: 00 6d + 1fc: 31 36 + 1fe: 6d 00 + 200: 65 69 + 202: 73 6e 61 6e csrrsi t3, 1766, 2 + 206: 2e 70 + 208: 61 72 + 20a: 74 2e + 20c: 30 00 + 20e: 65 6e + 210: 65 67 + 212: 00 65 + 214: 69 73 + 216: 6e 65 + 218: 67 00 65 6d jr 1750(a0) + 21c: 6f 76 69 00 jal a2, 618502 + 220: 65 63 + 222: 6d 70 + 224: 00 65 + 226: 69 73 + 228: 69 6e + 22a: 66 2e + 22c: 70 61 + 22e: 72 74 + 230: 2e 30 + 232: 00 65 + 234: 73 68 69 66 csrrsi a6, 1638, 18 + 238: 74 2e + 23a: 70 61 + 23c: 72 74 + 23e: 2e 30 + 240: 00 65 + 242: 6e 6f + 244: 72 6d + 246: 6c 7a + 248: 00 65 + 24a: 6d 64 + 24c: 6e 6f + 24e: 72 6d + 250: 00 65 + 252: 69 72 + 254: 65 6d + 256: 61 69 + 258: 6e 00 + 25a: 65 6d + 25c: 6f 76 6f 2e jal a2, 1012454 + 260: 69 73 + 262: 72 61 + 264: 2e 30 + 266: 00 65 + 268: 6d 75 + 26a: 6c 00 + 26c: 65 64 + 26e: 69 76 + 270: 00 65 + 272: 31 31 + 274: 33 74 6f 65 + 278: 2e 69 + 27a: 73 72 61 2e csrrci tp, 742, 2 + 27e: 30 00 + 280: 65 7a + 282: 65 72 + 284: 6f 00 65 6f j 329462 + 288: 6e 65 + 28a: 00 65 + 28c: 74 65 + 28e: 6e 73 + 290: 00 65 + 292: 6d 74 + 294: 65 6e + 296: 73 00 62 6d + 29a: 61 73 + 29c: 6b 00 6c 6f vx_tex zero, s8, s6, a3, rne + 2a0: 63 61 6c 65 bltu s8, s6, 1602 + 2a4: 63 6f 6e 76 bltu t3, t1, 1918 + 2a8: 2e 63 + 2aa: 00 6d + 2ac: 65 6d + 2ae: 63 68 72 2e bltu tp, t2, 752 + 2b2: 63 00 6d 6c beq s10, t1, 1728 + 2b6: 6f 63 6b 2e jal t1, 746214 + 2ba: 63 00 6d 70 beq s10, t1, 1792 + 2be: 72 65 + 2c0: 63 2e 63 00 + 2c4: 70 30 + 2c6: 35 2e + 2c8: 33 32 39 36 + 2cc: 00 73 + 2ce: 5f 66 72 65 + 2d2: 78 70 + 2d4: 2e 63 + 2d6: 00 73 + 2d8: 62 72 + 2da: 6b 72 2e 63 vx_tex tp, t3, s2, a2, dyn + 2de: 00 73 + 2e0: 70 72 + 2e2: 69 6e + 2e4: 74 66 + 2e6: 2e 63 + 2e8: 00 73 + 2ea: 74 72 + 2ec: 63 70 79 2e bgeu s2, t2, 736 + 2f0: 63 00 73 74 beq t1, t2, 1856 + 2f4: 72 6c + 2f6: 65 6e + 2f8: 2e 63 + 2fa: 00 73 + 2fc: 74 72 + 2fe: 6e 63 + 300: 70 79 + 302: 2e 63 + 304: 00 62 + 306: 6c 61 + 308: 6e 6b + 30a: 73 2e 34 34 csrrs t3, mtval, s0 + 30e: 34 37 + 310: 00 7a + 312: 65 72 + 314: 6f 65 73 2e jal a0, 223974 + 318: 34 34 + 31a: 34 38 + 31c: 00 61 + 31e: 73 73 65 72 csrrci t1, 1830, 10 + 322: 74 2e + 324: 63 00 66 69 beq a2, s6, 1664 + 328: 70 72 + 32a: 69 6e + 32c: 74 66 + 32e: 2e 63 + 330: 00 6c + 332: 6f 63 61 6c jal t1, 91846 + 336: 65 2e + 338: 63 00 6d 62 beq s10, t1, 1568 + 33c: 74 6f + 33e: 77 63 5f 72 + 342: 2e 63 + 344: 00 6d + 346: 65 6d + 348: 63 70 79 2e bgeu s2, t2, 736 + 34c: 63 00 6d 65 beq s10, s6, 1600 + 350: 6d 6d + 352: 6f 76 65 2d jal a2, 357078 + 356: 73 74 75 62 csrrci s0, 1575, 10 + 35a: 2e 63 + 35c: 00 5f + 35e: 5f 73 70 72 + 362: 69 6e + 364: 74 5f + 366: 72 2e + 368: 70 61 + 36a: 72 74 + 36c: 2e 30 + 36e: 00 5f + 370: 5f 73 62 70 + 374: 72 69 + 376: 6e 74 + 378: 66 00 + 37a: 62 6c + 37c: 61 6e + 37e: 6b 73 2e 34 vx_tex t1, t3, sp, t1, dyn + 382: 34 36 + 384: 31 00 + 386: 7a 65 + 388: 72 6f + 38a: 65 73 + 38c: 2e 34 + 38e: 34 36 + 390: 32 00 + 392: 77 63 74 6f + 396: 6d 62 + 398: 5f 72 2e 63 + 39c: 00 77 + 39e: 73 65 74 75 csrrsi a0, 1879, 8 + 3a2: 70 2e + 3a4: 63 00 61 62 beq sp, t1, 1568 + 3a8: 6f 72 74 2e jal tp, 293606 + 3ac: 63 00 66 66 beq a2, t1, 1632 + 3b0: 6c 75 + 3b2: 73 68 2e 63 csrrsi a6, 1586, 28 + 3b6: 00 66 + 3b8: 69 6e + 3ba: 64 66 + 3bc: 70 2e + 3be: 63 00 5f 5f beq t5, s5, 1504 + 3c2: 66 70 + 3c4: 5f 6c 6f 63 + 3c8: 6b 00 5f 5f vx_tex zero, t5, s5, a1, rne + 3cc: 73 69 6e 69 csrrsi s2, 1686, 28 + 3d0: 74 2e + 3d2: 70 61 + 3d4: 72 74 + 3d6: 2e 30 + 3d8: 00 5f + 3da: 5f 66 70 5f + 3de: 75 6e + 3e0: 6c 6f + 3e2: 63 6b 00 66 bltu zero, zero, 1654 + 3e6: 70 75 + 3e8: 74 77 + 3ea: 63 2e 63 00 + 3ee: 66 76 + 3f0: 77 72 69 74 + 3f4: 65 2e + 3f6: 63 00 66 77 beq a2, s6, 1888 + 3fa: 61 6c + 3fc: 6b 2e 63 00 vx_tex t3, t1, t1, zero, rdn + 400: 6d 61 + 402: 6b 65 62 75 + 406: 66 2e + 408: 63 00 73 69 beq t1, s7, 1664 + 40c: 67 6e 61 6c + 410: 2e 63 + 412: 00 5f + 414: 69 6e + 416: 69 74 + 418: 5f 73 69 67 + 41c: 6e 61 + 41e: 6c 5f + 420: 72 2e + 422: 70 61 + 424: 72 74 + 426: 2e 30 + 428: 00 73 + 42a: 69 67 + 42c: 6e 61 + 42e: 6c 72 + 430: 2e 63 + 432: 00 73 + 434: 74 64 + 436: 69 6f + 438: 2e 63 + 43a: 00 77 + 43c: 62 75 + 43e: 66 2e + 440: 63 00 77 63 beq a4, s7, 1568 + 444: 72 74 + 446: 6f 6d 62 2e jal s10, 156390 + 44a: 63 00 77 72 beq a4, t2, 1824 + 44e: 69 74 + 450: 65 72 + 452: 2e 63 + 454: 00 63 + 456: 6c 6f + 458: 73 65 72 2e csrrsi a0, 743, 4 + 45c: 63 00 66 63 beq a2, s6, 1568 + 460: 6c 6f + 462: 73 65 2e 63 csrrsi a0, 1586, 28 + 466: 00 66 + 468: 73 74 61 74 csrrci s0, 1862, 2 + 46c: 72 2e + 46e: 63 00 69 73 beq s2, s6, 1824 + 472: 61 74 + 474: 74 79 + 476: 72 2e + 478: 63 00 6c 73 beq s8, s6, 1824 + 47c: 65 65 + 47e: 6b 72 2e 63 vx_tex tp, t3, s2, a2, dyn + 482: 00 72 + 484: 65 61 + 486: 64 72 + 488: 2e 63 + 48a: 00 6c + 48c: 69 62 + 48e: 67 63 63 32 + 492: 2e 63 + 494: 00 64 + 496: 69 76 + 498: 64 66 + 49a: 33 2e 63 00 slt t3, t1, t1 + 49e: 6d 75 + 4a0: 6c 64 + 4a2: 66 33 + 4a4: 2e 63 + 4a6: 00 65 + 4a8: 71 74 + 4aa: 66 32 + 4ac: 2e 63 + 4ae: 00 67 + 4b0: 65 74 + 4b2: 66 32 + 4b4: 2e 63 + 4b6: 00 6c + 4b8: 65 74 + 4ba: 66 32 + 4bc: 2e 63 + 4be: 00 6d + 4c0: 75 6c + 4c2: 74 66 + 4c4: 33 2e 63 00 slt t3, t1, t1 + 4c8: 73 75 62 74 csrrci a0, 1862, 4 + 4cc: 66 33 + 4ce: 2e 63 + 4d0: 00 66 + 4d2: 69 78 + 4d4: 74 66 + 4d6: 73 69 2e 63 csrrsi s2, 1586, 28 + 4da: 00 66 + 4dc: 6c 6f + 4de: 61 74 + 4e0: 73 69 74 66 csrrsi s2, 1639, 8 + 4e4: 2e 63 + 4e6: 00 65 + 4e8: 78 74 + 4ea: 65 6e + 4ec: 64 73 + 4ee: 66 64 + 4f0: 66 32 + 4f2: 2e 63 + 4f4: 00 65 + 4f6: 78 74 + 4f8: 65 6e + 4fa: 64 64 + 4fc: 66 74 + 4fe: 66 32 + 500: 2e 63 + 502: 00 74 + 504: 72 75 + 506: 6e 63 + 508: 74 66 + 50a: 64 66 + 50c: 32 2e + 50e: 63 00 63 74 beq t1, t1, 1856 + 512: 79 70 + 514: 65 5f + 516: 2e 63 + 518: 00 69 + 51a: 6d 70 + 51c: 75 72 + 51e: 65 2e + 520: 63 00 69 6d beq s2, s6, 1728 + 524: 70 75 + 526: 72 65 + 528: 5f 64 61 74 + 52c: 61 00 + 52e: 5f 5f 66 69 + 532: 6e 69 + 534: 5f 61 72 72 + 538: 61 79 + 53a: 5f 65 6e 64 + 53e: 00 5f + 540: 5f 66 69 6e + 544: 69 5f + 546: 61 72 + 548: 72 61 + 54a: 79 5f + 54c: 73 74 61 72 csrrci s0, 1830, 2 + 550: 74 00 + 552: 5f 5f 69 6e + 556: 69 74 + 558: 5f 61 72 72 + 55c: 61 79 + 55e: 5f 65 6e 64 + 562: 00 5f + 564: 5f 70 72 65 + 568: 69 6e + 56a: 69 74 + 56c: 5f 61 72 72 + 570: 61 79 + 572: 5f 65 6e 64 + 576: 00 5f + 578: 5f 69 6e 69 + 57c: 74 5f + 57e: 61 72 + 580: 72 61 + 582: 79 5f + 584: 73 74 61 72 csrrci s0, 1830, 2 + 588: 74 00 + 58a: 5f 5f 70 72 + 58e: 65 69 + 590: 6e 69 + 592: 74 5f + 594: 61 72 + 596: 72 61 + 598: 79 5f + 59a: 73 74 61 72 csrrci s0, 1830, 2 + 59e: 74 00 + 5a0: 5f 6d 70 72 + 5a4: 65 63 + 5a6: 5f 6c 6f 67 + 5aa: 31 30 + 5ac: 00 5f + 5ae: 5f 61 6e 79 + 5b2: 5f 6f 6e 00 + 5b6: 5f 69 73 61 + 5ba: 74 74 + 5bc: 79 5f + 5be: 72 00 + 5c0: 5f 5f 6d 70 + 5c4: 72 65 + 5c6: 63 5f 74 69 bge s0, s7, 1694 + 5ca: 6e 79 + 5cc: 74 65 + 5ce: 6e 73 + 5d0: 00 73 + 5d2: 74 72 + 5d4: 63 70 79 00 bgeu s2, t2, 0 + 5d8: 5f 67 65 74 + 5dc: 70 69 + 5de: 64 00 + 5e0: 5f 6c 73 65 + 5e4: 65 6b + 5e6: 5f 72 00 5f + 5ea: 5f 67 65 74 + 5ee: 66 32 + 5f0: 00 5f + 5f2: 6b 69 6c 6c + 5f6: 5f 72 00 5f + 5fa: 5f 65 71 74 + 5fe: 66 32 + 600: 00 5f + 602: 77 63 72 74 + 606: 6f 6d 62 5f jal s10, 157174 + 60a: 72 00 + 60c: 5f 5f 73 73 + 610: 65 65 + 612: 6b 00 5f 5f vx_tex zero, t5, s5, a1, rne + 616: 73 69 6e 69 csrrsi s2, 1686, 28 + 61a: 74 00 + 61c: 5f 5f 73 77 + 620: 62 75 + 622: 66 5f + 624: 72 00 + 626: 5f 73 65 74 + 62a: 6c 6f + 62c: 63 61 6c 65 bltu s8, s6, 1602 + 630: 5f 72 00 5f + 634: 5f 73 74 61 + 638: 63 6b 5f 75 bltu t5, s5, 1878 + 63c: 73 61 67 65 csrrsi sp, 1622, 14 + 640: 00 5f + 642: 5f 73 66 6d + 646: 6f 72 65 67 jal tp, 358006 + 64a: 6c 75 + 64c: 65 00 + 64e: 5f 5f 6d 61 + 652: 6c 6c + 654: 6f 63 5f 75 jal t1, 1011540 + 658: 6e 6c + 65a: 6f 63 6b 00 jal t1, 745478 + 65e: 5f 5f 66 6c + 662: 6f 61 74 73 jal sp, 290614 + 666: 69 74 + 668: 66 00 + 66a: 6d 65 + 66c: 6d 6d + 66e: 6f 76 65 00 jal a2, 356358 + 672: 5f 63 6c 65 + 676: 61 6e + 678: 75 70 + 67a: 00 73 + 67c: 6e 70 + 67e: 72 69 + 680: 6e 74 + 682: 66 00 + 684: 5f 42 61 6c + 688: 6c 6f + 68a: 63 00 5f 5f beq t5, s5, 1504 + 68e: 6c 6f + 690: 63 61 6c 65 bltu s8, s6, 1602 + 694: 63 6f 6e 76 bltu t3, t1, 1918 + 698: 5f 6c 00 5f + 69c: 66 73 + 69e: 74 61 + 6a0: 74 5f + 6a2: 72 00 + 6a4: 65 72 + 6a6: 72 6e + 6a8: 6f 00 5f 5f j 986612 + 6ac: 73 65 6f 66 csrrsi a0, 1638, 30 + 6b0: 72 65 + 6b2: 61 64 + 6b4: 00 5f + 6b6: 5f 73 74 61 + 6ba: 63 6b 5f 73 bltu t5, s5, 1846 + 6be: 69 7a + 6c0: 65 00 + 6c2: 67 5f 77 73 + 6c6: 70 61 + 6c8: 77 6e 5f 61 + 6cc: 72 67 + 6ce: 73 00 5f 5f + 6d2: 53 44 41 54 + 6d6: 41 5f + 6d8: 42 45 + 6da: 47 49 4e 5f + 6de: 5f 00 6d 65 + 6e2: 6d 63 + 6e4: 70 79 + 6e6: 00 5f + 6e8: 63 6c 65 61 bltu a0, s6, 1560 + 6ec: 6e 75 + 6ee: 70 5f + 6f0: 72 00 + 6f2: 5f 73 76 66 + 6f6: 70 72 + 6f8: 69 6e + 6fa: 74 66 + 6fc: 5f 72 00 5f + 700: 5f 72 61 74 + 704: 69 6f + 706: 00 5f + 708: 5f 67 6c 6f + 70c: 62 61 + 70e: 6c 5f + 710: 70 6f + 712: 69 6e + 714: 74 65 + 716: 72 00 + 718: 5f 5f 6c 65 + 71c: 74 66 + 71e: 32 00 + 720: 5f 72 61 69 + 724: 73 65 5f 72 csrrsi a0, 1829, 30 + 728: 00 5f + 72a: 66 73 + 72c: 74 61 + 72e: 74 00 + 730: 5f 5f 61 73 + 734: 73 65 72 74 csrrsi a0, 1863, 4 + 738: 5f 66 75 6e + 73c: 63 00 5f 5f beq t5, s5, 1504 + 740: 6d 70 + 742: 72 65 + 744: 63 5f 74 65 bge s0, s7, 1630 + 748: 6e 73 + 74a: 00 5f + 74c: 5f 6d 61 6c + 750: 6c 6f + 752: 63 5f 74 6f bge s0, s7, 1790 + 756: 70 5f + 758: 70 61 + 75a: 64 00 + 75c: 5f 67 65 74 + 760: 70 69 + 762: 64 5f + 764: 72 00 + 766: 5f 6c 6f 63 + 76a: 61 6c + 76c: 65 63 + 76e: 6f 6e 76 5f jal t3, 421366 + 772: 72 00 + 774: 5f 5f 73 66 + 778: 76 77 + 77a: 72 69 + 77c: 74 65 + 77e: 5f 72 00 5f + 782: 5f 69 32 62 + 786: 00 5f + 788: 5f 73 69 67 + 78c: 74 72 + 78e: 61 6d + 790: 70 5f + 792: 72 00 + 794: 5f 73 62 72 + 798: 6b 5f 72 00 + 79c: 5f 72 65 61 + 7a0: 64 5f + 7a2: 72 00 + 7a4: 5f 66 63 6c + 7a8: 6f 73 65 5f jal t1, 357878 + 7ac: 72 00 + 7ae: 5f 70 6f 63 + 7b2: 6c 5f + 7b4: 6b 65 72 6e + 7b8: 65 6c + 7ba: 5f 6f 63 6c + 7be: 70 72 + 7c0: 69 6e + 7c2: 74 66 + 7c4: 5f 77 6f 72 + 7c8: 6b 67 72 6f + 7cc: 75 70 + 7ce: 00 66 + 7d0: 66 6c + 7d2: 75 73 + 7d4: 68 00 + 7d6: 5f 5f 6d 61 + 7da: 6c 6c + 7dc: 6f 63 5f 6d jal t1, 1011412 + 7e0: 61 78 + 7e2: 5f 73 62 72 + 7e6: 6b 65 64 5f + 7ea: 6d 65 + 7ec: 6d 00 + 7ee: 5f 5f 65 78 + 7f2: 74 65 + 7f4: 6e 64 + 7f6: 73 66 64 66 csrrsi a2, 1638, 8 + 7fa: 32 00 + 7fc: 5f 5f 62 32 + 800: 64 00 + 802: 5f 5f 75 6d + 806: 6f 64 64 69 jal s0, 288406 + 80a: 33 00 5f 69 + 80e: 73 61 74 74 csrrsi sp, 1863, 8 + 812: 79 00 + 814: 5f 67 6c 6f + 818: 62 61 + 81a: 6c 5f + 81c: 69 6d + 81e: 70 75 + 820: 72 65 + 822: 5f 70 74 72 + 826: 00 5f + 828: 72 65 + 82a: 61 6c + 82c: 6c 6f + 82e: 63 5f 72 00 bge tp, t2, 30 + 832: 5f 5f 6c 69 + 836: 62 63 + 838: 5f 69 6e 69 + 83c: 74 5f + 83e: 61 72 + 840: 72 61 + 842: 79 00 + 844: 5f 5f 75 64 + 848: 69 76 + 84a: 64 69 + 84c: 33 00 5f 66 + 850: 70 75 + 852: 74 77 + 854: 63 5f 72 00 bge tp, t2, 30 + 858: 5f 5f 6d 70 + 85c: 72 65 + 85e: 63 5f 62 69 bge tp, s6, 1694 + 862: 67 74 65 6e + 866: 73 00 5f 5f + 86a: 73 32 62 00 csrrc tp, 6, tp + 86e: 61 62 + 870: 6f 72 74 00 jal tp, 292870 + 874: 5f 73 62 72 + 878: 6b 00 5f 5f vx_tex zero, t5, s5, a1, rne + 87c: 6d 63 + 87e: 6d 70 + 880: 00 5f + 882: 5f 66 70 5f + 886: 6c 6f + 888: 63 6b 5f 61 bltu t5, s5, 1558 + 88c: 6c 6c + 88e: 00 5f + 890: 5f 6c 69 62 + 894: 63 5f 66 69 bge a2, s6, 1694 + 898: 6e 69 + 89a: 5f 61 72 72 + 89e: 61 79 + 8a0: 00 5f + 8a2: 5f 68 69 30 + 8a6: 62 69 + 8a8: 74 73 + 8aa: 00 5f + 8ac: 70 6f + 8ae: 63 6c 5f 6b bltu t5, s5, 1720 + 8b2: 65 72 + 8b4: 6e 65 + 8b6: 6c 5f + 8b8: 6f 63 6c 70 jal t1, 812806 + 8bc: 72 69 + 8be: 6e 74 + 8c0: 66 00 + 8c2: 5f 5f 66 69 + 8c6: 78 74 + 8c8: 66 73 + 8ca: 69 00 + 8cc: 5f 5f 70 6f + 8d0: 77 35 6d 75 + 8d4: 6c 74 + 8d6: 00 76 + 8d8: 78 5f + 8da: 73 65 74 5f csrrsi a0, 1527, 8 + 8de: 73 70 00 5f csrci 1520, 0 + 8e2: 5f 63 6c 7a + 8e6: 73 69 32 00 csrrsi s2, fcsr, 4 + 8ea: 5f 73 6e 70 + 8ee: 72 69 + 8f0: 6e 74 + 8f2: 66 5f + 8f4: 72 00 + 8f6: 5f 5f 73 66 + 8fa: 70 5f + 8fc: 6c 6f + 8fe: 63 6b 5f 61 bltu t5, s5, 1558 + 902: 63 71 75 69 bgeu a0, s7, 1666 + 906: 72 65 + 908: 00 6d + 90a: 65 6d + 90c: 63 68 72 00 bltu tp, t2, 16 + 910: 5f 73 70 72 + 914: 69 6e + 916: 74 66 + 918: 5f 72 00 5f + 91c: 66 72 + 91e: 65 65 + 920: 5f 72 00 5f + 924: 5f 6c 6f 63 + 928: 61 6c + 92a: 65 5f + 92c: 6d 62 + 92e: 5f 63 75 72 + 932: 5f 6d 61 78 + 936: 00 5f + 938: 5f 63 61 6c + 93c: 6c 5f + 93e: 65 78 + 940: 69 74 + 942: 70 72 + 944: 6f 63 73 00 jal t1, 223238 + 948: 5f 5f 6d 61 + 94c: 6c 6c + 94e: 6f 63 5f 73 jal t1, 1011508 + 952: 62 72 + 954: 6b 5f 62 61 + 958: 73 65 00 5f csrrsi a0, 1520, 0 + 95c: 6c 73 + 95e: 65 65 + 960: 6b 00 5f 5f vx_tex zero, t5, s5, a1, rne + 964: 6c 73 + 966: 68 69 + 968: 66 74 + 96a: 00 5f + 96c: 5f 6c 74 74 + 970: 66 32 + 972: 00 5f + 974: 5f 6e 65 74 + 978: 66 32 + 97a: 00 5f + 97c: 5f 73 73 70 + 980: 72 69 + 982: 6e 74 + 984: 5f 72 00 5f + 988: 5f 72 65 67 + 98c: 69 73 + 98e: 74 65 + 990: 72 5f + 992: 65 78 + 994: 69 74 + 996: 70 72 + 998: 6f 63 00 5f jal t1, 26096 + 99c: 70 6f + 99e: 63 6c 5f 6b bltu t5, s5, 1720 + 9a2: 65 72 + 9a4: 6e 65 + 9a6: 6c 5f + 9a8: 6f 63 6c 70 jal t1, 812806 + 9ac: 72 69 + 9ae: 6e 74 + 9b0: 66 5f + 9b2: 77 6f 72 6b + 9b6: 67 72 6f 75 + 9ba: 70 5f + 9bc: 66 61 + 9be: 73 74 00 5f csrrci s0, 1520, 0 + 9c2: 6c 64 + 9c4: 63 68 65 63 bltu a0, s6, 1584 + 9c8: 6b 00 5f 5f vx_tex zero, t5, s5, a1, rne + 9cc: 6d 75 + 9ce: 6c 74 + 9d0: 69 70 + 9d2: 6c 79 + 9d4: 00 73 + 9d6: 74 72 + 9d8: 6e 63 + 9da: 70 79 + 9dc: 00 5f + 9de: 5f 6d 61 6c + 9e2: 6c 6f + 9e4: 63 5f 63 75 bge t1, s6, 1886 + 9e8: 72 72 + 9ea: 65 6e + 9ec: 74 5f + 9ee: 6d 61 + 9f0: 6c 6c + 9f2: 69 6e + 9f4: 66 6f + 9f6: 00 5f + 9f8: 5f 64 32 62 + 9fc: 00 5f + 9fe: 5f 65 78 74 + a02: 65 6e + a04: 64 64 + a06: 66 74 + a08: 66 32 + a0a: 00 5f + a0c: 63 6c 6f 73 bltu t5, s6, 1848 + a10: 65 5f + a12: 72 00 + a14: 5f 5f 73 77 + a18: 73 65 74 75 csrrsi a0, 1879, 8 + a1c: 70 5f + a1e: 72 00 + a20: 5f 5f 64 69 + a24: 76 64 + a26: 66 33 + a28: 00 5f + a2a: 5f 73 66 70 + a2e: 00 5f + a30: 5f 63 6f 70 + a34: 79 62 + a36: 69 74 + a38: 73 00 5f 5f + a3c: 42 53 + a3e: 53 5f 45 4e + a42: 44 5f + a44: 5f 00 5f 5f + a48: 6d 61 + a4a: 6c 6c + a4c: 6f 63 5f 61 jal t1, 1011220 + a50: 76 5f + a52: 00 5f + a54: 5f 73 69 6e + a58: 69 74 + a5a: 5f 6c 6f 63 + a5e: 6b 5f 72 65 + a62: 6c 65 + a64: 61 73 + a66: 65 00 + a68: 5f 5f 6d 75 + a6c: 6c 64 + a6e: 66 33 + a70: 00 5f + a72: 5f 73 72 65 + a76: 61 64 + a78: 00 5f + a7a: 5f 6d 61 6c + a7e: 6c 6f + a80: 63 5f 6c 6f bge s8, s6, 1790 + a84: 63 6b 00 5f bltu zero, a6, 1526 + a88: 66 66 + a8a: 6c 75 + a8c: 73 68 5f 72 csrrsi a6, 1829, 30 + a90: 00 5f + a92: 63 61 6c 6c bltu s8, t1, 1730 + a96: 6f 63 5f 72 jal t1, 1011492 + a9a: 00 5f + a9c: 5f 62 73 73 + aa0: 5f 73 74 61 + aa4: 72 74 + aa6: 00 6d + aa8: 65 6d + aaa: 73 65 74 00 csrrsi a0, 7, 8 + aae: 5f 5f 6d 61 + ab2: 6c 6c + ab4: 6f 63 5f 6d jal t1, 1011412 + ab8: 61 78 + aba: 5f 74 6f 74 + abe: 61 6c + ac0: 5f 6d 65 6d + ac4: 00 5f + ac6: 5f 73 77 62 + aca: 75 66 + acc: 00 5f + ace: 5f 73 63 6c + ad2: 6f 73 65 00 jal t1, 356358 + ad6: 66 63 + ad8: 6c 6f + ada: 73 65 00 5f csrrsi a0, 1520, 0 + ade: 6d 61 + ae0: 6c 6c + ae2: 6f 63 5f 72 jal t1, 1011492 + ae6: 00 5f + ae8: 5f 61 73 63 + aec: 69 69 + aee: 5f 77 63 74 + af2: 6f 6d 62 00 jal s10, 155654 + af6: 5f 66 69 70 + afa: 72 69 + afc: 6e 74 + afe: 66 5f + b00: 72 00 + b02: 5f 69 6e 69 + b06: 74 5f + b08: 73 69 67 6e csrrsi s2, 1766, 14 + b0c: 61 6c + b0e: 00 5f + b10: 66 77 + b12: 61 6c + b14: 6b 00 5f 6d vx_tex zero, t5, s5, a3, rne + b18: 62 74 + b1a: 6f 77 63 5f jal a4, 226806 + b1e: 72 00 + b20: 5f 6d 61 6c + b24: 6c 6f + b26: 63 5f 74 72 bge s0, t2, 1854 + b2a: 69 6d + b2c: 5f 72 00 73 + b30: 74 72 + b32: 63 6d 70 00 bltu zero, t2, 26 + b36: 76 66 + b38: 69 70 + b3a: 72 69 + b3c: 6e 74 + b3e: 66 00 + b40: 5f 5f 6d 75 + b44: 6c 74 + b46: 66 33 + b48: 00 73 + b4a: 70 72 + b4c: 69 6e + b4e: 74 66 + b50: 00 5f + b52: 5f 63 6c 7a + b56: 5f 74 61 62 + b5a: 00 61 + b5c: 74 65 + b5e: 78 69 + b60: 74 00 + b62: 5f 77 72 69 + b66: 74 65 + b68: 5f 72 00 73 + b6c: 65 74 + b6e: 6c 6f + b70: 63 61 6c 65 bltu s8, s6, 1602 + b74: 00 5f + b76: 5f 73 66 6c + b7a: 75 73 + b7c: 68 5f + b7e: 72 00 + b80: 5f 5f 67 74 + b84: 74 66 + b86: 32 00 + b88: 5f 73 76 66 + b8c: 69 70 + b8e: 72 69 + b90: 6e 74 + b92: 66 5f + b94: 72 00 + b96: 5f 5f 61 73 + b9a: 63 69 69 5f bltu s2, s6, 1522 + b9e: 6d 62 + ba0: 74 6f + ba2: 77 63 00 5f + ba6: 5f 73 75 62 + baa: 74 66 + bac: 33 00 5f 5f + bb0: 75 6c + bb2: 70 00 + bb4: 5f 5f 66 70 + bb8: 5f 75 6e 6c + bbc: 6f 63 6b 5f jal t1, 746998 + bc0: 61 6c + bc2: 6c 00 + bc4: 6c 6f + bc6: 63 61 6c 65 bltu s8, s6, 1602 + bca: 63 6f 6e 76 bltu t3, t1, 1918 + bce: 00 5f + bd0: 5f 73 77 68 + bd4: 61 74 + bd6: 62 75 + bd8: 66 5f + bda: 72 00 + bdc: 5f 5f 44 41 + be0: 54 41 + be2: 5f 42 45 47 + be6: 49 4e + be8: 5f 5f 00 5f + bec: 77 72 69 74 + bf0: 65 00 + bf2: 5f 65 64 61 + bf6: 74 61 + bf8: 00 5f + bfa: 5f 66 70 75 + bfe: 74 77 + c00: 63 00 5f 5f beq t5, s5, 1504 + c04: 73 77 72 69 csrrci a4, 1687, 4 + c08: 74 65 + c0a: 00 5f + c0c: 5f 6d 61 6c + c10: 6c 6f + c12: 63 5f 74 72 bge s0, t2, 1854 + c16: 69 6d + c18: 5f 74 68 72 + c1c: 65 73 + c1e: 68 6f + c20: 6c 64 + c22: 00 5f + c24: 76 66 + c26: 69 70 + c28: 72 69 + c2a: 6e 74 + c2c: 66 5f + c2e: 72 00 + c30: 5f 66 77 61 + c34: 6c 6b + c36: 5f 72 65 65 + c3a: 6e 74 + c3c: 00 5f + c3e: 5f 6d 64 69 + c42: 66 66 + c44: 00 5f + c46: 6b 69 6c 6c + c4a: 00 5f + c4c: 5f 73 66 70 + c50: 5f 6c 6f 63 + c54: 6b 5f 72 65 + c58: 6c 65 + c5a: 61 73 + c5c: 65 00 + c5e: 5f 6c 64 74 + c62: 6f 61 5f 72 jal sp, 1011492 + c66: 00 76 + c68: 78 5f + c6a: 70 65 + c6c: 72 66 + c6e: 5f 64 75 6d + c72: 70 00 + c74: 5f 63 74 79 + c78: 70 65 + c7a: 5f 00 5f 72 + c7e: 65 61 + c80: 64 00 + c82: 5f 65 78 69 + c86: 74 00 + c88: 5f 5f 73 6d + c8c: 61 6b + c8e: 65 62 + c90: 75 66 + c92: 5f 72 00 73 + c96: 74 72 + c98: 6c 65 + c9a: 6e 00 + c9c: 5f 69 6e 69 + ca0: 74 5f + ca2: 73 69 67 6e csrrsi s2, 1766, 14 + ca6: 61 6c + ca8: 5f 72 00 5f + cac: 5f 61 73 73 + cb0: 65 72 + cb2: 74 00 + cb4: 5f 5f 73 70 + cb8: 72 69 + cba: 6e 74 + cbc: 5f 72 00 5f + cc0: 77 63 74 6f + cc4: 6d 62 + cc6: 5f 72 00 5f + cca: 5f 6c 6f 30 + cce: 62 69 + cd0: 74 73 + cd2: 00 76 + cd4: 78 5f + cd6: 73 70 61 77 csrci 1910, 2 + cda: 6e 5f + cdc: 6b 65 72 6e + ce0: 65 6c + ce2: 00 5f + ce4: 5f 73 69 67 + ce8: 74 72 + cea: 61 6d + cec: 70 00 + cee: 77 63 72 74 + cf2: 6f 6d 62 00 jal s10, 155654 + cf6: 66 72 + cf8: 65 78 + cfa: 70 00 + cfc: 76 78 + cfe: 5f 70 75 74 + d02: 63 68 61 72 bltu sp, t1, 1840 + d06: 00 5f + d08: 5f 67 6c 6f + d0c: 62 61 + d0e: 6c 5f + d10: 6c 6f + d12: 63 61 6c 65 bltu s8, s6, 1602 + d16: 00 5f + d18: 5f 74 72 75 + d1c: 6e 63 + d1e: 74 66 + d20: 64 66 + d22: 32 00 + d24: 72 61 + d26: 69 73 + d28: 65 00 + d2a: 5f 63 6c 6f + d2e: 73 65 00 5f csrrsi a0, 1520, 0 + d32: 5f 73 69 6e + d36: 69 74 + d38: 5f 6c 6f 63 + d3c: 6b 5f 61 63 + d40: 71 75 + d42: 69 72 + d44: 65 00 + d46: 5f 5f 6d 75 + d4a: 6c 74 + d4c: 61 64 + d4e: 64 00 + d50: 5f 42 66 72 + d54: 65 65 + d56: 00 + +Disassembly of section .shstrtab: + +00000000 .shstrtab: + 0: 00 2e + 2: 73 79 6d 74 csrrci s2, 1862, 26 + 6: 61 62 + 8: 00 2e + a: 73 74 72 74 csrrci s0, 1863, 4 + e: 61 62 + 10: 00 2e + 12: 73 68 73 74 csrrsi a6, 1863, 6 + 16: 72 74 + 18: 61 62 + 1a: 00 2e + 1c: 69 6e + 1e: 69 74 + 20: 00 2e + 22: 74 65 + 24: 78 74 + 26: 00 2e + 28: 72 6f + 2a: 64 61 + 2c: 74 61 + 2e: 00 2e + 30: 65 68 + 32: 5f 66 72 61 + 36: 6d 65 + 38: 00 2e + 3a: 69 6e + 3c: 69 74 + 3e: 5f 61 72 72 + 42: 61 79 + 44: 00 2e + 46: 64 61 + 48: 74 61 + 4a: 00 2e + 4c: 73 64 61 74 csrrsi s0, 1862, 2 + 50: 61 00 + 52: 2e 73 + 54: 62 73 + 56: 73 00 2e 62 + 5a: 73 73 00 2e csrrci t1, 736, 0 + 5e: 63 6f 6d 6d bltu s10, s6, 1758 + 62: 65 6e + 64: 74 00 + 66: 2e 72 + 68: 69 73 + 6a: 63 76 2e 61 bgeu t3, s2, 1548 + 6e: 74 74 + 70: 72 69 + 72: 62 75 + 74: 74 65 + 76: 73 00 2e 64 + 7a: 65 62 + 7c: 75 67 + 7e: 5f 61 72 61 + 82: 6e 67 + 84: 65 73 + 86: 00 2e + 88: 64 65 + 8a: 62 75 + 8c: 67 5f 69 6e + 90: 66 6f + 92: 00 2e + 94: 64 65 + 96: 62 75 + 98: 67 5f 61 62 + 9c: 62 72 + 9e: 65 76 + a0: 00 2e + a2: 64 65 + a4: 62 75 + a6: 67 5f 6c 69 + aa: 6e 65 + ac: 00 2e + ae: 64 65 + b0: 62 75 + b2: 67 5f 66 72 + b6: 61 6d + b8: 65 00 + ba: 2e 64 + bc: 65 62 + be: 75 67 + c0: 5f 73 74 72 + c4: 00 2e + c6: 64 65 + c8: 62 75 + ca: 67 5f 6c 6f + ce: 63 00 2e 64 beq t3, sp, 1600 + d2: 65 62 + d4: 75 67 + d6: 5f 72 61 6e + da: 67 65 73 00 diff --git a/tests/opencl/psort/Makefile b/tests/opencl/psort/Makefile index f1b48924..e7795db0 100644 --- a/tests/opencl/psort/Makefile +++ b/tests/opencl/psort/Makefile @@ -4,13 +4,13 @@ SYSROOT ?= $(RISCV_TOOLCHAIN_PATH)/riscv32-unknown-elf POCL_CC_PATH ?= /opt/pocl/compiler POCL_RT_PATH ?= /opt/pocl/runtime -OPTS ?= -n32 +OPTS ?= -f -n16 VORTEX_DRV_PATH ?= $(realpath ../../../driver) VORTEX_RT_PATH ?= $(realpath ../../../runtime) -K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -float-abi=hard -code-model=small" -K_CFLAGS += "-v -O3 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" +K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -mattr=+vortex -float-abi=hard -code-model=small" +K_CFLAGS += "-v -O3 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -Xclang -target-feature -Xclang +vortex -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" K_LDFLAGS += "-Wl,-Bstatic,-T$(VORTEX_RT_PATH)/linker/vx_link.ld -Wl,--gc-sections $(VORTEX_RT_PATH)/libvortexrt.a -lm" CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors @@ -35,13 +35,13 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ run-fpga: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-simx: $(PROJECT) kernel.pocl LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/opencl/psort/kernel.cl b/tests/opencl/psort/kernel.cl index bf5c7bb9..b8ebc5ba 100644 --- a/tests/opencl/psort/kernel.cl +++ b/tests/opencl/psort/kernel.cl @@ -1,4 +1,19 @@ -__kernel void psort (__global const float *in, __global float *out) +__kernel void psorti (__global const int *in, __global int *out) +{ + int gid = get_global_id(0); + int n = get_global_size(0); + + int ref = in[gid]; + + int pos = 0; + for (int i = 0; i < n; ++i) { + int cur = in[i]; + pos += (cur < ref) || ((cur == ref) && (i < gid)); + } + out[pos] = ref; +} + +__kernel void psortf (__global const float *in, __global float *out) { int gid = get_global_id(0); int n = get_global_size(0); @@ -8,7 +23,13 @@ __kernel void psort (__global const float *in, __global float *out) int pos = 0; for (int i = 0; i < n; ++i) { float cur = in[i]; - pos += (cur < ref) || (cur == ref && i < gid); + pos += (cur < ref) || ((cur == ref) && (i < gid)); + /*int cl = (cur < ref); + int ce = (cur == ref); + int ls = (i < gid); + int x = ce && ls; + int y = cl || x; + pos += y;*/ } out[pos] = ref; } \ No newline at end of file diff --git a/tests/opencl/psort/kernel.pocl b/tests/opencl/psort/kernel.pocl index 47a502e7..3e6d9b95 100644 Binary files a/tests/opencl/psort/kernel.pocl and b/tests/opencl/psort/kernel.pocl differ diff --git a/tests/opencl/psort/main.cc b/tests/opencl/psort/main.cc index ecd39c04..26a42807 100644 --- a/tests/opencl/psort/main.cc +++ b/tests/opencl/psort/main.cc @@ -7,7 +7,8 @@ #include #include -#define KERNEL_NAME "psort" +#define KERNEL0_NAME "psorti" +#define KERNEL1_NAME "psortf" #define CL_CHECK(_expr) \ do { \ @@ -52,14 +53,6 @@ static int read_kernel_file(const char* filename, uint8_t** data, size_t* size) return 0; } -static bool almost_equal(float a, float b, int ulp = 4) { - union fi_t { int i; float f; }; - fi_t fa, fb; - fa.f = a; - fb.f = b; - return std::abs(fa.i - fb.i) <= ulp; -} - cl_device_id device_id = NULL; cl_context context = NULL; cl_command_queue commandQueue = NULL; @@ -67,8 +60,8 @@ cl_program program = NULL; cl_kernel kernel = NULL; cl_mem a_memobj = NULL; cl_mem c_memobj = NULL; -float *h_a = NULL; -float *h_c = NULL; +int *h_a = NULL; +int *h_c = NULL; uint8_t *kernel_bin = NULL; static void cleanup() { @@ -86,15 +79,19 @@ static void cleanup() { } int size = 64; +bool float_enable = false; static void show_usage() { - printf("Usage: [-n size] [-h: help]\n"); + printf("Usage: [-f] [-n size] [-h: help]\n"); } static void parse_args(int argc, char **argv) { int c; - while ((c = getopt(argc, argv, "n:h?")) != -1) { + while ((c = getopt(argc, argv, "fn:h?")) != -1) { switch (c) { + case 'f': + float_enable = 1; + break; case 'n': size = atoi(optarg); break; @@ -132,7 +129,7 @@ int main (int argc, char **argv) { context = CL_CHECK2(clCreateContext(NULL, 1, &device_id, NULL, NULL, &_err)); printf("Allocate device buffers\n"); - size_t nbytes = size * sizeof(float); + size_t nbytes = size * sizeof(int); a_memobj = CL_CHECK2(clCreateBuffer(context, CL_MEM_READ_ONLY, nbytes, NULL, &_err)); c_memobj = CL_CHECK2(clCreateBuffer(context, CL_MEM_WRITE_ONLY, nbytes, NULL, &_err)); @@ -148,21 +145,28 @@ int main (int argc, char **argv) { CL_CHECK(clBuildProgram(program, 1, &device_id, NULL, NULL, NULL)); // Create kernel - kernel = CL_CHECK2(clCreateKernel(program, KERNEL_NAME, &_err)); + kernel = CL_CHECK2(clCreateKernel(program, (float_enable ? KERNEL1_NAME : KERNEL0_NAME), &_err)); // Set kernel arguments CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), (void *)&a_memobj)); CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), (void *)&c_memobj)); // Allocate memories for input arrays and output arrays. - h_a = (float*)malloc(nbytes); - h_c = (float*)malloc(nbytes); + h_a = (int*)malloc(nbytes); + h_c = (int*)malloc(nbytes); // Initialize values for array members. for (int i = 0; i < size; ++i) { - h_a[i] = sinf(i)*sinf(i); h_c[i] = 0xdeadbeef; - printf("*** [%d]: h_a=%f\n", i, h_a[i]); + if (float_enable) { + float value = sinf(i)*sinf(i); + h_a[i] = *(int*)&value; + printf("*** [%d]: h_a=%f\n", i, value); + } else { + int value = size*sinf(i); + h_a[i] = value; + printf("*** [%d]: h_a=%d\n", i, value); + } } // Creating command queue @@ -185,17 +189,37 @@ int main (int argc, char **argv) { CL_CHECK(clEnqueueReadBuffer(commandQueue, c_memobj, CL_TRUE, 0, nbytes, h_c, 0, NULL, NULL)); printf("Verify result\n"); + for (int i = 0; i < size; ++i) { + int value = h_c[i]; + if (float_enable) { + printf("*** [%d]: h_a=%f\n", i, *(float*)&value); + } else { + printf("*** [%d]: h_a=%d\n", i, value); + } + } int errors = 0; for (int i = 0; i < size; ++i) { - float ref = h_a[i]; + int ref = h_a[i]; + float ref_f = *(float*)&ref; int pos = 0; for (int j = 0; j < size; ++j) { - float cur = h_a[j]; - pos += (cur < ref) || (cur == ref && j < i); + int cur = h_a[j]; + if (float_enable) { + float cur_f = *(float*)&cur; + pos += (cur_f < ref_f) || (cur_f == ref_f && j < i); + } else { + pos += (cur < ref) || (cur == ref && j < i); + } } - if (!almost_equal(h_c[pos], ref)) { - if (errors < 100) - printf("*** error: [%d] expected=%f, actual=%f\n", pos, ref, h_c[pos]); + int value = h_c[pos]; + if (value != ref) { + if (errors < 100) { + if (float_enable) { + printf("*** error: [%d] expected=%f, actual=%f\n", pos, ref_f, *(float*)&value); + } else { + printf("*** error: [%d] expected=%d, actual=%d\n", pos, ref, value); + } + } ++errors; } } diff --git a/tests/opencl/psort/psort.dump b/tests/opencl/psort/psort.dump deleted file mode 100644 index 615d983f..00000000 --- a/tests/opencl/psort/psort.dump +++ /dev/null @@ -1,1720 +0,0 @@ - -/tmp/pocl_vortex_kernel-cd-5f-e9-7a-18.elf: file format ELF32-riscv - - -Disassembly of section .init: - -80000000 _start: -80000000: 97 05 00 00 auipc a1, 0 -80000004: 93 85 85 3d addi a1, a1, 984 -80000008: 73 25 10 fc csrr a0, 4033 -8000000c: 6b 10 b5 00 -80000010: ef 00 80 3c jal 968 -80000014: 13 05 10 00 addi a0, zero, 1 -80000018: 6b 00 05 00 -8000001c: 17 15 00 00 auipc a0, 1 -80000020: 13 05 85 41 addi a0, a0, 1048 -80000024: 17 16 00 00 auipc a2, 1 -80000028: 13 06 06 49 addi a2, a2, 1168 -8000002c: 33 06 a6 40 sub a2, a2, a0 -80000030: 93 05 00 00 mv a1, zero -80000034: ef 00 90 2a jal 2728 -80000038: 17 05 00 00 auipc a0, 0 -8000003c: 13 05 85 47 addi a0, a0, 1144 -80000040: ef 00 50 25 jal 2644 -80000044: ef 00 00 3d jal 976 -80000048: ef 00 00 02 jal 32 -8000004c: 6f 00 d0 25 j 2652 - -Disassembly of section .text: - -80000050 register_fini: -80000050: 93 07 00 00 mv a5, zero -80000054: 63 88 07 00 beqz a5, 16 -80000058: 37 05 00 80 lui a0, 524288 -8000005c: 13 05 05 4b addi a0, a0, 1200 -80000060: 6f 00 50 23 j 2612 -80000064: 67 80 00 00 ret - -80000068 main: -80000068: 13 01 01 ff addi sp, sp, -16 -8000006c: 23 26 11 00 sw ra, 12(sp) -80000070: 37 05 00 80 lui a0, 524288 -80000074: 93 05 45 1b addi a1, a0, 436 -80000078: 37 05 ff 7f lui a0, 524272 -8000007c: 13 06 45 03 addi a2, a0, 52 -80000080: 37 05 ff 7f lui a0, 524272 -80000084: ef 00 00 5d jal 1488 -80000088: 13 05 00 00 mv a0, zero -8000008c: 83 20 c1 00 lw ra, 12(sp) -80000090: 13 01 01 01 addi sp, sp, 16 -80000094: 67 80 00 00 ret - -80000098 _pocl_kernel_psort: -80000098: 13 01 01 ff addi sp, sp, -16 -8000009c: 23 26 11 00 sw ra, 12(sp) -800000a0: 23 24 81 00 sw s0, 8(sp) -800000a4: 23 22 91 00 sw s1, 4(sp) -800000a8: 23 20 21 01 sw s2, 0(sp) -800000ac: 13 04 01 01 addi s0, sp, 16 -800000b0: 13 71 c1 ff andi sp, sp, -4 -800000b4: 13 08 00 00 mv a6, zero -800000b8: 83 2e 86 01 lw t4, 24(a2) -800000bc: 03 23 c6 01 lw t1, 28(a2) -800000c0: 03 27 c6 00 lw a4, 12(a2) -800000c4: 83 27 06 00 lw a5, 0(a2) -800000c8: 83 28 06 02 lw a7, 32(a2) -800000cc: 33 86 de 02 mul a2, t4, a3 -800000d0: 33 0e c7 00 add t3, a4, a2 -800000d4: b3 8f d7 03 mul t6, a5, t4 -800000d8: 13 16 2e 00 slli a2, t3, 2 -800000dc: b3 02 c5 00 add t0, a0, a2 -800000e0: 6f 00 c0 00 j 12 -800000e4: 13 08 18 00 addi a6, a6, 1 -800000e8: 63 78 18 0b bgeu a6, a7, 176 -800000ec: 63 50 f0 09 blez t6, 128 -800000f0: 93 03 00 00 mv t2, zero -800000f4: 6f 00 c0 00 j 12 -800000f8: 93 83 13 00 addi t2, t2, 1 -800000fc: e3 f4 63 fe bgeu t2, t1, -24 -80000100: 13 0f 00 00 mv t5, zero -80000104: 6f 00 80 01 j 24 -80000108: 13 96 27 00 slli a2, a5, 2 -8000010c: 33 86 c5 00 add a2, a1, a2 -80000110: 13 0f 1f 00 addi t5, t5, 1 -80000114: 27 20 06 00 fsw ft0, 0(a2) -80000118: e3 70 df ff bgeu t5, t4, -32 -8000011c: 33 09 ee 01 add s2, t3, t5 -80000120: 13 16 29 00 slli a2, s2, 2 -80000124: 33 06 c5 00 add a2, a0, a2 -80000128: 07 20 06 00 flw ft0, 0(a2) -8000012c: 13 07 00 00 mv a4, zero -80000130: 93 07 00 00 mv a5, zero -80000134: 13 06 05 00 mv a2, a0 -80000138: 6f 00 40 01 j 20 -8000013c: b3 87 97 00 add a5, a5, s1 -80000140: 13 07 17 00 addi a4, a4, 1 -80000144: 13 06 46 00 addi a2, a2, 4 -80000148: e3 80 ef fc beq t6, a4, -64 -8000014c: 87 20 06 00 flw ft1, 0(a2) -80000150: d3 96 00 a0 flt.s a3, ft1, ft0 -80000154: 93 04 10 00 addi s1, zero, 1 -80000158: e3 92 06 fe bnez a3, -28 -8000015c: d3 a6 00 a0 feq.s a3, ft1, ft0 -80000160: b3 24 27 01 slt s1, a4, s2 -80000164: b3 f4 d4 00 and s1, s1, a3 -80000168: 6f f0 5f fd j -44 -8000016c: 13 06 00 00 mv a2, zero -80000170: 93 06 00 00 mv a3, zero -80000174: 13 87 02 00 mv a4, t0 -80000178: 83 27 07 00 lw a5, 0(a4) -8000017c: 23 a0 f5 00 sw a5, 0(a1) -80000180: 93 86 16 00 addi a3, a3, 1 -80000184: 13 07 47 00 addi a4, a4, 4 -80000188: e3 e8 d6 ff bltu a3, t4, -16 -8000018c: 13 06 16 00 addi a2, a2, 1 -80000190: e3 60 66 fe bltu a2, t1, -32 -80000194: 6f f0 1f f5 j -176 -80000198: 13 01 04 ff addi sp, s0, -16 -8000019c: 03 29 01 00 lw s2, 0(sp) -800001a0: 83 24 41 00 lw s1, 4(sp) -800001a4: 03 24 81 00 lw s0, 8(sp) -800001a8: 83 20 c1 00 lw ra, 12(sp) -800001ac: 13 01 01 01 addi sp, sp, 16 -800001b0: 67 80 00 00 ret - -800001b4 _pocl_kernel_psort_workgroup: -800001b4: 13 01 01 ff addi sp, sp, -16 -800001b8: 23 26 81 00 sw s0, 12(sp) -800001bc: 23 24 91 00 sw s1, 8(sp) -800001c0: 83 26 05 00 lw a3, 0(a0) -800001c4: 03 25 45 00 lw a0, 4(a0) -800001c8: 13 08 00 00 mv a6, zero -800001cc: 83 af 06 00 lw t6, 0(a3) -800001d0: 83 2e 05 00 lw t4, 0(a0) -800001d4: 03 af 85 01 lw t5, 24(a1) -800001d8: 03 a3 c5 01 lw t1, 28(a1) -800001dc: 03 a5 c5 00 lw a0, 12(a1) -800001e0: 83 a6 05 00 lw a3, 0(a1) -800001e4: 83 a8 05 02 lw a7, 32(a1) -800001e8: b3 05 cf 02 mul a1, t5, a2 -800001ec: 33 0e b5 00 add t3, a0, a1 -800001f0: b3 85 e6 03 mul a1, a3, t5 -800001f4: 13 15 2e 00 slli a0, t3, 2 -800001f8: b3 82 af 00 add t0, t6, a0 -800001fc: 6f 00 c0 00 j 12 -80000200: 13 08 18 00 addi a6, a6, 1 -80000204: 63 78 18 0b bgeu a6, a7, 176 -80000208: 63 50 b0 08 blez a1, 128 -8000020c: 93 03 00 00 mv t2, zero -80000210: 6f 00 c0 00 j 12 -80000214: 93 83 13 00 addi t2, t2, 1 -80000218: e3 f4 63 fe bgeu t2, t1, -24 -8000021c: 13 05 00 00 mv a0, zero -80000220: 6f 00 80 01 j 24 -80000224: 13 16 27 00 slli a2, a4, 2 -80000228: 33 86 ce 00 add a2, t4, a2 -8000022c: 13 05 15 00 addi a0, a0, 1 -80000230: 27 20 06 00 fsw ft0, 0(a2) -80000234: e3 70 e5 ff bgeu a0, t5, -32 -80000238: 33 06 ae 00 add a2, t3, a0 -8000023c: 93 16 26 00 slli a3, a2, 2 -80000240: b3 86 df 00 add a3, t6, a3 -80000244: 07 a0 06 00 flw ft0, 0(a3) -80000248: 93 07 00 00 mv a5, zero -8000024c: 13 07 00 00 mv a4, zero -80000250: 93 86 0f 00 mv a3, t6 -80000254: 6f 00 40 01 j 20 -80000258: 33 07 87 00 add a4, a4, s0 -8000025c: 93 87 17 00 addi a5, a5, 1 -80000260: 93 86 46 00 addi a3, a3, 4 -80000264: e3 80 f5 fc beq a1, a5, -64 -80000268: 87 a0 06 00 flw ft1, 0(a3) -8000026c: d3 94 00 a0 flt.s s1, ft1, ft0 -80000270: 13 04 10 00 addi s0, zero, 1 -80000274: e3 92 04 fe bnez s1, -28 -80000278: 53 a4 00 a0 feq.s s0, ft1, ft0 -8000027c: b3 a4 c7 00 slt s1, a5, a2 -80000280: 33 f4 84 00 and s0, s1, s0 -80000284: 6f f0 5f fd j -44 -80000288: 13 05 00 00 mv a0, zero -8000028c: 13 06 00 00 mv a2, zero -80000290: 93 86 02 00 mv a3, t0 -80000294: 03 a7 06 00 lw a4, 0(a3) -80000298: 23 a0 ee 00 sw a4, 0(t4) -8000029c: 13 06 16 00 addi a2, a2, 1 -800002a0: 93 86 46 00 addi a3, a3, 4 -800002a4: e3 68 e6 ff bltu a2, t5, -16 -800002a8: 13 05 15 00 addi a0, a0, 1 -800002ac: e3 60 65 fe bltu a0, t1, -32 -800002b0: 6f f0 1f f5 j -176 -800002b4: 83 24 81 00 lw s1, 8(sp) -800002b8: 03 24 c1 00 lw s0, 12(sp) -800002bc: 13 01 01 01 addi sp, sp, 16 -800002c0: 67 80 00 00 ret - -800002c4 _pocl_kernel_psort_workgroup_fast: -800002c4: 13 01 01 ff addi sp, sp, -16 -800002c8: 23 26 81 00 sw s0, 12(sp) -800002cc: 23 24 91 00 sw s1, 8(sp) -800002d0: 13 08 00 00 mv a6, zero -800002d4: 83 2f 05 00 lw t6, 0(a0) -800002d8: 83 2e 45 00 lw t4, 4(a0) -800002dc: 03 af 85 01 lw t5, 24(a1) -800002e0: 03 a3 c5 01 lw t1, 28(a1) -800002e4: 03 a5 c5 00 lw a0, 12(a1) -800002e8: 83 a6 05 00 lw a3, 0(a1) -800002ec: 83 a8 05 02 lw a7, 32(a1) -800002f0: b3 05 cf 02 mul a1, t5, a2 -800002f4: 33 0e b5 00 add t3, a0, a1 -800002f8: b3 85 e6 03 mul a1, a3, t5 -800002fc: 13 15 2e 00 slli a0, t3, 2 -80000300: b3 82 af 00 add t0, t6, a0 -80000304: 6f 00 c0 00 j 12 -80000308: 13 08 18 00 addi a6, a6, 1 -8000030c: 63 78 18 0b bgeu a6, a7, 176 -80000310: 63 50 b0 08 blez a1, 128 -80000314: 93 03 00 00 mv t2, zero -80000318: 6f 00 c0 00 j 12 -8000031c: 93 83 13 00 addi t2, t2, 1 -80000320: e3 f4 63 fe bgeu t2, t1, -24 -80000324: 93 06 00 00 mv a3, zero -80000328: 6f 00 80 01 j 24 -8000032c: 13 15 25 00 slli a0, a0, 2 -80000330: 33 85 ae 00 add a0, t4, a0 -80000334: 93 86 16 00 addi a3, a3, 1 -80000338: 27 20 05 00 fsw ft0, 0(a0) -8000033c: e3 f0 e6 ff bgeu a3, t5, -32 -80000340: 33 06 de 00 add a2, t3, a3 -80000344: 13 15 26 00 slli a0, a2, 2 -80000348: 33 85 af 00 add a0, t6, a0 -8000034c: 07 20 05 00 flw ft0, 0(a0) -80000350: 93 07 00 00 mv a5, zero -80000354: 13 05 00 00 mv a0, zero -80000358: 13 87 0f 00 mv a4, t6 -8000035c: 6f 00 40 01 j 20 -80000360: 33 05 85 00 add a0, a0, s0 -80000364: 93 87 17 00 addi a5, a5, 1 -80000368: 13 07 47 00 addi a4, a4, 4 -8000036c: e3 80 f5 fc beq a1, a5, -64 -80000370: 87 20 07 00 flw ft1, 0(a4) -80000374: d3 94 00 a0 flt.s s1, ft1, ft0 -80000378: 13 04 10 00 addi s0, zero, 1 -8000037c: e3 92 04 fe bnez s1, -28 -80000380: 53 a4 00 a0 feq.s s0, ft1, ft0 -80000384: b3 a4 c7 00 slt s1, a5, a2 -80000388: 33 f4 84 00 and s0, s1, s0 -8000038c: 6f f0 5f fd j -44 -80000390: 13 05 00 00 mv a0, zero -80000394: 13 06 00 00 mv a2, zero -80000398: 93 86 02 00 mv a3, t0 -8000039c: 03 a7 06 00 lw a4, 0(a3) -800003a0: 23 a0 ee 00 sw a4, 0(t4) -800003a4: 13 06 16 00 addi a2, a2, 1 -800003a8: 93 86 46 00 addi a3, a3, 4 -800003ac: e3 68 e6 ff bltu a2, t5, -16 -800003b0: 13 05 15 00 addi a0, a0, 1 -800003b4: e3 60 65 fe bltu a0, t1, -32 -800003b8: 6f f0 1f f5 j -176 -800003bc: 83 24 81 00 lw s1, 8(sp) -800003c0: 03 24 c1 00 lw s0, 12(sp) -800003c4: 13 01 01 01 addi sp, sp, 16 -800003c8: 67 80 00 00 ret - -800003cc _exit: -800003cc: ef 00 40 4b jal 1204 -800003d0: 13 05 00 00 mv a0, zero -800003d4: 6b 00 05 00 - -800003d8 vx_set_sp: -800003d8: 73 25 00 fc csrr a0, 4032 -800003dc: 6b 00 05 00 -800003e0: 97 11 00 00 auipc gp, 1 -800003e4: 93 81 81 42 addi gp, gp, 1064 -800003e8: 17 01 00 7f auipc sp, 520192 -800003ec: 13 01 81 c1 addi sp, sp, -1000 -800003f0: 93 05 00 40 addi a1, zero, 1024 -800003f4: 73 26 10 cc csrr a2, 3265 -800003f8: b3 85 c5 02 mul a1, a1, a2 -800003fc: 33 01 b1 40 sub sp, sp, a1 -80000400: f3 26 30 cc csrr a3, 3267 -80000404: 63 86 06 00 beqz a3, 12 -80000408: 13 05 00 00 mv a0, zero -8000040c: 6b 00 05 00 - -80000410 RETURN: -80000410: 67 80 00 00 ret - -80000414 __libc_init_array: -80000414: 13 01 01 ff addi sp, sp, -16 -80000418: 23 24 81 00 sw s0, 8(sp) -8000041c: 23 20 21 01 sw s2, 0(sp) -80000420: 37 14 00 80 lui s0, 524289 -80000424: 37 19 00 80 lui s2, 524289 -80000428: 93 07 04 00 mv a5, s0 -8000042c: 13 09 09 00 mv s2, s2 -80000430: 33 09 f9 40 sub s2, s2, a5 -80000434: 23 26 11 00 sw ra, 12(sp) -80000438: 23 22 91 00 sw s1, 4(sp) -8000043c: 13 59 29 40 srai s2, s2, 2 -80000440: 63 00 09 02 beqz s2, 32 -80000444: 13 04 04 00 mv s0, s0 -80000448: 93 04 00 00 mv s1, zero -8000044c: 83 27 04 00 lw a5, 0(s0) -80000450: 93 84 14 00 addi s1, s1, 1 -80000454: 13 04 44 00 addi s0, s0, 4 -80000458: e7 80 07 00 jalr a5 -8000045c: e3 18 99 fe bne s2, s1, -16 -80000460: 37 14 00 80 lui s0, 524289 -80000464: 37 19 00 80 lui s2, 524289 -80000468: 93 07 04 00 mv a5, s0 -8000046c: 13 09 49 00 addi s2, s2, 4 -80000470: 33 09 f9 40 sub s2, s2, a5 -80000474: 13 59 29 40 srai s2, s2, 2 -80000478: 63 00 09 02 beqz s2, 32 -8000047c: 13 04 04 00 mv s0, s0 -80000480: 93 04 00 00 mv s1, zero -80000484: 83 27 04 00 lw a5, 0(s0) -80000488: 93 84 14 00 addi s1, s1, 1 -8000048c: 13 04 44 00 addi s0, s0, 4 -80000490: e7 80 07 00 jalr a5 -80000494: e3 18 99 fe bne s2, s1, -16 -80000498: 83 20 c1 00 lw ra, 12(sp) -8000049c: 03 24 81 00 lw s0, 8(sp) -800004a0: 83 24 41 00 lw s1, 4(sp) -800004a4: 03 29 01 00 lw s2, 0(sp) -800004a8: 13 01 01 01 addi sp, sp, 16 -800004ac: 67 80 00 00 ret - -800004b0 __libc_fini_array: -800004b0: 13 01 01 ff addi sp, sp, -16 -800004b4: 23 24 81 00 sw s0, 8(sp) -800004b8: b7 17 00 80 lui a5, 524289 -800004bc: 37 14 00 80 lui s0, 524289 -800004c0: 13 04 44 00 addi s0, s0, 4 -800004c4: 93 87 47 00 addi a5, a5, 4 -800004c8: b3 87 87 40 sub a5, a5, s0 -800004cc: 23 22 91 00 sw s1, 4(sp) -800004d0: 23 26 11 00 sw ra, 12(sp) -800004d4: 93 d4 27 40 srai s1, a5, 2 -800004d8: 63 80 04 02 beqz s1, 32 -800004dc: 93 87 c7 ff addi a5, a5, -4 -800004e0: 33 84 87 00 add s0, a5, s0 -800004e4: 83 27 04 00 lw a5, 0(s0) -800004e8: 93 84 f4 ff addi s1, s1, -1 -800004ec: 13 04 c4 ff addi s0, s0, -4 -800004f0: e7 80 07 00 jalr a5 -800004f4: e3 98 04 fe bnez s1, -16 -800004f8: 83 20 c1 00 lw ra, 12(sp) -800004fc: 03 24 81 00 lw s0, 8(sp) -80000500: 83 24 41 00 lw s1, 4(sp) -80000504: 13 01 01 01 addi sp, sp, 16 -80000508: 67 80 00 00 ret - -8000050c spawn_kernel_callback: -8000050c: 13 01 01 fe addi sp, sp, -32 -80000510: 23 2e 11 00 sw ra, 28(sp) -80000514: 23 2c 81 00 sw s0, 24(sp) -80000518: 23 2a 91 00 sw s1, 20(sp) -8000051c: 23 28 21 01 sw s2, 16(sp) -80000520: 23 26 31 01 sw s3, 12(sp) -80000524: 23 24 41 01 sw s4, 8(sp) -80000528: 23 22 51 01 sw s5, 4(sp) -8000052c: f3 27 00 fc csrr a5, 4032 -80000530: 6b 80 07 00 -80000534: f3 26 50 cc csrr a3, 3269 -80000538: 73 29 30 cc csrr s2, 3267 -8000053c: 73 27 00 cc csrr a4, 3264 -80000540: 73 26 00 fc csrr a2, 4032 -80000544: b7 17 00 80 lui a5, 524289 -80000548: 93 96 26 00 slli a3, a3, 2 -8000054c: 93 87 47 43 addi a5, a5, 1076 -80000550: b3 87 d7 00 add a5, a5, a3 -80000554: 03 a4 07 00 lw s0, 0(a5) -80000558: 83 24 44 01 lw s1, 20(s0) -8000055c: 83 26 04 01 lw a3, 16(s0) -80000560: b3 2a 99 00 slt s5, s2, s1 -80000564: 93 87 04 00 mv a5, s1 -80000568: b3 8a da 00 add s5, s5, a3 -8000056c: b3 84 26 03 mul s1, a3, s2 -80000570: 63 54 f9 00 bge s2, a5, 8 -80000574: 93 07 09 00 mv a5, s2 -80000578: b3 84 f4 00 add s1, s1, a5 -8000057c: 83 25 04 00 lw a1, 0(s0) -80000580: 83 26 c4 00 lw a3, 12(s0) -80000584: 83 a9 05 00 lw s3, 0(a1) -80000588: 03 aa 45 00 lw s4, 4(a1) -8000058c: b3 84 c4 02 mul s1, s1, a2 -80000590: b3 87 ea 02 mul a5, s5, a4 -80000594: b3 84 d4 00 add s1, s1, a3 -80000598: b3 84 f4 00 add s1, s1, a5 -8000059c: b3 8a 9a 00 add s5, s5, s1 -800005a0: 33 8a 49 03 mul s4, s3, s4 -800005a4: 63 c0 54 07 blt s1, s5, 96 -800005a8: 6f 00 00 08 j 128 -800005ac: 03 47 a4 01 lbu a4, 26(s0) -800005b0: 83 46 94 01 lbu a3, 25(s0) -800005b4: 33 d7 e4 40 sra a4, s1, a4 -800005b8: b3 07 47 03 mul a5, a4, s4 -800005bc: b3 87 f4 40 sub a5, s1, a5 -800005c0: 63 80 06 06 beqz a3, 96 -800005c4: 83 46 b4 01 lbu a3, 27(s0) -800005c8: b3 d6 d7 40 sra a3, a5, a3 -800005cc: b3 88 36 03 mul a7, a3, s3 -800005d0: 03 ae 45 01 lw t3, 20(a1) -800005d4: 03 a3 05 01 lw t1, 16(a1) -800005d8: 03 a6 c5 00 lw a2, 12(a1) -800005dc: 03 28 44 00 lw a6, 4(s0) -800005e0: 03 25 84 00 lw a0, 8(s0) -800005e4: 93 84 14 00 addi s1, s1, 1 -800005e8: 33 07 c7 01 add a4, a4, t3 -800005ec: b3 86 66 00 add a3, a3, t1 -800005f0: b3 87 17 41 sub a5, a5, a7 -800005f4: 33 86 c7 00 add a2, a5, a2 -800005f8: e7 00 08 00 jalr a6 -800005fc: 63 86 9a 02 beq s5, s1, 44 -80000600: 83 25 04 00 lw a1, 0(s0) -80000604: 83 47 84 01 lbu a5, 24(s0) -80000608: e3 92 07 fa bnez a5, -92 -8000060c: 33 c7 44 03 div a4, s1, s4 -80000610: 83 46 94 01 lbu a3, 25(s0) -80000614: b3 07 47 03 mul a5, a4, s4 -80000618: b3 87 f4 40 sub a5, s1, a5 -8000061c: e3 94 06 fa bnez a3, -88 -80000620: b3 c6 37 03 div a3, a5, s3 -80000624: 6f f0 9f fa j -88 -80000628: 13 39 19 00 seqz s2, s2 -8000062c: 6b 00 09 00 -80000630: 83 20 c1 01 lw ra, 28(sp) -80000634: 03 24 81 01 lw s0, 24(sp) -80000638: 83 24 41 01 lw s1, 20(sp) -8000063c: 03 29 01 01 lw s2, 16(sp) -80000640: 83 29 c1 00 lw s3, 12(sp) -80000644: 03 2a 81 00 lw s4, 8(sp) -80000648: 83 2a 41 00 lw s5, 4(sp) -8000064c: 13 01 01 02 addi sp, sp, 32 -80000650: 67 80 00 00 ret - -80000654 vx_spawn_kernel: -80000654: 13 01 01 fc addi sp, sp, -64 -80000658: 23 2e 11 02 sw ra, 60(sp) -8000065c: 23 2c 81 02 sw s0, 56(sp) -80000660: 23 2a 91 02 sw s1, 52(sp) -80000664: 23 28 21 03 sw s2, 48(sp) -80000668: 23 26 31 03 sw s3, 44(sp) -8000066c: f3 28 20 fc csrr a7, 4034 -80000670: 73 23 10 fc csrr t1, 4033 -80000674: 73 24 00 fc csrr s0, 4032 -80000678: f3 27 50 cc csrr a5, 3269 -8000067c: 13 07 f0 01 addi a4, zero, 31 -80000680: 63 46 f7 0e blt a4, a5, 236 -80000684: 03 2e 05 00 lw t3, 0(a0) -80000688: 83 26 45 00 lw a3, 4(a0) -8000068c: 03 28 85 00 lw a6, 8(a0) -80000690: b3 0e 83 02 mul t4, t1, s0 -80000694: 13 07 10 00 addi a4, zero, 1 -80000698: b3 06 de 02 mul a3, t3, a3 -8000069c: 33 88 06 03 mul a6, a3, a6 -800006a0: 63 d4 0e 01 bge t4, a6, 8 -800006a4: 33 47 d8 03 div a4, a6, t4 -800006a8: 63 c0 e8 0e blt a7, a4, 224 -800006ac: 63 d0 e7 0c bge a5, a4, 192 -800006b0: 93 88 f8 ff addi a7, a7, -1 -800006b4: b3 4e e8 02 div t4, a6, a4 -800006b8: 93 84 0e 00 mv s1, t4 -800006bc: 63 96 f8 00 bne a7, a5, 12 -800006c0: 33 67 e8 02 rem a4, a6, a4 -800006c4: b3 04 d7 01 add s1, a4, t4 -800006c8: 33 c9 84 02 div s2, s1, s0 -800006cc: b3 e4 84 02 rem s1, s1, s0 -800006d0: 63 42 69 0c blt s2, t1, 196 -800006d4: 93 02 10 00 addi t0, zero, 1 -800006d8: 33 48 69 02 div a6, s2, t1 -800006dc: 63 06 08 00 beqz a6, 12 -800006e0: 93 02 08 00 mv t0, a6 -800006e4: 33 68 69 02 rem a6, s2, t1 -800006e8: d3 f7 06 d0 fcvt.s.w fa5, a3 -800006ec: 93 8f f6 ff addi t6, a3, -1 -800006f0: 13 0f fe ff addi t5, t3, -1 -800006f4: b7 19 00 80 lui s3, 524289 -800006f8: b3 f6 df 00 and a3, t6, a3 -800006fc: 93 89 49 43 addi s3, s3, 1076 -80000700: 93 b6 16 00 seqz a3, a3 -80000704: 23 22 a1 00 sw a0, 4(sp) -80000708: 23 24 b1 00 sw a1, 8(sp) -8000070c: 23 26 c1 00 sw a2, 12(sp) -80000710: 23 2a 51 00 sw t0, 20(sp) -80000714: 23 2c 01 01 sw a6, 24(sp) -80000718: 23 0e d1 00 sb a3, 28(sp) -8000071c: 33 87 fe 02 mul a4, t4, a5 -80000720: d3 8e 07 e0 fmv.x.w t4, fa5 -80000724: d3 77 0e d0 fcvt.s.w fa5, t3 -80000728: 93 97 27 00 slli a5, a5, 2 -8000072c: 33 7e cf 01 and t3, t5, t3 -80000730: d3 88 07 e0 fmv.x.w a7, fa5 -80000734: 93 de 7e 41 srai t4, t4, 23 -80000738: 13 3e 1e 00 seqz t3, t3 -8000073c: 93 d8 78 41 srai a7, a7, 23 -80000740: 93 8e 1e f8 addi t4, t4, -127 -80000744: 93 88 18 f8 addi a7, a7, -127 -80000748: b3 87 f9 00 add a5, s3, a5 -8000074c: 23 28 e1 00 sw a4, 16(sp) -80000750: 13 07 41 00 addi a4, sp, 4 -80000754: a3 0e c1 01 sb t3, 29(sp) -80000758: 23 0f d1 01 sb t4, 30(sp) -8000075c: a3 0f 11 01 sb a7, 31(sp) -80000760: 23 a0 e7 00 sw a4, 0(a5) -80000764: 63 4e 20 03 bgtz s2, 60 -80000768: 63 9c 04 04 bnez s1, 88 -8000076c: 83 20 c1 03 lw ra, 60(sp) -80000770: 03 24 81 03 lw s0, 56(sp) -80000774: 83 24 41 03 lw s1, 52(sp) -80000778: 03 29 01 03 lw s2, 48(sp) -8000077c: 83 29 c1 02 lw s3, 44(sp) -80000780: 13 01 01 04 addi sp, sp, 64 -80000784: 67 80 00 00 ret -80000788: 13 87 08 00 mv a4, a7 -8000078c: e3 c2 e7 f2 blt a5, a4, -220 -80000790: 6f f0 df fd j -36 -80000794: 13 08 00 00 mv a6, zero -80000798: 93 02 10 00 addi t0, zero, 1 -8000079c: 6f f0 df f4 j -180 -800007a0: 13 07 09 00 mv a4, s2 -800007a4: 63 54 23 01 bge t1, s2, 8 -800007a8: 13 07 03 00 mv a4, t1 -800007ac: b7 07 00 80 lui a5, 524288 -800007b0: 93 87 c7 50 addi a5, a5, 1292 -800007b4: 6b 10 f7 00 -800007b8: ef f0 5f d5 jal -684 -800007bc: e3 88 04 fa beqz s1, -80 -800007c0: 33 04 89 02 mul s0, s2, s0 -800007c4: 23 28 81 00 sw s0, 16(sp) -800007c8: 6b 80 04 00 -800007cc: 73 27 50 cc csrr a4, 3269 -800007d0: f3 27 20 cc csrr a5, 3266 -800007d4: 13 17 27 00 slli a4, a4, 2 -800007d8: b3 89 e9 00 add s3, s3, a4 -800007dc: 03 a5 09 00 lw a0, 0(s3) -800007e0: 83 25 05 00 lw a1, 0(a0) -800007e4: 83 26 c5 00 lw a3, 12(a0) -800007e8: 03 47 85 01 lbu a4, 24(a0) -800007ec: 03 a8 05 00 lw a6, 0(a1) -800007f0: 03 a6 45 00 lw a2, 4(a1) -800007f4: b3 87 d7 00 add a5, a5, a3 -800007f8: 33 06 c8 02 mul a2, a6, a2 -800007fc: 63 0e 07 06 beqz a4, 124 -80000800: 03 47 a5 01 lbu a4, 26(a0) -80000804: 33 d7 e7 40 sra a4, a5, a4 -80000808: 83 46 95 01 lbu a3, 25(a0) -8000080c: 33 06 e6 02 mul a2, a2, a4 -80000810: b3 87 c7 40 sub a5, a5, a2 -80000814: 63 8e 06 04 beqz a3, 92 -80000818: 83 48 b5 01 lbu a7, 27(a0) -8000081c: b3 d8 17 41 sra a7, a5, a7 -80000820: 33 08 18 03 mul a6, a6, a7 -80000824: 03 ae 45 01 lw t3, 20(a1) -80000828: 83 a6 05 01 lw a3, 16(a1) -8000082c: 03 a6 c5 00 lw a2, 12(a1) -80000830: 03 23 45 00 lw t1, 4(a0) -80000834: 03 25 85 00 lw a0, 8(a0) -80000838: 33 07 c7 01 add a4, a4, t3 -8000083c: b3 86 d8 00 add a3, a7, a3 -80000840: b3 87 07 41 sub a5, a5, a6 -80000844: 33 86 c7 00 add a2, a5, a2 -80000848: e7 00 03 00 jalr t1 -8000084c: 93 07 10 00 addi a5, zero, 1 -80000850: 6b 80 07 00 -80000854: 83 20 c1 03 lw ra, 60(sp) -80000858: 03 24 81 03 lw s0, 56(sp) -8000085c: 83 24 41 03 lw s1, 52(sp) -80000860: 03 29 01 03 lw s2, 48(sp) -80000864: 83 29 c1 02 lw s3, 44(sp) -80000868: 13 01 01 04 addi sp, sp, 64 -8000086c: 67 80 00 00 ret -80000870: b3 c8 07 03 div a7, a5, a6 -80000874: 6f f0 df fa j -84 -80000878: 33 c7 c7 02 div a4, a5, a2 -8000087c: 6f f0 df f8 j -116 - -80000880 vx_perf_dump: -80000880: f3 27 50 cc csrr a5, 3269 -80000884: 37 07 ff 00 lui a4, 4080 -80000888: b3 87 e7 00 add a5, a5, a4 -8000088c: 93 97 87 00 slli a5, a5, 8 -80000890: 73 27 00 b0 csrr a4, mcycle -80000894: 23 a0 e7 00 sw a4, 0(a5) -80000898: 73 27 10 b0 csrr a4, 2817 -8000089c: 23 a2 e7 00 sw a4, 4(a5) -800008a0: 73 27 20 b0 csrr a4, minstret -800008a4: 23 a4 e7 00 sw a4, 8(a5) -800008a8: 73 27 30 b0 csrr a4, mhpmcounter3 -800008ac: 23 a6 e7 00 sw a4, 12(a5) -800008b0: 73 27 40 b0 csrr a4, mhpmcounter4 -800008b4: 23 a8 e7 00 sw a4, 16(a5) -800008b8: 73 27 50 b0 csrr a4, mhpmcounter5 -800008bc: 23 aa e7 00 sw a4, 20(a5) -800008c0: 73 27 60 b0 csrr a4, mhpmcounter6 -800008c4: 23 ac e7 00 sw a4, 24(a5) -800008c8: 73 27 70 b0 csrr a4, mhpmcounter7 -800008cc: 23 ae e7 00 sw a4, 28(a5) -800008d0: 73 27 80 b0 csrr a4, mhpmcounter8 -800008d4: 23 a0 e7 02 sw a4, 32(a5) -800008d8: 73 27 90 b0 csrr a4, mhpmcounter9 -800008dc: 23 a2 e7 02 sw a4, 36(a5) -800008e0: 73 27 a0 b0 csrr a4, mhpmcounter10 -800008e4: 23 a4 e7 02 sw a4, 40(a5) -800008e8: 73 27 b0 b0 csrr a4, mhpmcounter11 -800008ec: 23 a6 e7 02 sw a4, 44(a5) -800008f0: 73 27 c0 b0 csrr a4, mhpmcounter12 -800008f4: 23 a8 e7 02 sw a4, 48(a5) -800008f8: 73 27 d0 b0 csrr a4, mhpmcounter13 -800008fc: 23 aa e7 02 sw a4, 52(a5) -80000900: 73 27 e0 b0 csrr a4, mhpmcounter14 -80000904: 23 ac e7 02 sw a4, 56(a5) -80000908: 73 27 f0 b0 csrr a4, mhpmcounter15 -8000090c: 23 ae e7 02 sw a4, 60(a5) -80000910: 73 27 00 b1 csrr a4, mhpmcounter16 -80000914: 23 a0 e7 04 sw a4, 64(a5) -80000918: 73 27 10 b1 csrr a4, mhpmcounter17 -8000091c: 23 a2 e7 04 sw a4, 68(a5) -80000920: 73 27 20 b1 csrr a4, mhpmcounter18 -80000924: 23 a4 e7 04 sw a4, 72(a5) -80000928: 73 27 30 b1 csrr a4, mhpmcounter19 -8000092c: 23 a6 e7 04 sw a4, 76(a5) -80000930: 73 27 40 b1 csrr a4, mhpmcounter20 -80000934: 23 a8 e7 04 sw a4, 80(a5) -80000938: 73 27 50 b1 csrr a4, mhpmcounter21 -8000093c: 23 aa e7 04 sw a4, 84(a5) -80000940: 73 27 60 b1 csrr a4, mhpmcounter22 -80000944: 23 ac e7 04 sw a4, 88(a5) -80000948: 73 27 70 b1 csrr a4, mhpmcounter23 -8000094c: 23 ae e7 04 sw a4, 92(a5) -80000950: 73 27 80 b1 csrr a4, mhpmcounter24 -80000954: 23 a0 e7 06 sw a4, 96(a5) -80000958: 73 27 90 b1 csrr a4, mhpmcounter25 -8000095c: 23 a2 e7 06 sw a4, 100(a5) -80000960: 73 27 a0 b1 csrr a4, mhpmcounter26 -80000964: 23 a4 e7 06 sw a4, 104(a5) -80000968: 73 27 b0 b1 csrr a4, mhpmcounter27 -8000096c: 23 a6 e7 06 sw a4, 108(a5) -80000970: 73 27 c0 b1 csrr a4, mhpmcounter28 -80000974: 23 a8 e7 06 sw a4, 112(a5) -80000978: 73 27 d0 b1 csrr a4, mhpmcounter29 -8000097c: 23 aa e7 06 sw a4, 116(a5) -80000980: 73 27 e0 b1 csrr a4, mhpmcounter30 -80000984: 23 ac e7 06 sw a4, 120(a5) -80000988: 73 27 f0 b1 csrr a4, mhpmcounter31 -8000098c: 23 ae e7 06 sw a4, 124(a5) -80000990: 73 27 00 b8 csrr a4, mcycleh -80000994: 23 a0 e7 08 sw a4, 128(a5) -80000998: 73 27 10 b8 csrr a4, 2945 -8000099c: 23 a2 e7 08 sw a4, 132(a5) -800009a0: 73 27 20 b8 csrr a4, minstreth -800009a4: 23 a4 e7 08 sw a4, 136(a5) -800009a8: 73 27 30 b8 csrr a4, mhpmcounter3h -800009ac: 23 a6 e7 08 sw a4, 140(a5) -800009b0: 73 27 40 b8 csrr a4, mhpmcounter4h -800009b4: 23 a8 e7 08 sw a4, 144(a5) -800009b8: 73 27 50 b8 csrr a4, mhpmcounter5h -800009bc: 23 aa e7 08 sw a4, 148(a5) -800009c0: 73 27 60 b8 csrr a4, mhpmcounter6h -800009c4: 23 ac e7 08 sw a4, 152(a5) -800009c8: 73 27 70 b8 csrr a4, mhpmcounter7h -800009cc: 23 ae e7 08 sw a4, 156(a5) -800009d0: 73 27 80 b8 csrr a4, mhpmcounter8h -800009d4: 23 a0 e7 0a sw a4, 160(a5) -800009d8: 73 27 90 b8 csrr a4, mhpmcounter9h -800009dc: 23 a2 e7 0a sw a4, 164(a5) -800009e0: 73 27 a0 b8 csrr a4, mhpmcounter10h -800009e4: 23 a4 e7 0a sw a4, 168(a5) -800009e8: 73 27 b0 b8 csrr a4, mhpmcounter11h -800009ec: 23 a6 e7 0a sw a4, 172(a5) -800009f0: 73 27 c0 b8 csrr a4, mhpmcounter12h -800009f4: 23 a8 e7 0a sw a4, 176(a5) -800009f8: 73 27 d0 b8 csrr a4, mhpmcounter13h -800009fc: 23 aa e7 0a sw a4, 180(a5) -80000a00: 73 27 e0 b8 csrr a4, mhpmcounter14h -80000a04: 23 ac e7 0a sw a4, 184(a5) -80000a08: 73 27 f0 b8 csrr a4, mhpmcounter15h -80000a0c: 23 ae e7 0a sw a4, 188(a5) -80000a10: 73 27 00 b9 csrr a4, mhpmcounter16h -80000a14: 23 a0 e7 0c sw a4, 192(a5) -80000a18: 73 27 10 b9 csrr a4, mhpmcounter17h -80000a1c: 23 a2 e7 0c sw a4, 196(a5) -80000a20: 73 27 20 b9 csrr a4, mhpmcounter18h -80000a24: 23 a4 e7 0c sw a4, 200(a5) -80000a28: 73 27 30 b9 csrr a4, mhpmcounter19h -80000a2c: 23 a6 e7 0c sw a4, 204(a5) -80000a30: 73 27 40 b9 csrr a4, mhpmcounter20h -80000a34: 23 a8 e7 0c sw a4, 208(a5) -80000a38: 73 27 50 b9 csrr a4, mhpmcounter21h -80000a3c: 23 aa e7 0c sw a4, 212(a5) -80000a40: 73 27 60 b9 csrr a4, mhpmcounter22h -80000a44: 23 ac e7 0c sw a4, 216(a5) -80000a48: 73 27 70 b9 csrr a4, mhpmcounter23h -80000a4c: 23 ae e7 0c sw a4, 220(a5) -80000a50: 73 27 80 b9 csrr a4, mhpmcounter24h -80000a54: 23 a0 e7 0e sw a4, 224(a5) -80000a58: 73 27 90 b9 csrr a4, mhpmcounter25h -80000a5c: 23 a2 e7 0e sw a4, 228(a5) -80000a60: 73 27 a0 b9 csrr a4, mhpmcounter26h -80000a64: 23 a4 e7 0e sw a4, 232(a5) -80000a68: 73 27 b0 b9 csrr a4, mhpmcounter27h -80000a6c: 23 a6 e7 0e sw a4, 236(a5) -80000a70: 73 27 c0 b9 csrr a4, mhpmcounter28h -80000a74: 23 a8 e7 0e sw a4, 240(a5) -80000a78: 73 27 d0 b9 csrr a4, mhpmcounter29h -80000a7c: 23 aa e7 0e sw a4, 244(a5) -80000a80: 73 27 e0 b9 csrr a4, mhpmcounter30h -80000a84: 23 ac e7 0e sw a4, 248(a5) -80000a88: 73 27 f0 b9 csrr a4, mhpmcounter31h -80000a8c: 23 ae e7 0e sw a4, 252(a5) -80000a90: 67 80 00 00 ret - -80000a94 atexit: -80000a94: 93 05 05 00 mv a1, a0 -80000a98: 93 06 00 00 mv a3, zero -80000a9c: 13 06 00 00 mv a2, zero -80000aa0: 13 05 00 00 mv a0, zero -80000aa4: 6f 00 40 11 j 276 - -80000aa8 exit: -80000aa8: 13 01 01 ff addi sp, sp, -16 -80000aac: 93 05 00 00 mv a1, zero -80000ab0: 23 24 81 00 sw s0, 8(sp) -80000ab4: 23 26 11 00 sw ra, 12(sp) -80000ab8: 13 04 05 00 mv s0, a0 -80000abc: ef 00 80 19 jal 408 -80000ac0: b7 17 00 80 lui a5, 524289 -80000ac4: 03 a5 07 43 lw a0, 1072(a5) -80000ac8: 83 27 c5 03 lw a5, 60(a0) -80000acc: 63 84 07 00 beqz a5, 8 -80000ad0: e7 80 07 00 jalr a5 -80000ad4: 13 05 04 00 mv a0, s0 -80000ad8: ef f0 5f 8f jal -1804 - -80000adc memset: -80000adc: 13 03 f0 00 addi t1, zero, 15 -80000ae0: 13 07 05 00 mv a4, a0 -80000ae4: 63 7e c3 02 bgeu t1, a2, 60 -80000ae8: 93 77 f7 00 andi a5, a4, 15 -80000aec: 63 90 07 0a bnez a5, 160 -80000af0: 63 92 05 08 bnez a1, 132 -80000af4: 93 76 06 ff andi a3, a2, -16 -80000af8: 13 76 f6 00 andi a2, a2, 15 -80000afc: b3 86 e6 00 add a3, a3, a4 -80000b00: 23 20 b7 00 sw a1, 0(a4) -80000b04: 23 22 b7 00 sw a1, 4(a4) -80000b08: 23 24 b7 00 sw a1, 8(a4) -80000b0c: 23 26 b7 00 sw a1, 12(a4) -80000b10: 13 07 07 01 addi a4, a4, 16 -80000b14: e3 66 d7 fe bltu a4, a3, -20 -80000b18: 63 14 06 00 bnez a2, 8 -80000b1c: 67 80 00 00 ret -80000b20: b3 06 c3 40 sub a3, t1, a2 -80000b24: 93 96 26 00 slli a3, a3, 2 -80000b28: 97 02 00 00 auipc t0, 0 -80000b2c: b3 86 56 00 add a3, a3, t0 -80000b30: 67 80 c6 00 jr 12(a3) -80000b34: 23 07 b7 00 sb a1, 14(a4) -80000b38: a3 06 b7 00 sb a1, 13(a4) -80000b3c: 23 06 b7 00 sb a1, 12(a4) -80000b40: a3 05 b7 00 sb a1, 11(a4) -80000b44: 23 05 b7 00 sb a1, 10(a4) -80000b48: a3 04 b7 00 sb a1, 9(a4) -80000b4c: 23 04 b7 00 sb a1, 8(a4) -80000b50: a3 03 b7 00 sb a1, 7(a4) -80000b54: 23 03 b7 00 sb a1, 6(a4) -80000b58: a3 02 b7 00 sb a1, 5(a4) -80000b5c: 23 02 b7 00 sb a1, 4(a4) -80000b60: a3 01 b7 00 sb a1, 3(a4) -80000b64: 23 01 b7 00 sb a1, 2(a4) -80000b68: a3 00 b7 00 sb a1, 1(a4) -80000b6c: 23 00 b7 00 sb a1, 0(a4) -80000b70: 67 80 00 00 ret -80000b74: 93 f5 f5 0f andi a1, a1, 255 -80000b78: 93 96 85 00 slli a3, a1, 8 -80000b7c: b3 e5 d5 00 or a1, a1, a3 -80000b80: 93 96 05 01 slli a3, a1, 16 -80000b84: b3 e5 d5 00 or a1, a1, a3 -80000b88: 6f f0 df f6 j -148 -80000b8c: 93 96 27 00 slli a3, a5, 2 -80000b90: 97 02 00 00 auipc t0, 0 -80000b94: b3 86 56 00 add a3, a3, t0 -80000b98: 93 82 00 00 mv t0, ra -80000b9c: e7 80 06 fa jalr -96(a3) -80000ba0: 93 80 02 00 mv ra, t0 -80000ba4: 93 87 07 ff addi a5, a5, -16 -80000ba8: 33 07 f7 40 sub a4, a4, a5 -80000bac: 33 06 f6 00 add a2, a2, a5 -80000bb0: e3 78 c3 f6 bgeu t1, a2, -144 -80000bb4: 6f f0 df f3 j -196 - -80000bb8 __register_exitproc: -80000bb8: b7 17 00 80 lui a5, 524289 -80000bbc: 03 a7 07 43 lw a4, 1072(a5) -80000bc0: 83 27 87 14 lw a5, 328(a4) -80000bc4: 63 8c 07 04 beqz a5, 88 -80000bc8: 03 a7 47 00 lw a4, 4(a5) -80000bcc: 13 08 f0 01 addi a6, zero, 31 -80000bd0: 63 4e e8 06 blt a6, a4, 124 -80000bd4: 13 18 27 00 slli a6, a4, 2 -80000bd8: 63 06 05 02 beqz a0, 44 -80000bdc: 33 83 07 01 add t1, a5, a6 -80000be0: 23 24 c3 08 sw a2, 136(t1) -80000be4: 83 a8 87 18 lw a7, 392(a5) -80000be8: 13 06 10 00 addi a2, zero, 1 -80000bec: 33 16 e6 00 sll a2, a2, a4 -80000bf0: b3 e8 c8 00 or a7, a7, a2 -80000bf4: 23 a4 17 19 sw a7, 392(a5) -80000bf8: 23 24 d3 10 sw a3, 264(t1) -80000bfc: 93 06 20 00 addi a3, zero, 2 -80000c00: 63 04 d5 02 beq a0, a3, 40 -80000c04: 13 07 17 00 addi a4, a4, 1 -80000c08: 23 a2 e7 00 sw a4, 4(a5) -80000c0c: b3 87 07 01 add a5, a5, a6 -80000c10: 23 a4 b7 00 sw a1, 8(a5) -80000c14: 13 05 00 00 mv a0, zero -80000c18: 67 80 00 00 ret -80000c1c: 93 07 c7 14 addi a5, a4, 332 -80000c20: 23 24 f7 14 sw a5, 328(a4) -80000c24: 6f f0 5f fa j -92 -80000c28: 83 a6 c7 18 lw a3, 396(a5) -80000c2c: 13 07 17 00 addi a4, a4, 1 -80000c30: 23 a2 e7 00 sw a4, 4(a5) -80000c34: 33 e6 c6 00 or a2, a3, a2 -80000c38: 23 a6 c7 18 sw a2, 396(a5) -80000c3c: b3 87 07 01 add a5, a5, a6 -80000c40: 23 a4 b7 00 sw a1, 8(a5) -80000c44: 13 05 00 00 mv a0, zero -80000c48: 67 80 00 00 ret -80000c4c: 13 05 f0 ff addi a0, zero, -1 -80000c50: 67 80 00 00 ret - -80000c54 __call_exitprocs: -80000c54: 13 01 01 fd addi sp, sp, -48 -80000c58: b7 17 00 80 lui a5, 524289 -80000c5c: 23 2c 41 01 sw s4, 24(sp) -80000c60: 03 aa 07 43 lw s4, 1072(a5) -80000c64: 23 20 21 03 sw s2, 32(sp) -80000c68: 23 26 11 02 sw ra, 44(sp) -80000c6c: 03 29 8a 14 lw s2, 328(s4) -80000c70: 23 24 81 02 sw s0, 40(sp) -80000c74: 23 22 91 02 sw s1, 36(sp) -80000c78: 23 2e 31 01 sw s3, 28(sp) -80000c7c: 23 2a 51 01 sw s5, 20(sp) -80000c80: 23 28 61 01 sw s6, 16(sp) -80000c84: 23 26 71 01 sw s7, 12(sp) -80000c88: 23 24 81 01 sw s8, 8(sp) -80000c8c: 63 00 09 04 beqz s2, 64 -80000c90: 13 0b 05 00 mv s6, a0 -80000c94: 93 8b 05 00 mv s7, a1 -80000c98: 93 0a 10 00 addi s5, zero, 1 -80000c9c: 93 09 f0 ff addi s3, zero, -1 -80000ca0: 83 24 49 00 lw s1, 4(s2) -80000ca4: 13 84 f4 ff addi s0, s1, -1 -80000ca8: 63 42 04 02 bltz s0, 36 -80000cac: 93 94 24 00 slli s1, s1, 2 -80000cb0: b3 04 99 00 add s1, s2, s1 -80000cb4: 63 84 0b 04 beqz s7, 72 -80000cb8: 83 a7 44 10 lw a5, 260(s1) -80000cbc: 63 80 77 05 beq a5, s7, 64 -80000cc0: 13 04 f4 ff addi s0, s0, -1 -80000cc4: 93 84 c4 ff addi s1, s1, -4 -80000cc8: e3 16 34 ff bne s0, s3, -20 -80000ccc: 83 20 c1 02 lw ra, 44(sp) -80000cd0: 03 24 81 02 lw s0, 40(sp) -80000cd4: 83 24 41 02 lw s1, 36(sp) -80000cd8: 03 29 01 02 lw s2, 32(sp) -80000cdc: 83 29 c1 01 lw s3, 28(sp) -80000ce0: 03 2a 81 01 lw s4, 24(sp) -80000ce4: 83 2a 41 01 lw s5, 20(sp) -80000ce8: 03 2b 01 01 lw s6, 16(sp) -80000cec: 83 2b c1 00 lw s7, 12(sp) -80000cf0: 03 2c 81 00 lw s8, 8(sp) -80000cf4: 13 01 01 03 addi sp, sp, 48 -80000cf8: 67 80 00 00 ret -80000cfc: 83 27 49 00 lw a5, 4(s2) -80000d00: 83 a6 44 00 lw a3, 4(s1) -80000d04: 93 87 f7 ff addi a5, a5, -1 -80000d08: 63 8e 87 04 beq a5, s0, 92 -80000d0c: 23 a2 04 00 sw zero, 4(s1) -80000d10: e3 88 06 fa beqz a3, -80 -80000d14: 83 27 89 18 lw a5, 392(s2) -80000d18: 33 97 8a 00 sll a4, s5, s0 -80000d1c: 03 2c 49 00 lw s8, 4(s2) -80000d20: b3 77 f7 00 and a5, a4, a5 -80000d24: 63 92 07 02 bnez a5, 36 -80000d28: e7 80 06 00 jalr a3 -80000d2c: 03 27 49 00 lw a4, 4(s2) -80000d30: 83 27 8a 14 lw a5, 328(s4) -80000d34: 63 14 87 01 bne a4, s8, 8 -80000d38: e3 04 f9 f8 beq s2, a5, -120 -80000d3c: e3 88 07 f8 beqz a5, -112 -80000d40: 13 89 07 00 mv s2, a5 -80000d44: 6f f0 df f5 j -164 -80000d48: 83 27 c9 18 lw a5, 396(s2) -80000d4c: 83 a5 44 08 lw a1, 132(s1) -80000d50: 33 77 f7 00 and a4, a4, a5 -80000d54: 63 1c 07 00 bnez a4, 24 -80000d58: 13 05 0b 00 mv a0, s6 -80000d5c: e7 80 06 00 jalr a3 -80000d60: 6f f0 df fc j -52 -80000d64: 23 22 89 00 sw s0, 4(s2) -80000d68: 6f f0 9f fa j -88 -80000d6c: 13 85 05 00 mv a0, a1 -80000d70: e7 80 06 00 jalr a3 -80000d74: 6f f0 9f fb j -72 - -Disassembly of section .init_array: - -80001000 __preinit_array_start: -80001000: 50 00 -80001002: 00 80 - -Disassembly of section .data: - -80001008 impure_data: -80001008: 00 00 -8000100a: 00 00 -8000100c: f4 12 -8000100e: 00 80 -80001010: 5c 13 -80001012: 00 80 -80001014: c4 13 -80001016: 00 80 - ... -800010b0: 01 00 -800010b2: 00 00 -800010b4: 00 00 -800010b6: 00 00 -800010b8: 0e 33 -800010ba: cd ab -800010bc: 34 12 -800010be: 6d e6 -800010c0: ec de -800010c2: 05 00 -800010c4: 0b 00 00 00 - ... - -Disassembly of section .sdata: - -80001430 _global_impure_ptr: -80001430: 08 10 -80001432: 00 80 - -Disassembly of section .bss: - -80001434 g_wspawn_args: -... - -Disassembly of section .comment: - -00000000 .comment: - 0: 63 6c 61 6e bltu sp, t1, 1784 - 4: 67 20 76 65 - 8: 72 73 - a: 69 6f - c: 6e 20 - e: 31 30 - 10: 2e 30 - 12: 2e 31 - 14: 20 28 - 16: 68 74 - 18: 74 70 - 1a: 73 3a 2f 2f csrrc s4, 754, t5 - 1e: 67 69 74 68 - 22: 75 62 - 24: 2e 63 - 26: 6f 6d 2f 6c jal s10, 1009346 - 2a: 6c 76 - 2c: 6d 2f - 2e: 6c 6c - 30: 76 6d - 32: 2d 70 - 34: 72 6f - 36: 6a 65 - 38: 63 74 2e 67 bgeu t3, s2, 1640 - 3c: 69 74 - 3e: 20 65 - 40: 66 33 - 42: 32 63 - 44: 36 31 - 46: 31 61 - 48: 61 32 - 4a: 31 34 - 4c: 64 65 - 4e: 61 38 - 50: 35 35 - 52: 33 36 34 65 - 56: 66 64 - 58: 37 62 61 34 lui tp, 214550 - 5c: 35 31 - 5e: 65 63 - 60: 35 65 - 62: 63 33 66 37 - 66: 34 29 - 68: 00 47 - 6a: 43 43 3a 20 fmadd.s ft6, fs4, ft3, ft4, rmm - 6e: 28 47 - 70: 4e 55 - 72: 29 20 - 74: 39 2e - 76: 32 2e - 78: 30 00 - -Disassembly of section .riscv.attributes: - -00000000 .riscv.attributes: - 0: 41 25 - 2: 00 00 - 4: 00 72 - 6: 69 73 - 8: 63 76 00 01 bgeu zero, a6, 12 - c: 1b 00 00 00 - 10: 04 10 - 12: 05 72 - 14: 76 33 - 16: 32 69 - 18: 32 70 - 1a: 30 5f - 1c: 6d 32 - 1e: 70 30 - 20: 5f 66 32 70 - 24: 30 00 - -Disassembly of section .symtab: - -00000000 .symtab: - ... - 14: 00 00 - 16: 00 80 - 18: 00 00 - 1a: 00 00 - 1c: 03 00 01 00 lb zero, 0(sp) - 20: 00 00 - 22: 00 00 - 24: 50 00 - 26: 00 80 - 28: 00 00 - 2a: 00 00 - 2c: 03 00 02 00 lb zero, 0(tp) - 30: 00 00 - 32: 00 00 - 34: 00 10 - 36: 00 80 - 38: 00 00 - 3a: 00 00 - 3c: 03 00 03 00 lb zero, 0(t1) - 40: 00 00 - 42: 00 00 - 44: 08 10 - 46: 00 80 - 48: 00 00 - 4a: 00 00 - 4c: 03 00 04 00 lb zero, 0(s0) - 50: 00 00 - 52: 00 00 - 54: 30 14 - 56: 00 80 - 58: 00 00 - 5a: 00 00 - 5c: 03 00 05 00 lb zero, 0(a0) - 60: 00 00 - 62: 00 00 - 64: 34 14 - 66: 00 80 - 68: 00 00 - 6a: 00 00 - 6c: 03 00 06 00 lb zero, 0(a2) - ... - 7c: 03 00 07 00 lb zero, 0(a4) - ... - 8c: 03 00 08 00 lb zero, 0(a6) - 90: 01 00 - ... - 9a: 00 00 - 9c: 04 00 - 9e: f1 ff - a0: 0e 00 - a2: 00 00 - a4: 10 04 - a6: 00 80 - a8: 00 00 - aa: 00 00 - ac: 00 00 - ae: 02 00 - b0: 15 00 - ... - ba: 00 00 - bc: 04 00 - be: f1 ff - c0: 25 00 - c2: 00 00 - c4: 50 00 - c6: 00 80 - c8: 18 00 - ca: 00 00 - cc: 02 00 - ce: 02 00 - d0: 33 00 00 00 add zero, zero, zero - ... - dc: 04 00 - de: f1 ff - e0: 57 00 00 00 - ... - ec: 04 00 - ee: f1 ff - f0: 63 00 00 00 beqz zero, 0 - ... - fc: 04 00 - fe: f1 ff - 100: 71 00 - ... - 10a: 00 00 - 10c: 04 00 - 10e: f1 ff - 110: 7c 00 - 112: 00 00 - 114: 0c 05 - 116: 00 80 - 118: 48 01 - 11a: 00 00 - 11c: 02 00 - 11e: 02 00 - 120: 92 00 - ... - 12a: 00 00 - 12c: 04 00 - 12e: f1 ff - 130: 9e 00 - ... - 13a: 00 00 - 13c: 04 00 - 13e: f1 ff - 140: a0 00 - ... - 14a: 00 00 - 14c: 04 00 - 14e: f1 ff - 150: 9c 00 - ... - 15a: 00 00 - 15c: 04 00 - 15e: f1 ff - 160: a7 00 00 00 - ... - 16c: 04 00 - 16e: f1 ff - 170: b0 00 - 172: 00 00 - 174: 08 10 - 176: 00 80 - 178: 28 04 - 17a: 00 00 - 17c: 01 00 - 17e: 04 00 - ... - 18c: 04 00 - 18e: f1 ff - 190: bc 00 - 192: 00 00 - 194: 04 10 - 196: 00 80 - 198: 00 00 - 19a: 00 00 - 19c: 00 00 - 19e: 03 00 cd 00 lb zero, 12(s10) - 1a2: 00 00 - 1a4: 04 10 - 1a6: 00 80 - 1a8: 00 00 - 1aa: 00 00 - 1ac: 00 00 - 1ae: 03 00 e0 00 lb zero, 14(zero) - 1b2: 00 00 - 1b4: 04 10 - 1b6: 00 80 - 1b8: 00 00 - 1ba: 00 00 - 1bc: 00 00 - 1be: 03 00 f1 00 lb zero, 15(sp) - 1c2: 00 00 - 1c4: 00 10 - 1c6: 00 80 - 1c8: 00 00 - 1ca: 00 00 - 1cc: 00 00 - 1ce: 03 00 05 01 lb zero, 16(a0) - 1d2: 00 00 - 1d4: 00 10 - 1d6: 00 80 - 1d8: 00 00 - 1da: 00 00 - 1dc: 00 00 - 1de: 03 00 18 01 lb zero, 17(a6) - 1e2: 00 00 - 1e4: 00 10 - 1e6: 00 80 - 1e8: 00 00 - 1ea: 00 00 - 1ec: 00 00 - 1ee: 03 00 2e 01 lb zero, 18(t3) - ... - 1fa: 00 00 - 1fc: 10 00 - 1fe: f1 ff - 200: 3c 01 - 202: 00 00 - 204: b4 01 - 206: 00 80 - 208: 10 01 - 20a: 00 00 - 20c: 12 00 - 20e: 02 00 - 210: 59 01 - 212: 00 00 - 214: 00 04 - 216: 00 00 - 218: 00 00 - 21a: 00 00 - 21c: 10 00 - 21e: f1 ff - 220: 66 01 - 222: 00 00 - 224: 34 14 - 226: 00 80 - 228: 80 00 - 22a: 00 00 - 22c: 11 00 - 22e: 06 00 - 230: 74 01 - 232: 00 00 - 234: 30 14 - 236: 00 80 - 238: 00 00 - 23a: 00 00 - 23c: 10 00 - 23e: 05 00 - 240: 84 01 - 242: 00 00 - 244: 08 18 - 246: 00 80 - 248: 00 00 - 24a: 00 00 - 24c: 10 00 - 24e: f1 ff - 250: 95 01 - 252: 00 00 - 254: 30 14 - 256: 00 80 - 258: 04 00 - 25a: 00 00 - 25c: 11 00 - 25e: 05 00 - 260: a8 01 - 262: 00 00 - 264: 14 04 - 266: 00 80 - 268: 9c 00 - 26a: 00 00 - 26c: 12 00 - 26e: 02 00 - 270: ba 01 - 272: 00 00 - 274: b0 04 - 276: 00 80 - 278: 5c 00 - 27a: 00 00 - 27c: 12 00 - 27e: 02 00 - 280: cc 01 - 282: 00 00 - 284: 00 00 - 286: 00 ff - 288: 00 00 - 28a: 00 00 - 28c: 10 00 - 28e: f1 ff - 290: d8 01 - 292: 00 00 - 294: d8 03 - 296: 00 80 - 298: 00 00 - 29a: 00 00 - 29c: 12 00 - 29e: 02 00 - 2a0: e2 01 - 2a2: 00 00 - 2a4: 54 0c - 2a6: 00 80 - 2a8: 24 01 - 2aa: 00 00 - 2ac: 12 00 - 2ae: 02 00 - 2b0: 4d 02 - 2b2: 00 00 - 2b4: 00 00 - 2b6: 00 80 - 2b8: 50 00 - 2ba: 00 00 - 2bc: 12 00 - 2be: 01 00 - 2c0: f3 01 00 00 - 2c4: b8 0b - 2c6: 00 80 - 2c8: 9c 00 - 2ca: 00 00 - 2cc: 12 00 - 2ce: 02 00 - 2d0: 07 02 00 00 - 2d4: 98 00 - 2d6: 00 80 - 2d8: 1c 01 - 2da: 00 00 - 2dc: 12 00 - 2de: 02 00 - 2e0: 1a 02 - 2e2: 00 00 - 2e4: b4 14 - 2e6: 00 80 - 2e8: 00 00 - 2ea: 00 00 - 2ec: 10 00 - 2ee: 06 00 - 2f0: 26 02 - 2f2: 00 00 - 2f4: c4 02 - 2f6: 00 80 - 2f8: 08 01 - 2fa: 00 00 - 2fc: 12 00 - 2fe: 02 00 - 300: 48 02 - 302: 00 00 - 304: 34 14 - 306: 00 80 - 308: 00 00 - 30a: 00 00 - 30c: 10 00 - 30e: 06 00 - 310: 54 02 - 312: 00 00 - 314: dc 0a - 316: 00 80 - 318: dc 00 - 31a: 00 00 - 31c: 12 00 - 31e: 02 00 - 320: 5b 02 00 00 - 324: 68 00 - 326: 00 80 - 328: 30 00 - 32a: 00 00 - 32c: 12 00 - 32e: 02 00 - 330: 60 02 - 332: 00 00 - 334: 94 0a - 336: 00 80 - 338: 14 00 - 33a: 00 00 - 33c: 12 00 - 33e: 02 00 - 340: 67 02 00 00 jalr tp, zero - 344: 08 10 - 346: 00 80 - 348: 00 00 - 34a: 00 00 - 34c: 10 00 - 34e: 04 00 - 350: 76 02 - 352: 00 00 - 354: 34 14 - 356: 00 80 - 358: 00 00 - 35a: 00 00 - 35c: 10 00 - 35e: 05 00 - 360: c8 00 - 362: 00 00 - 364: b4 14 - 366: 00 80 - 368: 00 00 - 36a: 00 00 - 36c: 10 00 - 36e: 06 00 - 370: 8b 02 00 00 - 374: a8 0a - 376: 00 80 - 378: 34 00 - 37a: 00 00 - 37c: 12 00 - 37e: 02 00 - 380: 7d 02 - 382: 00 00 - 384: 80 08 - 386: 00 80 - 388: 14 02 - 38a: 00 00 - 38c: 12 00 - 38e: 02 00 - 390: 8a 02 - 392: 00 00 - 394: cc 03 - 396: 00 80 - 398: 00 00 - 39a: 00 00 - 39c: 12 00 - 39e: 02 00 - 3a0: 90 02 - 3a2: 00 00 - 3a4: 54 06 - 3a6: 00 80 - 3a8: 2c 02 - 3aa: 00 00 - 3ac: 12 00 - 3ae: 02 00 - -Disassembly of section .strtab: - -00000000 .strtab: - 0: 00 76 - 2: 78 5f - 4: 73 74 61 72 csrrci s0, 1830, 2 - 8: 74 2e - a: 53 2e 6f 00 fadd.s ft8, ft10, ft6, rdn - e: 52 45 - 10: 54 55 - 12: 52 4e - 14: 00 5f - 16: 5f 63 61 6c - 1a: 6c 5f - 1c: 61 74 - 1e: 65 78 - 20: 69 74 - 22: 2e 63 - 24: 00 72 - 26: 65 67 - 28: 69 73 - 2a: 74 65 - 2c: 72 5f - 2e: 66 69 - 30: 6e 69 - 32: 00 70 - 34: 6f 63 6c 5f jal t1, 812534 - 38: 76 6f - 3a: 72 74 - 3c: 65 78 - 3e: 5f 6b 65 72 - 42: 6e 65 - 44: 6c 2d - 46: 65 64 - 48: 2d 66 - 4a: 31 2d - 4c: 35 32 - 4e: 2d 64 - 50: 36 2d - 52: 64 33 - 54: 2e 63 - 56: 00 70 - 58: 61 72 - 5a: 61 6c - 5c: 6c 65 - 5e: 6c 5f - 60: 62 63 - 62: 00 76 - 64: 78 5f - 66: 73 79 73 63 csrrci s2, 1591, 6 - 6a: 61 6c - 6c: 6c 73 - 6e: 2e 63 - 70: 00 76 - 72: 78 5f - 74: 73 70 61 77 csrci 1910, 2 - 78: 6e 2e - 7a: 63 00 73 70 beq t1, t2, 1792 - 7e: 61 77 - 80: 6e 5f - 82: 6b 65 72 6e - 86: 65 6c - 88: 5f 63 61 6c - 8c: 6c 62 - 8e: 61 63 - 90: 6b 00 76 78 - 94: 5f 70 65 72 - 98: 66 2e - 9a: 63 00 5f 5f beq t5, s5, 1504 - 9e: 61 74 - a0: 65 78 - a2: 69 74 - a4: 2e 63 - a6: 00 69 - a8: 6d 70 - aa: 75 72 - ac: 65 2e - ae: 63 00 69 6d beq s2, s6, 1728 - b2: 70 75 - b4: 72 65 - b6: 5f 64 61 74 - ba: 61 00 - bc: 5f 5f 66 69 - c0: 6e 69 - c2: 5f 61 72 72 - c6: 61 79 - c8: 5f 65 6e 64 - cc: 00 5f - ce: 5f 66 69 6e - d2: 69 5f - d4: 61 72 - d6: 72 61 - d8: 79 5f - da: 73 74 61 72 csrrci s0, 1830, 2 - de: 74 00 - e0: 5f 5f 69 6e - e4: 69 74 - e6: 5f 61 72 72 - ea: 61 79 - ec: 5f 65 6e 64 - f0: 00 5f - f2: 5f 70 72 65 - f6: 69 6e - f8: 69 74 - fa: 5f 61 72 72 - fe: 61 79 - 100: 5f 65 6e 64 - 104: 00 5f - 106: 5f 69 6e 69 - 10a: 74 5f - 10c: 61 72 - 10e: 72 61 - 110: 79 5f - 112: 73 74 61 72 csrrci s0, 1830, 2 - 116: 74 00 - 118: 5f 5f 70 72 - 11c: 65 69 - 11e: 6e 69 - 120: 74 5f - 122: 61 72 - 124: 72 61 - 126: 79 5f - 128: 73 74 61 72 csrrci s0, 1830, 2 - 12c: 74 00 - 12e: 5f 5f 73 74 - 132: 61 63 - 134: 6b 5f 75 73 - 138: 61 67 - 13a: 65 00 - 13c: 5f 70 6f 63 - 140: 6c 5f - 142: 6b 65 72 6e - 146: 65 6c - 148: 5f 70 73 6f - 14c: 72 74 - 14e: 5f 77 6f 72 - 152: 6b 67 72 6f - 156: 75 70 - 158: 00 5f - 15a: 5f 73 74 61 - 15e: 63 6b 5f 73 bltu t5, s5, 1846 - 162: 69 7a - 164: 65 00 - 166: 67 5f 77 73 - 16a: 70 61 - 16c: 77 6e 5f 61 - 170: 72 67 - 172: 73 00 5f 5f - 176: 53 44 41 54 - 17a: 41 5f - 17c: 42 45 - 17e: 47 49 4e 5f - 182: 5f 00 5f 5f - 186: 67 6c 6f 62 - 18a: 61 6c - 18c: 5f 70 6f 69 - 190: 6e 74 - 192: 65 72 - 194: 00 5f - 196: 67 6c 6f 62 - 19a: 61 6c - 19c: 5f 69 6d 70 - 1a0: 75 72 - 1a2: 65 5f - 1a4: 70 74 - 1a6: 72 00 - 1a8: 5f 5f 6c 69 - 1ac: 62 63 - 1ae: 5f 69 6e 69 - 1b2: 74 5f - 1b4: 61 72 - 1b6: 72 61 - 1b8: 79 00 - 1ba: 5f 5f 6c 69 - 1be: 62 63 - 1c0: 5f 66 69 6e - 1c4: 69 5f - 1c6: 61 72 - 1c8: 72 61 - 1ca: 79 00 - 1cc: 5f 5f 73 74 - 1d0: 61 63 - 1d2: 6b 5f 74 6f - 1d6: 70 00 - 1d8: 76 78 - 1da: 5f 73 65 74 - 1de: 5f 73 70 00 - 1e2: 5f 5f 63 61 - 1e6: 6c 6c - 1e8: 5f 65 78 69 - 1ec: 74 70 - 1ee: 72 6f - 1f0: 63 73 00 5f bgeu zero, a6, 1510 - 1f4: 5f 72 65 67 - 1f8: 69 73 - 1fa: 74 65 - 1fc: 72 5f - 1fe: 65 78 - 200: 69 74 - 202: 70 72 - 204: 6f 63 00 5f jal t1, 26096 - 208: 70 6f - 20a: 63 6c 5f 6b bltu t5, s5, 1720 - 20e: 65 72 - 210: 6e 65 - 212: 6c 5f - 214: 70 73 - 216: 6f 72 74 00 jal tp, 292870 - 21a: 5f 5f 42 53 - 21e: 53 5f 45 4e - 222: 44 5f - 224: 5f 00 5f 70 - 228: 6f 63 6c 5f jal t1, 812534 - 22c: 6b 65 72 6e - 230: 65 6c - 232: 5f 70 73 6f - 236: 72 74 - 238: 5f 77 6f 72 - 23c: 6b 67 72 6f - 240: 75 70 - 242: 5f 66 61 73 - 246: 74 00 - 248: 5f 5f 62 73 - 24c: 73 5f 73 74 csrrwi t5, 1863, 6 - 250: 61 72 - 252: 74 00 - 254: 6d 65 - 256: 6d 73 - 258: 65 74 - 25a: 00 6d - 25c: 61 69 - 25e: 6e 00 - 260: 61 74 - 262: 65 78 - 264: 69 74 - 266: 00 5f - 268: 5f 44 41 54 - 26c: 41 5f - 26e: 42 45 - 270: 47 49 4e 5f - 274: 5f 00 5f 65 - 278: 64 61 - 27a: 74 61 - 27c: 00 76 - 27e: 78 5f - 280: 70 65 - 282: 72 66 - 284: 5f 64 75 6d - 288: 70 00 - 28a: 5f 65 78 69 - 28e: 74 00 - 290: 76 78 - 292: 5f 73 70 61 - 296: 77 6e 5f 6b - 29a: 65 72 - 29c: 6e 65 - 29e: 6c 00 - -Disassembly of section .shstrtab: - -00000000 .shstrtab: - 0: 00 2e - 2: 73 79 6d 74 csrrci s2, 1862, 26 - 6: 61 62 - 8: 00 2e - a: 73 74 72 74 csrrci s0, 1863, 4 - e: 61 62 - 10: 00 2e - 12: 73 68 73 74 csrrsi a6, 1863, 6 - 16: 72 74 - 18: 61 62 - 1a: 00 2e - 1c: 69 6e - 1e: 69 74 - 20: 00 2e - 22: 74 65 - 24: 78 74 - 26: 00 2e - 28: 69 6e - 2a: 69 74 - 2c: 5f 61 72 72 - 30: 61 79 - 32: 00 2e - 34: 64 61 - 36: 74 61 - 38: 00 2e - 3a: 73 64 61 74 csrrsi s0, 1862, 2 - 3e: 61 00 - 40: 2e 62 - 42: 73 73 00 2e csrrci t1, 736, 0 - 46: 63 6f 6d 6d bltu s10, s6, 1758 - 4a: 65 6e - 4c: 74 00 - 4e: 2e 72 - 50: 69 73 - 52: 63 76 2e 61 bgeu t3, s2, 1548 - 56: 74 74 - 58: 72 69 - 5a: 62 75 - 5c: 74 65 - 5e: 73 - 5f: 00 diff --git a/tests/opencl/psort/psortf.dump b/tests/opencl/psort/psortf.dump new file mode 100644 index 00000000..686304ee --- /dev/null +++ b/tests/opencl/psort/psortf.dump @@ -0,0 +1,1785 @@ + +/tmp/pocl_vortex_kernel-06-d7-80-34-5c.elf: file format ELF32-riscv + + +Disassembly of section .init: + +80000000 _start: +80000000: 97 05 00 00 auipc a1, 0 +80000004: 93 85 c5 3f addi a1, a1, 1020 +80000008: 73 25 10 fc csrr a0, 4033 +8000000c: 6b 10 b5 00 vx_wspawn a0, a1 +80000010: ef 00 c0 3e jal 1004 +80000014: 13 05 10 00 addi a0, zero, 1 +80000018: 6b 00 05 00 vx_tmc a0 +8000001c: 17 15 00 00 auipc a0, 1 +80000020: 13 05 85 41 addi a0, a0, 1048 +80000024: 17 16 00 00 auipc a2, 1 +80000028: 13 06 06 49 addi a2, a2, 1168 +8000002c: 33 06 a6 40 sub a2, a2, a0 +80000030: 93 05 00 00 mv a1, zero +80000034: ef 00 10 31 jal 2832 +80000038: 17 05 00 00 auipc a0, 0 +8000003c: 13 05 45 49 addi a0, a0, 1172 +80000040: ef 00 d0 2b jal 2748 +80000044: ef 00 c0 3e jal 1004 +80000048: ef 00 00 02 jal 32 +8000004c: 6f 00 50 2c j 2756 + +Disassembly of section .text: + +80000050 register_fini: +80000050: 93 07 00 00 mv a5, zero +80000054: 63 88 07 00 beqz a5, 16 +80000058: 37 05 00 80 lui a0, 524288 +8000005c: 13 05 c5 4c addi a0, a0, 1228 +80000060: 6f 00 d0 29 j 2716 +80000064: 67 80 00 00 ret + +80000068 main: +80000068: 13 01 01 ff addi sp, sp, -16 +8000006c: 23 26 11 00 sw ra, 12(sp) +80000070: 37 05 00 80 lui a0, 524288 +80000074: 93 05 45 1b addi a1, a0, 436 +80000078: 37 05 ff 7f lui a0, 524272 +8000007c: 13 06 45 03 addi a2, a0, 52 +80000080: 37 05 ff 7f lui a0, 524272 +80000084: ef 00 00 6b jal 1712 +80000088: 13 05 00 00 mv a0, zero +8000008c: 83 20 c1 00 lw ra, 12(sp) +80000090: 13 01 01 01 addi sp, sp, 16 +80000094: 67 80 00 00 ret + +80000098 _pocl_kernel_psortf: +80000098: 13 01 01 ff addi sp, sp, -16 +8000009c: 23 26 11 00 sw ra, 12(sp) +800000a0: 23 24 81 00 sw s0, 8(sp) +800000a4: 23 22 91 00 sw s1, 4(sp) +800000a8: 23 20 21 01 sw s2, 0(sp) +800000ac: 13 04 01 01 addi s0, sp, 16 +800000b0: 13 71 c1 ff andi sp, sp, -4 +800000b4: 13 08 00 00 mv a6, zero +800000b8: 83 2e 86 01 lw t4, 24(a2) +800000bc: 03 23 c6 01 lw t1, 28(a2) +800000c0: 03 27 c6 00 lw a4, 12(a2) +800000c4: 83 27 06 00 lw a5, 0(a2) +800000c8: 83 28 06 02 lw a7, 32(a2) +800000cc: 33 86 de 02 mul a2, t4, a3 +800000d0: 33 0e c7 00 add t3, a4, a2 +800000d4: b3 8f d7 03 mul t6, a5, t4 +800000d8: 13 16 2e 00 slli a2, t3, 2 +800000dc: b3 02 c5 00 add t0, a0, a2 +800000e0: 6f 00 c0 00 j 12 +800000e4: 13 08 18 00 addi a6, a6, 1 +800000e8: 63 78 18 0b bgeu a6, a7, 176 +800000ec: 63 50 f0 09 blez t6, 128 +800000f0: 93 03 00 00 mv t2, zero +800000f4: 6f 00 c0 00 j 12 +800000f8: 93 83 13 00 addi t2, t2, 1 +800000fc: e3 f4 63 fe bgeu t2, t1, -24 +80000100: 13 0f 00 00 mv t5, zero +80000104: 6f 00 80 01 j 24 +80000108: 13 96 27 00 slli a2, a5, 2 +8000010c: 33 86 c5 00 add a2, a1, a2 +80000110: 13 0f 1f 00 addi t5, t5, 1 +80000114: 27 20 06 00 fsw ft0, 0(a2) +80000118: e3 70 df ff bgeu t5, t4, -32 +8000011c: 33 09 ee 01 add s2, t3, t5 +80000120: 13 16 29 00 slli a2, s2, 2 +80000124: 33 06 c5 00 add a2, a0, a2 +80000128: 07 20 06 00 flw ft0, 0(a2) +8000012c: 13 07 00 00 mv a4, zero +80000130: 93 07 00 00 mv a5, zero +80000134: 13 06 05 00 mv a2, a0 +80000138: 6f 00 40 01 j 20 +8000013c: b3 87 97 00 add a5, a5, s1 +80000140: 13 07 17 00 addi a4, a4, 1 +80000144: 13 06 46 00 addi a2, a2, 4 +80000148: e3 80 ef fc beq t6, a4, -64 +8000014c: 87 20 06 00 flw ft1, 0(a2) +80000150: d3 96 00 a0 flt.s a3, ft1, ft0 +80000154: 93 04 10 00 addi s1, zero, 1 +80000158: e3 92 06 fe bnez a3, -28 +8000015c: b3 26 27 01 slt a3, a4, s2 +80000160: d3 a4 00 a0 feq.s s1, ft1, ft0 +80000164: b3 f4 96 00 and s1, a3, s1 +80000168: 6f f0 5f fd j -44 +8000016c: 13 06 00 00 mv a2, zero +80000170: 93 06 00 00 mv a3, zero +80000174: 13 87 02 00 mv a4, t0 +80000178: 83 27 07 00 lw a5, 0(a4) +8000017c: 23 a0 f5 00 sw a5, 0(a1) +80000180: 93 86 16 00 addi a3, a3, 1 +80000184: 13 07 47 00 addi a4, a4, 4 +80000188: e3 e8 d6 ff bltu a3, t4, -16 +8000018c: 13 06 16 00 addi a2, a2, 1 +80000190: e3 60 66 fe bltu a2, t1, -32 +80000194: 6f f0 1f f5 j -176 +80000198: 13 01 04 ff addi sp, s0, -16 +8000019c: 03 29 01 00 lw s2, 0(sp) +800001a0: 83 24 41 00 lw s1, 4(sp) +800001a4: 03 24 81 00 lw s0, 8(sp) +800001a8: 83 20 c1 00 lw ra, 12(sp) +800001ac: 13 01 01 01 addi sp, sp, 16 +800001b0: 67 80 00 00 ret + +800001b4 _pocl_kernel_psortf_workgroup: +800001b4: 13 01 01 ff addi sp, sp, -16 +800001b8: 23 26 81 00 sw s0, 12(sp) +800001bc: 23 24 91 00 sw s1, 8(sp) +800001c0: 23 22 21 01 sw s2, 4(sp) +800001c4: 83 26 05 00 lw a3, 0(a0) +800001c8: 03 25 45 00 lw a0, 4(a0) +800001cc: 13 08 00 00 mv a6, zero +800001d0: 83 af 06 00 lw t6, 0(a3) +800001d4: 83 2e 05 00 lw t4, 0(a0) +800001d8: 03 af 85 01 lw t5, 24(a1) +800001dc: 03 a3 c5 01 lw t1, 28(a1) +800001e0: 03 a5 c5 00 lw a0, 12(a1) +800001e4: 83 a6 05 00 lw a3, 0(a1) +800001e8: 83 a8 05 02 lw a7, 32(a1) +800001ec: b3 05 cf 02 mul a1, t5, a2 +800001f0: 33 0e b5 00 add t3, a0, a1 +800001f4: b3 85 e6 03 mul a1, a3, t5 +800001f8: 13 15 2e 00 slli a0, t3, 2 +800001fc: b3 82 af 00 add t0, t6, a0 +80000200: 6f 00 c0 00 j 12 +80000204: 13 08 18 00 addi a6, a6, 1 +80000208: 63 70 18 0d bgeu a6, a7, 192 +8000020c: 63 58 b0 08 blez a1, 144 +80000210: 93 03 00 00 mv t2, zero +80000214: 6f 00 c0 00 j 12 +80000218: 93 83 13 00 addi t2, t2, 1 +8000021c: e3 f4 63 fe bgeu t2, t1, -24 +80000220: 13 05 00 00 mv a0, zero +80000224: 6f 00 c0 01 j 28 +80000228: 6b 00 09 00 vx_tmc s2 +8000022c: 13 16 27 00 slli a2, a4, 2 +80000230: 33 86 ce 00 add a2, t4, a2 +80000234: 13 05 15 00 addi a0, a0, 1 +80000238: 27 20 06 00 fsw ft0, 0(a2) +8000023c: e3 7e e5 fd bgeu a0, t5, -36 +80000240: 33 06 ae 00 add a2, t3, a0 +80000244: 93 16 26 00 slli a3, a2, 2 +80000248: b3 86 df 00 add a3, t6, a3 +8000024c: 07 a0 06 00 flw ft0, 0(a3) +80000250: 93 07 00 00 mv a5, zero +80000254: 13 07 00 00 mv a4, zero +80000258: 73 29 40 cc csrr s2, tmask +8000025c: 13 84 0f 00 mv s0, t6 +80000260: 6f 00 80 01 j 24 +80000264: 6b 30 00 00 vx_join +80000268: 33 07 97 00 add a4, a4, s1 +8000026c: 93 87 17 00 addi a5, a5, 1 +80000270: 13 04 44 00 addi s0, s0, 4 +80000274: e3 8a f5 fa beq a1, a5, -76 +80000278: 87 20 04 00 flw ft1, 0(s0) +8000027c: d3 96 00 a0 flt.s a3, ft1, ft0 +80000280: 6b a0 06 00 vx_split a3 +80000284: 93 04 10 00 addi s1, zero, 1 +80000288: e3 9e 06 fc bnez a3, -36 +8000028c: b3 a6 c7 00 slt a3, a5, a2 +80000290: d3 a4 00 a0 feq.s s1, ft1, ft0 +80000294: b3 f4 96 00 and s1, a3, s1 +80000298: 6f f0 df fc j -52 +8000029c: 13 05 00 00 mv a0, zero +800002a0: 13 06 00 00 mv a2, zero +800002a4: 93 86 02 00 mv a3, t0 +800002a8: 03 a7 06 00 lw a4, 0(a3) +800002ac: 23 a0 ee 00 sw a4, 0(t4) +800002b0: 13 06 16 00 addi a2, a2, 1 +800002b4: 93 86 46 00 addi a3, a3, 4 +800002b8: e3 68 e6 ff bltu a2, t5, -16 +800002bc: 13 05 15 00 addi a0, a0, 1 +800002c0: e3 60 65 fe bltu a0, t1, -32 +800002c4: 6f f0 1f f4 j -192 +800002c8: 03 29 41 00 lw s2, 4(sp) +800002cc: 83 24 81 00 lw s1, 8(sp) +800002d0: 03 24 c1 00 lw s0, 12(sp) +800002d4: 13 01 01 01 addi sp, sp, 16 +800002d8: 67 80 00 00 ret + +800002dc _pocl_kernel_psortf_workgroup_fast: +800002dc: 13 01 01 ff addi sp, sp, -16 +800002e0: 23 26 81 00 sw s0, 12(sp) +800002e4: 23 24 91 00 sw s1, 8(sp) +800002e8: 13 08 00 00 mv a6, zero +800002ec: 83 2f 05 00 lw t6, 0(a0) +800002f0: 83 2e 45 00 lw t4, 4(a0) +800002f4: 03 af 85 01 lw t5, 24(a1) +800002f8: 03 a3 c5 01 lw t1, 28(a1) +800002fc: 03 a5 c5 00 lw a0, 12(a1) +80000300: 83 a6 05 00 lw a3, 0(a1) +80000304: 83 a8 05 02 lw a7, 32(a1) +80000308: b3 05 cf 02 mul a1, t5, a2 +8000030c: 33 0e b5 00 add t3, a0, a1 +80000310: b3 85 e6 03 mul a1, a3, t5 +80000314: 13 15 2e 00 slli a0, t3, 2 +80000318: b3 82 af 00 add t0, t6, a0 +8000031c: 6f 00 c0 00 j 12 +80000320: 13 08 18 00 addi a6, a6, 1 +80000324: 63 78 18 0b bgeu a6, a7, 176 +80000328: 63 50 b0 08 blez a1, 128 +8000032c: 93 03 00 00 mv t2, zero +80000330: 6f 00 c0 00 j 12 +80000334: 93 83 13 00 addi t2, t2, 1 +80000338: e3 f4 63 fe bgeu t2, t1, -24 +8000033c: 93 06 00 00 mv a3, zero +80000340: 6f 00 80 01 j 24 +80000344: 13 15 25 00 slli a0, a0, 2 +80000348: 33 85 ae 00 add a0, t4, a0 +8000034c: 93 86 16 00 addi a3, a3, 1 +80000350: 27 20 05 00 fsw ft0, 0(a0) +80000354: e3 f0 e6 ff bgeu a3, t5, -32 +80000358: 33 06 de 00 add a2, t3, a3 +8000035c: 13 15 26 00 slli a0, a2, 2 +80000360: 33 85 af 00 add a0, t6, a0 +80000364: 07 20 05 00 flw ft0, 0(a0) +80000368: 93 07 00 00 mv a5, zero +8000036c: 13 05 00 00 mv a0, zero +80000370: 13 87 0f 00 mv a4, t6 +80000374: 6f 00 40 01 j 20 +80000378: 33 05 85 00 add a0, a0, s0 +8000037c: 93 87 17 00 addi a5, a5, 1 +80000380: 13 07 47 00 addi a4, a4, 4 +80000384: e3 80 f5 fc beq a1, a5, -64 +80000388: 87 20 07 00 flw ft1, 0(a4) +8000038c: d3 94 00 a0 flt.s s1, ft1, ft0 +80000390: 13 04 10 00 addi s0, zero, 1 +80000394: e3 92 04 fe bnez s1, -28 +80000398: 33 a4 c7 00 slt s0, a5, a2 +8000039c: d3 a4 00 a0 feq.s s1, ft1, ft0 +800003a0: 33 74 94 00 and s0, s0, s1 +800003a4: 6f f0 5f fd j -44 +800003a8: 13 05 00 00 mv a0, zero +800003ac: 13 06 00 00 mv a2, zero +800003b0: 93 86 02 00 mv a3, t0 +800003b4: 03 a7 06 00 lw a4, 0(a3) +800003b8: 23 a0 ee 00 sw a4, 0(t4) +800003bc: 13 06 16 00 addi a2, a2, 1 +800003c0: 93 86 46 00 addi a3, a3, 4 +800003c4: e3 68 e6 ff bltu a2, t5, -16 +800003c8: 13 05 15 00 addi a0, a0, 1 +800003cc: e3 60 65 fe bltu a0, t1, -32 +800003d0: 6f f0 1f f5 j -176 +800003d4: 83 24 81 00 lw s1, 8(sp) +800003d8: 03 24 c1 00 lw s0, 12(sp) +800003dc: 13 01 01 01 addi sp, sp, 16 +800003e0: 67 80 00 00 ret + +800003e4 _exit: +800003e4: 63 06 05 00 beqz a0, 12 +800003e8: 93 01 05 00 mv gp, a0 +800003ec: 73 00 00 00 ecall + +800003f0 label_exit_next: +800003f0: ef 00 80 4f jal 1272 +800003f4: 13 05 00 00 mv a0, zero +800003f8: 6b 00 05 00 vx_tmc a0 + +800003fc vx_set_sp: +800003fc: 13 05 f0 ff addi a0, zero, -1 +80000400: 6b 00 05 00 vx_tmc a0 +80000404: 97 11 00 00 auipc gp, 1 +80000408: 93 81 41 40 addi gp, gp, 1028 +8000040c: 37 01 00 ff lui sp, 1044480 +80000410: 73 26 10 cc csrr a2, 3265 +80000414: 93 15 a6 00 slli a1, a2, 10 +80000418: 33 01 b1 40 sub sp, sp, a1 +8000041c: f3 26 30 cc csrr a3, 3267 +80000420: 63 86 06 00 beqz a3, 12 +80000424: 13 05 00 00 mv a0, zero +80000428: 6b 00 05 00 vx_tmc a0 + +8000042c RETURN: +8000042c: 67 80 00 00 ret + +80000430 __libc_init_array: +80000430: 13 01 01 ff addi sp, sp, -16 +80000434: 23 24 81 00 sw s0, 8(sp) +80000438: 23 20 21 01 sw s2, 0(sp) +8000043c: 37 14 00 80 lui s0, 524289 +80000440: 37 19 00 80 lui s2, 524289 +80000444: 93 07 04 00 mv a5, s0 +80000448: 13 09 09 00 mv s2, s2 +8000044c: 33 09 f9 40 sub s2, s2, a5 +80000450: 23 26 11 00 sw ra, 12(sp) +80000454: 23 22 91 00 sw s1, 4(sp) +80000458: 13 59 29 40 srai s2, s2, 2 +8000045c: 63 00 09 02 beqz s2, 32 +80000460: 13 04 04 00 mv s0, s0 +80000464: 93 04 00 00 mv s1, zero +80000468: 83 27 04 00 lw a5, 0(s0) +8000046c: 93 84 14 00 addi s1, s1, 1 +80000470: 13 04 44 00 addi s0, s0, 4 +80000474: e7 80 07 00 jalr a5 +80000478: e3 18 99 fe bne s2, s1, -16 +8000047c: 37 14 00 80 lui s0, 524289 +80000480: 37 19 00 80 lui s2, 524289 +80000484: 93 07 04 00 mv a5, s0 +80000488: 13 09 49 00 addi s2, s2, 4 +8000048c: 33 09 f9 40 sub s2, s2, a5 +80000490: 13 59 29 40 srai s2, s2, 2 +80000494: 63 00 09 02 beqz s2, 32 +80000498: 13 04 04 00 mv s0, s0 +8000049c: 93 04 00 00 mv s1, zero +800004a0: 83 27 04 00 lw a5, 0(s0) +800004a4: 93 84 14 00 addi s1, s1, 1 +800004a8: 13 04 44 00 addi s0, s0, 4 +800004ac: e7 80 07 00 jalr a5 +800004b0: e3 18 99 fe bne s2, s1, -16 +800004b4: 83 20 c1 00 lw ra, 12(sp) +800004b8: 03 24 81 00 lw s0, 8(sp) +800004bc: 83 24 41 00 lw s1, 4(sp) +800004c0: 03 29 01 00 lw s2, 0(sp) +800004c4: 13 01 01 01 addi sp, sp, 16 +800004c8: 67 80 00 00 ret + +800004cc __libc_fini_array: +800004cc: 13 01 01 ff addi sp, sp, -16 +800004d0: 23 24 81 00 sw s0, 8(sp) +800004d4: b7 17 00 80 lui a5, 524289 +800004d8: 37 14 00 80 lui s0, 524289 +800004dc: 13 04 44 00 addi s0, s0, 4 +800004e0: 93 87 47 00 addi a5, a5, 4 +800004e4: b3 87 87 40 sub a5, a5, s0 +800004e8: 23 22 91 00 sw s1, 4(sp) +800004ec: 23 26 11 00 sw ra, 12(sp) +800004f0: 93 d4 27 40 srai s1, a5, 2 +800004f4: 63 80 04 02 beqz s1, 32 +800004f8: 93 87 c7 ff addi a5, a5, -4 +800004fc: 33 84 87 00 add s0, a5, s0 +80000500: 83 27 04 00 lw a5, 0(s0) +80000504: 93 84 f4 ff addi s1, s1, -1 +80000508: 13 04 c4 ff addi s0, s0, -4 +8000050c: e7 80 07 00 jalr a5 +80000510: e3 98 04 fe bnez s1, -16 +80000514: 83 20 c1 00 lw ra, 12(sp) +80000518: 03 24 81 00 lw s0, 8(sp) +8000051c: 83 24 41 00 lw s1, 4(sp) +80000520: 13 01 01 01 addi sp, sp, 16 +80000524: 67 80 00 00 ret + +80000528 spawn_kernel_all_stub: +80000528: 13 01 01 fe addi sp, sp, -32 +8000052c: 23 2e 11 00 sw ra, 28(sp) +80000530: 23 2c 81 00 sw s0, 24(sp) +80000534: 23 2a 91 00 sw s1, 20(sp) +80000538: 23 28 21 01 sw s2, 16(sp) +8000053c: 23 26 31 01 sw s3, 12(sp) +80000540: 23 24 41 01 sw s4, 8(sp) +80000544: 73 26 50 cc csrr a2, 3269 +80000548: 73 27 30 cc csrr a4, 3267 +8000054c: f3 26 00 cc csrr a3, 3264 +80000550: 73 25 00 fc csrr a0, 4032 +80000554: b7 17 00 80 lui a5, 524289 +80000558: 13 16 26 00 slli a2, a2, 2 +8000055c: 93 87 47 43 addi a5, a5, 1076 +80000560: b3 87 c7 00 add a5, a5, a2 +80000564: 03 a4 07 00 lw s0, 0(a5) +80000568: 83 24 44 01 lw s1, 20(s0) +8000056c: 03 26 04 01 lw a2, 16(s0) +80000570: 33 2a 97 00 slt s4, a4, s1 +80000574: 93 87 04 00 mv a5, s1 +80000578: 33 0a ca 00 add s4, s4, a2 +8000057c: b3 04 e6 02 mul s1, a2, a4 +80000580: 63 54 f7 00 bge a4, a5, 8 +80000584: 93 07 07 00 mv a5, a4 +80000588: b3 84 f4 00 add s1, s1, a5 +8000058c: 83 25 04 00 lw a1, 0(s0) +80000590: 03 27 c4 00 lw a4, 12(s0) +80000594: 03 a9 05 00 lw s2, 0(a1) +80000598: 83 a9 45 00 lw s3, 4(a1) +8000059c: b3 84 a4 02 mul s1, s1, a0 +800005a0: b3 07 da 02 mul a5, s4, a3 +800005a4: b3 84 e4 00 add s1, s1, a4 +800005a8: b3 84 f4 00 add s1, s1, a5 +800005ac: 33 0a 9a 00 add s4, s4, s1 +800005b0: b3 09 39 03 mul s3, s2, s3 +800005b4: 63 c0 44 07 blt s1, s4, 96 +800005b8: 6f 00 00 08 j 128 +800005bc: 03 47 e4 01 lbu a4, 30(s0) +800005c0: 83 46 d4 01 lbu a3, 29(s0) +800005c4: 33 d7 e4 40 sra a4, s1, a4 +800005c8: b3 07 37 03 mul a5, a4, s3 +800005cc: b3 87 f4 40 sub a5, s1, a5 +800005d0: 63 80 06 06 beqz a3, 96 +800005d4: 83 46 f4 01 lbu a3, 31(s0) +800005d8: b3 d6 d7 40 sra a3, a5, a3 +800005dc: b3 88 26 03 mul a7, a3, s2 +800005e0: 03 ae 45 01 lw t3, 20(a1) +800005e4: 03 a3 05 01 lw t1, 16(a1) +800005e8: 03 a6 c5 00 lw a2, 12(a1) +800005ec: 03 28 44 00 lw a6, 4(s0) +800005f0: 03 25 84 00 lw a0, 8(s0) +800005f4: 93 84 14 00 addi s1, s1, 1 +800005f8: 33 07 c7 01 add a4, a4, t3 +800005fc: b3 86 66 00 add a3, a3, t1 +80000600: b3 87 17 41 sub a5, a5, a7 +80000604: 33 86 c7 00 add a2, a5, a2 +80000608: e7 00 08 00 jalr a6 +8000060c: 63 06 9a 02 beq s4, s1, 44 +80000610: 83 25 04 00 lw a1, 0(s0) +80000614: 83 47 c4 01 lbu a5, 28(s0) +80000618: e3 92 07 fa bnez a5, -92 +8000061c: 33 c7 34 03 div a4, s1, s3 +80000620: 83 46 d4 01 lbu a3, 29(s0) +80000624: b3 07 37 03 mul a5, a4, s3 +80000628: b3 87 f4 40 sub a5, s1, a5 +8000062c: e3 94 06 fa bnez a3, -88 +80000630: b3 c6 27 03 div a3, a5, s2 +80000634: 6f f0 9f fa j -88 +80000638: 03 27 84 01 lw a4, 24(s0) +8000063c: 93 07 00 00 mv a5, zero +80000640: 6b c0 e7 00 vx_bar a5, a4 +80000644: 83 20 c1 01 lw ra, 28(sp) +80000648: 03 24 81 01 lw s0, 24(sp) +8000064c: 83 24 41 01 lw s1, 20(sp) +80000650: 03 29 01 01 lw s2, 16(sp) +80000654: 83 29 c1 00 lw s3, 12(sp) +80000658: 03 2a 81 00 lw s4, 8(sp) +8000065c: 13 01 01 02 addi sp, sp, 32 +80000660: 67 80 00 00 ret + +80000664 spawn_kernel_rem_stub: +80000664: f3 26 50 cc csrr a3, 3269 +80000668: f3 27 20 cc csrr a5, 3266 +8000066c: 37 17 00 80 lui a4, 524289 +80000670: 93 96 26 00 slli a3, a3, 2 +80000674: 13 07 47 43 addi a4, a4, 1076 +80000678: 33 07 d7 00 add a4, a4, a3 +8000067c: 03 25 07 00 lw a0, 0(a4) +80000680: 83 25 05 00 lw a1, 0(a0) +80000684: 83 26 c5 00 lw a3, 12(a0) +80000688: 03 47 c5 01 lbu a4, 28(a0) +8000068c: 83 a8 05 00 lw a7, 0(a1) +80000690: 03 a6 45 00 lw a2, 4(a1) +80000694: b3 87 d7 00 add a5, a5, a3 +80000698: 33 86 c8 02 mul a2, a7, a2 +8000069c: 63 08 07 04 beqz a4, 80 +800006a0: 03 47 e5 01 lbu a4, 30(a0) +800006a4: 83 46 d5 01 lbu a3, 29(a0) +800006a8: 33 d7 e7 40 sra a4, a5, a4 +800006ac: 33 06 c7 02 mul a2, a4, a2 +800006b0: b3 87 c7 40 sub a5, a5, a2 +800006b4: 63 86 06 04 beqz a3, 76 +800006b8: 83 46 f5 01 lbu a3, 31(a0) +800006bc: 33 d8 d7 40 sra a6, a5, a3 +800006c0: 83 a6 05 01 lw a3, 16(a1) +800006c4: 03 ae 45 01 lw t3, 20(a1) +800006c8: 03 a6 c5 00 lw a2, 12(a1) +800006cc: b3 06 d8 00 add a3, a6, a3 +800006d0: 33 08 18 03 mul a6, a6, a7 +800006d4: 03 23 45 00 lw t1, 4(a0) +800006d8: 03 25 85 00 lw a0, 8(a0) +800006dc: 33 07 c7 01 add a4, a4, t3 +800006e0: b3 87 07 41 sub a5, a5, a6 +800006e4: 33 86 c7 00 add a2, a5, a2 +800006e8: 67 00 03 00 jr t1 +800006ec: 33 c7 c7 02 div a4, a5, a2 +800006f0: 83 46 d5 01 lbu a3, 29(a0) +800006f4: 33 06 c7 02 mul a2, a4, a2 +800006f8: b3 87 c7 40 sub a5, a5, a2 +800006fc: e3 9e 06 fa bnez a3, -68 +80000700: 33 c8 17 03 div a6, a5, a7 +80000704: 6f f0 df fb j -68 + +80000708 spawn_kernel_all_cb: +80000708: 13 01 01 ff addi sp, sp, -16 +8000070c: 23 26 11 00 sw ra, 12(sp) +80000710: 93 07 f0 ff addi a5, zero, -1 +80000714: 6b 80 07 00 vx_tmc a5 +80000718: ef f0 1f e1 jal -496 +8000071c: f3 27 30 cc csrr a5, 3267 +80000720: 93 b7 17 00 seqz a5, a5 +80000724: 6b 80 07 00 vx_tmc a5 +80000728: 83 20 c1 00 lw ra, 12(sp) +8000072c: 13 01 01 01 addi sp, sp, 16 +80000730: 67 80 00 00 ret + +80000734 vx_spawn_kernel: +80000734: 13 01 01 fd addi sp, sp, -48 +80000738: 23 26 11 02 sw ra, 44(sp) +8000073c: 23 24 81 02 sw s0, 40(sp) +80000740: 23 22 91 02 sw s1, 36(sp) +80000744: 23 20 21 03 sw s2, 32(sp) +80000748: f3 28 20 fc csrr a7, 4034 +8000074c: 73 23 10 fc csrr t1, 4033 +80000750: f3 24 00 fc csrr s1, 4032 +80000754: f3 27 50 cc csrr a5, 3269 +80000758: 13 07 f0 01 addi a4, zero, 31 +8000075c: 63 46 f7 0e blt a4, a5, 236 +80000760: 03 2e 05 00 lw t3, 0(a0) +80000764: 83 26 45 00 lw a3, 4(a0) +80000768: 03 28 85 00 lw a6, 8(a0) +8000076c: b3 0e 93 02 mul t4, t1, s1 +80000770: 13 07 10 00 addi a4, zero, 1 +80000774: b3 06 de 02 mul a3, t3, a3 +80000778: 33 88 06 03 mul a6, a3, a6 +8000077c: 63 d4 0e 01 bge t4, a6, 8 +80000780: 33 47 d8 03 div a4, a6, t4 +80000784: 63 ce e8 0c blt a7, a4, 220 +80000788: 63 d0 e7 0c bge a5, a4, 192 +8000078c: 93 88 f8 ff addi a7, a7, -1 +80000790: b3 4e e8 02 div t4, a6, a4 +80000794: 13 84 0e 00 mv s0, t4 +80000798: 63 96 f8 00 bne a7, a5, 12 +8000079c: 33 67 e8 02 rem a4, a6, a4 +800007a0: 33 04 d7 01 add s0, a4, t4 +800007a4: 33 49 94 02 div s2, s0, s1 +800007a8: 33 64 94 02 rem s0, s0, s1 +800007ac: 63 40 69 0c blt s2, t1, 192 +800007b0: 93 0f 10 00 addi t6, zero, 1 +800007b4: 33 4f 69 02 div t5, s2, t1 +800007b8: 63 06 0f 00 beqz t5, 12 +800007bc: 93 0f 0f 00 mv t6, t5 +800007c0: 33 6f 69 02 rem t5, s2, t1 +800007c4: d3 f7 06 d0 fcvt.s.w fa5, a3 +800007c8: 13 07 fe ff addi a4, t3, -1 +800007cc: 93 82 f6 ff addi t0, a3, -1 +800007d0: d3 88 07 e0 fmv.x.w a7, fa5 +800007d4: d3 77 0e d0 fcvt.s.w fa5, t3 +800007d8: 33 7e c7 01 and t3, a4, t3 +800007dc: 37 17 00 80 lui a4, 524289 +800007e0: 53 88 07 e0 fmv.x.w a6, fa5 +800007e4: b3 f6 d2 00 and a3, t0, a3 +800007e8: 93 d8 78 41 srai a7, a7, 23 +800007ec: 13 58 78 41 srai a6, a6, 23 +800007f0: 13 07 47 43 addi a4, a4, 1076 +800007f4: 93 b6 16 00 seqz a3, a3 +800007f8: 13 3e 1e 00 seqz t3, t3 +800007fc: 93 88 18 f8 addi a7, a7, -127 +80000800: 13 08 18 f8 addi a6, a6, -127 +80000804: 23 20 a1 00 sw a0, 0(sp) +80000808: 23 22 b1 00 sw a1, 4(sp) +8000080c: 23 24 c1 00 sw a2, 8(sp) +80000810: 23 28 f1 01 sw t6, 16(sp) +80000814: 23 2a e1 01 sw t5, 20(sp) +80000818: 23 2c 01 00 sw zero, 24(sp) +8000081c: 23 0e d1 00 sb a3, 28(sp) +80000820: a3 0e c1 01 sb t3, 29(sp) +80000824: 23 0f 11 01 sb a7, 30(sp) +80000828: a3 0f 01 01 sb a6, 31(sp) +8000082c: b3 8e fe 02 mul t4, t4, a5 +80000830: 93 97 27 00 slli a5, a5, 2 +80000834: b3 07 f7 00 add a5, a4, a5 +80000838: 23 a0 27 00 sw sp, 0(a5) +8000083c: 23 26 d1 01 sw t4, 12(sp) +80000840: 63 4c 20 03 bgtz s2, 56 +80000844: 63 16 04 06 bnez s0, 108 +80000848: 83 20 c1 02 lw ra, 44(sp) +8000084c: 03 24 81 02 lw s0, 40(sp) +80000850: 83 24 41 02 lw s1, 36(sp) +80000854: 03 29 01 02 lw s2, 32(sp) +80000858: 13 01 01 03 addi sp, sp, 48 +8000085c: 67 80 00 00 ret +80000860: 13 87 08 00 mv a4, a7 +80000864: e3 c4 e7 f2 blt a5, a4, -216 +80000868: 6f f0 1f fe j -32 +8000086c: 13 0f 00 00 mv t5, zero +80000870: 93 0f 10 00 addi t6, zero, 1 +80000874: 6f f0 1f f5 j -176 +80000878: 13 07 09 00 mv a4, s2 +8000087c: 63 54 23 01 bge t1, s2, 8 +80000880: 13 07 03 00 mv a4, t1 +80000884: b7 07 00 80 lui a5, 524288 +80000888: 23 2c e1 00 sw a4, 24(sp) +8000088c: 93 87 87 70 addi a5, a5, 1800 +80000890: 6b 10 f7 00 vx_wspawn a4, a5 +80000894: 93 07 f0 ff addi a5, zero, -1 +80000898: 6b 80 07 00 vx_tmc a5 +8000089c: ef f0 df c8 jal -884 +800008a0: f3 27 30 cc csrr a5, 3267 +800008a4: 93 b7 17 00 seqz a5, a5 +800008a8: 6b 80 07 00 vx_tmc a5 +800008ac: e3 0e 04 f8 beqz s0, -100 +800008b0: b3 04 99 02 mul s1, s2, s1 +800008b4: 13 09 10 00 addi s2, zero, 1 +800008b8: 33 14 89 00 sll s0, s2, s0 +800008bc: 13 04 f4 ff addi s0, s0, -1 +800008c0: 23 26 91 00 sw s1, 12(sp) +800008c4: 6b 00 04 00 vx_tmc s0 +800008c8: ef f0 df d9 jal -612 +800008cc: 6b 00 09 00 vx_tmc s2 +800008d0: 83 20 c1 02 lw ra, 44(sp) +800008d4: 03 24 81 02 lw s0, 40(sp) +800008d8: 83 24 41 02 lw s1, 36(sp) +800008dc: 03 29 01 02 lw s2, 32(sp) +800008e0: 13 01 01 03 addi sp, sp, 48 +800008e4: 67 80 00 00 ret + +800008e8 vx_perf_dump: +800008e8: f3 27 50 cc csrr a5, 3269 +800008ec: 37 07 ff 00 lui a4, 4080 +800008f0: b3 87 e7 00 add a5, a5, a4 +800008f4: 93 97 87 00 slli a5, a5, 8 +800008f8: 73 27 00 b0 csrr a4, mcycle +800008fc: 23 a0 e7 00 sw a4, 0(a5) +80000900: 73 27 10 b0 csrr a4, 2817 +80000904: 23 a2 e7 00 sw a4, 4(a5) +80000908: 73 27 20 b0 csrr a4, minstret +8000090c: 23 a4 e7 00 sw a4, 8(a5) +80000910: 73 27 30 b0 csrr a4, mhpmcounter3 +80000914: 23 a6 e7 00 sw a4, 12(a5) +80000918: 73 27 40 b0 csrr a4, mhpmcounter4 +8000091c: 23 a8 e7 00 sw a4, 16(a5) +80000920: 73 27 50 b0 csrr a4, mhpmcounter5 +80000924: 23 aa e7 00 sw a4, 20(a5) +80000928: 73 27 60 b0 csrr a4, mhpmcounter6 +8000092c: 23 ac e7 00 sw a4, 24(a5) +80000930: 73 27 70 b0 csrr a4, mhpmcounter7 +80000934: 23 ae e7 00 sw a4, 28(a5) +80000938: 73 27 80 b0 csrr a4, mhpmcounter8 +8000093c: 23 a0 e7 02 sw a4, 32(a5) +80000940: 73 27 90 b0 csrr a4, mhpmcounter9 +80000944: 23 a2 e7 02 sw a4, 36(a5) +80000948: 73 27 a0 b0 csrr a4, mhpmcounter10 +8000094c: 23 a4 e7 02 sw a4, 40(a5) +80000950: 73 27 b0 b0 csrr a4, mhpmcounter11 +80000954: 23 a6 e7 02 sw a4, 44(a5) +80000958: 73 27 c0 b0 csrr a4, mhpmcounter12 +8000095c: 23 a8 e7 02 sw a4, 48(a5) +80000960: 73 27 d0 b0 csrr a4, mhpmcounter13 +80000964: 23 aa e7 02 sw a4, 52(a5) +80000968: 73 27 e0 b0 csrr a4, mhpmcounter14 +8000096c: 23 ac e7 02 sw a4, 56(a5) +80000970: 73 27 f0 b0 csrr a4, mhpmcounter15 +80000974: 23 ae e7 02 sw a4, 60(a5) +80000978: 73 27 00 b1 csrr a4, mhpmcounter16 +8000097c: 23 a0 e7 04 sw a4, 64(a5) +80000980: 73 27 10 b1 csrr a4, mhpmcounter17 +80000984: 23 a2 e7 04 sw a4, 68(a5) +80000988: 73 27 20 b1 csrr a4, mhpmcounter18 +8000098c: 23 a4 e7 04 sw a4, 72(a5) +80000990: 73 27 30 b1 csrr a4, mhpmcounter19 +80000994: 23 a6 e7 04 sw a4, 76(a5) +80000998: 73 27 40 b1 csrr a4, mhpmcounter20 +8000099c: 23 a8 e7 04 sw a4, 80(a5) +800009a0: 73 27 50 b1 csrr a4, mhpmcounter21 +800009a4: 23 aa e7 04 sw a4, 84(a5) +800009a8: 73 27 60 b1 csrr a4, mhpmcounter22 +800009ac: 23 ac e7 04 sw a4, 88(a5) +800009b0: 73 27 70 b1 csrr a4, mhpmcounter23 +800009b4: 23 ae e7 04 sw a4, 92(a5) +800009b8: 73 27 80 b1 csrr a4, mhpmcounter24 +800009bc: 23 a0 e7 06 sw a4, 96(a5) +800009c0: 73 27 90 b1 csrr a4, mhpmcounter25 +800009c4: 23 a2 e7 06 sw a4, 100(a5) +800009c8: 73 27 a0 b1 csrr a4, mhpmcounter26 +800009cc: 23 a4 e7 06 sw a4, 104(a5) +800009d0: 73 27 b0 b1 csrr a4, mhpmcounter27 +800009d4: 23 a6 e7 06 sw a4, 108(a5) +800009d8: 73 27 c0 b1 csrr a4, mhpmcounter28 +800009dc: 23 a8 e7 06 sw a4, 112(a5) +800009e0: 73 27 d0 b1 csrr a4, mhpmcounter29 +800009e4: 23 aa e7 06 sw a4, 116(a5) +800009e8: 73 27 e0 b1 csrr a4, mhpmcounter30 +800009ec: 23 ac e7 06 sw a4, 120(a5) +800009f0: 73 27 f0 b1 csrr a4, mhpmcounter31 +800009f4: 23 ae e7 06 sw a4, 124(a5) +800009f8: 73 27 00 b8 csrr a4, mcycleh +800009fc: 23 a0 e7 08 sw a4, 128(a5) +80000a00: 73 27 10 b8 csrr a4, 2945 +80000a04: 23 a2 e7 08 sw a4, 132(a5) +80000a08: 73 27 20 b8 csrr a4, minstreth +80000a0c: 23 a4 e7 08 sw a4, 136(a5) +80000a10: 73 27 30 b8 csrr a4, mhpmcounter3h +80000a14: 23 a6 e7 08 sw a4, 140(a5) +80000a18: 73 27 40 b8 csrr a4, mhpmcounter4h +80000a1c: 23 a8 e7 08 sw a4, 144(a5) +80000a20: 73 27 50 b8 csrr a4, mhpmcounter5h +80000a24: 23 aa e7 08 sw a4, 148(a5) +80000a28: 73 27 60 b8 csrr a4, mhpmcounter6h +80000a2c: 23 ac e7 08 sw a4, 152(a5) +80000a30: 73 27 70 b8 csrr a4, mhpmcounter7h +80000a34: 23 ae e7 08 sw a4, 156(a5) +80000a38: 73 27 80 b8 csrr a4, mhpmcounter8h +80000a3c: 23 a0 e7 0a sw a4, 160(a5) +80000a40: 73 27 90 b8 csrr a4, mhpmcounter9h +80000a44: 23 a2 e7 0a sw a4, 164(a5) +80000a48: 73 27 a0 b8 csrr a4, mhpmcounter10h +80000a4c: 23 a4 e7 0a sw a4, 168(a5) +80000a50: 73 27 b0 b8 csrr a4, mhpmcounter11h +80000a54: 23 a6 e7 0a sw a4, 172(a5) +80000a58: 73 27 c0 b8 csrr a4, mhpmcounter12h +80000a5c: 23 a8 e7 0a sw a4, 176(a5) +80000a60: 73 27 d0 b8 csrr a4, mhpmcounter13h +80000a64: 23 aa e7 0a sw a4, 180(a5) +80000a68: 73 27 e0 b8 csrr a4, mhpmcounter14h +80000a6c: 23 ac e7 0a sw a4, 184(a5) +80000a70: 73 27 f0 b8 csrr a4, mhpmcounter15h +80000a74: 23 ae e7 0a sw a4, 188(a5) +80000a78: 73 27 00 b9 csrr a4, mhpmcounter16h +80000a7c: 23 a0 e7 0c sw a4, 192(a5) +80000a80: 73 27 10 b9 csrr a4, mhpmcounter17h +80000a84: 23 a2 e7 0c sw a4, 196(a5) +80000a88: 73 27 20 b9 csrr a4, mhpmcounter18h +80000a8c: 23 a4 e7 0c sw a4, 200(a5) +80000a90: 73 27 30 b9 csrr a4, mhpmcounter19h +80000a94: 23 a6 e7 0c sw a4, 204(a5) +80000a98: 73 27 40 b9 csrr a4, mhpmcounter20h +80000a9c: 23 a8 e7 0c sw a4, 208(a5) +80000aa0: 73 27 50 b9 csrr a4, mhpmcounter21h +80000aa4: 23 aa e7 0c sw a4, 212(a5) +80000aa8: 73 27 60 b9 csrr a4, mhpmcounter22h +80000aac: 23 ac e7 0c sw a4, 216(a5) +80000ab0: 73 27 70 b9 csrr a4, mhpmcounter23h +80000ab4: 23 ae e7 0c sw a4, 220(a5) +80000ab8: 73 27 80 b9 csrr a4, mhpmcounter24h +80000abc: 23 a0 e7 0e sw a4, 224(a5) +80000ac0: 73 27 90 b9 csrr a4, mhpmcounter25h +80000ac4: 23 a2 e7 0e sw a4, 228(a5) +80000ac8: 73 27 a0 b9 csrr a4, mhpmcounter26h +80000acc: 23 a4 e7 0e sw a4, 232(a5) +80000ad0: 73 27 b0 b9 csrr a4, mhpmcounter27h +80000ad4: 23 a6 e7 0e sw a4, 236(a5) +80000ad8: 73 27 c0 b9 csrr a4, mhpmcounter28h +80000adc: 23 a8 e7 0e sw a4, 240(a5) +80000ae0: 73 27 d0 b9 csrr a4, mhpmcounter29h +80000ae4: 23 aa e7 0e sw a4, 244(a5) +80000ae8: 73 27 e0 b9 csrr a4, mhpmcounter30h +80000aec: 23 ac e7 0e sw a4, 248(a5) +80000af0: 73 27 f0 b9 csrr a4, mhpmcounter31h +80000af4: 23 ae e7 0e sw a4, 252(a5) +80000af8: 67 80 00 00 ret + +80000afc atexit: +80000afc: 93 05 05 00 mv a1, a0 +80000b00: 93 06 00 00 mv a3, zero +80000b04: 13 06 00 00 mv a2, zero +80000b08: 13 05 00 00 mv a0, zero +80000b0c: 6f 00 40 11 j 276 + +80000b10 exit: +80000b10: 13 01 01 ff addi sp, sp, -16 +80000b14: 93 05 00 00 mv a1, zero +80000b18: 23 24 81 00 sw s0, 8(sp) +80000b1c: 23 26 11 00 sw ra, 12(sp) +80000b20: 13 04 05 00 mv s0, a0 +80000b24: ef 00 80 19 jal 408 +80000b28: b7 17 00 80 lui a5, 524289 +80000b2c: 03 a5 07 43 lw a0, 1072(a5) +80000b30: 83 27 c5 03 lw a5, 60(a0) +80000b34: 63 84 07 00 beqz a5, 8 +80000b38: e7 80 07 00 jalr a5 +80000b3c: 13 05 04 00 mv a0, s0 +80000b40: ef f0 5f 8a jal -1884 + +80000b44 memset: +80000b44: 13 03 f0 00 addi t1, zero, 15 +80000b48: 13 07 05 00 mv a4, a0 +80000b4c: 63 7e c3 02 bgeu t1, a2, 60 +80000b50: 93 77 f7 00 andi a5, a4, 15 +80000b54: 63 90 07 0a bnez a5, 160 +80000b58: 63 92 05 08 bnez a1, 132 +80000b5c: 93 76 06 ff andi a3, a2, -16 +80000b60: 13 76 f6 00 andi a2, a2, 15 +80000b64: b3 86 e6 00 add a3, a3, a4 +80000b68: 23 20 b7 00 sw a1, 0(a4) +80000b6c: 23 22 b7 00 sw a1, 4(a4) +80000b70: 23 24 b7 00 sw a1, 8(a4) +80000b74: 23 26 b7 00 sw a1, 12(a4) +80000b78: 13 07 07 01 addi a4, a4, 16 +80000b7c: e3 66 d7 fe bltu a4, a3, -20 +80000b80: 63 14 06 00 bnez a2, 8 +80000b84: 67 80 00 00 ret +80000b88: b3 06 c3 40 sub a3, t1, a2 +80000b8c: 93 96 26 00 slli a3, a3, 2 +80000b90: 97 02 00 00 auipc t0, 0 +80000b94: b3 86 56 00 add a3, a3, t0 +80000b98: 67 80 c6 00 jr 12(a3) +80000b9c: 23 07 b7 00 sb a1, 14(a4) +80000ba0: a3 06 b7 00 sb a1, 13(a4) +80000ba4: 23 06 b7 00 sb a1, 12(a4) +80000ba8: a3 05 b7 00 sb a1, 11(a4) +80000bac: 23 05 b7 00 sb a1, 10(a4) +80000bb0: a3 04 b7 00 sb a1, 9(a4) +80000bb4: 23 04 b7 00 sb a1, 8(a4) +80000bb8: a3 03 b7 00 sb a1, 7(a4) +80000bbc: 23 03 b7 00 sb a1, 6(a4) +80000bc0: a3 02 b7 00 sb a1, 5(a4) +80000bc4: 23 02 b7 00 sb a1, 4(a4) +80000bc8: a3 01 b7 00 sb a1, 3(a4) +80000bcc: 23 01 b7 00 sb a1, 2(a4) +80000bd0: a3 00 b7 00 sb a1, 1(a4) +80000bd4: 23 00 b7 00 sb a1, 0(a4) +80000bd8: 67 80 00 00 ret +80000bdc: 93 f5 f5 0f andi a1, a1, 255 +80000be0: 93 96 85 00 slli a3, a1, 8 +80000be4: b3 e5 d5 00 or a1, a1, a3 +80000be8: 93 96 05 01 slli a3, a1, 16 +80000bec: b3 e5 d5 00 or a1, a1, a3 +80000bf0: 6f f0 df f6 j -148 +80000bf4: 93 96 27 00 slli a3, a5, 2 +80000bf8: 97 02 00 00 auipc t0, 0 +80000bfc: b3 86 56 00 add a3, a3, t0 +80000c00: 93 82 00 00 mv t0, ra +80000c04: e7 80 06 fa jalr -96(a3) +80000c08: 93 80 02 00 mv ra, t0 +80000c0c: 93 87 07 ff addi a5, a5, -16 +80000c10: 33 07 f7 40 sub a4, a4, a5 +80000c14: 33 06 f6 00 add a2, a2, a5 +80000c18: e3 78 c3 f6 bgeu t1, a2, -144 +80000c1c: 6f f0 df f3 j -196 + +80000c20 __register_exitproc: +80000c20: b7 17 00 80 lui a5, 524289 +80000c24: 03 a7 07 43 lw a4, 1072(a5) +80000c28: 83 27 87 14 lw a5, 328(a4) +80000c2c: 63 8c 07 04 beqz a5, 88 +80000c30: 03 a7 47 00 lw a4, 4(a5) +80000c34: 13 08 f0 01 addi a6, zero, 31 +80000c38: 63 4e e8 06 blt a6, a4, 124 +80000c3c: 13 18 27 00 slli a6, a4, 2 +80000c40: 63 06 05 02 beqz a0, 44 +80000c44: 33 83 07 01 add t1, a5, a6 +80000c48: 23 24 c3 08 sw a2, 136(t1) +80000c4c: 83 a8 87 18 lw a7, 392(a5) +80000c50: 13 06 10 00 addi a2, zero, 1 +80000c54: 33 16 e6 00 sll a2, a2, a4 +80000c58: b3 e8 c8 00 or a7, a7, a2 +80000c5c: 23 a4 17 19 sw a7, 392(a5) +80000c60: 23 24 d3 10 sw a3, 264(t1) +80000c64: 93 06 20 00 addi a3, zero, 2 +80000c68: 63 04 d5 02 beq a0, a3, 40 +80000c6c: 13 07 17 00 addi a4, a4, 1 +80000c70: 23 a2 e7 00 sw a4, 4(a5) +80000c74: b3 87 07 01 add a5, a5, a6 +80000c78: 23 a4 b7 00 sw a1, 8(a5) +80000c7c: 13 05 00 00 mv a0, zero +80000c80: 67 80 00 00 ret +80000c84: 93 07 c7 14 addi a5, a4, 332 +80000c88: 23 24 f7 14 sw a5, 328(a4) +80000c8c: 6f f0 5f fa j -92 +80000c90: 83 a6 c7 18 lw a3, 396(a5) +80000c94: 13 07 17 00 addi a4, a4, 1 +80000c98: 23 a2 e7 00 sw a4, 4(a5) +80000c9c: 33 e6 c6 00 or a2, a3, a2 +80000ca0: 23 a6 c7 18 sw a2, 396(a5) +80000ca4: b3 87 07 01 add a5, a5, a6 +80000ca8: 23 a4 b7 00 sw a1, 8(a5) +80000cac: 13 05 00 00 mv a0, zero +80000cb0: 67 80 00 00 ret +80000cb4: 13 05 f0 ff addi a0, zero, -1 +80000cb8: 67 80 00 00 ret + +80000cbc __call_exitprocs: +80000cbc: 13 01 01 fd addi sp, sp, -48 +80000cc0: b7 17 00 80 lui a5, 524289 +80000cc4: 23 2c 41 01 sw s4, 24(sp) +80000cc8: 03 aa 07 43 lw s4, 1072(a5) +80000ccc: 23 20 21 03 sw s2, 32(sp) +80000cd0: 23 26 11 02 sw ra, 44(sp) +80000cd4: 03 29 8a 14 lw s2, 328(s4) +80000cd8: 23 24 81 02 sw s0, 40(sp) +80000cdc: 23 22 91 02 sw s1, 36(sp) +80000ce0: 23 2e 31 01 sw s3, 28(sp) +80000ce4: 23 2a 51 01 sw s5, 20(sp) +80000ce8: 23 28 61 01 sw s6, 16(sp) +80000cec: 23 26 71 01 sw s7, 12(sp) +80000cf0: 23 24 81 01 sw s8, 8(sp) +80000cf4: 63 00 09 04 beqz s2, 64 +80000cf8: 13 0b 05 00 mv s6, a0 +80000cfc: 93 8b 05 00 mv s7, a1 +80000d00: 93 0a 10 00 addi s5, zero, 1 +80000d04: 93 09 f0 ff addi s3, zero, -1 +80000d08: 83 24 49 00 lw s1, 4(s2) +80000d0c: 13 84 f4 ff addi s0, s1, -1 +80000d10: 63 42 04 02 bltz s0, 36 +80000d14: 93 94 24 00 slli s1, s1, 2 +80000d18: b3 04 99 00 add s1, s2, s1 +80000d1c: 63 84 0b 04 beqz s7, 72 +80000d20: 83 a7 44 10 lw a5, 260(s1) +80000d24: 63 80 77 05 beq a5, s7, 64 +80000d28: 13 04 f4 ff addi s0, s0, -1 +80000d2c: 93 84 c4 ff addi s1, s1, -4 +80000d30: e3 16 34 ff bne s0, s3, -20 +80000d34: 83 20 c1 02 lw ra, 44(sp) +80000d38: 03 24 81 02 lw s0, 40(sp) +80000d3c: 83 24 41 02 lw s1, 36(sp) +80000d40: 03 29 01 02 lw s2, 32(sp) +80000d44: 83 29 c1 01 lw s3, 28(sp) +80000d48: 03 2a 81 01 lw s4, 24(sp) +80000d4c: 83 2a 41 01 lw s5, 20(sp) +80000d50: 03 2b 01 01 lw s6, 16(sp) +80000d54: 83 2b c1 00 lw s7, 12(sp) +80000d58: 03 2c 81 00 lw s8, 8(sp) +80000d5c: 13 01 01 03 addi sp, sp, 48 +80000d60: 67 80 00 00 ret +80000d64: 83 27 49 00 lw a5, 4(s2) +80000d68: 83 a6 44 00 lw a3, 4(s1) +80000d6c: 93 87 f7 ff addi a5, a5, -1 +80000d70: 63 8e 87 04 beq a5, s0, 92 +80000d74: 23 a2 04 00 sw zero, 4(s1) +80000d78: e3 88 06 fa beqz a3, -80 +80000d7c: 83 27 89 18 lw a5, 392(s2) +80000d80: 33 97 8a 00 sll a4, s5, s0 +80000d84: 03 2c 49 00 lw s8, 4(s2) +80000d88: b3 77 f7 00 and a5, a4, a5 +80000d8c: 63 92 07 02 bnez a5, 36 +80000d90: e7 80 06 00 jalr a3 +80000d94: 03 27 49 00 lw a4, 4(s2) +80000d98: 83 27 8a 14 lw a5, 328(s4) +80000d9c: 63 14 87 01 bne a4, s8, 8 +80000da0: e3 04 f9 f8 beq s2, a5, -120 +80000da4: e3 88 07 f8 beqz a5, -112 +80000da8: 13 89 07 00 mv s2, a5 +80000dac: 6f f0 df f5 j -164 +80000db0: 83 27 c9 18 lw a5, 396(s2) +80000db4: 83 a5 44 08 lw a1, 132(s1) +80000db8: 33 77 f7 00 and a4, a4, a5 +80000dbc: 63 1c 07 00 bnez a4, 24 +80000dc0: 13 05 0b 00 mv a0, s6 +80000dc4: e7 80 06 00 jalr a3 +80000dc8: 6f f0 df fc j -52 +80000dcc: 23 22 89 00 sw s0, 4(s2) +80000dd0: 6f f0 9f fa j -88 +80000dd4: 13 85 05 00 mv a0, a1 +80000dd8: e7 80 06 00 jalr a3 +80000ddc: 6f f0 9f fb j -72 + +Disassembly of section .init_array: + +80001000 __preinit_array_start: +80001000: 50 00 +80001002: 00 80 + +Disassembly of section .data: + +80001008 impure_data: +80001008: 00 00 +8000100a: 00 00 +8000100c: f4 12 +8000100e: 00 80 +80001010: 5c 13 +80001012: 00 80 +80001014: c4 13 +80001016: 00 80 + ... +800010b0: 01 00 +800010b2: 00 00 +800010b4: 00 00 +800010b6: 00 00 +800010b8: 0e 33 +800010ba: cd ab +800010bc: 34 12 +800010be: 6d e6 +800010c0: ec de +800010c2: 05 00 +800010c4: 0b 00 00 00 + ... + +Disassembly of section .sdata: + +80001430 _global_impure_ptr: +80001430: 08 10 +80001432: 00 80 + +Disassembly of section .bss: + +80001434 g_wspawn_args: +... + +Disassembly of section .comment: + +00000000 .comment: + 0: 63 6c 61 6e bltu sp, t1, 1784 + 4: 67 20 76 65 + 8: 72 73 + a: 69 6f + c: 6e 20 + e: 31 30 + 10: 2e 30 + 12: 2e 31 + 14: 20 28 + 16: 68 74 + 18: 74 70 + 1a: 73 3a 2f 2f csrrc s4, 754, t5 + 1e: 67 69 74 68 + 22: 75 62 + 24: 2e 63 + 26: 6f 6d 2f 6c jal s10, 1009346 + 2a: 6c 76 + 2c: 6d 2f + 2e: 6c 6c + 30: 76 6d + 32: 2d 70 + 34: 72 6f + 36: 6a 65 + 38: 63 74 2e 67 bgeu t3, s2, 1640 + 3c: 69 74 + 3e: 20 32 + 40: 61 32 + 42: 33 65 66 61 + 46: 63 33 35 32 + 4a: 66 39 + 4c: 31 39 + 4e: 65 62 + 50: 64 31 + 52: 65 63 + 54: 31 62 + 56: 65 34 + 58: 35 31 + 5a: 34 36 + 5c: 64 36 + 5e: 61 39 + 60: 66 61 + 62: 32 31 + 64: 62 35 + 66: 33 29 00 47 + 6a: 43 43 3a 20 fmadd.s ft6, fs4, ft3, ft4, rmm + 6e: 28 47 + 70: 4e 55 + 72: 29 20 + 74: 39 2e + 76: 32 2e + 78: 30 00 + +Disassembly of section .riscv.attributes: + +00000000 .riscv.attributes: + 0: 41 25 + 2: 00 00 + 4: 00 72 + 6: 69 73 + 8: 63 76 00 01 bgeu zero, a6, 12 + c: 1b 00 00 00 + 10: 04 10 + 12: 05 72 + 14: 76 33 + 16: 32 69 + 18: 32 70 + 1a: 30 5f + 1c: 6d 32 + 1e: 70 30 + 20: 5f 66 32 70 + 24: 30 00 + +Disassembly of section .symtab: + +00000000 .symtab: + ... + 14: 00 00 + 16: 00 80 + 18: 00 00 + 1a: 00 00 + 1c: 03 00 01 00 lb zero, 0(sp) + 20: 00 00 + 22: 00 00 + 24: 50 00 + 26: 00 80 + 28: 00 00 + 2a: 00 00 + 2c: 03 00 02 00 lb zero, 0(tp) + 30: 00 00 + 32: 00 00 + 34: 00 10 + 36: 00 80 + 38: 00 00 + 3a: 00 00 + 3c: 03 00 03 00 lb zero, 0(t1) + 40: 00 00 + 42: 00 00 + 44: 08 10 + 46: 00 80 + 48: 00 00 + 4a: 00 00 + 4c: 03 00 04 00 lb zero, 0(s0) + 50: 00 00 + 52: 00 00 + 54: 30 14 + 56: 00 80 + 58: 00 00 + 5a: 00 00 + 5c: 03 00 05 00 lb zero, 0(a0) + 60: 00 00 + 62: 00 00 + 64: 34 14 + 66: 00 80 + 68: 00 00 + 6a: 00 00 + 6c: 03 00 06 00 lb zero, 0(a2) + ... + 7c: 03 00 07 00 lb zero, 0(a4) + ... + 8c: 03 00 08 00 lb zero, 0(a6) + 90: 01 00 + ... + 9a: 00 00 + 9c: 04 00 + 9e: f1 ff + a0: 0e 00 + a2: 00 00 + a4: f0 03 + a6: 00 80 + a8: 00 00 + aa: 00 00 + ac: 00 00 + ae: 02 00 + b0: 1e 00 + b2: 00 00 + b4: 2c 04 + b6: 00 80 + b8: 00 00 + ba: 00 00 + bc: 00 00 + be: 02 00 + c0: 25 00 + ... + ca: 00 00 + cc: 04 00 + ce: f1 ff + d0: 35 00 + d2: 00 00 + d4: 50 00 + d6: 00 80 + d8: 18 00 + da: 00 00 + dc: 02 00 + de: 02 00 + e0: 43 00 00 00 fmadd.s ft0, ft0, ft0, ft0, rne + ... + ec: 04 00 + ee: f1 ff + f0: 67 00 00 00 jr zero + ... + fc: 04 00 + fe: f1 ff + 100: 73 00 00 00 ecall + ... + 10c: 04 00 + 10e: f1 ff + 110: 81 00 + ... + 11a: 00 00 + 11c: 04 00 + 11e: f1 ff + 120: 8c 00 + 122: 00 00 + 124: 28 05 + 126: 00 80 + 128: 3c 01 + 12a: 00 00 + 12c: 02 00 + 12e: 02 00 + 130: a2 00 + 132: 00 00 + 134: 64 06 + 136: 00 80 + 138: a4 00 + 13a: 00 00 + 13c: 02 00 + 13e: 02 00 + 140: b8 00 + 142: 00 00 + 144: 08 07 + 146: 00 80 + 148: 2c 00 + 14a: 00 00 + 14c: 02 00 + 14e: 02 00 + 150: cc 00 + ... + 15a: 00 00 + 15c: 04 00 + 15e: f1 ff + 160: d8 00 + ... + 16a: 00 00 + 16c: 04 00 + 16e: f1 ff + 170: da 00 + ... + 17a: 00 00 + 17c: 04 00 + 17e: f1 ff + 180: d6 00 + ... + 18a: 00 00 + 18c: 04 00 + 18e: f1 ff + 190: e1 00 + ... + 19a: 00 00 + 19c: 04 00 + 19e: f1 ff + 1a0: ea 00 + 1a2: 00 00 + 1a4: 08 10 + 1a6: 00 80 + 1a8: 28 04 + 1aa: 00 00 + 1ac: 01 00 + 1ae: 04 00 + ... + 1bc: 04 00 + 1be: f1 ff + 1c0: f6 00 + 1c2: 00 00 + 1c4: 04 10 + 1c6: 00 80 + 1c8: 00 00 + 1ca: 00 00 + 1cc: 00 00 + 1ce: 03 00 07 01 lb zero, 16(a4) + 1d2: 00 00 + 1d4: 04 10 + 1d6: 00 80 + 1d8: 00 00 + 1da: 00 00 + 1dc: 00 00 + 1de: 03 00 1a 01 lb zero, 17(s4) + 1e2: 00 00 + 1e4: 04 10 + 1e6: 00 80 + 1e8: 00 00 + 1ea: 00 00 + 1ec: 00 00 + 1ee: 03 00 2b 01 lb zero, 18(s6) + 1f2: 00 00 + 1f4: 00 10 + 1f6: 00 80 + 1f8: 00 00 + 1fa: 00 00 + 1fc: 00 00 + 1fe: 03 00 3f 01 lb zero, 19(t5) + 202: 00 00 + 204: 00 10 + 206: 00 80 + 208: 00 00 + 20a: 00 00 + 20c: 00 00 + 20e: 03 00 52 01 lb zero, 21(tp) + 212: 00 00 + 214: 00 10 + 216: 00 80 + 218: 00 00 + 21a: 00 00 + 21c: 00 00 + 21e: 03 00 68 01 lb zero, 22(a6) + ... + 22a: 00 00 + 22c: 10 00 + 22e: f1 ff + 230: 76 01 + 232: 00 00 + 234: 00 04 + 236: 00 00 + 238: 00 00 + 23a: 00 00 + 23c: 10 00 + 23e: f1 ff + 240: 83 01 00 00 lb gp, 0(zero) + 244: 34 14 + 246: 00 80 + 248: 80 00 + 24a: 00 00 + 24c: 11 00 + 24e: 06 00 + 250: 91 01 + 252: 00 00 + 254: 30 14 + 256: 00 80 + 258: 00 00 + 25a: 00 00 + 25c: 10 00 + 25e: 05 00 + 260: a1 01 + 262: 00 00 + 264: 08 18 + 266: 00 80 + 268: 00 00 + 26a: 00 00 + 26c: 10 00 + 26e: f1 ff + 270: b2 01 + 272: 00 00 + 274: dc 02 + 276: 00 80 + 278: 08 01 + 27a: 00 00 + 27c: 12 00 + 27e: 02 00 + 280: d5 01 + 282: 00 00 + 284: 30 14 + 286: 00 80 + 288: 04 00 + 28a: 00 00 + 28c: 11 00 + 28e: 05 00 + 290: e8 01 + 292: 00 00 + 294: 30 04 + 296: 00 80 + 298: 9c 00 + 29a: 00 00 + 29c: 12 00 + 29e: 02 00 + 2a0: fa 01 + 2a2: 00 00 + 2a4: cc 04 + 2a6: 00 80 + 2a8: 5c 00 + 2aa: 00 00 + 2ac: 12 00 + 2ae: 02 00 + 2b0: 0c 02 + 2b2: 00 00 + 2b4: fc 03 + 2b6: 00 80 + 2b8: 00 00 + 2ba: 00 00 + 2bc: 12 00 + 2be: 02 00 + 2c0: 16 02 + 2c2: 00 00 + 2c4: bc 0c + 2c6: 00 80 + 2c8: 24 01 + 2ca: 00 00 + 2cc: 12 00 + 2ce: 02 00 + 2d0: 60 02 + 2d2: 00 00 + 2d4: 00 00 + 2d6: 00 80 + 2d8: 50 00 + 2da: 00 00 + 2dc: 12 00 + 2de: 01 00 + 2e0: 27 02 00 00 + 2e4: 98 00 + 2e6: 00 80 + 2e8: 1c 01 + 2ea: 00 00 + 2ec: 12 00 + 2ee: 02 00 + 2f0: 3b 02 00 00 + 2f4: 20 0c + 2f6: 00 80 + 2f8: 9c 00 + 2fa: 00 00 + 2fc: 12 00 + 2fe: 02 00 + 300: 4f 02 00 00 fnmadd.s ft4, ft0, ft0, ft0, rne + 304: b4 14 + 306: 00 80 + 308: 00 00 + 30a: 00 00 + 30c: 10 00 + 30e: 06 00 + 310: 5b 02 00 00 + 314: 34 14 + 316: 00 80 + 318: 00 00 + 31a: 00 00 + 31c: 10 00 + 31e: 06 00 + 320: 67 02 00 00 jalr tp, zero + 324: 44 0b + 326: 00 80 + 328: dc 00 + 32a: 00 00 + 32c: 12 00 + 32e: 02 00 + 330: 6e 02 + 332: 00 00 + 334: 68 00 + 336: 00 80 + 338: 30 00 + 33a: 00 00 + 33c: 12 00 + 33e: 02 00 + 340: 73 02 00 00 + 344: fc 0a + 346: 00 80 + 348: 14 00 + 34a: 00 00 + 34c: 12 00 + 34e: 02 00 + 350: 7a 02 + 352: 00 00 + 354: b4 01 + 356: 00 80 + 358: 28 01 + 35a: 00 00 + 35c: 12 00 + 35e: 02 00 + 360: 98 02 + 362: 00 00 + 364: 08 10 + 366: 00 80 + 368: 00 00 + 36a: 00 00 + 36c: 10 00 + 36e: 04 00 + 370: a7 02 00 00 + 374: 34 14 + 376: 00 80 + 378: 00 00 + 37a: 00 00 + 37c: 10 00 + 37e: 05 00 + 380: 02 01 + 382: 00 00 + 384: b4 14 + 386: 00 80 + 388: 00 00 + 38a: 00 00 + 38c: 10 00 + 38e: 06 00 + 390: bc 02 + 392: 00 00 + 394: 10 0b + 396: 00 80 + 398: 34 00 + 39a: 00 00 + 39c: 12 00 + 39e: 02 00 + 3a0: ae 02 + 3a2: 00 00 + 3a4: e8 08 + 3a6: 00 80 + 3a8: 14 02 + 3aa: 00 00 + 3ac: 12 00 + 3ae: 02 00 + 3b0: bb 02 00 00 + 3b4: e4 03 + 3b6: 00 80 + 3b8: 00 00 + 3ba: 00 00 + 3bc: 12 00 + 3be: 02 00 + 3c0: c1 02 + 3c2: 00 00 + 3c4: 34 07 + 3c6: 00 80 + 3c8: b4 01 + 3ca: 00 00 + 3cc: 12 00 + 3ce: 02 00 + +Disassembly of section .strtab: + +00000000 .strtab: + 0: 00 76 + 2: 78 5f + 4: 73 74 61 72 csrrci s0, 1830, 2 + 8: 74 2e + a: 53 2e 6f 00 fadd.s ft8, ft10, ft6, rdn + e: 6c 61 + 10: 62 65 + 12: 6c 5f + 14: 65 78 + 16: 69 74 + 18: 5f 6e 65 78 + 1c: 74 00 + 1e: 52 45 + 20: 54 55 + 22: 52 4e + 24: 00 5f + 26: 5f 63 61 6c + 2a: 6c 5f + 2c: 61 74 + 2e: 65 78 + 30: 69 74 + 32: 2e 63 + 34: 00 72 + 36: 65 67 + 38: 69 73 + 3a: 74 65 + 3c: 72 5f + 3e: 66 69 + 40: 6e 69 + 42: 00 70 + 44: 6f 63 6c 5f jal t1, 812534 + 48: 76 6f + 4a: 72 74 + 4c: 65 78 + 4e: 5f 6b 65 72 + 52: 6e 65 + 54: 6c 2d + 56: 32 36 + 58: 2d 61 + 5a: 32 2d + 5c: 34 64 + 5e: 2d 32 + 60: 65 2d + 62: 32 33 + 64: 2e 63 + 66: 00 70 + 68: 61 72 + 6a: 61 6c + 6c: 6c 65 + 6e: 6c 5f + 70: 62 63 + 72: 00 76 + 74: 78 5f + 76: 73 79 73 63 csrrci s2, 1591, 6 + 7a: 61 6c + 7c: 6c 73 + 7e: 2e 63 + 80: 00 76 + 82: 78 5f + 84: 73 70 61 77 csrci 1910, 2 + 88: 6e 2e + 8a: 63 00 73 70 beq t1, t2, 1792 + 8e: 61 77 + 90: 6e 5f + 92: 6b 65 72 6e + 96: 65 6c + 98: 5f 61 6c 6c + 9c: 5f 73 74 75 + a0: 62 00 + a2: 73 70 61 77 csrci 1910, 2 + a6: 6e 5f + a8: 6b 65 72 6e + ac: 65 6c + ae: 5f 72 65 6d + b2: 5f 73 74 75 + b6: 62 00 + b8: 73 70 61 77 csrci 1910, 2 + bc: 6e 5f + be: 6b 65 72 6e + c2: 65 6c + c4: 5f 61 6c 6c + c8: 5f 63 62 00 + cc: 76 78 + ce: 5f 70 65 72 + d2: 66 2e + d4: 63 00 5f 5f beq t5, s5, 1504 + d8: 61 74 + da: 65 78 + dc: 69 74 + de: 2e 63 + e0: 00 69 + e2: 6d 70 + e4: 75 72 + e6: 65 2e + e8: 63 00 69 6d beq s2, s6, 1728 + ec: 70 75 + ee: 72 65 + f0: 5f 64 61 74 + f4: 61 00 + f6: 5f 5f 66 69 + fa: 6e 69 + fc: 5f 61 72 72 + 100: 61 79 + 102: 5f 65 6e 64 + 106: 00 5f + 108: 5f 66 69 6e + 10c: 69 5f + 10e: 61 72 + 110: 72 61 + 112: 79 5f + 114: 73 74 61 72 csrrci s0, 1830, 2 + 118: 74 00 + 11a: 5f 5f 69 6e + 11e: 69 74 + 120: 5f 61 72 72 + 124: 61 79 + 126: 5f 65 6e 64 + 12a: 00 5f + 12c: 5f 70 72 65 + 130: 69 6e + 132: 69 74 + 134: 5f 61 72 72 + 138: 61 79 + 13a: 5f 65 6e 64 + 13e: 00 5f + 140: 5f 69 6e 69 + 144: 74 5f + 146: 61 72 + 148: 72 61 + 14a: 79 5f + 14c: 73 74 61 72 csrrci s0, 1830, 2 + 150: 74 00 + 152: 5f 5f 70 72 + 156: 65 69 + 158: 6e 69 + 15a: 74 5f + 15c: 61 72 + 15e: 72 61 + 160: 79 5f + 162: 73 74 61 72 csrrci s0, 1830, 2 + 166: 74 00 + 168: 5f 5f 73 74 + 16c: 61 63 + 16e: 6b 5f 75 73 + 172: 61 67 + 174: 65 00 + 176: 5f 5f 73 74 + 17a: 61 63 + 17c: 6b 5f 73 69 + 180: 7a 65 + 182: 00 67 + 184: 5f 77 73 70 + 188: 61 77 + 18a: 6e 5f + 18c: 61 72 + 18e: 67 73 00 5f + 192: 5f 53 44 41 + 196: 54 41 + 198: 5f 42 45 47 + 19c: 49 4e + 19e: 5f 5f 00 5f + 1a2: 5f 67 6c 6f + 1a6: 62 61 + 1a8: 6c 5f + 1aa: 70 6f + 1ac: 69 6e + 1ae: 74 65 + 1b0: 72 00 + 1b2: 5f 70 6f 63 + 1b6: 6c 5f + 1b8: 6b 65 72 6e + 1bc: 65 6c + 1be: 5f 70 73 6f + 1c2: 72 74 + 1c4: 66 5f + 1c6: 77 6f 72 6b + 1ca: 67 72 6f 75 + 1ce: 70 5f + 1d0: 66 61 + 1d2: 73 74 00 5f csrrci s0, 1520, 0 + 1d6: 67 6c 6f 62 + 1da: 61 6c + 1dc: 5f 69 6d 70 + 1e0: 75 72 + 1e2: 65 5f + 1e4: 70 74 + 1e6: 72 00 + 1e8: 5f 5f 6c 69 + 1ec: 62 63 + 1ee: 5f 69 6e 69 + 1f2: 74 5f + 1f4: 61 72 + 1f6: 72 61 + 1f8: 79 00 + 1fa: 5f 5f 6c 69 + 1fe: 62 63 + 200: 5f 66 69 6e + 204: 69 5f + 206: 61 72 + 208: 72 61 + 20a: 79 00 + 20c: 76 78 + 20e: 5f 73 65 74 + 212: 5f 73 70 00 + 216: 5f 5f 63 61 + 21a: 6c 6c + 21c: 5f 65 78 69 + 220: 74 70 + 222: 72 6f + 224: 63 73 00 5f bgeu zero, a6, 1510 + 228: 70 6f + 22a: 63 6c 5f 6b bltu t5, s5, 1720 + 22e: 65 72 + 230: 6e 65 + 232: 6c 5f + 234: 70 73 + 236: 6f 72 74 66 jal tp, 294502 + 23a: 00 5f + 23c: 5f 72 65 67 + 240: 69 73 + 242: 74 65 + 244: 72 5f + 246: 65 78 + 248: 69 74 + 24a: 70 72 + 24c: 6f 63 00 5f jal t1, 26096 + 250: 5f 42 53 53 + 254: 5f 45 4e 44 + 258: 5f 5f 00 5f + 25c: 5f 62 73 73 + 260: 5f 73 74 61 + 264: 72 74 + 266: 00 6d + 268: 65 6d + 26a: 73 65 74 00 csrrsi a0, 7, 8 + 26e: 6d 61 + 270: 69 6e + 272: 00 61 + 274: 74 65 + 276: 78 69 + 278: 74 00 + 27a: 5f 70 6f 63 + 27e: 6c 5f + 280: 6b 65 72 6e + 284: 65 6c + 286: 5f 70 73 6f + 28a: 72 74 + 28c: 66 5f + 28e: 77 6f 72 6b + 292: 67 72 6f 75 + 296: 70 00 + 298: 5f 5f 44 41 + 29c: 54 41 + 29e: 5f 42 45 47 + 2a2: 49 4e + 2a4: 5f 5f 00 5f + 2a8: 65 64 + 2aa: 61 74 + 2ac: 61 00 + 2ae: 76 78 + 2b0: 5f 70 65 72 + 2b4: 66 5f + 2b6: 64 75 + 2b8: 6d 70 + 2ba: 00 5f + 2bc: 65 78 + 2be: 69 74 + 2c0: 00 76 + 2c2: 78 5f + 2c4: 73 70 61 77 csrci 1910, 2 + 2c8: 6e 5f + 2ca: 6b 65 72 6e + 2ce: 65 6c + 2d0: 00 + +Disassembly of section .shstrtab: + +00000000 .shstrtab: + 0: 00 2e + 2: 73 79 6d 74 csrrci s2, 1862, 26 + 6: 61 62 + 8: 00 2e + a: 73 74 72 74 csrrci s0, 1863, 4 + e: 61 62 + 10: 00 2e + 12: 73 68 73 74 csrrsi a6, 1863, 6 + 16: 72 74 + 18: 61 62 + 1a: 00 2e + 1c: 69 6e + 1e: 69 74 + 20: 00 2e + 22: 74 65 + 24: 78 74 + 26: 00 2e + 28: 69 6e + 2a: 69 74 + 2c: 5f 61 72 72 + 30: 61 79 + 32: 00 2e + 34: 64 61 + 36: 74 61 + 38: 00 2e + 3a: 73 64 61 74 csrrsi s0, 1862, 2 + 3e: 61 00 + 40: 2e 62 + 42: 73 73 00 2e csrrci t1, 736, 0 + 46: 63 6f 6d 6d bltu s10, s6, 1758 + 4a: 65 6e + 4c: 74 00 + 4e: 2e 72 + 50: 69 73 + 52: 63 76 2e 61 bgeu t3, s2, 1548 + 56: 74 74 + 58: 72 69 + 5a: 62 75 + 5c: 74 65 + 5e: 73 + 5f: 00 diff --git a/tests/opencl/psort/psorti.dump b/tests/opencl/psort/psorti.dump new file mode 100644 index 00000000..593919f5 --- /dev/null +++ b/tests/opencl/psort/psorti.dump @@ -0,0 +1,1784 @@ + +/tmp/pocl_vortex_kernel-07-0e-3f-a5-12.elf: file format ELF32-riscv + + +Disassembly of section .init: + +80000000 _start: +80000000: 97 05 00 00 auipc a1, 0 +80000004: 93 85 05 3f addi a1, a1, 1008 +80000008: 73 25 10 fc csrr a0, 4033 +8000000c: 6b 10 b5 00 vx_wspawn a0, a1 +80000010: ef 00 00 3e jal 992 +80000014: 13 05 10 00 addi a0, zero, 1 +80000018: 6b 00 05 00 vx_tmc a0 +8000001c: 17 15 00 00 auipc a0, 1 +80000020: 13 05 85 41 addi a0, a0, 1048 +80000024: 17 16 00 00 auipc a2, 1 +80000028: 13 06 06 49 addi a2, a2, 1168 +8000002c: 33 06 a6 40 sub a2, a2, a0 +80000030: 93 05 00 00 mv a1, zero +80000034: ef 00 50 30 jal 2820 +80000038: 17 05 00 00 auipc a0, 0 +8000003c: 13 05 85 48 addi a0, a0, 1160 +80000040: ef 00 10 2b jal 2736 +80000044: ef 00 00 3e jal 992 +80000048: ef 00 00 02 jal 32 +8000004c: 6f 00 90 2b j 2744 + +Disassembly of section .text: + +80000050 register_fini: +80000050: 93 07 00 00 mv a5, zero +80000054: 63 88 07 00 beqz a5, 16 +80000058: 37 05 00 80 lui a0, 524288 +8000005c: 13 05 05 4c addi a0, a0, 1216 +80000060: 6f 00 10 29 j 2704 +80000064: 67 80 00 00 ret + +80000068 main: +80000068: 13 01 01 ff addi sp, sp, -16 +8000006c: 23 26 11 00 sw ra, 12(sp) +80000070: 37 05 00 80 lui a0, 524288 +80000074: 93 05 85 1b addi a1, a0, 440 +80000078: 37 05 ff 7f lui a0, 524272 +8000007c: 13 06 45 03 addi a2, a0, 52 +80000080: 37 05 ff 7f lui a0, 524272 +80000084: ef 00 40 6a jal 1700 +80000088: 13 05 00 00 mv a0, zero +8000008c: 83 20 c1 00 lw ra, 12(sp) +80000090: 13 01 01 01 addi sp, sp, 16 +80000094: 67 80 00 00 ret + +80000098 _pocl_kernel_psorti: +80000098: 13 01 01 fe addi sp, sp, -32 +8000009c: 23 2e 11 00 sw ra, 28(sp) +800000a0: 23 2c 81 00 sw s0, 24(sp) +800000a4: 23 2a 91 00 sw s1, 20(sp) +800000a8: 23 28 21 01 sw s2, 16(sp) +800000ac: 23 26 31 01 sw s3, 12(sp) +800000b0: 23 24 41 01 sw s4, 8(sp) +800000b4: 13 04 01 02 addi s0, sp, 32 +800000b8: 13 71 c1 ff andi sp, sp, -4 +800000bc: 13 08 00 00 mv a6, zero +800000c0: 83 2e 86 01 lw t4, 24(a2) +800000c4: 03 23 c6 01 lw t1, 28(a2) +800000c8: 03 27 c6 00 lw a4, 12(a2) +800000cc: 83 27 06 00 lw a5, 0(a2) +800000d0: 83 28 06 02 lw a7, 32(a2) +800000d4: 33 86 de 02 mul a2, t4, a3 +800000d8: 33 0e c7 00 add t3, a4, a2 +800000dc: b3 8f d7 03 mul t6, a5, t4 +800000e0: 13 16 2e 00 slli a2, t3, 2 +800000e4: b3 02 c5 00 add t0, a0, a2 +800000e8: 6f 00 c0 00 j 12 +800000ec: 13 08 18 00 addi a6, a6, 1 +800000f0: 63 72 18 0b bgeu a6, a7, 164 +800000f4: 63 5a f0 07 blez t6, 116 +800000f8: 93 03 00 00 mv t2, zero +800000fc: 13 0f 00 00 mv t5, zero +80000100: 33 09 ee 01 add s2, t3, t5 +80000104: 13 16 29 00 slli a2, s2, 2 +80000108: 33 06 c5 00 add a2, a0, a2 +8000010c: 83 29 06 00 lw s3, 0(a2) +80000110: 13 06 00 00 mv a2, zero +80000114: 13 07 00 00 mv a4, zero +80000118: 93 04 05 00 mv s1, a0 +8000011c: 83 a7 04 00 lw a5, 0(s1) +80000120: 33 aa 37 01 slt s4, a5, s3 +80000124: b3 c7 37 01 xor a5, a5, s3 +80000128: 93 b7 17 00 seqz a5, a5 +8000012c: b3 26 26 01 slt a3, a2, s2 +80000130: b3 f6 f6 00 and a3, a3, a5 +80000134: b3 66 da 00 or a3, s4, a3 +80000138: 33 07 d7 00 add a4, a4, a3 +8000013c: 13 06 16 00 addi a2, a2, 1 +80000140: 93 84 44 00 addi s1, s1, 4 +80000144: e3 9c cf fc bne t6, a2, -40 +80000148: 13 16 27 00 slli a2, a4, 2 +8000014c: 33 86 c5 00 add a2, a1, a2 +80000150: 13 0f 1f 00 addi t5, t5, 1 +80000154: 23 20 36 01 sw s3, 0(a2) +80000158: e3 64 df fb bltu t5, t4, -88 +8000015c: 93 83 13 00 addi t2, t2, 1 +80000160: e3 ee 63 f8 bltu t2, t1, -100 +80000164: 6f f0 9f f8 j -120 +80000168: 93 06 00 00 mv a3, zero +8000016c: 13 06 00 00 mv a2, zero +80000170: 13 87 02 00 mv a4, t0 +80000174: 83 27 07 00 lw a5, 0(a4) +80000178: 23 a0 f5 00 sw a5, 0(a1) +8000017c: 13 06 16 00 addi a2, a2, 1 +80000180: 13 07 47 00 addi a4, a4, 4 +80000184: e3 68 d6 ff bltu a2, t4, -16 +80000188: 93 86 16 00 addi a3, a3, 1 +8000018c: e3 e0 66 fe bltu a3, t1, -32 +80000190: 6f f0 df f5 j -164 +80000194: 13 01 04 fe addi sp, s0, -32 +80000198: 03 2a 81 00 lw s4, 8(sp) +8000019c: 83 29 c1 00 lw s3, 12(sp) +800001a0: 03 29 01 01 lw s2, 16(sp) +800001a4: 83 24 41 01 lw s1, 20(sp) +800001a8: 03 24 81 01 lw s0, 24(sp) +800001ac: 83 20 c1 01 lw ra, 28(sp) +800001b0: 13 01 01 02 addi sp, sp, 32 +800001b4: 67 80 00 00 ret + +800001b8 _pocl_kernel_psorti_workgroup: +800001b8: 13 01 01 ff addi sp, sp, -16 +800001bc: 23 26 81 00 sw s0, 12(sp) +800001c0: 23 24 91 00 sw s1, 8(sp) +800001c4: 23 22 21 01 sw s2, 4(sp) +800001c8: 23 20 31 01 sw s3, 0(sp) +800001cc: 83 26 05 00 lw a3, 0(a0) +800001d0: 03 25 45 00 lw a0, 4(a0) +800001d4: 13 08 00 00 mv a6, zero +800001d8: 83 af 06 00 lw t6, 0(a3) +800001dc: 83 2e 05 00 lw t4, 0(a0) +800001e0: 03 af 85 01 lw t5, 24(a1) +800001e4: 03 a3 c5 01 lw t1, 28(a1) +800001e8: 03 a5 c5 00 lw a0, 12(a1) +800001ec: 83 a6 05 00 lw a3, 0(a1) +800001f0: 83 a8 05 02 lw a7, 32(a1) +800001f4: b3 05 cf 02 mul a1, t5, a2 +800001f8: 33 0e b5 00 add t3, a0, a1 +800001fc: b3 89 e6 03 mul s3, a3, t5 +80000200: 13 15 2e 00 slli a0, t3, 2 +80000204: b3 82 af 00 add t0, t6, a0 +80000208: 6f 00 c0 00 j 12 +8000020c: 13 08 18 00 addi a6, a6, 1 +80000210: 63 72 18 0b bgeu a6, a7, 164 +80000214: 63 5a 30 07 blez s3, 116 +80000218: 93 03 00 00 mv t2, zero +8000021c: 13 09 00 00 mv s2, zero +80000220: 33 07 2e 01 add a4, t3, s2 +80000224: 13 16 27 00 slli a2, a4, 2 +80000228: 33 86 cf 00 add a2, t6, a2 +8000022c: 03 26 06 00 lw a2, 0(a2) +80000230: 93 06 00 00 mv a3, zero +80000234: 93 07 00 00 mv a5, zero +80000238: 13 84 0f 00 mv s0, t6 +8000023c: 83 24 04 00 lw s1, 0(s0) +80000240: 33 a5 c4 00 slt a0, s1, a2 +80000244: b3 c4 c4 00 xor s1, s1, a2 +80000248: 93 b4 14 00 seqz s1, s1 +8000024c: b3 a5 e6 00 slt a1, a3, a4 +80000250: b3 f5 95 00 and a1, a1, s1 +80000254: 33 65 b5 00 or a0, a0, a1 +80000258: b3 87 a7 00 add a5, a5, a0 +8000025c: 93 86 16 00 addi a3, a3, 1 +80000260: 13 04 44 00 addi s0, s0, 4 +80000264: e3 9c d9 fc bne s3, a3, -40 +80000268: 93 96 27 00 slli a3, a5, 2 +8000026c: b3 86 de 00 add a3, t4, a3 +80000270: 13 09 19 00 addi s2, s2, 1 +80000274: 23 a0 c6 00 sw a2, 0(a3) +80000278: e3 64 e9 fb bltu s2, t5, -88 +8000027c: 93 83 13 00 addi t2, t2, 1 +80000280: e3 ee 63 f8 bltu t2, t1, -100 +80000284: 6f f0 9f f8 j -120 +80000288: 13 05 00 00 mv a0, zero +8000028c: 13 06 00 00 mv a2, zero +80000290: 93 86 02 00 mv a3, t0 +80000294: 83 a5 06 00 lw a1, 0(a3) +80000298: 23 a0 be 00 sw a1, 0(t4) +8000029c: 13 06 16 00 addi a2, a2, 1 +800002a0: 93 86 46 00 addi a3, a3, 4 +800002a4: e3 68 e6 ff bltu a2, t5, -16 +800002a8: 13 05 15 00 addi a0, a0, 1 +800002ac: e3 60 65 fe bltu a0, t1, -32 +800002b0: 6f f0 df f5 j -164 +800002b4: 83 29 01 00 lw s3, 0(sp) +800002b8: 03 29 41 00 lw s2, 4(sp) +800002bc: 83 24 81 00 lw s1, 8(sp) +800002c0: 03 24 c1 00 lw s0, 12(sp) +800002c4: 13 01 01 01 addi sp, sp, 16 +800002c8: 67 80 00 00 ret + +800002cc _pocl_kernel_psorti_workgroup_fast: +800002cc: 13 01 01 ff addi sp, sp, -16 +800002d0: 23 26 81 00 sw s0, 12(sp) +800002d4: 23 24 91 00 sw s1, 8(sp) +800002d8: 23 22 21 01 sw s2, 4(sp) +800002dc: 23 20 31 01 sw s3, 0(sp) +800002e0: 13 08 00 00 mv a6, zero +800002e4: 83 2f 05 00 lw t6, 0(a0) +800002e8: 83 2e 45 00 lw t4, 4(a0) +800002ec: 03 af 85 01 lw t5, 24(a1) +800002f0: 03 a3 c5 01 lw t1, 28(a1) +800002f4: 03 a5 c5 00 lw a0, 12(a1) +800002f8: 83 a6 05 00 lw a3, 0(a1) +800002fc: 83 a8 05 02 lw a7, 32(a1) +80000300: b3 05 cf 02 mul a1, t5, a2 +80000304: 33 0e b5 00 add t3, a0, a1 +80000308: b3 89 e6 03 mul s3, a3, t5 +8000030c: 13 15 2e 00 slli a0, t3, 2 +80000310: b3 82 af 00 add t0, t6, a0 +80000314: 6f 00 c0 00 j 12 +80000318: 13 08 18 00 addi a6, a6, 1 +8000031c: 63 72 18 0b bgeu a6, a7, 164 +80000320: 63 5a 30 07 blez s3, 116 +80000324: 93 03 00 00 mv t2, zero +80000328: 13 09 00 00 mv s2, zero +8000032c: 33 05 2e 01 add a0, t3, s2 +80000330: 13 16 25 00 slli a2, a0, 2 +80000334: 33 86 cf 00 add a2, t6, a2 +80000338: 03 26 06 00 lw a2, 0(a2) +8000033c: 13 07 00 00 mv a4, zero +80000340: 93 07 00 00 mv a5, zero +80000344: 13 84 0f 00 mv s0, t6 +80000348: 83 24 04 00 lw s1, 0(s0) +8000034c: b3 a6 c4 00 slt a3, s1, a2 +80000350: b3 c4 c4 00 xor s1, s1, a2 +80000354: 93 b4 14 00 seqz s1, s1 +80000358: b3 25 a7 00 slt a1, a4, a0 +8000035c: b3 f5 95 00 and a1, a1, s1 +80000360: b3 e5 b6 00 or a1, a3, a1 +80000364: b3 87 b7 00 add a5, a5, a1 +80000368: 13 07 17 00 addi a4, a4, 1 +8000036c: 13 04 44 00 addi s0, s0, 4 +80000370: e3 9c e9 fc bne s3, a4, -40 +80000374: 13 95 27 00 slli a0, a5, 2 +80000378: 33 85 ae 00 add a0, t4, a0 +8000037c: 13 09 19 00 addi s2, s2, 1 +80000380: 23 20 c5 00 sw a2, 0(a0) +80000384: e3 64 e9 fb bltu s2, t5, -88 +80000388: 93 83 13 00 addi t2, t2, 1 +8000038c: e3 ee 63 f8 bltu t2, t1, -100 +80000390: 6f f0 9f f8 j -120 +80000394: 13 05 00 00 mv a0, zero +80000398: 13 06 00 00 mv a2, zero +8000039c: 93 86 02 00 mv a3, t0 +800003a0: 83 a5 06 00 lw a1, 0(a3) +800003a4: 23 a0 be 00 sw a1, 0(t4) +800003a8: 13 06 16 00 addi a2, a2, 1 +800003ac: 93 86 46 00 addi a3, a3, 4 +800003b0: e3 68 e6 ff bltu a2, t5, -16 +800003b4: 13 05 15 00 addi a0, a0, 1 +800003b8: e3 60 65 fe bltu a0, t1, -32 +800003bc: 6f f0 df f5 j -164 +800003c0: 83 29 01 00 lw s3, 0(sp) +800003c4: 03 29 41 00 lw s2, 4(sp) +800003c8: 83 24 81 00 lw s1, 8(sp) +800003cc: 03 24 c1 00 lw s0, 12(sp) +800003d0: 13 01 01 01 addi sp, sp, 16 +800003d4: 67 80 00 00 ret + +800003d8 _exit: +800003d8: 63 06 05 00 beqz a0, 12 +800003dc: 93 01 05 00 mv gp, a0 +800003e0: 73 00 00 00 ecall + +800003e4 label_exit_next: +800003e4: ef 00 80 4f jal 1272 +800003e8: 13 05 00 00 mv a0, zero +800003ec: 6b 00 05 00 vx_tmc a0 + +800003f0 vx_set_sp: +800003f0: 13 05 f0 ff addi a0, zero, -1 +800003f4: 6b 00 05 00 vx_tmc a0 +800003f8: 97 11 00 00 auipc gp, 1 +800003fc: 93 81 01 41 addi gp, gp, 1040 +80000400: 37 01 00 ff lui sp, 1044480 +80000404: 73 26 10 cc csrr a2, 3265 +80000408: 93 15 a6 00 slli a1, a2, 10 +8000040c: 33 01 b1 40 sub sp, sp, a1 +80000410: f3 26 30 cc csrr a3, 3267 +80000414: 63 86 06 00 beqz a3, 12 +80000418: 13 05 00 00 mv a0, zero +8000041c: 6b 00 05 00 vx_tmc a0 + +80000420 RETURN: +80000420: 67 80 00 00 ret + +80000424 __libc_init_array: +80000424: 13 01 01 ff addi sp, sp, -16 +80000428: 23 24 81 00 sw s0, 8(sp) +8000042c: 23 20 21 01 sw s2, 0(sp) +80000430: 37 14 00 80 lui s0, 524289 +80000434: 37 19 00 80 lui s2, 524289 +80000438: 93 07 04 00 mv a5, s0 +8000043c: 13 09 09 00 mv s2, s2 +80000440: 33 09 f9 40 sub s2, s2, a5 +80000444: 23 26 11 00 sw ra, 12(sp) +80000448: 23 22 91 00 sw s1, 4(sp) +8000044c: 13 59 29 40 srai s2, s2, 2 +80000450: 63 00 09 02 beqz s2, 32 +80000454: 13 04 04 00 mv s0, s0 +80000458: 93 04 00 00 mv s1, zero +8000045c: 83 27 04 00 lw a5, 0(s0) +80000460: 93 84 14 00 addi s1, s1, 1 +80000464: 13 04 44 00 addi s0, s0, 4 +80000468: e7 80 07 00 jalr a5 +8000046c: e3 18 99 fe bne s2, s1, -16 +80000470: 37 14 00 80 lui s0, 524289 +80000474: 37 19 00 80 lui s2, 524289 +80000478: 93 07 04 00 mv a5, s0 +8000047c: 13 09 49 00 addi s2, s2, 4 +80000480: 33 09 f9 40 sub s2, s2, a5 +80000484: 13 59 29 40 srai s2, s2, 2 +80000488: 63 00 09 02 beqz s2, 32 +8000048c: 13 04 04 00 mv s0, s0 +80000490: 93 04 00 00 mv s1, zero +80000494: 83 27 04 00 lw a5, 0(s0) +80000498: 93 84 14 00 addi s1, s1, 1 +8000049c: 13 04 44 00 addi s0, s0, 4 +800004a0: e7 80 07 00 jalr a5 +800004a4: e3 18 99 fe bne s2, s1, -16 +800004a8: 83 20 c1 00 lw ra, 12(sp) +800004ac: 03 24 81 00 lw s0, 8(sp) +800004b0: 83 24 41 00 lw s1, 4(sp) +800004b4: 03 29 01 00 lw s2, 0(sp) +800004b8: 13 01 01 01 addi sp, sp, 16 +800004bc: 67 80 00 00 ret + +800004c0 __libc_fini_array: +800004c0: 13 01 01 ff addi sp, sp, -16 +800004c4: 23 24 81 00 sw s0, 8(sp) +800004c8: b7 17 00 80 lui a5, 524289 +800004cc: 37 14 00 80 lui s0, 524289 +800004d0: 13 04 44 00 addi s0, s0, 4 +800004d4: 93 87 47 00 addi a5, a5, 4 +800004d8: b3 87 87 40 sub a5, a5, s0 +800004dc: 23 22 91 00 sw s1, 4(sp) +800004e0: 23 26 11 00 sw ra, 12(sp) +800004e4: 93 d4 27 40 srai s1, a5, 2 +800004e8: 63 80 04 02 beqz s1, 32 +800004ec: 93 87 c7 ff addi a5, a5, -4 +800004f0: 33 84 87 00 add s0, a5, s0 +800004f4: 83 27 04 00 lw a5, 0(s0) +800004f8: 93 84 f4 ff addi s1, s1, -1 +800004fc: 13 04 c4 ff addi s0, s0, -4 +80000500: e7 80 07 00 jalr a5 +80000504: e3 98 04 fe bnez s1, -16 +80000508: 83 20 c1 00 lw ra, 12(sp) +8000050c: 03 24 81 00 lw s0, 8(sp) +80000510: 83 24 41 00 lw s1, 4(sp) +80000514: 13 01 01 01 addi sp, sp, 16 +80000518: 67 80 00 00 ret + +8000051c spawn_kernel_all_stub: +8000051c: 13 01 01 fe addi sp, sp, -32 +80000520: 23 2e 11 00 sw ra, 28(sp) +80000524: 23 2c 81 00 sw s0, 24(sp) +80000528: 23 2a 91 00 sw s1, 20(sp) +8000052c: 23 28 21 01 sw s2, 16(sp) +80000530: 23 26 31 01 sw s3, 12(sp) +80000534: 23 24 41 01 sw s4, 8(sp) +80000538: 73 26 50 cc csrr a2, 3269 +8000053c: 73 27 30 cc csrr a4, 3267 +80000540: f3 26 00 cc csrr a3, 3264 +80000544: 73 25 00 fc csrr a0, 4032 +80000548: b7 17 00 80 lui a5, 524289 +8000054c: 13 16 26 00 slli a2, a2, 2 +80000550: 93 87 47 43 addi a5, a5, 1076 +80000554: b3 87 c7 00 add a5, a5, a2 +80000558: 03 a4 07 00 lw s0, 0(a5) +8000055c: 83 24 44 01 lw s1, 20(s0) +80000560: 03 26 04 01 lw a2, 16(s0) +80000564: 33 2a 97 00 slt s4, a4, s1 +80000568: 93 87 04 00 mv a5, s1 +8000056c: 33 0a ca 00 add s4, s4, a2 +80000570: b3 04 e6 02 mul s1, a2, a4 +80000574: 63 54 f7 00 bge a4, a5, 8 +80000578: 93 07 07 00 mv a5, a4 +8000057c: b3 84 f4 00 add s1, s1, a5 +80000580: 83 25 04 00 lw a1, 0(s0) +80000584: 03 27 c4 00 lw a4, 12(s0) +80000588: 03 a9 05 00 lw s2, 0(a1) +8000058c: 83 a9 45 00 lw s3, 4(a1) +80000590: b3 84 a4 02 mul s1, s1, a0 +80000594: b3 07 da 02 mul a5, s4, a3 +80000598: b3 84 e4 00 add s1, s1, a4 +8000059c: b3 84 f4 00 add s1, s1, a5 +800005a0: 33 0a 9a 00 add s4, s4, s1 +800005a4: b3 09 39 03 mul s3, s2, s3 +800005a8: 63 c0 44 07 blt s1, s4, 96 +800005ac: 6f 00 00 08 j 128 +800005b0: 03 47 e4 01 lbu a4, 30(s0) +800005b4: 83 46 d4 01 lbu a3, 29(s0) +800005b8: 33 d7 e4 40 sra a4, s1, a4 +800005bc: b3 07 37 03 mul a5, a4, s3 +800005c0: b3 87 f4 40 sub a5, s1, a5 +800005c4: 63 80 06 06 beqz a3, 96 +800005c8: 83 46 f4 01 lbu a3, 31(s0) +800005cc: b3 d6 d7 40 sra a3, a5, a3 +800005d0: b3 88 26 03 mul a7, a3, s2 +800005d4: 03 ae 45 01 lw t3, 20(a1) +800005d8: 03 a3 05 01 lw t1, 16(a1) +800005dc: 03 a6 c5 00 lw a2, 12(a1) +800005e0: 03 28 44 00 lw a6, 4(s0) +800005e4: 03 25 84 00 lw a0, 8(s0) +800005e8: 93 84 14 00 addi s1, s1, 1 +800005ec: 33 07 c7 01 add a4, a4, t3 +800005f0: b3 86 66 00 add a3, a3, t1 +800005f4: b3 87 17 41 sub a5, a5, a7 +800005f8: 33 86 c7 00 add a2, a5, a2 +800005fc: e7 00 08 00 jalr a6 +80000600: 63 06 9a 02 beq s4, s1, 44 +80000604: 83 25 04 00 lw a1, 0(s0) +80000608: 83 47 c4 01 lbu a5, 28(s0) +8000060c: e3 92 07 fa bnez a5, -92 +80000610: 33 c7 34 03 div a4, s1, s3 +80000614: 83 46 d4 01 lbu a3, 29(s0) +80000618: b3 07 37 03 mul a5, a4, s3 +8000061c: b3 87 f4 40 sub a5, s1, a5 +80000620: e3 94 06 fa bnez a3, -88 +80000624: b3 c6 27 03 div a3, a5, s2 +80000628: 6f f0 9f fa j -88 +8000062c: 03 27 84 01 lw a4, 24(s0) +80000630: 93 07 00 00 mv a5, zero +80000634: 6b c0 e7 00 vx_bar a5, a4 +80000638: 83 20 c1 01 lw ra, 28(sp) +8000063c: 03 24 81 01 lw s0, 24(sp) +80000640: 83 24 41 01 lw s1, 20(sp) +80000644: 03 29 01 01 lw s2, 16(sp) +80000648: 83 29 c1 00 lw s3, 12(sp) +8000064c: 03 2a 81 00 lw s4, 8(sp) +80000650: 13 01 01 02 addi sp, sp, 32 +80000654: 67 80 00 00 ret + +80000658 spawn_kernel_rem_stub: +80000658: f3 26 50 cc csrr a3, 3269 +8000065c: f3 27 20 cc csrr a5, 3266 +80000660: 37 17 00 80 lui a4, 524289 +80000664: 93 96 26 00 slli a3, a3, 2 +80000668: 13 07 47 43 addi a4, a4, 1076 +8000066c: 33 07 d7 00 add a4, a4, a3 +80000670: 03 25 07 00 lw a0, 0(a4) +80000674: 83 25 05 00 lw a1, 0(a0) +80000678: 83 26 c5 00 lw a3, 12(a0) +8000067c: 03 47 c5 01 lbu a4, 28(a0) +80000680: 83 a8 05 00 lw a7, 0(a1) +80000684: 03 a6 45 00 lw a2, 4(a1) +80000688: b3 87 d7 00 add a5, a5, a3 +8000068c: 33 86 c8 02 mul a2, a7, a2 +80000690: 63 08 07 04 beqz a4, 80 +80000694: 03 47 e5 01 lbu a4, 30(a0) +80000698: 83 46 d5 01 lbu a3, 29(a0) +8000069c: 33 d7 e7 40 sra a4, a5, a4 +800006a0: 33 06 c7 02 mul a2, a4, a2 +800006a4: b3 87 c7 40 sub a5, a5, a2 +800006a8: 63 86 06 04 beqz a3, 76 +800006ac: 83 46 f5 01 lbu a3, 31(a0) +800006b0: 33 d8 d7 40 sra a6, a5, a3 +800006b4: 83 a6 05 01 lw a3, 16(a1) +800006b8: 03 ae 45 01 lw t3, 20(a1) +800006bc: 03 a6 c5 00 lw a2, 12(a1) +800006c0: b3 06 d8 00 add a3, a6, a3 +800006c4: 33 08 18 03 mul a6, a6, a7 +800006c8: 03 23 45 00 lw t1, 4(a0) +800006cc: 03 25 85 00 lw a0, 8(a0) +800006d0: 33 07 c7 01 add a4, a4, t3 +800006d4: b3 87 07 41 sub a5, a5, a6 +800006d8: 33 86 c7 00 add a2, a5, a2 +800006dc: 67 00 03 00 jr t1 +800006e0: 33 c7 c7 02 div a4, a5, a2 +800006e4: 83 46 d5 01 lbu a3, 29(a0) +800006e8: 33 06 c7 02 mul a2, a4, a2 +800006ec: b3 87 c7 40 sub a5, a5, a2 +800006f0: e3 9e 06 fa bnez a3, -68 +800006f4: 33 c8 17 03 div a6, a5, a7 +800006f8: 6f f0 df fb j -68 + +800006fc spawn_kernel_all_cb: +800006fc: 13 01 01 ff addi sp, sp, -16 +80000700: 23 26 11 00 sw ra, 12(sp) +80000704: 93 07 f0 ff addi a5, zero, -1 +80000708: 6b 80 07 00 vx_tmc a5 +8000070c: ef f0 1f e1 jal -496 +80000710: f3 27 30 cc csrr a5, 3267 +80000714: 93 b7 17 00 seqz a5, a5 +80000718: 6b 80 07 00 vx_tmc a5 +8000071c: 83 20 c1 00 lw ra, 12(sp) +80000720: 13 01 01 01 addi sp, sp, 16 +80000724: 67 80 00 00 ret + +80000728 vx_spawn_kernel: +80000728: 13 01 01 fd addi sp, sp, -48 +8000072c: 23 26 11 02 sw ra, 44(sp) +80000730: 23 24 81 02 sw s0, 40(sp) +80000734: 23 22 91 02 sw s1, 36(sp) +80000738: 23 20 21 03 sw s2, 32(sp) +8000073c: f3 28 20 fc csrr a7, 4034 +80000740: 73 23 10 fc csrr t1, 4033 +80000744: f3 24 00 fc csrr s1, 4032 +80000748: f3 27 50 cc csrr a5, 3269 +8000074c: 13 07 f0 01 addi a4, zero, 31 +80000750: 63 46 f7 0e blt a4, a5, 236 +80000754: 03 2e 05 00 lw t3, 0(a0) +80000758: 83 26 45 00 lw a3, 4(a0) +8000075c: 03 28 85 00 lw a6, 8(a0) +80000760: b3 0e 93 02 mul t4, t1, s1 +80000764: 13 07 10 00 addi a4, zero, 1 +80000768: b3 06 de 02 mul a3, t3, a3 +8000076c: 33 88 06 03 mul a6, a3, a6 +80000770: 63 d4 0e 01 bge t4, a6, 8 +80000774: 33 47 d8 03 div a4, a6, t4 +80000778: 63 ce e8 0c blt a7, a4, 220 +8000077c: 63 d0 e7 0c bge a5, a4, 192 +80000780: 93 88 f8 ff addi a7, a7, -1 +80000784: b3 4e e8 02 div t4, a6, a4 +80000788: 13 84 0e 00 mv s0, t4 +8000078c: 63 96 f8 00 bne a7, a5, 12 +80000790: 33 67 e8 02 rem a4, a6, a4 +80000794: 33 04 d7 01 add s0, a4, t4 +80000798: 33 49 94 02 div s2, s0, s1 +8000079c: 33 64 94 02 rem s0, s0, s1 +800007a0: 63 40 69 0c blt s2, t1, 192 +800007a4: 93 0f 10 00 addi t6, zero, 1 +800007a8: 33 4f 69 02 div t5, s2, t1 +800007ac: 63 06 0f 00 beqz t5, 12 +800007b0: 93 0f 0f 00 mv t6, t5 +800007b4: 33 6f 69 02 rem t5, s2, t1 +800007b8: d3 f7 06 d0 fcvt.s.w fa5, a3 +800007bc: 13 07 fe ff addi a4, t3, -1 +800007c0: 93 82 f6 ff addi t0, a3, -1 +800007c4: d3 88 07 e0 fmv.x.w a7, fa5 +800007c8: d3 77 0e d0 fcvt.s.w fa5, t3 +800007cc: 33 7e c7 01 and t3, a4, t3 +800007d0: 37 17 00 80 lui a4, 524289 +800007d4: 53 88 07 e0 fmv.x.w a6, fa5 +800007d8: b3 f6 d2 00 and a3, t0, a3 +800007dc: 93 d8 78 41 srai a7, a7, 23 +800007e0: 13 58 78 41 srai a6, a6, 23 +800007e4: 13 07 47 43 addi a4, a4, 1076 +800007e8: 93 b6 16 00 seqz a3, a3 +800007ec: 13 3e 1e 00 seqz t3, t3 +800007f0: 93 88 18 f8 addi a7, a7, -127 +800007f4: 13 08 18 f8 addi a6, a6, -127 +800007f8: 23 20 a1 00 sw a0, 0(sp) +800007fc: 23 22 b1 00 sw a1, 4(sp) +80000800: 23 24 c1 00 sw a2, 8(sp) +80000804: 23 28 f1 01 sw t6, 16(sp) +80000808: 23 2a e1 01 sw t5, 20(sp) +8000080c: 23 2c 01 00 sw zero, 24(sp) +80000810: 23 0e d1 00 sb a3, 28(sp) +80000814: a3 0e c1 01 sb t3, 29(sp) +80000818: 23 0f 11 01 sb a7, 30(sp) +8000081c: a3 0f 01 01 sb a6, 31(sp) +80000820: b3 8e fe 02 mul t4, t4, a5 +80000824: 93 97 27 00 slli a5, a5, 2 +80000828: b3 07 f7 00 add a5, a4, a5 +8000082c: 23 a0 27 00 sw sp, 0(a5) +80000830: 23 26 d1 01 sw t4, 12(sp) +80000834: 63 4c 20 03 bgtz s2, 56 +80000838: 63 16 04 06 bnez s0, 108 +8000083c: 83 20 c1 02 lw ra, 44(sp) +80000840: 03 24 81 02 lw s0, 40(sp) +80000844: 83 24 41 02 lw s1, 36(sp) +80000848: 03 29 01 02 lw s2, 32(sp) +8000084c: 13 01 01 03 addi sp, sp, 48 +80000850: 67 80 00 00 ret +80000854: 13 87 08 00 mv a4, a7 +80000858: e3 c4 e7 f2 blt a5, a4, -216 +8000085c: 6f f0 1f fe j -32 +80000860: 13 0f 00 00 mv t5, zero +80000864: 93 0f 10 00 addi t6, zero, 1 +80000868: 6f f0 1f f5 j -176 +8000086c: 13 07 09 00 mv a4, s2 +80000870: 63 54 23 01 bge t1, s2, 8 +80000874: 13 07 03 00 mv a4, t1 +80000878: b7 07 00 80 lui a5, 524288 +8000087c: 23 2c e1 00 sw a4, 24(sp) +80000880: 93 87 c7 6f addi a5, a5, 1788 +80000884: 6b 10 f7 00 vx_wspawn a4, a5 +80000888: 93 07 f0 ff addi a5, zero, -1 +8000088c: 6b 80 07 00 vx_tmc a5 +80000890: ef f0 df c8 jal -884 +80000894: f3 27 30 cc csrr a5, 3267 +80000898: 93 b7 17 00 seqz a5, a5 +8000089c: 6b 80 07 00 vx_tmc a5 +800008a0: e3 0e 04 f8 beqz s0, -100 +800008a4: b3 04 99 02 mul s1, s2, s1 +800008a8: 13 09 10 00 addi s2, zero, 1 +800008ac: 33 14 89 00 sll s0, s2, s0 +800008b0: 13 04 f4 ff addi s0, s0, -1 +800008b4: 23 26 91 00 sw s1, 12(sp) +800008b8: 6b 00 04 00 vx_tmc s0 +800008bc: ef f0 df d9 jal -612 +800008c0: 6b 00 09 00 vx_tmc s2 +800008c4: 83 20 c1 02 lw ra, 44(sp) +800008c8: 03 24 81 02 lw s0, 40(sp) +800008cc: 83 24 41 02 lw s1, 36(sp) +800008d0: 03 29 01 02 lw s2, 32(sp) +800008d4: 13 01 01 03 addi sp, sp, 48 +800008d8: 67 80 00 00 ret + +800008dc vx_perf_dump: +800008dc: f3 27 50 cc csrr a5, 3269 +800008e0: 37 07 ff 00 lui a4, 4080 +800008e4: b3 87 e7 00 add a5, a5, a4 +800008e8: 93 97 87 00 slli a5, a5, 8 +800008ec: 73 27 00 b0 csrr a4, mcycle +800008f0: 23 a0 e7 00 sw a4, 0(a5) +800008f4: 73 27 10 b0 csrr a4, 2817 +800008f8: 23 a2 e7 00 sw a4, 4(a5) +800008fc: 73 27 20 b0 csrr a4, minstret +80000900: 23 a4 e7 00 sw a4, 8(a5) +80000904: 73 27 30 b0 csrr a4, mhpmcounter3 +80000908: 23 a6 e7 00 sw a4, 12(a5) +8000090c: 73 27 40 b0 csrr a4, mhpmcounter4 +80000910: 23 a8 e7 00 sw a4, 16(a5) +80000914: 73 27 50 b0 csrr a4, mhpmcounter5 +80000918: 23 aa e7 00 sw a4, 20(a5) +8000091c: 73 27 60 b0 csrr a4, mhpmcounter6 +80000920: 23 ac e7 00 sw a4, 24(a5) +80000924: 73 27 70 b0 csrr a4, mhpmcounter7 +80000928: 23 ae e7 00 sw a4, 28(a5) +8000092c: 73 27 80 b0 csrr a4, mhpmcounter8 +80000930: 23 a0 e7 02 sw a4, 32(a5) +80000934: 73 27 90 b0 csrr a4, mhpmcounter9 +80000938: 23 a2 e7 02 sw a4, 36(a5) +8000093c: 73 27 a0 b0 csrr a4, mhpmcounter10 +80000940: 23 a4 e7 02 sw a4, 40(a5) +80000944: 73 27 b0 b0 csrr a4, mhpmcounter11 +80000948: 23 a6 e7 02 sw a4, 44(a5) +8000094c: 73 27 c0 b0 csrr a4, mhpmcounter12 +80000950: 23 a8 e7 02 sw a4, 48(a5) +80000954: 73 27 d0 b0 csrr a4, mhpmcounter13 +80000958: 23 aa e7 02 sw a4, 52(a5) +8000095c: 73 27 e0 b0 csrr a4, mhpmcounter14 +80000960: 23 ac e7 02 sw a4, 56(a5) +80000964: 73 27 f0 b0 csrr a4, mhpmcounter15 +80000968: 23 ae e7 02 sw a4, 60(a5) +8000096c: 73 27 00 b1 csrr a4, mhpmcounter16 +80000970: 23 a0 e7 04 sw a4, 64(a5) +80000974: 73 27 10 b1 csrr a4, mhpmcounter17 +80000978: 23 a2 e7 04 sw a4, 68(a5) +8000097c: 73 27 20 b1 csrr a4, mhpmcounter18 +80000980: 23 a4 e7 04 sw a4, 72(a5) +80000984: 73 27 30 b1 csrr a4, mhpmcounter19 +80000988: 23 a6 e7 04 sw a4, 76(a5) +8000098c: 73 27 40 b1 csrr a4, mhpmcounter20 +80000990: 23 a8 e7 04 sw a4, 80(a5) +80000994: 73 27 50 b1 csrr a4, mhpmcounter21 +80000998: 23 aa e7 04 sw a4, 84(a5) +8000099c: 73 27 60 b1 csrr a4, mhpmcounter22 +800009a0: 23 ac e7 04 sw a4, 88(a5) +800009a4: 73 27 70 b1 csrr a4, mhpmcounter23 +800009a8: 23 ae e7 04 sw a4, 92(a5) +800009ac: 73 27 80 b1 csrr a4, mhpmcounter24 +800009b0: 23 a0 e7 06 sw a4, 96(a5) +800009b4: 73 27 90 b1 csrr a4, mhpmcounter25 +800009b8: 23 a2 e7 06 sw a4, 100(a5) +800009bc: 73 27 a0 b1 csrr a4, mhpmcounter26 +800009c0: 23 a4 e7 06 sw a4, 104(a5) +800009c4: 73 27 b0 b1 csrr a4, mhpmcounter27 +800009c8: 23 a6 e7 06 sw a4, 108(a5) +800009cc: 73 27 c0 b1 csrr a4, mhpmcounter28 +800009d0: 23 a8 e7 06 sw a4, 112(a5) +800009d4: 73 27 d0 b1 csrr a4, mhpmcounter29 +800009d8: 23 aa e7 06 sw a4, 116(a5) +800009dc: 73 27 e0 b1 csrr a4, mhpmcounter30 +800009e0: 23 ac e7 06 sw a4, 120(a5) +800009e4: 73 27 f0 b1 csrr a4, mhpmcounter31 +800009e8: 23 ae e7 06 sw a4, 124(a5) +800009ec: 73 27 00 b8 csrr a4, mcycleh +800009f0: 23 a0 e7 08 sw a4, 128(a5) +800009f4: 73 27 10 b8 csrr a4, 2945 +800009f8: 23 a2 e7 08 sw a4, 132(a5) +800009fc: 73 27 20 b8 csrr a4, minstreth +80000a00: 23 a4 e7 08 sw a4, 136(a5) +80000a04: 73 27 30 b8 csrr a4, mhpmcounter3h +80000a08: 23 a6 e7 08 sw a4, 140(a5) +80000a0c: 73 27 40 b8 csrr a4, mhpmcounter4h +80000a10: 23 a8 e7 08 sw a4, 144(a5) +80000a14: 73 27 50 b8 csrr a4, mhpmcounter5h +80000a18: 23 aa e7 08 sw a4, 148(a5) +80000a1c: 73 27 60 b8 csrr a4, mhpmcounter6h +80000a20: 23 ac e7 08 sw a4, 152(a5) +80000a24: 73 27 70 b8 csrr a4, mhpmcounter7h +80000a28: 23 ae e7 08 sw a4, 156(a5) +80000a2c: 73 27 80 b8 csrr a4, mhpmcounter8h +80000a30: 23 a0 e7 0a sw a4, 160(a5) +80000a34: 73 27 90 b8 csrr a4, mhpmcounter9h +80000a38: 23 a2 e7 0a sw a4, 164(a5) +80000a3c: 73 27 a0 b8 csrr a4, mhpmcounter10h +80000a40: 23 a4 e7 0a sw a4, 168(a5) +80000a44: 73 27 b0 b8 csrr a4, mhpmcounter11h +80000a48: 23 a6 e7 0a sw a4, 172(a5) +80000a4c: 73 27 c0 b8 csrr a4, mhpmcounter12h +80000a50: 23 a8 e7 0a sw a4, 176(a5) +80000a54: 73 27 d0 b8 csrr a4, mhpmcounter13h +80000a58: 23 aa e7 0a sw a4, 180(a5) +80000a5c: 73 27 e0 b8 csrr a4, mhpmcounter14h +80000a60: 23 ac e7 0a sw a4, 184(a5) +80000a64: 73 27 f0 b8 csrr a4, mhpmcounter15h +80000a68: 23 ae e7 0a sw a4, 188(a5) +80000a6c: 73 27 00 b9 csrr a4, mhpmcounter16h +80000a70: 23 a0 e7 0c sw a4, 192(a5) +80000a74: 73 27 10 b9 csrr a4, mhpmcounter17h +80000a78: 23 a2 e7 0c sw a4, 196(a5) +80000a7c: 73 27 20 b9 csrr a4, mhpmcounter18h +80000a80: 23 a4 e7 0c sw a4, 200(a5) +80000a84: 73 27 30 b9 csrr a4, mhpmcounter19h +80000a88: 23 a6 e7 0c sw a4, 204(a5) +80000a8c: 73 27 40 b9 csrr a4, mhpmcounter20h +80000a90: 23 a8 e7 0c sw a4, 208(a5) +80000a94: 73 27 50 b9 csrr a4, mhpmcounter21h +80000a98: 23 aa e7 0c sw a4, 212(a5) +80000a9c: 73 27 60 b9 csrr a4, mhpmcounter22h +80000aa0: 23 ac e7 0c sw a4, 216(a5) +80000aa4: 73 27 70 b9 csrr a4, mhpmcounter23h +80000aa8: 23 ae e7 0c sw a4, 220(a5) +80000aac: 73 27 80 b9 csrr a4, mhpmcounter24h +80000ab0: 23 a0 e7 0e sw a4, 224(a5) +80000ab4: 73 27 90 b9 csrr a4, mhpmcounter25h +80000ab8: 23 a2 e7 0e sw a4, 228(a5) +80000abc: 73 27 a0 b9 csrr a4, mhpmcounter26h +80000ac0: 23 a4 e7 0e sw a4, 232(a5) +80000ac4: 73 27 b0 b9 csrr a4, mhpmcounter27h +80000ac8: 23 a6 e7 0e sw a4, 236(a5) +80000acc: 73 27 c0 b9 csrr a4, mhpmcounter28h +80000ad0: 23 a8 e7 0e sw a4, 240(a5) +80000ad4: 73 27 d0 b9 csrr a4, mhpmcounter29h +80000ad8: 23 aa e7 0e sw a4, 244(a5) +80000adc: 73 27 e0 b9 csrr a4, mhpmcounter30h +80000ae0: 23 ac e7 0e sw a4, 248(a5) +80000ae4: 73 27 f0 b9 csrr a4, mhpmcounter31h +80000ae8: 23 ae e7 0e sw a4, 252(a5) +80000aec: 67 80 00 00 ret + +80000af0 atexit: +80000af0: 93 05 05 00 mv a1, a0 +80000af4: 93 06 00 00 mv a3, zero +80000af8: 13 06 00 00 mv a2, zero +80000afc: 13 05 00 00 mv a0, zero +80000b00: 6f 00 40 11 j 276 + +80000b04 exit: +80000b04: 13 01 01 ff addi sp, sp, -16 +80000b08: 93 05 00 00 mv a1, zero +80000b0c: 23 24 81 00 sw s0, 8(sp) +80000b10: 23 26 11 00 sw ra, 12(sp) +80000b14: 13 04 05 00 mv s0, a0 +80000b18: ef 00 80 19 jal 408 +80000b1c: b7 17 00 80 lui a5, 524289 +80000b20: 03 a5 07 43 lw a0, 1072(a5) +80000b24: 83 27 c5 03 lw a5, 60(a0) +80000b28: 63 84 07 00 beqz a5, 8 +80000b2c: e7 80 07 00 jalr a5 +80000b30: 13 05 04 00 mv a0, s0 +80000b34: ef f0 5f 8a jal -1884 + +80000b38 memset: +80000b38: 13 03 f0 00 addi t1, zero, 15 +80000b3c: 13 07 05 00 mv a4, a0 +80000b40: 63 7e c3 02 bgeu t1, a2, 60 +80000b44: 93 77 f7 00 andi a5, a4, 15 +80000b48: 63 90 07 0a bnez a5, 160 +80000b4c: 63 92 05 08 bnez a1, 132 +80000b50: 93 76 06 ff andi a3, a2, -16 +80000b54: 13 76 f6 00 andi a2, a2, 15 +80000b58: b3 86 e6 00 add a3, a3, a4 +80000b5c: 23 20 b7 00 sw a1, 0(a4) +80000b60: 23 22 b7 00 sw a1, 4(a4) +80000b64: 23 24 b7 00 sw a1, 8(a4) +80000b68: 23 26 b7 00 sw a1, 12(a4) +80000b6c: 13 07 07 01 addi a4, a4, 16 +80000b70: e3 66 d7 fe bltu a4, a3, -20 +80000b74: 63 14 06 00 bnez a2, 8 +80000b78: 67 80 00 00 ret +80000b7c: b3 06 c3 40 sub a3, t1, a2 +80000b80: 93 96 26 00 slli a3, a3, 2 +80000b84: 97 02 00 00 auipc t0, 0 +80000b88: b3 86 56 00 add a3, a3, t0 +80000b8c: 67 80 c6 00 jr 12(a3) +80000b90: 23 07 b7 00 sb a1, 14(a4) +80000b94: a3 06 b7 00 sb a1, 13(a4) +80000b98: 23 06 b7 00 sb a1, 12(a4) +80000b9c: a3 05 b7 00 sb a1, 11(a4) +80000ba0: 23 05 b7 00 sb a1, 10(a4) +80000ba4: a3 04 b7 00 sb a1, 9(a4) +80000ba8: 23 04 b7 00 sb a1, 8(a4) +80000bac: a3 03 b7 00 sb a1, 7(a4) +80000bb0: 23 03 b7 00 sb a1, 6(a4) +80000bb4: a3 02 b7 00 sb a1, 5(a4) +80000bb8: 23 02 b7 00 sb a1, 4(a4) +80000bbc: a3 01 b7 00 sb a1, 3(a4) +80000bc0: 23 01 b7 00 sb a1, 2(a4) +80000bc4: a3 00 b7 00 sb a1, 1(a4) +80000bc8: 23 00 b7 00 sb a1, 0(a4) +80000bcc: 67 80 00 00 ret +80000bd0: 93 f5 f5 0f andi a1, a1, 255 +80000bd4: 93 96 85 00 slli a3, a1, 8 +80000bd8: b3 e5 d5 00 or a1, a1, a3 +80000bdc: 93 96 05 01 slli a3, a1, 16 +80000be0: b3 e5 d5 00 or a1, a1, a3 +80000be4: 6f f0 df f6 j -148 +80000be8: 93 96 27 00 slli a3, a5, 2 +80000bec: 97 02 00 00 auipc t0, 0 +80000bf0: b3 86 56 00 add a3, a3, t0 +80000bf4: 93 82 00 00 mv t0, ra +80000bf8: e7 80 06 fa jalr -96(a3) +80000bfc: 93 80 02 00 mv ra, t0 +80000c00: 93 87 07 ff addi a5, a5, -16 +80000c04: 33 07 f7 40 sub a4, a4, a5 +80000c08: 33 06 f6 00 add a2, a2, a5 +80000c0c: e3 78 c3 f6 bgeu t1, a2, -144 +80000c10: 6f f0 df f3 j -196 + +80000c14 __register_exitproc: +80000c14: b7 17 00 80 lui a5, 524289 +80000c18: 03 a7 07 43 lw a4, 1072(a5) +80000c1c: 83 27 87 14 lw a5, 328(a4) +80000c20: 63 8c 07 04 beqz a5, 88 +80000c24: 03 a7 47 00 lw a4, 4(a5) +80000c28: 13 08 f0 01 addi a6, zero, 31 +80000c2c: 63 4e e8 06 blt a6, a4, 124 +80000c30: 13 18 27 00 slli a6, a4, 2 +80000c34: 63 06 05 02 beqz a0, 44 +80000c38: 33 83 07 01 add t1, a5, a6 +80000c3c: 23 24 c3 08 sw a2, 136(t1) +80000c40: 83 a8 87 18 lw a7, 392(a5) +80000c44: 13 06 10 00 addi a2, zero, 1 +80000c48: 33 16 e6 00 sll a2, a2, a4 +80000c4c: b3 e8 c8 00 or a7, a7, a2 +80000c50: 23 a4 17 19 sw a7, 392(a5) +80000c54: 23 24 d3 10 sw a3, 264(t1) +80000c58: 93 06 20 00 addi a3, zero, 2 +80000c5c: 63 04 d5 02 beq a0, a3, 40 +80000c60: 13 07 17 00 addi a4, a4, 1 +80000c64: 23 a2 e7 00 sw a4, 4(a5) +80000c68: b3 87 07 01 add a5, a5, a6 +80000c6c: 23 a4 b7 00 sw a1, 8(a5) +80000c70: 13 05 00 00 mv a0, zero +80000c74: 67 80 00 00 ret +80000c78: 93 07 c7 14 addi a5, a4, 332 +80000c7c: 23 24 f7 14 sw a5, 328(a4) +80000c80: 6f f0 5f fa j -92 +80000c84: 83 a6 c7 18 lw a3, 396(a5) +80000c88: 13 07 17 00 addi a4, a4, 1 +80000c8c: 23 a2 e7 00 sw a4, 4(a5) +80000c90: 33 e6 c6 00 or a2, a3, a2 +80000c94: 23 a6 c7 18 sw a2, 396(a5) +80000c98: b3 87 07 01 add a5, a5, a6 +80000c9c: 23 a4 b7 00 sw a1, 8(a5) +80000ca0: 13 05 00 00 mv a0, zero +80000ca4: 67 80 00 00 ret +80000ca8: 13 05 f0 ff addi a0, zero, -1 +80000cac: 67 80 00 00 ret + +80000cb0 __call_exitprocs: +80000cb0: 13 01 01 fd addi sp, sp, -48 +80000cb4: b7 17 00 80 lui a5, 524289 +80000cb8: 23 2c 41 01 sw s4, 24(sp) +80000cbc: 03 aa 07 43 lw s4, 1072(a5) +80000cc0: 23 20 21 03 sw s2, 32(sp) +80000cc4: 23 26 11 02 sw ra, 44(sp) +80000cc8: 03 29 8a 14 lw s2, 328(s4) +80000ccc: 23 24 81 02 sw s0, 40(sp) +80000cd0: 23 22 91 02 sw s1, 36(sp) +80000cd4: 23 2e 31 01 sw s3, 28(sp) +80000cd8: 23 2a 51 01 sw s5, 20(sp) +80000cdc: 23 28 61 01 sw s6, 16(sp) +80000ce0: 23 26 71 01 sw s7, 12(sp) +80000ce4: 23 24 81 01 sw s8, 8(sp) +80000ce8: 63 00 09 04 beqz s2, 64 +80000cec: 13 0b 05 00 mv s6, a0 +80000cf0: 93 8b 05 00 mv s7, a1 +80000cf4: 93 0a 10 00 addi s5, zero, 1 +80000cf8: 93 09 f0 ff addi s3, zero, -1 +80000cfc: 83 24 49 00 lw s1, 4(s2) +80000d00: 13 84 f4 ff addi s0, s1, -1 +80000d04: 63 42 04 02 bltz s0, 36 +80000d08: 93 94 24 00 slli s1, s1, 2 +80000d0c: b3 04 99 00 add s1, s2, s1 +80000d10: 63 84 0b 04 beqz s7, 72 +80000d14: 83 a7 44 10 lw a5, 260(s1) +80000d18: 63 80 77 05 beq a5, s7, 64 +80000d1c: 13 04 f4 ff addi s0, s0, -1 +80000d20: 93 84 c4 ff addi s1, s1, -4 +80000d24: e3 16 34 ff bne s0, s3, -20 +80000d28: 83 20 c1 02 lw ra, 44(sp) +80000d2c: 03 24 81 02 lw s0, 40(sp) +80000d30: 83 24 41 02 lw s1, 36(sp) +80000d34: 03 29 01 02 lw s2, 32(sp) +80000d38: 83 29 c1 01 lw s3, 28(sp) +80000d3c: 03 2a 81 01 lw s4, 24(sp) +80000d40: 83 2a 41 01 lw s5, 20(sp) +80000d44: 03 2b 01 01 lw s6, 16(sp) +80000d48: 83 2b c1 00 lw s7, 12(sp) +80000d4c: 03 2c 81 00 lw s8, 8(sp) +80000d50: 13 01 01 03 addi sp, sp, 48 +80000d54: 67 80 00 00 ret +80000d58: 83 27 49 00 lw a5, 4(s2) +80000d5c: 83 a6 44 00 lw a3, 4(s1) +80000d60: 93 87 f7 ff addi a5, a5, -1 +80000d64: 63 8e 87 04 beq a5, s0, 92 +80000d68: 23 a2 04 00 sw zero, 4(s1) +80000d6c: e3 88 06 fa beqz a3, -80 +80000d70: 83 27 89 18 lw a5, 392(s2) +80000d74: 33 97 8a 00 sll a4, s5, s0 +80000d78: 03 2c 49 00 lw s8, 4(s2) +80000d7c: b3 77 f7 00 and a5, a4, a5 +80000d80: 63 92 07 02 bnez a5, 36 +80000d84: e7 80 06 00 jalr a3 +80000d88: 03 27 49 00 lw a4, 4(s2) +80000d8c: 83 27 8a 14 lw a5, 328(s4) +80000d90: 63 14 87 01 bne a4, s8, 8 +80000d94: e3 04 f9 f8 beq s2, a5, -120 +80000d98: e3 88 07 f8 beqz a5, -112 +80000d9c: 13 89 07 00 mv s2, a5 +80000da0: 6f f0 df f5 j -164 +80000da4: 83 27 c9 18 lw a5, 396(s2) +80000da8: 83 a5 44 08 lw a1, 132(s1) +80000dac: 33 77 f7 00 and a4, a4, a5 +80000db0: 63 1c 07 00 bnez a4, 24 +80000db4: 13 05 0b 00 mv a0, s6 +80000db8: e7 80 06 00 jalr a3 +80000dbc: 6f f0 df fc j -52 +80000dc0: 23 22 89 00 sw s0, 4(s2) +80000dc4: 6f f0 9f fa j -88 +80000dc8: 13 85 05 00 mv a0, a1 +80000dcc: e7 80 06 00 jalr a3 +80000dd0: 6f f0 9f fb j -72 + +Disassembly of section .init_array: + +80001000 __preinit_array_start: +80001000: 50 00 +80001002: 00 80 + +Disassembly of section .data: + +80001008 impure_data: +80001008: 00 00 +8000100a: 00 00 +8000100c: f4 12 +8000100e: 00 80 +80001010: 5c 13 +80001012: 00 80 +80001014: c4 13 +80001016: 00 80 + ... +800010b0: 01 00 +800010b2: 00 00 +800010b4: 00 00 +800010b6: 00 00 +800010b8: 0e 33 +800010ba: cd ab +800010bc: 34 12 +800010be: 6d e6 +800010c0: ec de +800010c2: 05 00 +800010c4: 0b 00 00 00 + ... + +Disassembly of section .sdata: + +80001430 _global_impure_ptr: +80001430: 08 10 +80001432: 00 80 + +Disassembly of section .bss: + +80001434 g_wspawn_args: +... + +Disassembly of section .comment: + +00000000 .comment: + 0: 63 6c 61 6e bltu sp, t1, 1784 + 4: 67 20 76 65 + 8: 72 73 + a: 69 6f + c: 6e 20 + e: 31 30 + 10: 2e 30 + 12: 2e 31 + 14: 20 28 + 16: 68 74 + 18: 74 70 + 1a: 73 3a 2f 2f csrrc s4, 754, t5 + 1e: 67 69 74 68 + 22: 75 62 + 24: 2e 63 + 26: 6f 6d 2f 6c jal s10, 1009346 + 2a: 6c 76 + 2c: 6d 2f + 2e: 6c 6c + 30: 76 6d + 32: 2d 70 + 34: 72 6f + 36: 6a 65 + 38: 63 74 2e 67 bgeu t3, s2, 1640 + 3c: 69 74 + 3e: 20 32 + 40: 61 32 + 42: 33 65 66 61 + 46: 63 33 35 32 + 4a: 66 39 + 4c: 31 39 + 4e: 65 62 + 50: 64 31 + 52: 65 63 + 54: 31 62 + 56: 65 34 + 58: 35 31 + 5a: 34 36 + 5c: 64 36 + 5e: 61 39 + 60: 66 61 + 62: 32 31 + 64: 62 35 + 66: 33 29 00 47 + 6a: 43 43 3a 20 fmadd.s ft6, fs4, ft3, ft4, rmm + 6e: 28 47 + 70: 4e 55 + 72: 29 20 + 74: 39 2e + 76: 32 2e + 78: 30 00 + +Disassembly of section .riscv.attributes: + +00000000 .riscv.attributes: + 0: 41 25 + 2: 00 00 + 4: 00 72 + 6: 69 73 + 8: 63 76 00 01 bgeu zero, a6, 12 + c: 1b 00 00 00 + 10: 04 10 + 12: 05 72 + 14: 76 33 + 16: 32 69 + 18: 32 70 + 1a: 30 5f + 1c: 6d 32 + 1e: 70 30 + 20: 5f 66 32 70 + 24: 30 00 + +Disassembly of section .symtab: + +00000000 .symtab: + ... + 14: 00 00 + 16: 00 80 + 18: 00 00 + 1a: 00 00 + 1c: 03 00 01 00 lb zero, 0(sp) + 20: 00 00 + 22: 00 00 + 24: 50 00 + 26: 00 80 + 28: 00 00 + 2a: 00 00 + 2c: 03 00 02 00 lb zero, 0(tp) + 30: 00 00 + 32: 00 00 + 34: 00 10 + 36: 00 80 + 38: 00 00 + 3a: 00 00 + 3c: 03 00 03 00 lb zero, 0(t1) + 40: 00 00 + 42: 00 00 + 44: 08 10 + 46: 00 80 + 48: 00 00 + 4a: 00 00 + 4c: 03 00 04 00 lb zero, 0(s0) + 50: 00 00 + 52: 00 00 + 54: 30 14 + 56: 00 80 + 58: 00 00 + 5a: 00 00 + 5c: 03 00 05 00 lb zero, 0(a0) + 60: 00 00 + 62: 00 00 + 64: 34 14 + 66: 00 80 + 68: 00 00 + 6a: 00 00 + 6c: 03 00 06 00 lb zero, 0(a2) + ... + 7c: 03 00 07 00 lb zero, 0(a4) + ... + 8c: 03 00 08 00 lb zero, 0(a6) + 90: 01 00 + ... + 9a: 00 00 + 9c: 04 00 + 9e: f1 ff + a0: 0e 00 + a2: 00 00 + a4: e4 03 + a6: 00 80 + a8: 00 00 + aa: 00 00 + ac: 00 00 + ae: 02 00 + b0: 1e 00 + b2: 00 00 + b4: 20 04 + b6: 00 80 + b8: 00 00 + ba: 00 00 + bc: 00 00 + be: 02 00 + c0: 25 00 + ... + ca: 00 00 + cc: 04 00 + ce: f1 ff + d0: 35 00 + d2: 00 00 + d4: 50 00 + d6: 00 80 + d8: 18 00 + da: 00 00 + dc: 02 00 + de: 02 00 + e0: 43 00 00 00 fmadd.s ft0, ft0, ft0, ft0, rne + ... + ec: 04 00 + ee: f1 ff + f0: 67 00 00 00 jr zero + ... + fc: 04 00 + fe: f1 ff + 100: 73 00 00 00 ecall + ... + 10c: 04 00 + 10e: f1 ff + 110: 81 00 + ... + 11a: 00 00 + 11c: 04 00 + 11e: f1 ff + 120: 8c 00 + 122: 00 00 + 124: 1c 05 + 126: 00 80 + 128: 3c 01 + 12a: 00 00 + 12c: 02 00 + 12e: 02 00 + 130: a2 00 + 132: 00 00 + 134: 58 06 + 136: 00 80 + 138: a4 00 + 13a: 00 00 + 13c: 02 00 + 13e: 02 00 + 140: b8 00 + 142: 00 00 + 144: fc 06 + 146: 00 80 + 148: 2c 00 + 14a: 00 00 + 14c: 02 00 + 14e: 02 00 + 150: cc 00 + ... + 15a: 00 00 + 15c: 04 00 + 15e: f1 ff + 160: d8 00 + ... + 16a: 00 00 + 16c: 04 00 + 16e: f1 ff + 170: da 00 + ... + 17a: 00 00 + 17c: 04 00 + 17e: f1 ff + 180: d6 00 + ... + 18a: 00 00 + 18c: 04 00 + 18e: f1 ff + 190: e1 00 + ... + 19a: 00 00 + 19c: 04 00 + 19e: f1 ff + 1a0: ea 00 + 1a2: 00 00 + 1a4: 08 10 + 1a6: 00 80 + 1a8: 28 04 + 1aa: 00 00 + 1ac: 01 00 + 1ae: 04 00 + ... + 1bc: 04 00 + 1be: f1 ff + 1c0: f6 00 + 1c2: 00 00 + 1c4: 04 10 + 1c6: 00 80 + 1c8: 00 00 + 1ca: 00 00 + 1cc: 00 00 + 1ce: 03 00 07 01 lb zero, 16(a4) + 1d2: 00 00 + 1d4: 04 10 + 1d6: 00 80 + 1d8: 00 00 + 1da: 00 00 + 1dc: 00 00 + 1de: 03 00 1a 01 lb zero, 17(s4) + 1e2: 00 00 + 1e4: 04 10 + 1e6: 00 80 + 1e8: 00 00 + 1ea: 00 00 + 1ec: 00 00 + 1ee: 03 00 2b 01 lb zero, 18(s6) + 1f2: 00 00 + 1f4: 00 10 + 1f6: 00 80 + 1f8: 00 00 + 1fa: 00 00 + 1fc: 00 00 + 1fe: 03 00 3f 01 lb zero, 19(t5) + 202: 00 00 + 204: 00 10 + 206: 00 80 + 208: 00 00 + 20a: 00 00 + 20c: 00 00 + 20e: 03 00 52 01 lb zero, 21(tp) + 212: 00 00 + 214: 00 10 + 216: 00 80 + 218: 00 00 + 21a: 00 00 + 21c: 00 00 + 21e: 03 00 68 01 lb zero, 22(a6) + ... + 22a: 00 00 + 22c: 10 00 + 22e: f1 ff + 230: 76 01 + 232: 00 00 + 234: 00 04 + 236: 00 00 + 238: 00 00 + 23a: 00 00 + 23c: 10 00 + 23e: f1 ff + 240: 83 01 00 00 lb gp, 0(zero) + 244: 34 14 + 246: 00 80 + 248: 80 00 + 24a: 00 00 + 24c: 11 00 + 24e: 06 00 + 250: 91 01 + 252: 00 00 + 254: 30 14 + 256: 00 80 + 258: 00 00 + 25a: 00 00 + 25c: 10 00 + 25e: 05 00 + 260: a1 01 + 262: 00 00 + 264: b8 01 + 266: 00 80 + 268: 14 01 + 26a: 00 00 + 26c: 12 00 + 26e: 02 00 + 270: bf 01 00 00 + 274: 08 18 + 276: 00 80 + 278: 00 00 + 27a: 00 00 + 27c: 10 00 + 27e: f1 ff + 280: d0 01 + 282: 00 00 + 284: 30 14 + 286: 00 80 + 288: 04 00 + 28a: 00 00 + 28c: 11 00 + 28e: 05 00 + 290: e3 01 00 00 beqz zero, 2050 + 294: 24 04 + 296: 00 80 + 298: 9c 00 + 29a: 00 00 + 29c: 12 00 + 29e: 02 00 + 2a0: f5 01 + 2a2: 00 00 + 2a4: c0 04 + 2a6: 00 80 + 2a8: 5c 00 + 2aa: 00 00 + 2ac: 12 00 + 2ae: 02 00 + 2b0: 07 02 00 00 + 2b4: f0 03 + 2b6: 00 80 + 2b8: 00 00 + 2ba: 00 00 + 2bc: 12 00 + 2be: 02 00 + 2c0: 11 02 + 2c2: 00 00 + 2c4: b0 0c + 2c6: 00 80 + 2c8: 24 01 + 2ca: 00 00 + 2cc: 12 00 + 2ce: 02 00 + 2d0: 47 02 00 00 fmsub.s ft4, ft0, ft0, ft0, rne + 2d4: 00 00 + 2d6: 00 80 + 2d8: 50 00 + 2da: 00 00 + 2dc: 12 00 + 2de: 01 00 + 2e0: 22 02 + 2e2: 00 00 + 2e4: 14 0c + 2e6: 00 80 + 2e8: 9c 00 + 2ea: 00 00 + 2ec: 12 00 + 2ee: 02 00 + 2f0: 36 02 + 2f2: 00 00 + 2f4: b4 14 + 2f6: 00 80 + 2f8: 00 00 + 2fa: 00 00 + 2fc: 10 00 + 2fe: 06 00 + 300: 42 02 + 302: 00 00 + 304: 34 14 + 306: 00 80 + 308: 00 00 + 30a: 00 00 + 30c: 10 00 + 30e: 06 00 + 310: 4e 02 + 312: 00 00 + 314: 38 0b + 316: 00 80 + 318: dc 00 + 31a: 00 00 + 31c: 12 00 + 31e: 02 00 + 320: 55 02 + 322: 00 00 + 324: 68 00 + 326: 00 80 + 328: 30 00 + 32a: 00 00 + 32c: 12 00 + 32e: 02 00 + 330: 5a 02 + 332: 00 00 + 334: f0 0a + 336: 00 80 + 338: 14 00 + 33a: 00 00 + 33c: 12 00 + 33e: 02 00 + 340: 61 02 + 342: 00 00 + 344: cc 02 + 346: 00 80 + 348: 0c 01 + 34a: 00 00 + 34c: 12 00 + 34e: 02 00 + 350: 84 02 + 352: 00 00 + 354: 08 10 + 356: 00 80 + 358: 00 00 + 35a: 00 00 + 35c: 10 00 + 35e: 04 00 + 360: 93 02 00 00 mv t0, zero + 364: 34 14 + 366: 00 80 + 368: 00 00 + 36a: 00 00 + 36c: 10 00 + 36e: 05 00 + 370: 02 01 + 372: 00 00 + 374: b4 14 + 376: 00 80 + 378: 00 00 + 37a: 00 00 + 37c: 10 00 + 37e: 06 00 + 380: a8 02 + 382: 00 00 + 384: 04 0b + 386: 00 80 + 388: 34 00 + 38a: 00 00 + 38c: 12 00 + 38e: 02 00 + 390: 9a 02 + 392: 00 00 + 394: dc 08 + 396: 00 80 + 398: 14 02 + 39a: 00 00 + 39c: 12 00 + 39e: 02 00 + 3a0: a7 02 00 00 + 3a4: d8 03 + 3a6: 00 80 + 3a8: 00 00 + 3aa: 00 00 + 3ac: 12 00 + 3ae: 02 00 + 3b0: ad 02 + 3b2: 00 00 + 3b4: 98 00 + 3b6: 00 80 + 3b8: 20 01 + 3ba: 00 00 + 3bc: 12 00 + 3be: 02 00 + 3c0: c1 02 + 3c2: 00 00 + 3c4: 28 07 + 3c6: 00 80 + 3c8: b4 01 + 3ca: 00 00 + 3cc: 12 00 + 3ce: 02 00 + +Disassembly of section .strtab: + +00000000 .strtab: + 0: 00 76 + 2: 78 5f + 4: 73 74 61 72 csrrci s0, 1830, 2 + 8: 74 2e + a: 53 2e 6f 00 fadd.s ft8, ft10, ft6, rdn + e: 6c 61 + 10: 62 65 + 12: 6c 5f + 14: 65 78 + 16: 69 74 + 18: 5f 6e 65 78 + 1c: 74 00 + 1e: 52 45 + 20: 54 55 + 22: 52 4e + 24: 00 5f + 26: 5f 63 61 6c + 2a: 6c 5f + 2c: 61 74 + 2e: 65 78 + 30: 69 74 + 32: 2e 63 + 34: 00 72 + 36: 65 67 + 38: 69 73 + 3a: 74 65 + 3c: 72 5f + 3e: 66 69 + 40: 6e 69 + 42: 00 70 + 44: 6f 63 6c 5f jal t1, 812534 + 48: 76 6f + 4a: 72 74 + 4c: 65 78 + 4e: 5f 6b 65 72 + 52: 6e 65 + 54: 6c 2d + 56: 32 34 + 58: 2d 36 + 5a: 37 2d 66 37 lui s10, 226914 + 5e: 2d 30 + 60: 38 2d + 62: 63 66 2e 63 bltu t3, s2, 1580 + 66: 00 70 + 68: 61 72 + 6a: 61 6c + 6c: 6c 65 + 6e: 6c 5f + 70: 62 63 + 72: 00 76 + 74: 78 5f + 76: 73 79 73 63 csrrci s2, 1591, 6 + 7a: 61 6c + 7c: 6c 73 + 7e: 2e 63 + 80: 00 76 + 82: 78 5f + 84: 73 70 61 77 csrci 1910, 2 + 88: 6e 2e + 8a: 63 00 73 70 beq t1, t2, 1792 + 8e: 61 77 + 90: 6e 5f + 92: 6b 65 72 6e + 96: 65 6c + 98: 5f 61 6c 6c + 9c: 5f 73 74 75 + a0: 62 00 + a2: 73 70 61 77 csrci 1910, 2 + a6: 6e 5f + a8: 6b 65 72 6e + ac: 65 6c + ae: 5f 72 65 6d + b2: 5f 73 74 75 + b6: 62 00 + b8: 73 70 61 77 csrci 1910, 2 + bc: 6e 5f + be: 6b 65 72 6e + c2: 65 6c + c4: 5f 61 6c 6c + c8: 5f 63 62 00 + cc: 76 78 + ce: 5f 70 65 72 + d2: 66 2e + d4: 63 00 5f 5f beq t5, s5, 1504 + d8: 61 74 + da: 65 78 + dc: 69 74 + de: 2e 63 + e0: 00 69 + e2: 6d 70 + e4: 75 72 + e6: 65 2e + e8: 63 00 69 6d beq s2, s6, 1728 + ec: 70 75 + ee: 72 65 + f0: 5f 64 61 74 + f4: 61 00 + f6: 5f 5f 66 69 + fa: 6e 69 + fc: 5f 61 72 72 + 100: 61 79 + 102: 5f 65 6e 64 + 106: 00 5f + 108: 5f 66 69 6e + 10c: 69 5f + 10e: 61 72 + 110: 72 61 + 112: 79 5f + 114: 73 74 61 72 csrrci s0, 1830, 2 + 118: 74 00 + 11a: 5f 5f 69 6e + 11e: 69 74 + 120: 5f 61 72 72 + 124: 61 79 + 126: 5f 65 6e 64 + 12a: 00 5f + 12c: 5f 70 72 65 + 130: 69 6e + 132: 69 74 + 134: 5f 61 72 72 + 138: 61 79 + 13a: 5f 65 6e 64 + 13e: 00 5f + 140: 5f 69 6e 69 + 144: 74 5f + 146: 61 72 + 148: 72 61 + 14a: 79 5f + 14c: 73 74 61 72 csrrci s0, 1830, 2 + 150: 74 00 + 152: 5f 5f 70 72 + 156: 65 69 + 158: 6e 69 + 15a: 74 5f + 15c: 61 72 + 15e: 72 61 + 160: 79 5f + 162: 73 74 61 72 csrrci s0, 1830, 2 + 166: 74 00 + 168: 5f 5f 73 74 + 16c: 61 63 + 16e: 6b 5f 75 73 + 172: 61 67 + 174: 65 00 + 176: 5f 5f 73 74 + 17a: 61 63 + 17c: 6b 5f 73 69 + 180: 7a 65 + 182: 00 67 + 184: 5f 77 73 70 + 188: 61 77 + 18a: 6e 5f + 18c: 61 72 + 18e: 67 73 00 5f + 192: 5f 53 44 41 + 196: 54 41 + 198: 5f 42 45 47 + 19c: 49 4e + 19e: 5f 5f 00 5f + 1a2: 70 6f + 1a4: 63 6c 5f 6b bltu t5, s5, 1720 + 1a8: 65 72 + 1aa: 6e 65 + 1ac: 6c 5f + 1ae: 70 73 + 1b0: 6f 72 74 69 jal tp, 294550 + 1b4: 5f 77 6f 72 + 1b8: 6b 67 72 6f + 1bc: 75 70 + 1be: 00 5f + 1c0: 5f 67 6c 6f + 1c4: 62 61 + 1c6: 6c 5f + 1c8: 70 6f + 1ca: 69 6e + 1cc: 74 65 + 1ce: 72 00 + 1d0: 5f 67 6c 6f + 1d4: 62 61 + 1d6: 6c 5f + 1d8: 69 6d + 1da: 70 75 + 1dc: 72 65 + 1de: 5f 70 74 72 + 1e2: 00 5f + 1e4: 5f 6c 69 62 + 1e8: 63 5f 69 6e bge s2, t1, 1790 + 1ec: 69 74 + 1ee: 5f 61 72 72 + 1f2: 61 79 + 1f4: 00 5f + 1f6: 5f 6c 69 62 + 1fa: 63 5f 66 69 bge a2, s6, 1694 + 1fe: 6e 69 + 200: 5f 61 72 72 + 204: 61 79 + 206: 00 76 + 208: 78 5f + 20a: 73 65 74 5f csrrsi a0, 1527, 8 + 20e: 73 70 00 5f csrci 1520, 0 + 212: 5f 63 61 6c + 216: 6c 5f + 218: 65 78 + 21a: 69 74 + 21c: 70 72 + 21e: 6f 63 73 00 jal t1, 223238 + 222: 5f 5f 72 65 + 226: 67 69 73 74 + 22a: 65 72 + 22c: 5f 65 78 69 + 230: 74 70 + 232: 72 6f + 234: 63 00 5f 5f beq t5, s5, 1504 + 238: 42 53 + 23a: 53 5f 45 4e + 23e: 44 5f + 240: 5f 00 5f 5f + 244: 62 73 + 246: 73 5f 73 74 csrrwi t5, 1863, 6 + 24a: 61 72 + 24c: 74 00 + 24e: 6d 65 + 250: 6d 73 + 252: 65 74 + 254: 00 6d + 256: 61 69 + 258: 6e 00 + 25a: 61 74 + 25c: 65 78 + 25e: 69 74 + 260: 00 5f + 262: 70 6f + 264: 63 6c 5f 6b bltu t5, s5, 1720 + 268: 65 72 + 26a: 6e 65 + 26c: 6c 5f + 26e: 70 73 + 270: 6f 72 74 69 jal tp, 294550 + 274: 5f 77 6f 72 + 278: 6b 67 72 6f + 27c: 75 70 + 27e: 5f 66 61 73 + 282: 74 00 + 284: 5f 5f 44 41 + 288: 54 41 + 28a: 5f 42 45 47 + 28e: 49 4e + 290: 5f 5f 00 5f + 294: 65 64 + 296: 61 74 + 298: 61 00 + 29a: 76 78 + 29c: 5f 70 65 72 + 2a0: 66 5f + 2a2: 64 75 + 2a4: 6d 70 + 2a6: 00 5f + 2a8: 65 78 + 2aa: 69 74 + 2ac: 00 5f + 2ae: 70 6f + 2b0: 63 6c 5f 6b bltu t5, s5, 1720 + 2b4: 65 72 + 2b6: 6e 65 + 2b8: 6c 5f + 2ba: 70 73 + 2bc: 6f 72 74 69 jal tp, 294550 + 2c0: 00 76 + 2c2: 78 5f + 2c4: 73 70 61 77 csrci 1910, 2 + 2c8: 6e 5f + 2ca: 6b 65 72 6e + 2ce: 65 6c + 2d0: 00 + +Disassembly of section .shstrtab: + +00000000 .shstrtab: + 0: 00 2e + 2: 73 79 6d 74 csrrci s2, 1862, 26 + 6: 61 62 + 8: 00 2e + a: 73 74 72 74 csrrci s0, 1863, 4 + e: 61 62 + 10: 00 2e + 12: 73 68 73 74 csrrsi a6, 1863, 6 + 16: 72 74 + 18: 61 62 + 1a: 00 2e + 1c: 69 6e + 1e: 69 74 + 20: 00 2e + 22: 74 65 + 24: 78 74 + 26: 00 2e + 28: 69 6e + 2a: 69 74 + 2c: 5f 61 72 72 + 30: 61 79 + 32: 00 2e + 34: 64 61 + 36: 74 61 + 38: 00 2e + 3a: 73 64 61 74 csrrsi s0, 1862, 2 + 3e: 61 00 + 40: 2e 62 + 42: 73 73 00 2e csrrci t1, 736, 0 + 46: 63 6f 6d 6d bltu s10, s6, 1758 + 4a: 65 6e + 4c: 74 00 + 4e: 2e 72 + 50: 69 73 + 52: 63 76 2e 61 bgeu t3, s2, 1548 + 56: 74 74 + 58: 72 69 + 5a: 62 75 + 5c: 74 65 + 5e: 73 + 5f: 00 diff --git a/tests/opencl/saxpy/Makefile b/tests/opencl/saxpy/Makefile index 0414fcff..a4a2db87 100644 --- a/tests/opencl/saxpy/Makefile +++ b/tests/opencl/saxpy/Makefile @@ -9,8 +9,8 @@ VORTEX_RT_PATH ?= $(realpath ../../../runtime) OPTS ?= -n1024 -K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -float-abi=hard -code-model=small" -K_CFLAGS += "-v -O3 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" +K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -mattr=+vortex -float-abi=hard -code-model=small" +K_CFLAGS += "-v -O3 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -Xclang -target-feature -Xclang +vortex -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" K_LDFLAGS += "-Wl,-Bstatic,-T$(VORTEX_RT_PATH)/linker/vx_link.ld -Wl,--gc-sections $(VORTEX_RT_PATH)/libvortexrt.a -lm" CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors @@ -35,13 +35,13 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ run-fpga: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-simx: $(PROJECT) kernel.pocl LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/opencl/saxpy/kernel.pocl b/tests/opencl/saxpy/kernel.pocl index e22c3ed1..8ac13900 100644 Binary files a/tests/opencl/saxpy/kernel.pocl and b/tests/opencl/saxpy/kernel.pocl differ diff --git a/tests/opencl/saxpy/saxpy.dump b/tests/opencl/saxpy/saxpy.dump index 56a19426..d490348c 100644 --- a/tests/opencl/saxpy/saxpy.dump +++ b/tests/opencl/saxpy/saxpy.dump @@ -1,39 +1,39 @@ -/tmp/pocl_vortex_kernel-1a-29-17-50-fc.elf: file format ELF32-riscv +/tmp/pocl_vortex_kernel-10-cf-53-cd-1a.elf: file format ELF32-riscv Disassembly of section .init: 80000000 _start: 80000000: 97 05 00 00 auipc a1, 0 -80000004: 93 85 05 24 addi a1, a1, 576 +80000004: 93 85 c5 24 addi a1, a1, 588 80000008: 73 25 10 fc csrr a0, 4033 -8000000c: 6b 10 b5 00 -80000010: ef 00 00 23 jal 560 +8000000c: 6b 10 b5 00 vx_wspawn a0, a1 +80000010: ef 00 c0 23 jal 572 80000014: 13 05 10 00 addi a0, zero, 1 -80000018: 6b 00 05 00 +80000018: 6b 00 05 00 vx_tmc a0 8000001c: 17 15 00 00 auipc a0, 1 80000020: 13 05 85 41 addi a0, a0, 1048 80000024: 17 16 00 00 auipc a2, 1 80000028: 13 06 06 49 addi a2, a2, 1168 8000002c: 33 06 a6 40 sub a2, a2, a0 80000030: 93 05 00 00 mv a1, zero -80000034: ef 00 10 11 jal 2320 -80000038: 17 15 00 00 auipc a0, 1 -8000003c: 13 05 45 81 addi a0, a0, -2028 -80000040: ef 00 40 7c jal 1988 -80000044: ef 00 50 06 jal 2148 +80000034: ef 00 10 16 jal 2400 +80000038: 17 05 00 00 auipc a0, 0 +8000003c: 13 05 45 2e addi a0, a0, 740 +80000040: ef 00 d0 10 jal 2316 +80000044: ef 00 c0 23 jal 572 80000048: ef 00 00 02 jal 32 -8000004c: 6f 00 c0 7c j 1996 +8000004c: 6f 00 50 11 j 2324 Disassembly of section .text: 80000050 register_fini: 80000050: 93 07 00 00 mv a5, zero 80000054: 63 88 07 00 beqz a5, 16 -80000058: 37 15 00 80 lui a0, 524289 -8000005c: 13 05 c5 84 addi a0, a0, -1972 -80000060: 6f 00 40 7a j 1956 +80000058: 37 05 00 80 lui a0, 524288 +8000005c: 13 05 c5 31 addi a0, a0, 796 +80000060: 6f 00 d0 0e j 2284 80000064: 67 80 00 00 ret 80000068 main: @@ -44,7 +44,7 @@ Disassembly of section .text: 80000078: 37 05 ff 7f lui a0, 524272 8000007c: 13 06 45 03 addi a2, a0, 52 80000080: 37 05 ff 7f lui a0, 524272 -80000084: ef 00 00 34 jal 832 +80000084: ef 00 00 50 jal 1280 80000088: 13 05 00 00 mv a0, zero 8000008c: 83 20 c1 00 lw ra, 12(sp) 80000090: 13 01 01 01 addi sp, sp, 16 @@ -160,649 +160,675 @@ Disassembly of section .text: 80000230: 67 80 00 00 ret 80000234 _exit: -80000234: ef 00 c0 3b jal 956 -80000238: 13 05 00 00 mv a0, zero -8000023c: 6b 00 05 00 +80000234: 63 06 05 00 beqz a0, 12 +80000238: 93 01 05 00 mv gp, a0 +8000023c: 73 00 00 00 ecall -80000240 vx_set_sp: -80000240: 73 25 00 fc csrr a0, 4032 -80000244: 6b 00 05 00 -80000248: 97 11 00 00 auipc gp, 1 -8000024c: 93 81 01 5c addi gp, gp, 1472 -80000250: 17 01 00 7f auipc sp, 520192 -80000254: 13 01 01 db addi sp, sp, -592 -80000258: 93 05 00 40 addi a1, zero, 1024 -8000025c: 73 26 10 cc csrr a2, 3265 -80000260: b3 85 c5 02 mul a1, a1, a2 -80000264: 33 01 b1 40 sub sp, sp, a1 -80000268: f3 26 30 cc csrr a3, 3267 -8000026c: 63 86 06 00 beqz a3, 12 -80000270: 13 05 00 00 mv a0, zero -80000274: 6b 00 05 00 +80000240 label_exit_next: +80000240: ef 00 80 4f jal 1272 +80000244: 13 05 00 00 mv a0, zero +80000248: 6b 00 05 00 vx_tmc a0 -80000278 RETURN: -80000278: 67 80 00 00 ret +8000024c vx_set_sp: +8000024c: 13 05 f0 ff addi a0, zero, -1 +80000250: 6b 00 05 00 vx_tmc a0 +80000254: 97 11 00 00 auipc gp, 1 +80000258: 93 81 41 5b addi gp, gp, 1460 +8000025c: 37 01 00 ff lui sp, 1044480 +80000260: 73 26 10 cc csrr a2, 3265 +80000264: 93 15 a6 00 slli a1, a2, 10 +80000268: 33 01 b1 40 sub sp, sp, a1 +8000026c: f3 26 30 cc csrr a3, 3267 +80000270: 63 86 06 00 beqz a3, 12 +80000274: 13 05 00 00 mv a0, zero +80000278: 6b 00 05 00 vx_tmc a0 -8000027c spawn_kernel_callback: -8000027c: 13 01 01 fe addi sp, sp, -32 -80000280: 23 2e 11 00 sw ra, 28(sp) -80000284: 23 2c 81 00 sw s0, 24(sp) -80000288: 23 2a 91 00 sw s1, 20(sp) -8000028c: 23 28 21 01 sw s2, 16(sp) -80000290: 23 26 31 01 sw s3, 12(sp) -80000294: 23 24 41 01 sw s4, 8(sp) -80000298: 23 22 51 01 sw s5, 4(sp) -8000029c: f3 27 00 fc csrr a5, 4032 -800002a0: 6b 80 07 00 -800002a4: f3 26 50 cc csrr a3, 3269 -800002a8: 73 29 30 cc csrr s2, 3267 -800002ac: 73 27 00 cc csrr a4, 3264 -800002b0: 73 26 00 fc csrr a2, 4032 -800002b4: b7 17 00 80 lui a5, 524289 -800002b8: 93 96 26 00 slli a3, a3, 2 -800002bc: 93 87 47 43 addi a5, a5, 1076 -800002c0: b3 87 d7 00 add a5, a5, a3 -800002c4: 03 a4 07 00 lw s0, 0(a5) -800002c8: 83 24 44 01 lw s1, 20(s0) -800002cc: 83 26 04 01 lw a3, 16(s0) -800002d0: b3 2a 99 00 slt s5, s2, s1 -800002d4: 93 87 04 00 mv a5, s1 -800002d8: b3 8a da 00 add s5, s5, a3 -800002dc: b3 84 26 03 mul s1, a3, s2 -800002e0: 63 54 f9 00 bge s2, a5, 8 -800002e4: 93 07 09 00 mv a5, s2 -800002e8: b3 84 f4 00 add s1, s1, a5 -800002ec: 83 25 04 00 lw a1, 0(s0) -800002f0: 83 26 c4 00 lw a3, 12(s0) -800002f4: 83 a9 05 00 lw s3, 0(a1) -800002f8: 03 aa 45 00 lw s4, 4(a1) -800002fc: b3 84 c4 02 mul s1, s1, a2 -80000300: b3 87 ea 02 mul a5, s5, a4 -80000304: b3 84 d4 00 add s1, s1, a3 -80000308: b3 84 f4 00 add s1, s1, a5 -8000030c: b3 8a 9a 00 add s5, s5, s1 -80000310: 33 8a 49 03 mul s4, s3, s4 -80000314: 63 c0 54 07 blt s1, s5, 96 -80000318: 6f 00 00 08 j 128 -8000031c: 03 47 a4 01 lbu a4, 26(s0) -80000320: 83 46 94 01 lbu a3, 25(s0) -80000324: 33 d7 e4 40 sra a4, s1, a4 -80000328: b3 07 47 03 mul a5, a4, s4 -8000032c: b3 87 f4 40 sub a5, s1, a5 -80000330: 63 80 06 06 beqz a3, 96 -80000334: 83 46 b4 01 lbu a3, 27(s0) -80000338: b3 d6 d7 40 sra a3, a5, a3 -8000033c: b3 88 36 03 mul a7, a3, s3 -80000340: 03 ae 45 01 lw t3, 20(a1) -80000344: 03 a3 05 01 lw t1, 16(a1) -80000348: 03 a6 c5 00 lw a2, 12(a1) -8000034c: 03 28 44 00 lw a6, 4(s0) -80000350: 03 25 84 00 lw a0, 8(s0) -80000354: 93 84 14 00 addi s1, s1, 1 -80000358: 33 07 c7 01 add a4, a4, t3 -8000035c: b3 86 66 00 add a3, a3, t1 -80000360: b3 87 17 41 sub a5, a5, a7 -80000364: 33 86 c7 00 add a2, a5, a2 -80000368: e7 00 08 00 jalr a6 -8000036c: 63 86 9a 02 beq s5, s1, 44 -80000370: 83 25 04 00 lw a1, 0(s0) -80000374: 83 47 84 01 lbu a5, 24(s0) -80000378: e3 92 07 fa bnez a5, -92 -8000037c: 33 c7 44 03 div a4, s1, s4 -80000380: 83 46 94 01 lbu a3, 25(s0) -80000384: b3 07 47 03 mul a5, a4, s4 -80000388: b3 87 f4 40 sub a5, s1, a5 -8000038c: e3 94 06 fa bnez a3, -88 -80000390: b3 c6 37 03 div a3, a5, s3 -80000394: 6f f0 9f fa j -88 -80000398: 13 39 19 00 seqz s2, s2 -8000039c: 6b 00 09 00 -800003a0: 83 20 c1 01 lw ra, 28(sp) -800003a4: 03 24 81 01 lw s0, 24(sp) -800003a8: 83 24 41 01 lw s1, 20(sp) -800003ac: 03 29 01 01 lw s2, 16(sp) -800003b0: 83 29 c1 00 lw s3, 12(sp) -800003b4: 03 2a 81 00 lw s4, 8(sp) -800003b8: 83 2a 41 00 lw s5, 4(sp) -800003bc: 13 01 01 02 addi sp, sp, 32 -800003c0: 67 80 00 00 ret +8000027c RETURN: +8000027c: 67 80 00 00 ret -800003c4 vx_spawn_kernel: -800003c4: 13 01 01 fc addi sp, sp, -64 -800003c8: 23 2e 11 02 sw ra, 60(sp) -800003cc: 23 2c 81 02 sw s0, 56(sp) -800003d0: 23 2a 91 02 sw s1, 52(sp) -800003d4: 23 28 21 03 sw s2, 48(sp) -800003d8: 23 26 31 03 sw s3, 44(sp) -800003dc: f3 28 20 fc csrr a7, 4034 -800003e0: 73 23 10 fc csrr t1, 4033 -800003e4: 73 24 00 fc csrr s0, 4032 -800003e8: f3 27 50 cc csrr a5, 3269 -800003ec: 13 07 f0 01 addi a4, zero, 31 -800003f0: 63 46 f7 0e blt a4, a5, 236 -800003f4: 03 2e 05 00 lw t3, 0(a0) -800003f8: 83 26 45 00 lw a3, 4(a0) -800003fc: 03 28 85 00 lw a6, 8(a0) -80000400: b3 0e 83 02 mul t4, t1, s0 -80000404: 13 07 10 00 addi a4, zero, 1 -80000408: b3 06 de 02 mul a3, t3, a3 -8000040c: 33 88 06 03 mul a6, a3, a6 -80000410: 63 d4 0e 01 bge t4, a6, 8 -80000414: 33 47 d8 03 div a4, a6, t4 -80000418: 63 c0 e8 0e blt a7, a4, 224 -8000041c: 63 d0 e7 0c bge a5, a4, 192 -80000420: 93 88 f8 ff addi a7, a7, -1 -80000424: b3 4e e8 02 div t4, a6, a4 -80000428: 93 84 0e 00 mv s1, t4 -8000042c: 63 96 f8 00 bne a7, a5, 12 -80000430: 33 67 e8 02 rem a4, a6, a4 -80000434: b3 04 d7 01 add s1, a4, t4 -80000438: 33 c9 84 02 div s2, s1, s0 -8000043c: b3 e4 84 02 rem s1, s1, s0 -80000440: 63 42 69 0c blt s2, t1, 196 -80000444: 93 02 10 00 addi t0, zero, 1 -80000448: 33 48 69 02 div a6, s2, t1 -8000044c: 63 06 08 00 beqz a6, 12 -80000450: 93 02 08 00 mv t0, a6 -80000454: 33 68 69 02 rem a6, s2, t1 -80000458: d3 f7 06 d0 fcvt.s.w fa5, a3 -8000045c: 93 8f f6 ff addi t6, a3, -1 -80000460: 13 0f fe ff addi t5, t3, -1 -80000464: b7 19 00 80 lui s3, 524289 -80000468: b3 f6 df 00 and a3, t6, a3 -8000046c: 93 89 49 43 addi s3, s3, 1076 -80000470: 93 b6 16 00 seqz a3, a3 -80000474: 23 22 a1 00 sw a0, 4(sp) -80000478: 23 24 b1 00 sw a1, 8(sp) -8000047c: 23 26 c1 00 sw a2, 12(sp) -80000480: 23 2a 51 00 sw t0, 20(sp) -80000484: 23 2c 01 01 sw a6, 24(sp) -80000488: 23 0e d1 00 sb a3, 28(sp) -8000048c: 33 87 fe 02 mul a4, t4, a5 -80000490: d3 8e 07 e0 fmv.x.w t4, fa5 -80000494: d3 77 0e d0 fcvt.s.w fa5, t3 -80000498: 93 97 27 00 slli a5, a5, 2 -8000049c: 33 7e cf 01 and t3, t5, t3 -800004a0: d3 88 07 e0 fmv.x.w a7, fa5 -800004a4: 93 de 7e 41 srai t4, t4, 23 -800004a8: 13 3e 1e 00 seqz t3, t3 -800004ac: 93 d8 78 41 srai a7, a7, 23 -800004b0: 93 8e 1e f8 addi t4, t4, -127 -800004b4: 93 88 18 f8 addi a7, a7, -127 -800004b8: b3 87 f9 00 add a5, s3, a5 -800004bc: 23 28 e1 00 sw a4, 16(sp) -800004c0: 13 07 41 00 addi a4, sp, 4 -800004c4: a3 0e c1 01 sb t3, 29(sp) -800004c8: 23 0f d1 01 sb t4, 30(sp) -800004cc: a3 0f 11 01 sb a7, 31(sp) -800004d0: 23 a0 e7 00 sw a4, 0(a5) -800004d4: 63 4e 20 03 bgtz s2, 60 -800004d8: 63 9c 04 04 bnez s1, 88 -800004dc: 83 20 c1 03 lw ra, 60(sp) -800004e0: 03 24 81 03 lw s0, 56(sp) -800004e4: 83 24 41 03 lw s1, 52(sp) -800004e8: 03 29 01 03 lw s2, 48(sp) -800004ec: 83 29 c1 02 lw s3, 44(sp) -800004f0: 13 01 01 04 addi sp, sp, 64 -800004f4: 67 80 00 00 ret -800004f8: 13 87 08 00 mv a4, a7 -800004fc: e3 c2 e7 f2 blt a5, a4, -220 -80000500: 6f f0 df fd j -36 -80000504: 13 08 00 00 mv a6, zero -80000508: 93 02 10 00 addi t0, zero, 1 -8000050c: 6f f0 df f4 j -180 -80000510: 13 07 09 00 mv a4, s2 -80000514: 63 54 23 01 bge t1, s2, 8 -80000518: 13 07 03 00 mv a4, t1 -8000051c: b7 07 00 80 lui a5, 524288 -80000520: 93 87 c7 27 addi a5, a5, 636 -80000524: 6b 10 f7 00 -80000528: ef f0 5f d5 jal -684 -8000052c: e3 88 04 fa beqz s1, -80 -80000530: 33 04 89 02 mul s0, s2, s0 -80000534: 23 28 81 00 sw s0, 16(sp) -80000538: 6b 80 04 00 -8000053c: 73 27 50 cc csrr a4, 3269 -80000540: f3 27 20 cc csrr a5, 3266 -80000544: 13 17 27 00 slli a4, a4, 2 -80000548: b3 89 e9 00 add s3, s3, a4 -8000054c: 03 a5 09 00 lw a0, 0(s3) -80000550: 83 25 05 00 lw a1, 0(a0) -80000554: 83 26 c5 00 lw a3, 12(a0) -80000558: 03 47 85 01 lbu a4, 24(a0) -8000055c: 03 a8 05 00 lw a6, 0(a1) -80000560: 03 a6 45 00 lw a2, 4(a1) -80000564: b3 87 d7 00 add a5, a5, a3 -80000568: 33 06 c8 02 mul a2, a6, a2 -8000056c: 63 0e 07 06 beqz a4, 124 -80000570: 03 47 a5 01 lbu a4, 26(a0) -80000574: 33 d7 e7 40 sra a4, a5, a4 -80000578: 83 46 95 01 lbu a3, 25(a0) -8000057c: 33 06 e6 02 mul a2, a2, a4 -80000580: b3 87 c7 40 sub a5, a5, a2 -80000584: 63 8e 06 04 beqz a3, 92 -80000588: 83 48 b5 01 lbu a7, 27(a0) -8000058c: b3 d8 17 41 sra a7, a5, a7 -80000590: 33 08 18 03 mul a6, a6, a7 -80000594: 03 ae 45 01 lw t3, 20(a1) -80000598: 83 a6 05 01 lw a3, 16(a1) -8000059c: 03 a6 c5 00 lw a2, 12(a1) -800005a0: 03 23 45 00 lw t1, 4(a0) -800005a4: 03 25 85 00 lw a0, 8(a0) -800005a8: 33 07 c7 01 add a4, a4, t3 -800005ac: b3 86 d8 00 add a3, a7, a3 -800005b0: b3 87 07 41 sub a5, a5, a6 -800005b4: 33 86 c7 00 add a2, a5, a2 -800005b8: e7 00 03 00 jalr t1 -800005bc: 93 07 10 00 addi a5, zero, 1 -800005c0: 6b 80 07 00 -800005c4: 83 20 c1 03 lw ra, 60(sp) -800005c8: 03 24 81 03 lw s0, 56(sp) -800005cc: 83 24 41 03 lw s1, 52(sp) -800005d0: 03 29 01 03 lw s2, 48(sp) -800005d4: 83 29 c1 02 lw s3, 44(sp) -800005d8: 13 01 01 04 addi sp, sp, 64 -800005dc: 67 80 00 00 ret -800005e0: b3 c8 07 03 div a7, a5, a6 -800005e4: 6f f0 df fa j -84 -800005e8: 33 c7 c7 02 div a4, a5, a2 -800005ec: 6f f0 df f8 j -116 +80000280 __libc_init_array: +80000280: 13 01 01 ff addi sp, sp, -16 +80000284: 23 24 81 00 sw s0, 8(sp) +80000288: 23 20 21 01 sw s2, 0(sp) +8000028c: 37 14 00 80 lui s0, 524289 +80000290: 37 19 00 80 lui s2, 524289 +80000294: 93 07 04 00 mv a5, s0 +80000298: 13 09 09 00 mv s2, s2 +8000029c: 33 09 f9 40 sub s2, s2, a5 +800002a0: 23 26 11 00 sw ra, 12(sp) +800002a4: 23 22 91 00 sw s1, 4(sp) +800002a8: 13 59 29 40 srai s2, s2, 2 +800002ac: 63 00 09 02 beqz s2, 32 +800002b0: 13 04 04 00 mv s0, s0 +800002b4: 93 04 00 00 mv s1, zero +800002b8: 83 27 04 00 lw a5, 0(s0) +800002bc: 93 84 14 00 addi s1, s1, 1 +800002c0: 13 04 44 00 addi s0, s0, 4 +800002c4: e7 80 07 00 jalr a5 +800002c8: e3 18 99 fe bne s2, s1, -16 +800002cc: 37 14 00 80 lui s0, 524289 +800002d0: 37 19 00 80 lui s2, 524289 +800002d4: 93 07 04 00 mv a5, s0 +800002d8: 13 09 49 00 addi s2, s2, 4 +800002dc: 33 09 f9 40 sub s2, s2, a5 +800002e0: 13 59 29 40 srai s2, s2, 2 +800002e4: 63 00 09 02 beqz s2, 32 +800002e8: 13 04 04 00 mv s0, s0 +800002ec: 93 04 00 00 mv s1, zero +800002f0: 83 27 04 00 lw a5, 0(s0) +800002f4: 93 84 14 00 addi s1, s1, 1 +800002f8: 13 04 44 00 addi s0, s0, 4 +800002fc: e7 80 07 00 jalr a5 +80000300: e3 18 99 fe bne s2, s1, -16 +80000304: 83 20 c1 00 lw ra, 12(sp) +80000308: 03 24 81 00 lw s0, 8(sp) +8000030c: 83 24 41 00 lw s1, 4(sp) +80000310: 03 29 01 00 lw s2, 0(sp) +80000314: 13 01 01 01 addi sp, sp, 16 +80000318: 67 80 00 00 ret -800005f0 vx_perf_dump: -800005f0: f3 27 50 cc csrr a5, 3269 -800005f4: 37 07 ff 00 lui a4, 4080 -800005f8: b3 87 e7 00 add a5, a5, a4 -800005fc: 93 97 87 00 slli a5, a5, 8 -80000600: 73 27 00 b0 csrr a4, mcycle -80000604: 23 a0 e7 00 sw a4, 0(a5) -80000608: 73 27 10 b0 csrr a4, 2817 -8000060c: 23 a2 e7 00 sw a4, 4(a5) -80000610: 73 27 20 b0 csrr a4, minstret -80000614: 23 a4 e7 00 sw a4, 8(a5) -80000618: 73 27 30 b0 csrr a4, mhpmcounter3 -8000061c: 23 a6 e7 00 sw a4, 12(a5) -80000620: 73 27 40 b0 csrr a4, mhpmcounter4 -80000624: 23 a8 e7 00 sw a4, 16(a5) -80000628: 73 27 50 b0 csrr a4, mhpmcounter5 -8000062c: 23 aa e7 00 sw a4, 20(a5) -80000630: 73 27 60 b0 csrr a4, mhpmcounter6 -80000634: 23 ac e7 00 sw a4, 24(a5) -80000638: 73 27 70 b0 csrr a4, mhpmcounter7 -8000063c: 23 ae e7 00 sw a4, 28(a5) -80000640: 73 27 80 b0 csrr a4, mhpmcounter8 -80000644: 23 a0 e7 02 sw a4, 32(a5) -80000648: 73 27 90 b0 csrr a4, mhpmcounter9 -8000064c: 23 a2 e7 02 sw a4, 36(a5) -80000650: 73 27 a0 b0 csrr a4, mhpmcounter10 -80000654: 23 a4 e7 02 sw a4, 40(a5) -80000658: 73 27 b0 b0 csrr a4, mhpmcounter11 -8000065c: 23 a6 e7 02 sw a4, 44(a5) -80000660: 73 27 c0 b0 csrr a4, mhpmcounter12 -80000664: 23 a8 e7 02 sw a4, 48(a5) -80000668: 73 27 d0 b0 csrr a4, mhpmcounter13 -8000066c: 23 aa e7 02 sw a4, 52(a5) -80000670: 73 27 e0 b0 csrr a4, mhpmcounter14 -80000674: 23 ac e7 02 sw a4, 56(a5) -80000678: 73 27 f0 b0 csrr a4, mhpmcounter15 -8000067c: 23 ae e7 02 sw a4, 60(a5) -80000680: 73 27 00 b1 csrr a4, mhpmcounter16 -80000684: 23 a0 e7 04 sw a4, 64(a5) -80000688: 73 27 10 b1 csrr a4, mhpmcounter17 -8000068c: 23 a2 e7 04 sw a4, 68(a5) -80000690: 73 27 20 b1 csrr a4, mhpmcounter18 -80000694: 23 a4 e7 04 sw a4, 72(a5) -80000698: 73 27 30 b1 csrr a4, mhpmcounter19 -8000069c: 23 a6 e7 04 sw a4, 76(a5) -800006a0: 73 27 40 b1 csrr a4, mhpmcounter20 -800006a4: 23 a8 e7 04 sw a4, 80(a5) -800006a8: 73 27 50 b1 csrr a4, mhpmcounter21 -800006ac: 23 aa e7 04 sw a4, 84(a5) -800006b0: 73 27 60 b1 csrr a4, mhpmcounter22 -800006b4: 23 ac e7 04 sw a4, 88(a5) -800006b8: 73 27 70 b1 csrr a4, mhpmcounter23 -800006bc: 23 ae e7 04 sw a4, 92(a5) -800006c0: 73 27 80 b1 csrr a4, mhpmcounter24 -800006c4: 23 a0 e7 06 sw a4, 96(a5) -800006c8: 73 27 90 b1 csrr a4, mhpmcounter25 -800006cc: 23 a2 e7 06 sw a4, 100(a5) -800006d0: 73 27 a0 b1 csrr a4, mhpmcounter26 -800006d4: 23 a4 e7 06 sw a4, 104(a5) -800006d8: 73 27 b0 b1 csrr a4, mhpmcounter27 -800006dc: 23 a6 e7 06 sw a4, 108(a5) -800006e0: 73 27 c0 b1 csrr a4, mhpmcounter28 -800006e4: 23 a8 e7 06 sw a4, 112(a5) -800006e8: 73 27 d0 b1 csrr a4, mhpmcounter29 -800006ec: 23 aa e7 06 sw a4, 116(a5) -800006f0: 73 27 e0 b1 csrr a4, mhpmcounter30 -800006f4: 23 ac e7 06 sw a4, 120(a5) -800006f8: 73 27 f0 b1 csrr a4, mhpmcounter31 -800006fc: 23 ae e7 06 sw a4, 124(a5) -80000700: 73 27 00 b8 csrr a4, mcycleh -80000704: 23 a0 e7 08 sw a4, 128(a5) -80000708: 73 27 10 b8 csrr a4, 2945 -8000070c: 23 a2 e7 08 sw a4, 132(a5) -80000710: 73 27 20 b8 csrr a4, minstreth -80000714: 23 a4 e7 08 sw a4, 136(a5) -80000718: 73 27 30 b8 csrr a4, mhpmcounter3h -8000071c: 23 a6 e7 08 sw a4, 140(a5) -80000720: 73 27 40 b8 csrr a4, mhpmcounter4h -80000724: 23 a8 e7 08 sw a4, 144(a5) -80000728: 73 27 50 b8 csrr a4, mhpmcounter5h -8000072c: 23 aa e7 08 sw a4, 148(a5) -80000730: 73 27 60 b8 csrr a4, mhpmcounter6h -80000734: 23 ac e7 08 sw a4, 152(a5) -80000738: 73 27 70 b8 csrr a4, mhpmcounter7h -8000073c: 23 ae e7 08 sw a4, 156(a5) -80000740: 73 27 80 b8 csrr a4, mhpmcounter8h -80000744: 23 a0 e7 0a sw a4, 160(a5) -80000748: 73 27 90 b8 csrr a4, mhpmcounter9h -8000074c: 23 a2 e7 0a sw a4, 164(a5) -80000750: 73 27 a0 b8 csrr a4, mhpmcounter10h -80000754: 23 a4 e7 0a sw a4, 168(a5) -80000758: 73 27 b0 b8 csrr a4, mhpmcounter11h -8000075c: 23 a6 e7 0a sw a4, 172(a5) -80000760: 73 27 c0 b8 csrr a4, mhpmcounter12h -80000764: 23 a8 e7 0a sw a4, 176(a5) -80000768: 73 27 d0 b8 csrr a4, mhpmcounter13h -8000076c: 23 aa e7 0a sw a4, 180(a5) -80000770: 73 27 e0 b8 csrr a4, mhpmcounter14h -80000774: 23 ac e7 0a sw a4, 184(a5) -80000778: 73 27 f0 b8 csrr a4, mhpmcounter15h -8000077c: 23 ae e7 0a sw a4, 188(a5) -80000780: 73 27 00 b9 csrr a4, mhpmcounter16h -80000784: 23 a0 e7 0c sw a4, 192(a5) -80000788: 73 27 10 b9 csrr a4, mhpmcounter17h -8000078c: 23 a2 e7 0c sw a4, 196(a5) -80000790: 73 27 20 b9 csrr a4, mhpmcounter18h -80000794: 23 a4 e7 0c sw a4, 200(a5) -80000798: 73 27 30 b9 csrr a4, mhpmcounter19h -8000079c: 23 a6 e7 0c sw a4, 204(a5) -800007a0: 73 27 40 b9 csrr a4, mhpmcounter20h -800007a4: 23 a8 e7 0c sw a4, 208(a5) -800007a8: 73 27 50 b9 csrr a4, mhpmcounter21h -800007ac: 23 aa e7 0c sw a4, 212(a5) -800007b0: 73 27 60 b9 csrr a4, mhpmcounter22h -800007b4: 23 ac e7 0c sw a4, 216(a5) -800007b8: 73 27 70 b9 csrr a4, mhpmcounter23h -800007bc: 23 ae e7 0c sw a4, 220(a5) -800007c0: 73 27 80 b9 csrr a4, mhpmcounter24h -800007c4: 23 a0 e7 0e sw a4, 224(a5) -800007c8: 73 27 90 b9 csrr a4, mhpmcounter25h -800007cc: 23 a2 e7 0e sw a4, 228(a5) -800007d0: 73 27 a0 b9 csrr a4, mhpmcounter26h -800007d4: 23 a4 e7 0e sw a4, 232(a5) -800007d8: 73 27 b0 b9 csrr a4, mhpmcounter27h -800007dc: 23 a6 e7 0e sw a4, 236(a5) -800007e0: 73 27 c0 b9 csrr a4, mhpmcounter28h -800007e4: 23 a8 e7 0e sw a4, 240(a5) -800007e8: 73 27 d0 b9 csrr a4, mhpmcounter29h -800007ec: 23 aa e7 0e sw a4, 244(a5) -800007f0: 73 27 e0 b9 csrr a4, mhpmcounter30h -800007f4: 23 ac e7 0e sw a4, 248(a5) -800007f8: 73 27 f0 b9 csrr a4, mhpmcounter31h -800007fc: 23 ae e7 0e sw a4, 252(a5) -80000800: 67 80 00 00 ret +8000031c __libc_fini_array: +8000031c: 13 01 01 ff addi sp, sp, -16 +80000320: 23 24 81 00 sw s0, 8(sp) +80000324: b7 17 00 80 lui a5, 524289 +80000328: 37 14 00 80 lui s0, 524289 +8000032c: 13 04 44 00 addi s0, s0, 4 +80000330: 93 87 47 00 addi a5, a5, 4 +80000334: b3 87 87 40 sub a5, a5, s0 +80000338: 23 22 91 00 sw s1, 4(sp) +8000033c: 23 26 11 00 sw ra, 12(sp) +80000340: 93 d4 27 40 srai s1, a5, 2 +80000344: 63 80 04 02 beqz s1, 32 +80000348: 93 87 c7 ff addi a5, a5, -4 +8000034c: 33 84 87 00 add s0, a5, s0 +80000350: 83 27 04 00 lw a5, 0(s0) +80000354: 93 84 f4 ff addi s1, s1, -1 +80000358: 13 04 c4 ff addi s0, s0, -4 +8000035c: e7 80 07 00 jalr a5 +80000360: e3 98 04 fe bnez s1, -16 +80000364: 83 20 c1 00 lw ra, 12(sp) +80000368: 03 24 81 00 lw s0, 8(sp) +8000036c: 83 24 41 00 lw s1, 4(sp) +80000370: 13 01 01 01 addi sp, sp, 16 +80000374: 67 80 00 00 ret -80000804 atexit: -80000804: 93 05 05 00 mv a1, a0 -80000808: 93 06 00 00 mv a3, zero -8000080c: 13 06 00 00 mv a2, zero -80000810: 13 05 00 00 mv a0, zero -80000814: 6f 00 c0 20 j 524 +80000378 spawn_kernel_all_stub: +80000378: 13 01 01 fe addi sp, sp, -32 +8000037c: 23 2e 11 00 sw ra, 28(sp) +80000380: 23 2c 81 00 sw s0, 24(sp) +80000384: 23 2a 91 00 sw s1, 20(sp) +80000388: 23 28 21 01 sw s2, 16(sp) +8000038c: 23 26 31 01 sw s3, 12(sp) +80000390: 23 24 41 01 sw s4, 8(sp) +80000394: 73 26 50 cc csrr a2, 3269 +80000398: 73 27 30 cc csrr a4, 3267 +8000039c: f3 26 00 cc csrr a3, 3264 +800003a0: 73 25 00 fc csrr a0, 4032 +800003a4: b7 17 00 80 lui a5, 524289 +800003a8: 13 16 26 00 slli a2, a2, 2 +800003ac: 93 87 47 43 addi a5, a5, 1076 +800003b0: b3 87 c7 00 add a5, a5, a2 +800003b4: 03 a4 07 00 lw s0, 0(a5) +800003b8: 83 24 44 01 lw s1, 20(s0) +800003bc: 03 26 04 01 lw a2, 16(s0) +800003c0: 33 2a 97 00 slt s4, a4, s1 +800003c4: 93 87 04 00 mv a5, s1 +800003c8: 33 0a ca 00 add s4, s4, a2 +800003cc: b3 04 e6 02 mul s1, a2, a4 +800003d0: 63 54 f7 00 bge a4, a5, 8 +800003d4: 93 07 07 00 mv a5, a4 +800003d8: b3 84 f4 00 add s1, s1, a5 +800003dc: 83 25 04 00 lw a1, 0(s0) +800003e0: 03 27 c4 00 lw a4, 12(s0) +800003e4: 03 a9 05 00 lw s2, 0(a1) +800003e8: 83 a9 45 00 lw s3, 4(a1) +800003ec: b3 84 a4 02 mul s1, s1, a0 +800003f0: b3 07 da 02 mul a5, s4, a3 +800003f4: b3 84 e4 00 add s1, s1, a4 +800003f8: b3 84 f4 00 add s1, s1, a5 +800003fc: 33 0a 9a 00 add s4, s4, s1 +80000400: b3 09 39 03 mul s3, s2, s3 +80000404: 63 c0 44 07 blt s1, s4, 96 +80000408: 6f 00 00 08 j 128 +8000040c: 03 47 e4 01 lbu a4, 30(s0) +80000410: 83 46 d4 01 lbu a3, 29(s0) +80000414: 33 d7 e4 40 sra a4, s1, a4 +80000418: b3 07 37 03 mul a5, a4, s3 +8000041c: b3 87 f4 40 sub a5, s1, a5 +80000420: 63 80 06 06 beqz a3, 96 +80000424: 83 46 f4 01 lbu a3, 31(s0) +80000428: b3 d6 d7 40 sra a3, a5, a3 +8000042c: b3 88 26 03 mul a7, a3, s2 +80000430: 03 ae 45 01 lw t3, 20(a1) +80000434: 03 a3 05 01 lw t1, 16(a1) +80000438: 03 a6 c5 00 lw a2, 12(a1) +8000043c: 03 28 44 00 lw a6, 4(s0) +80000440: 03 25 84 00 lw a0, 8(s0) +80000444: 93 84 14 00 addi s1, s1, 1 +80000448: 33 07 c7 01 add a4, a4, t3 +8000044c: b3 86 66 00 add a3, a3, t1 +80000450: b3 87 17 41 sub a5, a5, a7 +80000454: 33 86 c7 00 add a2, a5, a2 +80000458: e7 00 08 00 jalr a6 +8000045c: 63 06 9a 02 beq s4, s1, 44 +80000460: 83 25 04 00 lw a1, 0(s0) +80000464: 83 47 c4 01 lbu a5, 28(s0) +80000468: e3 92 07 fa bnez a5, -92 +8000046c: 33 c7 34 03 div a4, s1, s3 +80000470: 83 46 d4 01 lbu a3, 29(s0) +80000474: b3 07 37 03 mul a5, a4, s3 +80000478: b3 87 f4 40 sub a5, s1, a5 +8000047c: e3 94 06 fa bnez a3, -88 +80000480: b3 c6 27 03 div a3, a5, s2 +80000484: 6f f0 9f fa j -88 +80000488: 03 27 84 01 lw a4, 24(s0) +8000048c: 93 07 00 00 mv a5, zero +80000490: 6b c0 e7 00 vx_bar a5, a4 +80000494: 83 20 c1 01 lw ra, 28(sp) +80000498: 03 24 81 01 lw s0, 24(sp) +8000049c: 83 24 41 01 lw s1, 20(sp) +800004a0: 03 29 01 01 lw s2, 16(sp) +800004a4: 83 29 c1 00 lw s3, 12(sp) +800004a8: 03 2a 81 00 lw s4, 8(sp) +800004ac: 13 01 01 02 addi sp, sp, 32 +800004b0: 67 80 00 00 ret -80000818 exit: -80000818: 13 01 01 ff addi sp, sp, -16 -8000081c: 93 05 00 00 mv a1, zero -80000820: 23 24 81 00 sw s0, 8(sp) -80000824: 23 26 11 00 sw ra, 12(sp) -80000828: 13 04 05 00 mv s0, a0 -8000082c: ef 00 00 29 jal 656 -80000830: b7 17 00 80 lui a5, 524289 -80000834: 03 a5 07 43 lw a0, 1072(a5) -80000838: 83 27 c5 03 lw a5, 60(a0) -8000083c: 63 84 07 00 beqz a5, 8 -80000840: e7 80 07 00 jalr a5 -80000844: 13 05 04 00 mv a0, s0 -80000848: ef f0 df 9e jal -1556 +800004b4 spawn_kernel_rem_stub: +800004b4: f3 26 50 cc csrr a3, 3269 +800004b8: f3 27 20 cc csrr a5, 3266 +800004bc: 37 17 00 80 lui a4, 524289 +800004c0: 93 96 26 00 slli a3, a3, 2 +800004c4: 13 07 47 43 addi a4, a4, 1076 +800004c8: 33 07 d7 00 add a4, a4, a3 +800004cc: 03 25 07 00 lw a0, 0(a4) +800004d0: 83 25 05 00 lw a1, 0(a0) +800004d4: 83 26 c5 00 lw a3, 12(a0) +800004d8: 03 47 c5 01 lbu a4, 28(a0) +800004dc: 83 a8 05 00 lw a7, 0(a1) +800004e0: 03 a6 45 00 lw a2, 4(a1) +800004e4: b3 87 d7 00 add a5, a5, a3 +800004e8: 33 86 c8 02 mul a2, a7, a2 +800004ec: 63 08 07 04 beqz a4, 80 +800004f0: 03 47 e5 01 lbu a4, 30(a0) +800004f4: 83 46 d5 01 lbu a3, 29(a0) +800004f8: 33 d7 e7 40 sra a4, a5, a4 +800004fc: 33 06 c7 02 mul a2, a4, a2 +80000500: b3 87 c7 40 sub a5, a5, a2 +80000504: 63 86 06 04 beqz a3, 76 +80000508: 83 46 f5 01 lbu a3, 31(a0) +8000050c: 33 d8 d7 40 sra a6, a5, a3 +80000510: 83 a6 05 01 lw a3, 16(a1) +80000514: 03 ae 45 01 lw t3, 20(a1) +80000518: 03 a6 c5 00 lw a2, 12(a1) +8000051c: b3 06 d8 00 add a3, a6, a3 +80000520: 33 08 18 03 mul a6, a6, a7 +80000524: 03 23 45 00 lw t1, 4(a0) +80000528: 03 25 85 00 lw a0, 8(a0) +8000052c: 33 07 c7 01 add a4, a4, t3 +80000530: b3 87 07 41 sub a5, a5, a6 +80000534: 33 86 c7 00 add a2, a5, a2 +80000538: 67 00 03 00 jr t1 +8000053c: 33 c7 c7 02 div a4, a5, a2 +80000540: 83 46 d5 01 lbu a3, 29(a0) +80000544: 33 06 c7 02 mul a2, a4, a2 +80000548: b3 87 c7 40 sub a5, a5, a2 +8000054c: e3 9e 06 fa bnez a3, -68 +80000550: 33 c8 17 03 div a6, a5, a7 +80000554: 6f f0 df fb j -68 -8000084c __libc_fini_array: -8000084c: 13 01 01 ff addi sp, sp, -16 -80000850: 23 24 81 00 sw s0, 8(sp) -80000854: b7 17 00 80 lui a5, 524289 -80000858: 37 14 00 80 lui s0, 524289 -8000085c: 13 04 44 00 addi s0, s0, 4 -80000860: 93 87 47 00 addi a5, a5, 4 -80000864: b3 87 87 40 sub a5, a5, s0 -80000868: 23 22 91 00 sw s1, 4(sp) -8000086c: 23 26 11 00 sw ra, 12(sp) -80000870: 93 d4 27 40 srai s1, a5, 2 -80000874: 63 80 04 02 beqz s1, 32 -80000878: 93 87 c7 ff addi a5, a5, -4 -8000087c: 33 84 87 00 add s0, a5, s0 -80000880: 83 27 04 00 lw a5, 0(s0) -80000884: 93 84 f4 ff addi s1, s1, -1 -80000888: 13 04 c4 ff addi s0, s0, -4 -8000088c: e7 80 07 00 jalr a5 -80000890: e3 98 04 fe bnez s1, -16 -80000894: 83 20 c1 00 lw ra, 12(sp) -80000898: 03 24 81 00 lw s0, 8(sp) -8000089c: 83 24 41 00 lw s1, 4(sp) -800008a0: 13 01 01 01 addi sp, sp, 16 -800008a4: 67 80 00 00 ret +80000558 spawn_kernel_all_cb: +80000558: 13 01 01 ff addi sp, sp, -16 +8000055c: 23 26 11 00 sw ra, 12(sp) +80000560: 93 07 f0 ff addi a5, zero, -1 +80000564: 6b 80 07 00 vx_tmc a5 +80000568: ef f0 1f e1 jal -496 +8000056c: f3 27 30 cc csrr a5, 3267 +80000570: 93 b7 17 00 seqz a5, a5 +80000574: 6b 80 07 00 vx_tmc a5 +80000578: 83 20 c1 00 lw ra, 12(sp) +8000057c: 13 01 01 01 addi sp, sp, 16 +80000580: 67 80 00 00 ret -800008a8 __libc_init_array: -800008a8: 13 01 01 ff addi sp, sp, -16 -800008ac: 23 24 81 00 sw s0, 8(sp) -800008b0: 23 20 21 01 sw s2, 0(sp) -800008b4: 37 14 00 80 lui s0, 524289 -800008b8: 37 19 00 80 lui s2, 524289 -800008bc: 93 07 04 00 mv a5, s0 -800008c0: 13 09 09 00 mv s2, s2 -800008c4: 33 09 f9 40 sub s2, s2, a5 -800008c8: 23 26 11 00 sw ra, 12(sp) -800008cc: 23 22 91 00 sw s1, 4(sp) -800008d0: 13 59 29 40 srai s2, s2, 2 -800008d4: 63 00 09 02 beqz s2, 32 -800008d8: 13 04 04 00 mv s0, s0 -800008dc: 93 04 00 00 mv s1, zero -800008e0: 83 27 04 00 lw a5, 0(s0) -800008e4: 93 84 14 00 addi s1, s1, 1 -800008e8: 13 04 44 00 addi s0, s0, 4 -800008ec: e7 80 07 00 jalr a5 -800008f0: e3 18 99 fe bne s2, s1, -16 -800008f4: 37 14 00 80 lui s0, 524289 -800008f8: 37 19 00 80 lui s2, 524289 -800008fc: 93 07 04 00 mv a5, s0 -80000900: 13 09 49 00 addi s2, s2, 4 -80000904: 33 09 f9 40 sub s2, s2, a5 -80000908: 13 59 29 40 srai s2, s2, 2 -8000090c: 63 00 09 02 beqz s2, 32 -80000910: 13 04 04 00 mv s0, s0 -80000914: 93 04 00 00 mv s1, zero -80000918: 83 27 04 00 lw a5, 0(s0) -8000091c: 93 84 14 00 addi s1, s1, 1 -80000920: 13 04 44 00 addi s0, s0, 4 -80000924: e7 80 07 00 jalr a5 -80000928: e3 18 99 fe bne s2, s1, -16 -8000092c: 83 20 c1 00 lw ra, 12(sp) -80000930: 03 24 81 00 lw s0, 8(sp) -80000934: 83 24 41 00 lw s1, 4(sp) -80000938: 03 29 01 00 lw s2, 0(sp) -8000093c: 13 01 01 01 addi sp, sp, 16 -80000940: 67 80 00 00 ret +80000584 vx_spawn_kernel: +80000584: 13 01 01 fd addi sp, sp, -48 +80000588: 23 26 11 02 sw ra, 44(sp) +8000058c: 23 24 81 02 sw s0, 40(sp) +80000590: 23 22 91 02 sw s1, 36(sp) +80000594: 23 20 21 03 sw s2, 32(sp) +80000598: f3 28 20 fc csrr a7, 4034 +8000059c: 73 23 10 fc csrr t1, 4033 +800005a0: f3 24 00 fc csrr s1, 4032 +800005a4: f3 27 50 cc csrr a5, 3269 +800005a8: 13 07 f0 01 addi a4, zero, 31 +800005ac: 63 46 f7 0e blt a4, a5, 236 +800005b0: 03 2e 05 00 lw t3, 0(a0) +800005b4: 83 26 45 00 lw a3, 4(a0) +800005b8: 03 28 85 00 lw a6, 8(a0) +800005bc: b3 0e 93 02 mul t4, t1, s1 +800005c0: 13 07 10 00 addi a4, zero, 1 +800005c4: b3 06 de 02 mul a3, t3, a3 +800005c8: 33 88 06 03 mul a6, a3, a6 +800005cc: 63 d4 0e 01 bge t4, a6, 8 +800005d0: 33 47 d8 03 div a4, a6, t4 +800005d4: 63 ce e8 0c blt a7, a4, 220 +800005d8: 63 d0 e7 0c bge a5, a4, 192 +800005dc: 93 88 f8 ff addi a7, a7, -1 +800005e0: b3 4e e8 02 div t4, a6, a4 +800005e4: 13 84 0e 00 mv s0, t4 +800005e8: 63 96 f8 00 bne a7, a5, 12 +800005ec: 33 67 e8 02 rem a4, a6, a4 +800005f0: 33 04 d7 01 add s0, a4, t4 +800005f4: 33 49 94 02 div s2, s0, s1 +800005f8: 33 64 94 02 rem s0, s0, s1 +800005fc: 63 40 69 0c blt s2, t1, 192 +80000600: 93 0f 10 00 addi t6, zero, 1 +80000604: 33 4f 69 02 div t5, s2, t1 +80000608: 63 06 0f 00 beqz t5, 12 +8000060c: 93 0f 0f 00 mv t6, t5 +80000610: 33 6f 69 02 rem t5, s2, t1 +80000614: d3 f7 06 d0 fcvt.s.w fa5, a3 +80000618: 13 07 fe ff addi a4, t3, -1 +8000061c: 93 82 f6 ff addi t0, a3, -1 +80000620: d3 88 07 e0 fmv.x.w a7, fa5 +80000624: d3 77 0e d0 fcvt.s.w fa5, t3 +80000628: 33 7e c7 01 and t3, a4, t3 +8000062c: 37 17 00 80 lui a4, 524289 +80000630: 53 88 07 e0 fmv.x.w a6, fa5 +80000634: b3 f6 d2 00 and a3, t0, a3 +80000638: 93 d8 78 41 srai a7, a7, 23 +8000063c: 13 58 78 41 srai a6, a6, 23 +80000640: 13 07 47 43 addi a4, a4, 1076 +80000644: 93 b6 16 00 seqz a3, a3 +80000648: 13 3e 1e 00 seqz t3, t3 +8000064c: 93 88 18 f8 addi a7, a7, -127 +80000650: 13 08 18 f8 addi a6, a6, -127 +80000654: 23 20 a1 00 sw a0, 0(sp) +80000658: 23 22 b1 00 sw a1, 4(sp) +8000065c: 23 24 c1 00 sw a2, 8(sp) +80000660: 23 28 f1 01 sw t6, 16(sp) +80000664: 23 2a e1 01 sw t5, 20(sp) +80000668: 23 2c 01 00 sw zero, 24(sp) +8000066c: 23 0e d1 00 sb a3, 28(sp) +80000670: a3 0e c1 01 sb t3, 29(sp) +80000674: 23 0f 11 01 sb a7, 30(sp) +80000678: a3 0f 01 01 sb a6, 31(sp) +8000067c: b3 8e fe 02 mul t4, t4, a5 +80000680: 93 97 27 00 slli a5, a5, 2 +80000684: b3 07 f7 00 add a5, a4, a5 +80000688: 23 a0 27 00 sw sp, 0(a5) +8000068c: 23 26 d1 01 sw t4, 12(sp) +80000690: 63 4c 20 03 bgtz s2, 56 +80000694: 63 16 04 06 bnez s0, 108 +80000698: 83 20 c1 02 lw ra, 44(sp) +8000069c: 03 24 81 02 lw s0, 40(sp) +800006a0: 83 24 41 02 lw s1, 36(sp) +800006a4: 03 29 01 02 lw s2, 32(sp) +800006a8: 13 01 01 03 addi sp, sp, 48 +800006ac: 67 80 00 00 ret +800006b0: 13 87 08 00 mv a4, a7 +800006b4: e3 c4 e7 f2 blt a5, a4, -216 +800006b8: 6f f0 1f fe j -32 +800006bc: 13 0f 00 00 mv t5, zero +800006c0: 93 0f 10 00 addi t6, zero, 1 +800006c4: 6f f0 1f f5 j -176 +800006c8: 13 07 09 00 mv a4, s2 +800006cc: 63 54 23 01 bge t1, s2, 8 +800006d0: 13 07 03 00 mv a4, t1 +800006d4: b7 07 00 80 lui a5, 524288 +800006d8: 23 2c e1 00 sw a4, 24(sp) +800006dc: 93 87 87 55 addi a5, a5, 1368 +800006e0: 6b 10 f7 00 vx_wspawn a4, a5 +800006e4: 93 07 f0 ff addi a5, zero, -1 +800006e8: 6b 80 07 00 vx_tmc a5 +800006ec: ef f0 df c8 jal -884 +800006f0: f3 27 30 cc csrr a5, 3267 +800006f4: 93 b7 17 00 seqz a5, a5 +800006f8: 6b 80 07 00 vx_tmc a5 +800006fc: e3 0e 04 f8 beqz s0, -100 +80000700: b3 04 99 02 mul s1, s2, s1 +80000704: 13 09 10 00 addi s2, zero, 1 +80000708: 33 14 89 00 sll s0, s2, s0 +8000070c: 13 04 f4 ff addi s0, s0, -1 +80000710: 23 26 91 00 sw s1, 12(sp) +80000714: 6b 00 04 00 vx_tmc s0 +80000718: ef f0 df d9 jal -612 +8000071c: 6b 00 09 00 vx_tmc s2 +80000720: 83 20 c1 02 lw ra, 44(sp) +80000724: 03 24 81 02 lw s0, 40(sp) +80000728: 83 24 41 02 lw s1, 36(sp) +8000072c: 03 29 01 02 lw s2, 32(sp) +80000730: 13 01 01 03 addi sp, sp, 48 +80000734: 67 80 00 00 ret -80000944 memset: -80000944: 13 03 f0 00 addi t1, zero, 15 -80000948: 13 07 05 00 mv a4, a0 -8000094c: 63 7e c3 02 bgeu t1, a2, 60 -80000950: 93 77 f7 00 andi a5, a4, 15 -80000954: 63 90 07 0a bnez a5, 160 -80000958: 63 92 05 08 bnez a1, 132 -8000095c: 93 76 06 ff andi a3, a2, -16 -80000960: 13 76 f6 00 andi a2, a2, 15 -80000964: b3 86 e6 00 add a3, a3, a4 -80000968: 23 20 b7 00 sw a1, 0(a4) -8000096c: 23 22 b7 00 sw a1, 4(a4) -80000970: 23 24 b7 00 sw a1, 8(a4) -80000974: 23 26 b7 00 sw a1, 12(a4) -80000978: 13 07 07 01 addi a4, a4, 16 -8000097c: e3 66 d7 fe bltu a4, a3, -20 -80000980: 63 14 06 00 bnez a2, 8 -80000984: 67 80 00 00 ret -80000988: b3 06 c3 40 sub a3, t1, a2 -8000098c: 93 96 26 00 slli a3, a3, 2 -80000990: 97 02 00 00 auipc t0, 0 -80000994: b3 86 56 00 add a3, a3, t0 -80000998: 67 80 c6 00 jr 12(a3) -8000099c: 23 07 b7 00 sb a1, 14(a4) -800009a0: a3 06 b7 00 sb a1, 13(a4) -800009a4: 23 06 b7 00 sb a1, 12(a4) -800009a8: a3 05 b7 00 sb a1, 11(a4) -800009ac: 23 05 b7 00 sb a1, 10(a4) -800009b0: a3 04 b7 00 sb a1, 9(a4) -800009b4: 23 04 b7 00 sb a1, 8(a4) -800009b8: a3 03 b7 00 sb a1, 7(a4) -800009bc: 23 03 b7 00 sb a1, 6(a4) -800009c0: a3 02 b7 00 sb a1, 5(a4) -800009c4: 23 02 b7 00 sb a1, 4(a4) -800009c8: a3 01 b7 00 sb a1, 3(a4) -800009cc: 23 01 b7 00 sb a1, 2(a4) -800009d0: a3 00 b7 00 sb a1, 1(a4) -800009d4: 23 00 b7 00 sb a1, 0(a4) -800009d8: 67 80 00 00 ret -800009dc: 93 f5 f5 0f andi a1, a1, 255 -800009e0: 93 96 85 00 slli a3, a1, 8 -800009e4: b3 e5 d5 00 or a1, a1, a3 -800009e8: 93 96 05 01 slli a3, a1, 16 -800009ec: b3 e5 d5 00 or a1, a1, a3 -800009f0: 6f f0 df f6 j -148 -800009f4: 93 96 27 00 slli a3, a5, 2 -800009f8: 97 02 00 00 auipc t0, 0 -800009fc: b3 86 56 00 add a3, a3, t0 -80000a00: 93 82 00 00 mv t0, ra -80000a04: e7 80 06 fa jalr -96(a3) -80000a08: 93 80 02 00 mv ra, t0 -80000a0c: 93 87 07 ff addi a5, a5, -16 -80000a10: 33 07 f7 40 sub a4, a4, a5 -80000a14: 33 06 f6 00 add a2, a2, a5 -80000a18: e3 78 c3 f6 bgeu t1, a2, -144 -80000a1c: 6f f0 df f3 j -196 +80000738 vx_perf_dump: +80000738: f3 27 50 cc csrr a5, 3269 +8000073c: 37 07 ff 00 lui a4, 4080 +80000740: b3 87 e7 00 add a5, a5, a4 +80000744: 93 97 87 00 slli a5, a5, 8 +80000748: 73 27 00 b0 csrr a4, mcycle +8000074c: 23 a0 e7 00 sw a4, 0(a5) +80000750: 73 27 10 b0 csrr a4, 2817 +80000754: 23 a2 e7 00 sw a4, 4(a5) +80000758: 73 27 20 b0 csrr a4, minstret +8000075c: 23 a4 e7 00 sw a4, 8(a5) +80000760: 73 27 30 b0 csrr a4, mhpmcounter3 +80000764: 23 a6 e7 00 sw a4, 12(a5) +80000768: 73 27 40 b0 csrr a4, mhpmcounter4 +8000076c: 23 a8 e7 00 sw a4, 16(a5) +80000770: 73 27 50 b0 csrr a4, mhpmcounter5 +80000774: 23 aa e7 00 sw a4, 20(a5) +80000778: 73 27 60 b0 csrr a4, mhpmcounter6 +8000077c: 23 ac e7 00 sw a4, 24(a5) +80000780: 73 27 70 b0 csrr a4, mhpmcounter7 +80000784: 23 ae e7 00 sw a4, 28(a5) +80000788: 73 27 80 b0 csrr a4, mhpmcounter8 +8000078c: 23 a0 e7 02 sw a4, 32(a5) +80000790: 73 27 90 b0 csrr a4, mhpmcounter9 +80000794: 23 a2 e7 02 sw a4, 36(a5) +80000798: 73 27 a0 b0 csrr a4, mhpmcounter10 +8000079c: 23 a4 e7 02 sw a4, 40(a5) +800007a0: 73 27 b0 b0 csrr a4, mhpmcounter11 +800007a4: 23 a6 e7 02 sw a4, 44(a5) +800007a8: 73 27 c0 b0 csrr a4, mhpmcounter12 +800007ac: 23 a8 e7 02 sw a4, 48(a5) +800007b0: 73 27 d0 b0 csrr a4, mhpmcounter13 +800007b4: 23 aa e7 02 sw a4, 52(a5) +800007b8: 73 27 e0 b0 csrr a4, mhpmcounter14 +800007bc: 23 ac e7 02 sw a4, 56(a5) +800007c0: 73 27 f0 b0 csrr a4, mhpmcounter15 +800007c4: 23 ae e7 02 sw a4, 60(a5) +800007c8: 73 27 00 b1 csrr a4, mhpmcounter16 +800007cc: 23 a0 e7 04 sw a4, 64(a5) +800007d0: 73 27 10 b1 csrr a4, mhpmcounter17 +800007d4: 23 a2 e7 04 sw a4, 68(a5) +800007d8: 73 27 20 b1 csrr a4, mhpmcounter18 +800007dc: 23 a4 e7 04 sw a4, 72(a5) +800007e0: 73 27 30 b1 csrr a4, mhpmcounter19 +800007e4: 23 a6 e7 04 sw a4, 76(a5) +800007e8: 73 27 40 b1 csrr a4, mhpmcounter20 +800007ec: 23 a8 e7 04 sw a4, 80(a5) +800007f0: 73 27 50 b1 csrr a4, mhpmcounter21 +800007f4: 23 aa e7 04 sw a4, 84(a5) +800007f8: 73 27 60 b1 csrr a4, mhpmcounter22 +800007fc: 23 ac e7 04 sw a4, 88(a5) +80000800: 73 27 70 b1 csrr a4, mhpmcounter23 +80000804: 23 ae e7 04 sw a4, 92(a5) +80000808: 73 27 80 b1 csrr a4, mhpmcounter24 +8000080c: 23 a0 e7 06 sw a4, 96(a5) +80000810: 73 27 90 b1 csrr a4, mhpmcounter25 +80000814: 23 a2 e7 06 sw a4, 100(a5) +80000818: 73 27 a0 b1 csrr a4, mhpmcounter26 +8000081c: 23 a4 e7 06 sw a4, 104(a5) +80000820: 73 27 b0 b1 csrr a4, mhpmcounter27 +80000824: 23 a6 e7 06 sw a4, 108(a5) +80000828: 73 27 c0 b1 csrr a4, mhpmcounter28 +8000082c: 23 a8 e7 06 sw a4, 112(a5) +80000830: 73 27 d0 b1 csrr a4, mhpmcounter29 +80000834: 23 aa e7 06 sw a4, 116(a5) +80000838: 73 27 e0 b1 csrr a4, mhpmcounter30 +8000083c: 23 ac e7 06 sw a4, 120(a5) +80000840: 73 27 f0 b1 csrr a4, mhpmcounter31 +80000844: 23 ae e7 06 sw a4, 124(a5) +80000848: 73 27 00 b8 csrr a4, mcycleh +8000084c: 23 a0 e7 08 sw a4, 128(a5) +80000850: 73 27 10 b8 csrr a4, 2945 +80000854: 23 a2 e7 08 sw a4, 132(a5) +80000858: 73 27 20 b8 csrr a4, minstreth +8000085c: 23 a4 e7 08 sw a4, 136(a5) +80000860: 73 27 30 b8 csrr a4, mhpmcounter3h +80000864: 23 a6 e7 08 sw a4, 140(a5) +80000868: 73 27 40 b8 csrr a4, mhpmcounter4h +8000086c: 23 a8 e7 08 sw a4, 144(a5) +80000870: 73 27 50 b8 csrr a4, mhpmcounter5h +80000874: 23 aa e7 08 sw a4, 148(a5) +80000878: 73 27 60 b8 csrr a4, mhpmcounter6h +8000087c: 23 ac e7 08 sw a4, 152(a5) +80000880: 73 27 70 b8 csrr a4, mhpmcounter7h +80000884: 23 ae e7 08 sw a4, 156(a5) +80000888: 73 27 80 b8 csrr a4, mhpmcounter8h +8000088c: 23 a0 e7 0a sw a4, 160(a5) +80000890: 73 27 90 b8 csrr a4, mhpmcounter9h +80000894: 23 a2 e7 0a sw a4, 164(a5) +80000898: 73 27 a0 b8 csrr a4, mhpmcounter10h +8000089c: 23 a4 e7 0a sw a4, 168(a5) +800008a0: 73 27 b0 b8 csrr a4, mhpmcounter11h +800008a4: 23 a6 e7 0a sw a4, 172(a5) +800008a8: 73 27 c0 b8 csrr a4, mhpmcounter12h +800008ac: 23 a8 e7 0a sw a4, 176(a5) +800008b0: 73 27 d0 b8 csrr a4, mhpmcounter13h +800008b4: 23 aa e7 0a sw a4, 180(a5) +800008b8: 73 27 e0 b8 csrr a4, mhpmcounter14h +800008bc: 23 ac e7 0a sw a4, 184(a5) +800008c0: 73 27 f0 b8 csrr a4, mhpmcounter15h +800008c4: 23 ae e7 0a sw a4, 188(a5) +800008c8: 73 27 00 b9 csrr a4, mhpmcounter16h +800008cc: 23 a0 e7 0c sw a4, 192(a5) +800008d0: 73 27 10 b9 csrr a4, mhpmcounter17h +800008d4: 23 a2 e7 0c sw a4, 196(a5) +800008d8: 73 27 20 b9 csrr a4, mhpmcounter18h +800008dc: 23 a4 e7 0c sw a4, 200(a5) +800008e0: 73 27 30 b9 csrr a4, mhpmcounter19h +800008e4: 23 a6 e7 0c sw a4, 204(a5) +800008e8: 73 27 40 b9 csrr a4, mhpmcounter20h +800008ec: 23 a8 e7 0c sw a4, 208(a5) +800008f0: 73 27 50 b9 csrr a4, mhpmcounter21h +800008f4: 23 aa e7 0c sw a4, 212(a5) +800008f8: 73 27 60 b9 csrr a4, mhpmcounter22h +800008fc: 23 ac e7 0c sw a4, 216(a5) +80000900: 73 27 70 b9 csrr a4, mhpmcounter23h +80000904: 23 ae e7 0c sw a4, 220(a5) +80000908: 73 27 80 b9 csrr a4, mhpmcounter24h +8000090c: 23 a0 e7 0e sw a4, 224(a5) +80000910: 73 27 90 b9 csrr a4, mhpmcounter25h +80000914: 23 a2 e7 0e sw a4, 228(a5) +80000918: 73 27 a0 b9 csrr a4, mhpmcounter26h +8000091c: 23 a4 e7 0e sw a4, 232(a5) +80000920: 73 27 b0 b9 csrr a4, mhpmcounter27h +80000924: 23 a6 e7 0e sw a4, 236(a5) +80000928: 73 27 c0 b9 csrr a4, mhpmcounter28h +8000092c: 23 a8 e7 0e sw a4, 240(a5) +80000930: 73 27 d0 b9 csrr a4, mhpmcounter29h +80000934: 23 aa e7 0e sw a4, 244(a5) +80000938: 73 27 e0 b9 csrr a4, mhpmcounter30h +8000093c: 23 ac e7 0e sw a4, 248(a5) +80000940: 73 27 f0 b9 csrr a4, mhpmcounter31h +80000944: 23 ae e7 0e sw a4, 252(a5) +80000948: 67 80 00 00 ret -80000a20 __register_exitproc: -80000a20: b7 17 00 80 lui a5, 524289 -80000a24: 03 a7 07 43 lw a4, 1072(a5) -80000a28: 83 27 87 14 lw a5, 328(a4) -80000a2c: 63 8c 07 04 beqz a5, 88 -80000a30: 03 a7 47 00 lw a4, 4(a5) -80000a34: 13 08 f0 01 addi a6, zero, 31 -80000a38: 63 4e e8 06 blt a6, a4, 124 -80000a3c: 13 18 27 00 slli a6, a4, 2 -80000a40: 63 06 05 02 beqz a0, 44 -80000a44: 33 83 07 01 add t1, a5, a6 -80000a48: 23 24 c3 08 sw a2, 136(t1) -80000a4c: 83 a8 87 18 lw a7, 392(a5) -80000a50: 13 06 10 00 addi a2, zero, 1 -80000a54: 33 16 e6 00 sll a2, a2, a4 -80000a58: b3 e8 c8 00 or a7, a7, a2 -80000a5c: 23 a4 17 19 sw a7, 392(a5) -80000a60: 23 24 d3 10 sw a3, 264(t1) -80000a64: 93 06 20 00 addi a3, zero, 2 -80000a68: 63 04 d5 02 beq a0, a3, 40 -80000a6c: 13 07 17 00 addi a4, a4, 1 -80000a70: 23 a2 e7 00 sw a4, 4(a5) -80000a74: b3 87 07 01 add a5, a5, a6 -80000a78: 23 a4 b7 00 sw a1, 8(a5) -80000a7c: 13 05 00 00 mv a0, zero -80000a80: 67 80 00 00 ret -80000a84: 93 07 c7 14 addi a5, a4, 332 -80000a88: 23 24 f7 14 sw a5, 328(a4) -80000a8c: 6f f0 5f fa j -92 -80000a90: 83 a6 c7 18 lw a3, 396(a5) -80000a94: 13 07 17 00 addi a4, a4, 1 -80000a98: 23 a2 e7 00 sw a4, 4(a5) -80000a9c: 33 e6 c6 00 or a2, a3, a2 -80000aa0: 23 a6 c7 18 sw a2, 396(a5) -80000aa4: b3 87 07 01 add a5, a5, a6 -80000aa8: 23 a4 b7 00 sw a1, 8(a5) -80000aac: 13 05 00 00 mv a0, zero -80000ab0: 67 80 00 00 ret -80000ab4: 13 05 f0 ff addi a0, zero, -1 -80000ab8: 67 80 00 00 ret +8000094c atexit: +8000094c: 93 05 05 00 mv a1, a0 +80000950: 93 06 00 00 mv a3, zero +80000954: 13 06 00 00 mv a2, zero +80000958: 13 05 00 00 mv a0, zero +8000095c: 6f 00 40 11 j 276 -80000abc __call_exitprocs: -80000abc: 13 01 01 fd addi sp, sp, -48 -80000ac0: b7 17 00 80 lui a5, 524289 -80000ac4: 23 2c 41 01 sw s4, 24(sp) -80000ac8: 03 aa 07 43 lw s4, 1072(a5) -80000acc: 23 20 21 03 sw s2, 32(sp) -80000ad0: 23 26 11 02 sw ra, 44(sp) -80000ad4: 03 29 8a 14 lw s2, 328(s4) -80000ad8: 23 24 81 02 sw s0, 40(sp) -80000adc: 23 22 91 02 sw s1, 36(sp) -80000ae0: 23 2e 31 01 sw s3, 28(sp) -80000ae4: 23 2a 51 01 sw s5, 20(sp) -80000ae8: 23 28 61 01 sw s6, 16(sp) -80000aec: 23 26 71 01 sw s7, 12(sp) -80000af0: 23 24 81 01 sw s8, 8(sp) -80000af4: 63 00 09 04 beqz s2, 64 -80000af8: 13 0b 05 00 mv s6, a0 -80000afc: 93 8b 05 00 mv s7, a1 -80000b00: 93 0a 10 00 addi s5, zero, 1 -80000b04: 93 09 f0 ff addi s3, zero, -1 -80000b08: 83 24 49 00 lw s1, 4(s2) -80000b0c: 13 84 f4 ff addi s0, s1, -1 -80000b10: 63 42 04 02 bltz s0, 36 -80000b14: 93 94 24 00 slli s1, s1, 2 -80000b18: b3 04 99 00 add s1, s2, s1 -80000b1c: 63 84 0b 04 beqz s7, 72 -80000b20: 83 a7 44 10 lw a5, 260(s1) -80000b24: 63 80 77 05 beq a5, s7, 64 -80000b28: 13 04 f4 ff addi s0, s0, -1 -80000b2c: 93 84 c4 ff addi s1, s1, -4 -80000b30: e3 16 34 ff bne s0, s3, -20 -80000b34: 83 20 c1 02 lw ra, 44(sp) -80000b38: 03 24 81 02 lw s0, 40(sp) -80000b3c: 83 24 41 02 lw s1, 36(sp) -80000b40: 03 29 01 02 lw s2, 32(sp) -80000b44: 83 29 c1 01 lw s3, 28(sp) -80000b48: 03 2a 81 01 lw s4, 24(sp) -80000b4c: 83 2a 41 01 lw s5, 20(sp) -80000b50: 03 2b 01 01 lw s6, 16(sp) -80000b54: 83 2b c1 00 lw s7, 12(sp) -80000b58: 03 2c 81 00 lw s8, 8(sp) -80000b5c: 13 01 01 03 addi sp, sp, 48 -80000b60: 67 80 00 00 ret -80000b64: 83 27 49 00 lw a5, 4(s2) -80000b68: 83 a6 44 00 lw a3, 4(s1) -80000b6c: 93 87 f7 ff addi a5, a5, -1 -80000b70: 63 8e 87 04 beq a5, s0, 92 -80000b74: 23 a2 04 00 sw zero, 4(s1) -80000b78: e3 88 06 fa beqz a3, -80 -80000b7c: 83 27 89 18 lw a5, 392(s2) -80000b80: 33 97 8a 00 sll a4, s5, s0 -80000b84: 03 2c 49 00 lw s8, 4(s2) -80000b88: b3 77 f7 00 and a5, a4, a5 -80000b8c: 63 92 07 02 bnez a5, 36 -80000b90: e7 80 06 00 jalr a3 -80000b94: 03 27 49 00 lw a4, 4(s2) -80000b98: 83 27 8a 14 lw a5, 328(s4) -80000b9c: 63 14 87 01 bne a4, s8, 8 -80000ba0: e3 04 f9 f8 beq s2, a5, -120 -80000ba4: e3 88 07 f8 beqz a5, -112 -80000ba8: 13 89 07 00 mv s2, a5 -80000bac: 6f f0 df f5 j -164 -80000bb0: 83 27 c9 18 lw a5, 396(s2) -80000bb4: 83 a5 44 08 lw a1, 132(s1) -80000bb8: 33 77 f7 00 and a4, a4, a5 -80000bbc: 63 1c 07 00 bnez a4, 24 -80000bc0: 13 05 0b 00 mv a0, s6 -80000bc4: e7 80 06 00 jalr a3 -80000bc8: 6f f0 df fc j -52 -80000bcc: 23 22 89 00 sw s0, 4(s2) -80000bd0: 6f f0 9f fa j -88 -80000bd4: 13 85 05 00 mv a0, a1 -80000bd8: e7 80 06 00 jalr a3 -80000bdc: 6f f0 9f fb j -72 +80000960 exit: +80000960: 13 01 01 ff addi sp, sp, -16 +80000964: 93 05 00 00 mv a1, zero +80000968: 23 24 81 00 sw s0, 8(sp) +8000096c: 23 26 11 00 sw ra, 12(sp) +80000970: 13 04 05 00 mv s0, a0 +80000974: ef 00 80 19 jal 408 +80000978: b7 17 00 80 lui a5, 524289 +8000097c: 03 a5 07 43 lw a0, 1072(a5) +80000980: 83 27 c5 03 lw a5, 60(a0) +80000984: 63 84 07 00 beqz a5, 8 +80000988: e7 80 07 00 jalr a5 +8000098c: 13 05 04 00 mv a0, s0 +80000990: ef f0 5f 8a jal -1884 + +80000994 memset: +80000994: 13 03 f0 00 addi t1, zero, 15 +80000998: 13 07 05 00 mv a4, a0 +8000099c: 63 7e c3 02 bgeu t1, a2, 60 +800009a0: 93 77 f7 00 andi a5, a4, 15 +800009a4: 63 90 07 0a bnez a5, 160 +800009a8: 63 92 05 08 bnez a1, 132 +800009ac: 93 76 06 ff andi a3, a2, -16 +800009b0: 13 76 f6 00 andi a2, a2, 15 +800009b4: b3 86 e6 00 add a3, a3, a4 +800009b8: 23 20 b7 00 sw a1, 0(a4) +800009bc: 23 22 b7 00 sw a1, 4(a4) +800009c0: 23 24 b7 00 sw a1, 8(a4) +800009c4: 23 26 b7 00 sw a1, 12(a4) +800009c8: 13 07 07 01 addi a4, a4, 16 +800009cc: e3 66 d7 fe bltu a4, a3, -20 +800009d0: 63 14 06 00 bnez a2, 8 +800009d4: 67 80 00 00 ret +800009d8: b3 06 c3 40 sub a3, t1, a2 +800009dc: 93 96 26 00 slli a3, a3, 2 +800009e0: 97 02 00 00 auipc t0, 0 +800009e4: b3 86 56 00 add a3, a3, t0 +800009e8: 67 80 c6 00 jr 12(a3) +800009ec: 23 07 b7 00 sb a1, 14(a4) +800009f0: a3 06 b7 00 sb a1, 13(a4) +800009f4: 23 06 b7 00 sb a1, 12(a4) +800009f8: a3 05 b7 00 sb a1, 11(a4) +800009fc: 23 05 b7 00 sb a1, 10(a4) +80000a00: a3 04 b7 00 sb a1, 9(a4) +80000a04: 23 04 b7 00 sb a1, 8(a4) +80000a08: a3 03 b7 00 sb a1, 7(a4) +80000a0c: 23 03 b7 00 sb a1, 6(a4) +80000a10: a3 02 b7 00 sb a1, 5(a4) +80000a14: 23 02 b7 00 sb a1, 4(a4) +80000a18: a3 01 b7 00 sb a1, 3(a4) +80000a1c: 23 01 b7 00 sb a1, 2(a4) +80000a20: a3 00 b7 00 sb a1, 1(a4) +80000a24: 23 00 b7 00 sb a1, 0(a4) +80000a28: 67 80 00 00 ret +80000a2c: 93 f5 f5 0f andi a1, a1, 255 +80000a30: 93 96 85 00 slli a3, a1, 8 +80000a34: b3 e5 d5 00 or a1, a1, a3 +80000a38: 93 96 05 01 slli a3, a1, 16 +80000a3c: b3 e5 d5 00 or a1, a1, a3 +80000a40: 6f f0 df f6 j -148 +80000a44: 93 96 27 00 slli a3, a5, 2 +80000a48: 97 02 00 00 auipc t0, 0 +80000a4c: b3 86 56 00 add a3, a3, t0 +80000a50: 93 82 00 00 mv t0, ra +80000a54: e7 80 06 fa jalr -96(a3) +80000a58: 93 80 02 00 mv ra, t0 +80000a5c: 93 87 07 ff addi a5, a5, -16 +80000a60: 33 07 f7 40 sub a4, a4, a5 +80000a64: 33 06 f6 00 add a2, a2, a5 +80000a68: e3 78 c3 f6 bgeu t1, a2, -144 +80000a6c: 6f f0 df f3 j -196 + +80000a70 __register_exitproc: +80000a70: b7 17 00 80 lui a5, 524289 +80000a74: 03 a7 07 43 lw a4, 1072(a5) +80000a78: 83 27 87 14 lw a5, 328(a4) +80000a7c: 63 8c 07 04 beqz a5, 88 +80000a80: 03 a7 47 00 lw a4, 4(a5) +80000a84: 13 08 f0 01 addi a6, zero, 31 +80000a88: 63 4e e8 06 blt a6, a4, 124 +80000a8c: 13 18 27 00 slli a6, a4, 2 +80000a90: 63 06 05 02 beqz a0, 44 +80000a94: 33 83 07 01 add t1, a5, a6 +80000a98: 23 24 c3 08 sw a2, 136(t1) +80000a9c: 83 a8 87 18 lw a7, 392(a5) +80000aa0: 13 06 10 00 addi a2, zero, 1 +80000aa4: 33 16 e6 00 sll a2, a2, a4 +80000aa8: b3 e8 c8 00 or a7, a7, a2 +80000aac: 23 a4 17 19 sw a7, 392(a5) +80000ab0: 23 24 d3 10 sw a3, 264(t1) +80000ab4: 93 06 20 00 addi a3, zero, 2 +80000ab8: 63 04 d5 02 beq a0, a3, 40 +80000abc: 13 07 17 00 addi a4, a4, 1 +80000ac0: 23 a2 e7 00 sw a4, 4(a5) +80000ac4: b3 87 07 01 add a5, a5, a6 +80000ac8: 23 a4 b7 00 sw a1, 8(a5) +80000acc: 13 05 00 00 mv a0, zero +80000ad0: 67 80 00 00 ret +80000ad4: 93 07 c7 14 addi a5, a4, 332 +80000ad8: 23 24 f7 14 sw a5, 328(a4) +80000adc: 6f f0 5f fa j -92 +80000ae0: 83 a6 c7 18 lw a3, 396(a5) +80000ae4: 13 07 17 00 addi a4, a4, 1 +80000ae8: 23 a2 e7 00 sw a4, 4(a5) +80000aec: 33 e6 c6 00 or a2, a3, a2 +80000af0: 23 a6 c7 18 sw a2, 396(a5) +80000af4: b3 87 07 01 add a5, a5, a6 +80000af8: 23 a4 b7 00 sw a1, 8(a5) +80000afc: 13 05 00 00 mv a0, zero +80000b00: 67 80 00 00 ret +80000b04: 13 05 f0 ff addi a0, zero, -1 +80000b08: 67 80 00 00 ret + +80000b0c __call_exitprocs: +80000b0c: 13 01 01 fd addi sp, sp, -48 +80000b10: b7 17 00 80 lui a5, 524289 +80000b14: 23 2c 41 01 sw s4, 24(sp) +80000b18: 03 aa 07 43 lw s4, 1072(a5) +80000b1c: 23 20 21 03 sw s2, 32(sp) +80000b20: 23 26 11 02 sw ra, 44(sp) +80000b24: 03 29 8a 14 lw s2, 328(s4) +80000b28: 23 24 81 02 sw s0, 40(sp) +80000b2c: 23 22 91 02 sw s1, 36(sp) +80000b30: 23 2e 31 01 sw s3, 28(sp) +80000b34: 23 2a 51 01 sw s5, 20(sp) +80000b38: 23 28 61 01 sw s6, 16(sp) +80000b3c: 23 26 71 01 sw s7, 12(sp) +80000b40: 23 24 81 01 sw s8, 8(sp) +80000b44: 63 00 09 04 beqz s2, 64 +80000b48: 13 0b 05 00 mv s6, a0 +80000b4c: 93 8b 05 00 mv s7, a1 +80000b50: 93 0a 10 00 addi s5, zero, 1 +80000b54: 93 09 f0 ff addi s3, zero, -1 +80000b58: 83 24 49 00 lw s1, 4(s2) +80000b5c: 13 84 f4 ff addi s0, s1, -1 +80000b60: 63 42 04 02 bltz s0, 36 +80000b64: 93 94 24 00 slli s1, s1, 2 +80000b68: b3 04 99 00 add s1, s2, s1 +80000b6c: 63 84 0b 04 beqz s7, 72 +80000b70: 83 a7 44 10 lw a5, 260(s1) +80000b74: 63 80 77 05 beq a5, s7, 64 +80000b78: 13 04 f4 ff addi s0, s0, -1 +80000b7c: 93 84 c4 ff addi s1, s1, -4 +80000b80: e3 16 34 ff bne s0, s3, -20 +80000b84: 83 20 c1 02 lw ra, 44(sp) +80000b88: 03 24 81 02 lw s0, 40(sp) +80000b8c: 83 24 41 02 lw s1, 36(sp) +80000b90: 03 29 01 02 lw s2, 32(sp) +80000b94: 83 29 c1 01 lw s3, 28(sp) +80000b98: 03 2a 81 01 lw s4, 24(sp) +80000b9c: 83 2a 41 01 lw s5, 20(sp) +80000ba0: 03 2b 01 01 lw s6, 16(sp) +80000ba4: 83 2b c1 00 lw s7, 12(sp) +80000ba8: 03 2c 81 00 lw s8, 8(sp) +80000bac: 13 01 01 03 addi sp, sp, 48 +80000bb0: 67 80 00 00 ret +80000bb4: 83 27 49 00 lw a5, 4(s2) +80000bb8: 83 a6 44 00 lw a3, 4(s1) +80000bbc: 93 87 f7 ff addi a5, a5, -1 +80000bc0: 63 8e 87 04 beq a5, s0, 92 +80000bc4: 23 a2 04 00 sw zero, 4(s1) +80000bc8: e3 88 06 fa beqz a3, -80 +80000bcc: 83 27 89 18 lw a5, 392(s2) +80000bd0: 33 97 8a 00 sll a4, s5, s0 +80000bd4: 03 2c 49 00 lw s8, 4(s2) +80000bd8: b3 77 f7 00 and a5, a4, a5 +80000bdc: 63 92 07 02 bnez a5, 36 +80000be0: e7 80 06 00 jalr a3 +80000be4: 03 27 49 00 lw a4, 4(s2) +80000be8: 83 27 8a 14 lw a5, 328(s4) +80000bec: 63 14 87 01 bne a4, s8, 8 +80000bf0: e3 04 f9 f8 beq s2, a5, -120 +80000bf4: e3 88 07 f8 beqz a5, -112 +80000bf8: 13 89 07 00 mv s2, a5 +80000bfc: 6f f0 df f5 j -164 +80000c00: 83 27 c9 18 lw a5, 396(s2) +80000c04: 83 a5 44 08 lw a1, 132(s1) +80000c08: 33 77 f7 00 and a4, a4, a5 +80000c0c: 63 1c 07 00 bnez a4, 24 +80000c10: 13 05 0b 00 mv a0, s6 +80000c14: e7 80 06 00 jalr a3 +80000c18: 6f f0 df fc j -52 +80000c1c: 23 22 89 00 sw s0, 4(s2) +80000c20: 6f f0 9f fa j -88 +80000c24: 13 85 05 00 mv a0, a1 +80000c28: e7 80 06 00 jalr a3 +80000c2c: 6f f0 9f fb j -72 Disassembly of section .init_array: @@ -874,25 +900,25 @@ Disassembly of section .comment: 36: 6a 65 38: 63 74 2e 67 bgeu t3, s2, 1640 3c: 69 74 - 3e: 20 65 - 40: 66 33 - 42: 32 63 - 44: 36 31 - 46: 31 61 - 48: 61 32 - 4a: 31 34 - 4c: 64 65 - 4e: 61 38 - 50: 35 35 - 52: 33 36 34 65 - 56: 66 64 - 58: 37 62 61 34 lui tp, 214550 - 5c: 35 31 - 5e: 65 63 - 60: 35 65 - 62: 63 33 66 37 - 66: 34 29 - 68: 00 47 + 3e: 20 32 + 40: 61 32 + 42: 33 65 66 61 + 46: 63 33 35 32 + 4a: 66 39 + 4c: 31 39 + 4e: 65 62 + 50: 64 31 + 52: 65 63 + 54: 31 62 + 56: 65 34 + 58: 35 31 + 5a: 34 36 + 5c: 64 36 + 5e: 61 39 + 60: 66 61 + 62: 32 31 + 64: 62 35 + 66: 33 29 00 47 6a: 43 43 3a 20 fmadd.s ft6, fs4, ft3, ft4, rmm 6e: 28 47 70: 4e 55 @@ -976,347 +1002,356 @@ Disassembly of section .symtab: 9e: f1 ff a0: 0e 00 a2: 00 00 - a4: 78 02 + a4: 40 02 a6: 00 80 a8: 00 00 aa: 00 00 ac: 00 00 ae: 02 00 - b0: 15 00 - ... + b0: 1e 00 + b2: 00 00 + b4: 7c 02 + b6: 00 80 + b8: 00 00 ba: 00 00 - bc: 04 00 - be: f1 ff + bc: 00 00 + be: 02 00 c0: 25 00 - c2: 00 00 - c4: 50 00 - c6: 00 80 - c8: 18 00 - ca: 00 00 - cc: 02 00 - ce: 02 00 - d0: 33 00 00 00 add zero, zero, zero ... - dc: 04 00 - de: f1 ff - e0: 57 00 00 00 + ca: 00 00 + cc: 04 00 + ce: f1 ff + d0: 35 00 + d2: 00 00 + d4: 50 00 + d6: 00 80 + d8: 18 00 + da: 00 00 + dc: 02 00 + de: 02 00 + e0: 43 00 00 00 fmadd.s ft0, ft0, ft0, ft0, rne ... ec: 04 00 ee: f1 ff - f0: 63 00 00 00 beqz zero, 0 + f0: 67 00 00 00 jr zero ... fc: 04 00 fe: f1 ff - 100: 6e 00 - 102: 00 00 - 104: 7c 02 - 106: 00 80 - 108: 48 01 - 10a: 00 00 - 10c: 02 00 - 10e: 02 00 - 110: 84 00 + 100: 73 00 00 00 ecall + ... + 10c: 04 00 + 10e: f1 ff + 110: 81 00 ... 11a: 00 00 11c: 04 00 11e: f1 ff - 120: 9e 00 - ... + 120: 8c 00 + 122: 00 00 + 124: 78 03 + 126: 00 80 + 128: 3c 01 12a: 00 00 - 12c: 04 00 - 12e: f1 ff - 130: a0 00 - ... + 12c: 02 00 + 12e: 02 00 + 130: a2 00 + 132: 00 00 + 134: b4 04 + 136: 00 80 + 138: a4 00 13a: 00 00 - 13c: 04 00 - 13e: f1 ff - 140: 8e 00 - ... + 13c: 02 00 + 13e: 02 00 + 140: b8 00 + 142: 00 00 + 144: 58 05 + 146: 00 80 + 148: 2c 00 14a: 00 00 - 14c: 04 00 - 14e: f1 ff - 150: 95 00 + 14c: 02 00 + 14e: 02 00 + 150: cc 00 ... 15a: 00 00 15c: 04 00 15e: f1 ff - 160: 9c 00 + 160: d8 00 ... 16a: 00 00 16c: 04 00 16e: f1 ff - 170: a7 00 00 00 + 170: da 00 ... + 17a: 00 00 17c: 04 00 17e: f1 ff - 180: b0 00 - 182: 00 00 - 184: 08 10 - 186: 00 80 - 188: 28 04 - 18a: 00 00 - 18c: 01 00 - 18e: 04 00 + 180: d6 00 ... + 18a: 00 00 + 18c: 04 00 + 18e: f1 ff + 190: e1 00 + ... + 19a: 00 00 19c: 04 00 19e: f1 ff - 1a0: bc 00 + 1a0: ea 00 1a2: 00 00 - 1a4: 04 10 + 1a4: 08 10 1a6: 00 80 - 1a8: 00 00 + 1a8: 28 04 1aa: 00 00 - 1ac: 00 00 - 1ae: 03 00 cd 00 lb zero, 12(s10) - 1b2: 00 00 - 1b4: 04 10 - 1b6: 00 80 - 1b8: 00 00 - 1ba: 00 00 - 1bc: 00 00 - 1be: 03 00 e0 00 lb zero, 14(zero) + 1ac: 01 00 + 1ae: 04 00 + ... + 1bc: 04 00 + 1be: f1 ff + 1c0: f6 00 1c2: 00 00 1c4: 04 10 1c6: 00 80 1c8: 00 00 1ca: 00 00 1cc: 00 00 - 1ce: 03 00 f1 00 lb zero, 15(sp) + 1ce: 03 00 07 01 lb zero, 16(a4) 1d2: 00 00 - 1d4: 00 10 + 1d4: 04 10 1d6: 00 80 1d8: 00 00 1da: 00 00 1dc: 00 00 - 1de: 03 00 05 01 lb zero, 16(a0) + 1de: 03 00 1a 01 lb zero, 17(s4) 1e2: 00 00 - 1e4: 00 10 + 1e4: 04 10 1e6: 00 80 1e8: 00 00 1ea: 00 00 1ec: 00 00 - 1ee: 03 00 18 01 lb zero, 17(a6) + 1ee: 03 00 2b 01 lb zero, 18(s6) 1f2: 00 00 1f4: 00 10 1f6: 00 80 1f8: 00 00 1fa: 00 00 1fc: 00 00 - 1fe: 03 00 2e 01 lb zero, 18(t3) - ... + 1fe: 03 00 3f 01 lb zero, 19(t5) + 202: 00 00 + 204: 00 10 + 206: 00 80 + 208: 00 00 20a: 00 00 - 20c: 10 00 - 20e: f1 ff - 210: 3c 01 + 20c: 00 00 + 20e: 03 00 52 01 lb zero, 21(tp) 212: 00 00 - 214: 00 04 - 216: 00 00 + 214: 00 10 + 216: 00 80 218: 00 00 21a: 00 00 - 21c: 10 00 - 21e: f1 ff - 220: 49 01 - 222: 00 00 - 224: 34 14 - 226: 00 80 - 228: 80 00 + 21c: 00 00 + 21e: 03 00 68 01 lb zero, 22(a6) + ... 22a: 00 00 - 22c: 11 00 - 22e: 06 00 - 230: 57 01 00 00 - 234: 30 14 - 236: 00 80 + 22c: 10 00 + 22e: f1 ff + 230: 76 01 + 232: 00 00 + 234: 00 04 + 236: 00 00 238: 00 00 23a: 00 00 23c: 10 00 - 23e: 05 00 - 240: 67 01 00 00 jalr sp, zero - 244: 08 18 + 23e: f1 ff + 240: 83 01 00 00 lb gp, 0(zero) + 244: 34 14 246: 00 80 - 248: 00 00 + 248: 80 00 24a: 00 00 - 24c: 10 00 - 24e: f1 ff - 250: 78 01 + 24c: 11 00 + 24e: 06 00 + 250: 91 01 252: 00 00 254: 30 14 256: 00 80 - 258: 04 00 + 258: 00 00 25a: 00 00 - 25c: 11 00 + 25c: 10 00 25e: 05 00 - 260: 8b 01 00 00 - 264: a8 08 + 260: a1 01 + 262: 00 00 + 264: 08 18 266: 00 80 - 268: 9c 00 + 268: 00 00 26a: 00 00 - 26c: 12 00 - 26e: 02 00 - 270: 9d 01 + 26c: 10 00 + 26e: f1 ff + 270: b2 01 272: 00 00 - 274: 4c 08 + 274: 30 14 276: 00 80 - 278: 5c 00 + 278: 04 00 27a: 00 00 - 27c: 12 00 - 27e: 02 00 - 280: af 01 00 00 - 284: 98 00 + 27c: 11 00 + 27e: 05 00 + 280: c5 01 + 282: 00 00 + 284: 80 02 286: 00 80 - 288: 94 00 + 288: 9c 00 28a: 00 00 28c: 12 00 28e: 02 00 - 290: c2 01 - 292: 00 00 - 294: 00 00 - 296: 00 ff - 298: 00 00 + 290: d7 01 00 00 + 294: 1c 03 + 296: 00 80 + 298: 5c 00 29a: 00 00 - 29c: 10 00 - 29e: f1 ff - 2a0: ce 01 + 29c: 12 00 + 29e: 02 00 + 2a0: e9 01 2a2: 00 00 - 2a4: 40 02 + 2a4: 98 00 2a6: 00 80 - 2a8: 00 00 + 2a8: 94 00 2aa: 00 00 2ac: 12 00 2ae: 02 00 - 2b0: d8 01 + 2b0: fc 01 2b2: 00 00 - 2b4: bc 0a + 2b4: 4c 02 2b6: 00 80 - 2b8: 24 01 + 2b8: 00 00 2ba: 00 00 2bc: 12 00 2be: 02 00 - 2c0: 0e 02 + 2c0: 06 02 2c2: 00 00 - 2c4: 00 00 + 2c4: 0c 0b 2c6: 00 80 - 2c8: 50 00 + 2c8: 24 01 2ca: 00 00 2cc: 12 00 - 2ce: 01 00 - 2d0: e9 01 + 2ce: 02 00 + 2d0: 3c 02 2d2: 00 00 - 2d4: 20 0a + 2d4: 00 00 2d6: 00 80 - 2d8: 9c 00 + 2d8: 50 00 2da: 00 00 2dc: 12 00 - 2de: 02 00 - 2e0: fd 01 - 2e2: 00 00 - 2e4: b4 14 + 2de: 01 00 + 2e0: 17 02 00 00 auipc tp, 0 + 2e4: 70 0a 2e6: 00 80 - 2e8: 00 00 + 2e8: 9c 00 2ea: 00 00 - 2ec: 10 00 - 2ee: 06 00 - 2f0: 09 02 - 2f2: 00 00 - 2f4: 34 14 + 2ec: 12 00 + 2ee: 02 00 + 2f0: 2b 02 00 00 + 2f4: b4 14 2f6: 00 80 2f8: 00 00 2fa: 00 00 2fc: 10 00 2fe: 06 00 - 300: 15 02 - 302: 00 00 - 304: 44 09 + 300: 37 02 00 00 lui tp, 0 + 304: 34 14 306: 00 80 - 308: dc 00 + 308: 00 00 30a: 00 00 - 30c: 12 00 - 30e: 02 00 - 310: 1c 02 - 312: 00 00 - 314: 68 00 + 30c: 10 00 + 30e: 06 00 + 310: 43 02 00 00 fmadd.s ft4, ft0, ft0, ft0, rne + 314: 94 09 316: 00 80 - 318: 30 00 + 318: dc 00 31a: 00 00 31c: 12 00 31e: 02 00 - 320: 21 02 + 320: 4a 02 322: 00 00 - 324: b4 01 + 324: 68 00 326: 00 80 - 328: 80 00 + 328: 30 00 32a: 00 00 32c: 12 00 32e: 02 00 - 330: 43 02 00 00 fmadd.s ft4, ft0, ft0, ft0, rne - 334: 04 08 + 330: 4f 02 00 00 fnmadd.s ft4, ft0, ft0, ft0, rne + 334: b4 01 336: 00 80 - 338: 14 00 + 338: 80 00 33a: 00 00 33c: 12 00 33e: 02 00 - 340: 4a 02 + 340: 71 02 342: 00 00 - 344: 08 10 + 344: 4c 09 346: 00 80 - 348: 00 00 + 348: 14 00 34a: 00 00 - 34c: 10 00 - 34e: 04 00 - 350: 59 02 + 34c: 12 00 + 34e: 02 00 + 350: 78 02 352: 00 00 - 354: 34 14 + 354: 08 10 356: 00 80 358: 00 00 35a: 00 00 35c: 10 00 - 35e: 05 00 - 360: c8 00 - 362: 00 00 - 364: b4 14 + 35e: 04 00 + 360: 87 02 00 00 + 364: 34 14 366: 00 80 368: 00 00 36a: 00 00 36c: 10 00 - 36e: 06 00 - 370: 6e 02 + 36e: 05 00 + 370: 02 01 372: 00 00 - 374: 18 08 + 374: b4 14 376: 00 80 - 378: 34 00 + 378: 00 00 37a: 00 00 - 37c: 12 00 - 37e: 02 00 - 380: 60 02 + 37c: 10 00 + 37e: 06 00 + 380: 9c 02 382: 00 00 - 384: f0 05 + 384: 60 09 386: 00 80 - 388: 14 02 + 388: 34 00 38a: 00 00 38c: 12 00 38e: 02 00 - 390: 6d 02 + 390: 8e 02 392: 00 00 - 394: 34 02 + 394: 38 07 396: 00 80 - 398: 00 00 + 398: 14 02 39a: 00 00 39c: 12 00 39e: 02 00 - 3a0: 73 02 00 00 - 3a4: 2c 01 + 3a0: 9b 02 00 00 + 3a4: 34 02 3a6: 00 80 - 3a8: 88 00 + 3a8: 00 00 3aa: 00 00 3ac: 12 00 3ae: 02 00 - 3b0: 90 02 + 3b0: a1 02 3b2: 00 00 - 3b4: c4 03 + 3b4: 2c 01 3b6: 00 80 - 3b8: 2c 02 + 3b8: 88 00 3ba: 00 00 3bc: 12 00 3be: 02 00 + 3c0: be 02 + 3c2: 00 00 + 3c4: 84 05 + 3c6: 00 80 + 3c8: b4 01 + 3ca: 00 00 + 3cc: 12 00 + 3ce: 02 00 Disassembly of section .strtab: @@ -1326,256 +1361,272 @@ Disassembly of section .strtab: 4: 73 74 61 72 csrrci s0, 1830, 2 8: 74 2e a: 53 2e 6f 00 fadd.s ft8, ft10, ft6, rdn - e: 52 45 - 10: 54 55 - 12: 52 4e - 14: 00 5f - 16: 5f 63 61 6c - 1a: 6c 5f - 1c: 61 74 - 1e: 65 78 - 20: 69 74 - 22: 2e 63 - 24: 00 72 - 26: 65 67 - 28: 69 73 - 2a: 74 65 - 2c: 72 5f - 2e: 66 69 - 30: 6e 69 - 32: 00 70 - 34: 6f 63 6c 5f jal t1, 812534 - 38: 76 6f - 3a: 72 74 - 3c: 65 78 - 3e: 5f 6b 65 72 - 42: 6e 65 - 44: 6c 2d - 46: 34 63 - 48: 2d 65 - 4a: 30 2d - 4c: 39 35 - 4e: 2d 63 - 50: 37 2d 31 35 lui s10, 217874 - 54: 2e 63 - 56: 00 70 - 58: 61 72 - 5a: 61 6c - 5c: 6c 65 - 5e: 6c 5f - 60: 62 63 - 62: 00 76 - 64: 78 5f - 66: 73 70 61 77 csrci 1910, 2 - 6a: 6e 2e - 6c: 63 00 73 70 beq t1, t2, 1792 - 70: 61 77 - 72: 6e 5f - 74: 6b 65 72 6e - 78: 65 6c - 7a: 5f 63 61 6c - 7e: 6c 62 - 80: 61 63 - 82: 6b 00 76 78 - 86: 5f 70 65 72 - 8a: 66 2e - 8c: 63 00 66 69 beq a2, s6, 1664 - 90: 6e 69 - 92: 2e 63 - 94: 00 69 - 96: 6e 69 - 98: 74 2e - 9a: 63 00 5f 5f beq t5, s5, 1504 - 9e: 61 74 - a0: 65 78 - a2: 69 74 - a4: 2e 63 - a6: 00 69 - a8: 6d 70 - aa: 75 72 - ac: 65 2e - ae: 63 00 69 6d beq s2, s6, 1728 - b2: 70 75 - b4: 72 65 - b6: 5f 64 61 74 - ba: 61 00 - bc: 5f 5f 66 69 - c0: 6e 69 - c2: 5f 61 72 72 - c6: 61 79 - c8: 5f 65 6e 64 - cc: 00 5f - ce: 5f 66 69 6e - d2: 69 5f - d4: 61 72 - d6: 72 61 - d8: 79 5f - da: 73 74 61 72 csrrci s0, 1830, 2 - de: 74 00 - e0: 5f 5f 69 6e - e4: 69 74 - e6: 5f 61 72 72 - ea: 61 79 - ec: 5f 65 6e 64 - f0: 00 5f - f2: 5f 70 72 65 - f6: 69 6e - f8: 69 74 - fa: 5f 61 72 72 - fe: 61 79 - 100: 5f 65 6e 64 - 104: 00 5f - 106: 5f 69 6e 69 - 10a: 74 5f - 10c: 61 72 - 10e: 72 61 - 110: 79 5f - 112: 73 74 61 72 csrrci s0, 1830, 2 - 116: 74 00 - 118: 5f 5f 70 72 - 11c: 65 69 - 11e: 6e 69 - 120: 74 5f - 122: 61 72 - 124: 72 61 - 126: 79 5f - 128: 73 74 61 72 csrrci s0, 1830, 2 - 12c: 74 00 - 12e: 5f 5f 73 74 - 132: 61 63 - 134: 6b 5f 75 73 - 138: 61 67 - 13a: 65 00 - 13c: 5f 5f 73 74 - 140: 61 63 - 142: 6b 5f 73 69 - 146: 7a 65 - 148: 00 67 - 14a: 5f 77 73 70 - 14e: 61 77 - 150: 6e 5f - 152: 61 72 - 154: 67 73 00 5f - 158: 5f 53 44 41 - 15c: 54 41 - 15e: 5f 42 45 47 - 162: 49 4e - 164: 5f 5f 00 5f - 168: 5f 67 6c 6f - 16c: 62 61 - 16e: 6c 5f - 170: 70 6f - 172: 69 6e - 174: 74 65 - 176: 72 00 - 178: 5f 67 6c 6f - 17c: 62 61 - 17e: 6c 5f - 180: 69 6d - 182: 70 75 - 184: 72 65 - 186: 5f 70 74 72 - 18a: 00 5f - 18c: 5f 6c 69 62 - 190: 63 5f 69 6e bge s2, t1, 1790 - 194: 69 74 - 196: 5f 61 72 72 - 19a: 61 79 - 19c: 00 5f - 19e: 5f 6c 69 62 - 1a2: 63 5f 66 69 bge a2, s6, 1694 - 1a6: 6e 69 - 1a8: 5f 61 72 72 - 1ac: 61 79 - 1ae: 00 5f - 1b0: 70 6f - 1b2: 63 6c 5f 6b bltu t5, s5, 1720 - 1b6: 65 72 - 1b8: 6e 65 - 1ba: 6c 5f - 1bc: 73 61 78 70 csrrsi sp, 1799, 16 - 1c0: 79 00 - 1c2: 5f 5f 73 74 - 1c6: 61 63 - 1c8: 6b 5f 74 6f - 1cc: 70 00 - 1ce: 76 78 - 1d0: 5f 73 65 74 - 1d4: 5f 73 70 00 - 1d8: 5f 5f 63 61 - 1dc: 6c 6c - 1de: 5f 65 78 69 - 1e2: 74 70 - 1e4: 72 6f - 1e6: 63 73 00 5f bgeu zero, a6, 1510 - 1ea: 5f 72 65 67 - 1ee: 69 73 - 1f0: 74 65 - 1f2: 72 5f - 1f4: 65 78 - 1f6: 69 74 - 1f8: 70 72 - 1fa: 6f 63 00 5f jal t1, 26096 - 1fe: 5f 42 53 53 - 202: 5f 45 4e 44 - 206: 5f 5f 00 5f - 20a: 5f 62 73 73 - 20e: 5f 73 74 61 - 212: 72 74 - 214: 00 6d - 216: 65 6d - 218: 73 65 74 00 csrrsi a0, 7, 8 - 21c: 6d 61 - 21e: 69 6e - 220: 00 5f - 222: 70 6f - 224: 63 6c 5f 6b bltu t5, s5, 1720 - 228: 65 72 - 22a: 6e 65 - 22c: 6c 5f - 22e: 73 61 78 70 csrrsi sp, 1799, 16 - 232: 79 5f - 234: 77 6f 72 6b - 238: 67 72 6f 75 - 23c: 70 5f - 23e: 66 61 - 240: 73 74 00 61 csrrci s0, 1552, 0 - 244: 74 65 - 246: 78 69 - 248: 74 00 - 24a: 5f 5f 44 41 - 24e: 54 41 - 250: 5f 42 45 47 - 254: 49 4e - 256: 5f 5f 00 5f - 25a: 65 64 - 25c: 61 74 - 25e: 61 00 - 260: 76 78 - 262: 5f 70 65 72 - 266: 66 5f - 268: 64 75 - 26a: 6d 70 - 26c: 00 5f - 26e: 65 78 - 270: 69 74 - 272: 00 5f - 274: 70 6f - 276: 63 6c 5f 6b bltu t5, s5, 1720 - 27a: 65 72 - 27c: 6e 65 - 27e: 6c 5f - 280: 73 61 78 70 csrrsi sp, 1799, 16 - 284: 79 5f - 286: 77 6f 72 6b - 28a: 67 72 6f 75 - 28e: 70 00 - 290: 76 78 - 292: 5f 73 70 61 - 296: 77 6e 5f 6b - 29a: 65 72 - 29c: 6e 65 - 29e: 6c 00 + e: 6c 61 + 10: 62 65 + 12: 6c 5f + 14: 65 78 + 16: 69 74 + 18: 5f 6e 65 78 + 1c: 74 00 + 1e: 52 45 + 20: 54 55 + 22: 52 4e + 24: 00 5f + 26: 5f 63 61 6c + 2a: 6c 5f + 2c: 61 74 + 2e: 65 78 + 30: 69 74 + 32: 2e 63 + 34: 00 72 + 36: 65 67 + 38: 69 73 + 3a: 74 65 + 3c: 72 5f + 3e: 66 69 + 40: 6e 69 + 42: 00 70 + 44: 6f 63 6c 5f jal t1, 812534 + 48: 76 6f + 4a: 72 74 + 4c: 65 78 + 4e: 5f 6b 65 72 + 52: 6e 65 + 54: 6c 2d + 56: 65 39 + 58: 2d 33 + 5a: 33 2d 65 64 + 5e: 2d 33 + 60: 38 2d + 62: 36 33 + 64: 2e 63 + 66: 00 70 + 68: 61 72 + 6a: 61 6c + 6c: 6c 65 + 6e: 6c 5f + 70: 62 63 + 72: 00 76 + 74: 78 5f + 76: 73 79 73 63 csrrci s2, 1591, 6 + 7a: 61 6c + 7c: 6c 73 + 7e: 2e 63 + 80: 00 76 + 82: 78 5f + 84: 73 70 61 77 csrci 1910, 2 + 88: 6e 2e + 8a: 63 00 73 70 beq t1, t2, 1792 + 8e: 61 77 + 90: 6e 5f + 92: 6b 65 72 6e + 96: 65 6c + 98: 5f 61 6c 6c + 9c: 5f 73 74 75 + a0: 62 00 + a2: 73 70 61 77 csrci 1910, 2 + a6: 6e 5f + a8: 6b 65 72 6e + ac: 65 6c + ae: 5f 72 65 6d + b2: 5f 73 74 75 + b6: 62 00 + b8: 73 70 61 77 csrci 1910, 2 + bc: 6e 5f + be: 6b 65 72 6e + c2: 65 6c + c4: 5f 61 6c 6c + c8: 5f 63 62 00 + cc: 76 78 + ce: 5f 70 65 72 + d2: 66 2e + d4: 63 00 5f 5f beq t5, s5, 1504 + d8: 61 74 + da: 65 78 + dc: 69 74 + de: 2e 63 + e0: 00 69 + e2: 6d 70 + e4: 75 72 + e6: 65 2e + e8: 63 00 69 6d beq s2, s6, 1728 + ec: 70 75 + ee: 72 65 + f0: 5f 64 61 74 + f4: 61 00 + f6: 5f 5f 66 69 + fa: 6e 69 + fc: 5f 61 72 72 + 100: 61 79 + 102: 5f 65 6e 64 + 106: 00 5f + 108: 5f 66 69 6e + 10c: 69 5f + 10e: 61 72 + 110: 72 61 + 112: 79 5f + 114: 73 74 61 72 csrrci s0, 1830, 2 + 118: 74 00 + 11a: 5f 5f 69 6e + 11e: 69 74 + 120: 5f 61 72 72 + 124: 61 79 + 126: 5f 65 6e 64 + 12a: 00 5f + 12c: 5f 70 72 65 + 130: 69 6e + 132: 69 74 + 134: 5f 61 72 72 + 138: 61 79 + 13a: 5f 65 6e 64 + 13e: 00 5f + 140: 5f 69 6e 69 + 144: 74 5f + 146: 61 72 + 148: 72 61 + 14a: 79 5f + 14c: 73 74 61 72 csrrci s0, 1830, 2 + 150: 74 00 + 152: 5f 5f 70 72 + 156: 65 69 + 158: 6e 69 + 15a: 74 5f + 15c: 61 72 + 15e: 72 61 + 160: 79 5f + 162: 73 74 61 72 csrrci s0, 1830, 2 + 166: 74 00 + 168: 5f 5f 73 74 + 16c: 61 63 + 16e: 6b 5f 75 73 + 172: 61 67 + 174: 65 00 + 176: 5f 5f 73 74 + 17a: 61 63 + 17c: 6b 5f 73 69 + 180: 7a 65 + 182: 00 67 + 184: 5f 77 73 70 + 188: 61 77 + 18a: 6e 5f + 18c: 61 72 + 18e: 67 73 00 5f + 192: 5f 53 44 41 + 196: 54 41 + 198: 5f 42 45 47 + 19c: 49 4e + 19e: 5f 5f 00 5f + 1a2: 5f 67 6c 6f + 1a6: 62 61 + 1a8: 6c 5f + 1aa: 70 6f + 1ac: 69 6e + 1ae: 74 65 + 1b0: 72 00 + 1b2: 5f 67 6c 6f + 1b6: 62 61 + 1b8: 6c 5f + 1ba: 69 6d + 1bc: 70 75 + 1be: 72 65 + 1c0: 5f 70 74 72 + 1c4: 00 5f + 1c6: 5f 6c 69 62 + 1ca: 63 5f 69 6e bge s2, t1, 1790 + 1ce: 69 74 + 1d0: 5f 61 72 72 + 1d4: 61 79 + 1d6: 00 5f + 1d8: 5f 6c 69 62 + 1dc: 63 5f 66 69 bge a2, s6, 1694 + 1e0: 6e 69 + 1e2: 5f 61 72 72 + 1e6: 61 79 + 1e8: 00 5f + 1ea: 70 6f + 1ec: 63 6c 5f 6b bltu t5, s5, 1720 + 1f0: 65 72 + 1f2: 6e 65 + 1f4: 6c 5f + 1f6: 73 61 78 70 csrrsi sp, 1799, 16 + 1fa: 79 00 + 1fc: 76 78 + 1fe: 5f 73 65 74 + 202: 5f 73 70 00 + 206: 5f 5f 63 61 + 20a: 6c 6c + 20c: 5f 65 78 69 + 210: 74 70 + 212: 72 6f + 214: 63 73 00 5f bgeu zero, a6, 1510 + 218: 5f 72 65 67 + 21c: 69 73 + 21e: 74 65 + 220: 72 5f + 222: 65 78 + 224: 69 74 + 226: 70 72 + 228: 6f 63 00 5f jal t1, 26096 + 22c: 5f 42 53 53 + 230: 5f 45 4e 44 + 234: 5f 5f 00 5f + 238: 5f 62 73 73 + 23c: 5f 73 74 61 + 240: 72 74 + 242: 00 6d + 244: 65 6d + 246: 73 65 74 00 csrrsi a0, 7, 8 + 24a: 6d 61 + 24c: 69 6e + 24e: 00 5f + 250: 70 6f + 252: 63 6c 5f 6b bltu t5, s5, 1720 + 256: 65 72 + 258: 6e 65 + 25a: 6c 5f + 25c: 73 61 78 70 csrrsi sp, 1799, 16 + 260: 79 5f + 262: 77 6f 72 6b + 266: 67 72 6f 75 + 26a: 70 5f + 26c: 66 61 + 26e: 73 74 00 61 csrrci s0, 1552, 0 + 272: 74 65 + 274: 78 69 + 276: 74 00 + 278: 5f 5f 44 41 + 27c: 54 41 + 27e: 5f 42 45 47 + 282: 49 4e + 284: 5f 5f 00 5f + 288: 65 64 + 28a: 61 74 + 28c: 61 00 + 28e: 76 78 + 290: 5f 70 65 72 + 294: 66 5f + 296: 64 75 + 298: 6d 70 + 29a: 00 5f + 29c: 65 78 + 29e: 69 74 + 2a0: 00 5f + 2a2: 70 6f + 2a4: 63 6c 5f 6b bltu t5, s5, 1720 + 2a8: 65 72 + 2aa: 6e 65 + 2ac: 6c 5f + 2ae: 73 61 78 70 csrrsi sp, 1799, 16 + 2b2: 79 5f + 2b4: 77 6f 72 6b + 2b8: 67 72 6f 75 + 2bc: 70 00 + 2be: 76 78 + 2c0: 5f 73 70 61 + 2c4: 77 6e 5f 6b + 2c8: 65 72 + 2ca: 6e 65 + 2cc: 6c 00 Disassembly of section .shstrtab: diff --git a/tests/opencl/sfilter/Makefile b/tests/opencl/sfilter/Makefile index 6a22e827..bf9849bb 100644 --- a/tests/opencl/sfilter/Makefile +++ b/tests/opencl/sfilter/Makefile @@ -9,8 +9,8 @@ VORTEX_RT_PATH ?= $(realpath ../../../runtime) OPTS ?= -n16 -K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -float-abi=hard -code-model=small" -K_CFLAGS += "-v -O3 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" +K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -mattr=+vortex -float-abi=hard -code-model=small" +K_CFLAGS += "-v -O3 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -Xclang -target-feature -Xclang +vortex -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" K_LDFLAGS += "-Wl,-Bstatic,-T$(VORTEX_RT_PATH)/linker/vx_link.ld -Wl,--gc-sections $(VORTEX_RT_PATH)/libvortexrt.a -lm" CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors @@ -35,13 +35,13 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ run-fpga: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-simx: $(PROJECT) kernel.pocl LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/opencl/sfilter/kernel.pocl b/tests/opencl/sfilter/kernel.pocl index d25af866..573a663c 100644 Binary files a/tests/opencl/sfilter/kernel.pocl and b/tests/opencl/sfilter/kernel.pocl differ diff --git a/tests/opencl/sfilter/sfilter.dump b/tests/opencl/sfilter/sfilter.dump index fa8424d3..34b6463d 100644 --- a/tests/opencl/sfilter/sfilter.dump +++ b/tests/opencl/sfilter/sfilter.dump @@ -1,30 +1,30 @@ -/tmp/pocl_vortex_kernel-9f-8e-ef-77-50.elf: file format ELF32-riscv +/tmp/pocl_vortex_kernel-e6-7b-41-af-c4.elf: file format ELF32-riscv Disassembly of section .init: 80000000 _start: 80000000: 97 05 00 00 auipc a1, 0 -80000004: 93 85 05 7d addi a1, a1, 2000 +80000004: 93 85 c5 7d addi a1, a1, 2012 80000008: 73 25 10 fc csrr a0, 4033 -8000000c: 6b 10 b5 00 -80000010: ef 00 00 7c jal 1984 +8000000c: 6b 10 b5 00 vx_wspawn a0, a1 +80000010: ef 00 c0 7c jal 1996 80000014: 13 05 10 00 addi a0, zero, 1 -80000018: 6b 00 05 00 +80000018: 6b 00 05 00 vx_tmc a0 8000001c: 17 25 00 00 auipc a0, 2 -80000020: 13 05 85 58 addi a0, a0, 1416 +80000020: 13 05 85 5d addi a0, a0, 1496 80000024: 17 26 00 00 auipc a2, 2 -80000028: 13 06 06 60 addi a2, a2, 1536 +80000028: 13 06 06 65 addi a2, a2, 1616 8000002c: 33 06 a6 40 sub a2, a2, a0 80000030: 93 05 00 00 mv a1, zero -80000034: ef 00 10 6a jal 3744 +80000034: ef 00 10 6f jal 3824 80000038: 17 15 00 00 auipc a0, 1 -8000003c: 13 05 45 da addi a0, a0, -604 -80000040: ef 00 50 55 jal 3412 -80000044: ef 00 50 5f jal 3572 +8000003c: 13 05 45 87 addi a0, a0, -1932 +80000040: ef 00 d0 69 jal 3740 +80000044: ef 00 c0 7c jal 1996 80000048: ef 00 00 02 jal 32 -8000004c: 6f 00 d0 55 j 3420 +8000004c: 6f 00 50 6a j 3748 Disassembly of section .text: @@ -32,8 +32,8 @@ Disassembly of section .text: 80000050: 93 07 00 00 mv a5, zero 80000054: 63 88 07 00 beqz a5, 16 80000058: 37 15 00 80 lui a0, 524289 -8000005c: 13 05 c5 dd addi a0, a0, -548 -80000060: 6f 00 50 53 j 3380 +8000005c: 13 05 c5 8a addi a0, a0, -1876 +80000060: 6f 00 d0 67 j 3708 80000064: 67 80 00 00 ret 80000068 main: @@ -44,7 +44,7 @@ Disassembly of section .text: 80000078: 37 05 ff 7f lui a0, 524272 8000007c: 13 06 45 03 addi a2, a0, 52 80000080: 37 05 ff 7f lui a0, 524272 -80000084: ef 00 10 0d jal 2256 +80000084: ef 00 10 29 jal 2704 80000088: 13 05 00 00 mv a0, zero 8000008c: 83 20 c1 00 lw ra, 12(sp) 80000090: 13 01 01 01 addi sp, sp, 16 @@ -516,690 +516,716 @@ Disassembly of section .text: 800007c0: 67 80 00 00 ret 800007c4 _exit: -800007c4: ef 00 c0 3b jal 956 -800007c8: 13 05 00 00 mv a0, zero -800007cc: 6b 00 05 00 +800007c4: 63 06 05 00 beqz a0, 12 +800007c8: 93 01 05 00 mv gp, a0 +800007cc: 73 00 00 00 ecall -800007d0 vx_set_sp: -800007d0: 73 25 00 fc csrr a0, 4032 -800007d4: 6b 00 05 00 -800007d8: 97 21 00 00 auipc gp, 2 -800007dc: 93 81 01 1a addi gp, gp, 416 -800007e0: 17 01 00 7f auipc sp, 520192 -800007e4: 13 01 01 82 addi sp, sp, -2016 -800007e8: 93 05 00 40 addi a1, zero, 1024 -800007ec: 73 26 10 cc csrr a2, 3265 -800007f0: b3 85 c5 02 mul a1, a1, a2 -800007f4: 33 01 b1 40 sub sp, sp, a1 -800007f8: f3 26 30 cc csrr a3, 3267 -800007fc: 63 86 06 00 beqz a3, 12 -80000800: 13 05 00 00 mv a0, zero -80000804: 6b 00 05 00 +800007d0 label_exit_next: +800007d0: ef 00 80 4f jal 1272 +800007d4: 13 05 00 00 mv a0, zero +800007d8: 6b 00 05 00 vx_tmc a0 -80000808 RETURN: -80000808: 67 80 00 00 ret +800007dc vx_set_sp: +800007dc: 13 05 f0 ff addi a0, zero, -1 +800007e0: 6b 00 05 00 vx_tmc a0 +800007e4: 97 21 00 00 auipc gp, 2 +800007e8: 93 81 41 1e addi gp, gp, 484 +800007ec: 37 01 00 ff lui sp, 1044480 +800007f0: 73 26 10 cc csrr a2, 3265 +800007f4: 93 15 a6 00 slli a1, a2, 10 +800007f8: 33 01 b1 40 sub sp, sp, a1 +800007fc: f3 26 30 cc csrr a3, 3267 +80000800: 63 86 06 00 beqz a3, 12 +80000804: 13 05 00 00 mv a0, zero +80000808: 6b 00 05 00 vx_tmc a0 -8000080c spawn_kernel_callback: -8000080c: 13 01 01 fe addi sp, sp, -32 -80000810: 23 2e 11 00 sw ra, 28(sp) -80000814: 23 2c 81 00 sw s0, 24(sp) -80000818: 23 2a 91 00 sw s1, 20(sp) -8000081c: 23 28 21 01 sw s2, 16(sp) -80000820: 23 26 31 01 sw s3, 12(sp) -80000824: 23 24 41 01 sw s4, 8(sp) -80000828: 23 22 51 01 sw s5, 4(sp) -8000082c: f3 27 00 fc csrr a5, 4032 -80000830: 6b 80 07 00 -80000834: f3 26 50 cc csrr a3, 3269 -80000838: 73 29 30 cc csrr s2, 3267 -8000083c: 73 27 00 cc csrr a4, 3264 -80000840: 73 26 00 fc csrr a2, 4032 -80000844: b7 27 00 80 lui a5, 524290 -80000848: 93 96 26 00 slli a3, a3, 2 -8000084c: 93 87 47 5a addi a5, a5, 1444 -80000850: b3 87 d7 00 add a5, a5, a3 -80000854: 03 a4 07 00 lw s0, 0(a5) -80000858: 83 24 44 01 lw s1, 20(s0) -8000085c: 83 26 04 01 lw a3, 16(s0) -80000860: b3 2a 99 00 slt s5, s2, s1 -80000864: 93 87 04 00 mv a5, s1 -80000868: b3 8a da 00 add s5, s5, a3 -8000086c: b3 84 26 03 mul s1, a3, s2 -80000870: 63 54 f9 00 bge s2, a5, 8 -80000874: 93 07 09 00 mv a5, s2 -80000878: b3 84 f4 00 add s1, s1, a5 -8000087c: 83 25 04 00 lw a1, 0(s0) -80000880: 83 26 c4 00 lw a3, 12(s0) -80000884: 83 a9 05 00 lw s3, 0(a1) -80000888: 03 aa 45 00 lw s4, 4(a1) -8000088c: b3 84 c4 02 mul s1, s1, a2 -80000890: b3 87 ea 02 mul a5, s5, a4 -80000894: b3 84 d4 00 add s1, s1, a3 -80000898: b3 84 f4 00 add s1, s1, a5 -8000089c: b3 8a 9a 00 add s5, s5, s1 -800008a0: 33 8a 49 03 mul s4, s3, s4 -800008a4: 63 c0 54 07 blt s1, s5, 96 -800008a8: 6f 00 00 08 j 128 -800008ac: 03 47 a4 01 lbu a4, 26(s0) -800008b0: 83 46 94 01 lbu a3, 25(s0) -800008b4: 33 d7 e4 40 sra a4, s1, a4 -800008b8: b3 07 47 03 mul a5, a4, s4 -800008bc: b3 87 f4 40 sub a5, s1, a5 -800008c0: 63 80 06 06 beqz a3, 96 -800008c4: 83 46 b4 01 lbu a3, 27(s0) -800008c8: b3 d6 d7 40 sra a3, a5, a3 -800008cc: b3 88 36 03 mul a7, a3, s3 -800008d0: 03 ae 45 01 lw t3, 20(a1) -800008d4: 03 a3 05 01 lw t1, 16(a1) -800008d8: 03 a6 c5 00 lw a2, 12(a1) -800008dc: 03 28 44 00 lw a6, 4(s0) -800008e0: 03 25 84 00 lw a0, 8(s0) -800008e4: 93 84 14 00 addi s1, s1, 1 -800008e8: 33 07 c7 01 add a4, a4, t3 -800008ec: b3 86 66 00 add a3, a3, t1 -800008f0: b3 87 17 41 sub a5, a5, a7 -800008f4: 33 86 c7 00 add a2, a5, a2 -800008f8: e7 00 08 00 jalr a6 -800008fc: 63 86 9a 02 beq s5, s1, 44 -80000900: 83 25 04 00 lw a1, 0(s0) -80000904: 83 47 84 01 lbu a5, 24(s0) -80000908: e3 92 07 fa bnez a5, -92 -8000090c: 33 c7 44 03 div a4, s1, s4 -80000910: 83 46 94 01 lbu a3, 25(s0) -80000914: b3 07 47 03 mul a5, a4, s4 -80000918: b3 87 f4 40 sub a5, s1, a5 -8000091c: e3 94 06 fa bnez a3, -88 -80000920: b3 c6 37 03 div a3, a5, s3 -80000924: 6f f0 9f fa j -88 -80000928: 13 39 19 00 seqz s2, s2 -8000092c: 6b 00 09 00 -80000930: 83 20 c1 01 lw ra, 28(sp) -80000934: 03 24 81 01 lw s0, 24(sp) -80000938: 83 24 41 01 lw s1, 20(sp) -8000093c: 03 29 01 01 lw s2, 16(sp) -80000940: 83 29 c1 00 lw s3, 12(sp) -80000944: 03 2a 81 00 lw s4, 8(sp) -80000948: 83 2a 41 00 lw s5, 4(sp) -8000094c: 13 01 01 02 addi sp, sp, 32 -80000950: 67 80 00 00 ret +8000080c RETURN: +8000080c: 67 80 00 00 ret -80000954 vx_spawn_kernel: -80000954: 13 01 01 fc addi sp, sp, -64 -80000958: 23 2e 11 02 sw ra, 60(sp) -8000095c: 23 2c 81 02 sw s0, 56(sp) -80000960: 23 2a 91 02 sw s1, 52(sp) -80000964: 23 28 21 03 sw s2, 48(sp) -80000968: 23 26 31 03 sw s3, 44(sp) -8000096c: f3 28 20 fc csrr a7, 4034 -80000970: 73 23 10 fc csrr t1, 4033 -80000974: 73 24 00 fc csrr s0, 4032 -80000978: f3 27 50 cc csrr a5, 3269 -8000097c: 13 07 f0 01 addi a4, zero, 31 -80000980: 63 46 f7 0e blt a4, a5, 236 -80000984: 03 2e 05 00 lw t3, 0(a0) -80000988: 83 26 45 00 lw a3, 4(a0) -8000098c: 03 28 85 00 lw a6, 8(a0) -80000990: b3 0e 83 02 mul t4, t1, s0 -80000994: 13 07 10 00 addi a4, zero, 1 -80000998: b3 06 de 02 mul a3, t3, a3 -8000099c: 33 88 06 03 mul a6, a3, a6 -800009a0: 63 d4 0e 01 bge t4, a6, 8 -800009a4: 33 47 d8 03 div a4, a6, t4 -800009a8: 63 c0 e8 0e blt a7, a4, 224 -800009ac: 63 d0 e7 0c bge a5, a4, 192 -800009b0: 93 88 f8 ff addi a7, a7, -1 -800009b4: b3 4e e8 02 div t4, a6, a4 -800009b8: 93 84 0e 00 mv s1, t4 -800009bc: 63 96 f8 00 bne a7, a5, 12 -800009c0: 33 67 e8 02 rem a4, a6, a4 -800009c4: b3 04 d7 01 add s1, a4, t4 -800009c8: 33 c9 84 02 div s2, s1, s0 -800009cc: b3 e4 84 02 rem s1, s1, s0 -800009d0: 63 42 69 0c blt s2, t1, 196 -800009d4: 93 02 10 00 addi t0, zero, 1 -800009d8: 33 48 69 02 div a6, s2, t1 -800009dc: 63 06 08 00 beqz a6, 12 -800009e0: 93 02 08 00 mv t0, a6 -800009e4: 33 68 69 02 rem a6, s2, t1 -800009e8: d3 f7 06 d0 fcvt.s.w fa5, a3 -800009ec: 93 8f f6 ff addi t6, a3, -1 -800009f0: 13 0f fe ff addi t5, t3, -1 -800009f4: b7 29 00 80 lui s3, 524290 -800009f8: b3 f6 df 00 and a3, t6, a3 -800009fc: 93 89 49 5a addi s3, s3, 1444 -80000a00: 93 b6 16 00 seqz a3, a3 -80000a04: 23 22 a1 00 sw a0, 4(sp) -80000a08: 23 24 b1 00 sw a1, 8(sp) -80000a0c: 23 26 c1 00 sw a2, 12(sp) -80000a10: 23 2a 51 00 sw t0, 20(sp) -80000a14: 23 2c 01 01 sw a6, 24(sp) -80000a18: 23 0e d1 00 sb a3, 28(sp) -80000a1c: 33 87 fe 02 mul a4, t4, a5 -80000a20: d3 8e 07 e0 fmv.x.w t4, fa5 -80000a24: d3 77 0e d0 fcvt.s.w fa5, t3 -80000a28: 93 97 27 00 slli a5, a5, 2 -80000a2c: 33 7e cf 01 and t3, t5, t3 -80000a30: d3 88 07 e0 fmv.x.w a7, fa5 -80000a34: 93 de 7e 41 srai t4, t4, 23 -80000a38: 13 3e 1e 00 seqz t3, t3 -80000a3c: 93 d8 78 41 srai a7, a7, 23 -80000a40: 93 8e 1e f8 addi t4, t4, -127 -80000a44: 93 88 18 f8 addi a7, a7, -127 -80000a48: b3 87 f9 00 add a5, s3, a5 -80000a4c: 23 28 e1 00 sw a4, 16(sp) -80000a50: 13 07 41 00 addi a4, sp, 4 -80000a54: a3 0e c1 01 sb t3, 29(sp) -80000a58: 23 0f d1 01 sb t4, 30(sp) -80000a5c: a3 0f 11 01 sb a7, 31(sp) -80000a60: 23 a0 e7 00 sw a4, 0(a5) -80000a64: 63 4e 20 03 bgtz s2, 60 -80000a68: 63 9c 04 04 bnez s1, 88 -80000a6c: 83 20 c1 03 lw ra, 60(sp) -80000a70: 03 24 81 03 lw s0, 56(sp) -80000a74: 83 24 41 03 lw s1, 52(sp) -80000a78: 03 29 01 03 lw s2, 48(sp) -80000a7c: 83 29 c1 02 lw s3, 44(sp) -80000a80: 13 01 01 04 addi sp, sp, 64 -80000a84: 67 80 00 00 ret -80000a88: 13 87 08 00 mv a4, a7 -80000a8c: e3 c2 e7 f2 blt a5, a4, -220 -80000a90: 6f f0 df fd j -36 -80000a94: 13 08 00 00 mv a6, zero -80000a98: 93 02 10 00 addi t0, zero, 1 -80000a9c: 6f f0 df f4 j -180 -80000aa0: 13 07 09 00 mv a4, s2 -80000aa4: 63 54 23 01 bge t1, s2, 8 -80000aa8: 13 07 03 00 mv a4, t1 -80000aac: b7 17 00 80 lui a5, 524289 -80000ab0: 93 87 c7 80 addi a5, a5, -2036 -80000ab4: 6b 10 f7 00 -80000ab8: ef f0 5f d5 jal -684 -80000abc: e3 88 04 fa beqz s1, -80 -80000ac0: 33 04 89 02 mul s0, s2, s0 -80000ac4: 23 28 81 00 sw s0, 16(sp) -80000ac8: 6b 80 04 00 -80000acc: 73 27 50 cc csrr a4, 3269 -80000ad0: f3 27 20 cc csrr a5, 3266 -80000ad4: 13 17 27 00 slli a4, a4, 2 -80000ad8: b3 89 e9 00 add s3, s3, a4 -80000adc: 03 a5 09 00 lw a0, 0(s3) -80000ae0: 83 25 05 00 lw a1, 0(a0) -80000ae4: 83 26 c5 00 lw a3, 12(a0) -80000ae8: 03 47 85 01 lbu a4, 24(a0) -80000aec: 03 a8 05 00 lw a6, 0(a1) -80000af0: 03 a6 45 00 lw a2, 4(a1) -80000af4: b3 87 d7 00 add a5, a5, a3 -80000af8: 33 06 c8 02 mul a2, a6, a2 -80000afc: 63 0e 07 06 beqz a4, 124 -80000b00: 03 47 a5 01 lbu a4, 26(a0) -80000b04: 33 d7 e7 40 sra a4, a5, a4 -80000b08: 83 46 95 01 lbu a3, 25(a0) -80000b0c: 33 06 e6 02 mul a2, a2, a4 -80000b10: b3 87 c7 40 sub a5, a5, a2 -80000b14: 63 8e 06 04 beqz a3, 92 -80000b18: 83 48 b5 01 lbu a7, 27(a0) -80000b1c: b3 d8 17 41 sra a7, a5, a7 -80000b20: 33 08 18 03 mul a6, a6, a7 -80000b24: 03 ae 45 01 lw t3, 20(a1) -80000b28: 83 a6 05 01 lw a3, 16(a1) -80000b2c: 03 a6 c5 00 lw a2, 12(a1) -80000b30: 03 23 45 00 lw t1, 4(a0) -80000b34: 03 25 85 00 lw a0, 8(a0) -80000b38: 33 07 c7 01 add a4, a4, t3 -80000b3c: b3 86 d8 00 add a3, a7, a3 -80000b40: b3 87 07 41 sub a5, a5, a6 -80000b44: 33 86 c7 00 add a2, a5, a2 -80000b48: e7 00 03 00 jalr t1 -80000b4c: 93 07 10 00 addi a5, zero, 1 -80000b50: 6b 80 07 00 -80000b54: 83 20 c1 03 lw ra, 60(sp) -80000b58: 03 24 81 03 lw s0, 56(sp) -80000b5c: 83 24 41 03 lw s1, 52(sp) -80000b60: 03 29 01 03 lw s2, 48(sp) -80000b64: 83 29 c1 02 lw s3, 44(sp) -80000b68: 13 01 01 04 addi sp, sp, 64 -80000b6c: 67 80 00 00 ret -80000b70: b3 c8 07 03 div a7, a5, a6 -80000b74: 6f f0 df fa j -84 -80000b78: 33 c7 c7 02 div a4, a5, a2 -80000b7c: 6f f0 df f8 j -116 +80000810 __libc_init_array: +80000810: 13 01 01 ff addi sp, sp, -16 +80000814: 23 24 81 00 sw s0, 8(sp) +80000818: 23 20 21 01 sw s2, 0(sp) +8000081c: 37 24 00 80 lui s0, 524290 +80000820: 37 29 00 80 lui s2, 524290 +80000824: 93 07 04 1c addi a5, s0, 448 +80000828: 13 09 09 1c addi s2, s2, 448 +8000082c: 33 09 f9 40 sub s2, s2, a5 +80000830: 23 26 11 00 sw ra, 12(sp) +80000834: 23 22 91 00 sw s1, 4(sp) +80000838: 13 59 29 40 srai s2, s2, 2 +8000083c: 63 00 09 02 beqz s2, 32 +80000840: 13 04 04 1c addi s0, s0, 448 +80000844: 93 04 00 00 mv s1, zero +80000848: 83 27 04 00 lw a5, 0(s0) +8000084c: 93 84 14 00 addi s1, s1, 1 +80000850: 13 04 44 00 addi s0, s0, 4 +80000854: e7 80 07 00 jalr a5 +80000858: e3 18 99 fe bne s2, s1, -16 +8000085c: 37 24 00 80 lui s0, 524290 +80000860: 37 29 00 80 lui s2, 524290 +80000864: 93 07 04 1c addi a5, s0, 448 +80000868: 13 09 49 1c addi s2, s2, 452 +8000086c: 33 09 f9 40 sub s2, s2, a5 +80000870: 13 59 29 40 srai s2, s2, 2 +80000874: 63 00 09 02 beqz s2, 32 +80000878: 13 04 04 1c addi s0, s0, 448 +8000087c: 93 04 00 00 mv s1, zero +80000880: 83 27 04 00 lw a5, 0(s0) +80000884: 93 84 14 00 addi s1, s1, 1 +80000888: 13 04 44 00 addi s0, s0, 4 +8000088c: e7 80 07 00 jalr a5 +80000890: e3 18 99 fe bne s2, s1, -16 +80000894: 83 20 c1 00 lw ra, 12(sp) +80000898: 03 24 81 00 lw s0, 8(sp) +8000089c: 83 24 41 00 lw s1, 4(sp) +800008a0: 03 29 01 00 lw s2, 0(sp) +800008a4: 13 01 01 01 addi sp, sp, 16 +800008a8: 67 80 00 00 ret -80000b80 vx_perf_dump: -80000b80: f3 27 50 cc csrr a5, 3269 -80000b84: 37 07 ff 00 lui a4, 4080 -80000b88: b3 87 e7 00 add a5, a5, a4 -80000b8c: 93 97 87 00 slli a5, a5, 8 -80000b90: 73 27 00 b0 csrr a4, mcycle -80000b94: 23 a0 e7 00 sw a4, 0(a5) -80000b98: 73 27 10 b0 csrr a4, 2817 -80000b9c: 23 a2 e7 00 sw a4, 4(a5) -80000ba0: 73 27 20 b0 csrr a4, minstret -80000ba4: 23 a4 e7 00 sw a4, 8(a5) -80000ba8: 73 27 30 b0 csrr a4, mhpmcounter3 -80000bac: 23 a6 e7 00 sw a4, 12(a5) -80000bb0: 73 27 40 b0 csrr a4, mhpmcounter4 -80000bb4: 23 a8 e7 00 sw a4, 16(a5) -80000bb8: 73 27 50 b0 csrr a4, mhpmcounter5 -80000bbc: 23 aa e7 00 sw a4, 20(a5) -80000bc0: 73 27 60 b0 csrr a4, mhpmcounter6 -80000bc4: 23 ac e7 00 sw a4, 24(a5) -80000bc8: 73 27 70 b0 csrr a4, mhpmcounter7 -80000bcc: 23 ae e7 00 sw a4, 28(a5) -80000bd0: 73 27 80 b0 csrr a4, mhpmcounter8 -80000bd4: 23 a0 e7 02 sw a4, 32(a5) -80000bd8: 73 27 90 b0 csrr a4, mhpmcounter9 -80000bdc: 23 a2 e7 02 sw a4, 36(a5) -80000be0: 73 27 a0 b0 csrr a4, mhpmcounter10 -80000be4: 23 a4 e7 02 sw a4, 40(a5) -80000be8: 73 27 b0 b0 csrr a4, mhpmcounter11 -80000bec: 23 a6 e7 02 sw a4, 44(a5) -80000bf0: 73 27 c0 b0 csrr a4, mhpmcounter12 -80000bf4: 23 a8 e7 02 sw a4, 48(a5) -80000bf8: 73 27 d0 b0 csrr a4, mhpmcounter13 -80000bfc: 23 aa e7 02 sw a4, 52(a5) -80000c00: 73 27 e0 b0 csrr a4, mhpmcounter14 -80000c04: 23 ac e7 02 sw a4, 56(a5) -80000c08: 73 27 f0 b0 csrr a4, mhpmcounter15 -80000c0c: 23 ae e7 02 sw a4, 60(a5) -80000c10: 73 27 00 b1 csrr a4, mhpmcounter16 -80000c14: 23 a0 e7 04 sw a4, 64(a5) -80000c18: 73 27 10 b1 csrr a4, mhpmcounter17 -80000c1c: 23 a2 e7 04 sw a4, 68(a5) -80000c20: 73 27 20 b1 csrr a4, mhpmcounter18 -80000c24: 23 a4 e7 04 sw a4, 72(a5) -80000c28: 73 27 30 b1 csrr a4, mhpmcounter19 -80000c2c: 23 a6 e7 04 sw a4, 76(a5) -80000c30: 73 27 40 b1 csrr a4, mhpmcounter20 -80000c34: 23 a8 e7 04 sw a4, 80(a5) -80000c38: 73 27 50 b1 csrr a4, mhpmcounter21 -80000c3c: 23 aa e7 04 sw a4, 84(a5) -80000c40: 73 27 60 b1 csrr a4, mhpmcounter22 -80000c44: 23 ac e7 04 sw a4, 88(a5) -80000c48: 73 27 70 b1 csrr a4, mhpmcounter23 -80000c4c: 23 ae e7 04 sw a4, 92(a5) -80000c50: 73 27 80 b1 csrr a4, mhpmcounter24 -80000c54: 23 a0 e7 06 sw a4, 96(a5) -80000c58: 73 27 90 b1 csrr a4, mhpmcounter25 -80000c5c: 23 a2 e7 06 sw a4, 100(a5) -80000c60: 73 27 a0 b1 csrr a4, mhpmcounter26 -80000c64: 23 a4 e7 06 sw a4, 104(a5) -80000c68: 73 27 b0 b1 csrr a4, mhpmcounter27 -80000c6c: 23 a6 e7 06 sw a4, 108(a5) -80000c70: 73 27 c0 b1 csrr a4, mhpmcounter28 -80000c74: 23 a8 e7 06 sw a4, 112(a5) -80000c78: 73 27 d0 b1 csrr a4, mhpmcounter29 -80000c7c: 23 aa e7 06 sw a4, 116(a5) -80000c80: 73 27 e0 b1 csrr a4, mhpmcounter30 -80000c84: 23 ac e7 06 sw a4, 120(a5) -80000c88: 73 27 f0 b1 csrr a4, mhpmcounter31 -80000c8c: 23 ae e7 06 sw a4, 124(a5) -80000c90: 73 27 00 b8 csrr a4, mcycleh -80000c94: 23 a0 e7 08 sw a4, 128(a5) -80000c98: 73 27 10 b8 csrr a4, 2945 -80000c9c: 23 a2 e7 08 sw a4, 132(a5) -80000ca0: 73 27 20 b8 csrr a4, minstreth -80000ca4: 23 a4 e7 08 sw a4, 136(a5) -80000ca8: 73 27 30 b8 csrr a4, mhpmcounter3h -80000cac: 23 a6 e7 08 sw a4, 140(a5) -80000cb0: 73 27 40 b8 csrr a4, mhpmcounter4h -80000cb4: 23 a8 e7 08 sw a4, 144(a5) -80000cb8: 73 27 50 b8 csrr a4, mhpmcounter5h -80000cbc: 23 aa e7 08 sw a4, 148(a5) -80000cc0: 73 27 60 b8 csrr a4, mhpmcounter6h -80000cc4: 23 ac e7 08 sw a4, 152(a5) -80000cc8: 73 27 70 b8 csrr a4, mhpmcounter7h -80000ccc: 23 ae e7 08 sw a4, 156(a5) -80000cd0: 73 27 80 b8 csrr a4, mhpmcounter8h -80000cd4: 23 a0 e7 0a sw a4, 160(a5) -80000cd8: 73 27 90 b8 csrr a4, mhpmcounter9h -80000cdc: 23 a2 e7 0a sw a4, 164(a5) -80000ce0: 73 27 a0 b8 csrr a4, mhpmcounter10h -80000ce4: 23 a4 e7 0a sw a4, 168(a5) -80000ce8: 73 27 b0 b8 csrr a4, mhpmcounter11h -80000cec: 23 a6 e7 0a sw a4, 172(a5) -80000cf0: 73 27 c0 b8 csrr a4, mhpmcounter12h -80000cf4: 23 a8 e7 0a sw a4, 176(a5) -80000cf8: 73 27 d0 b8 csrr a4, mhpmcounter13h -80000cfc: 23 aa e7 0a sw a4, 180(a5) -80000d00: 73 27 e0 b8 csrr a4, mhpmcounter14h -80000d04: 23 ac e7 0a sw a4, 184(a5) -80000d08: 73 27 f0 b8 csrr a4, mhpmcounter15h -80000d0c: 23 ae e7 0a sw a4, 188(a5) -80000d10: 73 27 00 b9 csrr a4, mhpmcounter16h -80000d14: 23 a0 e7 0c sw a4, 192(a5) -80000d18: 73 27 10 b9 csrr a4, mhpmcounter17h -80000d1c: 23 a2 e7 0c sw a4, 196(a5) -80000d20: 73 27 20 b9 csrr a4, mhpmcounter18h -80000d24: 23 a4 e7 0c sw a4, 200(a5) -80000d28: 73 27 30 b9 csrr a4, mhpmcounter19h -80000d2c: 23 a6 e7 0c sw a4, 204(a5) -80000d30: 73 27 40 b9 csrr a4, mhpmcounter20h -80000d34: 23 a8 e7 0c sw a4, 208(a5) -80000d38: 73 27 50 b9 csrr a4, mhpmcounter21h -80000d3c: 23 aa e7 0c sw a4, 212(a5) -80000d40: 73 27 60 b9 csrr a4, mhpmcounter22h -80000d44: 23 ac e7 0c sw a4, 216(a5) -80000d48: 73 27 70 b9 csrr a4, mhpmcounter23h -80000d4c: 23 ae e7 0c sw a4, 220(a5) -80000d50: 73 27 80 b9 csrr a4, mhpmcounter24h -80000d54: 23 a0 e7 0e sw a4, 224(a5) -80000d58: 73 27 90 b9 csrr a4, mhpmcounter25h -80000d5c: 23 a2 e7 0e sw a4, 228(a5) -80000d60: 73 27 a0 b9 csrr a4, mhpmcounter26h -80000d64: 23 a4 e7 0e sw a4, 232(a5) -80000d68: 73 27 b0 b9 csrr a4, mhpmcounter27h -80000d6c: 23 a6 e7 0e sw a4, 236(a5) -80000d70: 73 27 c0 b9 csrr a4, mhpmcounter28h -80000d74: 23 a8 e7 0e sw a4, 240(a5) -80000d78: 73 27 d0 b9 csrr a4, mhpmcounter29h -80000d7c: 23 aa e7 0e sw a4, 244(a5) -80000d80: 73 27 e0 b9 csrr a4, mhpmcounter30h -80000d84: 23 ac e7 0e sw a4, 248(a5) -80000d88: 73 27 f0 b9 csrr a4, mhpmcounter31h -80000d8c: 23 ae e7 0e sw a4, 252(a5) -80000d90: 67 80 00 00 ret +800008ac __libc_fini_array: +800008ac: 13 01 01 ff addi sp, sp, -16 +800008b0: 23 24 81 00 sw s0, 8(sp) +800008b4: b7 27 00 80 lui a5, 524290 +800008b8: 37 24 00 80 lui s0, 524290 +800008bc: 13 04 44 1c addi s0, s0, 452 +800008c0: 93 87 47 1c addi a5, a5, 452 +800008c4: b3 87 87 40 sub a5, a5, s0 +800008c8: 23 22 91 00 sw s1, 4(sp) +800008cc: 23 26 11 00 sw ra, 12(sp) +800008d0: 93 d4 27 40 srai s1, a5, 2 +800008d4: 63 80 04 02 beqz s1, 32 +800008d8: 93 87 c7 ff addi a5, a5, -4 +800008dc: 33 84 87 00 add s0, a5, s0 +800008e0: 83 27 04 00 lw a5, 0(s0) +800008e4: 93 84 f4 ff addi s1, s1, -1 +800008e8: 13 04 c4 ff addi s0, s0, -4 +800008ec: e7 80 07 00 jalr a5 +800008f0: e3 98 04 fe bnez s1, -16 +800008f4: 83 20 c1 00 lw ra, 12(sp) +800008f8: 03 24 81 00 lw s0, 8(sp) +800008fc: 83 24 41 00 lw s1, 4(sp) +80000900: 13 01 01 01 addi sp, sp, 16 +80000904: 67 80 00 00 ret -80000d94 atexit: -80000d94: 93 05 05 00 mv a1, a0 -80000d98: 93 06 00 00 mv a3, zero -80000d9c: 13 06 00 00 mv a2, zero -80000da0: 13 05 00 00 mv a0, zero -80000da4: 6f 00 c0 20 j 524 +80000908 spawn_kernel_all_stub: +80000908: 13 01 01 fe addi sp, sp, -32 +8000090c: 23 2e 11 00 sw ra, 28(sp) +80000910: 23 2c 81 00 sw s0, 24(sp) +80000914: 23 2a 91 00 sw s1, 20(sp) +80000918: 23 28 21 01 sw s2, 16(sp) +8000091c: 23 26 31 01 sw s3, 12(sp) +80000920: 23 24 41 01 sw s4, 8(sp) +80000924: 73 26 50 cc csrr a2, 3269 +80000928: 73 27 30 cc csrr a4, 3267 +8000092c: f3 26 00 cc csrr a3, 3264 +80000930: 73 25 00 fc csrr a0, 4032 +80000934: b7 27 00 80 lui a5, 524290 +80000938: 13 16 26 00 slli a2, a2, 2 +8000093c: 93 87 47 5f addi a5, a5, 1524 +80000940: b3 87 c7 00 add a5, a5, a2 +80000944: 03 a4 07 00 lw s0, 0(a5) +80000948: 83 24 44 01 lw s1, 20(s0) +8000094c: 03 26 04 01 lw a2, 16(s0) +80000950: 33 2a 97 00 slt s4, a4, s1 +80000954: 93 87 04 00 mv a5, s1 +80000958: 33 0a ca 00 add s4, s4, a2 +8000095c: b3 04 e6 02 mul s1, a2, a4 +80000960: 63 54 f7 00 bge a4, a5, 8 +80000964: 93 07 07 00 mv a5, a4 +80000968: b3 84 f4 00 add s1, s1, a5 +8000096c: 83 25 04 00 lw a1, 0(s0) +80000970: 03 27 c4 00 lw a4, 12(s0) +80000974: 03 a9 05 00 lw s2, 0(a1) +80000978: 83 a9 45 00 lw s3, 4(a1) +8000097c: b3 84 a4 02 mul s1, s1, a0 +80000980: b3 07 da 02 mul a5, s4, a3 +80000984: b3 84 e4 00 add s1, s1, a4 +80000988: b3 84 f4 00 add s1, s1, a5 +8000098c: 33 0a 9a 00 add s4, s4, s1 +80000990: b3 09 39 03 mul s3, s2, s3 +80000994: 63 c0 44 07 blt s1, s4, 96 +80000998: 6f 00 00 08 j 128 +8000099c: 03 47 e4 01 lbu a4, 30(s0) +800009a0: 83 46 d4 01 lbu a3, 29(s0) +800009a4: 33 d7 e4 40 sra a4, s1, a4 +800009a8: b3 07 37 03 mul a5, a4, s3 +800009ac: b3 87 f4 40 sub a5, s1, a5 +800009b0: 63 80 06 06 beqz a3, 96 +800009b4: 83 46 f4 01 lbu a3, 31(s0) +800009b8: b3 d6 d7 40 sra a3, a5, a3 +800009bc: b3 88 26 03 mul a7, a3, s2 +800009c0: 03 ae 45 01 lw t3, 20(a1) +800009c4: 03 a3 05 01 lw t1, 16(a1) +800009c8: 03 a6 c5 00 lw a2, 12(a1) +800009cc: 03 28 44 00 lw a6, 4(s0) +800009d0: 03 25 84 00 lw a0, 8(s0) +800009d4: 93 84 14 00 addi s1, s1, 1 +800009d8: 33 07 c7 01 add a4, a4, t3 +800009dc: b3 86 66 00 add a3, a3, t1 +800009e0: b3 87 17 41 sub a5, a5, a7 +800009e4: 33 86 c7 00 add a2, a5, a2 +800009e8: e7 00 08 00 jalr a6 +800009ec: 63 06 9a 02 beq s4, s1, 44 +800009f0: 83 25 04 00 lw a1, 0(s0) +800009f4: 83 47 c4 01 lbu a5, 28(s0) +800009f8: e3 92 07 fa bnez a5, -92 +800009fc: 33 c7 34 03 div a4, s1, s3 +80000a00: 83 46 d4 01 lbu a3, 29(s0) +80000a04: b3 07 37 03 mul a5, a4, s3 +80000a08: b3 87 f4 40 sub a5, s1, a5 +80000a0c: e3 94 06 fa bnez a3, -88 +80000a10: b3 c6 27 03 div a3, a5, s2 +80000a14: 6f f0 9f fa j -88 +80000a18: 03 27 84 01 lw a4, 24(s0) +80000a1c: 93 07 00 00 mv a5, zero +80000a20: 6b c0 e7 00 vx_bar a5, a4 +80000a24: 83 20 c1 01 lw ra, 28(sp) +80000a28: 03 24 81 01 lw s0, 24(sp) +80000a2c: 83 24 41 01 lw s1, 20(sp) +80000a30: 03 29 01 01 lw s2, 16(sp) +80000a34: 83 29 c1 00 lw s3, 12(sp) +80000a38: 03 2a 81 00 lw s4, 8(sp) +80000a3c: 13 01 01 02 addi sp, sp, 32 +80000a40: 67 80 00 00 ret -80000da8 exit: -80000da8: 13 01 01 ff addi sp, sp, -16 -80000dac: 93 05 00 00 mv a1, zero -80000db0: 23 24 81 00 sw s0, 8(sp) -80000db4: 23 26 11 00 sw ra, 12(sp) -80000db8: 13 04 05 00 mv s0, a0 -80000dbc: ef 00 00 29 jal 656 -80000dc0: b7 27 00 80 lui a5, 524290 -80000dc4: 03 a5 07 5a lw a0, 1440(a5) -80000dc8: 83 27 c5 03 lw a5, 60(a0) -80000dcc: 63 84 07 00 beqz a5, 8 -80000dd0: e7 80 07 00 jalr a5 -80000dd4: 13 05 04 00 mv a0, s0 -80000dd8: ef f0 df 9e jal -1556 +80000a44 spawn_kernel_rem_stub: +80000a44: f3 26 50 cc csrr a3, 3269 +80000a48: f3 27 20 cc csrr a5, 3266 +80000a4c: 37 27 00 80 lui a4, 524290 +80000a50: 93 96 26 00 slli a3, a3, 2 +80000a54: 13 07 47 5f addi a4, a4, 1524 +80000a58: 33 07 d7 00 add a4, a4, a3 +80000a5c: 03 25 07 00 lw a0, 0(a4) +80000a60: 83 25 05 00 lw a1, 0(a0) +80000a64: 83 26 c5 00 lw a3, 12(a0) +80000a68: 03 47 c5 01 lbu a4, 28(a0) +80000a6c: 83 a8 05 00 lw a7, 0(a1) +80000a70: 03 a6 45 00 lw a2, 4(a1) +80000a74: b3 87 d7 00 add a5, a5, a3 +80000a78: 33 86 c8 02 mul a2, a7, a2 +80000a7c: 63 08 07 04 beqz a4, 80 +80000a80: 03 47 e5 01 lbu a4, 30(a0) +80000a84: 83 46 d5 01 lbu a3, 29(a0) +80000a88: 33 d7 e7 40 sra a4, a5, a4 +80000a8c: 33 06 c7 02 mul a2, a4, a2 +80000a90: b3 87 c7 40 sub a5, a5, a2 +80000a94: 63 86 06 04 beqz a3, 76 +80000a98: 83 46 f5 01 lbu a3, 31(a0) +80000a9c: 33 d8 d7 40 sra a6, a5, a3 +80000aa0: 83 a6 05 01 lw a3, 16(a1) +80000aa4: 03 ae 45 01 lw t3, 20(a1) +80000aa8: 03 a6 c5 00 lw a2, 12(a1) +80000aac: b3 06 d8 00 add a3, a6, a3 +80000ab0: 33 08 18 03 mul a6, a6, a7 +80000ab4: 03 23 45 00 lw t1, 4(a0) +80000ab8: 03 25 85 00 lw a0, 8(a0) +80000abc: 33 07 c7 01 add a4, a4, t3 +80000ac0: b3 87 07 41 sub a5, a5, a6 +80000ac4: 33 86 c7 00 add a2, a5, a2 +80000ac8: 67 00 03 00 jr t1 +80000acc: 33 c7 c7 02 div a4, a5, a2 +80000ad0: 83 46 d5 01 lbu a3, 29(a0) +80000ad4: 33 06 c7 02 mul a2, a4, a2 +80000ad8: b3 87 c7 40 sub a5, a5, a2 +80000adc: e3 9e 06 fa bnez a3, -68 +80000ae0: 33 c8 17 03 div a6, a5, a7 +80000ae4: 6f f0 df fb j -68 -80000ddc __libc_fini_array: -80000ddc: 13 01 01 ff addi sp, sp, -16 -80000de0: 23 24 81 00 sw s0, 8(sp) -80000de4: b7 27 00 80 lui a5, 524290 -80000de8: 37 24 00 80 lui s0, 524290 -80000dec: 13 04 44 17 addi s0, s0, 372 -80000df0: 93 87 47 17 addi a5, a5, 372 -80000df4: b3 87 87 40 sub a5, a5, s0 -80000df8: 23 22 91 00 sw s1, 4(sp) -80000dfc: 23 26 11 00 sw ra, 12(sp) -80000e00: 93 d4 27 40 srai s1, a5, 2 -80000e04: 63 80 04 02 beqz s1, 32 -80000e08: 93 87 c7 ff addi a5, a5, -4 -80000e0c: 33 84 87 00 add s0, a5, s0 -80000e10: 83 27 04 00 lw a5, 0(s0) -80000e14: 93 84 f4 ff addi s1, s1, -1 -80000e18: 13 04 c4 ff addi s0, s0, -4 -80000e1c: e7 80 07 00 jalr a5 -80000e20: e3 98 04 fe bnez s1, -16 -80000e24: 83 20 c1 00 lw ra, 12(sp) -80000e28: 03 24 81 00 lw s0, 8(sp) -80000e2c: 83 24 41 00 lw s1, 4(sp) -80000e30: 13 01 01 01 addi sp, sp, 16 -80000e34: 67 80 00 00 ret +80000ae8 spawn_kernel_all_cb: +80000ae8: 13 01 01 ff addi sp, sp, -16 +80000aec: 23 26 11 00 sw ra, 12(sp) +80000af0: 93 07 f0 ff addi a5, zero, -1 +80000af4: 6b 80 07 00 vx_tmc a5 +80000af8: ef f0 1f e1 jal -496 +80000afc: f3 27 30 cc csrr a5, 3267 +80000b00: 93 b7 17 00 seqz a5, a5 +80000b04: 6b 80 07 00 vx_tmc a5 +80000b08: 83 20 c1 00 lw ra, 12(sp) +80000b0c: 13 01 01 01 addi sp, sp, 16 +80000b10: 67 80 00 00 ret -80000e38 __libc_init_array: -80000e38: 13 01 01 ff addi sp, sp, -16 -80000e3c: 23 24 81 00 sw s0, 8(sp) -80000e40: 23 20 21 01 sw s2, 0(sp) -80000e44: 37 24 00 80 lui s0, 524290 -80000e48: 37 29 00 80 lui s2, 524290 -80000e4c: 93 07 04 17 addi a5, s0, 368 -80000e50: 13 09 09 17 addi s2, s2, 368 -80000e54: 33 09 f9 40 sub s2, s2, a5 -80000e58: 23 26 11 00 sw ra, 12(sp) -80000e5c: 23 22 91 00 sw s1, 4(sp) -80000e60: 13 59 29 40 srai s2, s2, 2 -80000e64: 63 00 09 02 beqz s2, 32 -80000e68: 13 04 04 17 addi s0, s0, 368 -80000e6c: 93 04 00 00 mv s1, zero -80000e70: 83 27 04 00 lw a5, 0(s0) -80000e74: 93 84 14 00 addi s1, s1, 1 -80000e78: 13 04 44 00 addi s0, s0, 4 -80000e7c: e7 80 07 00 jalr a5 -80000e80: e3 18 99 fe bne s2, s1, -16 -80000e84: 37 24 00 80 lui s0, 524290 -80000e88: 37 29 00 80 lui s2, 524290 -80000e8c: 93 07 04 17 addi a5, s0, 368 -80000e90: 13 09 49 17 addi s2, s2, 372 -80000e94: 33 09 f9 40 sub s2, s2, a5 -80000e98: 13 59 29 40 srai s2, s2, 2 -80000e9c: 63 00 09 02 beqz s2, 32 -80000ea0: 13 04 04 17 addi s0, s0, 368 -80000ea4: 93 04 00 00 mv s1, zero -80000ea8: 83 27 04 00 lw a5, 0(s0) -80000eac: 93 84 14 00 addi s1, s1, 1 -80000eb0: 13 04 44 00 addi s0, s0, 4 -80000eb4: e7 80 07 00 jalr a5 -80000eb8: e3 18 99 fe bne s2, s1, -16 -80000ebc: 83 20 c1 00 lw ra, 12(sp) -80000ec0: 03 24 81 00 lw s0, 8(sp) -80000ec4: 83 24 41 00 lw s1, 4(sp) -80000ec8: 03 29 01 00 lw s2, 0(sp) -80000ecc: 13 01 01 01 addi sp, sp, 16 -80000ed0: 67 80 00 00 ret +80000b14 vx_spawn_kernel: +80000b14: 13 01 01 fd addi sp, sp, -48 +80000b18: 23 26 11 02 sw ra, 44(sp) +80000b1c: 23 24 81 02 sw s0, 40(sp) +80000b20: 23 22 91 02 sw s1, 36(sp) +80000b24: 23 20 21 03 sw s2, 32(sp) +80000b28: f3 28 20 fc csrr a7, 4034 +80000b2c: 73 23 10 fc csrr t1, 4033 +80000b30: f3 24 00 fc csrr s1, 4032 +80000b34: f3 27 50 cc csrr a5, 3269 +80000b38: 13 07 f0 01 addi a4, zero, 31 +80000b3c: 63 46 f7 0e blt a4, a5, 236 +80000b40: 03 2e 05 00 lw t3, 0(a0) +80000b44: 83 26 45 00 lw a3, 4(a0) +80000b48: 03 28 85 00 lw a6, 8(a0) +80000b4c: b3 0e 93 02 mul t4, t1, s1 +80000b50: 13 07 10 00 addi a4, zero, 1 +80000b54: b3 06 de 02 mul a3, t3, a3 +80000b58: 33 88 06 03 mul a6, a3, a6 +80000b5c: 63 d4 0e 01 bge t4, a6, 8 +80000b60: 33 47 d8 03 div a4, a6, t4 +80000b64: 63 ce e8 0c blt a7, a4, 220 +80000b68: 63 d0 e7 0c bge a5, a4, 192 +80000b6c: 93 88 f8 ff addi a7, a7, -1 +80000b70: b3 4e e8 02 div t4, a6, a4 +80000b74: 13 84 0e 00 mv s0, t4 +80000b78: 63 96 f8 00 bne a7, a5, 12 +80000b7c: 33 67 e8 02 rem a4, a6, a4 +80000b80: 33 04 d7 01 add s0, a4, t4 +80000b84: 33 49 94 02 div s2, s0, s1 +80000b88: 33 64 94 02 rem s0, s0, s1 +80000b8c: 63 40 69 0c blt s2, t1, 192 +80000b90: 93 0f 10 00 addi t6, zero, 1 +80000b94: 33 4f 69 02 div t5, s2, t1 +80000b98: 63 06 0f 00 beqz t5, 12 +80000b9c: 93 0f 0f 00 mv t6, t5 +80000ba0: 33 6f 69 02 rem t5, s2, t1 +80000ba4: d3 f7 06 d0 fcvt.s.w fa5, a3 +80000ba8: 13 07 fe ff addi a4, t3, -1 +80000bac: 93 82 f6 ff addi t0, a3, -1 +80000bb0: d3 88 07 e0 fmv.x.w a7, fa5 +80000bb4: d3 77 0e d0 fcvt.s.w fa5, t3 +80000bb8: 33 7e c7 01 and t3, a4, t3 +80000bbc: 37 27 00 80 lui a4, 524290 +80000bc0: 53 88 07 e0 fmv.x.w a6, fa5 +80000bc4: b3 f6 d2 00 and a3, t0, a3 +80000bc8: 93 d8 78 41 srai a7, a7, 23 +80000bcc: 13 58 78 41 srai a6, a6, 23 +80000bd0: 13 07 47 5f addi a4, a4, 1524 +80000bd4: 93 b6 16 00 seqz a3, a3 +80000bd8: 13 3e 1e 00 seqz t3, t3 +80000bdc: 93 88 18 f8 addi a7, a7, -127 +80000be0: 13 08 18 f8 addi a6, a6, -127 +80000be4: 23 20 a1 00 sw a0, 0(sp) +80000be8: 23 22 b1 00 sw a1, 4(sp) +80000bec: 23 24 c1 00 sw a2, 8(sp) +80000bf0: 23 28 f1 01 sw t6, 16(sp) +80000bf4: 23 2a e1 01 sw t5, 20(sp) +80000bf8: 23 2c 01 00 sw zero, 24(sp) +80000bfc: 23 0e d1 00 sb a3, 28(sp) +80000c00: a3 0e c1 01 sb t3, 29(sp) +80000c04: 23 0f 11 01 sb a7, 30(sp) +80000c08: a3 0f 01 01 sb a6, 31(sp) +80000c0c: b3 8e fe 02 mul t4, t4, a5 +80000c10: 93 97 27 00 slli a5, a5, 2 +80000c14: b3 07 f7 00 add a5, a4, a5 +80000c18: 23 a0 27 00 sw sp, 0(a5) +80000c1c: 23 26 d1 01 sw t4, 12(sp) +80000c20: 63 4c 20 03 bgtz s2, 56 +80000c24: 63 16 04 06 bnez s0, 108 +80000c28: 83 20 c1 02 lw ra, 44(sp) +80000c2c: 03 24 81 02 lw s0, 40(sp) +80000c30: 83 24 41 02 lw s1, 36(sp) +80000c34: 03 29 01 02 lw s2, 32(sp) +80000c38: 13 01 01 03 addi sp, sp, 48 +80000c3c: 67 80 00 00 ret +80000c40: 13 87 08 00 mv a4, a7 +80000c44: e3 c4 e7 f2 blt a5, a4, -216 +80000c48: 6f f0 1f fe j -32 +80000c4c: 13 0f 00 00 mv t5, zero +80000c50: 93 0f 10 00 addi t6, zero, 1 +80000c54: 6f f0 1f f5 j -176 +80000c58: 13 07 09 00 mv a4, s2 +80000c5c: 63 54 23 01 bge t1, s2, 8 +80000c60: 13 07 03 00 mv a4, t1 +80000c64: b7 17 00 80 lui a5, 524289 +80000c68: 23 2c e1 00 sw a4, 24(sp) +80000c6c: 93 87 87 ae addi a5, a5, -1304 +80000c70: 6b 10 f7 00 vx_wspawn a4, a5 +80000c74: 93 07 f0 ff addi a5, zero, -1 +80000c78: 6b 80 07 00 vx_tmc a5 +80000c7c: ef f0 df c8 jal -884 +80000c80: f3 27 30 cc csrr a5, 3267 +80000c84: 93 b7 17 00 seqz a5, a5 +80000c88: 6b 80 07 00 vx_tmc a5 +80000c8c: e3 0e 04 f8 beqz s0, -100 +80000c90: b3 04 99 02 mul s1, s2, s1 +80000c94: 13 09 10 00 addi s2, zero, 1 +80000c98: 33 14 89 00 sll s0, s2, s0 +80000c9c: 13 04 f4 ff addi s0, s0, -1 +80000ca0: 23 26 91 00 sw s1, 12(sp) +80000ca4: 6b 00 04 00 vx_tmc s0 +80000ca8: ef f0 df d9 jal -612 +80000cac: 6b 00 09 00 vx_tmc s2 +80000cb0: 83 20 c1 02 lw ra, 44(sp) +80000cb4: 03 24 81 02 lw s0, 40(sp) +80000cb8: 83 24 41 02 lw s1, 36(sp) +80000cbc: 03 29 01 02 lw s2, 32(sp) +80000cc0: 13 01 01 03 addi sp, sp, 48 +80000cc4: 67 80 00 00 ret -80000ed4 memset: -80000ed4: 13 03 f0 00 addi t1, zero, 15 -80000ed8: 13 07 05 00 mv a4, a0 -80000edc: 63 7e c3 02 bgeu t1, a2, 60 -80000ee0: 93 77 f7 00 andi a5, a4, 15 -80000ee4: 63 90 07 0a bnez a5, 160 -80000ee8: 63 92 05 08 bnez a1, 132 -80000eec: 93 76 06 ff andi a3, a2, -16 -80000ef0: 13 76 f6 00 andi a2, a2, 15 -80000ef4: b3 86 e6 00 add a3, a3, a4 -80000ef8: 23 20 b7 00 sw a1, 0(a4) -80000efc: 23 22 b7 00 sw a1, 4(a4) -80000f00: 23 24 b7 00 sw a1, 8(a4) -80000f04: 23 26 b7 00 sw a1, 12(a4) -80000f08: 13 07 07 01 addi a4, a4, 16 -80000f0c: e3 66 d7 fe bltu a4, a3, -20 -80000f10: 63 14 06 00 bnez a2, 8 -80000f14: 67 80 00 00 ret -80000f18: b3 06 c3 40 sub a3, t1, a2 -80000f1c: 93 96 26 00 slli a3, a3, 2 -80000f20: 97 02 00 00 auipc t0, 0 -80000f24: b3 86 56 00 add a3, a3, t0 -80000f28: 67 80 c6 00 jr 12(a3) -80000f2c: 23 07 b7 00 sb a1, 14(a4) -80000f30: a3 06 b7 00 sb a1, 13(a4) -80000f34: 23 06 b7 00 sb a1, 12(a4) -80000f38: a3 05 b7 00 sb a1, 11(a4) -80000f3c: 23 05 b7 00 sb a1, 10(a4) -80000f40: a3 04 b7 00 sb a1, 9(a4) -80000f44: 23 04 b7 00 sb a1, 8(a4) -80000f48: a3 03 b7 00 sb a1, 7(a4) -80000f4c: 23 03 b7 00 sb a1, 6(a4) -80000f50: a3 02 b7 00 sb a1, 5(a4) -80000f54: 23 02 b7 00 sb a1, 4(a4) -80000f58: a3 01 b7 00 sb a1, 3(a4) -80000f5c: 23 01 b7 00 sb a1, 2(a4) -80000f60: a3 00 b7 00 sb a1, 1(a4) -80000f64: 23 00 b7 00 sb a1, 0(a4) -80000f68: 67 80 00 00 ret -80000f6c: 93 f5 f5 0f andi a1, a1, 255 -80000f70: 93 96 85 00 slli a3, a1, 8 -80000f74: b3 e5 d5 00 or a1, a1, a3 -80000f78: 93 96 05 01 slli a3, a1, 16 -80000f7c: b3 e5 d5 00 or a1, a1, a3 -80000f80: 6f f0 df f6 j -148 -80000f84: 93 96 27 00 slli a3, a5, 2 -80000f88: 97 02 00 00 auipc t0, 0 -80000f8c: b3 86 56 00 add a3, a3, t0 -80000f90: 93 82 00 00 mv t0, ra -80000f94: e7 80 06 fa jalr -96(a3) -80000f98: 93 80 02 00 mv ra, t0 -80000f9c: 93 87 07 ff addi a5, a5, -16 -80000fa0: 33 07 f7 40 sub a4, a4, a5 -80000fa4: 33 06 f6 00 add a2, a2, a5 -80000fa8: e3 78 c3 f6 bgeu t1, a2, -144 -80000fac: 6f f0 df f3 j -196 +80000cc8 vx_perf_dump: +80000cc8: f3 27 50 cc csrr a5, 3269 +80000ccc: 37 07 ff 00 lui a4, 4080 +80000cd0: b3 87 e7 00 add a5, a5, a4 +80000cd4: 93 97 87 00 slli a5, a5, 8 +80000cd8: 73 27 00 b0 csrr a4, mcycle +80000cdc: 23 a0 e7 00 sw a4, 0(a5) +80000ce0: 73 27 10 b0 csrr a4, 2817 +80000ce4: 23 a2 e7 00 sw a4, 4(a5) +80000ce8: 73 27 20 b0 csrr a4, minstret +80000cec: 23 a4 e7 00 sw a4, 8(a5) +80000cf0: 73 27 30 b0 csrr a4, mhpmcounter3 +80000cf4: 23 a6 e7 00 sw a4, 12(a5) +80000cf8: 73 27 40 b0 csrr a4, mhpmcounter4 +80000cfc: 23 a8 e7 00 sw a4, 16(a5) +80000d00: 73 27 50 b0 csrr a4, mhpmcounter5 +80000d04: 23 aa e7 00 sw a4, 20(a5) +80000d08: 73 27 60 b0 csrr a4, mhpmcounter6 +80000d0c: 23 ac e7 00 sw a4, 24(a5) +80000d10: 73 27 70 b0 csrr a4, mhpmcounter7 +80000d14: 23 ae e7 00 sw a4, 28(a5) +80000d18: 73 27 80 b0 csrr a4, mhpmcounter8 +80000d1c: 23 a0 e7 02 sw a4, 32(a5) +80000d20: 73 27 90 b0 csrr a4, mhpmcounter9 +80000d24: 23 a2 e7 02 sw a4, 36(a5) +80000d28: 73 27 a0 b0 csrr a4, mhpmcounter10 +80000d2c: 23 a4 e7 02 sw a4, 40(a5) +80000d30: 73 27 b0 b0 csrr a4, mhpmcounter11 +80000d34: 23 a6 e7 02 sw a4, 44(a5) +80000d38: 73 27 c0 b0 csrr a4, mhpmcounter12 +80000d3c: 23 a8 e7 02 sw a4, 48(a5) +80000d40: 73 27 d0 b0 csrr a4, mhpmcounter13 +80000d44: 23 aa e7 02 sw a4, 52(a5) +80000d48: 73 27 e0 b0 csrr a4, mhpmcounter14 +80000d4c: 23 ac e7 02 sw a4, 56(a5) +80000d50: 73 27 f0 b0 csrr a4, mhpmcounter15 +80000d54: 23 ae e7 02 sw a4, 60(a5) +80000d58: 73 27 00 b1 csrr a4, mhpmcounter16 +80000d5c: 23 a0 e7 04 sw a4, 64(a5) +80000d60: 73 27 10 b1 csrr a4, mhpmcounter17 +80000d64: 23 a2 e7 04 sw a4, 68(a5) +80000d68: 73 27 20 b1 csrr a4, mhpmcounter18 +80000d6c: 23 a4 e7 04 sw a4, 72(a5) +80000d70: 73 27 30 b1 csrr a4, mhpmcounter19 +80000d74: 23 a6 e7 04 sw a4, 76(a5) +80000d78: 73 27 40 b1 csrr a4, mhpmcounter20 +80000d7c: 23 a8 e7 04 sw a4, 80(a5) +80000d80: 73 27 50 b1 csrr a4, mhpmcounter21 +80000d84: 23 aa e7 04 sw a4, 84(a5) +80000d88: 73 27 60 b1 csrr a4, mhpmcounter22 +80000d8c: 23 ac e7 04 sw a4, 88(a5) +80000d90: 73 27 70 b1 csrr a4, mhpmcounter23 +80000d94: 23 ae e7 04 sw a4, 92(a5) +80000d98: 73 27 80 b1 csrr a4, mhpmcounter24 +80000d9c: 23 a0 e7 06 sw a4, 96(a5) +80000da0: 73 27 90 b1 csrr a4, mhpmcounter25 +80000da4: 23 a2 e7 06 sw a4, 100(a5) +80000da8: 73 27 a0 b1 csrr a4, mhpmcounter26 +80000dac: 23 a4 e7 06 sw a4, 104(a5) +80000db0: 73 27 b0 b1 csrr a4, mhpmcounter27 +80000db4: 23 a6 e7 06 sw a4, 108(a5) +80000db8: 73 27 c0 b1 csrr a4, mhpmcounter28 +80000dbc: 23 a8 e7 06 sw a4, 112(a5) +80000dc0: 73 27 d0 b1 csrr a4, mhpmcounter29 +80000dc4: 23 aa e7 06 sw a4, 116(a5) +80000dc8: 73 27 e0 b1 csrr a4, mhpmcounter30 +80000dcc: 23 ac e7 06 sw a4, 120(a5) +80000dd0: 73 27 f0 b1 csrr a4, mhpmcounter31 +80000dd4: 23 ae e7 06 sw a4, 124(a5) +80000dd8: 73 27 00 b8 csrr a4, mcycleh +80000ddc: 23 a0 e7 08 sw a4, 128(a5) +80000de0: 73 27 10 b8 csrr a4, 2945 +80000de4: 23 a2 e7 08 sw a4, 132(a5) +80000de8: 73 27 20 b8 csrr a4, minstreth +80000dec: 23 a4 e7 08 sw a4, 136(a5) +80000df0: 73 27 30 b8 csrr a4, mhpmcounter3h +80000df4: 23 a6 e7 08 sw a4, 140(a5) +80000df8: 73 27 40 b8 csrr a4, mhpmcounter4h +80000dfc: 23 a8 e7 08 sw a4, 144(a5) +80000e00: 73 27 50 b8 csrr a4, mhpmcounter5h +80000e04: 23 aa e7 08 sw a4, 148(a5) +80000e08: 73 27 60 b8 csrr a4, mhpmcounter6h +80000e0c: 23 ac e7 08 sw a4, 152(a5) +80000e10: 73 27 70 b8 csrr a4, mhpmcounter7h +80000e14: 23 ae e7 08 sw a4, 156(a5) +80000e18: 73 27 80 b8 csrr a4, mhpmcounter8h +80000e1c: 23 a0 e7 0a sw a4, 160(a5) +80000e20: 73 27 90 b8 csrr a4, mhpmcounter9h +80000e24: 23 a2 e7 0a sw a4, 164(a5) +80000e28: 73 27 a0 b8 csrr a4, mhpmcounter10h +80000e2c: 23 a4 e7 0a sw a4, 168(a5) +80000e30: 73 27 b0 b8 csrr a4, mhpmcounter11h +80000e34: 23 a6 e7 0a sw a4, 172(a5) +80000e38: 73 27 c0 b8 csrr a4, mhpmcounter12h +80000e3c: 23 a8 e7 0a sw a4, 176(a5) +80000e40: 73 27 d0 b8 csrr a4, mhpmcounter13h +80000e44: 23 aa e7 0a sw a4, 180(a5) +80000e48: 73 27 e0 b8 csrr a4, mhpmcounter14h +80000e4c: 23 ac e7 0a sw a4, 184(a5) +80000e50: 73 27 f0 b8 csrr a4, mhpmcounter15h +80000e54: 23 ae e7 0a sw a4, 188(a5) +80000e58: 73 27 00 b9 csrr a4, mhpmcounter16h +80000e5c: 23 a0 e7 0c sw a4, 192(a5) +80000e60: 73 27 10 b9 csrr a4, mhpmcounter17h +80000e64: 23 a2 e7 0c sw a4, 196(a5) +80000e68: 73 27 20 b9 csrr a4, mhpmcounter18h +80000e6c: 23 a4 e7 0c sw a4, 200(a5) +80000e70: 73 27 30 b9 csrr a4, mhpmcounter19h +80000e74: 23 a6 e7 0c sw a4, 204(a5) +80000e78: 73 27 40 b9 csrr a4, mhpmcounter20h +80000e7c: 23 a8 e7 0c sw a4, 208(a5) +80000e80: 73 27 50 b9 csrr a4, mhpmcounter21h +80000e84: 23 aa e7 0c sw a4, 212(a5) +80000e88: 73 27 60 b9 csrr a4, mhpmcounter22h +80000e8c: 23 ac e7 0c sw a4, 216(a5) +80000e90: 73 27 70 b9 csrr a4, mhpmcounter23h +80000e94: 23 ae e7 0c sw a4, 220(a5) +80000e98: 73 27 80 b9 csrr a4, mhpmcounter24h +80000e9c: 23 a0 e7 0e sw a4, 224(a5) +80000ea0: 73 27 90 b9 csrr a4, mhpmcounter25h +80000ea4: 23 a2 e7 0e sw a4, 228(a5) +80000ea8: 73 27 a0 b9 csrr a4, mhpmcounter26h +80000eac: 23 a4 e7 0e sw a4, 232(a5) +80000eb0: 73 27 b0 b9 csrr a4, mhpmcounter27h +80000eb4: 23 a6 e7 0e sw a4, 236(a5) +80000eb8: 73 27 c0 b9 csrr a4, mhpmcounter28h +80000ebc: 23 a8 e7 0e sw a4, 240(a5) +80000ec0: 73 27 d0 b9 csrr a4, mhpmcounter29h +80000ec4: 23 aa e7 0e sw a4, 244(a5) +80000ec8: 73 27 e0 b9 csrr a4, mhpmcounter30h +80000ecc: 23 ac e7 0e sw a4, 248(a5) +80000ed0: 73 27 f0 b9 csrr a4, mhpmcounter31h +80000ed4: 23 ae e7 0e sw a4, 252(a5) +80000ed8: 67 80 00 00 ret -80000fb0 __register_exitproc: -80000fb0: b7 27 00 80 lui a5, 524290 -80000fb4: 03 a7 07 5a lw a4, 1440(a5) -80000fb8: 83 27 87 14 lw a5, 328(a4) -80000fbc: 63 8c 07 04 beqz a5, 88 -80000fc0: 03 a7 47 00 lw a4, 4(a5) -80000fc4: 13 08 f0 01 addi a6, zero, 31 -80000fc8: 63 4e e8 06 blt a6, a4, 124 -80000fcc: 13 18 27 00 slli a6, a4, 2 -80000fd0: 63 06 05 02 beqz a0, 44 -80000fd4: 33 83 07 01 add t1, a5, a6 -80000fd8: 23 24 c3 08 sw a2, 136(t1) -80000fdc: 83 a8 87 18 lw a7, 392(a5) -80000fe0: 13 06 10 00 addi a2, zero, 1 -80000fe4: 33 16 e6 00 sll a2, a2, a4 -80000fe8: b3 e8 c8 00 or a7, a7, a2 -80000fec: 23 a4 17 19 sw a7, 392(a5) -80000ff0: 23 24 d3 10 sw a3, 264(t1) -80000ff4: 93 06 20 00 addi a3, zero, 2 -80000ff8: 63 04 d5 02 beq a0, a3, 40 -80000ffc: 13 07 17 00 addi a4, a4, 1 -80001000: 23 a2 e7 00 sw a4, 4(a5) -80001004: b3 87 07 01 add a5, a5, a6 -80001008: 23 a4 b7 00 sw a1, 8(a5) -8000100c: 13 05 00 00 mv a0, zero -80001010: 67 80 00 00 ret -80001014: 93 07 c7 14 addi a5, a4, 332 -80001018: 23 24 f7 14 sw a5, 328(a4) -8000101c: 6f f0 5f fa j -92 -80001020: 83 a6 c7 18 lw a3, 396(a5) -80001024: 13 07 17 00 addi a4, a4, 1 -80001028: 23 a2 e7 00 sw a4, 4(a5) -8000102c: 33 e6 c6 00 or a2, a3, a2 -80001030: 23 a6 c7 18 sw a2, 396(a5) -80001034: b3 87 07 01 add a5, a5, a6 -80001038: 23 a4 b7 00 sw a1, 8(a5) -8000103c: 13 05 00 00 mv a0, zero -80001040: 67 80 00 00 ret -80001044: 13 05 f0 ff addi a0, zero, -1 -80001048: 67 80 00 00 ret +80000edc atexit: +80000edc: 93 05 05 00 mv a1, a0 +80000ee0: 93 06 00 00 mv a3, zero +80000ee4: 13 06 00 00 mv a2, zero +80000ee8: 13 05 00 00 mv a0, zero +80000eec: 6f 00 40 11 j 276 -8000104c __call_exitprocs: -8000104c: 13 01 01 fd addi sp, sp, -48 -80001050: b7 27 00 80 lui a5, 524290 -80001054: 23 2c 41 01 sw s4, 24(sp) -80001058: 03 aa 07 5a lw s4, 1440(a5) -8000105c: 23 20 21 03 sw s2, 32(sp) -80001060: 23 26 11 02 sw ra, 44(sp) -80001064: 03 29 8a 14 lw s2, 328(s4) -80001068: 23 24 81 02 sw s0, 40(sp) -8000106c: 23 22 91 02 sw s1, 36(sp) -80001070: 23 2e 31 01 sw s3, 28(sp) -80001074: 23 2a 51 01 sw s5, 20(sp) -80001078: 23 28 61 01 sw s6, 16(sp) -8000107c: 23 26 71 01 sw s7, 12(sp) -80001080: 23 24 81 01 sw s8, 8(sp) -80001084: 63 00 09 04 beqz s2, 64 -80001088: 13 0b 05 00 mv s6, a0 -8000108c: 93 8b 05 00 mv s7, a1 -80001090: 93 0a 10 00 addi s5, zero, 1 -80001094: 93 09 f0 ff addi s3, zero, -1 -80001098: 83 24 49 00 lw s1, 4(s2) -8000109c: 13 84 f4 ff addi s0, s1, -1 -800010a0: 63 42 04 02 bltz s0, 36 -800010a4: 93 94 24 00 slli s1, s1, 2 -800010a8: b3 04 99 00 add s1, s2, s1 -800010ac: 63 84 0b 04 beqz s7, 72 -800010b0: 83 a7 44 10 lw a5, 260(s1) -800010b4: 63 80 77 05 beq a5, s7, 64 -800010b8: 13 04 f4 ff addi s0, s0, -1 -800010bc: 93 84 c4 ff addi s1, s1, -4 -800010c0: e3 16 34 ff bne s0, s3, -20 -800010c4: 83 20 c1 02 lw ra, 44(sp) -800010c8: 03 24 81 02 lw s0, 40(sp) -800010cc: 83 24 41 02 lw s1, 36(sp) -800010d0: 03 29 01 02 lw s2, 32(sp) -800010d4: 83 29 c1 01 lw s3, 28(sp) -800010d8: 03 2a 81 01 lw s4, 24(sp) -800010dc: 83 2a 41 01 lw s5, 20(sp) -800010e0: 03 2b 01 01 lw s6, 16(sp) -800010e4: 83 2b c1 00 lw s7, 12(sp) -800010e8: 03 2c 81 00 lw s8, 8(sp) -800010ec: 13 01 01 03 addi sp, sp, 48 -800010f0: 67 80 00 00 ret -800010f4: 83 27 49 00 lw a5, 4(s2) -800010f8: 83 a6 44 00 lw a3, 4(s1) -800010fc: 93 87 f7 ff addi a5, a5, -1 -80001100: 63 8e 87 04 beq a5, s0, 92 -80001104: 23 a2 04 00 sw zero, 4(s1) -80001108: e3 88 06 fa beqz a3, -80 -8000110c: 83 27 89 18 lw a5, 392(s2) -80001110: 33 97 8a 00 sll a4, s5, s0 -80001114: 03 2c 49 00 lw s8, 4(s2) -80001118: b3 77 f7 00 and a5, a4, a5 -8000111c: 63 92 07 02 bnez a5, 36 -80001120: e7 80 06 00 jalr a3 -80001124: 03 27 49 00 lw a4, 4(s2) -80001128: 83 27 8a 14 lw a5, 328(s4) -8000112c: 63 14 87 01 bne a4, s8, 8 -80001130: e3 04 f9 f8 beq s2, a5, -120 -80001134: e3 88 07 f8 beqz a5, -112 -80001138: 13 89 07 00 mv s2, a5 -8000113c: 6f f0 df f5 j -164 -80001140: 83 27 c9 18 lw a5, 396(s2) -80001144: 83 a5 44 08 lw a1, 132(s1) -80001148: 33 77 f7 00 and a4, a4, a5 -8000114c: 63 1c 07 00 bnez a4, 24 -80001150: 13 05 0b 00 mv a0, s6 -80001154: e7 80 06 00 jalr a3 -80001158: 6f f0 df fc j -52 -8000115c: 23 22 89 00 sw s0, 4(s2) -80001160: 6f f0 9f fa j -88 -80001164: 13 85 05 00 mv a0, a1 -80001168: e7 80 06 00 jalr a3 -8000116c: 6f f0 9f fb j -72 +80000ef0 exit: +80000ef0: 13 01 01 ff addi sp, sp, -16 +80000ef4: 93 05 00 00 mv a1, zero +80000ef8: 23 24 81 00 sw s0, 8(sp) +80000efc: 23 26 11 00 sw ra, 12(sp) +80000f00: 13 04 05 00 mv s0, a0 +80000f04: ef 00 80 19 jal 408 +80000f08: b7 27 00 80 lui a5, 524290 +80000f0c: 03 a5 07 5f lw a0, 1520(a5) +80000f10: 83 27 c5 03 lw a5, 60(a0) +80000f14: 63 84 07 00 beqz a5, 8 +80000f18: e7 80 07 00 jalr a5 +80000f1c: 13 05 04 00 mv a0, s0 +80000f20: ef f0 5f 8a jal -1884 + +80000f24 memset: +80000f24: 13 03 f0 00 addi t1, zero, 15 +80000f28: 13 07 05 00 mv a4, a0 +80000f2c: 63 7e c3 02 bgeu t1, a2, 60 +80000f30: 93 77 f7 00 andi a5, a4, 15 +80000f34: 63 90 07 0a bnez a5, 160 +80000f38: 63 92 05 08 bnez a1, 132 +80000f3c: 93 76 06 ff andi a3, a2, -16 +80000f40: 13 76 f6 00 andi a2, a2, 15 +80000f44: b3 86 e6 00 add a3, a3, a4 +80000f48: 23 20 b7 00 sw a1, 0(a4) +80000f4c: 23 22 b7 00 sw a1, 4(a4) +80000f50: 23 24 b7 00 sw a1, 8(a4) +80000f54: 23 26 b7 00 sw a1, 12(a4) +80000f58: 13 07 07 01 addi a4, a4, 16 +80000f5c: e3 66 d7 fe bltu a4, a3, -20 +80000f60: 63 14 06 00 bnez a2, 8 +80000f64: 67 80 00 00 ret +80000f68: b3 06 c3 40 sub a3, t1, a2 +80000f6c: 93 96 26 00 slli a3, a3, 2 +80000f70: 97 02 00 00 auipc t0, 0 +80000f74: b3 86 56 00 add a3, a3, t0 +80000f78: 67 80 c6 00 jr 12(a3) +80000f7c: 23 07 b7 00 sb a1, 14(a4) +80000f80: a3 06 b7 00 sb a1, 13(a4) +80000f84: 23 06 b7 00 sb a1, 12(a4) +80000f88: a3 05 b7 00 sb a1, 11(a4) +80000f8c: 23 05 b7 00 sb a1, 10(a4) +80000f90: a3 04 b7 00 sb a1, 9(a4) +80000f94: 23 04 b7 00 sb a1, 8(a4) +80000f98: a3 03 b7 00 sb a1, 7(a4) +80000f9c: 23 03 b7 00 sb a1, 6(a4) +80000fa0: a3 02 b7 00 sb a1, 5(a4) +80000fa4: 23 02 b7 00 sb a1, 4(a4) +80000fa8: a3 01 b7 00 sb a1, 3(a4) +80000fac: 23 01 b7 00 sb a1, 2(a4) +80000fb0: a3 00 b7 00 sb a1, 1(a4) +80000fb4: 23 00 b7 00 sb a1, 0(a4) +80000fb8: 67 80 00 00 ret +80000fbc: 93 f5 f5 0f andi a1, a1, 255 +80000fc0: 93 96 85 00 slli a3, a1, 8 +80000fc4: b3 e5 d5 00 or a1, a1, a3 +80000fc8: 93 96 05 01 slli a3, a1, 16 +80000fcc: b3 e5 d5 00 or a1, a1, a3 +80000fd0: 6f f0 df f6 j -148 +80000fd4: 93 96 27 00 slli a3, a5, 2 +80000fd8: 97 02 00 00 auipc t0, 0 +80000fdc: b3 86 56 00 add a3, a3, t0 +80000fe0: 93 82 00 00 mv t0, ra +80000fe4: e7 80 06 fa jalr -96(a3) +80000fe8: 93 80 02 00 mv ra, t0 +80000fec: 93 87 07 ff addi a5, a5, -16 +80000ff0: 33 07 f7 40 sub a4, a4, a5 +80000ff4: 33 06 f6 00 add a2, a2, a5 +80000ff8: e3 78 c3 f6 bgeu t1, a2, -144 +80000ffc: 6f f0 df f3 j -196 + +80001000 __register_exitproc: +80001000: b7 27 00 80 lui a5, 524290 +80001004: 03 a7 07 5f lw a4, 1520(a5) +80001008: 83 27 87 14 lw a5, 328(a4) +8000100c: 63 8c 07 04 beqz a5, 88 +80001010: 03 a7 47 00 lw a4, 4(a5) +80001014: 13 08 f0 01 addi a6, zero, 31 +80001018: 63 4e e8 06 blt a6, a4, 124 +8000101c: 13 18 27 00 slli a6, a4, 2 +80001020: 63 06 05 02 beqz a0, 44 +80001024: 33 83 07 01 add t1, a5, a6 +80001028: 23 24 c3 08 sw a2, 136(t1) +8000102c: 83 a8 87 18 lw a7, 392(a5) +80001030: 13 06 10 00 addi a2, zero, 1 +80001034: 33 16 e6 00 sll a2, a2, a4 +80001038: b3 e8 c8 00 or a7, a7, a2 +8000103c: 23 a4 17 19 sw a7, 392(a5) +80001040: 23 24 d3 10 sw a3, 264(t1) +80001044: 93 06 20 00 addi a3, zero, 2 +80001048: 63 04 d5 02 beq a0, a3, 40 +8000104c: 13 07 17 00 addi a4, a4, 1 +80001050: 23 a2 e7 00 sw a4, 4(a5) +80001054: b3 87 07 01 add a5, a5, a6 +80001058: 23 a4 b7 00 sw a1, 8(a5) +8000105c: 13 05 00 00 mv a0, zero +80001060: 67 80 00 00 ret +80001064: 93 07 c7 14 addi a5, a4, 332 +80001068: 23 24 f7 14 sw a5, 328(a4) +8000106c: 6f f0 5f fa j -92 +80001070: 83 a6 c7 18 lw a3, 396(a5) +80001074: 13 07 17 00 addi a4, a4, 1 +80001078: 23 a2 e7 00 sw a4, 4(a5) +8000107c: 33 e6 c6 00 or a2, a3, a2 +80001080: 23 a6 c7 18 sw a2, 396(a5) +80001084: b3 87 07 01 add a5, a5, a6 +80001088: 23 a4 b7 00 sw a1, 8(a5) +8000108c: 13 05 00 00 mv a0, zero +80001090: 67 80 00 00 ret +80001094: 13 05 f0 ff addi a0, zero, -1 +80001098: 67 80 00 00 ret + +8000109c __call_exitprocs: +8000109c: 13 01 01 fd addi sp, sp, -48 +800010a0: b7 27 00 80 lui a5, 524290 +800010a4: 23 2c 41 01 sw s4, 24(sp) +800010a8: 03 aa 07 5f lw s4, 1520(a5) +800010ac: 23 20 21 03 sw s2, 32(sp) +800010b0: 23 26 11 02 sw ra, 44(sp) +800010b4: 03 29 8a 14 lw s2, 328(s4) +800010b8: 23 24 81 02 sw s0, 40(sp) +800010bc: 23 22 91 02 sw s1, 36(sp) +800010c0: 23 2e 31 01 sw s3, 28(sp) +800010c4: 23 2a 51 01 sw s5, 20(sp) +800010c8: 23 28 61 01 sw s6, 16(sp) +800010cc: 23 26 71 01 sw s7, 12(sp) +800010d0: 23 24 81 01 sw s8, 8(sp) +800010d4: 63 00 09 04 beqz s2, 64 +800010d8: 13 0b 05 00 mv s6, a0 +800010dc: 93 8b 05 00 mv s7, a1 +800010e0: 93 0a 10 00 addi s5, zero, 1 +800010e4: 93 09 f0 ff addi s3, zero, -1 +800010e8: 83 24 49 00 lw s1, 4(s2) +800010ec: 13 84 f4 ff addi s0, s1, -1 +800010f0: 63 42 04 02 bltz s0, 36 +800010f4: 93 94 24 00 slli s1, s1, 2 +800010f8: b3 04 99 00 add s1, s2, s1 +800010fc: 63 84 0b 04 beqz s7, 72 +80001100: 83 a7 44 10 lw a5, 260(s1) +80001104: 63 80 77 05 beq a5, s7, 64 +80001108: 13 04 f4 ff addi s0, s0, -1 +8000110c: 93 84 c4 ff addi s1, s1, -4 +80001110: e3 16 34 ff bne s0, s3, -20 +80001114: 83 20 c1 02 lw ra, 44(sp) +80001118: 03 24 81 02 lw s0, 40(sp) +8000111c: 83 24 41 02 lw s1, 36(sp) +80001120: 03 29 01 02 lw s2, 32(sp) +80001124: 83 29 c1 01 lw s3, 28(sp) +80001128: 03 2a 81 01 lw s4, 24(sp) +8000112c: 83 2a 41 01 lw s5, 20(sp) +80001130: 03 2b 01 01 lw s6, 16(sp) +80001134: 83 2b c1 00 lw s7, 12(sp) +80001138: 03 2c 81 00 lw s8, 8(sp) +8000113c: 13 01 01 03 addi sp, sp, 48 +80001140: 67 80 00 00 ret +80001144: 83 27 49 00 lw a5, 4(s2) +80001148: 83 a6 44 00 lw a3, 4(s1) +8000114c: 93 87 f7 ff addi a5, a5, -1 +80001150: 63 8e 87 04 beq a5, s0, 92 +80001154: 23 a2 04 00 sw zero, 4(s1) +80001158: e3 88 06 fa beqz a3, -80 +8000115c: 83 27 89 18 lw a5, 392(s2) +80001160: 33 97 8a 00 sll a4, s5, s0 +80001164: 03 2c 49 00 lw s8, 4(s2) +80001168: b3 77 f7 00 and a5, a4, a5 +8000116c: 63 92 07 02 bnez a5, 36 +80001170: e7 80 06 00 jalr a3 +80001174: 03 27 49 00 lw a4, 4(s2) +80001178: 83 27 8a 14 lw a5, 328(s4) +8000117c: 63 14 87 01 bne a4, s8, 8 +80001180: e3 04 f9 f8 beq s2, a5, -120 +80001184: e3 88 07 f8 beqz a5, -112 +80001188: 13 89 07 00 mv s2, a5 +8000118c: 6f f0 df f5 j -164 +80001190: 83 27 c9 18 lw a5, 396(s2) +80001194: 83 a5 44 08 lw a1, 132(s1) +80001198: 33 77 f7 00 and a4, a4, a5 +8000119c: 63 1c 07 00 bnez a4, 24 +800011a0: 13 05 0b 00 mv a0, s6 +800011a4: e7 80 06 00 jalr a3 +800011a8: 6f f0 df fc j -52 +800011ac: 23 22 89 00 sw s0, 4(s2) +800011b0: 6f f0 9f fa j -88 +800011b4: 13 85 05 00 mv a0, a1 +800011b8: e7 80 06 00 jalr a3 +800011bc: 6f f0 9f fb j -72 Disassembly of section .init_array: -80002170 __preinit_array_start: -80002170: 50 00 -80002172: 00 80 +800021c0 __preinit_array_start: +800021c0: 50 00 +800021c2: 00 80 Disassembly of section .data: -80002178 impure_data: -80002178: 00 00 -8000217a: 00 00 -8000217c: 64 24 -8000217e: 00 80 -80002180: cc 24 -80002182: 00 80 -80002184: 34 25 -80002186: 00 80 +800021c8 impure_data: +800021c8: 00 00 +800021ca: 00 00 +800021cc: b4 24 +800021ce: 00 80 +800021d0: 1c 25 +800021d2: 00 80 +800021d4: 84 25 +800021d6: 00 80 ... -80002220: 01 00 -80002222: 00 00 -80002224: 00 00 -80002226: 00 00 -80002228: 0e 33 -8000222a: cd ab -8000222c: 34 12 -8000222e: 6d e6 -80002230: ec de -80002232: 05 00 -80002234: 0b 00 00 00 +80002270: 01 00 +80002272: 00 00 +80002274: 00 00 +80002276: 00 00 +80002278: 0e 33 +8000227a: cd ab +8000227c: 34 12 +8000227e: 6d e6 +80002280: ec de +80002282: 05 00 +80002284: 0b 00 00 00 ... Disassembly of section .sdata: -800025a0 _global_impure_ptr: -800025a0: 78 21 -800025a2: 00 80 +800025f0 _global_impure_ptr: +800025f0: c8 21 +800025f2: 00 80 Disassembly of section .bss: -800025a4 g_wspawn_args: +800025f4 g_wspawn_args: ... Disassembly of section .comment: @@ -1230,25 +1256,25 @@ Disassembly of section .comment: 36: 6a 65 38: 63 74 2e 67 bgeu t3, s2, 1640 3c: 69 74 - 3e: 20 65 - 40: 66 33 - 42: 32 63 - 44: 36 31 - 46: 31 61 - 48: 61 32 - 4a: 31 34 - 4c: 64 65 - 4e: 61 38 - 50: 35 35 - 52: 33 36 34 65 - 56: 66 64 - 58: 37 62 61 34 lui tp, 214550 - 5c: 35 31 - 5e: 65 63 - 60: 35 65 - 62: 63 33 66 37 - 66: 34 29 - 68: 00 47 + 3e: 20 32 + 40: 61 32 + 42: 33 65 66 61 + 46: 63 33 35 32 + 4a: 66 39 + 4c: 31 39 + 4e: 65 62 + 50: 64 31 + 52: 65 63 + 54: 31 62 + 56: 65 34 + 58: 35 31 + 5a: 34 36 + 5c: 64 36 + 5e: 61 39 + 60: 66 61 + 62: 32 31 + 64: 62 35 + 66: 33 29 00 47 6a: 43 43 3a 20 fmadd.s ft6, fs4, ft3, ft4, rmm 6e: 28 47 70: 4e 55 @@ -1295,28 +1321,28 @@ Disassembly of section .symtab: 2c: 03 00 02 00 lb zero, 0(tp) 30: 00 00 32: 00 00 - 34: 70 21 + 34: c0 21 36: 00 80 38: 00 00 3a: 00 00 3c: 03 00 03 00 lb zero, 0(t1) 40: 00 00 42: 00 00 - 44: 78 21 + 44: c8 21 46: 00 80 48: 00 00 4a: 00 00 4c: 03 00 04 00 lb zero, 0(s0) 50: 00 00 52: 00 00 - 54: a0 25 + 54: f0 25 56: 00 80 58: 00 00 5a: 00 00 5c: 03 00 05 00 lb zero, 0(a0) 60: 00 00 62: 00 00 - 64: a4 25 + 64: f4 25 66: 00 80 68: 00 00 6a: 00 00 @@ -1332,343 +1358,360 @@ Disassembly of section .symtab: 9e: f1 ff a0: 0e 00 a2: 00 00 - a4: 08 08 + a4: d0 07 a6: 00 80 a8: 00 00 aa: 00 00 ac: 00 00 ae: 02 00 - b0: 15 00 - ... + b0: 1e 00 + b2: 00 00 + b4: 0c 08 + b6: 00 80 + b8: 00 00 ba: 00 00 - bc: 04 00 - be: f1 ff + bc: 00 00 + be: 02 00 c0: 25 00 - c2: 00 00 - c4: 50 00 - c6: 00 80 - c8: 18 00 - ca: 00 00 - cc: 02 00 - ce: 02 00 - d0: 33 00 00 00 add zero, zero, zero ... - dc: 04 00 - de: f1 ff - e0: 57 00 00 00 + ca: 00 00 + cc: 04 00 + ce: f1 ff + d0: 35 00 + d2: 00 00 + d4: 50 00 + d6: 00 80 + d8: 18 00 + da: 00 00 + dc: 02 00 + de: 02 00 + e0: 43 00 00 00 fmadd.s ft0, ft0, ft0, ft0, rne ... ec: 04 00 ee: f1 ff - f0: 63 00 00 00 beqz zero, 0 + f0: 67 00 00 00 jr zero ... fc: 04 00 fe: f1 ff - 100: 6e 00 - 102: 00 00 - 104: 0c 08 - 106: 00 80 - 108: 48 01 - 10a: 00 00 - 10c: 02 00 - 10e: 02 00 - 110: 84 00 + 100: 73 00 00 00 ecall + ... + 10c: 04 00 + 10e: f1 ff + 110: 81 00 ... 11a: 00 00 11c: 04 00 11e: f1 ff - 120: 9e 00 - ... + 120: 8c 00 + 122: 00 00 + 124: 08 09 + 126: 00 80 + 128: 3c 01 12a: 00 00 - 12c: 04 00 - 12e: f1 ff - 130: a0 00 - ... + 12c: 02 00 + 12e: 02 00 + 130: a2 00 + 132: 00 00 + 134: 44 0a + 136: 00 80 + 138: a4 00 13a: 00 00 - 13c: 04 00 - 13e: f1 ff - 140: 8e 00 - ... + 13c: 02 00 + 13e: 02 00 + 140: b8 00 + 142: 00 00 + 144: e8 0a + 146: 00 80 + 148: 2c 00 14a: 00 00 - 14c: 04 00 - 14e: f1 ff - 150: 95 00 + 14c: 02 00 + 14e: 02 00 + 150: cc 00 ... 15a: 00 00 15c: 04 00 15e: f1 ff - 160: 9c 00 + 160: d8 00 ... 16a: 00 00 16c: 04 00 16e: f1 ff - 170: a7 00 00 00 + 170: da 00 ... + 17a: 00 00 17c: 04 00 17e: f1 ff - 180: b0 00 - 182: 00 00 - 184: 78 21 - 186: 00 80 - 188: 28 04 - 18a: 00 00 - 18c: 01 00 - 18e: 04 00 + 180: d6 00 ... + 18a: 00 00 + 18c: 04 00 + 18e: f1 ff + 190: e1 00 + ... + 19a: 00 00 19c: 04 00 19e: f1 ff - 1a0: bc 00 + 1a0: ea 00 1a2: 00 00 - 1a4: 74 21 + 1a4: c8 21 1a6: 00 80 - 1a8: 00 00 + 1a8: 28 04 1aa: 00 00 - 1ac: 00 00 - 1ae: 03 00 cd 00 lb zero, 12(s10) - 1b2: 00 00 - 1b4: 74 21 - 1b6: 00 80 - 1b8: 00 00 - 1ba: 00 00 - 1bc: 00 00 - 1be: 03 00 e0 00 lb zero, 14(zero) + 1ac: 01 00 + 1ae: 04 00 + ... + 1bc: 04 00 + 1be: f1 ff + 1c0: f6 00 1c2: 00 00 - 1c4: 74 21 + 1c4: c4 21 1c6: 00 80 1c8: 00 00 1ca: 00 00 1cc: 00 00 - 1ce: 03 00 f1 00 lb zero, 15(sp) + 1ce: 03 00 07 01 lb zero, 16(a4) 1d2: 00 00 - 1d4: 70 21 + 1d4: c4 21 1d6: 00 80 1d8: 00 00 1da: 00 00 1dc: 00 00 - 1de: 03 00 05 01 lb zero, 16(a0) + 1de: 03 00 1a 01 lb zero, 17(s4) 1e2: 00 00 - 1e4: 70 21 + 1e4: c4 21 1e6: 00 80 1e8: 00 00 1ea: 00 00 1ec: 00 00 - 1ee: 03 00 18 01 lb zero, 17(a6) + 1ee: 03 00 2b 01 lb zero, 18(s6) 1f2: 00 00 - 1f4: 70 21 + 1f4: c0 21 1f6: 00 80 1f8: 00 00 1fa: 00 00 1fc: 00 00 - 1fe: 03 00 2e 01 lb zero, 18(t3) - ... + 1fe: 03 00 3f 01 lb zero, 19(t5) + 202: 00 00 + 204: c0 21 + 206: 00 80 + 208: 00 00 20a: 00 00 - 20c: 10 00 - 20e: f1 ff - 210: 3c 01 + 20c: 00 00 + 20e: 03 00 52 01 lb zero, 21(tp) 212: 00 00 - 214: 00 04 - 216: 00 00 + 214: c0 21 + 216: 00 80 218: 00 00 21a: 00 00 - 21c: 10 00 - 21e: f1 ff - 220: 49 01 - 222: 00 00 - 224: a4 25 - 226: 00 80 - 228: 80 00 + 21c: 00 00 + 21e: 03 00 68 01 lb zero, 22(a6) + ... 22a: 00 00 - 22c: 11 00 - 22e: 06 00 - 230: 57 01 00 00 - 234: a0 25 - 236: 00 80 + 22c: 10 00 + 22e: f1 ff + 230: 76 01 + 232: 00 00 + 234: 00 04 + 236: 00 00 238: 00 00 23a: 00 00 23c: 10 00 - 23e: 05 00 - 240: 67 01 00 00 jalr sp, zero - 244: 78 29 + 23e: f1 ff + 240: 83 01 00 00 lb gp, 0(zero) + 244: f4 25 246: 00 80 - 248: 00 00 + 248: 80 00 24a: 00 00 - 24c: 10 00 - 24e: f1 ff - 250: 78 01 + 24c: 11 00 + 24e: 06 00 + 250: 91 01 252: 00 00 - 254: a0 25 + 254: f0 25 256: 00 80 - 258: 04 00 + 258: 00 00 25a: 00 00 - 25c: 11 00 + 25c: 10 00 25e: 05 00 - 260: 8b 01 00 00 - 264: 38 0e + 260: a1 01 + 262: 00 00 + 264: c8 29 266: 00 80 - 268: 9c 00 + 268: 00 00 26a: 00 00 - 26c: 12 00 - 26e: 02 00 - 270: 9d 01 + 26c: 10 00 + 26e: f1 ff + 270: b2 01 272: 00 00 - 274: dc 0d + 274: f0 25 276: 00 80 - 278: 5c 00 + 278: 04 00 27a: 00 00 - 27c: 12 00 - 27e: 02 00 - 280: af 01 00 00 - 284: 00 00 - 286: 00 ff - 288: 00 00 + 27c: 11 00 + 27e: 05 00 + 280: c5 01 + 282: 00 00 + 284: 10 08 + 286: 00 80 + 288: 9c 00 28a: 00 00 - 28c: 10 00 - 28e: f1 ff - 290: bb 01 00 00 - 294: d0 07 + 28c: 12 00 + 28e: 02 00 + 290: d7 01 00 00 + 294: ac 08 296: 00 80 - 298: 00 00 + 298: 5c 00 29a: 00 00 29c: 12 00 29e: 02 00 - 2a0: c5 01 + 2a0: e9 01 2a2: 00 00 - 2a4: 4c 10 + 2a4: dc 07 2a6: 00 80 - 2a8: 24 01 + 2a8: 00 00 2aa: 00 00 2ac: 12 00 2ae: 02 00 - 2b0: 10 02 - 2b2: 00 00 - 2b4: 00 00 + 2b0: f3 01 00 00 + 2b4: 9c 10 2b6: 00 80 - 2b8: 50 00 + 2b8: 24 01 2ba: 00 00 2bc: 12 00 - 2be: 01 00 - 2c0: d6 01 + 2be: 02 00 + 2c0: 3e 02 2c2: 00 00 - 2c4: b0 0f + 2c4: 00 00 2c6: 00 80 - 2c8: 9c 00 + 2c8: 50 00 2ca: 00 00 2cc: 12 00 - 2ce: 02 00 - 2d0: ea 01 + 2ce: 01 00 + 2d0: 04 02 2d2: 00 00 - 2d4: 98 00 + 2d4: 00 10 2d6: 00 80 - 2d8: 34 02 + 2d8: 9c 00 2da: 00 00 2dc: 12 00 2de: 02 00 - 2e0: ff 01 00 00 - 2e4: 24 26 + 2e0: 18 02 + 2e2: 00 00 + 2e4: 98 00 2e6: 00 80 - 2e8: 00 00 + 2e8: 34 02 2ea: 00 00 - 2ec: 10 00 - 2ee: 06 00 - 2f0: 0b 02 00 00 - 2f4: a4 25 + 2ec: 12 00 + 2ee: 02 00 + 2f0: 2d 02 + 2f2: 00 00 + 2f4: 74 26 2f6: 00 80 2f8: 00 00 2fa: 00 00 2fc: 10 00 2fe: 06 00 - 300: 17 02 00 00 auipc tp, 0 - 304: d4 0e + 300: 39 02 + 302: 00 00 + 304: f4 25 306: 00 80 - 308: dc 00 + 308: 00 00 30a: 00 00 - 30c: 12 00 - 30e: 02 00 - 310: 1e 02 + 30c: 10 00 + 30e: 06 00 + 310: 45 02 312: 00 00 - 314: 68 00 + 314: 24 0f 316: 00 80 - 318: 30 00 + 318: dc 00 31a: 00 00 31c: 12 00 31e: 02 00 - 320: 23 02 00 00 sb zero, 4(zero) - 324: cc 02 + 320: 4c 02 + 322: 00 00 + 324: 68 00 326: 00 80 - 328: 80 02 + 328: 30 00 32a: 00 00 32c: 12 00 32e: 02 00 - 330: 42 02 + 330: 51 02 332: 00 00 - 334: 94 0d + 334: cc 02 336: 00 80 - 338: 14 00 + 338: 80 02 33a: 00 00 33c: 12 00 33e: 02 00 - 340: 49 02 + 340: 70 02 342: 00 00 - 344: 78 21 + 344: dc 0e 346: 00 80 - 348: 00 00 + 348: 14 00 34a: 00 00 - 34c: 10 00 - 34e: 04 00 - 350: 58 02 - 352: 00 00 - 354: a4 25 + 34c: 12 00 + 34e: 02 00 + 350: 77 02 00 00 + 354: c8 21 356: 00 80 358: 00 00 35a: 00 00 35c: 10 00 - 35e: 05 00 - 360: c8 00 + 35e: 04 00 + 360: 86 02 362: 00 00 - 364: 24 26 + 364: f4 25 366: 00 80 368: 00 00 36a: 00 00 36c: 10 00 - 36e: 06 00 - 370: 6d 02 + 36e: 05 00 + 370: 02 01 372: 00 00 - 374: a8 0d + 374: 74 26 376: 00 80 - 378: 34 00 + 378: 00 00 37a: 00 00 - 37c: 12 00 - 37e: 02 00 - 380: 5f 02 00 00 - 384: 80 0b + 37c: 10 00 + 37e: 06 00 + 380: 9b 02 00 00 + 384: f0 0e 386: 00 80 - 388: 14 02 + 388: 34 00 38a: 00 00 38c: 12 00 38e: 02 00 - 390: 6c 02 + 390: 8d 02 392: 00 00 - 394: c4 07 + 394: c8 0c 396: 00 80 - 398: 00 00 + 398: 14 02 39a: 00 00 39c: 12 00 39e: 02 00 - 3a0: 72 02 + 3a0: 9a 02 3a2: 00 00 - 3a4: 4c 05 + 3a4: c4 07 3a6: 00 80 - 3a8: 78 02 + 3a8: 00 00 3aa: 00 00 3ac: 12 00 3ae: 02 00 - 3b0: 96 02 + 3b0: a0 02 3b2: 00 00 - 3b4: 54 09 + 3b4: 4c 05 3b6: 00 80 - 3b8: 2c 02 + 3b8: 78 02 3ba: 00 00 3bc: 12 00 3be: 02 00 + 3c0: c4 02 + 3c2: 00 00 + 3c4: 14 0b + 3c6: 00 80 + 3c8: b4 01 + 3ca: 00 00 + 3cc: 12 00 + 3ce: 02 00 Disassembly of section .strtab: @@ -1678,255 +1721,271 @@ Disassembly of section .strtab: 4: 73 74 61 72 csrrci s0, 1830, 2 8: 74 2e a: 53 2e 6f 00 fadd.s ft8, ft10, ft6, rdn - e: 52 45 - 10: 54 55 - 12: 52 4e - 14: 00 5f - 16: 5f 63 61 6c - 1a: 6c 5f - 1c: 61 74 - 1e: 65 78 - 20: 69 74 - 22: 2e 63 - 24: 00 72 - 26: 65 67 - 28: 69 73 - 2a: 74 65 - 2c: 72 5f - 2e: 66 69 - 30: 6e 69 - 32: 00 70 - 34: 6f 63 6c 5f jal t1, 812534 - 38: 76 6f - 3a: 72 74 - 3c: 65 78 - 3e: 5f 6b 65 72 - 42: 6e 65 - 44: 6c 2d - 46: 30 37 - 48: 2d 33 - 4a: 36 2d - 4c: 31 64 - 4e: 2d 66 - 50: 32 2d - 52: 66 65 - 54: 2e 63 - 56: 00 70 - 58: 61 72 - 5a: 61 6c - 5c: 6c 65 - 5e: 6c 5f - 60: 62 63 - 62: 00 76 - 64: 78 5f - 66: 73 70 61 77 csrci 1910, 2 - 6a: 6e 2e - 6c: 63 00 73 70 beq t1, t2, 1792 - 70: 61 77 - 72: 6e 5f - 74: 6b 65 72 6e - 78: 65 6c - 7a: 5f 63 61 6c - 7e: 6c 62 - 80: 61 63 - 82: 6b 00 76 78 - 86: 5f 70 65 72 - 8a: 66 2e - 8c: 63 00 66 69 beq a2, s6, 1664 - 90: 6e 69 - 92: 2e 63 - 94: 00 69 - 96: 6e 69 - 98: 74 2e - 9a: 63 00 5f 5f beq t5, s5, 1504 - 9e: 61 74 - a0: 65 78 - a2: 69 74 - a4: 2e 63 - a6: 00 69 - a8: 6d 70 - aa: 75 72 - ac: 65 2e - ae: 63 00 69 6d beq s2, s6, 1728 - b2: 70 75 - b4: 72 65 - b6: 5f 64 61 74 - ba: 61 00 - bc: 5f 5f 66 69 - c0: 6e 69 - c2: 5f 61 72 72 - c6: 61 79 - c8: 5f 65 6e 64 - cc: 00 5f - ce: 5f 66 69 6e - d2: 69 5f - d4: 61 72 - d6: 72 61 - d8: 79 5f - da: 73 74 61 72 csrrci s0, 1830, 2 - de: 74 00 - e0: 5f 5f 69 6e - e4: 69 74 - e6: 5f 61 72 72 - ea: 61 79 - ec: 5f 65 6e 64 - f0: 00 5f - f2: 5f 70 72 65 - f6: 69 6e - f8: 69 74 - fa: 5f 61 72 72 - fe: 61 79 - 100: 5f 65 6e 64 - 104: 00 5f - 106: 5f 69 6e 69 - 10a: 74 5f - 10c: 61 72 - 10e: 72 61 - 110: 79 5f - 112: 73 74 61 72 csrrci s0, 1830, 2 - 116: 74 00 - 118: 5f 5f 70 72 - 11c: 65 69 - 11e: 6e 69 - 120: 74 5f - 122: 61 72 - 124: 72 61 - 126: 79 5f - 128: 73 74 61 72 csrrci s0, 1830, 2 - 12c: 74 00 - 12e: 5f 5f 73 74 - 132: 61 63 - 134: 6b 5f 75 73 - 138: 61 67 - 13a: 65 00 - 13c: 5f 5f 73 74 - 140: 61 63 - 142: 6b 5f 73 69 - 146: 7a 65 - 148: 00 67 - 14a: 5f 77 73 70 - 14e: 61 77 - 150: 6e 5f - 152: 61 72 - 154: 67 73 00 5f - 158: 5f 53 44 41 - 15c: 54 41 - 15e: 5f 42 45 47 - 162: 49 4e - 164: 5f 5f 00 5f - 168: 5f 67 6c 6f - 16c: 62 61 - 16e: 6c 5f - 170: 70 6f - 172: 69 6e - 174: 74 65 - 176: 72 00 - 178: 5f 67 6c 6f - 17c: 62 61 - 17e: 6c 5f - 180: 69 6d - 182: 70 75 - 184: 72 65 - 186: 5f 70 74 72 - 18a: 00 5f - 18c: 5f 6c 69 62 - 190: 63 5f 69 6e bge s2, t1, 1790 - 194: 69 74 - 196: 5f 61 72 72 - 19a: 61 79 - 19c: 00 5f - 19e: 5f 6c 69 62 - 1a2: 63 5f 66 69 bge a2, s6, 1694 - 1a6: 6e 69 - 1a8: 5f 61 72 72 - 1ac: 61 79 - 1ae: 00 5f - 1b0: 5f 73 74 61 - 1b4: 63 6b 5f 74 bltu t5, t0, 1878 - 1b8: 6f 70 00 76 j 30560 - 1bc: 78 5f - 1be: 73 65 74 5f csrrsi a0, 1527, 8 - 1c2: 73 70 00 5f csrci 1520, 0 - 1c6: 5f 63 61 6c - 1ca: 6c 5f - 1cc: 65 78 + e: 6c 61 + 10: 62 65 + 12: 6c 5f + 14: 65 78 + 16: 69 74 + 18: 5f 6e 65 78 + 1c: 74 00 + 1e: 52 45 + 20: 54 55 + 22: 52 4e + 24: 00 5f + 26: 5f 63 61 6c + 2a: 6c 5f + 2c: 61 74 + 2e: 65 78 + 30: 69 74 + 32: 2e 63 + 34: 00 72 + 36: 65 67 + 38: 69 73 + 3a: 74 65 + 3c: 72 5f + 3e: 66 69 + 40: 6e 69 + 42: 00 70 + 44: 6f 63 6c 5f jal t1, 812534 + 48: 76 6f + 4a: 72 74 + 4c: 65 78 + 4e: 5f 6b 65 72 + 52: 6e 65 + 54: 6c 2d + 56: 34 38 + 58: 2d 31 + 5a: 37 2d 66 33 lui s10, 210530 + 5e: 2d 63 + 60: 34 2d + 62: 65 32 + 64: 2e 63 + 66: 00 70 + 68: 61 72 + 6a: 61 6c + 6c: 6c 65 + 6e: 6c 5f + 70: 62 63 + 72: 00 76 + 74: 78 5f + 76: 73 79 73 63 csrrci s2, 1591, 6 + 7a: 61 6c + 7c: 6c 73 + 7e: 2e 63 + 80: 00 76 + 82: 78 5f + 84: 73 70 61 77 csrci 1910, 2 + 88: 6e 2e + 8a: 63 00 73 70 beq t1, t2, 1792 + 8e: 61 77 + 90: 6e 5f + 92: 6b 65 72 6e + 96: 65 6c + 98: 5f 61 6c 6c + 9c: 5f 73 74 75 + a0: 62 00 + a2: 73 70 61 77 csrci 1910, 2 + a6: 6e 5f + a8: 6b 65 72 6e + ac: 65 6c + ae: 5f 72 65 6d + b2: 5f 73 74 75 + b6: 62 00 + b8: 73 70 61 77 csrci 1910, 2 + bc: 6e 5f + be: 6b 65 72 6e + c2: 65 6c + c4: 5f 61 6c 6c + c8: 5f 63 62 00 + cc: 76 78 + ce: 5f 70 65 72 + d2: 66 2e + d4: 63 00 5f 5f beq t5, s5, 1504 + d8: 61 74 + da: 65 78 + dc: 69 74 + de: 2e 63 + e0: 00 69 + e2: 6d 70 + e4: 75 72 + e6: 65 2e + e8: 63 00 69 6d beq s2, s6, 1728 + ec: 70 75 + ee: 72 65 + f0: 5f 64 61 74 + f4: 61 00 + f6: 5f 5f 66 69 + fa: 6e 69 + fc: 5f 61 72 72 + 100: 61 79 + 102: 5f 65 6e 64 + 106: 00 5f + 108: 5f 66 69 6e + 10c: 69 5f + 10e: 61 72 + 110: 72 61 + 112: 79 5f + 114: 73 74 61 72 csrrci s0, 1830, 2 + 118: 74 00 + 11a: 5f 5f 69 6e + 11e: 69 74 + 120: 5f 61 72 72 + 124: 61 79 + 126: 5f 65 6e 64 + 12a: 00 5f + 12c: 5f 70 72 65 + 130: 69 6e + 132: 69 74 + 134: 5f 61 72 72 + 138: 61 79 + 13a: 5f 65 6e 64 + 13e: 00 5f + 140: 5f 69 6e 69 + 144: 74 5f + 146: 61 72 + 148: 72 61 + 14a: 79 5f + 14c: 73 74 61 72 csrrci s0, 1830, 2 + 150: 74 00 + 152: 5f 5f 70 72 + 156: 65 69 + 158: 6e 69 + 15a: 74 5f + 15c: 61 72 + 15e: 72 61 + 160: 79 5f + 162: 73 74 61 72 csrrci s0, 1830, 2 + 166: 74 00 + 168: 5f 5f 73 74 + 16c: 61 63 + 16e: 6b 5f 75 73 + 172: 61 67 + 174: 65 00 + 176: 5f 5f 73 74 + 17a: 61 63 + 17c: 6b 5f 73 69 + 180: 7a 65 + 182: 00 67 + 184: 5f 77 73 70 + 188: 61 77 + 18a: 6e 5f + 18c: 61 72 + 18e: 67 73 00 5f + 192: 5f 53 44 41 + 196: 54 41 + 198: 5f 42 45 47 + 19c: 49 4e + 19e: 5f 5f 00 5f + 1a2: 5f 67 6c 6f + 1a6: 62 61 + 1a8: 6c 5f + 1aa: 70 6f + 1ac: 69 6e + 1ae: 74 65 + 1b0: 72 00 + 1b2: 5f 67 6c 6f + 1b6: 62 61 + 1b8: 6c 5f + 1ba: 69 6d + 1bc: 70 75 + 1be: 72 65 + 1c0: 5f 70 74 72 + 1c4: 00 5f + 1c6: 5f 6c 69 62 + 1ca: 63 5f 69 6e bge s2, t1, 1790 1ce: 69 74 - 1d0: 70 72 - 1d2: 6f 63 73 00 jal t1, 223238 - 1d6: 5f 5f 72 65 - 1da: 67 69 73 74 - 1de: 65 72 - 1e0: 5f 65 78 69 - 1e4: 74 70 - 1e6: 72 6f - 1e8: 63 00 5f 70 beq t5, t0, 1792 - 1ec: 6f 63 6c 5f jal t1, 812534 - 1f0: 6b 65 72 6e - 1f4: 65 6c - 1f6: 5f 73 66 69 - 1fa: 6c 74 - 1fc: 65 72 - 1fe: 00 5f - 200: 5f 42 53 53 - 204: 5f 45 4e 44 - 208: 5f 5f 00 5f - 20c: 5f 62 73 73 - 210: 5f 73 74 61 - 214: 72 74 - 216: 00 6d - 218: 65 6d - 21a: 73 65 74 00 csrrsi a0, 7, 8 - 21e: 6d 61 - 220: 69 6e - 222: 00 5f - 224: 70 6f - 226: 63 6c 5f 6b bltu t5, s5, 1720 + 1d0: 5f 61 72 72 + 1d4: 61 79 + 1d6: 00 5f + 1d8: 5f 6c 69 62 + 1dc: 63 5f 66 69 bge a2, s6, 1694 + 1e0: 6e 69 + 1e2: 5f 61 72 72 + 1e6: 61 79 + 1e8: 00 76 + 1ea: 78 5f + 1ec: 73 65 74 5f csrrsi a0, 1527, 8 + 1f0: 73 70 00 5f csrci 1520, 0 + 1f4: 5f 63 61 6c + 1f8: 6c 5f + 1fa: 65 78 + 1fc: 69 74 + 1fe: 70 72 + 200: 6f 63 73 00 jal t1, 223238 + 204: 5f 5f 72 65 + 208: 67 69 73 74 + 20c: 65 72 + 20e: 5f 65 78 69 + 212: 74 70 + 214: 72 6f + 216: 63 00 5f 70 beq t5, t0, 1792 + 21a: 6f 63 6c 5f jal t1, 812534 + 21e: 6b 65 72 6e + 222: 65 6c + 224: 5f 73 66 69 + 228: 6c 74 22a: 65 72 - 22c: 6e 65 - 22e: 6c 5f - 230: 73 66 69 6c csrrsi a2, 1734, 18 - 234: 74 65 - 236: 72 5f - 238: 77 6f 72 6b - 23c: 67 72 6f 75 - 240: 70 00 - 242: 61 74 - 244: 65 78 - 246: 69 74 - 248: 00 5f - 24a: 5f 44 41 54 - 24e: 41 5f - 250: 42 45 - 252: 47 49 4e 5f - 256: 5f 00 5f 65 - 25a: 64 61 - 25c: 74 61 - 25e: 00 76 - 260: 78 5f - 262: 70 65 - 264: 72 66 - 266: 5f 64 75 6d - 26a: 70 00 - 26c: 5f 65 78 69 - 270: 74 00 - 272: 5f 70 6f 63 - 276: 6c 5f - 278: 6b 65 72 6e - 27c: 65 6c - 27e: 5f 73 66 69 - 282: 6c 74 - 284: 65 72 - 286: 5f 77 6f 72 - 28a: 6b 67 72 6f - 28e: 75 70 - 290: 5f 66 61 73 - 294: 74 00 - 296: 76 78 - 298: 5f 73 70 61 - 29c: 77 6e 5f 6b - 2a0: 65 72 - 2a2: 6e 65 - 2a4: 6c 00 + 22c: 00 5f + 22e: 5f 42 53 53 + 232: 5f 45 4e 44 + 236: 5f 5f 00 5f + 23a: 5f 62 73 73 + 23e: 5f 73 74 61 + 242: 72 74 + 244: 00 6d + 246: 65 6d + 248: 73 65 74 00 csrrsi a0, 7, 8 + 24c: 6d 61 + 24e: 69 6e + 250: 00 5f + 252: 70 6f + 254: 63 6c 5f 6b bltu t5, s5, 1720 + 258: 65 72 + 25a: 6e 65 + 25c: 6c 5f + 25e: 73 66 69 6c csrrsi a2, 1734, 18 + 262: 74 65 + 264: 72 5f + 266: 77 6f 72 6b + 26a: 67 72 6f 75 + 26e: 70 00 + 270: 61 74 + 272: 65 78 + 274: 69 74 + 276: 00 5f + 278: 5f 44 41 54 + 27c: 41 5f + 27e: 42 45 + 280: 47 49 4e 5f + 284: 5f 00 5f 65 + 288: 64 61 + 28a: 74 61 + 28c: 00 76 + 28e: 78 5f + 290: 70 65 + 292: 72 66 + 294: 5f 64 75 6d + 298: 70 00 + 29a: 5f 65 78 69 + 29e: 74 00 + 2a0: 5f 70 6f 63 + 2a4: 6c 5f + 2a6: 6b 65 72 6e + 2aa: 65 6c + 2ac: 5f 73 66 69 + 2b0: 6c 74 + 2b2: 65 72 + 2b4: 5f 77 6f 72 + 2b8: 6b 67 72 6f + 2bc: 75 70 + 2be: 5f 66 61 73 + 2c2: 74 00 + 2c4: 76 78 + 2c6: 5f 73 70 61 + 2ca: 77 6e 5f 6b + 2ce: 65 72 + 2d0: 6e 65 + 2d2: 6c 00 Disassembly of section .shstrtab: diff --git a/tests/opencl/sgemm/Makefile b/tests/opencl/sgemm/Makefile index ebfcad08..adb0b79e 100644 --- a/tests/opencl/sgemm/Makefile +++ b/tests/opencl/sgemm/Makefile @@ -9,8 +9,8 @@ OPTS ?= -n32 VORTEX_DRV_PATH ?= $(realpath ../../../driver) VORTEX_RT_PATH ?= $(realpath ../../../runtime) -K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -float-abi=hard -code-model=small" -K_CFLAGS += "-v -O3 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" +K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -mattr=+vortex -float-abi=hard -code-model=small" +K_CFLAGS += "-v -O3 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -Xclang -target-feature -Xclang +vortex -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" K_LDFLAGS += "-Wl,-Bstatic,-T$(VORTEX_RT_PATH)/linker/vx_link.ld -Wl,--gc-sections $(VORTEX_RT_PATH)/libvortexrt.a -lm" CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors @@ -35,13 +35,13 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ run-fpga: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-simx: $(PROJECT) kernel.pocl LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/opencl/sgemm/kernel.pocl b/tests/opencl/sgemm/kernel.pocl index e9f6d282..75bb6850 100644 Binary files a/tests/opencl/sgemm/kernel.pocl and b/tests/opencl/sgemm/kernel.pocl differ diff --git a/tests/opencl/sgemm/sgemm.dump b/tests/opencl/sgemm/sgemm.dump index 708277b7..51277e2d 100644 --- a/tests/opencl/sgemm/sgemm.dump +++ b/tests/opencl/sgemm/sgemm.dump @@ -1,39 +1,39 @@ -/tmp/pocl_vortex_kernel-35-bd-3b-d7-33.elf: file format ELF32-riscv +/tmp/pocl_vortex_kernel-c6-56-37-00-54.elf: file format ELF32-riscv Disassembly of section .init: 80000000 _start: 80000000: 97 05 00 00 auipc a1, 0 -80000004: 93 85 85 4d addi a1, a1, 1240 +80000004: 93 85 05 52 addi a1, a1, 1312 80000008: 73 25 10 fc csrr a0, 4033 -8000000c: 6b 10 b5 00 -80000010: ef 00 80 4c jal 1224 +8000000c: 6b 10 b5 00 vx_wspawn a0, a1 +80000010: ef 00 00 51 jal 1296 80000014: 13 05 10 00 addi a0, zero, 1 -80000018: 6b 00 05 00 +80000018: 6b 00 05 00 vx_tmc a0 8000001c: 17 15 00 00 auipc a0, 1 80000020: 13 05 45 42 addi a0, a0, 1060 80000024: 17 16 00 00 auipc a2, 1 80000028: 13 06 c6 49 addi a2, a2, 1180 8000002c: 33 06 a6 40 sub a2, a2, a0 80000030: 93 05 00 00 mv a1, zero -80000034: ef 00 90 3a jal 2984 -80000038: 17 15 00 00 auipc a0, 1 -8000003c: 13 05 c5 aa addi a0, a0, -1364 -80000040: ef 00 d0 25 jal 2652 -80000044: ef 00 d0 2f jal 2812 +80000034: ef 00 50 43 jal 3124 +80000038: 17 05 00 00 auipc a0, 0 +8000003c: 13 05 85 5b addi a0, a0, 1464 +80000040: ef 00 10 3e jal 3040 +80000044: ef 00 00 51 jal 1296 80000048: ef 00 00 02 jal 32 -8000004c: 6f 00 50 26 j 2660 +8000004c: 6f 00 90 3e j 3048 Disassembly of section .text: 80000050 register_fini: 80000050: 93 07 00 00 mv a5, zero 80000054: 63 88 07 00 beqz a5, 16 -80000058: 37 15 00 80 lui a0, 524289 -8000005c: 13 05 45 ae addi a0, a0, -1308 -80000060: 6f 00 d0 23 j 2620 +80000058: 37 05 00 80 lui a0, 524288 +8000005c: 13 05 05 5f addi a0, a0, 1520 +80000060: 6f 00 10 3c j 3008 80000064: 67 80 00 00 ret 80000068 main: @@ -44,7 +44,7 @@ Disassembly of section .text: 80000078: 37 05 ff 7f lui a0, 524272 8000007c: 13 06 45 03 addi a2, a0, 52 80000080: 37 05 ff 7f lui a0, 524272 -80000084: ef 00 80 5d jal 1496 +80000084: ef 00 40 7d jal 2004 80000088: 13 05 00 00 mv a0, zero 8000008c: 83 20 c1 00 lw ra, 12(sp) 80000090: 13 01 01 01 addi sp, sp, 16 @@ -143,832 +143,873 @@ Disassembly of section .text: 800001fc: 67 80 00 00 ret 80000200 _pocl_kernel_sgemm_workgroup: -80000200: 13 01 01 fe addi sp, sp, -32 -80000204: 23 2e 81 00 sw s0, 28(sp) -80000208: 23 2c 91 00 sw s1, 24(sp) -8000020c: 23 2a 21 01 sw s2, 20(sp) -80000210: 23 28 31 01 sw s3, 16(sp) -80000214: 23 26 41 01 sw s4, 12(sp) -80000218: 23 24 51 01 sw s5, 8(sp) -8000021c: 13 08 00 00 mv a6, zero -80000220: 03 27 05 00 lw a4, 0(a0) -80000224: 83 27 45 00 lw a5, 4(a0) -80000228: 83 24 85 00 lw s1, 8(a0) -8000022c: 03 25 c5 00 lw a0, 12(a0) -80000230: 03 27 07 00 lw a4, 0(a4) -80000234: 83 a7 07 00 lw a5, 0(a5) -80000238: 83 af 04 00 lw t6, 0(s1) -8000023c: 83 29 05 00 lw s3, 0(a0) -80000240: 03 aa 85 01 lw s4, 24(a1) -80000244: 83 a8 c5 01 lw a7, 28(a1) -80000248: 03 a5 c5 00 lw a0, 12(a1) -8000024c: 83 a2 05 02 lw t0, 32(a1) -80000250: 83 a5 05 01 lw a1, 16(a1) -80000254: 33 06 ca 02 mul a2, s4, a2 -80000258: 33 09 c5 00 add s2, a0, a2 -8000025c: 33 85 d8 02 mul a0, a7, a3 -80000260: 33 8e a5 00 add t3, a1, a0 -80000264: 33 85 c9 03 mul a0, s3, t3 -80000268: b3 05 a9 00 add a1, s2, a0 -8000026c: 93 95 25 00 slli a1, a1, 2 -80000270: 33 83 bf 00 add t1, t6, a1 -80000274: 13 15 25 00 slli a0, a0, 2 -80000278: b3 83 a7 00 add t2, a5, a0 -8000027c: 37 15 00 80 lui a0, 524289 -80000280: 13 05 85 43 addi a0, a0, 1080 -80000284: 07 20 05 00 flw ft0, 0(a0) -80000288: 13 15 29 00 slli a0, s2, 2 -8000028c: b3 0e a7 00 add t4, a4, a0 -80000290: 13 96 29 00 slli a2, s3, 2 -80000294: 6f 00 c0 00 j 12 -80000298: 13 08 18 00 addi a6, a6, 1 -8000029c: 63 78 58 0a bgeu a6, t0, 176 -800002a0: 63 5e 30 07 blez s3, 124 -800002a4: 13 0f 00 00 mv t5, zero -800002a8: 93 8a 03 00 mv s5, t2 -800002ac: 13 05 00 00 mv a0, zero -800002b0: b3 05 ee 01 add a1, t3, t5 -800002b4: 33 84 35 03 mul s0, a1, s3 -800002b8: 93 87 0e 00 mv a5, t4 -800002bc: b3 05 a9 00 add a1, s2, a0 -800002c0: 93 84 07 00 mv s1, a5 -800002c4: 93 86 0a 00 mv a3, s5 -800002c8: 13 87 09 00 mv a4, s3 -800002cc: d3 00 00 20 fmv.s ft1, ft0 -800002d0: 07 a1 04 00 flw ft2, 0(s1) -800002d4: 87 a1 06 00 flw ft3, 0(a3) -800002d8: 53 71 31 10 fmul.s ft2, ft2, ft3 -800002dc: d3 70 11 00 fadd.s ft1, ft2, ft1 -800002e0: 13 07 f7 ff addi a4, a4, -1 -800002e4: 93 86 46 00 addi a3, a3, 4 -800002e8: b3 84 c4 00 add s1, s1, a2 -800002ec: e3 12 07 fe bnez a4, -28 -800002f0: b3 85 85 00 add a1, a1, s0 -800002f4: 93 95 25 00 slli a1, a1, 2 -800002f8: b3 85 bf 00 add a1, t6, a1 -800002fc: 27 a0 15 00 fsw ft1, 0(a1) -80000300: 13 05 15 00 addi a0, a0, 1 -80000304: 93 87 47 00 addi a5, a5, 4 -80000308: e3 6a 45 fb bltu a0, s4, -76 -8000030c: 13 0f 1f 00 addi t5, t5, 1 -80000310: b3 8a ca 00 add s5, s5, a2 -80000314: e3 6c 1f f9 bltu t5, a7, -104 -80000318: 6f f0 1f f8 j -128 -8000031c: 13 05 00 00 mv a0, zero -80000320: 93 06 03 00 mv a3, t1 -80000324: 93 05 00 00 mv a1, zero -80000328: 13 87 06 00 mv a4, a3 -8000032c: 23 20 07 00 sw zero, 0(a4) -80000330: 93 85 15 00 addi a1, a1, 1 -80000334: 13 07 47 00 addi a4, a4, 4 -80000338: e3 ea 45 ff bltu a1, s4, -12 -8000033c: 13 05 15 00 addi a0, a0, 1 -80000340: b3 86 c6 00 add a3, a3, a2 -80000344: e3 60 15 ff bltu a0, a7, -32 -80000348: 6f f0 1f f5 j -176 -8000034c: 83 2a 81 00 lw s5, 8(sp) -80000350: 03 2a c1 00 lw s4, 12(sp) -80000354: 83 29 01 01 lw s3, 16(sp) -80000358: 03 29 41 01 lw s2, 20(sp) -8000035c: 83 24 81 01 lw s1, 24(sp) -80000360: 03 24 c1 01 lw s0, 28(sp) -80000364: 13 01 01 02 addi sp, sp, 32 -80000368: 67 80 00 00 ret +80000200: 13 01 01 fd addi sp, sp, -48 +80000204: 23 26 81 02 sw s0, 44(sp) +80000208: 23 24 91 02 sw s1, 40(sp) +8000020c: 23 22 21 03 sw s2, 36(sp) +80000210: 23 20 31 03 sw s3, 32(sp) +80000214: 23 2e 41 01 sw s4, 28(sp) +80000218: 23 2c 51 01 sw s5, 24(sp) +8000021c: 23 2a 61 01 sw s6, 20(sp) +80000220: 23 28 71 01 sw s7, 16(sp) +80000224: 23 26 81 01 sw s8, 12(sp) +80000228: 13 08 00 00 mv a6, zero +8000022c: 03 27 05 00 lw a4, 0(a0) +80000230: 83 27 45 00 lw a5, 4(a0) +80000234: 83 24 85 00 lw s1, 8(a0) +80000238: 03 25 c5 00 lw a0, 12(a0) +8000023c: 03 27 07 00 lw a4, 0(a4) +80000240: 83 a7 07 00 lw a5, 0(a5) +80000244: 03 a9 04 00 lw s2, 0(s1) +80000248: 03 2a 05 00 lw s4, 0(a0) +8000024c: 83 aa 85 01 lw s5, 24(a1) +80000250: 83 a8 c5 01 lw a7, 28(a1) +80000254: 03 a5 c5 00 lw a0, 12(a1) +80000258: 83 a2 05 02 lw t0, 32(a1) +8000025c: 83 a5 05 01 lw a1, 16(a1) +80000260: 33 86 ca 02 mul a2, s5, a2 +80000264: b3 09 c5 00 add s3, a0, a2 +80000268: 33 85 d8 02 mul a0, a7, a3 +8000026c: b3 8e a5 00 add t4, a1, a0 +80000270: 33 05 da 03 mul a0, s4, t4 +80000274: b3 85 a9 00 add a1, s3, a0 +80000278: 93 95 25 00 slli a1, a1, 2 +8000027c: 33 03 b9 00 add t1, s2, a1 +80000280: 93 16 2a 00 slli a3, s4, 2 +80000284: 13 15 25 00 slli a0, a0, 2 +80000288: b3 83 a7 00 add t2, a5, a0 +8000028c: 37 15 00 80 lui a0, 524289 +80000290: 13 05 85 43 addi a0, a0, 1080 +80000294: 07 20 05 00 flw ft0, 0(a0) +80000298: 13 95 29 00 slli a0, s3, 2 +8000029c: 33 0f a7 00 add t5, a4, a0 +800002a0: 73 2e 40 cc csrr t3, tmask +800002a4: 6f 00 00 01 j 16 +800002a8: 6b 30 00 00 vx_join +800002ac: 13 08 18 00 addi a6, a6, 1 +800002b0: 63 74 58 0c bgeu a6, t0, 200 +800002b4: 33 25 40 01 sgtz a0, s4 +800002b8: 6b 20 05 00 vx_split a0 +800002bc: 63 56 40 09 blez s4, 140 +800002c0: 93 0f 00 00 mv t6, zero +800002c4: 13 8b 03 00 mv s6, t2 +800002c8: 13 04 00 00 mv s0, zero +800002cc: 33 85 fe 01 add a0, t4, t6 +800002d0: b3 0b 45 03 mul s7, a0, s4 +800002d4: 13 07 0f 00 mv a4, t5 +800002d8: 33 8c 89 00 add s8, s3, s0 +800002dc: f3 27 40 cc csrr a5, tmask +800002e0: 13 05 07 00 mv a0, a4 +800002e4: 13 06 0b 00 mv a2, s6 +800002e8: 93 04 0a 00 mv s1, s4 +800002ec: d3 00 00 20 fmv.s ft1, ft0 +800002f0: 07 21 05 00 flw ft2, 0(a0) +800002f4: 87 21 06 00 flw ft3, 0(a2) +800002f8: 53 71 31 10 fmul.s ft2, ft2, ft3 +800002fc: 93 84 f4 ff addi s1, s1, -1 +80000300: b3 35 90 00 snez a1, s1 +80000304: 6b 80 15 00 vx_pred a1 +80000308: d3 70 11 00 fadd.s ft1, ft2, ft1 +8000030c: 13 06 46 00 addi a2, a2, 4 +80000310: 33 05 d5 00 add a0, a0, a3 +80000314: e3 9e 04 fc bnez s1, -36 +80000318: 6b 80 07 00 vx_tmc a5 +8000031c: 33 05 7c 01 add a0, s8, s7 +80000320: 13 15 25 00 slli a0, a0, 2 +80000324: 33 05 a9 00 add a0, s2, a0 +80000328: 27 20 15 00 fsw ft1, 0(a0) +8000032c: 13 04 14 00 addi s0, s0, 1 +80000330: 13 07 47 00 addi a4, a4, 4 +80000334: e3 62 54 fb bltu s0, s5, -92 +80000338: 93 8f 1f 00 addi t6, t6, 1 +8000033c: 33 0b db 00 add s6, s6, a3 +80000340: e3 e4 1f f9 bltu t6, a7, -120 +80000344: 6f f0 5f f6 j -156 +80000348: 13 05 00 00 mv a0, zero +8000034c: 93 05 03 00 mv a1, t1 +80000350: 13 06 00 00 mv a2, zero +80000354: 13 87 05 00 mv a4, a1 +80000358: 23 20 07 00 sw zero, 0(a4) +8000035c: 13 06 16 00 addi a2, a2, 1 +80000360: 13 07 47 00 addi a4, a4, 4 +80000364: e3 6a 56 ff bltu a2, s5, -12 +80000368: 13 05 15 00 addi a0, a0, 1 +8000036c: b3 85 d5 00 add a1, a1, a3 +80000370: e3 60 15 ff bltu a0, a7, -32 +80000374: 6f f0 5f f3 j -204 +80000378: 6b 00 0e 00 vx_tmc t3 +8000037c: 03 2c c1 00 lw s8, 12(sp) +80000380: 83 2b 01 01 lw s7, 16(sp) +80000384: 03 2b 41 01 lw s6, 20(sp) +80000388: 83 2a 81 01 lw s5, 24(sp) +8000038c: 03 2a c1 01 lw s4, 28(sp) +80000390: 83 29 01 02 lw s3, 32(sp) +80000394: 03 29 41 02 lw s2, 36(sp) +80000398: 83 24 81 02 lw s1, 40(sp) +8000039c: 03 24 c1 02 lw s0, 44(sp) +800003a0: 13 01 01 03 addi sp, sp, 48 +800003a4: 67 80 00 00 ret -8000036c _pocl_kernel_sgemm_workgroup_fast: -8000036c: 13 01 01 fe addi sp, sp, -32 -80000370: 23 2e 81 00 sw s0, 28(sp) -80000374: 23 2c 91 00 sw s1, 24(sp) -80000378: 23 2a 21 01 sw s2, 20(sp) -8000037c: 23 28 31 01 sw s3, 16(sp) -80000380: 23 26 41 01 sw s4, 12(sp) -80000384: 23 24 51 01 sw s5, 8(sp) -80000388: 13 08 00 00 mv a6, zero -8000038c: 03 27 c5 00 lw a4, 12(a0) -80000390: 83 27 05 00 lw a5, 0(a0) -80000394: 83 24 45 00 lw s1, 4(a0) -80000398: 83 2f 85 00 lw t6, 8(a0) -8000039c: 83 29 07 00 lw s3, 0(a4) -800003a0: 03 aa 85 01 lw s4, 24(a1) -800003a4: 83 a8 c5 01 lw a7, 28(a1) -800003a8: 03 a5 c5 00 lw a0, 12(a1) -800003ac: 83 a2 05 02 lw t0, 32(a1) -800003b0: 83 a5 05 01 lw a1, 16(a1) -800003b4: 33 06 ca 02 mul a2, s4, a2 -800003b8: 33 09 c5 00 add s2, a0, a2 -800003bc: 33 85 d8 02 mul a0, a7, a3 -800003c0: 33 8e a5 00 add t3, a1, a0 -800003c4: 33 85 c9 03 mul a0, s3, t3 -800003c8: b3 05 a9 00 add a1, s2, a0 -800003cc: 93 95 25 00 slli a1, a1, 2 -800003d0: 33 83 bf 00 add t1, t6, a1 -800003d4: 13 15 25 00 slli a0, a0, 2 -800003d8: b3 83 a4 00 add t2, s1, a0 -800003dc: 37 15 00 80 lui a0, 524289 -800003e0: 13 05 c5 43 addi a0, a0, 1084 -800003e4: 07 20 05 00 flw ft0, 0(a0) -800003e8: 13 15 29 00 slli a0, s2, 2 -800003ec: b3 8e a7 00 add t4, a5, a0 -800003f0: 13 96 29 00 slli a2, s3, 2 -800003f4: 6f 00 c0 00 j 12 -800003f8: 13 08 18 00 addi a6, a6, 1 -800003fc: 63 78 58 0a bgeu a6, t0, 176 -80000400: 63 5e 30 07 blez s3, 124 -80000404: 13 0f 00 00 mv t5, zero -80000408: 93 8a 03 00 mv s5, t2 -8000040c: 13 05 00 00 mv a0, zero -80000410: b3 05 ee 01 add a1, t3, t5 -80000414: 33 84 35 03 mul s0, a1, s3 -80000418: 93 87 0e 00 mv a5, t4 -8000041c: b3 05 a9 00 add a1, s2, a0 -80000420: 93 84 07 00 mv s1, a5 -80000424: 93 86 0a 00 mv a3, s5 -80000428: 13 87 09 00 mv a4, s3 -8000042c: d3 00 00 20 fmv.s ft1, ft0 -80000430: 07 a1 04 00 flw ft2, 0(s1) -80000434: 87 a1 06 00 flw ft3, 0(a3) -80000438: 53 71 31 10 fmul.s ft2, ft2, ft3 -8000043c: d3 70 11 00 fadd.s ft1, ft2, ft1 -80000440: 13 07 f7 ff addi a4, a4, -1 -80000444: 93 86 46 00 addi a3, a3, 4 -80000448: b3 84 c4 00 add s1, s1, a2 -8000044c: e3 12 07 fe bnez a4, -28 -80000450: b3 85 85 00 add a1, a1, s0 -80000454: 93 95 25 00 slli a1, a1, 2 -80000458: b3 85 bf 00 add a1, t6, a1 -8000045c: 27 a0 15 00 fsw ft1, 0(a1) -80000460: 13 05 15 00 addi a0, a0, 1 -80000464: 93 87 47 00 addi a5, a5, 4 -80000468: e3 6a 45 fb bltu a0, s4, -76 -8000046c: 13 0f 1f 00 addi t5, t5, 1 -80000470: b3 8a ca 00 add s5, s5, a2 -80000474: e3 6c 1f f9 bltu t5, a7, -104 -80000478: 6f f0 1f f8 j -128 -8000047c: 13 05 00 00 mv a0, zero -80000480: 93 05 03 00 mv a1, t1 -80000484: 93 06 00 00 mv a3, zero -80000488: 13 87 05 00 mv a4, a1 -8000048c: 23 20 07 00 sw zero, 0(a4) -80000490: 93 86 16 00 addi a3, a3, 1 -80000494: 13 07 47 00 addi a4, a4, 4 -80000498: e3 ea 46 ff bltu a3, s4, -12 +800003a8 _pocl_kernel_sgemm_workgroup_fast: +800003a8: 13 01 01 fe addi sp, sp, -32 +800003ac: 23 2e 81 00 sw s0, 28(sp) +800003b0: 23 2c 91 00 sw s1, 24(sp) +800003b4: 23 2a 21 01 sw s2, 20(sp) +800003b8: 23 28 31 01 sw s3, 16(sp) +800003bc: 23 26 41 01 sw s4, 12(sp) +800003c0: 23 24 51 01 sw s5, 8(sp) +800003c4: 13 08 00 00 mv a6, zero +800003c8: 03 27 c5 00 lw a4, 12(a0) +800003cc: 83 27 05 00 lw a5, 0(a0) +800003d0: 83 24 45 00 lw s1, 4(a0) +800003d4: 83 2f 85 00 lw t6, 8(a0) +800003d8: 83 29 07 00 lw s3, 0(a4) +800003dc: 03 aa 85 01 lw s4, 24(a1) +800003e0: 83 a8 c5 01 lw a7, 28(a1) +800003e4: 03 a5 c5 00 lw a0, 12(a1) +800003e8: 83 a2 05 02 lw t0, 32(a1) +800003ec: 83 a5 05 01 lw a1, 16(a1) +800003f0: 33 06 ca 02 mul a2, s4, a2 +800003f4: 33 09 c5 00 add s2, a0, a2 +800003f8: 33 85 d8 02 mul a0, a7, a3 +800003fc: 33 8e a5 00 add t3, a1, a0 +80000400: 33 85 c9 03 mul a0, s3, t3 +80000404: b3 05 a9 00 add a1, s2, a0 +80000408: 93 95 25 00 slli a1, a1, 2 +8000040c: 33 83 bf 00 add t1, t6, a1 +80000410: 13 15 25 00 slli a0, a0, 2 +80000414: b3 83 a4 00 add t2, s1, a0 +80000418: 37 15 00 80 lui a0, 524289 +8000041c: 13 05 c5 43 addi a0, a0, 1084 +80000420: 07 20 05 00 flw ft0, 0(a0) +80000424: 13 15 29 00 slli a0, s2, 2 +80000428: b3 8e a7 00 add t4, a5, a0 +8000042c: 13 96 29 00 slli a2, s3, 2 +80000430: 6f 00 c0 00 j 12 +80000434: 13 08 18 00 addi a6, a6, 1 +80000438: 63 78 58 0a bgeu a6, t0, 176 +8000043c: 63 5e 30 07 blez s3, 124 +80000440: 13 0f 00 00 mv t5, zero +80000444: 93 8a 03 00 mv s5, t2 +80000448: 13 05 00 00 mv a0, zero +8000044c: b3 05 ee 01 add a1, t3, t5 +80000450: 33 84 35 03 mul s0, a1, s3 +80000454: 93 87 0e 00 mv a5, t4 +80000458: b3 05 a9 00 add a1, s2, a0 +8000045c: 93 84 07 00 mv s1, a5 +80000460: 93 86 0a 00 mv a3, s5 +80000464: 13 87 09 00 mv a4, s3 +80000468: d3 00 00 20 fmv.s ft1, ft0 +8000046c: 07 a1 04 00 flw ft2, 0(s1) +80000470: 87 a1 06 00 flw ft3, 0(a3) +80000474: 53 71 31 10 fmul.s ft2, ft2, ft3 +80000478: d3 70 11 00 fadd.s ft1, ft2, ft1 +8000047c: 13 07 f7 ff addi a4, a4, -1 +80000480: 93 86 46 00 addi a3, a3, 4 +80000484: b3 84 c4 00 add s1, s1, a2 +80000488: e3 12 07 fe bnez a4, -28 +8000048c: b3 85 85 00 add a1, a1, s0 +80000490: 93 95 25 00 slli a1, a1, 2 +80000494: b3 85 bf 00 add a1, t6, a1 +80000498: 27 a0 15 00 fsw ft1, 0(a1) 8000049c: 13 05 15 00 addi a0, a0, 1 -800004a0: b3 85 c5 00 add a1, a1, a2 -800004a4: e3 60 15 ff bltu a0, a7, -32 -800004a8: 6f f0 1f f5 j -176 -800004ac: 83 2a 81 00 lw s5, 8(sp) -800004b0: 03 2a c1 00 lw s4, 12(sp) -800004b4: 83 29 01 01 lw s3, 16(sp) -800004b8: 03 29 41 01 lw s2, 20(sp) -800004bc: 83 24 81 01 lw s1, 24(sp) -800004c0: 03 24 c1 01 lw s0, 28(sp) -800004c4: 13 01 01 02 addi sp, sp, 32 -800004c8: 67 80 00 00 ret +800004a0: 93 87 47 00 addi a5, a5, 4 +800004a4: e3 6a 45 fb bltu a0, s4, -76 +800004a8: 13 0f 1f 00 addi t5, t5, 1 +800004ac: b3 8a ca 00 add s5, s5, a2 +800004b0: e3 6c 1f f9 bltu t5, a7, -104 +800004b4: 6f f0 1f f8 j -128 +800004b8: 13 05 00 00 mv a0, zero +800004bc: 93 05 03 00 mv a1, t1 +800004c0: 93 06 00 00 mv a3, zero +800004c4: 13 87 05 00 mv a4, a1 +800004c8: 23 20 07 00 sw zero, 0(a4) +800004cc: 93 86 16 00 addi a3, a3, 1 +800004d0: 13 07 47 00 addi a4, a4, 4 +800004d4: e3 ea 46 ff bltu a3, s4, -12 +800004d8: 13 05 15 00 addi a0, a0, 1 +800004dc: b3 85 c5 00 add a1, a1, a2 +800004e0: e3 60 15 ff bltu a0, a7, -32 +800004e4: 6f f0 1f f5 j -176 +800004e8: 83 2a 81 00 lw s5, 8(sp) +800004ec: 03 2a c1 00 lw s4, 12(sp) +800004f0: 83 29 01 01 lw s3, 16(sp) +800004f4: 03 29 41 01 lw s2, 20(sp) +800004f8: 83 24 81 01 lw s1, 24(sp) +800004fc: 03 24 c1 01 lw s0, 28(sp) +80000500: 13 01 01 02 addi sp, sp, 32 +80000504: 67 80 00 00 ret -800004cc _exit: -800004cc: ef 00 c0 3b jal 956 -800004d0: 13 05 00 00 mv a0, zero -800004d4: 6b 00 05 00 +80000508 _exit: +80000508: 63 06 05 00 beqz a0, 12 +8000050c: 93 01 05 00 mv gp, a0 +80000510: 73 00 00 00 ecall -800004d8 vx_set_sp: -800004d8: 73 25 00 fc csrr a0, 4032 -800004dc: 6b 00 05 00 -800004e0: 97 11 00 00 auipc gp, 1 -800004e4: 93 81 81 32 addi gp, gp, 808 -800004e8: 17 01 00 7f auipc sp, 520192 -800004ec: 13 01 81 b1 addi sp, sp, -1256 -800004f0: 93 05 00 40 addi a1, zero, 1024 -800004f4: 73 26 10 cc csrr a2, 3265 -800004f8: b3 85 c5 02 mul a1, a1, a2 -800004fc: 33 01 b1 40 sub sp, sp, a1 -80000500: f3 26 30 cc csrr a3, 3267 -80000504: 63 86 06 00 beqz a3, 12 -80000508: 13 05 00 00 mv a0, zero -8000050c: 6b 00 05 00 +80000514 label_exit_next: +80000514: ef 00 80 4f jal 1272 +80000518: 13 05 00 00 mv a0, zero +8000051c: 6b 00 05 00 vx_tmc a0 -80000510 RETURN: -80000510: 67 80 00 00 ret +80000520 vx_set_sp: +80000520: 13 05 f0 ff addi a0, zero, -1 +80000524: 6b 00 05 00 vx_tmc a0 +80000528: 97 11 00 00 auipc gp, 1 +8000052c: 93 81 01 2e addi gp, gp, 736 +80000530: 37 01 00 ff lui sp, 1044480 +80000534: 73 26 10 cc csrr a2, 3265 +80000538: 93 15 a6 00 slli a1, a2, 10 +8000053c: 33 01 b1 40 sub sp, sp, a1 +80000540: f3 26 30 cc csrr a3, 3267 +80000544: 63 86 06 00 beqz a3, 12 +80000548: 13 05 00 00 mv a0, zero +8000054c: 6b 00 05 00 vx_tmc a0 -80000514 spawn_kernel_callback: -80000514: 13 01 01 fe addi sp, sp, -32 -80000518: 23 2e 11 00 sw ra, 28(sp) -8000051c: 23 2c 81 00 sw s0, 24(sp) -80000520: 23 2a 91 00 sw s1, 20(sp) -80000524: 23 28 21 01 sw s2, 16(sp) -80000528: 23 26 31 01 sw s3, 12(sp) -8000052c: 23 24 41 01 sw s4, 8(sp) -80000530: 23 22 51 01 sw s5, 4(sp) -80000534: f3 27 00 fc csrr a5, 4032 -80000538: 6b 80 07 00 -8000053c: f3 26 50 cc csrr a3, 3269 -80000540: 73 29 30 cc csrr s2, 3267 -80000544: 73 27 00 cc csrr a4, 3264 -80000548: 73 26 00 fc csrr a2, 4032 -8000054c: b7 17 00 80 lui a5, 524289 -80000550: 93 96 26 00 slli a3, a3, 2 -80000554: 93 87 07 44 addi a5, a5, 1088 -80000558: b3 87 d7 00 add a5, a5, a3 -8000055c: 03 a4 07 00 lw s0, 0(a5) -80000560: 83 24 44 01 lw s1, 20(s0) -80000564: 83 26 04 01 lw a3, 16(s0) -80000568: b3 2a 99 00 slt s5, s2, s1 -8000056c: 93 87 04 00 mv a5, s1 -80000570: b3 8a da 00 add s5, s5, a3 -80000574: b3 84 26 03 mul s1, a3, s2 -80000578: 63 54 f9 00 bge s2, a5, 8 -8000057c: 93 07 09 00 mv a5, s2 -80000580: b3 84 f4 00 add s1, s1, a5 -80000584: 83 25 04 00 lw a1, 0(s0) -80000588: 83 26 c4 00 lw a3, 12(s0) -8000058c: 83 a9 05 00 lw s3, 0(a1) -80000590: 03 aa 45 00 lw s4, 4(a1) -80000594: b3 84 c4 02 mul s1, s1, a2 -80000598: b3 87 ea 02 mul a5, s5, a4 -8000059c: b3 84 d4 00 add s1, s1, a3 -800005a0: b3 84 f4 00 add s1, s1, a5 -800005a4: b3 8a 9a 00 add s5, s5, s1 -800005a8: 33 8a 49 03 mul s4, s3, s4 -800005ac: 63 c0 54 07 blt s1, s5, 96 -800005b0: 6f 00 00 08 j 128 -800005b4: 03 47 a4 01 lbu a4, 26(s0) -800005b8: 83 46 94 01 lbu a3, 25(s0) -800005bc: 33 d7 e4 40 sra a4, s1, a4 -800005c0: b3 07 47 03 mul a5, a4, s4 -800005c4: b3 87 f4 40 sub a5, s1, a5 -800005c8: 63 80 06 06 beqz a3, 96 -800005cc: 83 46 b4 01 lbu a3, 27(s0) -800005d0: b3 d6 d7 40 sra a3, a5, a3 -800005d4: b3 88 36 03 mul a7, a3, s3 -800005d8: 03 ae 45 01 lw t3, 20(a1) -800005dc: 03 a3 05 01 lw t1, 16(a1) -800005e0: 03 a6 c5 00 lw a2, 12(a1) -800005e4: 03 28 44 00 lw a6, 4(s0) -800005e8: 03 25 84 00 lw a0, 8(s0) -800005ec: 93 84 14 00 addi s1, s1, 1 -800005f0: 33 07 c7 01 add a4, a4, t3 -800005f4: b3 86 66 00 add a3, a3, t1 -800005f8: b3 87 17 41 sub a5, a5, a7 -800005fc: 33 86 c7 00 add a2, a5, a2 -80000600: e7 00 08 00 jalr a6 -80000604: 63 86 9a 02 beq s5, s1, 44 -80000608: 83 25 04 00 lw a1, 0(s0) -8000060c: 83 47 84 01 lbu a5, 24(s0) -80000610: e3 92 07 fa bnez a5, -92 -80000614: 33 c7 44 03 div a4, s1, s4 -80000618: 83 46 94 01 lbu a3, 25(s0) -8000061c: b3 07 47 03 mul a5, a4, s4 -80000620: b3 87 f4 40 sub a5, s1, a5 -80000624: e3 94 06 fa bnez a3, -88 -80000628: b3 c6 37 03 div a3, a5, s3 -8000062c: 6f f0 9f fa j -88 -80000630: 13 39 19 00 seqz s2, s2 -80000634: 6b 00 09 00 -80000638: 83 20 c1 01 lw ra, 28(sp) -8000063c: 03 24 81 01 lw s0, 24(sp) -80000640: 83 24 41 01 lw s1, 20(sp) -80000644: 03 29 01 01 lw s2, 16(sp) -80000648: 83 29 c1 00 lw s3, 12(sp) -8000064c: 03 2a 81 00 lw s4, 8(sp) -80000650: 83 2a 41 00 lw s5, 4(sp) -80000654: 13 01 01 02 addi sp, sp, 32 -80000658: 67 80 00 00 ret +80000550 RETURN: +80000550: 67 80 00 00 ret -8000065c vx_spawn_kernel: -8000065c: 13 01 01 fc addi sp, sp, -64 -80000660: 23 2e 11 02 sw ra, 60(sp) -80000664: 23 2c 81 02 sw s0, 56(sp) -80000668: 23 2a 91 02 sw s1, 52(sp) -8000066c: 23 28 21 03 sw s2, 48(sp) -80000670: 23 26 31 03 sw s3, 44(sp) -80000674: f3 28 20 fc csrr a7, 4034 -80000678: 73 23 10 fc csrr t1, 4033 -8000067c: 73 24 00 fc csrr s0, 4032 -80000680: f3 27 50 cc csrr a5, 3269 -80000684: 13 07 f0 01 addi a4, zero, 31 -80000688: 63 46 f7 0e blt a4, a5, 236 -8000068c: 03 2e 05 00 lw t3, 0(a0) -80000690: 83 26 45 00 lw a3, 4(a0) -80000694: 03 28 85 00 lw a6, 8(a0) -80000698: b3 0e 83 02 mul t4, t1, s0 -8000069c: 13 07 10 00 addi a4, zero, 1 -800006a0: b3 06 de 02 mul a3, t3, a3 -800006a4: 33 88 06 03 mul a6, a3, a6 -800006a8: 63 d4 0e 01 bge t4, a6, 8 -800006ac: 33 47 d8 03 div a4, a6, t4 -800006b0: 63 c0 e8 0e blt a7, a4, 224 -800006b4: 63 d0 e7 0c bge a5, a4, 192 -800006b8: 93 88 f8 ff addi a7, a7, -1 -800006bc: b3 4e e8 02 div t4, a6, a4 -800006c0: 93 84 0e 00 mv s1, t4 -800006c4: 63 96 f8 00 bne a7, a5, 12 -800006c8: 33 67 e8 02 rem a4, a6, a4 -800006cc: b3 04 d7 01 add s1, a4, t4 -800006d0: 33 c9 84 02 div s2, s1, s0 -800006d4: b3 e4 84 02 rem s1, s1, s0 -800006d8: 63 42 69 0c blt s2, t1, 196 -800006dc: 93 02 10 00 addi t0, zero, 1 -800006e0: 33 48 69 02 div a6, s2, t1 -800006e4: 63 06 08 00 beqz a6, 12 -800006e8: 93 02 08 00 mv t0, a6 -800006ec: 33 68 69 02 rem a6, s2, t1 -800006f0: d3 f7 06 d0 fcvt.s.w fa5, a3 -800006f4: 93 8f f6 ff addi t6, a3, -1 -800006f8: 13 0f fe ff addi t5, t3, -1 -800006fc: b7 19 00 80 lui s3, 524289 -80000700: b3 f6 df 00 and a3, t6, a3 -80000704: 93 89 09 44 addi s3, s3, 1088 -80000708: 93 b6 16 00 seqz a3, a3 -8000070c: 23 22 a1 00 sw a0, 4(sp) -80000710: 23 24 b1 00 sw a1, 8(sp) -80000714: 23 26 c1 00 sw a2, 12(sp) -80000718: 23 2a 51 00 sw t0, 20(sp) -8000071c: 23 2c 01 01 sw a6, 24(sp) -80000720: 23 0e d1 00 sb a3, 28(sp) -80000724: 33 87 fe 02 mul a4, t4, a5 -80000728: d3 8e 07 e0 fmv.x.w t4, fa5 -8000072c: d3 77 0e d0 fcvt.s.w fa5, t3 -80000730: 93 97 27 00 slli a5, a5, 2 -80000734: 33 7e cf 01 and t3, t5, t3 -80000738: d3 88 07 e0 fmv.x.w a7, fa5 -8000073c: 93 de 7e 41 srai t4, t4, 23 -80000740: 13 3e 1e 00 seqz t3, t3 -80000744: 93 d8 78 41 srai a7, a7, 23 -80000748: 93 8e 1e f8 addi t4, t4, -127 -8000074c: 93 88 18 f8 addi a7, a7, -127 -80000750: b3 87 f9 00 add a5, s3, a5 -80000754: 23 28 e1 00 sw a4, 16(sp) -80000758: 13 07 41 00 addi a4, sp, 4 -8000075c: a3 0e c1 01 sb t3, 29(sp) -80000760: 23 0f d1 01 sb t4, 30(sp) -80000764: a3 0f 11 01 sb a7, 31(sp) -80000768: 23 a0 e7 00 sw a4, 0(a5) -8000076c: 63 4e 20 03 bgtz s2, 60 -80000770: 63 9c 04 04 bnez s1, 88 -80000774: 83 20 c1 03 lw ra, 60(sp) -80000778: 03 24 81 03 lw s0, 56(sp) -8000077c: 83 24 41 03 lw s1, 52(sp) -80000780: 03 29 01 03 lw s2, 48(sp) -80000784: 83 29 c1 02 lw s3, 44(sp) -80000788: 13 01 01 04 addi sp, sp, 64 -8000078c: 67 80 00 00 ret -80000790: 13 87 08 00 mv a4, a7 -80000794: e3 c2 e7 f2 blt a5, a4, -220 -80000798: 6f f0 df fd j -36 -8000079c: 13 08 00 00 mv a6, zero -800007a0: 93 02 10 00 addi t0, zero, 1 -800007a4: 6f f0 df f4 j -180 -800007a8: 13 07 09 00 mv a4, s2 -800007ac: 63 54 23 01 bge t1, s2, 8 -800007b0: 13 07 03 00 mv a4, t1 -800007b4: b7 07 00 80 lui a5, 524288 -800007b8: 93 87 47 51 addi a5, a5, 1300 -800007bc: 6b 10 f7 00 -800007c0: ef f0 5f d5 jal -684 -800007c4: e3 88 04 fa beqz s1, -80 -800007c8: 33 04 89 02 mul s0, s2, s0 -800007cc: 23 28 81 00 sw s0, 16(sp) -800007d0: 6b 80 04 00 -800007d4: 73 27 50 cc csrr a4, 3269 -800007d8: f3 27 20 cc csrr a5, 3266 -800007dc: 13 17 27 00 slli a4, a4, 2 -800007e0: b3 89 e9 00 add s3, s3, a4 -800007e4: 03 a5 09 00 lw a0, 0(s3) -800007e8: 83 25 05 00 lw a1, 0(a0) -800007ec: 83 26 c5 00 lw a3, 12(a0) -800007f0: 03 47 85 01 lbu a4, 24(a0) -800007f4: 03 a8 05 00 lw a6, 0(a1) -800007f8: 03 a6 45 00 lw a2, 4(a1) -800007fc: b3 87 d7 00 add a5, a5, a3 -80000800: 33 06 c8 02 mul a2, a6, a2 -80000804: 63 0e 07 06 beqz a4, 124 -80000808: 03 47 a5 01 lbu a4, 26(a0) -8000080c: 33 d7 e7 40 sra a4, a5, a4 -80000810: 83 46 95 01 lbu a3, 25(a0) -80000814: 33 06 e6 02 mul a2, a2, a4 -80000818: b3 87 c7 40 sub a5, a5, a2 -8000081c: 63 8e 06 04 beqz a3, 92 -80000820: 83 48 b5 01 lbu a7, 27(a0) -80000824: b3 d8 17 41 sra a7, a5, a7 -80000828: 33 08 18 03 mul a6, a6, a7 -8000082c: 03 ae 45 01 lw t3, 20(a1) -80000830: 83 a6 05 01 lw a3, 16(a1) -80000834: 03 a6 c5 00 lw a2, 12(a1) -80000838: 03 23 45 00 lw t1, 4(a0) -8000083c: 03 25 85 00 lw a0, 8(a0) -80000840: 33 07 c7 01 add a4, a4, t3 -80000844: b3 86 d8 00 add a3, a7, a3 -80000848: b3 87 07 41 sub a5, a5, a6 -8000084c: 33 86 c7 00 add a2, a5, a2 -80000850: e7 00 03 00 jalr t1 -80000854: 93 07 10 00 addi a5, zero, 1 -80000858: 6b 80 07 00 -8000085c: 83 20 c1 03 lw ra, 60(sp) -80000860: 03 24 81 03 lw s0, 56(sp) -80000864: 83 24 41 03 lw s1, 52(sp) -80000868: 03 29 01 03 lw s2, 48(sp) -8000086c: 83 29 c1 02 lw s3, 44(sp) -80000870: 13 01 01 04 addi sp, sp, 64 -80000874: 67 80 00 00 ret -80000878: b3 c8 07 03 div a7, a5, a6 -8000087c: 6f f0 df fa j -84 -80000880: 33 c7 c7 02 div a4, a5, a2 -80000884: 6f f0 df f8 j -116 +80000554 __libc_init_array: +80000554: 13 01 01 ff addi sp, sp, -16 +80000558: 23 24 81 00 sw s0, 8(sp) +8000055c: 23 20 21 01 sw s2, 0(sp) +80000560: 37 14 00 80 lui s0, 524289 +80000564: 37 19 00 80 lui s2, 524289 +80000568: 93 07 04 00 mv a5, s0 +8000056c: 13 09 09 00 mv s2, s2 +80000570: 33 09 f9 40 sub s2, s2, a5 +80000574: 23 26 11 00 sw ra, 12(sp) +80000578: 23 22 91 00 sw s1, 4(sp) +8000057c: 13 59 29 40 srai s2, s2, 2 +80000580: 63 00 09 02 beqz s2, 32 +80000584: 13 04 04 00 mv s0, s0 +80000588: 93 04 00 00 mv s1, zero +8000058c: 83 27 04 00 lw a5, 0(s0) +80000590: 93 84 14 00 addi s1, s1, 1 +80000594: 13 04 44 00 addi s0, s0, 4 +80000598: e7 80 07 00 jalr a5 +8000059c: e3 18 99 fe bne s2, s1, -16 +800005a0: 37 14 00 80 lui s0, 524289 +800005a4: 37 19 00 80 lui s2, 524289 +800005a8: 93 07 04 00 mv a5, s0 +800005ac: 13 09 49 00 addi s2, s2, 4 +800005b0: 33 09 f9 40 sub s2, s2, a5 +800005b4: 13 59 29 40 srai s2, s2, 2 +800005b8: 63 00 09 02 beqz s2, 32 +800005bc: 13 04 04 00 mv s0, s0 +800005c0: 93 04 00 00 mv s1, zero +800005c4: 83 27 04 00 lw a5, 0(s0) +800005c8: 93 84 14 00 addi s1, s1, 1 +800005cc: 13 04 44 00 addi s0, s0, 4 +800005d0: e7 80 07 00 jalr a5 +800005d4: e3 18 99 fe bne s2, s1, -16 +800005d8: 83 20 c1 00 lw ra, 12(sp) +800005dc: 03 24 81 00 lw s0, 8(sp) +800005e0: 83 24 41 00 lw s1, 4(sp) +800005e4: 03 29 01 00 lw s2, 0(sp) +800005e8: 13 01 01 01 addi sp, sp, 16 +800005ec: 67 80 00 00 ret -80000888 vx_perf_dump: -80000888: f3 27 50 cc csrr a5, 3269 -8000088c: 37 07 ff 00 lui a4, 4080 -80000890: b3 87 e7 00 add a5, a5, a4 -80000894: 93 97 87 00 slli a5, a5, 8 -80000898: 73 27 00 b0 csrr a4, mcycle -8000089c: 23 a0 e7 00 sw a4, 0(a5) -800008a0: 73 27 10 b0 csrr a4, 2817 -800008a4: 23 a2 e7 00 sw a4, 4(a5) -800008a8: 73 27 20 b0 csrr a4, minstret -800008ac: 23 a4 e7 00 sw a4, 8(a5) -800008b0: 73 27 30 b0 csrr a4, mhpmcounter3 -800008b4: 23 a6 e7 00 sw a4, 12(a5) -800008b8: 73 27 40 b0 csrr a4, mhpmcounter4 -800008bc: 23 a8 e7 00 sw a4, 16(a5) -800008c0: 73 27 50 b0 csrr a4, mhpmcounter5 -800008c4: 23 aa e7 00 sw a4, 20(a5) -800008c8: 73 27 60 b0 csrr a4, mhpmcounter6 -800008cc: 23 ac e7 00 sw a4, 24(a5) -800008d0: 73 27 70 b0 csrr a4, mhpmcounter7 -800008d4: 23 ae e7 00 sw a4, 28(a5) -800008d8: 73 27 80 b0 csrr a4, mhpmcounter8 -800008dc: 23 a0 e7 02 sw a4, 32(a5) -800008e0: 73 27 90 b0 csrr a4, mhpmcounter9 -800008e4: 23 a2 e7 02 sw a4, 36(a5) -800008e8: 73 27 a0 b0 csrr a4, mhpmcounter10 -800008ec: 23 a4 e7 02 sw a4, 40(a5) -800008f0: 73 27 b0 b0 csrr a4, mhpmcounter11 -800008f4: 23 a6 e7 02 sw a4, 44(a5) -800008f8: 73 27 c0 b0 csrr a4, mhpmcounter12 -800008fc: 23 a8 e7 02 sw a4, 48(a5) -80000900: 73 27 d0 b0 csrr a4, mhpmcounter13 -80000904: 23 aa e7 02 sw a4, 52(a5) -80000908: 73 27 e0 b0 csrr a4, mhpmcounter14 -8000090c: 23 ac e7 02 sw a4, 56(a5) -80000910: 73 27 f0 b0 csrr a4, mhpmcounter15 -80000914: 23 ae e7 02 sw a4, 60(a5) -80000918: 73 27 00 b1 csrr a4, mhpmcounter16 -8000091c: 23 a0 e7 04 sw a4, 64(a5) -80000920: 73 27 10 b1 csrr a4, mhpmcounter17 -80000924: 23 a2 e7 04 sw a4, 68(a5) -80000928: 73 27 20 b1 csrr a4, mhpmcounter18 -8000092c: 23 a4 e7 04 sw a4, 72(a5) -80000930: 73 27 30 b1 csrr a4, mhpmcounter19 -80000934: 23 a6 e7 04 sw a4, 76(a5) -80000938: 73 27 40 b1 csrr a4, mhpmcounter20 -8000093c: 23 a8 e7 04 sw a4, 80(a5) -80000940: 73 27 50 b1 csrr a4, mhpmcounter21 -80000944: 23 aa e7 04 sw a4, 84(a5) -80000948: 73 27 60 b1 csrr a4, mhpmcounter22 -8000094c: 23 ac e7 04 sw a4, 88(a5) -80000950: 73 27 70 b1 csrr a4, mhpmcounter23 -80000954: 23 ae e7 04 sw a4, 92(a5) -80000958: 73 27 80 b1 csrr a4, mhpmcounter24 -8000095c: 23 a0 e7 06 sw a4, 96(a5) -80000960: 73 27 90 b1 csrr a4, mhpmcounter25 -80000964: 23 a2 e7 06 sw a4, 100(a5) -80000968: 73 27 a0 b1 csrr a4, mhpmcounter26 -8000096c: 23 a4 e7 06 sw a4, 104(a5) -80000970: 73 27 b0 b1 csrr a4, mhpmcounter27 -80000974: 23 a6 e7 06 sw a4, 108(a5) -80000978: 73 27 c0 b1 csrr a4, mhpmcounter28 -8000097c: 23 a8 e7 06 sw a4, 112(a5) -80000980: 73 27 d0 b1 csrr a4, mhpmcounter29 -80000984: 23 aa e7 06 sw a4, 116(a5) -80000988: 73 27 e0 b1 csrr a4, mhpmcounter30 -8000098c: 23 ac e7 06 sw a4, 120(a5) -80000990: 73 27 f0 b1 csrr a4, mhpmcounter31 -80000994: 23 ae e7 06 sw a4, 124(a5) -80000998: 73 27 00 b8 csrr a4, mcycleh -8000099c: 23 a0 e7 08 sw a4, 128(a5) -800009a0: 73 27 10 b8 csrr a4, 2945 -800009a4: 23 a2 e7 08 sw a4, 132(a5) -800009a8: 73 27 20 b8 csrr a4, minstreth -800009ac: 23 a4 e7 08 sw a4, 136(a5) -800009b0: 73 27 30 b8 csrr a4, mhpmcounter3h -800009b4: 23 a6 e7 08 sw a4, 140(a5) -800009b8: 73 27 40 b8 csrr a4, mhpmcounter4h -800009bc: 23 a8 e7 08 sw a4, 144(a5) -800009c0: 73 27 50 b8 csrr a4, mhpmcounter5h -800009c4: 23 aa e7 08 sw a4, 148(a5) -800009c8: 73 27 60 b8 csrr a4, mhpmcounter6h -800009cc: 23 ac e7 08 sw a4, 152(a5) -800009d0: 73 27 70 b8 csrr a4, mhpmcounter7h -800009d4: 23 ae e7 08 sw a4, 156(a5) -800009d8: 73 27 80 b8 csrr a4, mhpmcounter8h -800009dc: 23 a0 e7 0a sw a4, 160(a5) -800009e0: 73 27 90 b8 csrr a4, mhpmcounter9h -800009e4: 23 a2 e7 0a sw a4, 164(a5) -800009e8: 73 27 a0 b8 csrr a4, mhpmcounter10h -800009ec: 23 a4 e7 0a sw a4, 168(a5) -800009f0: 73 27 b0 b8 csrr a4, mhpmcounter11h -800009f4: 23 a6 e7 0a sw a4, 172(a5) -800009f8: 73 27 c0 b8 csrr a4, mhpmcounter12h -800009fc: 23 a8 e7 0a sw a4, 176(a5) -80000a00: 73 27 d0 b8 csrr a4, mhpmcounter13h -80000a04: 23 aa e7 0a sw a4, 180(a5) -80000a08: 73 27 e0 b8 csrr a4, mhpmcounter14h -80000a0c: 23 ac e7 0a sw a4, 184(a5) -80000a10: 73 27 f0 b8 csrr a4, mhpmcounter15h -80000a14: 23 ae e7 0a sw a4, 188(a5) -80000a18: 73 27 00 b9 csrr a4, mhpmcounter16h -80000a1c: 23 a0 e7 0c sw a4, 192(a5) -80000a20: 73 27 10 b9 csrr a4, mhpmcounter17h -80000a24: 23 a2 e7 0c sw a4, 196(a5) -80000a28: 73 27 20 b9 csrr a4, mhpmcounter18h -80000a2c: 23 a4 e7 0c sw a4, 200(a5) -80000a30: 73 27 30 b9 csrr a4, mhpmcounter19h -80000a34: 23 a6 e7 0c sw a4, 204(a5) -80000a38: 73 27 40 b9 csrr a4, mhpmcounter20h -80000a3c: 23 a8 e7 0c sw a4, 208(a5) -80000a40: 73 27 50 b9 csrr a4, mhpmcounter21h -80000a44: 23 aa e7 0c sw a4, 212(a5) -80000a48: 73 27 60 b9 csrr a4, mhpmcounter22h -80000a4c: 23 ac e7 0c sw a4, 216(a5) -80000a50: 73 27 70 b9 csrr a4, mhpmcounter23h -80000a54: 23 ae e7 0c sw a4, 220(a5) -80000a58: 73 27 80 b9 csrr a4, mhpmcounter24h -80000a5c: 23 a0 e7 0e sw a4, 224(a5) -80000a60: 73 27 90 b9 csrr a4, mhpmcounter25h -80000a64: 23 a2 e7 0e sw a4, 228(a5) -80000a68: 73 27 a0 b9 csrr a4, mhpmcounter26h -80000a6c: 23 a4 e7 0e sw a4, 232(a5) -80000a70: 73 27 b0 b9 csrr a4, mhpmcounter27h -80000a74: 23 a6 e7 0e sw a4, 236(a5) -80000a78: 73 27 c0 b9 csrr a4, mhpmcounter28h -80000a7c: 23 a8 e7 0e sw a4, 240(a5) -80000a80: 73 27 d0 b9 csrr a4, mhpmcounter29h -80000a84: 23 aa e7 0e sw a4, 244(a5) -80000a88: 73 27 e0 b9 csrr a4, mhpmcounter30h -80000a8c: 23 ac e7 0e sw a4, 248(a5) -80000a90: 73 27 f0 b9 csrr a4, mhpmcounter31h -80000a94: 23 ae e7 0e sw a4, 252(a5) -80000a98: 67 80 00 00 ret +800005f0 __libc_fini_array: +800005f0: 13 01 01 ff addi sp, sp, -16 +800005f4: 23 24 81 00 sw s0, 8(sp) +800005f8: b7 17 00 80 lui a5, 524289 +800005fc: 37 14 00 80 lui s0, 524289 +80000600: 13 04 44 00 addi s0, s0, 4 +80000604: 93 87 47 00 addi a5, a5, 4 +80000608: b3 87 87 40 sub a5, a5, s0 +8000060c: 23 22 91 00 sw s1, 4(sp) +80000610: 23 26 11 00 sw ra, 12(sp) +80000614: 93 d4 27 40 srai s1, a5, 2 +80000618: 63 80 04 02 beqz s1, 32 +8000061c: 93 87 c7 ff addi a5, a5, -4 +80000620: 33 84 87 00 add s0, a5, s0 +80000624: 83 27 04 00 lw a5, 0(s0) +80000628: 93 84 f4 ff addi s1, s1, -1 +8000062c: 13 04 c4 ff addi s0, s0, -4 +80000630: e7 80 07 00 jalr a5 +80000634: e3 98 04 fe bnez s1, -16 +80000638: 83 20 c1 00 lw ra, 12(sp) +8000063c: 03 24 81 00 lw s0, 8(sp) +80000640: 83 24 41 00 lw s1, 4(sp) +80000644: 13 01 01 01 addi sp, sp, 16 +80000648: 67 80 00 00 ret -80000a9c atexit: -80000a9c: 93 05 05 00 mv a1, a0 -80000aa0: 93 06 00 00 mv a3, zero -80000aa4: 13 06 00 00 mv a2, zero -80000aa8: 13 05 00 00 mv a0, zero -80000aac: 6f 00 c0 20 j 524 +8000064c spawn_kernel_all_stub: +8000064c: 13 01 01 fe addi sp, sp, -32 +80000650: 23 2e 11 00 sw ra, 28(sp) +80000654: 23 2c 81 00 sw s0, 24(sp) +80000658: 23 2a 91 00 sw s1, 20(sp) +8000065c: 23 28 21 01 sw s2, 16(sp) +80000660: 23 26 31 01 sw s3, 12(sp) +80000664: 23 24 41 01 sw s4, 8(sp) +80000668: 73 26 50 cc csrr a2, 3269 +8000066c: 73 27 30 cc csrr a4, 3267 +80000670: f3 26 00 cc csrr a3, 3264 +80000674: 73 25 00 fc csrr a0, 4032 +80000678: b7 17 00 80 lui a5, 524289 +8000067c: 13 16 26 00 slli a2, a2, 2 +80000680: 93 87 07 44 addi a5, a5, 1088 +80000684: b3 87 c7 00 add a5, a5, a2 +80000688: 03 a4 07 00 lw s0, 0(a5) +8000068c: 83 24 44 01 lw s1, 20(s0) +80000690: 03 26 04 01 lw a2, 16(s0) +80000694: 33 2a 97 00 slt s4, a4, s1 +80000698: 93 87 04 00 mv a5, s1 +8000069c: 33 0a ca 00 add s4, s4, a2 +800006a0: b3 04 e6 02 mul s1, a2, a4 +800006a4: 63 54 f7 00 bge a4, a5, 8 +800006a8: 93 07 07 00 mv a5, a4 +800006ac: b3 84 f4 00 add s1, s1, a5 +800006b0: 83 25 04 00 lw a1, 0(s0) +800006b4: 03 27 c4 00 lw a4, 12(s0) +800006b8: 03 a9 05 00 lw s2, 0(a1) +800006bc: 83 a9 45 00 lw s3, 4(a1) +800006c0: b3 84 a4 02 mul s1, s1, a0 +800006c4: b3 07 da 02 mul a5, s4, a3 +800006c8: b3 84 e4 00 add s1, s1, a4 +800006cc: b3 84 f4 00 add s1, s1, a5 +800006d0: 33 0a 9a 00 add s4, s4, s1 +800006d4: b3 09 39 03 mul s3, s2, s3 +800006d8: 63 c0 44 07 blt s1, s4, 96 +800006dc: 6f 00 00 08 j 128 +800006e0: 03 47 e4 01 lbu a4, 30(s0) +800006e4: 83 46 d4 01 lbu a3, 29(s0) +800006e8: 33 d7 e4 40 sra a4, s1, a4 +800006ec: b3 07 37 03 mul a5, a4, s3 +800006f0: b3 87 f4 40 sub a5, s1, a5 +800006f4: 63 80 06 06 beqz a3, 96 +800006f8: 83 46 f4 01 lbu a3, 31(s0) +800006fc: b3 d6 d7 40 sra a3, a5, a3 +80000700: b3 88 26 03 mul a7, a3, s2 +80000704: 03 ae 45 01 lw t3, 20(a1) +80000708: 03 a3 05 01 lw t1, 16(a1) +8000070c: 03 a6 c5 00 lw a2, 12(a1) +80000710: 03 28 44 00 lw a6, 4(s0) +80000714: 03 25 84 00 lw a0, 8(s0) +80000718: 93 84 14 00 addi s1, s1, 1 +8000071c: 33 07 c7 01 add a4, a4, t3 +80000720: b3 86 66 00 add a3, a3, t1 +80000724: b3 87 17 41 sub a5, a5, a7 +80000728: 33 86 c7 00 add a2, a5, a2 +8000072c: e7 00 08 00 jalr a6 +80000730: 63 06 9a 02 beq s4, s1, 44 +80000734: 83 25 04 00 lw a1, 0(s0) +80000738: 83 47 c4 01 lbu a5, 28(s0) +8000073c: e3 92 07 fa bnez a5, -92 +80000740: 33 c7 34 03 div a4, s1, s3 +80000744: 83 46 d4 01 lbu a3, 29(s0) +80000748: b3 07 37 03 mul a5, a4, s3 +8000074c: b3 87 f4 40 sub a5, s1, a5 +80000750: e3 94 06 fa bnez a3, -88 +80000754: b3 c6 27 03 div a3, a5, s2 +80000758: 6f f0 9f fa j -88 +8000075c: 03 27 84 01 lw a4, 24(s0) +80000760: 93 07 00 00 mv a5, zero +80000764: 6b c0 e7 00 vx_bar a5, a4 +80000768: 83 20 c1 01 lw ra, 28(sp) +8000076c: 03 24 81 01 lw s0, 24(sp) +80000770: 83 24 41 01 lw s1, 20(sp) +80000774: 03 29 01 01 lw s2, 16(sp) +80000778: 83 29 c1 00 lw s3, 12(sp) +8000077c: 03 2a 81 00 lw s4, 8(sp) +80000780: 13 01 01 02 addi sp, sp, 32 +80000784: 67 80 00 00 ret -80000ab0 exit: -80000ab0: 13 01 01 ff addi sp, sp, -16 -80000ab4: 93 05 00 00 mv a1, zero -80000ab8: 23 24 81 00 sw s0, 8(sp) -80000abc: 23 26 11 00 sw ra, 12(sp) -80000ac0: 13 04 05 00 mv s0, a0 -80000ac4: ef 00 00 29 jal 656 -80000ac8: b7 17 00 80 lui a5, 524289 -80000acc: 03 a5 07 43 lw a0, 1072(a5) -80000ad0: 83 27 c5 03 lw a5, 60(a0) -80000ad4: 63 84 07 00 beqz a5, 8 -80000ad8: e7 80 07 00 jalr a5 -80000adc: 13 05 04 00 mv a0, s0 -80000ae0: ef f0 df 9e jal -1556 +80000788 spawn_kernel_rem_stub: +80000788: f3 26 50 cc csrr a3, 3269 +8000078c: f3 27 20 cc csrr a5, 3266 +80000790: 37 17 00 80 lui a4, 524289 +80000794: 93 96 26 00 slli a3, a3, 2 +80000798: 13 07 07 44 addi a4, a4, 1088 +8000079c: 33 07 d7 00 add a4, a4, a3 +800007a0: 03 25 07 00 lw a0, 0(a4) +800007a4: 83 25 05 00 lw a1, 0(a0) +800007a8: 83 26 c5 00 lw a3, 12(a0) +800007ac: 03 47 c5 01 lbu a4, 28(a0) +800007b0: 83 a8 05 00 lw a7, 0(a1) +800007b4: 03 a6 45 00 lw a2, 4(a1) +800007b8: b3 87 d7 00 add a5, a5, a3 +800007bc: 33 86 c8 02 mul a2, a7, a2 +800007c0: 63 08 07 04 beqz a4, 80 +800007c4: 03 47 e5 01 lbu a4, 30(a0) +800007c8: 83 46 d5 01 lbu a3, 29(a0) +800007cc: 33 d7 e7 40 sra a4, a5, a4 +800007d0: 33 06 c7 02 mul a2, a4, a2 +800007d4: b3 87 c7 40 sub a5, a5, a2 +800007d8: 63 86 06 04 beqz a3, 76 +800007dc: 83 46 f5 01 lbu a3, 31(a0) +800007e0: 33 d8 d7 40 sra a6, a5, a3 +800007e4: 83 a6 05 01 lw a3, 16(a1) +800007e8: 03 ae 45 01 lw t3, 20(a1) +800007ec: 03 a6 c5 00 lw a2, 12(a1) +800007f0: b3 06 d8 00 add a3, a6, a3 +800007f4: 33 08 18 03 mul a6, a6, a7 +800007f8: 03 23 45 00 lw t1, 4(a0) +800007fc: 03 25 85 00 lw a0, 8(a0) +80000800: 33 07 c7 01 add a4, a4, t3 +80000804: b3 87 07 41 sub a5, a5, a6 +80000808: 33 86 c7 00 add a2, a5, a2 +8000080c: 67 00 03 00 jr t1 +80000810: 33 c7 c7 02 div a4, a5, a2 +80000814: 83 46 d5 01 lbu a3, 29(a0) +80000818: 33 06 c7 02 mul a2, a4, a2 +8000081c: b3 87 c7 40 sub a5, a5, a2 +80000820: e3 9e 06 fa bnez a3, -68 +80000824: 33 c8 17 03 div a6, a5, a7 +80000828: 6f f0 df fb j -68 -80000ae4 __libc_fini_array: -80000ae4: 13 01 01 ff addi sp, sp, -16 -80000ae8: 23 24 81 00 sw s0, 8(sp) -80000aec: b7 17 00 80 lui a5, 524289 -80000af0: 37 14 00 80 lui s0, 524289 -80000af4: 13 04 44 00 addi s0, s0, 4 -80000af8: 93 87 47 00 addi a5, a5, 4 -80000afc: b3 87 87 40 sub a5, a5, s0 -80000b00: 23 22 91 00 sw s1, 4(sp) -80000b04: 23 26 11 00 sw ra, 12(sp) -80000b08: 93 d4 27 40 srai s1, a5, 2 -80000b0c: 63 80 04 02 beqz s1, 32 -80000b10: 93 87 c7 ff addi a5, a5, -4 -80000b14: 33 84 87 00 add s0, a5, s0 -80000b18: 83 27 04 00 lw a5, 0(s0) -80000b1c: 93 84 f4 ff addi s1, s1, -1 -80000b20: 13 04 c4 ff addi s0, s0, -4 -80000b24: e7 80 07 00 jalr a5 -80000b28: e3 98 04 fe bnez s1, -16 -80000b2c: 83 20 c1 00 lw ra, 12(sp) -80000b30: 03 24 81 00 lw s0, 8(sp) -80000b34: 83 24 41 00 lw s1, 4(sp) -80000b38: 13 01 01 01 addi sp, sp, 16 -80000b3c: 67 80 00 00 ret +8000082c spawn_kernel_all_cb: +8000082c: 13 01 01 ff addi sp, sp, -16 +80000830: 23 26 11 00 sw ra, 12(sp) +80000834: 93 07 f0 ff addi a5, zero, -1 +80000838: 6b 80 07 00 vx_tmc a5 +8000083c: ef f0 1f e1 jal -496 +80000840: f3 27 30 cc csrr a5, 3267 +80000844: 93 b7 17 00 seqz a5, a5 +80000848: 6b 80 07 00 vx_tmc a5 +8000084c: 83 20 c1 00 lw ra, 12(sp) +80000850: 13 01 01 01 addi sp, sp, 16 +80000854: 67 80 00 00 ret -80000b40 __libc_init_array: -80000b40: 13 01 01 ff addi sp, sp, -16 -80000b44: 23 24 81 00 sw s0, 8(sp) -80000b48: 23 20 21 01 sw s2, 0(sp) -80000b4c: 37 14 00 80 lui s0, 524289 -80000b50: 37 19 00 80 lui s2, 524289 -80000b54: 93 07 04 00 mv a5, s0 -80000b58: 13 09 09 00 mv s2, s2 -80000b5c: 33 09 f9 40 sub s2, s2, a5 -80000b60: 23 26 11 00 sw ra, 12(sp) -80000b64: 23 22 91 00 sw s1, 4(sp) -80000b68: 13 59 29 40 srai s2, s2, 2 -80000b6c: 63 00 09 02 beqz s2, 32 -80000b70: 13 04 04 00 mv s0, s0 -80000b74: 93 04 00 00 mv s1, zero -80000b78: 83 27 04 00 lw a5, 0(s0) -80000b7c: 93 84 14 00 addi s1, s1, 1 -80000b80: 13 04 44 00 addi s0, s0, 4 -80000b84: e7 80 07 00 jalr a5 -80000b88: e3 18 99 fe bne s2, s1, -16 -80000b8c: 37 14 00 80 lui s0, 524289 -80000b90: 37 19 00 80 lui s2, 524289 -80000b94: 93 07 04 00 mv a5, s0 -80000b98: 13 09 49 00 addi s2, s2, 4 -80000b9c: 33 09 f9 40 sub s2, s2, a5 -80000ba0: 13 59 29 40 srai s2, s2, 2 -80000ba4: 63 00 09 02 beqz s2, 32 -80000ba8: 13 04 04 00 mv s0, s0 -80000bac: 93 04 00 00 mv s1, zero -80000bb0: 83 27 04 00 lw a5, 0(s0) -80000bb4: 93 84 14 00 addi s1, s1, 1 -80000bb8: 13 04 44 00 addi s0, s0, 4 -80000bbc: e7 80 07 00 jalr a5 -80000bc0: e3 18 99 fe bne s2, s1, -16 -80000bc4: 83 20 c1 00 lw ra, 12(sp) -80000bc8: 03 24 81 00 lw s0, 8(sp) -80000bcc: 83 24 41 00 lw s1, 4(sp) -80000bd0: 03 29 01 00 lw s2, 0(sp) -80000bd4: 13 01 01 01 addi sp, sp, 16 -80000bd8: 67 80 00 00 ret +80000858 vx_spawn_kernel: +80000858: 13 01 01 fd addi sp, sp, -48 +8000085c: 23 26 11 02 sw ra, 44(sp) +80000860: 23 24 81 02 sw s0, 40(sp) +80000864: 23 22 91 02 sw s1, 36(sp) +80000868: 23 20 21 03 sw s2, 32(sp) +8000086c: f3 28 20 fc csrr a7, 4034 +80000870: 73 23 10 fc csrr t1, 4033 +80000874: f3 24 00 fc csrr s1, 4032 +80000878: f3 27 50 cc csrr a5, 3269 +8000087c: 13 07 f0 01 addi a4, zero, 31 +80000880: 63 46 f7 0e blt a4, a5, 236 +80000884: 03 2e 05 00 lw t3, 0(a0) +80000888: 83 26 45 00 lw a3, 4(a0) +8000088c: 03 28 85 00 lw a6, 8(a0) +80000890: b3 0e 93 02 mul t4, t1, s1 +80000894: 13 07 10 00 addi a4, zero, 1 +80000898: b3 06 de 02 mul a3, t3, a3 +8000089c: 33 88 06 03 mul a6, a3, a6 +800008a0: 63 d4 0e 01 bge t4, a6, 8 +800008a4: 33 47 d8 03 div a4, a6, t4 +800008a8: 63 ce e8 0c blt a7, a4, 220 +800008ac: 63 d0 e7 0c bge a5, a4, 192 +800008b0: 93 88 f8 ff addi a7, a7, -1 +800008b4: b3 4e e8 02 div t4, a6, a4 +800008b8: 13 84 0e 00 mv s0, t4 +800008bc: 63 96 f8 00 bne a7, a5, 12 +800008c0: 33 67 e8 02 rem a4, a6, a4 +800008c4: 33 04 d7 01 add s0, a4, t4 +800008c8: 33 49 94 02 div s2, s0, s1 +800008cc: 33 64 94 02 rem s0, s0, s1 +800008d0: 63 40 69 0c blt s2, t1, 192 +800008d4: 93 0f 10 00 addi t6, zero, 1 +800008d8: 33 4f 69 02 div t5, s2, t1 +800008dc: 63 06 0f 00 beqz t5, 12 +800008e0: 93 0f 0f 00 mv t6, t5 +800008e4: 33 6f 69 02 rem t5, s2, t1 +800008e8: d3 f7 06 d0 fcvt.s.w fa5, a3 +800008ec: 13 07 fe ff addi a4, t3, -1 +800008f0: 93 82 f6 ff addi t0, a3, -1 +800008f4: d3 88 07 e0 fmv.x.w a7, fa5 +800008f8: d3 77 0e d0 fcvt.s.w fa5, t3 +800008fc: 33 7e c7 01 and t3, a4, t3 +80000900: 37 17 00 80 lui a4, 524289 +80000904: 53 88 07 e0 fmv.x.w a6, fa5 +80000908: b3 f6 d2 00 and a3, t0, a3 +8000090c: 93 d8 78 41 srai a7, a7, 23 +80000910: 13 58 78 41 srai a6, a6, 23 +80000914: 13 07 07 44 addi a4, a4, 1088 +80000918: 93 b6 16 00 seqz a3, a3 +8000091c: 13 3e 1e 00 seqz t3, t3 +80000920: 93 88 18 f8 addi a7, a7, -127 +80000924: 13 08 18 f8 addi a6, a6, -127 +80000928: 23 20 a1 00 sw a0, 0(sp) +8000092c: 23 22 b1 00 sw a1, 4(sp) +80000930: 23 24 c1 00 sw a2, 8(sp) +80000934: 23 28 f1 01 sw t6, 16(sp) +80000938: 23 2a e1 01 sw t5, 20(sp) +8000093c: 23 2c 01 00 sw zero, 24(sp) +80000940: 23 0e d1 00 sb a3, 28(sp) +80000944: a3 0e c1 01 sb t3, 29(sp) +80000948: 23 0f 11 01 sb a7, 30(sp) +8000094c: a3 0f 01 01 sb a6, 31(sp) +80000950: b3 8e fe 02 mul t4, t4, a5 +80000954: 93 97 27 00 slli a5, a5, 2 +80000958: b3 07 f7 00 add a5, a4, a5 +8000095c: 23 a0 27 00 sw sp, 0(a5) +80000960: 23 26 d1 01 sw t4, 12(sp) +80000964: 63 4c 20 03 bgtz s2, 56 +80000968: 63 16 04 06 bnez s0, 108 +8000096c: 83 20 c1 02 lw ra, 44(sp) +80000970: 03 24 81 02 lw s0, 40(sp) +80000974: 83 24 41 02 lw s1, 36(sp) +80000978: 03 29 01 02 lw s2, 32(sp) +8000097c: 13 01 01 03 addi sp, sp, 48 +80000980: 67 80 00 00 ret +80000984: 13 87 08 00 mv a4, a7 +80000988: e3 c4 e7 f2 blt a5, a4, -216 +8000098c: 6f f0 1f fe j -32 +80000990: 13 0f 00 00 mv t5, zero +80000994: 93 0f 10 00 addi t6, zero, 1 +80000998: 6f f0 1f f5 j -176 +8000099c: 13 07 09 00 mv a4, s2 +800009a0: 63 54 23 01 bge t1, s2, 8 +800009a4: 13 07 03 00 mv a4, t1 +800009a8: b7 17 00 80 lui a5, 524289 +800009ac: 23 2c e1 00 sw a4, 24(sp) +800009b0: 93 87 c7 82 addi a5, a5, -2004 +800009b4: 6b 10 f7 00 vx_wspawn a4, a5 +800009b8: 93 07 f0 ff addi a5, zero, -1 +800009bc: 6b 80 07 00 vx_tmc a5 +800009c0: ef f0 df c8 jal -884 +800009c4: f3 27 30 cc csrr a5, 3267 +800009c8: 93 b7 17 00 seqz a5, a5 +800009cc: 6b 80 07 00 vx_tmc a5 +800009d0: e3 0e 04 f8 beqz s0, -100 +800009d4: b3 04 99 02 mul s1, s2, s1 +800009d8: 13 09 10 00 addi s2, zero, 1 +800009dc: 33 14 89 00 sll s0, s2, s0 +800009e0: 13 04 f4 ff addi s0, s0, -1 +800009e4: 23 26 91 00 sw s1, 12(sp) +800009e8: 6b 00 04 00 vx_tmc s0 +800009ec: ef f0 df d9 jal -612 +800009f0: 6b 00 09 00 vx_tmc s2 +800009f4: 83 20 c1 02 lw ra, 44(sp) +800009f8: 03 24 81 02 lw s0, 40(sp) +800009fc: 83 24 41 02 lw s1, 36(sp) +80000a00: 03 29 01 02 lw s2, 32(sp) +80000a04: 13 01 01 03 addi sp, sp, 48 +80000a08: 67 80 00 00 ret -80000bdc memset: -80000bdc: 13 03 f0 00 addi t1, zero, 15 -80000be0: 13 07 05 00 mv a4, a0 -80000be4: 63 7e c3 02 bgeu t1, a2, 60 -80000be8: 93 77 f7 00 andi a5, a4, 15 -80000bec: 63 90 07 0a bnez a5, 160 -80000bf0: 63 92 05 08 bnez a1, 132 -80000bf4: 93 76 06 ff andi a3, a2, -16 -80000bf8: 13 76 f6 00 andi a2, a2, 15 -80000bfc: b3 86 e6 00 add a3, a3, a4 -80000c00: 23 20 b7 00 sw a1, 0(a4) -80000c04: 23 22 b7 00 sw a1, 4(a4) -80000c08: 23 24 b7 00 sw a1, 8(a4) -80000c0c: 23 26 b7 00 sw a1, 12(a4) -80000c10: 13 07 07 01 addi a4, a4, 16 -80000c14: e3 66 d7 fe bltu a4, a3, -20 -80000c18: 63 14 06 00 bnez a2, 8 +80000a0c vx_perf_dump: +80000a0c: f3 27 50 cc csrr a5, 3269 +80000a10: 37 07 ff 00 lui a4, 4080 +80000a14: b3 87 e7 00 add a5, a5, a4 +80000a18: 93 97 87 00 slli a5, a5, 8 +80000a1c: 73 27 00 b0 csrr a4, mcycle +80000a20: 23 a0 e7 00 sw a4, 0(a5) +80000a24: 73 27 10 b0 csrr a4, 2817 +80000a28: 23 a2 e7 00 sw a4, 4(a5) +80000a2c: 73 27 20 b0 csrr a4, minstret +80000a30: 23 a4 e7 00 sw a4, 8(a5) +80000a34: 73 27 30 b0 csrr a4, mhpmcounter3 +80000a38: 23 a6 e7 00 sw a4, 12(a5) +80000a3c: 73 27 40 b0 csrr a4, mhpmcounter4 +80000a40: 23 a8 e7 00 sw a4, 16(a5) +80000a44: 73 27 50 b0 csrr a4, mhpmcounter5 +80000a48: 23 aa e7 00 sw a4, 20(a5) +80000a4c: 73 27 60 b0 csrr a4, mhpmcounter6 +80000a50: 23 ac e7 00 sw a4, 24(a5) +80000a54: 73 27 70 b0 csrr a4, mhpmcounter7 +80000a58: 23 ae e7 00 sw a4, 28(a5) +80000a5c: 73 27 80 b0 csrr a4, mhpmcounter8 +80000a60: 23 a0 e7 02 sw a4, 32(a5) +80000a64: 73 27 90 b0 csrr a4, mhpmcounter9 +80000a68: 23 a2 e7 02 sw a4, 36(a5) +80000a6c: 73 27 a0 b0 csrr a4, mhpmcounter10 +80000a70: 23 a4 e7 02 sw a4, 40(a5) +80000a74: 73 27 b0 b0 csrr a4, mhpmcounter11 +80000a78: 23 a6 e7 02 sw a4, 44(a5) +80000a7c: 73 27 c0 b0 csrr a4, mhpmcounter12 +80000a80: 23 a8 e7 02 sw a4, 48(a5) +80000a84: 73 27 d0 b0 csrr a4, mhpmcounter13 +80000a88: 23 aa e7 02 sw a4, 52(a5) +80000a8c: 73 27 e0 b0 csrr a4, mhpmcounter14 +80000a90: 23 ac e7 02 sw a4, 56(a5) +80000a94: 73 27 f0 b0 csrr a4, mhpmcounter15 +80000a98: 23 ae e7 02 sw a4, 60(a5) +80000a9c: 73 27 00 b1 csrr a4, mhpmcounter16 +80000aa0: 23 a0 e7 04 sw a4, 64(a5) +80000aa4: 73 27 10 b1 csrr a4, mhpmcounter17 +80000aa8: 23 a2 e7 04 sw a4, 68(a5) +80000aac: 73 27 20 b1 csrr a4, mhpmcounter18 +80000ab0: 23 a4 e7 04 sw a4, 72(a5) +80000ab4: 73 27 30 b1 csrr a4, mhpmcounter19 +80000ab8: 23 a6 e7 04 sw a4, 76(a5) +80000abc: 73 27 40 b1 csrr a4, mhpmcounter20 +80000ac0: 23 a8 e7 04 sw a4, 80(a5) +80000ac4: 73 27 50 b1 csrr a4, mhpmcounter21 +80000ac8: 23 aa e7 04 sw a4, 84(a5) +80000acc: 73 27 60 b1 csrr a4, mhpmcounter22 +80000ad0: 23 ac e7 04 sw a4, 88(a5) +80000ad4: 73 27 70 b1 csrr a4, mhpmcounter23 +80000ad8: 23 ae e7 04 sw a4, 92(a5) +80000adc: 73 27 80 b1 csrr a4, mhpmcounter24 +80000ae0: 23 a0 e7 06 sw a4, 96(a5) +80000ae4: 73 27 90 b1 csrr a4, mhpmcounter25 +80000ae8: 23 a2 e7 06 sw a4, 100(a5) +80000aec: 73 27 a0 b1 csrr a4, mhpmcounter26 +80000af0: 23 a4 e7 06 sw a4, 104(a5) +80000af4: 73 27 b0 b1 csrr a4, mhpmcounter27 +80000af8: 23 a6 e7 06 sw a4, 108(a5) +80000afc: 73 27 c0 b1 csrr a4, mhpmcounter28 +80000b00: 23 a8 e7 06 sw a4, 112(a5) +80000b04: 73 27 d0 b1 csrr a4, mhpmcounter29 +80000b08: 23 aa e7 06 sw a4, 116(a5) +80000b0c: 73 27 e0 b1 csrr a4, mhpmcounter30 +80000b10: 23 ac e7 06 sw a4, 120(a5) +80000b14: 73 27 f0 b1 csrr a4, mhpmcounter31 +80000b18: 23 ae e7 06 sw a4, 124(a5) +80000b1c: 73 27 00 b8 csrr a4, mcycleh +80000b20: 23 a0 e7 08 sw a4, 128(a5) +80000b24: 73 27 10 b8 csrr a4, 2945 +80000b28: 23 a2 e7 08 sw a4, 132(a5) +80000b2c: 73 27 20 b8 csrr a4, minstreth +80000b30: 23 a4 e7 08 sw a4, 136(a5) +80000b34: 73 27 30 b8 csrr a4, mhpmcounter3h +80000b38: 23 a6 e7 08 sw a4, 140(a5) +80000b3c: 73 27 40 b8 csrr a4, mhpmcounter4h +80000b40: 23 a8 e7 08 sw a4, 144(a5) +80000b44: 73 27 50 b8 csrr a4, mhpmcounter5h +80000b48: 23 aa e7 08 sw a4, 148(a5) +80000b4c: 73 27 60 b8 csrr a4, mhpmcounter6h +80000b50: 23 ac e7 08 sw a4, 152(a5) +80000b54: 73 27 70 b8 csrr a4, mhpmcounter7h +80000b58: 23 ae e7 08 sw a4, 156(a5) +80000b5c: 73 27 80 b8 csrr a4, mhpmcounter8h +80000b60: 23 a0 e7 0a sw a4, 160(a5) +80000b64: 73 27 90 b8 csrr a4, mhpmcounter9h +80000b68: 23 a2 e7 0a sw a4, 164(a5) +80000b6c: 73 27 a0 b8 csrr a4, mhpmcounter10h +80000b70: 23 a4 e7 0a sw a4, 168(a5) +80000b74: 73 27 b0 b8 csrr a4, mhpmcounter11h +80000b78: 23 a6 e7 0a sw a4, 172(a5) +80000b7c: 73 27 c0 b8 csrr a4, mhpmcounter12h +80000b80: 23 a8 e7 0a sw a4, 176(a5) +80000b84: 73 27 d0 b8 csrr a4, mhpmcounter13h +80000b88: 23 aa e7 0a sw a4, 180(a5) +80000b8c: 73 27 e0 b8 csrr a4, mhpmcounter14h +80000b90: 23 ac e7 0a sw a4, 184(a5) +80000b94: 73 27 f0 b8 csrr a4, mhpmcounter15h +80000b98: 23 ae e7 0a sw a4, 188(a5) +80000b9c: 73 27 00 b9 csrr a4, mhpmcounter16h +80000ba0: 23 a0 e7 0c sw a4, 192(a5) +80000ba4: 73 27 10 b9 csrr a4, mhpmcounter17h +80000ba8: 23 a2 e7 0c sw a4, 196(a5) +80000bac: 73 27 20 b9 csrr a4, mhpmcounter18h +80000bb0: 23 a4 e7 0c sw a4, 200(a5) +80000bb4: 73 27 30 b9 csrr a4, mhpmcounter19h +80000bb8: 23 a6 e7 0c sw a4, 204(a5) +80000bbc: 73 27 40 b9 csrr a4, mhpmcounter20h +80000bc0: 23 a8 e7 0c sw a4, 208(a5) +80000bc4: 73 27 50 b9 csrr a4, mhpmcounter21h +80000bc8: 23 aa e7 0c sw a4, 212(a5) +80000bcc: 73 27 60 b9 csrr a4, mhpmcounter22h +80000bd0: 23 ac e7 0c sw a4, 216(a5) +80000bd4: 73 27 70 b9 csrr a4, mhpmcounter23h +80000bd8: 23 ae e7 0c sw a4, 220(a5) +80000bdc: 73 27 80 b9 csrr a4, mhpmcounter24h +80000be0: 23 a0 e7 0e sw a4, 224(a5) +80000be4: 73 27 90 b9 csrr a4, mhpmcounter25h +80000be8: 23 a2 e7 0e sw a4, 228(a5) +80000bec: 73 27 a0 b9 csrr a4, mhpmcounter26h +80000bf0: 23 a4 e7 0e sw a4, 232(a5) +80000bf4: 73 27 b0 b9 csrr a4, mhpmcounter27h +80000bf8: 23 a6 e7 0e sw a4, 236(a5) +80000bfc: 73 27 c0 b9 csrr a4, mhpmcounter28h +80000c00: 23 a8 e7 0e sw a4, 240(a5) +80000c04: 73 27 d0 b9 csrr a4, mhpmcounter29h +80000c08: 23 aa e7 0e sw a4, 244(a5) +80000c0c: 73 27 e0 b9 csrr a4, mhpmcounter30h +80000c10: 23 ac e7 0e sw a4, 248(a5) +80000c14: 73 27 f0 b9 csrr a4, mhpmcounter31h +80000c18: 23 ae e7 0e sw a4, 252(a5) 80000c1c: 67 80 00 00 ret -80000c20: b3 06 c3 40 sub a3, t1, a2 -80000c24: 93 96 26 00 slli a3, a3, 2 -80000c28: 97 02 00 00 auipc t0, 0 -80000c2c: b3 86 56 00 add a3, a3, t0 -80000c30: 67 80 c6 00 jr 12(a3) -80000c34: 23 07 b7 00 sb a1, 14(a4) -80000c38: a3 06 b7 00 sb a1, 13(a4) -80000c3c: 23 06 b7 00 sb a1, 12(a4) -80000c40: a3 05 b7 00 sb a1, 11(a4) -80000c44: 23 05 b7 00 sb a1, 10(a4) -80000c48: a3 04 b7 00 sb a1, 9(a4) -80000c4c: 23 04 b7 00 sb a1, 8(a4) -80000c50: a3 03 b7 00 sb a1, 7(a4) -80000c54: 23 03 b7 00 sb a1, 6(a4) -80000c58: a3 02 b7 00 sb a1, 5(a4) -80000c5c: 23 02 b7 00 sb a1, 4(a4) -80000c60: a3 01 b7 00 sb a1, 3(a4) -80000c64: 23 01 b7 00 sb a1, 2(a4) -80000c68: a3 00 b7 00 sb a1, 1(a4) -80000c6c: 23 00 b7 00 sb a1, 0(a4) -80000c70: 67 80 00 00 ret -80000c74: 93 f5 f5 0f andi a1, a1, 255 -80000c78: 93 96 85 00 slli a3, a1, 8 -80000c7c: b3 e5 d5 00 or a1, a1, a3 -80000c80: 93 96 05 01 slli a3, a1, 16 -80000c84: b3 e5 d5 00 or a1, a1, a3 -80000c88: 6f f0 df f6 j -148 -80000c8c: 93 96 27 00 slli a3, a5, 2 -80000c90: 97 02 00 00 auipc t0, 0 -80000c94: b3 86 56 00 add a3, a3, t0 -80000c98: 93 82 00 00 mv t0, ra -80000c9c: e7 80 06 fa jalr -96(a3) -80000ca0: 93 80 02 00 mv ra, t0 -80000ca4: 93 87 07 ff addi a5, a5, -16 -80000ca8: 33 07 f7 40 sub a4, a4, a5 -80000cac: 33 06 f6 00 add a2, a2, a5 -80000cb0: e3 78 c3 f6 bgeu t1, a2, -144 -80000cb4: 6f f0 df f3 j -196 -80000cb8 __register_exitproc: -80000cb8: b7 17 00 80 lui a5, 524289 -80000cbc: 03 a7 07 43 lw a4, 1072(a5) -80000cc0: 83 27 87 14 lw a5, 328(a4) -80000cc4: 63 8c 07 04 beqz a5, 88 -80000cc8: 03 a7 47 00 lw a4, 4(a5) -80000ccc: 13 08 f0 01 addi a6, zero, 31 -80000cd0: 63 4e e8 06 blt a6, a4, 124 -80000cd4: 13 18 27 00 slli a6, a4, 2 -80000cd8: 63 06 05 02 beqz a0, 44 -80000cdc: 33 83 07 01 add t1, a5, a6 -80000ce0: 23 24 c3 08 sw a2, 136(t1) -80000ce4: 83 a8 87 18 lw a7, 392(a5) -80000ce8: 13 06 10 00 addi a2, zero, 1 -80000cec: 33 16 e6 00 sll a2, a2, a4 -80000cf0: b3 e8 c8 00 or a7, a7, a2 -80000cf4: 23 a4 17 19 sw a7, 392(a5) -80000cf8: 23 24 d3 10 sw a3, 264(t1) -80000cfc: 93 06 20 00 addi a3, zero, 2 -80000d00: 63 04 d5 02 beq a0, a3, 40 -80000d04: 13 07 17 00 addi a4, a4, 1 -80000d08: 23 a2 e7 00 sw a4, 4(a5) -80000d0c: b3 87 07 01 add a5, a5, a6 -80000d10: 23 a4 b7 00 sw a1, 8(a5) -80000d14: 13 05 00 00 mv a0, zero -80000d18: 67 80 00 00 ret -80000d1c: 93 07 c7 14 addi a5, a4, 332 -80000d20: 23 24 f7 14 sw a5, 328(a4) -80000d24: 6f f0 5f fa j -92 -80000d28: 83 a6 c7 18 lw a3, 396(a5) -80000d2c: 13 07 17 00 addi a4, a4, 1 -80000d30: 23 a2 e7 00 sw a4, 4(a5) -80000d34: 33 e6 c6 00 or a2, a3, a2 -80000d38: 23 a6 c7 18 sw a2, 396(a5) -80000d3c: b3 87 07 01 add a5, a5, a6 -80000d40: 23 a4 b7 00 sw a1, 8(a5) -80000d44: 13 05 00 00 mv a0, zero -80000d48: 67 80 00 00 ret -80000d4c: 13 05 f0 ff addi a0, zero, -1 -80000d50: 67 80 00 00 ret +80000c20 atexit: +80000c20: 93 05 05 00 mv a1, a0 +80000c24: 93 06 00 00 mv a3, zero +80000c28: 13 06 00 00 mv a2, zero +80000c2c: 13 05 00 00 mv a0, zero +80000c30: 6f 00 40 11 j 276 -80000d54 __call_exitprocs: -80000d54: 13 01 01 fd addi sp, sp, -48 -80000d58: b7 17 00 80 lui a5, 524289 -80000d5c: 23 2c 41 01 sw s4, 24(sp) -80000d60: 03 aa 07 43 lw s4, 1072(a5) -80000d64: 23 20 21 03 sw s2, 32(sp) -80000d68: 23 26 11 02 sw ra, 44(sp) -80000d6c: 03 29 8a 14 lw s2, 328(s4) -80000d70: 23 24 81 02 sw s0, 40(sp) -80000d74: 23 22 91 02 sw s1, 36(sp) -80000d78: 23 2e 31 01 sw s3, 28(sp) -80000d7c: 23 2a 51 01 sw s5, 20(sp) -80000d80: 23 28 61 01 sw s6, 16(sp) -80000d84: 23 26 71 01 sw s7, 12(sp) -80000d88: 23 24 81 01 sw s8, 8(sp) -80000d8c: 63 00 09 04 beqz s2, 64 -80000d90: 13 0b 05 00 mv s6, a0 -80000d94: 93 8b 05 00 mv s7, a1 -80000d98: 93 0a 10 00 addi s5, zero, 1 -80000d9c: 93 09 f0 ff addi s3, zero, -1 -80000da0: 83 24 49 00 lw s1, 4(s2) -80000da4: 13 84 f4 ff addi s0, s1, -1 -80000da8: 63 42 04 02 bltz s0, 36 -80000dac: 93 94 24 00 slli s1, s1, 2 -80000db0: b3 04 99 00 add s1, s2, s1 -80000db4: 63 84 0b 04 beqz s7, 72 -80000db8: 83 a7 44 10 lw a5, 260(s1) -80000dbc: 63 80 77 05 beq a5, s7, 64 -80000dc0: 13 04 f4 ff addi s0, s0, -1 -80000dc4: 93 84 c4 ff addi s1, s1, -4 -80000dc8: e3 16 34 ff bne s0, s3, -20 -80000dcc: 83 20 c1 02 lw ra, 44(sp) -80000dd0: 03 24 81 02 lw s0, 40(sp) -80000dd4: 83 24 41 02 lw s1, 36(sp) -80000dd8: 03 29 01 02 lw s2, 32(sp) -80000ddc: 83 29 c1 01 lw s3, 28(sp) -80000de0: 03 2a 81 01 lw s4, 24(sp) -80000de4: 83 2a 41 01 lw s5, 20(sp) -80000de8: 03 2b 01 01 lw s6, 16(sp) -80000dec: 83 2b c1 00 lw s7, 12(sp) -80000df0: 03 2c 81 00 lw s8, 8(sp) -80000df4: 13 01 01 03 addi sp, sp, 48 -80000df8: 67 80 00 00 ret -80000dfc: 83 27 49 00 lw a5, 4(s2) -80000e00: 83 a6 44 00 lw a3, 4(s1) -80000e04: 93 87 f7 ff addi a5, a5, -1 -80000e08: 63 8e 87 04 beq a5, s0, 92 -80000e0c: 23 a2 04 00 sw zero, 4(s1) -80000e10: e3 88 06 fa beqz a3, -80 -80000e14: 83 27 89 18 lw a5, 392(s2) -80000e18: 33 97 8a 00 sll a4, s5, s0 -80000e1c: 03 2c 49 00 lw s8, 4(s2) -80000e20: b3 77 f7 00 and a5, a4, a5 -80000e24: 63 92 07 02 bnez a5, 36 -80000e28: e7 80 06 00 jalr a3 -80000e2c: 03 27 49 00 lw a4, 4(s2) -80000e30: 83 27 8a 14 lw a5, 328(s4) -80000e34: 63 14 87 01 bne a4, s8, 8 -80000e38: e3 04 f9 f8 beq s2, a5, -120 -80000e3c: e3 88 07 f8 beqz a5, -112 -80000e40: 13 89 07 00 mv s2, a5 -80000e44: 6f f0 df f5 j -164 -80000e48: 83 27 c9 18 lw a5, 396(s2) -80000e4c: 83 a5 44 08 lw a1, 132(s1) -80000e50: 33 77 f7 00 and a4, a4, a5 -80000e54: 63 1c 07 00 bnez a4, 24 -80000e58: 13 05 0b 00 mv a0, s6 -80000e5c: e7 80 06 00 jalr a3 -80000e60: 6f f0 df fc j -52 -80000e64: 23 22 89 00 sw s0, 4(s2) -80000e68: 6f f0 9f fa j -88 -80000e6c: 13 85 05 00 mv a0, a1 -80000e70: e7 80 06 00 jalr a3 -80000e74: 6f f0 9f fb j -72 +80000c34 exit: +80000c34: 13 01 01 ff addi sp, sp, -16 +80000c38: 93 05 00 00 mv a1, zero +80000c3c: 23 24 81 00 sw s0, 8(sp) +80000c40: 23 26 11 00 sw ra, 12(sp) +80000c44: 13 04 05 00 mv s0, a0 +80000c48: ef 00 80 19 jal 408 +80000c4c: b7 17 00 80 lui a5, 524289 +80000c50: 03 a5 07 43 lw a0, 1072(a5) +80000c54: 83 27 c5 03 lw a5, 60(a0) +80000c58: 63 84 07 00 beqz a5, 8 +80000c5c: e7 80 07 00 jalr a5 +80000c60: 13 05 04 00 mv a0, s0 +80000c64: ef f0 5f 8a jal -1884 + +80000c68 memset: +80000c68: 13 03 f0 00 addi t1, zero, 15 +80000c6c: 13 07 05 00 mv a4, a0 +80000c70: 63 7e c3 02 bgeu t1, a2, 60 +80000c74: 93 77 f7 00 andi a5, a4, 15 +80000c78: 63 90 07 0a bnez a5, 160 +80000c7c: 63 92 05 08 bnez a1, 132 +80000c80: 93 76 06 ff andi a3, a2, -16 +80000c84: 13 76 f6 00 andi a2, a2, 15 +80000c88: b3 86 e6 00 add a3, a3, a4 +80000c8c: 23 20 b7 00 sw a1, 0(a4) +80000c90: 23 22 b7 00 sw a1, 4(a4) +80000c94: 23 24 b7 00 sw a1, 8(a4) +80000c98: 23 26 b7 00 sw a1, 12(a4) +80000c9c: 13 07 07 01 addi a4, a4, 16 +80000ca0: e3 66 d7 fe bltu a4, a3, -20 +80000ca4: 63 14 06 00 bnez a2, 8 +80000ca8: 67 80 00 00 ret +80000cac: b3 06 c3 40 sub a3, t1, a2 +80000cb0: 93 96 26 00 slli a3, a3, 2 +80000cb4: 97 02 00 00 auipc t0, 0 +80000cb8: b3 86 56 00 add a3, a3, t0 +80000cbc: 67 80 c6 00 jr 12(a3) +80000cc0: 23 07 b7 00 sb a1, 14(a4) +80000cc4: a3 06 b7 00 sb a1, 13(a4) +80000cc8: 23 06 b7 00 sb a1, 12(a4) +80000ccc: a3 05 b7 00 sb a1, 11(a4) +80000cd0: 23 05 b7 00 sb a1, 10(a4) +80000cd4: a3 04 b7 00 sb a1, 9(a4) +80000cd8: 23 04 b7 00 sb a1, 8(a4) +80000cdc: a3 03 b7 00 sb a1, 7(a4) +80000ce0: 23 03 b7 00 sb a1, 6(a4) +80000ce4: a3 02 b7 00 sb a1, 5(a4) +80000ce8: 23 02 b7 00 sb a1, 4(a4) +80000cec: a3 01 b7 00 sb a1, 3(a4) +80000cf0: 23 01 b7 00 sb a1, 2(a4) +80000cf4: a3 00 b7 00 sb a1, 1(a4) +80000cf8: 23 00 b7 00 sb a1, 0(a4) +80000cfc: 67 80 00 00 ret +80000d00: 93 f5 f5 0f andi a1, a1, 255 +80000d04: 93 96 85 00 slli a3, a1, 8 +80000d08: b3 e5 d5 00 or a1, a1, a3 +80000d0c: 93 96 05 01 slli a3, a1, 16 +80000d10: b3 e5 d5 00 or a1, a1, a3 +80000d14: 6f f0 df f6 j -148 +80000d18: 93 96 27 00 slli a3, a5, 2 +80000d1c: 97 02 00 00 auipc t0, 0 +80000d20: b3 86 56 00 add a3, a3, t0 +80000d24: 93 82 00 00 mv t0, ra +80000d28: e7 80 06 fa jalr -96(a3) +80000d2c: 93 80 02 00 mv ra, t0 +80000d30: 93 87 07 ff addi a5, a5, -16 +80000d34: 33 07 f7 40 sub a4, a4, a5 +80000d38: 33 06 f6 00 add a2, a2, a5 +80000d3c: e3 78 c3 f6 bgeu t1, a2, -144 +80000d40: 6f f0 df f3 j -196 + +80000d44 __register_exitproc: +80000d44: b7 17 00 80 lui a5, 524289 +80000d48: 03 a7 07 43 lw a4, 1072(a5) +80000d4c: 83 27 87 14 lw a5, 328(a4) +80000d50: 63 8c 07 04 beqz a5, 88 +80000d54: 03 a7 47 00 lw a4, 4(a5) +80000d58: 13 08 f0 01 addi a6, zero, 31 +80000d5c: 63 4e e8 06 blt a6, a4, 124 +80000d60: 13 18 27 00 slli a6, a4, 2 +80000d64: 63 06 05 02 beqz a0, 44 +80000d68: 33 83 07 01 add t1, a5, a6 +80000d6c: 23 24 c3 08 sw a2, 136(t1) +80000d70: 83 a8 87 18 lw a7, 392(a5) +80000d74: 13 06 10 00 addi a2, zero, 1 +80000d78: 33 16 e6 00 sll a2, a2, a4 +80000d7c: b3 e8 c8 00 or a7, a7, a2 +80000d80: 23 a4 17 19 sw a7, 392(a5) +80000d84: 23 24 d3 10 sw a3, 264(t1) +80000d88: 93 06 20 00 addi a3, zero, 2 +80000d8c: 63 04 d5 02 beq a0, a3, 40 +80000d90: 13 07 17 00 addi a4, a4, 1 +80000d94: 23 a2 e7 00 sw a4, 4(a5) +80000d98: b3 87 07 01 add a5, a5, a6 +80000d9c: 23 a4 b7 00 sw a1, 8(a5) +80000da0: 13 05 00 00 mv a0, zero +80000da4: 67 80 00 00 ret +80000da8: 93 07 c7 14 addi a5, a4, 332 +80000dac: 23 24 f7 14 sw a5, 328(a4) +80000db0: 6f f0 5f fa j -92 +80000db4: 83 a6 c7 18 lw a3, 396(a5) +80000db8: 13 07 17 00 addi a4, a4, 1 +80000dbc: 23 a2 e7 00 sw a4, 4(a5) +80000dc0: 33 e6 c6 00 or a2, a3, a2 +80000dc4: 23 a6 c7 18 sw a2, 396(a5) +80000dc8: b3 87 07 01 add a5, a5, a6 +80000dcc: 23 a4 b7 00 sw a1, 8(a5) +80000dd0: 13 05 00 00 mv a0, zero +80000dd4: 67 80 00 00 ret +80000dd8: 13 05 f0 ff addi a0, zero, -1 +80000ddc: 67 80 00 00 ret + +80000de0 __call_exitprocs: +80000de0: 13 01 01 fd addi sp, sp, -48 +80000de4: b7 17 00 80 lui a5, 524289 +80000de8: 23 2c 41 01 sw s4, 24(sp) +80000dec: 03 aa 07 43 lw s4, 1072(a5) +80000df0: 23 20 21 03 sw s2, 32(sp) +80000df4: 23 26 11 02 sw ra, 44(sp) +80000df8: 03 29 8a 14 lw s2, 328(s4) +80000dfc: 23 24 81 02 sw s0, 40(sp) +80000e00: 23 22 91 02 sw s1, 36(sp) +80000e04: 23 2e 31 01 sw s3, 28(sp) +80000e08: 23 2a 51 01 sw s5, 20(sp) +80000e0c: 23 28 61 01 sw s6, 16(sp) +80000e10: 23 26 71 01 sw s7, 12(sp) +80000e14: 23 24 81 01 sw s8, 8(sp) +80000e18: 63 00 09 04 beqz s2, 64 +80000e1c: 13 0b 05 00 mv s6, a0 +80000e20: 93 8b 05 00 mv s7, a1 +80000e24: 93 0a 10 00 addi s5, zero, 1 +80000e28: 93 09 f0 ff addi s3, zero, -1 +80000e2c: 83 24 49 00 lw s1, 4(s2) +80000e30: 13 84 f4 ff addi s0, s1, -1 +80000e34: 63 42 04 02 bltz s0, 36 +80000e38: 93 94 24 00 slli s1, s1, 2 +80000e3c: b3 04 99 00 add s1, s2, s1 +80000e40: 63 84 0b 04 beqz s7, 72 +80000e44: 83 a7 44 10 lw a5, 260(s1) +80000e48: 63 80 77 05 beq a5, s7, 64 +80000e4c: 13 04 f4 ff addi s0, s0, -1 +80000e50: 93 84 c4 ff addi s1, s1, -4 +80000e54: e3 16 34 ff bne s0, s3, -20 +80000e58: 83 20 c1 02 lw ra, 44(sp) +80000e5c: 03 24 81 02 lw s0, 40(sp) +80000e60: 83 24 41 02 lw s1, 36(sp) +80000e64: 03 29 01 02 lw s2, 32(sp) +80000e68: 83 29 c1 01 lw s3, 28(sp) +80000e6c: 03 2a 81 01 lw s4, 24(sp) +80000e70: 83 2a 41 01 lw s5, 20(sp) +80000e74: 03 2b 01 01 lw s6, 16(sp) +80000e78: 83 2b c1 00 lw s7, 12(sp) +80000e7c: 03 2c 81 00 lw s8, 8(sp) +80000e80: 13 01 01 03 addi sp, sp, 48 +80000e84: 67 80 00 00 ret +80000e88: 83 27 49 00 lw a5, 4(s2) +80000e8c: 83 a6 44 00 lw a3, 4(s1) +80000e90: 93 87 f7 ff addi a5, a5, -1 +80000e94: 63 8e 87 04 beq a5, s0, 92 +80000e98: 23 a2 04 00 sw zero, 4(s1) +80000e9c: e3 88 06 fa beqz a3, -80 +80000ea0: 83 27 89 18 lw a5, 392(s2) +80000ea4: 33 97 8a 00 sll a4, s5, s0 +80000ea8: 03 2c 49 00 lw s8, 4(s2) +80000eac: b3 77 f7 00 and a5, a4, a5 +80000eb0: 63 92 07 02 bnez a5, 36 +80000eb4: e7 80 06 00 jalr a3 +80000eb8: 03 27 49 00 lw a4, 4(s2) +80000ebc: 83 27 8a 14 lw a5, 328(s4) +80000ec0: 63 14 87 01 bne a4, s8, 8 +80000ec4: e3 04 f9 f8 beq s2, a5, -120 +80000ec8: e3 88 07 f8 beqz a5, -112 +80000ecc: 13 89 07 00 mv s2, a5 +80000ed0: 6f f0 df f5 j -164 +80000ed4: 83 27 c9 18 lw a5, 396(s2) +80000ed8: 83 a5 44 08 lw a1, 132(s1) +80000edc: 33 77 f7 00 and a4, a4, a5 +80000ee0: 63 1c 07 00 bnez a4, 24 +80000ee4: 13 05 0b 00 mv a0, s6 +80000ee8: e7 80 06 00 jalr a3 +80000eec: 6f f0 df fc j -52 +80000ef0: 23 22 89 00 sw s0, 4(s2) +80000ef4: 6f f0 9f fa j -88 +80000ef8: 13 85 05 00 mv a0, a1 +80000efc: e7 80 06 00 jalr a3 +80000f00: 6f f0 9f fb j -72 Disassembly of section .init_array: @@ -1041,25 +1082,25 @@ Disassembly of section .comment: 36: 6a 65 38: 63 74 2e 67 bgeu t3, s2, 1640 3c: 69 74 - 3e: 20 65 - 40: 66 33 - 42: 32 63 - 44: 36 31 - 46: 31 61 - 48: 61 32 - 4a: 31 34 - 4c: 64 65 - 4e: 61 38 - 50: 35 35 - 52: 33 36 34 65 - 56: 66 64 - 58: 37 62 61 34 lui tp, 214550 - 5c: 35 31 - 5e: 65 63 - 60: 35 65 - 62: 63 33 66 37 - 66: 34 29 - 68: 00 47 + 3e: 20 32 + 40: 61 32 + 42: 33 65 66 61 + 46: 63 33 35 32 + 4a: 66 39 + 4c: 31 39 + 4e: 65 62 + 50: 64 31 + 52: 65 63 + 54: 31 62 + 56: 65 34 + 58: 35 31 + 5a: 34 36 + 5c: 64 36 + 5e: 61 39 + 60: 66 61 + 62: 32 31 + 64: 62 35 + 66: 33 29 00 47 6a: 43 43 3a 20 fmadd.s ft6, fs4, ft3, ft4, rmm 6e: 28 47 70: 4e 55 @@ -1143,346 +1184,360 @@ Disassembly of section .symtab: 9e: f1 ff a0: 0e 00 a2: 00 00 - a4: 10 05 + a4: 14 05 a6: 00 80 a8: 00 00 aa: 00 00 ac: 00 00 ae: 02 00 - b0: 15 00 - ... + b0: 1e 00 + b2: 00 00 + b4: 50 05 + b6: 00 80 + b8: 00 00 ba: 00 00 - bc: 04 00 - be: f1 ff + bc: 00 00 + be: 02 00 c0: 25 00 - c2: 00 00 - c4: 50 00 - c6: 00 80 - c8: 18 00 - ca: 00 00 - cc: 02 00 - ce: 02 00 - d0: 33 00 00 00 add zero, zero, zero ... - dc: 04 00 - de: f1 ff - e0: 57 00 00 00 + ca: 00 00 + cc: 04 00 + ce: f1 ff + d0: 35 00 + d2: 00 00 + d4: 50 00 + d6: 00 80 + d8: 18 00 + da: 00 00 + dc: 02 00 + de: 02 00 + e0: 43 00 00 00 fmadd.s ft0, ft0, ft0, ft0, rne ... ec: 04 00 ee: f1 ff - f0: 63 00 00 00 beqz zero, 0 + f0: 67 00 00 00 jr zero ... fc: 04 00 fe: f1 ff - 100: 6e 00 - 102: 00 00 - 104: 14 05 - 106: 00 80 - 108: 48 01 - 10a: 00 00 - 10c: 02 00 - 10e: 02 00 - 110: 84 00 + 100: 73 00 00 00 ecall + ... + 10c: 04 00 + 10e: f1 ff + 110: 81 00 ... 11a: 00 00 11c: 04 00 11e: f1 ff - 120: 9e 00 - ... + 120: 8c 00 + 122: 00 00 + 124: 4c 06 + 126: 00 80 + 128: 3c 01 12a: 00 00 - 12c: 04 00 - 12e: f1 ff - 130: a0 00 - ... + 12c: 02 00 + 12e: 02 00 + 130: a2 00 + 132: 00 00 + 134: 88 07 + 136: 00 80 + 138: a4 00 13a: 00 00 - 13c: 04 00 - 13e: f1 ff - 140: 8e 00 - ... + 13c: 02 00 + 13e: 02 00 + 140: b8 00 + 142: 00 00 + 144: 2c 08 + 146: 00 80 + 148: 2c 00 14a: 00 00 - 14c: 04 00 - 14e: f1 ff - 150: 95 00 + 14c: 02 00 + 14e: 02 00 + 150: cc 00 ... 15a: 00 00 15c: 04 00 15e: f1 ff - 160: 9c 00 + 160: d8 00 ... 16a: 00 00 16c: 04 00 16e: f1 ff - 170: a7 00 00 00 + 170: da 00 ... + 17a: 00 00 17c: 04 00 17e: f1 ff - 180: b0 00 - 182: 00 00 - 184: 08 10 - 186: 00 80 - 188: 28 04 - 18a: 00 00 - 18c: 01 00 - 18e: 04 00 + 180: d6 00 ... + 18a: 00 00 + 18c: 04 00 + 18e: f1 ff + 190: e1 00 + ... + 19a: 00 00 19c: 04 00 19e: f1 ff - 1a0: bc 00 + 1a0: ea 00 1a2: 00 00 - 1a4: 04 10 + 1a4: 08 10 1a6: 00 80 - 1a8: 00 00 + 1a8: 28 04 1aa: 00 00 - 1ac: 00 00 - 1ae: 03 00 cd 00 lb zero, 12(s10) - 1b2: 00 00 - 1b4: 04 10 - 1b6: 00 80 - 1b8: 00 00 - 1ba: 00 00 - 1bc: 00 00 - 1be: 03 00 e0 00 lb zero, 14(zero) + 1ac: 01 00 + 1ae: 04 00 + ... + 1bc: 04 00 + 1be: f1 ff + 1c0: f6 00 1c2: 00 00 1c4: 04 10 1c6: 00 80 1c8: 00 00 1ca: 00 00 1cc: 00 00 - 1ce: 03 00 f1 00 lb zero, 15(sp) + 1ce: 03 00 07 01 lb zero, 16(a4) 1d2: 00 00 - 1d4: 00 10 + 1d4: 04 10 1d6: 00 80 1d8: 00 00 1da: 00 00 1dc: 00 00 - 1de: 03 00 05 01 lb zero, 16(a0) + 1de: 03 00 1a 01 lb zero, 17(s4) 1e2: 00 00 - 1e4: 00 10 + 1e4: 04 10 1e6: 00 80 1e8: 00 00 1ea: 00 00 1ec: 00 00 - 1ee: 03 00 18 01 lb zero, 17(a6) + 1ee: 03 00 2b 01 lb zero, 18(s6) 1f2: 00 00 1f4: 00 10 1f6: 00 80 1f8: 00 00 1fa: 00 00 1fc: 00 00 - 1fe: 03 00 2e 01 lb zero, 18(t3) - ... + 1fe: 03 00 3f 01 lb zero, 19(t5) + 202: 00 00 + 204: 00 10 + 206: 00 80 + 208: 00 00 20a: 00 00 - 20c: 10 00 - 20e: f1 ff - 210: 3c 01 + 20c: 00 00 + 20e: 03 00 52 01 lb zero, 21(tp) 212: 00 00 - 214: 00 04 - 216: 00 00 + 214: 00 10 + 216: 00 80 218: 00 00 21a: 00 00 - 21c: 10 00 - 21e: f1 ff - 220: 49 01 - 222: 00 00 - 224: 40 14 - 226: 00 80 - 228: 80 00 + 21c: 00 00 + 21e: 03 00 68 01 lb zero, 22(a6) + ... 22a: 00 00 - 22c: 11 00 - 22e: 06 00 - 230: 57 01 00 00 - 234: 00 02 - 236: 00 80 - 238: 6c 01 + 22c: 10 00 + 22e: f1 ff + 230: 76 01 + 232: 00 00 + 234: 00 04 + 236: 00 00 + 238: 00 00 23a: 00 00 - 23c: 12 00 - 23e: 02 00 - 240: 74 01 - 242: 00 00 - 244: 30 14 + 23c: 10 00 + 23e: f1 ff + 240: 83 01 00 00 lb gp, 0(zero) + 244: 40 14 246: 00 80 - 248: 00 00 + 248: 80 00 24a: 00 00 - 24c: 10 00 - 24e: 05 00 - 250: 84 01 + 24c: 11 00 + 24e: 06 00 + 250: 91 01 252: 00 00 - 254: 08 18 + 254: 00 02 256: 00 80 - 258: 00 00 + 258: a8 01 25a: 00 00 - 25c: 10 00 - 25e: f1 ff - 260: 95 01 + 25c: 12 00 + 25e: 02 00 + 260: ae 01 262: 00 00 264: 30 14 266: 00 80 - 268: 04 00 + 268: 00 00 26a: 00 00 - 26c: 11 00 + 26c: 10 00 26e: 05 00 - 270: a8 01 + 270: be 01 272: 00 00 - 274: 40 0b + 274: 08 18 276: 00 80 - 278: 9c 00 + 278: 00 00 27a: 00 00 - 27c: 12 00 - 27e: 02 00 - 280: ba 01 - 282: 00 00 - 284: e4 0a + 27c: 10 00 + 27e: f1 ff + 280: cf 01 00 00 fnmadd.s ft3, ft0, ft0, ft0, rne + 284: 30 14 286: 00 80 - 288: 5c 00 + 288: 04 00 28a: 00 00 - 28c: 12 00 - 28e: 02 00 - 290: cc 01 + 28c: 11 00 + 28e: 05 00 + 290: e2 01 292: 00 00 - 294: 00 00 - 296: 00 ff - 298: 00 00 + 294: 54 05 + 296: 00 80 + 298: 9c 00 29a: 00 00 - 29c: 10 00 - 29e: f1 ff - 2a0: d8 01 + 29c: 12 00 + 29e: 02 00 + 2a0: f4 01 2a2: 00 00 - 2a4: d8 04 + 2a4: f0 05 2a6: 00 80 - 2a8: 00 00 + 2a8: 5c 00 2aa: 00 00 2ac: 12 00 2ae: 02 00 - 2b0: e2 01 + 2b0: 06 02 2b2: 00 00 - 2b4: 54 0d + 2b4: 20 05 2b6: 00 80 - 2b8: 24 01 + 2b8: 00 00 2ba: 00 00 2bc: 12 00 2be: 02 00 - 2c0: 18 02 + 2c0: 10 02 2c2: 00 00 - 2c4: 00 00 + 2c4: e0 0d 2c6: 00 80 - 2c8: 50 00 + 2c8: 24 01 2ca: 00 00 2cc: 12 00 - 2ce: 01 00 - 2d0: f3 01 00 00 - 2d4: b8 0c + 2ce: 02 00 + 2d0: 46 02 + 2d2: 00 00 + 2d4: 00 00 2d6: 00 80 - 2d8: 9c 00 + 2d8: 50 00 2da: 00 00 2dc: 12 00 - 2de: 02 00 - 2e0: 07 02 00 00 - 2e4: c0 14 + 2de: 01 00 + 2e0: 21 02 + 2e2: 00 00 + 2e4: 44 0d 2e6: 00 80 - 2e8: 00 00 + 2e8: 9c 00 2ea: 00 00 - 2ec: 10 00 - 2ee: 06 00 - 2f0: 13 02 00 00 mv tp, zero - 2f4: 40 14 + 2ec: 12 00 + 2ee: 02 00 + 2f0: 35 02 + 2f2: 00 00 + 2f4: c0 14 2f6: 00 80 2f8: 00 00 2fa: 00 00 2fc: 10 00 2fe: 06 00 - 300: 1f 02 00 00 - 304: 6c 03 + 300: 41 02 + 302: 00 00 + 304: 40 14 306: 00 80 - 308: 60 01 + 308: 00 00 30a: 00 00 - 30c: 12 00 - 30e: 02 00 - 310: 41 02 + 30c: 10 00 + 30e: 06 00 + 310: 4d 02 312: 00 00 - 314: dc 0b + 314: a8 03 316: 00 80 - 318: dc 00 + 318: 60 01 31a: 00 00 31c: 12 00 31e: 02 00 - 320: 48 02 - 322: 00 00 - 324: 68 00 + 320: 6f 02 00 00 jal tp, 0 + 324: 68 0c 326: 00 80 - 328: 30 00 + 328: dc 00 32a: 00 00 32c: 12 00 32e: 02 00 - 330: 4d 02 + 330: 76 02 332: 00 00 - 334: 9c 0a + 334: 68 00 336: 00 80 - 338: 14 00 + 338: 30 00 33a: 00 00 33c: 12 00 33e: 02 00 - 340: 54 02 - 342: 00 00 - 344: 08 10 + 340: 7b 02 00 00 + 344: 20 0c 346: 00 80 - 348: 00 00 + 348: 14 00 34a: 00 00 - 34c: 10 00 - 34e: 04 00 - 350: 63 02 00 00 beqz zero, 4 - 354: 40 14 + 34c: 12 00 + 34e: 02 00 + 350: 82 02 + 352: 00 00 + 354: 08 10 356: 00 80 358: 00 00 35a: 00 00 35c: 10 00 - 35e: 05 00 - 360: c8 00 + 35e: 04 00 + 360: 91 02 362: 00 00 - 364: c0 14 + 364: 40 14 366: 00 80 368: 00 00 36a: 00 00 36c: 10 00 - 36e: 06 00 - 370: 8b 02 00 00 - 374: b0 0a + 36e: 05 00 + 370: 02 01 + 372: 00 00 + 374: c0 14 376: 00 80 - 378: 34 00 + 378: 00 00 37a: 00 00 - 37c: 12 00 - 37e: 02 00 - 380: 6a 02 + 37c: 10 00 + 37e: 06 00 + 380: b9 02 382: 00 00 - 384: 98 00 + 384: 34 0c 386: 00 80 - 388: 68 01 + 388: 34 00 38a: 00 00 38c: 12 00 38e: 02 00 - 390: 7d 02 + 390: 98 02 392: 00 00 - 394: 88 08 + 394: 98 00 396: 00 80 - 398: 14 02 + 398: 68 01 39a: 00 00 39c: 12 00 39e: 02 00 - 3a0: 8a 02 - 3a2: 00 00 - 3a4: cc 04 + 3a0: ab 02 00 00 + 3a4: 0c 0a 3a6: 00 80 - 3a8: 00 00 + 3a8: 14 02 3aa: 00 00 3ac: 12 00 3ae: 02 00 - 3b0: 90 02 + 3b0: b8 02 3b2: 00 00 - 3b4: 5c 06 + 3b4: 08 05 3b6: 00 80 - 3b8: 2c 02 + 3b8: 00 00 3ba: 00 00 3bc: 12 00 3be: 02 00 + 3c0: be 02 + 3c2: 00 00 + 3c4: 58 08 + 3c6: 00 80 + 3c8: b4 01 + 3ca: 00 00 + 3cc: 12 00 + 3ce: 02 00 Disassembly of section .strtab: @@ -1492,254 +1547,270 @@ Disassembly of section .strtab: 4: 73 74 61 72 csrrci s0, 1830, 2 8: 74 2e a: 53 2e 6f 00 fadd.s ft8, ft10, ft6, rdn - e: 52 45 - 10: 54 55 - 12: 52 4e - 14: 00 5f - 16: 5f 63 61 6c - 1a: 6c 5f - 1c: 61 74 - 1e: 65 78 - 20: 69 74 - 22: 2e 63 - 24: 00 72 - 26: 65 67 - 28: 69 73 - 2a: 74 65 - 2c: 72 5f - 2e: 66 69 - 30: 6e 69 - 32: 00 70 - 34: 6f 63 6c 5f jal t1, 812534 - 38: 76 6f - 3a: 72 74 - 3c: 65 78 - 3e: 5f 6b 65 72 - 42: 6e 65 - 44: 6c 2d - 46: 61 34 - 48: 2d 30 - 4a: 31 2d - 4c: 37 31 2d 35 lui sp, 217811 - 50: 37 2d 36 61 lui s10, 398178 - 54: 2e 63 - 56: 00 70 - 58: 61 72 - 5a: 61 6c - 5c: 6c 65 - 5e: 6c 5f - 60: 62 63 - 62: 00 76 - 64: 78 5f - 66: 73 70 61 77 csrci 1910, 2 - 6a: 6e 2e - 6c: 63 00 73 70 beq t1, t2, 1792 - 70: 61 77 - 72: 6e 5f - 74: 6b 65 72 6e - 78: 65 6c - 7a: 5f 63 61 6c - 7e: 6c 62 - 80: 61 63 - 82: 6b 00 76 78 - 86: 5f 70 65 72 - 8a: 66 2e - 8c: 63 00 66 69 beq a2, s6, 1664 - 90: 6e 69 - 92: 2e 63 - 94: 00 69 - 96: 6e 69 - 98: 74 2e - 9a: 63 00 5f 5f beq t5, s5, 1504 - 9e: 61 74 - a0: 65 78 - a2: 69 74 - a4: 2e 63 - a6: 00 69 - a8: 6d 70 - aa: 75 72 - ac: 65 2e - ae: 63 00 69 6d beq s2, s6, 1728 - b2: 70 75 - b4: 72 65 - b6: 5f 64 61 74 - ba: 61 00 - bc: 5f 5f 66 69 - c0: 6e 69 - c2: 5f 61 72 72 - c6: 61 79 - c8: 5f 65 6e 64 - cc: 00 5f - ce: 5f 66 69 6e - d2: 69 5f - d4: 61 72 - d6: 72 61 - d8: 79 5f - da: 73 74 61 72 csrrci s0, 1830, 2 - de: 74 00 - e0: 5f 5f 69 6e - e4: 69 74 - e6: 5f 61 72 72 - ea: 61 79 - ec: 5f 65 6e 64 - f0: 00 5f - f2: 5f 70 72 65 - f6: 69 6e - f8: 69 74 - fa: 5f 61 72 72 - fe: 61 79 - 100: 5f 65 6e 64 - 104: 00 5f - 106: 5f 69 6e 69 - 10a: 74 5f - 10c: 61 72 - 10e: 72 61 - 110: 79 5f - 112: 73 74 61 72 csrrci s0, 1830, 2 - 116: 74 00 - 118: 5f 5f 70 72 - 11c: 65 69 - 11e: 6e 69 - 120: 74 5f - 122: 61 72 - 124: 72 61 - 126: 79 5f - 128: 73 74 61 72 csrrci s0, 1830, 2 - 12c: 74 00 - 12e: 5f 5f 73 74 - 132: 61 63 - 134: 6b 5f 75 73 - 138: 61 67 - 13a: 65 00 - 13c: 5f 5f 73 74 - 140: 61 63 - 142: 6b 5f 73 69 - 146: 7a 65 - 148: 00 67 - 14a: 5f 77 73 70 - 14e: 61 77 - 150: 6e 5f - 152: 61 72 - 154: 67 73 00 5f - 158: 70 6f - 15a: 63 6c 5f 6b bltu t5, s5, 1720 - 15e: 65 72 - 160: 6e 65 - 162: 6c 5f - 164: 73 67 65 6d csrrsi a4, 1750, 10 - 168: 6d 5f - 16a: 77 6f 72 6b - 16e: 67 72 6f 75 - 172: 70 00 - 174: 5f 5f 53 44 - 178: 41 54 - 17a: 41 5f - 17c: 42 45 - 17e: 47 49 4e 5f - 182: 5f 00 5f 5f - 186: 67 6c 6f 62 - 18a: 61 6c - 18c: 5f 70 6f 69 - 190: 6e 74 - 192: 65 72 - 194: 00 5f - 196: 67 6c 6f 62 - 19a: 61 6c - 19c: 5f 69 6d 70 - 1a0: 75 72 - 1a2: 65 5f - 1a4: 70 74 - 1a6: 72 00 - 1a8: 5f 5f 6c 69 - 1ac: 62 63 - 1ae: 5f 69 6e 69 - 1b2: 74 5f - 1b4: 61 72 - 1b6: 72 61 - 1b8: 79 00 - 1ba: 5f 5f 6c 69 - 1be: 62 63 - 1c0: 5f 66 69 6e - 1c4: 69 5f - 1c6: 61 72 - 1c8: 72 61 - 1ca: 79 00 - 1cc: 5f 5f 73 74 - 1d0: 61 63 - 1d2: 6b 5f 74 6f - 1d6: 70 00 - 1d8: 76 78 - 1da: 5f 73 65 74 - 1de: 5f 73 70 00 - 1e2: 5f 5f 63 61 - 1e6: 6c 6c - 1e8: 5f 65 78 69 - 1ec: 74 70 - 1ee: 72 6f - 1f0: 63 73 00 5f bgeu zero, a6, 1510 - 1f4: 5f 72 65 67 - 1f8: 69 73 - 1fa: 74 65 - 1fc: 72 5f - 1fe: 65 78 - 200: 69 74 - 202: 70 72 - 204: 6f 63 00 5f jal t1, 26096 - 208: 5f 42 53 53 - 20c: 5f 45 4e 44 - 210: 5f 5f 00 5f - 214: 5f 62 73 73 - 218: 5f 73 74 61 - 21c: 72 74 - 21e: 00 5f - 220: 70 6f - 222: 63 6c 5f 6b bltu t5, s5, 1720 - 226: 65 72 - 228: 6e 65 - 22a: 6c 5f - 22c: 73 67 65 6d csrrsi a4, 1750, 10 - 230: 6d 5f - 232: 77 6f 72 6b - 236: 67 72 6f 75 - 23a: 70 5f - 23c: 66 61 - 23e: 73 74 00 6d csrrci s0, 1744, 0 - 242: 65 6d - 244: 73 65 74 00 csrrsi a0, 7, 8 - 248: 6d 61 - 24a: 69 6e - 24c: 00 61 - 24e: 74 65 - 250: 78 69 - 252: 74 00 - 254: 5f 5f 44 41 - 258: 54 41 - 25a: 5f 42 45 47 - 25e: 49 4e - 260: 5f 5f 00 5f - 264: 65 64 - 266: 61 74 - 268: 61 00 - 26a: 5f 70 6f 63 - 26e: 6c 5f - 270: 6b 65 72 6e - 274: 65 6c - 276: 5f 73 67 65 - 27a: 6d 6d - 27c: 00 76 - 27e: 78 5f - 280: 70 65 - 282: 72 66 - 284: 5f 64 75 6d - 288: 70 00 - 28a: 5f 65 78 69 - 28e: 74 00 - 290: 76 78 - 292: 5f 73 70 61 - 296: 77 6e 5f 6b - 29a: 65 72 - 29c: 6e 65 - 29e: 6c 00 + e: 6c 61 + 10: 62 65 + 12: 6c 5f + 14: 65 78 + 16: 69 74 + 18: 5f 6e 65 78 + 1c: 74 00 + 1e: 52 45 + 20: 54 55 + 22: 52 4e + 24: 00 5f + 26: 5f 63 61 6c + 2a: 6c 5f + 2c: 61 74 + 2e: 65 78 + 30: 69 74 + 32: 2e 63 + 34: 00 72 + 36: 65 67 + 38: 69 73 + 3a: 74 65 + 3c: 72 5f + 3e: 66 69 + 40: 6e 69 + 42: 00 70 + 44: 6f 63 6c 5f jal t1, 812534 + 48: 76 6f + 4a: 72 74 + 4c: 65 78 + 4e: 5f 6b 65 72 + 52: 6e 65 + 54: 6c 2d + 56: 62 39 + 58: 2d 31 + 5a: 31 2d + 5c: 33 34 2d 35 + 60: 33 2d 66 30 + 64: 2e 63 + 66: 00 70 + 68: 61 72 + 6a: 61 6c + 6c: 6c 65 + 6e: 6c 5f + 70: 62 63 + 72: 00 76 + 74: 78 5f + 76: 73 79 73 63 csrrci s2, 1591, 6 + 7a: 61 6c + 7c: 6c 73 + 7e: 2e 63 + 80: 00 76 + 82: 78 5f + 84: 73 70 61 77 csrci 1910, 2 + 88: 6e 2e + 8a: 63 00 73 70 beq t1, t2, 1792 + 8e: 61 77 + 90: 6e 5f + 92: 6b 65 72 6e + 96: 65 6c + 98: 5f 61 6c 6c + 9c: 5f 73 74 75 + a0: 62 00 + a2: 73 70 61 77 csrci 1910, 2 + a6: 6e 5f + a8: 6b 65 72 6e + ac: 65 6c + ae: 5f 72 65 6d + b2: 5f 73 74 75 + b6: 62 00 + b8: 73 70 61 77 csrci 1910, 2 + bc: 6e 5f + be: 6b 65 72 6e + c2: 65 6c + c4: 5f 61 6c 6c + c8: 5f 63 62 00 + cc: 76 78 + ce: 5f 70 65 72 + d2: 66 2e + d4: 63 00 5f 5f beq t5, s5, 1504 + d8: 61 74 + da: 65 78 + dc: 69 74 + de: 2e 63 + e0: 00 69 + e2: 6d 70 + e4: 75 72 + e6: 65 2e + e8: 63 00 69 6d beq s2, s6, 1728 + ec: 70 75 + ee: 72 65 + f0: 5f 64 61 74 + f4: 61 00 + f6: 5f 5f 66 69 + fa: 6e 69 + fc: 5f 61 72 72 + 100: 61 79 + 102: 5f 65 6e 64 + 106: 00 5f + 108: 5f 66 69 6e + 10c: 69 5f + 10e: 61 72 + 110: 72 61 + 112: 79 5f + 114: 73 74 61 72 csrrci s0, 1830, 2 + 118: 74 00 + 11a: 5f 5f 69 6e + 11e: 69 74 + 120: 5f 61 72 72 + 124: 61 79 + 126: 5f 65 6e 64 + 12a: 00 5f + 12c: 5f 70 72 65 + 130: 69 6e + 132: 69 74 + 134: 5f 61 72 72 + 138: 61 79 + 13a: 5f 65 6e 64 + 13e: 00 5f + 140: 5f 69 6e 69 + 144: 74 5f + 146: 61 72 + 148: 72 61 + 14a: 79 5f + 14c: 73 74 61 72 csrrci s0, 1830, 2 + 150: 74 00 + 152: 5f 5f 70 72 + 156: 65 69 + 158: 6e 69 + 15a: 74 5f + 15c: 61 72 + 15e: 72 61 + 160: 79 5f + 162: 73 74 61 72 csrrci s0, 1830, 2 + 166: 74 00 + 168: 5f 5f 73 74 + 16c: 61 63 + 16e: 6b 5f 75 73 + 172: 61 67 + 174: 65 00 + 176: 5f 5f 73 74 + 17a: 61 63 + 17c: 6b 5f 73 69 + 180: 7a 65 + 182: 00 67 + 184: 5f 77 73 70 + 188: 61 77 + 18a: 6e 5f + 18c: 61 72 + 18e: 67 73 00 5f + 192: 70 6f + 194: 63 6c 5f 6b bltu t5, s5, 1720 + 198: 65 72 + 19a: 6e 65 + 19c: 6c 5f + 19e: 73 67 65 6d csrrsi a4, 1750, 10 + 1a2: 6d 5f + 1a4: 77 6f 72 6b + 1a8: 67 72 6f 75 + 1ac: 70 00 + 1ae: 5f 5f 53 44 + 1b2: 41 54 + 1b4: 41 5f + 1b6: 42 45 + 1b8: 47 49 4e 5f + 1bc: 5f 00 5f 5f + 1c0: 67 6c 6f 62 + 1c4: 61 6c + 1c6: 5f 70 6f 69 + 1ca: 6e 74 + 1cc: 65 72 + 1ce: 00 5f + 1d0: 67 6c 6f 62 + 1d4: 61 6c + 1d6: 5f 69 6d 70 + 1da: 75 72 + 1dc: 65 5f + 1de: 70 74 + 1e0: 72 00 + 1e2: 5f 5f 6c 69 + 1e6: 62 63 + 1e8: 5f 69 6e 69 + 1ec: 74 5f + 1ee: 61 72 + 1f0: 72 61 + 1f2: 79 00 + 1f4: 5f 5f 6c 69 + 1f8: 62 63 + 1fa: 5f 66 69 6e + 1fe: 69 5f + 200: 61 72 + 202: 72 61 + 204: 79 00 + 206: 76 78 + 208: 5f 73 65 74 + 20c: 5f 73 70 00 + 210: 5f 5f 63 61 + 214: 6c 6c + 216: 5f 65 78 69 + 21a: 74 70 + 21c: 72 6f + 21e: 63 73 00 5f bgeu zero, a6, 1510 + 222: 5f 72 65 67 + 226: 69 73 + 228: 74 65 + 22a: 72 5f + 22c: 65 78 + 22e: 69 74 + 230: 70 72 + 232: 6f 63 00 5f jal t1, 26096 + 236: 5f 42 53 53 + 23a: 5f 45 4e 44 + 23e: 5f 5f 00 5f + 242: 5f 62 73 73 + 246: 5f 73 74 61 + 24a: 72 74 + 24c: 00 5f + 24e: 70 6f + 250: 63 6c 5f 6b bltu t5, s5, 1720 + 254: 65 72 + 256: 6e 65 + 258: 6c 5f + 25a: 73 67 65 6d csrrsi a4, 1750, 10 + 25e: 6d 5f + 260: 77 6f 72 6b + 264: 67 72 6f 75 + 268: 70 5f + 26a: 66 61 + 26c: 73 74 00 6d csrrci s0, 1744, 0 + 270: 65 6d + 272: 73 65 74 00 csrrsi a0, 7, 8 + 276: 6d 61 + 278: 69 6e + 27a: 00 61 + 27c: 74 65 + 27e: 78 69 + 280: 74 00 + 282: 5f 5f 44 41 + 286: 54 41 + 288: 5f 42 45 47 + 28c: 49 4e + 28e: 5f 5f 00 5f + 292: 65 64 + 294: 61 74 + 296: 61 00 + 298: 5f 70 6f 63 + 29c: 6c 5f + 29e: 6b 65 72 6e + 2a2: 65 6c + 2a4: 5f 73 67 65 + 2a8: 6d 6d + 2aa: 00 76 + 2ac: 78 5f + 2ae: 70 65 + 2b0: 72 66 + 2b2: 5f 64 75 6d + 2b6: 70 00 + 2b8: 5f 65 78 69 + 2bc: 74 00 + 2be: 76 78 + 2c0: 5f 73 70 61 + 2c4: 77 6e 5f 6b + 2c8: 65 72 + 2ca: 6e 65 + 2cc: 6c 00 Disassembly of section .shstrtab: diff --git a/tests/opencl/transpose/Makefile b/tests/opencl/transpose/Makefile index d19ad3c7..008e69bc 100644 --- a/tests/opencl/transpose/Makefile +++ b/tests/opencl/transpose/Makefile @@ -7,8 +7,8 @@ POCL_RT_PATH ?= /opt/pocl/runtime VORTEX_DRV_PATH ?= $(realpath ../../../driver) VORTEX_RT_PATH ?= $(realpath ../../../runtime) -K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -float-abi=hard -code-model=small" -K_CFLAGS += "-v -O3 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" +K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -mattr=+vortex -float-abi=hard -code-model=small" +K_CFLAGS += "-v -O3 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -Xclang -target-feature -Xclang +vortex -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" K_LDFLAGS += "-Wl,-Bstatic,-T$(VORTEX_RT_PATH)/linker/vx_link.ld -Wl,--gc-sections $(VORTEX_RT_PATH)/libvortexrt.a -lm" CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -pedantic -Wfatal-errors @@ -31,13 +31,13 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ run-fpga: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) run-asesim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) run-vlsim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) run-simx: $(PROJECT) kernel.pocl LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) diff --git a/tests/opencl/vecadd/Makefile b/tests/opencl/vecadd/Makefile index 04065438..b08a0be7 100644 --- a/tests/opencl/vecadd/Makefile +++ b/tests/opencl/vecadd/Makefile @@ -9,8 +9,8 @@ OPTS ?= -n64 VORTEX_DRV_PATH ?= $(realpath ../../../driver) VORTEX_RT_PATH ?= $(realpath ../../../runtime) -K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -float-abi=hard -code-model=small" -K_CFLAGS += "-v -O3 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" +K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -mattr=+vortex -float-abi=hard -code-model=small" +K_CFLAGS += "-v -O3 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -Xclang -target-feature -Xclang +vortex -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" K_LDFLAGS += "-Wl,-Bstatic,-T$(VORTEX_RT_PATH)/linker/vx_link.ld -Wl,--gc-sections $(VORTEX_RT_PATH)/libvortexrt.a -lm" CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors @@ -35,13 +35,13 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ run-fpga: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-simx: $(PROJECT) kernel.pocl LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/opencl/vecadd/kernel.pocl b/tests/opencl/vecadd/kernel.pocl index 230878b6..094da219 100644 Binary files a/tests/opencl/vecadd/kernel.pocl and b/tests/opencl/vecadd/kernel.pocl differ diff --git a/tests/opencl/vecadd/vecadd.dump b/tests/opencl/vecadd/vecadd.dump index 468485de..8a57bf4b 100644 --- a/tests/opencl/vecadd/vecadd.dump +++ b/tests/opencl/vecadd/vecadd.dump @@ -1,39 +1,39 @@ -/tmp/pocl_vortex_kernel-d3-1f-7f-52-5c.elf: file format ELF32-riscv +/tmp/pocl_vortex_kernel-76-54-b8-50-2a.elf: file format ELF32-riscv Disassembly of section .init: 80000000 _start: 80000000: 97 05 00 00 auipc a1, 0 -80000004: 93 85 45 25 addi a1, a1, 596 +80000004: 93 85 05 26 addi a1, a1, 608 80000008: 73 25 10 fc csrr a0, 4033 -8000000c: 6b 10 b5 00 -80000010: ef 00 40 24 jal 580 +8000000c: 6b 10 b5 00 vx_wspawn a0, a1 +80000010: ef 00 00 25 jal 592 80000014: 13 05 10 00 addi a0, zero, 1 -80000018: 6b 00 05 00 +80000018: 6b 00 05 00 vx_tmc a0 8000001c: 17 15 00 00 auipc a0, 1 80000020: 13 05 85 41 addi a0, a0, 1048 80000024: 17 16 00 00 auipc a2, 1 80000028: 13 06 06 49 addi a2, a2, 1168 8000002c: 33 06 a6 40 sub a2, a2, a0 80000030: 93 05 00 00 mv a1, zero -80000034: ef 00 50 12 jal 2340 -80000038: 17 15 00 00 auipc a0, 1 -8000003c: 13 05 85 82 addi a0, a0, -2008 -80000040: ef 00 80 7d jal 2008 -80000044: ef 00 90 07 jal 2168 +80000034: ef 00 50 17 jal 2420 +80000038: 17 05 00 00 auipc a0, 0 +8000003c: 13 05 85 2f addi a0, a0, 760 +80000040: ef 00 10 12 jal 2336 +80000044: ef 00 00 25 jal 592 80000048: ef 00 00 02 jal 32 -8000004c: 6f 00 00 7e j 2016 +8000004c: 6f 00 90 12 j 2344 Disassembly of section .text: 80000050 register_fini: 80000050: 93 07 00 00 mv a5, zero 80000054: 63 88 07 00 beqz a5, 16 -80000058: 37 15 00 80 lui a0, 524289 -8000005c: 13 05 05 86 addi a0, a0, -1952 -80000060: 6f 00 80 7b j 1976 +80000058: 37 05 00 80 lui a0, 524288 +8000005c: 13 05 05 33 addi a0, a0, 816 +80000060: 6f 00 10 10 j 2304 80000064: 67 80 00 00 ret 80000068 main: @@ -44,7 +44,7 @@ Disassembly of section .text: 80000078: 37 05 ff 7f lui a0, 524272 8000007c: 13 06 45 03 addi a2, a0, 52 80000080: 37 05 ff 7f lui a0, 524272 -80000084: ef 00 40 35 jal 852 +80000084: ef 00 40 51 jal 1300 80000088: 13 05 00 00 mv a0, zero 8000008c: 83 20 c1 00 lw ra, 12(sp) 80000090: 13 01 01 01 addi sp, sp, 16 @@ -165,649 +165,675 @@ Disassembly of section .text: 80000244: 67 80 00 00 ret 80000248 _exit: -80000248: ef 00 c0 3b jal 956 -8000024c: 13 05 00 00 mv a0, zero -80000250: 6b 00 05 00 +80000248: 63 06 05 00 beqz a0, 12 +8000024c: 93 01 05 00 mv gp, a0 +80000250: 73 00 00 00 ecall -80000254 vx_set_sp: -80000254: 73 25 00 fc csrr a0, 4032 -80000258: 6b 00 05 00 -8000025c: 97 11 00 00 auipc gp, 1 -80000260: 93 81 c1 5a addi gp, gp, 1452 -80000264: 17 01 00 7f auipc sp, 520192 -80000268: 13 01 c1 d9 addi sp, sp, -612 -8000026c: 93 05 00 40 addi a1, zero, 1024 -80000270: 73 26 10 cc csrr a2, 3265 -80000274: b3 85 c5 02 mul a1, a1, a2 -80000278: 33 01 b1 40 sub sp, sp, a1 -8000027c: f3 26 30 cc csrr a3, 3267 -80000280: 63 86 06 00 beqz a3, 12 -80000284: 13 05 00 00 mv a0, zero -80000288: 6b 00 05 00 +80000254 label_exit_next: +80000254: ef 00 80 4f jal 1272 +80000258: 13 05 00 00 mv a0, zero +8000025c: 6b 00 05 00 vx_tmc a0 -8000028c RETURN: -8000028c: 67 80 00 00 ret +80000260 vx_set_sp: +80000260: 13 05 f0 ff addi a0, zero, -1 +80000264: 6b 00 05 00 vx_tmc a0 +80000268: 97 11 00 00 auipc gp, 1 +8000026c: 93 81 01 5a addi gp, gp, 1440 +80000270: 37 01 00 ff lui sp, 1044480 +80000274: 73 26 10 cc csrr a2, 3265 +80000278: 93 15 a6 00 slli a1, a2, 10 +8000027c: 33 01 b1 40 sub sp, sp, a1 +80000280: f3 26 30 cc csrr a3, 3267 +80000284: 63 86 06 00 beqz a3, 12 +80000288: 13 05 00 00 mv a0, zero +8000028c: 6b 00 05 00 vx_tmc a0 -80000290 spawn_kernel_callback: -80000290: 13 01 01 fe addi sp, sp, -32 -80000294: 23 2e 11 00 sw ra, 28(sp) -80000298: 23 2c 81 00 sw s0, 24(sp) -8000029c: 23 2a 91 00 sw s1, 20(sp) -800002a0: 23 28 21 01 sw s2, 16(sp) -800002a4: 23 26 31 01 sw s3, 12(sp) -800002a8: 23 24 41 01 sw s4, 8(sp) -800002ac: 23 22 51 01 sw s5, 4(sp) -800002b0: f3 27 00 fc csrr a5, 4032 -800002b4: 6b 80 07 00 -800002b8: f3 26 50 cc csrr a3, 3269 -800002bc: 73 29 30 cc csrr s2, 3267 -800002c0: 73 27 00 cc csrr a4, 3264 -800002c4: 73 26 00 fc csrr a2, 4032 -800002c8: b7 17 00 80 lui a5, 524289 -800002cc: 93 96 26 00 slli a3, a3, 2 -800002d0: 93 87 47 43 addi a5, a5, 1076 -800002d4: b3 87 d7 00 add a5, a5, a3 -800002d8: 03 a4 07 00 lw s0, 0(a5) -800002dc: 83 24 44 01 lw s1, 20(s0) -800002e0: 83 26 04 01 lw a3, 16(s0) -800002e4: b3 2a 99 00 slt s5, s2, s1 -800002e8: 93 87 04 00 mv a5, s1 -800002ec: b3 8a da 00 add s5, s5, a3 -800002f0: b3 84 26 03 mul s1, a3, s2 -800002f4: 63 54 f9 00 bge s2, a5, 8 -800002f8: 93 07 09 00 mv a5, s2 -800002fc: b3 84 f4 00 add s1, s1, a5 -80000300: 83 25 04 00 lw a1, 0(s0) -80000304: 83 26 c4 00 lw a3, 12(s0) -80000308: 83 a9 05 00 lw s3, 0(a1) -8000030c: 03 aa 45 00 lw s4, 4(a1) -80000310: b3 84 c4 02 mul s1, s1, a2 -80000314: b3 87 ea 02 mul a5, s5, a4 -80000318: b3 84 d4 00 add s1, s1, a3 -8000031c: b3 84 f4 00 add s1, s1, a5 -80000320: b3 8a 9a 00 add s5, s5, s1 -80000324: 33 8a 49 03 mul s4, s3, s4 -80000328: 63 c0 54 07 blt s1, s5, 96 -8000032c: 6f 00 00 08 j 128 -80000330: 03 47 a4 01 lbu a4, 26(s0) -80000334: 83 46 94 01 lbu a3, 25(s0) -80000338: 33 d7 e4 40 sra a4, s1, a4 -8000033c: b3 07 47 03 mul a5, a4, s4 -80000340: b3 87 f4 40 sub a5, s1, a5 -80000344: 63 80 06 06 beqz a3, 96 -80000348: 83 46 b4 01 lbu a3, 27(s0) -8000034c: b3 d6 d7 40 sra a3, a5, a3 -80000350: b3 88 36 03 mul a7, a3, s3 -80000354: 03 ae 45 01 lw t3, 20(a1) -80000358: 03 a3 05 01 lw t1, 16(a1) -8000035c: 03 a6 c5 00 lw a2, 12(a1) -80000360: 03 28 44 00 lw a6, 4(s0) -80000364: 03 25 84 00 lw a0, 8(s0) -80000368: 93 84 14 00 addi s1, s1, 1 -8000036c: 33 07 c7 01 add a4, a4, t3 -80000370: b3 86 66 00 add a3, a3, t1 -80000374: b3 87 17 41 sub a5, a5, a7 -80000378: 33 86 c7 00 add a2, a5, a2 -8000037c: e7 00 08 00 jalr a6 -80000380: 63 86 9a 02 beq s5, s1, 44 -80000384: 83 25 04 00 lw a1, 0(s0) -80000388: 83 47 84 01 lbu a5, 24(s0) -8000038c: e3 92 07 fa bnez a5, -92 -80000390: 33 c7 44 03 div a4, s1, s4 -80000394: 83 46 94 01 lbu a3, 25(s0) -80000398: b3 07 47 03 mul a5, a4, s4 -8000039c: b3 87 f4 40 sub a5, s1, a5 -800003a0: e3 94 06 fa bnez a3, -88 -800003a4: b3 c6 37 03 div a3, a5, s3 -800003a8: 6f f0 9f fa j -88 -800003ac: 13 39 19 00 seqz s2, s2 -800003b0: 6b 00 09 00 -800003b4: 83 20 c1 01 lw ra, 28(sp) -800003b8: 03 24 81 01 lw s0, 24(sp) -800003bc: 83 24 41 01 lw s1, 20(sp) -800003c0: 03 29 01 01 lw s2, 16(sp) -800003c4: 83 29 c1 00 lw s3, 12(sp) -800003c8: 03 2a 81 00 lw s4, 8(sp) -800003cc: 83 2a 41 00 lw s5, 4(sp) -800003d0: 13 01 01 02 addi sp, sp, 32 -800003d4: 67 80 00 00 ret +80000290 RETURN: +80000290: 67 80 00 00 ret -800003d8 vx_spawn_kernel: -800003d8: 13 01 01 fc addi sp, sp, -64 -800003dc: 23 2e 11 02 sw ra, 60(sp) -800003e0: 23 2c 81 02 sw s0, 56(sp) -800003e4: 23 2a 91 02 sw s1, 52(sp) -800003e8: 23 28 21 03 sw s2, 48(sp) -800003ec: 23 26 31 03 sw s3, 44(sp) -800003f0: f3 28 20 fc csrr a7, 4034 -800003f4: 73 23 10 fc csrr t1, 4033 -800003f8: 73 24 00 fc csrr s0, 4032 -800003fc: f3 27 50 cc csrr a5, 3269 -80000400: 13 07 f0 01 addi a4, zero, 31 -80000404: 63 46 f7 0e blt a4, a5, 236 -80000408: 03 2e 05 00 lw t3, 0(a0) -8000040c: 83 26 45 00 lw a3, 4(a0) -80000410: 03 28 85 00 lw a6, 8(a0) -80000414: b3 0e 83 02 mul t4, t1, s0 -80000418: 13 07 10 00 addi a4, zero, 1 -8000041c: b3 06 de 02 mul a3, t3, a3 -80000420: 33 88 06 03 mul a6, a3, a6 -80000424: 63 d4 0e 01 bge t4, a6, 8 -80000428: 33 47 d8 03 div a4, a6, t4 -8000042c: 63 c0 e8 0e blt a7, a4, 224 -80000430: 63 d0 e7 0c bge a5, a4, 192 -80000434: 93 88 f8 ff addi a7, a7, -1 -80000438: b3 4e e8 02 div t4, a6, a4 -8000043c: 93 84 0e 00 mv s1, t4 -80000440: 63 96 f8 00 bne a7, a5, 12 -80000444: 33 67 e8 02 rem a4, a6, a4 -80000448: b3 04 d7 01 add s1, a4, t4 -8000044c: 33 c9 84 02 div s2, s1, s0 -80000450: b3 e4 84 02 rem s1, s1, s0 -80000454: 63 42 69 0c blt s2, t1, 196 -80000458: 93 02 10 00 addi t0, zero, 1 -8000045c: 33 48 69 02 div a6, s2, t1 -80000460: 63 06 08 00 beqz a6, 12 -80000464: 93 02 08 00 mv t0, a6 -80000468: 33 68 69 02 rem a6, s2, t1 -8000046c: d3 f7 06 d0 fcvt.s.w fa5, a3 -80000470: 93 8f f6 ff addi t6, a3, -1 -80000474: 13 0f fe ff addi t5, t3, -1 -80000478: b7 19 00 80 lui s3, 524289 -8000047c: b3 f6 df 00 and a3, t6, a3 -80000480: 93 89 49 43 addi s3, s3, 1076 -80000484: 93 b6 16 00 seqz a3, a3 -80000488: 23 22 a1 00 sw a0, 4(sp) -8000048c: 23 24 b1 00 sw a1, 8(sp) -80000490: 23 26 c1 00 sw a2, 12(sp) -80000494: 23 2a 51 00 sw t0, 20(sp) -80000498: 23 2c 01 01 sw a6, 24(sp) -8000049c: 23 0e d1 00 sb a3, 28(sp) -800004a0: 33 87 fe 02 mul a4, t4, a5 -800004a4: d3 8e 07 e0 fmv.x.w t4, fa5 -800004a8: d3 77 0e d0 fcvt.s.w fa5, t3 -800004ac: 93 97 27 00 slli a5, a5, 2 -800004b0: 33 7e cf 01 and t3, t5, t3 -800004b4: d3 88 07 e0 fmv.x.w a7, fa5 -800004b8: 93 de 7e 41 srai t4, t4, 23 -800004bc: 13 3e 1e 00 seqz t3, t3 -800004c0: 93 d8 78 41 srai a7, a7, 23 -800004c4: 93 8e 1e f8 addi t4, t4, -127 -800004c8: 93 88 18 f8 addi a7, a7, -127 -800004cc: b3 87 f9 00 add a5, s3, a5 -800004d0: 23 28 e1 00 sw a4, 16(sp) -800004d4: 13 07 41 00 addi a4, sp, 4 -800004d8: a3 0e c1 01 sb t3, 29(sp) -800004dc: 23 0f d1 01 sb t4, 30(sp) -800004e0: a3 0f 11 01 sb a7, 31(sp) -800004e4: 23 a0 e7 00 sw a4, 0(a5) -800004e8: 63 4e 20 03 bgtz s2, 60 -800004ec: 63 9c 04 04 bnez s1, 88 -800004f0: 83 20 c1 03 lw ra, 60(sp) -800004f4: 03 24 81 03 lw s0, 56(sp) -800004f8: 83 24 41 03 lw s1, 52(sp) -800004fc: 03 29 01 03 lw s2, 48(sp) -80000500: 83 29 c1 02 lw s3, 44(sp) -80000504: 13 01 01 04 addi sp, sp, 64 -80000508: 67 80 00 00 ret -8000050c: 13 87 08 00 mv a4, a7 -80000510: e3 c2 e7 f2 blt a5, a4, -220 -80000514: 6f f0 df fd j -36 -80000518: 13 08 00 00 mv a6, zero -8000051c: 93 02 10 00 addi t0, zero, 1 -80000520: 6f f0 df f4 j -180 -80000524: 13 07 09 00 mv a4, s2 -80000528: 63 54 23 01 bge t1, s2, 8 -8000052c: 13 07 03 00 mv a4, t1 -80000530: b7 07 00 80 lui a5, 524288 -80000534: 93 87 07 29 addi a5, a5, 656 -80000538: 6b 10 f7 00 -8000053c: ef f0 5f d5 jal -684 -80000540: e3 88 04 fa beqz s1, -80 -80000544: 33 04 89 02 mul s0, s2, s0 -80000548: 23 28 81 00 sw s0, 16(sp) -8000054c: 6b 80 04 00 -80000550: 73 27 50 cc csrr a4, 3269 -80000554: f3 27 20 cc csrr a5, 3266 -80000558: 13 17 27 00 slli a4, a4, 2 -8000055c: b3 89 e9 00 add s3, s3, a4 -80000560: 03 a5 09 00 lw a0, 0(s3) -80000564: 83 25 05 00 lw a1, 0(a0) -80000568: 83 26 c5 00 lw a3, 12(a0) -8000056c: 03 47 85 01 lbu a4, 24(a0) -80000570: 03 a8 05 00 lw a6, 0(a1) -80000574: 03 a6 45 00 lw a2, 4(a1) -80000578: b3 87 d7 00 add a5, a5, a3 -8000057c: 33 06 c8 02 mul a2, a6, a2 -80000580: 63 0e 07 06 beqz a4, 124 -80000584: 03 47 a5 01 lbu a4, 26(a0) -80000588: 33 d7 e7 40 sra a4, a5, a4 -8000058c: 83 46 95 01 lbu a3, 25(a0) -80000590: 33 06 e6 02 mul a2, a2, a4 -80000594: b3 87 c7 40 sub a5, a5, a2 -80000598: 63 8e 06 04 beqz a3, 92 -8000059c: 83 48 b5 01 lbu a7, 27(a0) -800005a0: b3 d8 17 41 sra a7, a5, a7 -800005a4: 33 08 18 03 mul a6, a6, a7 -800005a8: 03 ae 45 01 lw t3, 20(a1) -800005ac: 83 a6 05 01 lw a3, 16(a1) -800005b0: 03 a6 c5 00 lw a2, 12(a1) -800005b4: 03 23 45 00 lw t1, 4(a0) -800005b8: 03 25 85 00 lw a0, 8(a0) -800005bc: 33 07 c7 01 add a4, a4, t3 -800005c0: b3 86 d8 00 add a3, a7, a3 -800005c4: b3 87 07 41 sub a5, a5, a6 -800005c8: 33 86 c7 00 add a2, a5, a2 -800005cc: e7 00 03 00 jalr t1 -800005d0: 93 07 10 00 addi a5, zero, 1 -800005d4: 6b 80 07 00 -800005d8: 83 20 c1 03 lw ra, 60(sp) -800005dc: 03 24 81 03 lw s0, 56(sp) -800005e0: 83 24 41 03 lw s1, 52(sp) -800005e4: 03 29 01 03 lw s2, 48(sp) -800005e8: 83 29 c1 02 lw s3, 44(sp) -800005ec: 13 01 01 04 addi sp, sp, 64 -800005f0: 67 80 00 00 ret -800005f4: b3 c8 07 03 div a7, a5, a6 -800005f8: 6f f0 df fa j -84 -800005fc: 33 c7 c7 02 div a4, a5, a2 -80000600: 6f f0 df f8 j -116 +80000294 __libc_init_array: +80000294: 13 01 01 ff addi sp, sp, -16 +80000298: 23 24 81 00 sw s0, 8(sp) +8000029c: 23 20 21 01 sw s2, 0(sp) +800002a0: 37 14 00 80 lui s0, 524289 +800002a4: 37 19 00 80 lui s2, 524289 +800002a8: 93 07 04 00 mv a5, s0 +800002ac: 13 09 09 00 mv s2, s2 +800002b0: 33 09 f9 40 sub s2, s2, a5 +800002b4: 23 26 11 00 sw ra, 12(sp) +800002b8: 23 22 91 00 sw s1, 4(sp) +800002bc: 13 59 29 40 srai s2, s2, 2 +800002c0: 63 00 09 02 beqz s2, 32 +800002c4: 13 04 04 00 mv s0, s0 +800002c8: 93 04 00 00 mv s1, zero +800002cc: 83 27 04 00 lw a5, 0(s0) +800002d0: 93 84 14 00 addi s1, s1, 1 +800002d4: 13 04 44 00 addi s0, s0, 4 +800002d8: e7 80 07 00 jalr a5 +800002dc: e3 18 99 fe bne s2, s1, -16 +800002e0: 37 14 00 80 lui s0, 524289 +800002e4: 37 19 00 80 lui s2, 524289 +800002e8: 93 07 04 00 mv a5, s0 +800002ec: 13 09 49 00 addi s2, s2, 4 +800002f0: 33 09 f9 40 sub s2, s2, a5 +800002f4: 13 59 29 40 srai s2, s2, 2 +800002f8: 63 00 09 02 beqz s2, 32 +800002fc: 13 04 04 00 mv s0, s0 +80000300: 93 04 00 00 mv s1, zero +80000304: 83 27 04 00 lw a5, 0(s0) +80000308: 93 84 14 00 addi s1, s1, 1 +8000030c: 13 04 44 00 addi s0, s0, 4 +80000310: e7 80 07 00 jalr a5 +80000314: e3 18 99 fe bne s2, s1, -16 +80000318: 83 20 c1 00 lw ra, 12(sp) +8000031c: 03 24 81 00 lw s0, 8(sp) +80000320: 83 24 41 00 lw s1, 4(sp) +80000324: 03 29 01 00 lw s2, 0(sp) +80000328: 13 01 01 01 addi sp, sp, 16 +8000032c: 67 80 00 00 ret -80000604 vx_perf_dump: -80000604: f3 27 50 cc csrr a5, 3269 -80000608: 37 07 ff 00 lui a4, 4080 -8000060c: b3 87 e7 00 add a5, a5, a4 -80000610: 93 97 87 00 slli a5, a5, 8 -80000614: 73 27 00 b0 csrr a4, mcycle -80000618: 23 a0 e7 00 sw a4, 0(a5) -8000061c: 73 27 10 b0 csrr a4, 2817 -80000620: 23 a2 e7 00 sw a4, 4(a5) -80000624: 73 27 20 b0 csrr a4, minstret -80000628: 23 a4 e7 00 sw a4, 8(a5) -8000062c: 73 27 30 b0 csrr a4, mhpmcounter3 -80000630: 23 a6 e7 00 sw a4, 12(a5) -80000634: 73 27 40 b0 csrr a4, mhpmcounter4 -80000638: 23 a8 e7 00 sw a4, 16(a5) -8000063c: 73 27 50 b0 csrr a4, mhpmcounter5 -80000640: 23 aa e7 00 sw a4, 20(a5) -80000644: 73 27 60 b0 csrr a4, mhpmcounter6 -80000648: 23 ac e7 00 sw a4, 24(a5) -8000064c: 73 27 70 b0 csrr a4, mhpmcounter7 -80000650: 23 ae e7 00 sw a4, 28(a5) -80000654: 73 27 80 b0 csrr a4, mhpmcounter8 -80000658: 23 a0 e7 02 sw a4, 32(a5) -8000065c: 73 27 90 b0 csrr a4, mhpmcounter9 -80000660: 23 a2 e7 02 sw a4, 36(a5) -80000664: 73 27 a0 b0 csrr a4, mhpmcounter10 -80000668: 23 a4 e7 02 sw a4, 40(a5) -8000066c: 73 27 b0 b0 csrr a4, mhpmcounter11 -80000670: 23 a6 e7 02 sw a4, 44(a5) -80000674: 73 27 c0 b0 csrr a4, mhpmcounter12 -80000678: 23 a8 e7 02 sw a4, 48(a5) -8000067c: 73 27 d0 b0 csrr a4, mhpmcounter13 -80000680: 23 aa e7 02 sw a4, 52(a5) -80000684: 73 27 e0 b0 csrr a4, mhpmcounter14 -80000688: 23 ac e7 02 sw a4, 56(a5) -8000068c: 73 27 f0 b0 csrr a4, mhpmcounter15 -80000690: 23 ae e7 02 sw a4, 60(a5) -80000694: 73 27 00 b1 csrr a4, mhpmcounter16 -80000698: 23 a0 e7 04 sw a4, 64(a5) -8000069c: 73 27 10 b1 csrr a4, mhpmcounter17 -800006a0: 23 a2 e7 04 sw a4, 68(a5) -800006a4: 73 27 20 b1 csrr a4, mhpmcounter18 -800006a8: 23 a4 e7 04 sw a4, 72(a5) -800006ac: 73 27 30 b1 csrr a4, mhpmcounter19 -800006b0: 23 a6 e7 04 sw a4, 76(a5) -800006b4: 73 27 40 b1 csrr a4, mhpmcounter20 -800006b8: 23 a8 e7 04 sw a4, 80(a5) -800006bc: 73 27 50 b1 csrr a4, mhpmcounter21 -800006c0: 23 aa e7 04 sw a4, 84(a5) -800006c4: 73 27 60 b1 csrr a4, mhpmcounter22 -800006c8: 23 ac e7 04 sw a4, 88(a5) -800006cc: 73 27 70 b1 csrr a4, mhpmcounter23 -800006d0: 23 ae e7 04 sw a4, 92(a5) -800006d4: 73 27 80 b1 csrr a4, mhpmcounter24 -800006d8: 23 a0 e7 06 sw a4, 96(a5) -800006dc: 73 27 90 b1 csrr a4, mhpmcounter25 -800006e0: 23 a2 e7 06 sw a4, 100(a5) -800006e4: 73 27 a0 b1 csrr a4, mhpmcounter26 -800006e8: 23 a4 e7 06 sw a4, 104(a5) -800006ec: 73 27 b0 b1 csrr a4, mhpmcounter27 -800006f0: 23 a6 e7 06 sw a4, 108(a5) -800006f4: 73 27 c0 b1 csrr a4, mhpmcounter28 -800006f8: 23 a8 e7 06 sw a4, 112(a5) -800006fc: 73 27 d0 b1 csrr a4, mhpmcounter29 -80000700: 23 aa e7 06 sw a4, 116(a5) -80000704: 73 27 e0 b1 csrr a4, mhpmcounter30 -80000708: 23 ac e7 06 sw a4, 120(a5) -8000070c: 73 27 f0 b1 csrr a4, mhpmcounter31 -80000710: 23 ae e7 06 sw a4, 124(a5) -80000714: 73 27 00 b8 csrr a4, mcycleh -80000718: 23 a0 e7 08 sw a4, 128(a5) -8000071c: 73 27 10 b8 csrr a4, 2945 -80000720: 23 a2 e7 08 sw a4, 132(a5) -80000724: 73 27 20 b8 csrr a4, minstreth -80000728: 23 a4 e7 08 sw a4, 136(a5) -8000072c: 73 27 30 b8 csrr a4, mhpmcounter3h -80000730: 23 a6 e7 08 sw a4, 140(a5) -80000734: 73 27 40 b8 csrr a4, mhpmcounter4h -80000738: 23 a8 e7 08 sw a4, 144(a5) -8000073c: 73 27 50 b8 csrr a4, mhpmcounter5h -80000740: 23 aa e7 08 sw a4, 148(a5) -80000744: 73 27 60 b8 csrr a4, mhpmcounter6h -80000748: 23 ac e7 08 sw a4, 152(a5) -8000074c: 73 27 70 b8 csrr a4, mhpmcounter7h -80000750: 23 ae e7 08 sw a4, 156(a5) -80000754: 73 27 80 b8 csrr a4, mhpmcounter8h -80000758: 23 a0 e7 0a sw a4, 160(a5) -8000075c: 73 27 90 b8 csrr a4, mhpmcounter9h -80000760: 23 a2 e7 0a sw a4, 164(a5) -80000764: 73 27 a0 b8 csrr a4, mhpmcounter10h -80000768: 23 a4 e7 0a sw a4, 168(a5) -8000076c: 73 27 b0 b8 csrr a4, mhpmcounter11h -80000770: 23 a6 e7 0a sw a4, 172(a5) -80000774: 73 27 c0 b8 csrr a4, mhpmcounter12h -80000778: 23 a8 e7 0a sw a4, 176(a5) -8000077c: 73 27 d0 b8 csrr a4, mhpmcounter13h -80000780: 23 aa e7 0a sw a4, 180(a5) -80000784: 73 27 e0 b8 csrr a4, mhpmcounter14h -80000788: 23 ac e7 0a sw a4, 184(a5) -8000078c: 73 27 f0 b8 csrr a4, mhpmcounter15h -80000790: 23 ae e7 0a sw a4, 188(a5) -80000794: 73 27 00 b9 csrr a4, mhpmcounter16h -80000798: 23 a0 e7 0c sw a4, 192(a5) -8000079c: 73 27 10 b9 csrr a4, mhpmcounter17h -800007a0: 23 a2 e7 0c sw a4, 196(a5) -800007a4: 73 27 20 b9 csrr a4, mhpmcounter18h -800007a8: 23 a4 e7 0c sw a4, 200(a5) -800007ac: 73 27 30 b9 csrr a4, mhpmcounter19h -800007b0: 23 a6 e7 0c sw a4, 204(a5) -800007b4: 73 27 40 b9 csrr a4, mhpmcounter20h -800007b8: 23 a8 e7 0c sw a4, 208(a5) -800007bc: 73 27 50 b9 csrr a4, mhpmcounter21h -800007c0: 23 aa e7 0c sw a4, 212(a5) -800007c4: 73 27 60 b9 csrr a4, mhpmcounter22h -800007c8: 23 ac e7 0c sw a4, 216(a5) -800007cc: 73 27 70 b9 csrr a4, mhpmcounter23h -800007d0: 23 ae e7 0c sw a4, 220(a5) -800007d4: 73 27 80 b9 csrr a4, mhpmcounter24h -800007d8: 23 a0 e7 0e sw a4, 224(a5) -800007dc: 73 27 90 b9 csrr a4, mhpmcounter25h -800007e0: 23 a2 e7 0e sw a4, 228(a5) -800007e4: 73 27 a0 b9 csrr a4, mhpmcounter26h -800007e8: 23 a4 e7 0e sw a4, 232(a5) -800007ec: 73 27 b0 b9 csrr a4, mhpmcounter27h -800007f0: 23 a6 e7 0e sw a4, 236(a5) -800007f4: 73 27 c0 b9 csrr a4, mhpmcounter28h -800007f8: 23 a8 e7 0e sw a4, 240(a5) -800007fc: 73 27 d0 b9 csrr a4, mhpmcounter29h -80000800: 23 aa e7 0e sw a4, 244(a5) -80000804: 73 27 e0 b9 csrr a4, mhpmcounter30h -80000808: 23 ac e7 0e sw a4, 248(a5) -8000080c: 73 27 f0 b9 csrr a4, mhpmcounter31h -80000810: 23 ae e7 0e sw a4, 252(a5) -80000814: 67 80 00 00 ret +80000330 __libc_fini_array: +80000330: 13 01 01 ff addi sp, sp, -16 +80000334: 23 24 81 00 sw s0, 8(sp) +80000338: b7 17 00 80 lui a5, 524289 +8000033c: 37 14 00 80 lui s0, 524289 +80000340: 13 04 44 00 addi s0, s0, 4 +80000344: 93 87 47 00 addi a5, a5, 4 +80000348: b3 87 87 40 sub a5, a5, s0 +8000034c: 23 22 91 00 sw s1, 4(sp) +80000350: 23 26 11 00 sw ra, 12(sp) +80000354: 93 d4 27 40 srai s1, a5, 2 +80000358: 63 80 04 02 beqz s1, 32 +8000035c: 93 87 c7 ff addi a5, a5, -4 +80000360: 33 84 87 00 add s0, a5, s0 +80000364: 83 27 04 00 lw a5, 0(s0) +80000368: 93 84 f4 ff addi s1, s1, -1 +8000036c: 13 04 c4 ff addi s0, s0, -4 +80000370: e7 80 07 00 jalr a5 +80000374: e3 98 04 fe bnez s1, -16 +80000378: 83 20 c1 00 lw ra, 12(sp) +8000037c: 03 24 81 00 lw s0, 8(sp) +80000380: 83 24 41 00 lw s1, 4(sp) +80000384: 13 01 01 01 addi sp, sp, 16 +80000388: 67 80 00 00 ret -80000818 atexit: -80000818: 93 05 05 00 mv a1, a0 -8000081c: 93 06 00 00 mv a3, zero -80000820: 13 06 00 00 mv a2, zero -80000824: 13 05 00 00 mv a0, zero -80000828: 6f 00 c0 20 j 524 +8000038c spawn_kernel_all_stub: +8000038c: 13 01 01 fe addi sp, sp, -32 +80000390: 23 2e 11 00 sw ra, 28(sp) +80000394: 23 2c 81 00 sw s0, 24(sp) +80000398: 23 2a 91 00 sw s1, 20(sp) +8000039c: 23 28 21 01 sw s2, 16(sp) +800003a0: 23 26 31 01 sw s3, 12(sp) +800003a4: 23 24 41 01 sw s4, 8(sp) +800003a8: 73 26 50 cc csrr a2, 3269 +800003ac: 73 27 30 cc csrr a4, 3267 +800003b0: f3 26 00 cc csrr a3, 3264 +800003b4: 73 25 00 fc csrr a0, 4032 +800003b8: b7 17 00 80 lui a5, 524289 +800003bc: 13 16 26 00 slli a2, a2, 2 +800003c0: 93 87 47 43 addi a5, a5, 1076 +800003c4: b3 87 c7 00 add a5, a5, a2 +800003c8: 03 a4 07 00 lw s0, 0(a5) +800003cc: 83 24 44 01 lw s1, 20(s0) +800003d0: 03 26 04 01 lw a2, 16(s0) +800003d4: 33 2a 97 00 slt s4, a4, s1 +800003d8: 93 87 04 00 mv a5, s1 +800003dc: 33 0a ca 00 add s4, s4, a2 +800003e0: b3 04 e6 02 mul s1, a2, a4 +800003e4: 63 54 f7 00 bge a4, a5, 8 +800003e8: 93 07 07 00 mv a5, a4 +800003ec: b3 84 f4 00 add s1, s1, a5 +800003f0: 83 25 04 00 lw a1, 0(s0) +800003f4: 03 27 c4 00 lw a4, 12(s0) +800003f8: 03 a9 05 00 lw s2, 0(a1) +800003fc: 83 a9 45 00 lw s3, 4(a1) +80000400: b3 84 a4 02 mul s1, s1, a0 +80000404: b3 07 da 02 mul a5, s4, a3 +80000408: b3 84 e4 00 add s1, s1, a4 +8000040c: b3 84 f4 00 add s1, s1, a5 +80000410: 33 0a 9a 00 add s4, s4, s1 +80000414: b3 09 39 03 mul s3, s2, s3 +80000418: 63 c0 44 07 blt s1, s4, 96 +8000041c: 6f 00 00 08 j 128 +80000420: 03 47 e4 01 lbu a4, 30(s0) +80000424: 83 46 d4 01 lbu a3, 29(s0) +80000428: 33 d7 e4 40 sra a4, s1, a4 +8000042c: b3 07 37 03 mul a5, a4, s3 +80000430: b3 87 f4 40 sub a5, s1, a5 +80000434: 63 80 06 06 beqz a3, 96 +80000438: 83 46 f4 01 lbu a3, 31(s0) +8000043c: b3 d6 d7 40 sra a3, a5, a3 +80000440: b3 88 26 03 mul a7, a3, s2 +80000444: 03 ae 45 01 lw t3, 20(a1) +80000448: 03 a3 05 01 lw t1, 16(a1) +8000044c: 03 a6 c5 00 lw a2, 12(a1) +80000450: 03 28 44 00 lw a6, 4(s0) +80000454: 03 25 84 00 lw a0, 8(s0) +80000458: 93 84 14 00 addi s1, s1, 1 +8000045c: 33 07 c7 01 add a4, a4, t3 +80000460: b3 86 66 00 add a3, a3, t1 +80000464: b3 87 17 41 sub a5, a5, a7 +80000468: 33 86 c7 00 add a2, a5, a2 +8000046c: e7 00 08 00 jalr a6 +80000470: 63 06 9a 02 beq s4, s1, 44 +80000474: 83 25 04 00 lw a1, 0(s0) +80000478: 83 47 c4 01 lbu a5, 28(s0) +8000047c: e3 92 07 fa bnez a5, -92 +80000480: 33 c7 34 03 div a4, s1, s3 +80000484: 83 46 d4 01 lbu a3, 29(s0) +80000488: b3 07 37 03 mul a5, a4, s3 +8000048c: b3 87 f4 40 sub a5, s1, a5 +80000490: e3 94 06 fa bnez a3, -88 +80000494: b3 c6 27 03 div a3, a5, s2 +80000498: 6f f0 9f fa j -88 +8000049c: 03 27 84 01 lw a4, 24(s0) +800004a0: 93 07 00 00 mv a5, zero +800004a4: 6b c0 e7 00 vx_bar a5, a4 +800004a8: 83 20 c1 01 lw ra, 28(sp) +800004ac: 03 24 81 01 lw s0, 24(sp) +800004b0: 83 24 41 01 lw s1, 20(sp) +800004b4: 03 29 01 01 lw s2, 16(sp) +800004b8: 83 29 c1 00 lw s3, 12(sp) +800004bc: 03 2a 81 00 lw s4, 8(sp) +800004c0: 13 01 01 02 addi sp, sp, 32 +800004c4: 67 80 00 00 ret -8000082c exit: -8000082c: 13 01 01 ff addi sp, sp, -16 -80000830: 93 05 00 00 mv a1, zero -80000834: 23 24 81 00 sw s0, 8(sp) -80000838: 23 26 11 00 sw ra, 12(sp) -8000083c: 13 04 05 00 mv s0, a0 -80000840: ef 00 00 29 jal 656 -80000844: b7 17 00 80 lui a5, 524289 -80000848: 03 a5 07 43 lw a0, 1072(a5) -8000084c: 83 27 c5 03 lw a5, 60(a0) -80000850: 63 84 07 00 beqz a5, 8 -80000854: e7 80 07 00 jalr a5 -80000858: 13 05 04 00 mv a0, s0 -8000085c: ef f0 df 9e jal -1556 +800004c8 spawn_kernel_rem_stub: +800004c8: f3 26 50 cc csrr a3, 3269 +800004cc: f3 27 20 cc csrr a5, 3266 +800004d0: 37 17 00 80 lui a4, 524289 +800004d4: 93 96 26 00 slli a3, a3, 2 +800004d8: 13 07 47 43 addi a4, a4, 1076 +800004dc: 33 07 d7 00 add a4, a4, a3 +800004e0: 03 25 07 00 lw a0, 0(a4) +800004e4: 83 25 05 00 lw a1, 0(a0) +800004e8: 83 26 c5 00 lw a3, 12(a0) +800004ec: 03 47 c5 01 lbu a4, 28(a0) +800004f0: 83 a8 05 00 lw a7, 0(a1) +800004f4: 03 a6 45 00 lw a2, 4(a1) +800004f8: b3 87 d7 00 add a5, a5, a3 +800004fc: 33 86 c8 02 mul a2, a7, a2 +80000500: 63 08 07 04 beqz a4, 80 +80000504: 03 47 e5 01 lbu a4, 30(a0) +80000508: 83 46 d5 01 lbu a3, 29(a0) +8000050c: 33 d7 e7 40 sra a4, a5, a4 +80000510: 33 06 c7 02 mul a2, a4, a2 +80000514: b3 87 c7 40 sub a5, a5, a2 +80000518: 63 86 06 04 beqz a3, 76 +8000051c: 83 46 f5 01 lbu a3, 31(a0) +80000520: 33 d8 d7 40 sra a6, a5, a3 +80000524: 83 a6 05 01 lw a3, 16(a1) +80000528: 03 ae 45 01 lw t3, 20(a1) +8000052c: 03 a6 c5 00 lw a2, 12(a1) +80000530: b3 06 d8 00 add a3, a6, a3 +80000534: 33 08 18 03 mul a6, a6, a7 +80000538: 03 23 45 00 lw t1, 4(a0) +8000053c: 03 25 85 00 lw a0, 8(a0) +80000540: 33 07 c7 01 add a4, a4, t3 +80000544: b3 87 07 41 sub a5, a5, a6 +80000548: 33 86 c7 00 add a2, a5, a2 +8000054c: 67 00 03 00 jr t1 +80000550: 33 c7 c7 02 div a4, a5, a2 +80000554: 83 46 d5 01 lbu a3, 29(a0) +80000558: 33 06 c7 02 mul a2, a4, a2 +8000055c: b3 87 c7 40 sub a5, a5, a2 +80000560: e3 9e 06 fa bnez a3, -68 +80000564: 33 c8 17 03 div a6, a5, a7 +80000568: 6f f0 df fb j -68 -80000860 __libc_fini_array: -80000860: 13 01 01 ff addi sp, sp, -16 -80000864: 23 24 81 00 sw s0, 8(sp) -80000868: b7 17 00 80 lui a5, 524289 -8000086c: 37 14 00 80 lui s0, 524289 -80000870: 13 04 44 00 addi s0, s0, 4 -80000874: 93 87 47 00 addi a5, a5, 4 -80000878: b3 87 87 40 sub a5, a5, s0 -8000087c: 23 22 91 00 sw s1, 4(sp) -80000880: 23 26 11 00 sw ra, 12(sp) -80000884: 93 d4 27 40 srai s1, a5, 2 -80000888: 63 80 04 02 beqz s1, 32 -8000088c: 93 87 c7 ff addi a5, a5, -4 -80000890: 33 84 87 00 add s0, a5, s0 -80000894: 83 27 04 00 lw a5, 0(s0) -80000898: 93 84 f4 ff addi s1, s1, -1 -8000089c: 13 04 c4 ff addi s0, s0, -4 -800008a0: e7 80 07 00 jalr a5 -800008a4: e3 98 04 fe bnez s1, -16 -800008a8: 83 20 c1 00 lw ra, 12(sp) -800008ac: 03 24 81 00 lw s0, 8(sp) -800008b0: 83 24 41 00 lw s1, 4(sp) -800008b4: 13 01 01 01 addi sp, sp, 16 -800008b8: 67 80 00 00 ret +8000056c spawn_kernel_all_cb: +8000056c: 13 01 01 ff addi sp, sp, -16 +80000570: 23 26 11 00 sw ra, 12(sp) +80000574: 93 07 f0 ff addi a5, zero, -1 +80000578: 6b 80 07 00 vx_tmc a5 +8000057c: ef f0 1f e1 jal -496 +80000580: f3 27 30 cc csrr a5, 3267 +80000584: 93 b7 17 00 seqz a5, a5 +80000588: 6b 80 07 00 vx_tmc a5 +8000058c: 83 20 c1 00 lw ra, 12(sp) +80000590: 13 01 01 01 addi sp, sp, 16 +80000594: 67 80 00 00 ret -800008bc __libc_init_array: -800008bc: 13 01 01 ff addi sp, sp, -16 -800008c0: 23 24 81 00 sw s0, 8(sp) -800008c4: 23 20 21 01 sw s2, 0(sp) -800008c8: 37 14 00 80 lui s0, 524289 -800008cc: 37 19 00 80 lui s2, 524289 -800008d0: 93 07 04 00 mv a5, s0 -800008d4: 13 09 09 00 mv s2, s2 -800008d8: 33 09 f9 40 sub s2, s2, a5 -800008dc: 23 26 11 00 sw ra, 12(sp) -800008e0: 23 22 91 00 sw s1, 4(sp) -800008e4: 13 59 29 40 srai s2, s2, 2 -800008e8: 63 00 09 02 beqz s2, 32 -800008ec: 13 04 04 00 mv s0, s0 -800008f0: 93 04 00 00 mv s1, zero -800008f4: 83 27 04 00 lw a5, 0(s0) -800008f8: 93 84 14 00 addi s1, s1, 1 -800008fc: 13 04 44 00 addi s0, s0, 4 -80000900: e7 80 07 00 jalr a5 -80000904: e3 18 99 fe bne s2, s1, -16 -80000908: 37 14 00 80 lui s0, 524289 -8000090c: 37 19 00 80 lui s2, 524289 -80000910: 93 07 04 00 mv a5, s0 -80000914: 13 09 49 00 addi s2, s2, 4 -80000918: 33 09 f9 40 sub s2, s2, a5 -8000091c: 13 59 29 40 srai s2, s2, 2 -80000920: 63 00 09 02 beqz s2, 32 -80000924: 13 04 04 00 mv s0, s0 -80000928: 93 04 00 00 mv s1, zero -8000092c: 83 27 04 00 lw a5, 0(s0) -80000930: 93 84 14 00 addi s1, s1, 1 -80000934: 13 04 44 00 addi s0, s0, 4 -80000938: e7 80 07 00 jalr a5 -8000093c: e3 18 99 fe bne s2, s1, -16 -80000940: 83 20 c1 00 lw ra, 12(sp) -80000944: 03 24 81 00 lw s0, 8(sp) -80000948: 83 24 41 00 lw s1, 4(sp) -8000094c: 03 29 01 00 lw s2, 0(sp) -80000950: 13 01 01 01 addi sp, sp, 16 -80000954: 67 80 00 00 ret +80000598 vx_spawn_kernel: +80000598: 13 01 01 fd addi sp, sp, -48 +8000059c: 23 26 11 02 sw ra, 44(sp) +800005a0: 23 24 81 02 sw s0, 40(sp) +800005a4: 23 22 91 02 sw s1, 36(sp) +800005a8: 23 20 21 03 sw s2, 32(sp) +800005ac: f3 28 20 fc csrr a7, 4034 +800005b0: 73 23 10 fc csrr t1, 4033 +800005b4: f3 24 00 fc csrr s1, 4032 +800005b8: f3 27 50 cc csrr a5, 3269 +800005bc: 13 07 f0 01 addi a4, zero, 31 +800005c0: 63 46 f7 0e blt a4, a5, 236 +800005c4: 03 2e 05 00 lw t3, 0(a0) +800005c8: 83 26 45 00 lw a3, 4(a0) +800005cc: 03 28 85 00 lw a6, 8(a0) +800005d0: b3 0e 93 02 mul t4, t1, s1 +800005d4: 13 07 10 00 addi a4, zero, 1 +800005d8: b3 06 de 02 mul a3, t3, a3 +800005dc: 33 88 06 03 mul a6, a3, a6 +800005e0: 63 d4 0e 01 bge t4, a6, 8 +800005e4: 33 47 d8 03 div a4, a6, t4 +800005e8: 63 ce e8 0c blt a7, a4, 220 +800005ec: 63 d0 e7 0c bge a5, a4, 192 +800005f0: 93 88 f8 ff addi a7, a7, -1 +800005f4: b3 4e e8 02 div t4, a6, a4 +800005f8: 13 84 0e 00 mv s0, t4 +800005fc: 63 96 f8 00 bne a7, a5, 12 +80000600: 33 67 e8 02 rem a4, a6, a4 +80000604: 33 04 d7 01 add s0, a4, t4 +80000608: 33 49 94 02 div s2, s0, s1 +8000060c: 33 64 94 02 rem s0, s0, s1 +80000610: 63 40 69 0c blt s2, t1, 192 +80000614: 93 0f 10 00 addi t6, zero, 1 +80000618: 33 4f 69 02 div t5, s2, t1 +8000061c: 63 06 0f 00 beqz t5, 12 +80000620: 93 0f 0f 00 mv t6, t5 +80000624: 33 6f 69 02 rem t5, s2, t1 +80000628: d3 f7 06 d0 fcvt.s.w fa5, a3 +8000062c: 13 07 fe ff addi a4, t3, -1 +80000630: 93 82 f6 ff addi t0, a3, -1 +80000634: d3 88 07 e0 fmv.x.w a7, fa5 +80000638: d3 77 0e d0 fcvt.s.w fa5, t3 +8000063c: 33 7e c7 01 and t3, a4, t3 +80000640: 37 17 00 80 lui a4, 524289 +80000644: 53 88 07 e0 fmv.x.w a6, fa5 +80000648: b3 f6 d2 00 and a3, t0, a3 +8000064c: 93 d8 78 41 srai a7, a7, 23 +80000650: 13 58 78 41 srai a6, a6, 23 +80000654: 13 07 47 43 addi a4, a4, 1076 +80000658: 93 b6 16 00 seqz a3, a3 +8000065c: 13 3e 1e 00 seqz t3, t3 +80000660: 93 88 18 f8 addi a7, a7, -127 +80000664: 13 08 18 f8 addi a6, a6, -127 +80000668: 23 20 a1 00 sw a0, 0(sp) +8000066c: 23 22 b1 00 sw a1, 4(sp) +80000670: 23 24 c1 00 sw a2, 8(sp) +80000674: 23 28 f1 01 sw t6, 16(sp) +80000678: 23 2a e1 01 sw t5, 20(sp) +8000067c: 23 2c 01 00 sw zero, 24(sp) +80000680: 23 0e d1 00 sb a3, 28(sp) +80000684: a3 0e c1 01 sb t3, 29(sp) +80000688: 23 0f 11 01 sb a7, 30(sp) +8000068c: a3 0f 01 01 sb a6, 31(sp) +80000690: b3 8e fe 02 mul t4, t4, a5 +80000694: 93 97 27 00 slli a5, a5, 2 +80000698: b3 07 f7 00 add a5, a4, a5 +8000069c: 23 a0 27 00 sw sp, 0(a5) +800006a0: 23 26 d1 01 sw t4, 12(sp) +800006a4: 63 4c 20 03 bgtz s2, 56 +800006a8: 63 16 04 06 bnez s0, 108 +800006ac: 83 20 c1 02 lw ra, 44(sp) +800006b0: 03 24 81 02 lw s0, 40(sp) +800006b4: 83 24 41 02 lw s1, 36(sp) +800006b8: 03 29 01 02 lw s2, 32(sp) +800006bc: 13 01 01 03 addi sp, sp, 48 +800006c0: 67 80 00 00 ret +800006c4: 13 87 08 00 mv a4, a7 +800006c8: e3 c4 e7 f2 blt a5, a4, -216 +800006cc: 6f f0 1f fe j -32 +800006d0: 13 0f 00 00 mv t5, zero +800006d4: 93 0f 10 00 addi t6, zero, 1 +800006d8: 6f f0 1f f5 j -176 +800006dc: 13 07 09 00 mv a4, s2 +800006e0: 63 54 23 01 bge t1, s2, 8 +800006e4: 13 07 03 00 mv a4, t1 +800006e8: b7 07 00 80 lui a5, 524288 +800006ec: 23 2c e1 00 sw a4, 24(sp) +800006f0: 93 87 c7 56 addi a5, a5, 1388 +800006f4: 6b 10 f7 00 vx_wspawn a4, a5 +800006f8: 93 07 f0 ff addi a5, zero, -1 +800006fc: 6b 80 07 00 vx_tmc a5 +80000700: ef f0 df c8 jal -884 +80000704: f3 27 30 cc csrr a5, 3267 +80000708: 93 b7 17 00 seqz a5, a5 +8000070c: 6b 80 07 00 vx_tmc a5 +80000710: e3 0e 04 f8 beqz s0, -100 +80000714: b3 04 99 02 mul s1, s2, s1 +80000718: 13 09 10 00 addi s2, zero, 1 +8000071c: 33 14 89 00 sll s0, s2, s0 +80000720: 13 04 f4 ff addi s0, s0, -1 +80000724: 23 26 91 00 sw s1, 12(sp) +80000728: 6b 00 04 00 vx_tmc s0 +8000072c: ef f0 df d9 jal -612 +80000730: 6b 00 09 00 vx_tmc s2 +80000734: 83 20 c1 02 lw ra, 44(sp) +80000738: 03 24 81 02 lw s0, 40(sp) +8000073c: 83 24 41 02 lw s1, 36(sp) +80000740: 03 29 01 02 lw s2, 32(sp) +80000744: 13 01 01 03 addi sp, sp, 48 +80000748: 67 80 00 00 ret -80000958 memset: -80000958: 13 03 f0 00 addi t1, zero, 15 -8000095c: 13 07 05 00 mv a4, a0 -80000960: 63 7e c3 02 bgeu t1, a2, 60 -80000964: 93 77 f7 00 andi a5, a4, 15 -80000968: 63 90 07 0a bnez a5, 160 -8000096c: 63 92 05 08 bnez a1, 132 -80000970: 93 76 06 ff andi a3, a2, -16 -80000974: 13 76 f6 00 andi a2, a2, 15 -80000978: b3 86 e6 00 add a3, a3, a4 -8000097c: 23 20 b7 00 sw a1, 0(a4) -80000980: 23 22 b7 00 sw a1, 4(a4) -80000984: 23 24 b7 00 sw a1, 8(a4) -80000988: 23 26 b7 00 sw a1, 12(a4) -8000098c: 13 07 07 01 addi a4, a4, 16 -80000990: e3 66 d7 fe bltu a4, a3, -20 -80000994: 63 14 06 00 bnez a2, 8 -80000998: 67 80 00 00 ret -8000099c: b3 06 c3 40 sub a3, t1, a2 -800009a0: 93 96 26 00 slli a3, a3, 2 -800009a4: 97 02 00 00 auipc t0, 0 -800009a8: b3 86 56 00 add a3, a3, t0 -800009ac: 67 80 c6 00 jr 12(a3) -800009b0: 23 07 b7 00 sb a1, 14(a4) -800009b4: a3 06 b7 00 sb a1, 13(a4) -800009b8: 23 06 b7 00 sb a1, 12(a4) -800009bc: a3 05 b7 00 sb a1, 11(a4) -800009c0: 23 05 b7 00 sb a1, 10(a4) -800009c4: a3 04 b7 00 sb a1, 9(a4) -800009c8: 23 04 b7 00 sb a1, 8(a4) -800009cc: a3 03 b7 00 sb a1, 7(a4) -800009d0: 23 03 b7 00 sb a1, 6(a4) -800009d4: a3 02 b7 00 sb a1, 5(a4) -800009d8: 23 02 b7 00 sb a1, 4(a4) -800009dc: a3 01 b7 00 sb a1, 3(a4) -800009e0: 23 01 b7 00 sb a1, 2(a4) -800009e4: a3 00 b7 00 sb a1, 1(a4) -800009e8: 23 00 b7 00 sb a1, 0(a4) -800009ec: 67 80 00 00 ret -800009f0: 93 f5 f5 0f andi a1, a1, 255 -800009f4: 93 96 85 00 slli a3, a1, 8 -800009f8: b3 e5 d5 00 or a1, a1, a3 -800009fc: 93 96 05 01 slli a3, a1, 16 -80000a00: b3 e5 d5 00 or a1, a1, a3 -80000a04: 6f f0 df f6 j -148 -80000a08: 93 96 27 00 slli a3, a5, 2 -80000a0c: 97 02 00 00 auipc t0, 0 -80000a10: b3 86 56 00 add a3, a3, t0 -80000a14: 93 82 00 00 mv t0, ra -80000a18: e7 80 06 fa jalr -96(a3) -80000a1c: 93 80 02 00 mv ra, t0 -80000a20: 93 87 07 ff addi a5, a5, -16 -80000a24: 33 07 f7 40 sub a4, a4, a5 -80000a28: 33 06 f6 00 add a2, a2, a5 -80000a2c: e3 78 c3 f6 bgeu t1, a2, -144 -80000a30: 6f f0 df f3 j -196 +8000074c vx_perf_dump: +8000074c: f3 27 50 cc csrr a5, 3269 +80000750: 37 07 ff 00 lui a4, 4080 +80000754: b3 87 e7 00 add a5, a5, a4 +80000758: 93 97 87 00 slli a5, a5, 8 +8000075c: 73 27 00 b0 csrr a4, mcycle +80000760: 23 a0 e7 00 sw a4, 0(a5) +80000764: 73 27 10 b0 csrr a4, 2817 +80000768: 23 a2 e7 00 sw a4, 4(a5) +8000076c: 73 27 20 b0 csrr a4, minstret +80000770: 23 a4 e7 00 sw a4, 8(a5) +80000774: 73 27 30 b0 csrr a4, mhpmcounter3 +80000778: 23 a6 e7 00 sw a4, 12(a5) +8000077c: 73 27 40 b0 csrr a4, mhpmcounter4 +80000780: 23 a8 e7 00 sw a4, 16(a5) +80000784: 73 27 50 b0 csrr a4, mhpmcounter5 +80000788: 23 aa e7 00 sw a4, 20(a5) +8000078c: 73 27 60 b0 csrr a4, mhpmcounter6 +80000790: 23 ac e7 00 sw a4, 24(a5) +80000794: 73 27 70 b0 csrr a4, mhpmcounter7 +80000798: 23 ae e7 00 sw a4, 28(a5) +8000079c: 73 27 80 b0 csrr a4, mhpmcounter8 +800007a0: 23 a0 e7 02 sw a4, 32(a5) +800007a4: 73 27 90 b0 csrr a4, mhpmcounter9 +800007a8: 23 a2 e7 02 sw a4, 36(a5) +800007ac: 73 27 a0 b0 csrr a4, mhpmcounter10 +800007b0: 23 a4 e7 02 sw a4, 40(a5) +800007b4: 73 27 b0 b0 csrr a4, mhpmcounter11 +800007b8: 23 a6 e7 02 sw a4, 44(a5) +800007bc: 73 27 c0 b0 csrr a4, mhpmcounter12 +800007c0: 23 a8 e7 02 sw a4, 48(a5) +800007c4: 73 27 d0 b0 csrr a4, mhpmcounter13 +800007c8: 23 aa e7 02 sw a4, 52(a5) +800007cc: 73 27 e0 b0 csrr a4, mhpmcounter14 +800007d0: 23 ac e7 02 sw a4, 56(a5) +800007d4: 73 27 f0 b0 csrr a4, mhpmcounter15 +800007d8: 23 ae e7 02 sw a4, 60(a5) +800007dc: 73 27 00 b1 csrr a4, mhpmcounter16 +800007e0: 23 a0 e7 04 sw a4, 64(a5) +800007e4: 73 27 10 b1 csrr a4, mhpmcounter17 +800007e8: 23 a2 e7 04 sw a4, 68(a5) +800007ec: 73 27 20 b1 csrr a4, mhpmcounter18 +800007f0: 23 a4 e7 04 sw a4, 72(a5) +800007f4: 73 27 30 b1 csrr a4, mhpmcounter19 +800007f8: 23 a6 e7 04 sw a4, 76(a5) +800007fc: 73 27 40 b1 csrr a4, mhpmcounter20 +80000800: 23 a8 e7 04 sw a4, 80(a5) +80000804: 73 27 50 b1 csrr a4, mhpmcounter21 +80000808: 23 aa e7 04 sw a4, 84(a5) +8000080c: 73 27 60 b1 csrr a4, mhpmcounter22 +80000810: 23 ac e7 04 sw a4, 88(a5) +80000814: 73 27 70 b1 csrr a4, mhpmcounter23 +80000818: 23 ae e7 04 sw a4, 92(a5) +8000081c: 73 27 80 b1 csrr a4, mhpmcounter24 +80000820: 23 a0 e7 06 sw a4, 96(a5) +80000824: 73 27 90 b1 csrr a4, mhpmcounter25 +80000828: 23 a2 e7 06 sw a4, 100(a5) +8000082c: 73 27 a0 b1 csrr a4, mhpmcounter26 +80000830: 23 a4 e7 06 sw a4, 104(a5) +80000834: 73 27 b0 b1 csrr a4, mhpmcounter27 +80000838: 23 a6 e7 06 sw a4, 108(a5) +8000083c: 73 27 c0 b1 csrr a4, mhpmcounter28 +80000840: 23 a8 e7 06 sw a4, 112(a5) +80000844: 73 27 d0 b1 csrr a4, mhpmcounter29 +80000848: 23 aa e7 06 sw a4, 116(a5) +8000084c: 73 27 e0 b1 csrr a4, mhpmcounter30 +80000850: 23 ac e7 06 sw a4, 120(a5) +80000854: 73 27 f0 b1 csrr a4, mhpmcounter31 +80000858: 23 ae e7 06 sw a4, 124(a5) +8000085c: 73 27 00 b8 csrr a4, mcycleh +80000860: 23 a0 e7 08 sw a4, 128(a5) +80000864: 73 27 10 b8 csrr a4, 2945 +80000868: 23 a2 e7 08 sw a4, 132(a5) +8000086c: 73 27 20 b8 csrr a4, minstreth +80000870: 23 a4 e7 08 sw a4, 136(a5) +80000874: 73 27 30 b8 csrr a4, mhpmcounter3h +80000878: 23 a6 e7 08 sw a4, 140(a5) +8000087c: 73 27 40 b8 csrr a4, mhpmcounter4h +80000880: 23 a8 e7 08 sw a4, 144(a5) +80000884: 73 27 50 b8 csrr a4, mhpmcounter5h +80000888: 23 aa e7 08 sw a4, 148(a5) +8000088c: 73 27 60 b8 csrr a4, mhpmcounter6h +80000890: 23 ac e7 08 sw a4, 152(a5) +80000894: 73 27 70 b8 csrr a4, mhpmcounter7h +80000898: 23 ae e7 08 sw a4, 156(a5) +8000089c: 73 27 80 b8 csrr a4, mhpmcounter8h +800008a0: 23 a0 e7 0a sw a4, 160(a5) +800008a4: 73 27 90 b8 csrr a4, mhpmcounter9h +800008a8: 23 a2 e7 0a sw a4, 164(a5) +800008ac: 73 27 a0 b8 csrr a4, mhpmcounter10h +800008b0: 23 a4 e7 0a sw a4, 168(a5) +800008b4: 73 27 b0 b8 csrr a4, mhpmcounter11h +800008b8: 23 a6 e7 0a sw a4, 172(a5) +800008bc: 73 27 c0 b8 csrr a4, mhpmcounter12h +800008c0: 23 a8 e7 0a sw a4, 176(a5) +800008c4: 73 27 d0 b8 csrr a4, mhpmcounter13h +800008c8: 23 aa e7 0a sw a4, 180(a5) +800008cc: 73 27 e0 b8 csrr a4, mhpmcounter14h +800008d0: 23 ac e7 0a sw a4, 184(a5) +800008d4: 73 27 f0 b8 csrr a4, mhpmcounter15h +800008d8: 23 ae e7 0a sw a4, 188(a5) +800008dc: 73 27 00 b9 csrr a4, mhpmcounter16h +800008e0: 23 a0 e7 0c sw a4, 192(a5) +800008e4: 73 27 10 b9 csrr a4, mhpmcounter17h +800008e8: 23 a2 e7 0c sw a4, 196(a5) +800008ec: 73 27 20 b9 csrr a4, mhpmcounter18h +800008f0: 23 a4 e7 0c sw a4, 200(a5) +800008f4: 73 27 30 b9 csrr a4, mhpmcounter19h +800008f8: 23 a6 e7 0c sw a4, 204(a5) +800008fc: 73 27 40 b9 csrr a4, mhpmcounter20h +80000900: 23 a8 e7 0c sw a4, 208(a5) +80000904: 73 27 50 b9 csrr a4, mhpmcounter21h +80000908: 23 aa e7 0c sw a4, 212(a5) +8000090c: 73 27 60 b9 csrr a4, mhpmcounter22h +80000910: 23 ac e7 0c sw a4, 216(a5) +80000914: 73 27 70 b9 csrr a4, mhpmcounter23h +80000918: 23 ae e7 0c sw a4, 220(a5) +8000091c: 73 27 80 b9 csrr a4, mhpmcounter24h +80000920: 23 a0 e7 0e sw a4, 224(a5) +80000924: 73 27 90 b9 csrr a4, mhpmcounter25h +80000928: 23 a2 e7 0e sw a4, 228(a5) +8000092c: 73 27 a0 b9 csrr a4, mhpmcounter26h +80000930: 23 a4 e7 0e sw a4, 232(a5) +80000934: 73 27 b0 b9 csrr a4, mhpmcounter27h +80000938: 23 a6 e7 0e sw a4, 236(a5) +8000093c: 73 27 c0 b9 csrr a4, mhpmcounter28h +80000940: 23 a8 e7 0e sw a4, 240(a5) +80000944: 73 27 d0 b9 csrr a4, mhpmcounter29h +80000948: 23 aa e7 0e sw a4, 244(a5) +8000094c: 73 27 e0 b9 csrr a4, mhpmcounter30h +80000950: 23 ac e7 0e sw a4, 248(a5) +80000954: 73 27 f0 b9 csrr a4, mhpmcounter31h +80000958: 23 ae e7 0e sw a4, 252(a5) +8000095c: 67 80 00 00 ret -80000a34 __register_exitproc: -80000a34: b7 17 00 80 lui a5, 524289 -80000a38: 03 a7 07 43 lw a4, 1072(a5) -80000a3c: 83 27 87 14 lw a5, 328(a4) -80000a40: 63 8c 07 04 beqz a5, 88 -80000a44: 03 a7 47 00 lw a4, 4(a5) -80000a48: 13 08 f0 01 addi a6, zero, 31 -80000a4c: 63 4e e8 06 blt a6, a4, 124 -80000a50: 13 18 27 00 slli a6, a4, 2 -80000a54: 63 06 05 02 beqz a0, 44 -80000a58: 33 83 07 01 add t1, a5, a6 -80000a5c: 23 24 c3 08 sw a2, 136(t1) -80000a60: 83 a8 87 18 lw a7, 392(a5) -80000a64: 13 06 10 00 addi a2, zero, 1 -80000a68: 33 16 e6 00 sll a2, a2, a4 -80000a6c: b3 e8 c8 00 or a7, a7, a2 -80000a70: 23 a4 17 19 sw a7, 392(a5) -80000a74: 23 24 d3 10 sw a3, 264(t1) -80000a78: 93 06 20 00 addi a3, zero, 2 -80000a7c: 63 04 d5 02 beq a0, a3, 40 -80000a80: 13 07 17 00 addi a4, a4, 1 -80000a84: 23 a2 e7 00 sw a4, 4(a5) -80000a88: b3 87 07 01 add a5, a5, a6 -80000a8c: 23 a4 b7 00 sw a1, 8(a5) -80000a90: 13 05 00 00 mv a0, zero -80000a94: 67 80 00 00 ret -80000a98: 93 07 c7 14 addi a5, a4, 332 -80000a9c: 23 24 f7 14 sw a5, 328(a4) -80000aa0: 6f f0 5f fa j -92 -80000aa4: 83 a6 c7 18 lw a3, 396(a5) -80000aa8: 13 07 17 00 addi a4, a4, 1 -80000aac: 23 a2 e7 00 sw a4, 4(a5) -80000ab0: 33 e6 c6 00 or a2, a3, a2 -80000ab4: 23 a6 c7 18 sw a2, 396(a5) -80000ab8: b3 87 07 01 add a5, a5, a6 -80000abc: 23 a4 b7 00 sw a1, 8(a5) -80000ac0: 13 05 00 00 mv a0, zero -80000ac4: 67 80 00 00 ret -80000ac8: 13 05 f0 ff addi a0, zero, -1 -80000acc: 67 80 00 00 ret +80000960 atexit: +80000960: 93 05 05 00 mv a1, a0 +80000964: 93 06 00 00 mv a3, zero +80000968: 13 06 00 00 mv a2, zero +8000096c: 13 05 00 00 mv a0, zero +80000970: 6f 00 40 11 j 276 -80000ad0 __call_exitprocs: -80000ad0: 13 01 01 fd addi sp, sp, -48 -80000ad4: b7 17 00 80 lui a5, 524289 -80000ad8: 23 2c 41 01 sw s4, 24(sp) -80000adc: 03 aa 07 43 lw s4, 1072(a5) -80000ae0: 23 20 21 03 sw s2, 32(sp) -80000ae4: 23 26 11 02 sw ra, 44(sp) -80000ae8: 03 29 8a 14 lw s2, 328(s4) -80000aec: 23 24 81 02 sw s0, 40(sp) -80000af0: 23 22 91 02 sw s1, 36(sp) -80000af4: 23 2e 31 01 sw s3, 28(sp) -80000af8: 23 2a 51 01 sw s5, 20(sp) -80000afc: 23 28 61 01 sw s6, 16(sp) -80000b00: 23 26 71 01 sw s7, 12(sp) -80000b04: 23 24 81 01 sw s8, 8(sp) -80000b08: 63 00 09 04 beqz s2, 64 -80000b0c: 13 0b 05 00 mv s6, a0 -80000b10: 93 8b 05 00 mv s7, a1 -80000b14: 93 0a 10 00 addi s5, zero, 1 -80000b18: 93 09 f0 ff addi s3, zero, -1 -80000b1c: 83 24 49 00 lw s1, 4(s2) -80000b20: 13 84 f4 ff addi s0, s1, -1 -80000b24: 63 42 04 02 bltz s0, 36 -80000b28: 93 94 24 00 slli s1, s1, 2 -80000b2c: b3 04 99 00 add s1, s2, s1 -80000b30: 63 84 0b 04 beqz s7, 72 -80000b34: 83 a7 44 10 lw a5, 260(s1) -80000b38: 63 80 77 05 beq a5, s7, 64 -80000b3c: 13 04 f4 ff addi s0, s0, -1 -80000b40: 93 84 c4 ff addi s1, s1, -4 -80000b44: e3 16 34 ff bne s0, s3, -20 -80000b48: 83 20 c1 02 lw ra, 44(sp) -80000b4c: 03 24 81 02 lw s0, 40(sp) -80000b50: 83 24 41 02 lw s1, 36(sp) -80000b54: 03 29 01 02 lw s2, 32(sp) -80000b58: 83 29 c1 01 lw s3, 28(sp) -80000b5c: 03 2a 81 01 lw s4, 24(sp) -80000b60: 83 2a 41 01 lw s5, 20(sp) -80000b64: 03 2b 01 01 lw s6, 16(sp) -80000b68: 83 2b c1 00 lw s7, 12(sp) -80000b6c: 03 2c 81 00 lw s8, 8(sp) -80000b70: 13 01 01 03 addi sp, sp, 48 -80000b74: 67 80 00 00 ret -80000b78: 83 27 49 00 lw a5, 4(s2) -80000b7c: 83 a6 44 00 lw a3, 4(s1) -80000b80: 93 87 f7 ff addi a5, a5, -1 -80000b84: 63 8e 87 04 beq a5, s0, 92 -80000b88: 23 a2 04 00 sw zero, 4(s1) -80000b8c: e3 88 06 fa beqz a3, -80 -80000b90: 83 27 89 18 lw a5, 392(s2) -80000b94: 33 97 8a 00 sll a4, s5, s0 -80000b98: 03 2c 49 00 lw s8, 4(s2) -80000b9c: b3 77 f7 00 and a5, a4, a5 -80000ba0: 63 92 07 02 bnez a5, 36 -80000ba4: e7 80 06 00 jalr a3 -80000ba8: 03 27 49 00 lw a4, 4(s2) -80000bac: 83 27 8a 14 lw a5, 328(s4) -80000bb0: 63 14 87 01 bne a4, s8, 8 -80000bb4: e3 04 f9 f8 beq s2, a5, -120 -80000bb8: e3 88 07 f8 beqz a5, -112 -80000bbc: 13 89 07 00 mv s2, a5 -80000bc0: 6f f0 df f5 j -164 -80000bc4: 83 27 c9 18 lw a5, 396(s2) -80000bc8: 83 a5 44 08 lw a1, 132(s1) -80000bcc: 33 77 f7 00 and a4, a4, a5 -80000bd0: 63 1c 07 00 bnez a4, 24 -80000bd4: 13 05 0b 00 mv a0, s6 -80000bd8: e7 80 06 00 jalr a3 -80000bdc: 6f f0 df fc j -52 -80000be0: 23 22 89 00 sw s0, 4(s2) -80000be4: 6f f0 9f fa j -88 -80000be8: 13 85 05 00 mv a0, a1 -80000bec: e7 80 06 00 jalr a3 -80000bf0: 6f f0 9f fb j -72 +80000974 exit: +80000974: 13 01 01 ff addi sp, sp, -16 +80000978: 93 05 00 00 mv a1, zero +8000097c: 23 24 81 00 sw s0, 8(sp) +80000980: 23 26 11 00 sw ra, 12(sp) +80000984: 13 04 05 00 mv s0, a0 +80000988: ef 00 80 19 jal 408 +8000098c: b7 17 00 80 lui a5, 524289 +80000990: 03 a5 07 43 lw a0, 1072(a5) +80000994: 83 27 c5 03 lw a5, 60(a0) +80000998: 63 84 07 00 beqz a5, 8 +8000099c: e7 80 07 00 jalr a5 +800009a0: 13 05 04 00 mv a0, s0 +800009a4: ef f0 5f 8a jal -1884 + +800009a8 memset: +800009a8: 13 03 f0 00 addi t1, zero, 15 +800009ac: 13 07 05 00 mv a4, a0 +800009b0: 63 7e c3 02 bgeu t1, a2, 60 +800009b4: 93 77 f7 00 andi a5, a4, 15 +800009b8: 63 90 07 0a bnez a5, 160 +800009bc: 63 92 05 08 bnez a1, 132 +800009c0: 93 76 06 ff andi a3, a2, -16 +800009c4: 13 76 f6 00 andi a2, a2, 15 +800009c8: b3 86 e6 00 add a3, a3, a4 +800009cc: 23 20 b7 00 sw a1, 0(a4) +800009d0: 23 22 b7 00 sw a1, 4(a4) +800009d4: 23 24 b7 00 sw a1, 8(a4) +800009d8: 23 26 b7 00 sw a1, 12(a4) +800009dc: 13 07 07 01 addi a4, a4, 16 +800009e0: e3 66 d7 fe bltu a4, a3, -20 +800009e4: 63 14 06 00 bnez a2, 8 +800009e8: 67 80 00 00 ret +800009ec: b3 06 c3 40 sub a3, t1, a2 +800009f0: 93 96 26 00 slli a3, a3, 2 +800009f4: 97 02 00 00 auipc t0, 0 +800009f8: b3 86 56 00 add a3, a3, t0 +800009fc: 67 80 c6 00 jr 12(a3) +80000a00: 23 07 b7 00 sb a1, 14(a4) +80000a04: a3 06 b7 00 sb a1, 13(a4) +80000a08: 23 06 b7 00 sb a1, 12(a4) +80000a0c: a3 05 b7 00 sb a1, 11(a4) +80000a10: 23 05 b7 00 sb a1, 10(a4) +80000a14: a3 04 b7 00 sb a1, 9(a4) +80000a18: 23 04 b7 00 sb a1, 8(a4) +80000a1c: a3 03 b7 00 sb a1, 7(a4) +80000a20: 23 03 b7 00 sb a1, 6(a4) +80000a24: a3 02 b7 00 sb a1, 5(a4) +80000a28: 23 02 b7 00 sb a1, 4(a4) +80000a2c: a3 01 b7 00 sb a1, 3(a4) +80000a30: 23 01 b7 00 sb a1, 2(a4) +80000a34: a3 00 b7 00 sb a1, 1(a4) +80000a38: 23 00 b7 00 sb a1, 0(a4) +80000a3c: 67 80 00 00 ret +80000a40: 93 f5 f5 0f andi a1, a1, 255 +80000a44: 93 96 85 00 slli a3, a1, 8 +80000a48: b3 e5 d5 00 or a1, a1, a3 +80000a4c: 93 96 05 01 slli a3, a1, 16 +80000a50: b3 e5 d5 00 or a1, a1, a3 +80000a54: 6f f0 df f6 j -148 +80000a58: 93 96 27 00 slli a3, a5, 2 +80000a5c: 97 02 00 00 auipc t0, 0 +80000a60: b3 86 56 00 add a3, a3, t0 +80000a64: 93 82 00 00 mv t0, ra +80000a68: e7 80 06 fa jalr -96(a3) +80000a6c: 93 80 02 00 mv ra, t0 +80000a70: 93 87 07 ff addi a5, a5, -16 +80000a74: 33 07 f7 40 sub a4, a4, a5 +80000a78: 33 06 f6 00 add a2, a2, a5 +80000a7c: e3 78 c3 f6 bgeu t1, a2, -144 +80000a80: 6f f0 df f3 j -196 + +80000a84 __register_exitproc: +80000a84: b7 17 00 80 lui a5, 524289 +80000a88: 03 a7 07 43 lw a4, 1072(a5) +80000a8c: 83 27 87 14 lw a5, 328(a4) +80000a90: 63 8c 07 04 beqz a5, 88 +80000a94: 03 a7 47 00 lw a4, 4(a5) +80000a98: 13 08 f0 01 addi a6, zero, 31 +80000a9c: 63 4e e8 06 blt a6, a4, 124 +80000aa0: 13 18 27 00 slli a6, a4, 2 +80000aa4: 63 06 05 02 beqz a0, 44 +80000aa8: 33 83 07 01 add t1, a5, a6 +80000aac: 23 24 c3 08 sw a2, 136(t1) +80000ab0: 83 a8 87 18 lw a7, 392(a5) +80000ab4: 13 06 10 00 addi a2, zero, 1 +80000ab8: 33 16 e6 00 sll a2, a2, a4 +80000abc: b3 e8 c8 00 or a7, a7, a2 +80000ac0: 23 a4 17 19 sw a7, 392(a5) +80000ac4: 23 24 d3 10 sw a3, 264(t1) +80000ac8: 93 06 20 00 addi a3, zero, 2 +80000acc: 63 04 d5 02 beq a0, a3, 40 +80000ad0: 13 07 17 00 addi a4, a4, 1 +80000ad4: 23 a2 e7 00 sw a4, 4(a5) +80000ad8: b3 87 07 01 add a5, a5, a6 +80000adc: 23 a4 b7 00 sw a1, 8(a5) +80000ae0: 13 05 00 00 mv a0, zero +80000ae4: 67 80 00 00 ret +80000ae8: 93 07 c7 14 addi a5, a4, 332 +80000aec: 23 24 f7 14 sw a5, 328(a4) +80000af0: 6f f0 5f fa j -92 +80000af4: 83 a6 c7 18 lw a3, 396(a5) +80000af8: 13 07 17 00 addi a4, a4, 1 +80000afc: 23 a2 e7 00 sw a4, 4(a5) +80000b00: 33 e6 c6 00 or a2, a3, a2 +80000b04: 23 a6 c7 18 sw a2, 396(a5) +80000b08: b3 87 07 01 add a5, a5, a6 +80000b0c: 23 a4 b7 00 sw a1, 8(a5) +80000b10: 13 05 00 00 mv a0, zero +80000b14: 67 80 00 00 ret +80000b18: 13 05 f0 ff addi a0, zero, -1 +80000b1c: 67 80 00 00 ret + +80000b20 __call_exitprocs: +80000b20: 13 01 01 fd addi sp, sp, -48 +80000b24: b7 17 00 80 lui a5, 524289 +80000b28: 23 2c 41 01 sw s4, 24(sp) +80000b2c: 03 aa 07 43 lw s4, 1072(a5) +80000b30: 23 20 21 03 sw s2, 32(sp) +80000b34: 23 26 11 02 sw ra, 44(sp) +80000b38: 03 29 8a 14 lw s2, 328(s4) +80000b3c: 23 24 81 02 sw s0, 40(sp) +80000b40: 23 22 91 02 sw s1, 36(sp) +80000b44: 23 2e 31 01 sw s3, 28(sp) +80000b48: 23 2a 51 01 sw s5, 20(sp) +80000b4c: 23 28 61 01 sw s6, 16(sp) +80000b50: 23 26 71 01 sw s7, 12(sp) +80000b54: 23 24 81 01 sw s8, 8(sp) +80000b58: 63 00 09 04 beqz s2, 64 +80000b5c: 13 0b 05 00 mv s6, a0 +80000b60: 93 8b 05 00 mv s7, a1 +80000b64: 93 0a 10 00 addi s5, zero, 1 +80000b68: 93 09 f0 ff addi s3, zero, -1 +80000b6c: 83 24 49 00 lw s1, 4(s2) +80000b70: 13 84 f4 ff addi s0, s1, -1 +80000b74: 63 42 04 02 bltz s0, 36 +80000b78: 93 94 24 00 slli s1, s1, 2 +80000b7c: b3 04 99 00 add s1, s2, s1 +80000b80: 63 84 0b 04 beqz s7, 72 +80000b84: 83 a7 44 10 lw a5, 260(s1) +80000b88: 63 80 77 05 beq a5, s7, 64 +80000b8c: 13 04 f4 ff addi s0, s0, -1 +80000b90: 93 84 c4 ff addi s1, s1, -4 +80000b94: e3 16 34 ff bne s0, s3, -20 +80000b98: 83 20 c1 02 lw ra, 44(sp) +80000b9c: 03 24 81 02 lw s0, 40(sp) +80000ba0: 83 24 41 02 lw s1, 36(sp) +80000ba4: 03 29 01 02 lw s2, 32(sp) +80000ba8: 83 29 c1 01 lw s3, 28(sp) +80000bac: 03 2a 81 01 lw s4, 24(sp) +80000bb0: 83 2a 41 01 lw s5, 20(sp) +80000bb4: 03 2b 01 01 lw s6, 16(sp) +80000bb8: 83 2b c1 00 lw s7, 12(sp) +80000bbc: 03 2c 81 00 lw s8, 8(sp) +80000bc0: 13 01 01 03 addi sp, sp, 48 +80000bc4: 67 80 00 00 ret +80000bc8: 83 27 49 00 lw a5, 4(s2) +80000bcc: 83 a6 44 00 lw a3, 4(s1) +80000bd0: 93 87 f7 ff addi a5, a5, -1 +80000bd4: 63 8e 87 04 beq a5, s0, 92 +80000bd8: 23 a2 04 00 sw zero, 4(s1) +80000bdc: e3 88 06 fa beqz a3, -80 +80000be0: 83 27 89 18 lw a5, 392(s2) +80000be4: 33 97 8a 00 sll a4, s5, s0 +80000be8: 03 2c 49 00 lw s8, 4(s2) +80000bec: b3 77 f7 00 and a5, a4, a5 +80000bf0: 63 92 07 02 bnez a5, 36 +80000bf4: e7 80 06 00 jalr a3 +80000bf8: 03 27 49 00 lw a4, 4(s2) +80000bfc: 83 27 8a 14 lw a5, 328(s4) +80000c00: 63 14 87 01 bne a4, s8, 8 +80000c04: e3 04 f9 f8 beq s2, a5, -120 +80000c08: e3 88 07 f8 beqz a5, -112 +80000c0c: 13 89 07 00 mv s2, a5 +80000c10: 6f f0 df f5 j -164 +80000c14: 83 27 c9 18 lw a5, 396(s2) +80000c18: 83 a5 44 08 lw a1, 132(s1) +80000c1c: 33 77 f7 00 and a4, a4, a5 +80000c20: 63 1c 07 00 bnez a4, 24 +80000c24: 13 05 0b 00 mv a0, s6 +80000c28: e7 80 06 00 jalr a3 +80000c2c: 6f f0 df fc j -52 +80000c30: 23 22 89 00 sw s0, 4(s2) +80000c34: 6f f0 9f fa j -88 +80000c38: 13 85 05 00 mv a0, a1 +80000c3c: e7 80 06 00 jalr a3 +80000c40: 6f f0 9f fb j -72 Disassembly of section .init_array: @@ -879,25 +905,25 @@ Disassembly of section .comment: 36: 6a 65 38: 63 74 2e 67 bgeu t3, s2, 1640 3c: 69 74 - 3e: 20 65 - 40: 66 33 - 42: 32 63 - 44: 36 31 - 46: 31 61 - 48: 61 32 - 4a: 31 34 - 4c: 64 65 - 4e: 61 38 - 50: 35 35 - 52: 33 36 34 65 - 56: 66 64 - 58: 37 62 61 34 lui tp, 214550 - 5c: 35 31 - 5e: 65 63 - 60: 35 65 - 62: 63 33 66 37 - 66: 34 29 - 68: 00 47 + 3e: 20 32 + 40: 61 32 + 42: 33 65 66 61 + 46: 63 33 35 32 + 4a: 66 39 + 4c: 31 39 + 4e: 65 62 + 50: 64 31 + 52: 65 63 + 54: 31 62 + 56: 65 34 + 58: 35 31 + 5a: 34 36 + 5c: 64 36 + 5e: 61 39 + 60: 66 61 + 62: 32 31 + 64: 62 35 + 66: 33 29 00 47 6a: 43 43 3a 20 fmadd.s ft6, fs4, ft3, ft4, rmm 6e: 28 47 70: 4e 55 @@ -981,346 +1007,358 @@ Disassembly of section .symtab: 9e: f1 ff a0: 0e 00 a2: 00 00 - a4: 8c 02 + a4: 54 02 a6: 00 80 a8: 00 00 aa: 00 00 ac: 00 00 ae: 02 00 - b0: 15 00 - ... + b0: 1e 00 + b2: 00 00 + b4: 90 02 + b6: 00 80 + b8: 00 00 ba: 00 00 - bc: 04 00 - be: f1 ff + bc: 00 00 + be: 02 00 c0: 25 00 - c2: 00 00 - c4: 50 00 - c6: 00 80 - c8: 18 00 - ca: 00 00 - cc: 02 00 - ce: 02 00 - d0: 33 00 00 00 add zero, zero, zero ... - dc: 04 00 - de: f1 ff - e0: 57 00 00 00 + ca: 00 00 + cc: 04 00 + ce: f1 ff + d0: 35 00 + d2: 00 00 + d4: 50 00 + d6: 00 80 + d8: 18 00 + da: 00 00 + dc: 02 00 + de: 02 00 + e0: 43 00 00 00 fmadd.s ft0, ft0, ft0, ft0, rne ... ec: 04 00 ee: f1 ff - f0: 63 00 00 00 beqz zero, 0 + f0: 67 00 00 00 jr zero ... fc: 04 00 fe: f1 ff - 100: 6e 00 - 102: 00 00 - 104: 90 02 - 106: 00 80 - 108: 48 01 - 10a: 00 00 - 10c: 02 00 - 10e: 02 00 - 110: 84 00 + 100: 73 00 00 00 ecall + ... + 10c: 04 00 + 10e: f1 ff + 110: 81 00 ... 11a: 00 00 11c: 04 00 11e: f1 ff - 120: 9e 00 - ... + 120: 8c 00 + 122: 00 00 + 124: 8c 03 + 126: 00 80 + 128: 3c 01 12a: 00 00 - 12c: 04 00 - 12e: f1 ff - 130: a0 00 - ... + 12c: 02 00 + 12e: 02 00 + 130: a2 00 + 132: 00 00 + 134: c8 04 + 136: 00 80 + 138: a4 00 13a: 00 00 - 13c: 04 00 - 13e: f1 ff - 140: 8e 00 - ... + 13c: 02 00 + 13e: 02 00 + 140: b8 00 + 142: 00 00 + 144: 6c 05 + 146: 00 80 + 148: 2c 00 14a: 00 00 - 14c: 04 00 - 14e: f1 ff - 150: 95 00 + 14c: 02 00 + 14e: 02 00 + 150: cc 00 ... 15a: 00 00 15c: 04 00 15e: f1 ff - 160: 9c 00 + 160: d8 00 ... 16a: 00 00 16c: 04 00 16e: f1 ff - 170: a7 00 00 00 + 170: da 00 ... + 17a: 00 00 17c: 04 00 17e: f1 ff - 180: b0 00 - 182: 00 00 - 184: 08 10 - 186: 00 80 - 188: 28 04 - 18a: 00 00 - 18c: 01 00 - 18e: 04 00 + 180: d6 00 ... + 18a: 00 00 + 18c: 04 00 + 18e: f1 ff + 190: e1 00 + ... + 19a: 00 00 19c: 04 00 19e: f1 ff - 1a0: bc 00 + 1a0: ea 00 1a2: 00 00 - 1a4: 04 10 + 1a4: 08 10 1a6: 00 80 - 1a8: 00 00 + 1a8: 28 04 1aa: 00 00 - 1ac: 00 00 - 1ae: 03 00 cd 00 lb zero, 12(s10) - 1b2: 00 00 - 1b4: 04 10 - 1b6: 00 80 - 1b8: 00 00 - 1ba: 00 00 - 1bc: 00 00 - 1be: 03 00 e0 00 lb zero, 14(zero) + 1ac: 01 00 + 1ae: 04 00 + ... + 1bc: 04 00 + 1be: f1 ff + 1c0: f6 00 1c2: 00 00 1c4: 04 10 1c6: 00 80 1c8: 00 00 1ca: 00 00 1cc: 00 00 - 1ce: 03 00 f1 00 lb zero, 15(sp) + 1ce: 03 00 07 01 lb zero, 16(a4) 1d2: 00 00 - 1d4: 00 10 + 1d4: 04 10 1d6: 00 80 1d8: 00 00 1da: 00 00 1dc: 00 00 - 1de: 03 00 05 01 lb zero, 16(a0) + 1de: 03 00 1a 01 lb zero, 17(s4) 1e2: 00 00 - 1e4: 00 10 + 1e4: 04 10 1e6: 00 80 1e8: 00 00 1ea: 00 00 1ec: 00 00 - 1ee: 03 00 18 01 lb zero, 17(a6) + 1ee: 03 00 2b 01 lb zero, 18(s6) 1f2: 00 00 1f4: 00 10 1f6: 00 80 1f8: 00 00 1fa: 00 00 1fc: 00 00 - 1fe: 03 00 2e 01 lb zero, 18(t3) - ... + 1fe: 03 00 3f 01 lb zero, 19(t5) + 202: 00 00 + 204: 00 10 + 206: 00 80 + 208: 00 00 20a: 00 00 - 20c: 10 00 - 20e: f1 ff - 210: 3c 01 + 20c: 00 00 + 20e: 03 00 52 01 lb zero, 21(tp) 212: 00 00 - 214: 98 00 + 214: 00 10 216: 00 80 - 218: 9c 00 + 218: 00 00 21a: 00 00 - 21c: 12 00 - 21e: 02 00 - 220: 50 01 - 222: 00 00 - 224: 00 04 - 226: 00 00 - 228: 00 00 + 21c: 00 00 + 21e: 03 00 68 01 lb zero, 22(a6) + ... 22a: 00 00 22c: 10 00 22e: f1 ff - 230: 5d 01 + 230: 76 01 232: 00 00 - 234: 34 14 + 234: 98 00 236: 00 80 - 238: 80 00 + 238: 9c 00 23a: 00 00 - 23c: 11 00 - 23e: 06 00 - 240: 6b 01 00 00 - 244: 30 14 - 246: 00 80 + 23c: 12 00 + 23e: 02 00 + 240: 8a 01 + 242: 00 00 + 244: 00 04 + 246: 00 00 248: 00 00 24a: 00 00 24c: 10 00 - 24e: 05 00 - 250: 7b 01 00 00 - 254: 08 18 + 24e: f1 ff + 250: 97 01 00 00 auipc gp, 0 + 254: 34 14 256: 00 80 - 258: 00 00 + 258: 80 00 25a: 00 00 - 25c: 10 00 - 25e: f1 ff - 260: 8c 01 + 25c: 11 00 + 25e: 06 00 + 260: a5 01 262: 00 00 264: 30 14 266: 00 80 - 268: 04 00 + 268: 00 00 26a: 00 00 - 26c: 11 00 + 26c: 10 00 26e: 05 00 - 270: 9f 01 00 00 - 274: bc 08 + 270: b5 01 + 272: 00 00 + 274: 08 18 276: 00 80 - 278: 9c 00 + 278: 00 00 27a: 00 00 - 27c: 12 00 - 27e: 02 00 - 280: b1 01 + 27c: 10 00 + 27e: f1 ff + 280: c6 01 282: 00 00 - 284: 60 08 + 284: 30 14 286: 00 80 - 288: 5c 00 + 288: 04 00 28a: 00 00 - 28c: 12 00 - 28e: 02 00 - 290: c3 01 00 00 fmadd.s ft3, ft0, ft0, ft0, rne - 294: 00 00 - 296: 00 ff - 298: 00 00 + 28c: 11 00 + 28e: 05 00 + 290: d9 01 + 292: 00 00 + 294: 94 02 + 296: 00 80 + 298: 9c 00 29a: 00 00 - 29c: 10 00 - 29e: f1 ff - 2a0: cf 01 00 00 fnmadd.s ft3, ft0, ft0, ft0, rne - 2a4: 54 02 + 29c: 12 00 + 29e: 02 00 + 2a0: eb 01 00 00 vx_tex gp, zero, zero, zero, rne + 2a4: 30 03 2a6: 00 80 - 2a8: 00 00 + 2a8: 5c 00 2aa: 00 00 2ac: 12 00 2ae: 02 00 - 2b0: d9 01 + 2b0: fd 01 2b2: 00 00 - 2b4: d0 0a + 2b4: 60 02 2b6: 00 80 - 2b8: 24 01 + 2b8: 00 00 2ba: 00 00 2bc: 12 00 2be: 02 00 - 2c0: 0f 02 00 00 - 2c4: 00 00 + 2c0: 07 02 00 00 + 2c4: 20 0b 2c6: 00 80 - 2c8: 50 00 + 2c8: 24 01 2ca: 00 00 2cc: 12 00 - 2ce: 01 00 - 2d0: ea 01 + 2ce: 02 00 + 2d0: 3d 02 2d2: 00 00 - 2d4: 34 0a + 2d4: 00 00 2d6: 00 80 - 2d8: 9c 00 + 2d8: 50 00 2da: 00 00 2dc: 12 00 - 2de: 02 00 - 2e0: fe 01 + 2de: 01 00 + 2e0: 18 02 2e2: 00 00 - 2e4: b4 14 + 2e4: 84 0a 2e6: 00 80 - 2e8: 00 00 + 2e8: 9c 00 2ea: 00 00 - 2ec: 10 00 - 2ee: 06 00 - 2f0: 0a 02 + 2ec: 12 00 + 2ee: 02 00 + 2f0: 2c 02 2f2: 00 00 - 2f4: 34 14 + 2f4: b4 14 2f6: 00 80 2f8: 00 00 2fa: 00 00 2fc: 10 00 2fe: 06 00 - 300: 16 02 + 300: 38 02 302: 00 00 - 304: 58 09 + 304: 34 14 306: 00 80 - 308: dc 00 + 308: 00 00 30a: 00 00 - 30c: 12 00 - 30e: 02 00 - 310: 1d 02 + 30c: 10 00 + 30e: 06 00 + 310: 44 02 312: 00 00 - 314: 68 00 + 314: a8 09 316: 00 80 - 318: 30 00 + 318: dc 00 31a: 00 00 31c: 12 00 31e: 02 00 - 320: 22 02 - 322: 00 00 - 324: c4 01 + 320: 4b 02 00 00 fnmsub.s ft4, ft0, ft0, ft0, rne + 324: 68 00 326: 00 80 - 328: 84 00 + 328: 30 00 32a: 00 00 32c: 12 00 32e: 02 00 - 330: 45 02 + 330: 50 02 332: 00 00 - 334: 18 08 + 334: c4 01 336: 00 80 - 338: 14 00 + 338: 84 00 33a: 00 00 33c: 12 00 33e: 02 00 - 340: 4c 02 - 342: 00 00 - 344: 34 01 + 340: 73 02 00 00 + 344: 60 09 346: 00 80 - 348: 90 00 + 348: 14 00 34a: 00 00 34c: 12 00 34e: 02 00 - 350: 6a 02 + 350: 7a 02 352: 00 00 - 354: 08 10 + 354: 34 01 356: 00 80 - 358: 00 00 + 358: 90 00 35a: 00 00 - 35c: 10 00 - 35e: 04 00 - 360: 79 02 + 35c: 12 00 + 35e: 02 00 + 360: 98 02 362: 00 00 - 364: 34 14 + 364: 08 10 366: 00 80 368: 00 00 36a: 00 00 36c: 10 00 - 36e: 05 00 - 370: c8 00 - 372: 00 00 - 374: b4 14 + 36e: 04 00 + 370: a7 02 00 00 + 374: 34 14 376: 00 80 378: 00 00 37a: 00 00 37c: 10 00 - 37e: 06 00 - 380: 8e 02 + 37e: 05 00 + 380: 02 01 382: 00 00 - 384: 2c 08 + 384: b4 14 386: 00 80 - 388: 34 00 + 388: 00 00 38a: 00 00 - 38c: 12 00 - 38e: 02 00 - 390: 80 02 + 38c: 10 00 + 38e: 06 00 + 390: bc 02 392: 00 00 - 394: 04 06 + 394: 74 09 396: 00 80 - 398: 14 02 + 398: 34 00 39a: 00 00 39c: 12 00 39e: 02 00 - 3a0: 8d 02 + 3a0: ae 02 3a2: 00 00 - 3a4: 48 02 + 3a4: 4c 07 3a6: 00 80 - 3a8: 00 00 + 3a8: 14 02 3aa: 00 00 3ac: 12 00 3ae: 02 00 - 3b0: 93 02 00 00 mv t0, zero - 3b4: d8 03 + 3b0: bb 02 00 00 + 3b4: 48 02 3b6: 00 80 - 3b8: 2c 02 + 3b8: 00 00 3ba: 00 00 3bc: 12 00 3be: 02 00 + 3c0: c1 02 + 3c2: 00 00 + 3c4: 98 05 + 3c6: 00 80 + 3c8: b4 01 + 3ca: 00 00 + 3cc: 12 00 + 3ce: 02 00 Disassembly of section .strtab: @@ -1330,255 +1368,273 @@ Disassembly of section .strtab: 4: 73 74 61 72 csrrci s0, 1830, 2 8: 74 2e a: 53 2e 6f 00 fadd.s ft8, ft10, ft6, rdn - e: 52 45 - 10: 54 55 - 12: 52 4e - 14: 00 5f - 16: 5f 63 61 6c - 1a: 6c 5f - 1c: 61 74 - 1e: 65 78 - 20: 69 74 - 22: 2e 63 - 24: 00 72 - 26: 65 67 - 28: 69 73 - 2a: 74 65 - 2c: 72 5f - 2e: 66 69 - 30: 6e 69 - 32: 00 70 - 34: 6f 63 6c 5f jal t1, 812534 - 38: 76 6f - 3a: 72 74 - 3c: 65 78 - 3e: 5f 6b 65 72 - 42: 6e 65 - 44: 6c 2d - 46: 37 38 2d 36 lui a6, 221907 - 4a: 32 2d - 4c: 30 32 - 4e: 2d 39 - 50: 33 2d 63 35 - 54: 2e 63 - 56: 00 70 - 58: 61 72 - 5a: 61 6c - 5c: 6c 65 - 5e: 6c 5f - 60: 62 63 - 62: 00 76 - 64: 78 5f - 66: 73 70 61 77 csrci 1910, 2 - 6a: 6e 2e - 6c: 63 00 73 70 beq t1, t2, 1792 - 70: 61 77 - 72: 6e 5f - 74: 6b 65 72 6e - 78: 65 6c - 7a: 5f 63 61 6c - 7e: 6c 62 - 80: 61 63 - 82: 6b 00 76 78 - 86: 5f 70 65 72 - 8a: 66 2e - 8c: 63 00 66 69 beq a2, s6, 1664 - 90: 6e 69 - 92: 2e 63 - 94: 00 69 - 96: 6e 69 - 98: 74 2e - 9a: 63 00 5f 5f beq t5, s5, 1504 - 9e: 61 74 - a0: 65 78 - a2: 69 74 - a4: 2e 63 - a6: 00 69 - a8: 6d 70 - aa: 75 72 - ac: 65 2e - ae: 63 00 69 6d beq s2, s6, 1728 - b2: 70 75 - b4: 72 65 - b6: 5f 64 61 74 - ba: 61 00 - bc: 5f 5f 66 69 - c0: 6e 69 - c2: 5f 61 72 72 - c6: 61 79 - c8: 5f 65 6e 64 - cc: 00 5f - ce: 5f 66 69 6e - d2: 69 5f - d4: 61 72 - d6: 72 61 - d8: 79 5f - da: 73 74 61 72 csrrci s0, 1830, 2 - de: 74 00 - e0: 5f 5f 69 6e - e4: 69 74 - e6: 5f 61 72 72 - ea: 61 79 - ec: 5f 65 6e 64 - f0: 00 5f - f2: 5f 70 72 65 - f6: 69 6e - f8: 69 74 - fa: 5f 61 72 72 - fe: 61 79 - 100: 5f 65 6e 64 - 104: 00 5f - 106: 5f 69 6e 69 - 10a: 74 5f - 10c: 61 72 - 10e: 72 61 - 110: 79 5f - 112: 73 74 61 72 csrrci s0, 1830, 2 - 116: 74 00 - 118: 5f 5f 70 72 - 11c: 65 69 - 11e: 6e 69 - 120: 74 5f - 122: 61 72 - 124: 72 61 - 126: 79 5f - 128: 73 74 61 72 csrrci s0, 1830, 2 - 12c: 74 00 - 12e: 5f 5f 73 74 - 132: 61 63 - 134: 6b 5f 75 73 - 138: 61 67 - 13a: 65 00 - 13c: 5f 70 6f 63 - 140: 6c 5f - 142: 6b 65 72 6e - 146: 65 6c - 148: 5f 76 65 63 - 14c: 61 64 - 14e: 64 00 - 150: 5f 5f 73 74 - 154: 61 63 - 156: 6b 5f 73 69 - 15a: 7a 65 - 15c: 00 67 - 15e: 5f 77 73 70 - 162: 61 77 - 164: 6e 5f - 166: 61 72 - 168: 67 73 00 5f - 16c: 5f 53 44 41 - 170: 54 41 - 172: 5f 42 45 47 - 176: 49 4e - 178: 5f 5f 00 5f - 17c: 5f 67 6c 6f - 180: 62 61 - 182: 6c 5f - 184: 70 6f - 186: 69 6e - 188: 74 65 - 18a: 72 00 - 18c: 5f 67 6c 6f - 190: 62 61 - 192: 6c 5f - 194: 69 6d - 196: 70 75 - 198: 72 65 - 19a: 5f 70 74 72 - 19e: 00 5f - 1a0: 5f 6c 69 62 - 1a4: 63 5f 69 6e bge s2, t1, 1790 - 1a8: 69 74 - 1aa: 5f 61 72 72 - 1ae: 61 79 - 1b0: 00 5f - 1b2: 5f 6c 69 62 - 1b6: 63 5f 66 69 bge a2, s6, 1694 - 1ba: 6e 69 - 1bc: 5f 61 72 72 - 1c0: 61 79 - 1c2: 00 5f - 1c4: 5f 73 74 61 - 1c8: 63 6b 5f 74 bltu t5, t0, 1878 - 1cc: 6f 70 00 76 j 30560 - 1d0: 78 5f - 1d2: 73 65 74 5f csrrsi a0, 1527, 8 - 1d6: 73 70 00 5f csrci 1520, 0 - 1da: 5f 63 61 6c - 1de: 6c 5f - 1e0: 65 78 + e: 6c 61 + 10: 62 65 + 12: 6c 5f + 14: 65 78 + 16: 69 74 + 18: 5f 6e 65 78 + 1c: 74 00 + 1e: 52 45 + 20: 54 55 + 22: 52 4e + 24: 00 5f + 26: 5f 63 61 6c + 2a: 6c 5f + 2c: 61 74 + 2e: 65 78 + 30: 69 74 + 32: 2e 63 + 34: 00 72 + 36: 65 67 + 38: 69 73 + 3a: 74 65 + 3c: 72 5f + 3e: 66 69 + 40: 6e 69 + 42: 00 70 + 44: 6f 63 6c 5f jal t1, 812534 + 48: 76 6f + 4a: 72 74 + 4c: 65 78 + 4e: 5f 6b 65 72 + 52: 6e 65 + 54: 6c 2d + 56: 35 31 + 58: 2d 37 + 5a: 37 2d 34 63 lui s10, 406338 + 5e: 2d 31 + 60: 38 2d + 62: 61 35 + 64: 2e 63 + 66: 00 70 + 68: 61 72 + 6a: 61 6c + 6c: 6c 65 + 6e: 6c 5f + 70: 62 63 + 72: 00 76 + 74: 78 5f + 76: 73 79 73 63 csrrci s2, 1591, 6 + 7a: 61 6c + 7c: 6c 73 + 7e: 2e 63 + 80: 00 76 + 82: 78 5f + 84: 73 70 61 77 csrci 1910, 2 + 88: 6e 2e + 8a: 63 00 73 70 beq t1, t2, 1792 + 8e: 61 77 + 90: 6e 5f + 92: 6b 65 72 6e + 96: 65 6c + 98: 5f 61 6c 6c + 9c: 5f 73 74 75 + a0: 62 00 + a2: 73 70 61 77 csrci 1910, 2 + a6: 6e 5f + a8: 6b 65 72 6e + ac: 65 6c + ae: 5f 72 65 6d + b2: 5f 73 74 75 + b6: 62 00 + b8: 73 70 61 77 csrci 1910, 2 + bc: 6e 5f + be: 6b 65 72 6e + c2: 65 6c + c4: 5f 61 6c 6c + c8: 5f 63 62 00 + cc: 76 78 + ce: 5f 70 65 72 + d2: 66 2e + d4: 63 00 5f 5f beq t5, s5, 1504 + d8: 61 74 + da: 65 78 + dc: 69 74 + de: 2e 63 + e0: 00 69 + e2: 6d 70 + e4: 75 72 + e6: 65 2e + e8: 63 00 69 6d beq s2, s6, 1728 + ec: 70 75 + ee: 72 65 + f0: 5f 64 61 74 + f4: 61 00 + f6: 5f 5f 66 69 + fa: 6e 69 + fc: 5f 61 72 72 + 100: 61 79 + 102: 5f 65 6e 64 + 106: 00 5f + 108: 5f 66 69 6e + 10c: 69 5f + 10e: 61 72 + 110: 72 61 + 112: 79 5f + 114: 73 74 61 72 csrrci s0, 1830, 2 + 118: 74 00 + 11a: 5f 5f 69 6e + 11e: 69 74 + 120: 5f 61 72 72 + 124: 61 79 + 126: 5f 65 6e 64 + 12a: 00 5f + 12c: 5f 70 72 65 + 130: 69 6e + 132: 69 74 + 134: 5f 61 72 72 + 138: 61 79 + 13a: 5f 65 6e 64 + 13e: 00 5f + 140: 5f 69 6e 69 + 144: 74 5f + 146: 61 72 + 148: 72 61 + 14a: 79 5f + 14c: 73 74 61 72 csrrci s0, 1830, 2 + 150: 74 00 + 152: 5f 5f 70 72 + 156: 65 69 + 158: 6e 69 + 15a: 74 5f + 15c: 61 72 + 15e: 72 61 + 160: 79 5f + 162: 73 74 61 72 csrrci s0, 1830, 2 + 166: 74 00 + 168: 5f 5f 73 74 + 16c: 61 63 + 16e: 6b 5f 75 73 + 172: 61 67 + 174: 65 00 + 176: 5f 70 6f 63 + 17a: 6c 5f + 17c: 6b 65 72 6e + 180: 65 6c + 182: 5f 76 65 63 + 186: 61 64 + 188: 64 00 + 18a: 5f 5f 73 74 + 18e: 61 63 + 190: 6b 5f 73 69 + 194: 7a 65 + 196: 00 67 + 198: 5f 77 73 70 + 19c: 61 77 + 19e: 6e 5f + 1a0: 61 72 + 1a2: 67 73 00 5f + 1a6: 5f 53 44 41 + 1aa: 54 41 + 1ac: 5f 42 45 47 + 1b0: 49 4e + 1b2: 5f 5f 00 5f + 1b6: 5f 67 6c 6f + 1ba: 62 61 + 1bc: 6c 5f + 1be: 70 6f + 1c0: 69 6e + 1c2: 74 65 + 1c4: 72 00 + 1c6: 5f 67 6c 6f + 1ca: 62 61 + 1cc: 6c 5f + 1ce: 69 6d + 1d0: 70 75 + 1d2: 72 65 + 1d4: 5f 70 74 72 + 1d8: 00 5f + 1da: 5f 6c 69 62 + 1de: 63 5f 69 6e bge s2, t1, 1790 1e2: 69 74 - 1e4: 70 72 - 1e6: 6f 63 73 00 jal t1, 223238 - 1ea: 5f 5f 72 65 - 1ee: 67 69 73 74 - 1f2: 65 72 - 1f4: 5f 65 78 69 - 1f8: 74 70 - 1fa: 72 6f - 1fc: 63 00 5f 5f beq t5, s5, 1504 - 200: 42 53 - 202: 53 5f 45 4e - 206: 44 5f - 208: 5f 00 5f 5f - 20c: 62 73 - 20e: 73 5f 73 74 csrrwi t5, 1863, 6 - 212: 61 72 - 214: 74 00 - 216: 6d 65 - 218: 6d 73 - 21a: 65 74 - 21c: 00 6d - 21e: 61 69 - 220: 6e 00 - 222: 5f 70 6f 63 - 226: 6c 5f - 228: 6b 65 72 6e - 22c: 65 6c - 22e: 5f 76 65 63 - 232: 61 64 - 234: 64 5f - 236: 77 6f 72 6b - 23a: 67 72 6f 75 - 23e: 70 5f - 240: 66 61 - 242: 73 74 00 61 csrrci s0, 1552, 0 - 246: 74 65 - 248: 78 69 - 24a: 74 00 - 24c: 5f 70 6f 63 - 250: 6c 5f - 252: 6b 65 72 6e - 256: 65 6c - 258: 5f 76 65 63 - 25c: 61 64 - 25e: 64 5f - 260: 77 6f 72 6b - 264: 67 72 6f 75 - 268: 70 00 - 26a: 5f 5f 44 41 - 26e: 54 41 - 270: 5f 42 45 47 - 274: 49 4e - 276: 5f 5f 00 5f - 27a: 65 64 - 27c: 61 74 - 27e: 61 00 - 280: 76 78 - 282: 5f 70 65 72 - 286: 66 5f - 288: 64 75 - 28a: 6d 70 - 28c: 00 5f - 28e: 65 78 - 290: 69 74 - 292: 00 76 - 294: 78 5f - 296: 73 70 61 77 csrci 1910, 2 - 29a: 6e 5f - 29c: 6b 65 72 6e - 2a0: 65 6c - 2a2: 00 + 1e4: 5f 61 72 72 + 1e8: 61 79 + 1ea: 00 5f + 1ec: 5f 6c 69 62 + 1f0: 63 5f 66 69 bge a2, s6, 1694 + 1f4: 6e 69 + 1f6: 5f 61 72 72 + 1fa: 61 79 + 1fc: 00 76 + 1fe: 78 5f + 200: 73 65 74 5f csrrsi a0, 1527, 8 + 204: 73 70 00 5f csrci 1520, 0 + 208: 5f 63 61 6c + 20c: 6c 5f + 20e: 65 78 + 210: 69 74 + 212: 70 72 + 214: 6f 63 73 00 jal t1, 223238 + 218: 5f 5f 72 65 + 21c: 67 69 73 74 + 220: 65 72 + 222: 5f 65 78 69 + 226: 74 70 + 228: 72 6f + 22a: 63 00 5f 5f beq t5, s5, 1504 + 22e: 42 53 + 230: 53 5f 45 4e + 234: 44 5f + 236: 5f 00 5f 5f + 23a: 62 73 + 23c: 73 5f 73 74 csrrwi t5, 1863, 6 + 240: 61 72 + 242: 74 00 + 244: 6d 65 + 246: 6d 73 + 248: 65 74 + 24a: 00 6d + 24c: 61 69 + 24e: 6e 00 + 250: 5f 70 6f 63 + 254: 6c 5f + 256: 6b 65 72 6e + 25a: 65 6c + 25c: 5f 76 65 63 + 260: 61 64 + 262: 64 5f + 264: 77 6f 72 6b + 268: 67 72 6f 75 + 26c: 70 5f + 26e: 66 61 + 270: 73 74 00 61 csrrci s0, 1552, 0 + 274: 74 65 + 276: 78 69 + 278: 74 00 + 27a: 5f 70 6f 63 + 27e: 6c 5f + 280: 6b 65 72 6e + 284: 65 6c + 286: 5f 76 65 63 + 28a: 61 64 + 28c: 64 5f + 28e: 77 6f 72 6b + 292: 67 72 6f 75 + 296: 70 00 + 298: 5f 5f 44 41 + 29c: 54 41 + 29e: 5f 42 45 47 + 2a2: 49 4e + 2a4: 5f 5f 00 5f + 2a8: 65 64 + 2aa: 61 74 + 2ac: 61 00 + 2ae: 76 78 + 2b0: 5f 70 65 72 + 2b4: 66 5f + 2b6: 64 75 + 2b8: 6d 70 + 2ba: 00 5f + 2bc: 65 78 + 2be: 69 74 + 2c0: 00 76 + 2c2: 78 5f + 2c4: 73 70 61 77 csrci 1910, 2 + 2c8: 6e 5f + 2ca: 6b 65 72 6e + 2ce: 65 6c + 2d0: 00 Disassembly of section .shstrtab: diff --git a/tests/regression/basic/Makefile b/tests/regression/basic/Makefile index 139ec97d..dcf85e2d 100644 --- a/tests/regression/basic/Makefile +++ b/tests/regression/basic/Makefile @@ -45,13 +45,13 @@ run-simx: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-fpga: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-rtlsim: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/regression/basic/common.h b/tests/regression/basic/common.h index bedbface..e496cf34 100644 --- a/tests/regression/basic/common.h +++ b/tests/regression/basic/common.h @@ -3,10 +3,10 @@ #define KERNEL_ARG_DEV_MEM_ADDR 0x7ffff000 -struct kernel_arg_t { +typedef struct { uint32_t count; uint32_t src_ptr; uint32_t dst_ptr; -}; +} kernel_arg_t; #endif \ No newline at end of file diff --git a/tests/regression/basic/kernel.c b/tests/regression/basic/kernel.c index 3ac75e0b..5279d156 100644 --- a/tests/regression/basic/kernel.c +++ b/tests/regression/basic/kernel.c @@ -3,7 +3,7 @@ #include "common.h" void main() { - struct kernel_arg_t* arg = (struct kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR; + const kernel_arg_t* arg = (const kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR; uint32_t count = arg->count; int32_t* src_ptr = (int32_t*)arg->src_ptr; int32_t* dst_ptr = (int32_t*)arg->dst_ptr; diff --git a/tests/regression/demo/Makefile b/tests/regression/demo/Makefile index a78f605a..798f5780 100644 --- a/tests/regression/demo/Makefile +++ b/tests/regression/demo/Makefile @@ -45,13 +45,13 @@ run-simx: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-fpga: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-rtlsim: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/regression/demo/common.h b/tests/regression/demo/common.h index d6540ae1..3a38ae43 100644 --- a/tests/regression/demo/common.h +++ b/tests/regression/demo/common.h @@ -3,12 +3,12 @@ #define KERNEL_ARG_DEV_MEM_ADDR 0x7ffff000 -struct kernel_arg_t { +typedef struct { uint32_t num_tasks; uint32_t task_size; uint32_t src0_ptr; uint32_t src1_ptr; uint32_t dst_ptr; -}; +} kernel_arg_t; #endif \ No newline at end of file diff --git a/tests/regression/demo/kernel.c b/tests/regression/demo/kernel.c index 35b60efa..7e2b5dcd 100644 --- a/tests/regression/demo/kernel.c +++ b/tests/regression/demo/kernel.c @@ -3,12 +3,11 @@ #include #include "common.h" -void kernel_body(int task_id, void* arg) { - struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); - uint32_t count = _arg->task_size; - int32_t* src0_ptr = (int32_t*)_arg->src0_ptr; - int32_t* src1_ptr = (int32_t*)_arg->src1_ptr; - int32_t* dst_ptr = (int32_t*)_arg->dst_ptr; +void kernel_body(int task_id, const kernel_arg_t* arg) { + uint32_t count = arg->task_size; + int32_t* src0_ptr = (int32_t*)arg->src0_ptr; + int32_t* src1_ptr = (int32_t*)arg->src1_ptr; + int32_t* dst_ptr = (int32_t*)arg->dst_ptr; uint32_t offset = task_id * count; @@ -18,6 +17,6 @@ void kernel_body(int task_id, void* arg) { } void main() { - struct kernel_arg_t* arg = (struct kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR; + const kernel_arg_t* arg = (const kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR; vx_spawn_tasks(arg->num_tasks, kernel_body, arg); } \ No newline at end of file diff --git a/tests/regression/diverge/Makefile b/tests/regression/diverge/Makefile index 6c531257..679847af 100644 --- a/tests/regression/diverge/Makefile +++ b/tests/regression/diverge/Makefile @@ -45,13 +45,13 @@ run-simx: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-fpga: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-rtlsim: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/regression/diverge/common.h b/tests/regression/diverge/common.h index 73247b2c..6346c58e 100644 --- a/tests/regression/diverge/common.h +++ b/tests/regression/diverge/common.h @@ -3,10 +3,10 @@ #define KERNEL_ARG_DEV_MEM_ADDR 0x7ffff000 -struct kernel_arg_t { +typedef struct { uint32_t num_points; uint32_t src_ptr; uint32_t dst_ptr; -}; +} kernel_arg_t; #endif \ No newline at end of file diff --git a/tests/regression/diverge/kernel.c b/tests/regression/diverge/kernel.c index a71e516d..5d0745a1 100644 --- a/tests/regression/diverge/kernel.c +++ b/tests/regression/diverge/kernel.c @@ -5,10 +5,9 @@ // Parallel Selection sort -void kernel_body(int task_id, void* arg) { - struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); - int32_t* src_ptr = (int32_t*)_arg->src_ptr; - int32_t* dst_ptr = (int32_t*)_arg->dst_ptr; +void kernel_body(int task_id, const kernel_arg_t* arg) { + int32_t* src_ptr = (int32_t*)arg->src_ptr; + int32_t* dst_ptr = (int32_t*)arg->dst_ptr; int value = src_ptr[task_id]; @@ -45,6 +44,6 @@ void kernel_body(int task_id, void* arg) { } void main() { - struct kernel_arg_t* arg = (struct kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR; + const kernel_arg_t* arg = (const kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR; vx_spawn_tasks(arg->num_points, kernel_body, arg); } \ No newline at end of file diff --git a/tests/regression/dogfood/Makefile b/tests/regression/dogfood/Makefile index 2f89afc6..61113c7e 100644 --- a/tests/regression/dogfood/Makefile +++ b/tests/regression/dogfood/Makefile @@ -21,7 +21,7 @@ VX_SRCS = kernel.c #CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -pedantic -Wfatal-errors CXXFLAGS += -std=c++11 -O0 -g -Wall -Wextra -pedantic -Wfatal-errors -CXXFLAGS += -I$(VORTEX_DRV_PATH)/include +CXXFLAGS += -I$(VORTEX_DRV_PATH)/include -I$(VORTEX_RT_PATH)/../hw LDFLAGS += -L$(VORTEX_DRV_PATH)/stub -lvortex @@ -47,13 +47,13 @@ run-simx: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-fpga: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-rtlsim: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/regression/dogfood/common.h b/tests/regression/dogfood/common.h index 4f1e13f7..7e0f0b3d 100644 --- a/tests/regression/dogfood/common.h +++ b/tests/regression/dogfood/common.h @@ -3,13 +3,13 @@ #define KERNEL_ARG_DEV_MEM_ADDR 0x7ffff000 -struct kernel_arg_t { +typedef struct { uint32_t testid; uint32_t num_tasks; uint32_t task_size; uint32_t src0_ptr; uint32_t src1_ptr; uint32_t dst_ptr; -}; +} kernel_arg_t; #endif \ No newline at end of file diff --git a/tests/regression/dogfood/kernel.c b/tests/regression/dogfood/kernel.c index e5609182..f61e6a4e 100644 --- a/tests/regression/dogfood/kernel.c +++ b/tests/regression/dogfood/kernel.c @@ -4,19 +4,18 @@ #include #include "common.h" -typedef void (*PFN_Kernel)(int task_id, void* arg); +typedef void (*PFN_Kernel)(int task_id, const kernel_arg_t* arg); inline float __ieee754_sqrtf (float x) { asm ("fsqrt.s %0, %1" : "=f" (x) : "f" (x)); return x; } -void kernel_iadd(int task_id, void* arg) { - struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); - uint32_t count = _arg->task_size; - int32_t* src0_ptr = (int32_t*)_arg->src0_ptr; - int32_t* src1_ptr = (int32_t*)_arg->src1_ptr; - int32_t* dst_ptr = (int32_t*)_arg->dst_ptr; +void kernel_iadd(int task_id, const kernel_arg_t* arg) { + uint32_t count = arg->task_size; + int32_t* src0_ptr = (int32_t*)arg->src0_ptr; + int32_t* src1_ptr = (int32_t*)arg->src1_ptr; + int32_t* dst_ptr = (int32_t*)arg->dst_ptr; uint32_t offset = task_id * count; for (uint32_t i = 0; i < count; ++i) { @@ -27,12 +26,11 @@ void kernel_iadd(int task_id, void* arg) { } } -void kernel_imul(int task_id, void* arg) { - struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); - uint32_t count = _arg->task_size; - int32_t* src0_ptr = (int32_t*)_arg->src0_ptr; - int32_t* src1_ptr = (int32_t*)_arg->src1_ptr; - int32_t* dst_ptr = (int32_t*)_arg->dst_ptr; +void kernel_imul(int task_id, const kernel_arg_t* arg) { + uint32_t count = arg->task_size; + int32_t* src0_ptr = (int32_t*)arg->src0_ptr; + int32_t* src1_ptr = (int32_t*)arg->src1_ptr; + int32_t* dst_ptr = (int32_t*)arg->dst_ptr; uint32_t offset = task_id * count; for (uint32_t i = 0; i < count; ++i) { @@ -43,12 +41,11 @@ void kernel_imul(int task_id, void* arg) { } } -void kernel_idiv(int task_id, void* arg) { - struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); - uint32_t count = _arg->task_size; - int32_t* src0_ptr = (int32_t*)_arg->src0_ptr; - int32_t* src1_ptr = (int32_t*)_arg->src1_ptr; - int32_t* dst_ptr = (int32_t*)_arg->dst_ptr; +void kernel_idiv(int task_id, const kernel_arg_t* arg) { + uint32_t count = arg->task_size; + int32_t* src0_ptr = (int32_t*)arg->src0_ptr; + int32_t* src1_ptr = (int32_t*)arg->src1_ptr; + int32_t* dst_ptr = (int32_t*)arg->dst_ptr; uint32_t offset = task_id * count; for (uint32_t i = 0; i < count; ++i) { @@ -59,12 +56,11 @@ void kernel_idiv(int task_id, void* arg) { } } -void kernel_idiv_mul(int task_id, void* arg) { - struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); - uint32_t count = _arg->task_size; - int32_t* src0_ptr = (int32_t*)_arg->src0_ptr; - int32_t* src1_ptr = (int32_t*)_arg->src1_ptr; - int32_t* dst_ptr = (int32_t*)_arg->dst_ptr; +void kernel_idiv_mul(int task_id, const kernel_arg_t* arg) { + uint32_t count = arg->task_size; + int32_t* src0_ptr = (int32_t*)arg->src0_ptr; + int32_t* src1_ptr = (int32_t*)arg->src1_ptr; + int32_t* dst_ptr = (int32_t*)arg->dst_ptr; uint32_t offset = task_id * count; for (uint32_t i = 0; i < count; ++i) { @@ -77,12 +73,11 @@ void kernel_idiv_mul(int task_id, void* arg) { } } -void kernel_fadd(int task_id, void* arg) { - struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); - uint32_t count = _arg->task_size; - float* src0_ptr = (float*)_arg->src0_ptr; - float* src1_ptr = (float*)_arg->src1_ptr; - float* dst_ptr = (float*)_arg->dst_ptr; +void kernel_fadd(int task_id, const kernel_arg_t* arg) { + uint32_t count = arg->task_size; + float* src0_ptr = (float*)arg->src0_ptr; + float* src1_ptr = (float*)arg->src1_ptr; + float* dst_ptr = (float*)arg->dst_ptr; uint32_t offset = task_id * count; for (uint32_t i = 0; i < count; ++i) { @@ -93,12 +88,11 @@ void kernel_fadd(int task_id, void* arg) { } } -void kernel_fsub(int task_id, void* arg) { - struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); - uint32_t count = _arg->task_size; - float* src0_ptr = (float*)_arg->src0_ptr; - float* src1_ptr = (float*)_arg->src1_ptr; - float* dst_ptr = (float*)_arg->dst_ptr; +void kernel_fsub(int task_id, const kernel_arg_t* arg) { + uint32_t count = arg->task_size; + float* src0_ptr = (float*)arg->src0_ptr; + float* src1_ptr = (float*)arg->src1_ptr; + float* dst_ptr = (float*)arg->dst_ptr; uint32_t offset = task_id * count; for (uint32_t i = 0; i < count; ++i) { @@ -109,12 +103,11 @@ void kernel_fsub(int task_id, void* arg) { } } -void kernel_fmul(int task_id, void* arg) { - struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); - uint32_t count = _arg->task_size; - float* src0_ptr = (float*)_arg->src0_ptr; - float* src1_ptr = (float*)_arg->src1_ptr; - float* dst_ptr = (float*)_arg->dst_ptr; +void kernel_fmul(int task_id, const kernel_arg_t* arg) { + uint32_t count = arg->task_size; + float* src0_ptr = (float*)arg->src0_ptr; + float* src1_ptr = (float*)arg->src1_ptr; + float* dst_ptr = (float*)arg->dst_ptr; uint32_t offset = task_id * count; for (uint32_t i = 0; i < count; ++i) { @@ -125,12 +118,11 @@ void kernel_fmul(int task_id, void* arg) { } } -void kernel_fmadd(int task_id, void* arg) { - struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); - uint32_t count = _arg->task_size; - float* src0_ptr = (float*)_arg->src0_ptr; - float* src1_ptr = (float*)_arg->src1_ptr; - float* dst_ptr = (float*)_arg->dst_ptr; +void kernel_fmadd(int task_id, const kernel_arg_t* arg) { + uint32_t count = arg->task_size; + float* src0_ptr = (float*)arg->src0_ptr; + float* src1_ptr = (float*)arg->src1_ptr; + float* dst_ptr = (float*)arg->dst_ptr; uint32_t offset = task_id * count; for (uint32_t i = 0; i < count; ++i) { @@ -141,12 +133,11 @@ void kernel_fmadd(int task_id, void* arg) { } } -void kernel_fmsub(int task_id, void* arg) { - struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); - uint32_t count = _arg->task_size; - float* src0_ptr = (float*)_arg->src0_ptr; - float* src1_ptr = (float*)_arg->src1_ptr; - float* dst_ptr = (float*)_arg->dst_ptr; +void kernel_fmsub(int task_id, const kernel_arg_t* arg) { + uint32_t count = arg->task_size; + float* src0_ptr = (float*)arg->src0_ptr; + float* src1_ptr = (float*)arg->src1_ptr; + float* dst_ptr = (float*)arg->dst_ptr; uint32_t offset = task_id * count; for (uint32_t i = 0; i < count; ++i) { @@ -157,12 +148,11 @@ void kernel_fmsub(int task_id, void* arg) { } } -void kernel_fnmadd(int task_id, void* arg) { - struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); - uint32_t count = _arg->task_size; - float* src0_ptr = (float*)_arg->src0_ptr; - float* src1_ptr = (float*)_arg->src1_ptr; - float* dst_ptr = (float*)_arg->dst_ptr; +void kernel_fnmadd(int task_id, const kernel_arg_t* arg) { + uint32_t count = arg->task_size; + float* src0_ptr = (float*)arg->src0_ptr; + float* src1_ptr = (float*)arg->src1_ptr; + float* dst_ptr = (float*)arg->dst_ptr; uint32_t offset = task_id * count; for (uint32_t i = 0; i < count; ++i) { @@ -173,12 +163,11 @@ void kernel_fnmadd(int task_id, void* arg) { } } -void kernel_fnmsub(int task_id, void* arg) { - struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); - uint32_t count = _arg->task_size; - float* src0_ptr = (float*)_arg->src0_ptr; - float* src1_ptr = (float*)_arg->src1_ptr; - float* dst_ptr = (float*)_arg->dst_ptr; +void kernel_fnmsub(int task_id, const kernel_arg_t* arg) { + uint32_t count = arg->task_size; + float* src0_ptr = (float*)arg->src0_ptr; + float* src1_ptr = (float*)arg->src1_ptr; + float* dst_ptr = (float*)arg->dst_ptr; uint32_t offset = task_id * count; for (uint32_t i = 0; i < count; ++i) { @@ -189,12 +178,11 @@ void kernel_fnmsub(int task_id, void* arg) { } } -void kernel_fnmadd_madd(int task_id, void* arg) { - struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); - uint32_t count = _arg->task_size; - float* src0_ptr = (float*)_arg->src0_ptr; - float* src1_ptr = (float*)_arg->src1_ptr; - float* dst_ptr = (float*)_arg->dst_ptr; +void kernel_fnmadd_madd(int task_id, const kernel_arg_t* arg) { + uint32_t count = arg->task_size; + float* src0_ptr = (float*)arg->src0_ptr; + float* src1_ptr = (float*)arg->src1_ptr; + float* dst_ptr = (float*)arg->dst_ptr; uint32_t offset = task_id * count; for (uint32_t i = 0; i < count; ++i) { @@ -207,12 +195,11 @@ void kernel_fnmadd_madd(int task_id, void* arg) { } } -void kernel_fdiv(int task_id, void* arg) { - struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); - uint32_t count = _arg->task_size; - float* src0_ptr = (float*)_arg->src0_ptr; - float* src1_ptr = (float*)_arg->src1_ptr; - float* dst_ptr = (float*)_arg->dst_ptr; +void kernel_fdiv(int task_id, const kernel_arg_t* arg) { + uint32_t count = arg->task_size; + float* src0_ptr = (float*)arg->src0_ptr; + float* src1_ptr = (float*)arg->src1_ptr; + float* dst_ptr = (float*)arg->dst_ptr; uint32_t offset = task_id * count; for (uint32_t i = 0; i < count; ++i) { @@ -223,12 +210,11 @@ void kernel_fdiv(int task_id, void* arg) { } } -void kernel_fdiv2(int task_id, void* arg) { - struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); - uint32_t count = _arg->task_size; - float* src0_ptr = (float*)_arg->src0_ptr; - float* src1_ptr = (float*)_arg->src1_ptr; - float* dst_ptr = (float*)_arg->dst_ptr; +void kernel_fdiv2(int task_id, const kernel_arg_t* arg) { + uint32_t count = arg->task_size; + float* src0_ptr = (float*)arg->src0_ptr; + float* src1_ptr = (float*)arg->src1_ptr; + float* dst_ptr = (float*)arg->dst_ptr; uint32_t offset = task_id * count; for (uint32_t i = 0; i < count; ++i) { @@ -241,12 +227,11 @@ void kernel_fdiv2(int task_id, void* arg) { } } -void kernel_fsqrt(int task_id, void* arg) { - struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); - uint32_t count = _arg->task_size; - float* src0_ptr = (float*)_arg->src0_ptr; - float* src1_ptr = (float*)_arg->src1_ptr; - float* dst_ptr = (float*)_arg->dst_ptr; +void kernel_fsqrt(int task_id, const kernel_arg_t* arg) { + uint32_t count = arg->task_size; + float* src0_ptr = (float*)arg->src0_ptr; + float* src1_ptr = (float*)arg->src1_ptr; + float* dst_ptr = (float*)arg->dst_ptr; uint32_t offset = task_id * count; for (uint32_t i = 0; i < count; ++i) { @@ -257,12 +242,11 @@ void kernel_fsqrt(int task_id, void* arg) { } } -void kernel_ftoi(int task_id, void* arg) { - struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); - uint32_t count = _arg->task_size; - float* src0_ptr = (float*)_arg->src0_ptr; - float* src1_ptr = (float*)_arg->src1_ptr; - int32_t* dst_ptr = (int32_t*)_arg->dst_ptr; +void kernel_ftoi(int task_id, const kernel_arg_t* arg) { + uint32_t count = arg->task_size; + float* src0_ptr = (float*)arg->src0_ptr; + float* src1_ptr = (float*)arg->src1_ptr; + int32_t* dst_ptr = (int32_t*)arg->dst_ptr; uint32_t offset = task_id * count; for (uint32_t i = 0; i < count; ++i) { @@ -274,12 +258,11 @@ void kernel_ftoi(int task_id, void* arg) { } } -void kernel_ftou(int task_id, void* arg) { - struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); - uint32_t count = _arg->task_size; - float* src0_ptr = (float*)_arg->src0_ptr; - float* src1_ptr = (float*)_arg->src1_ptr; - uint32_t* dst_ptr = (uint32_t*)_arg->dst_ptr; +void kernel_ftou(int task_id, const kernel_arg_t* arg) { + uint32_t count = arg->task_size; + float* src0_ptr = (float*)arg->src0_ptr; + float* src1_ptr = (float*)arg->src1_ptr; + uint32_t* dst_ptr = (uint32_t*)arg->dst_ptr; uint32_t offset = task_id * count; for (uint32_t i = 0; i < count; ++i) { @@ -291,12 +274,11 @@ void kernel_ftou(int task_id, void* arg) { } } -void kernel_itof(int task_id, void* arg) { - struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); - uint32_t count = _arg->task_size; - int32_t* src0_ptr = (int32_t*)_arg->src0_ptr; - int32_t* src1_ptr = (int32_t*)_arg->src1_ptr; - float* dst_ptr = (float*)_arg->dst_ptr; +void kernel_itof(int task_id, const kernel_arg_t* arg) { + uint32_t count = arg->task_size; + int32_t* src0_ptr = (int32_t*)arg->src0_ptr; + int32_t* src1_ptr = (int32_t*)arg->src1_ptr; + float* dst_ptr = (float*)arg->dst_ptr; uint32_t offset = task_id * count; for (uint32_t i = 0; i < count; ++i) { @@ -308,12 +290,11 @@ void kernel_itof(int task_id, void* arg) { } } -void kernel_utof(int task_id, void* arg) { - struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); - uint32_t count = _arg->task_size; - int32_t* src0_ptr = (int32_t*)_arg->src0_ptr; - int32_t* src1_ptr = (int32_t*)_arg->src1_ptr; - float* dst_ptr = (float*)_arg->dst_ptr; +void kernel_utof(int task_id, const kernel_arg_t* arg) { + uint32_t count = arg->task_size; + int32_t* src0_ptr = (int32_t*)arg->src0_ptr; + int32_t* src1_ptr = (int32_t*)arg->src1_ptr; + float* dst_ptr = (float*)arg->dst_ptr; uint32_t offset = task_id * count; for (uint32_t i = 0; i < count; ++i) { @@ -348,6 +329,6 @@ static const PFN_Kernel sc_tests[] = { }; void main() { - struct kernel_arg_t* arg = (struct kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR; + const kernel_arg_t* arg = (const kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR; vx_spawn_tasks(arg->num_tasks, sc_tests[arg->testid], arg); } \ No newline at end of file diff --git a/tests/regression/dogfood/main.cpp b/tests/regression/dogfood/main.cpp index aab15522..804609ae 100644 --- a/tests/regression/dogfood/main.cpp +++ b/tests/regression/dogfood/main.cpp @@ -3,6 +3,7 @@ #include #include #include +#include #include "testcases.h" #include "common.h" diff --git a/tests/regression/fence/Makefile b/tests/regression/fence/Makefile index 7440669f..3491cb99 100644 --- a/tests/regression/fence/Makefile +++ b/tests/regression/fence/Makefile @@ -45,13 +45,13 @@ run-simx: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-fpga: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-rtlsim: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/regression/fence/common.h b/tests/regression/fence/common.h index d6540ae1..3a38ae43 100644 --- a/tests/regression/fence/common.h +++ b/tests/regression/fence/common.h @@ -3,12 +3,12 @@ #define KERNEL_ARG_DEV_MEM_ADDR 0x7ffff000 -struct kernel_arg_t { +typedef struct { uint32_t num_tasks; uint32_t task_size; uint32_t src0_ptr; uint32_t src1_ptr; uint32_t dst_ptr; -}; +} kernel_arg_t; #endif \ No newline at end of file diff --git a/tests/regression/fence/kernel.c b/tests/regression/fence/kernel.c index 1401bc87..bc39537f 100644 --- a/tests/regression/fence/kernel.c +++ b/tests/regression/fence/kernel.c @@ -3,12 +3,11 @@ #include #include "common.h" -void kernel_body(int task_id, void* arg) { - struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); - uint32_t count = _arg->task_size; - int32_t* src0_ptr = (int32_t*)_arg->src0_ptr; - int32_t* src1_ptr = (int32_t*)_arg->src1_ptr; - int32_t* dst_ptr = (int32_t*)_arg->dst_ptr; +void kernel_body(int task_id, const kernel_arg_t* arg) { + uint32_t count = arg->task_size; + int32_t* src0_ptr = (int32_t*)arg->src0_ptr; + int32_t* src1_ptr = (int32_t*)arg->src1_ptr; + int32_t* dst_ptr = (int32_t*)arg->dst_ptr; uint32_t offset = task_id * count; @@ -20,6 +19,6 @@ void kernel_body(int task_id, void* arg) { } void main() { - struct kernel_arg_t* arg = (struct kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR; + const kernel_arg_t* arg = (const kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR; vx_spawn_tasks(arg->num_tasks, kernel_body, arg); } \ No newline at end of file diff --git a/tests/regression/io_addr/Makefile b/tests/regression/io_addr/Makefile index 36f05992..80f62fc6 100644 --- a/tests/regression/io_addr/Makefile +++ b/tests/regression/io_addr/Makefile @@ -45,13 +45,13 @@ run-simx: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-fpga: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-rtlsim: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/regression/io_addr/common.h b/tests/regression/io_addr/common.h index 73247b2c..6346c58e 100644 --- a/tests/regression/io_addr/common.h +++ b/tests/regression/io_addr/common.h @@ -3,10 +3,10 @@ #define KERNEL_ARG_DEV_MEM_ADDR 0x7ffff000 -struct kernel_arg_t { +typedef struct { uint32_t num_points; uint32_t src_ptr; uint32_t dst_ptr; -}; +} kernel_arg_t; #endif \ No newline at end of file diff --git a/tests/regression/io_addr/kernel.c b/tests/regression/io_addr/kernel.c index 15b6ef8d..39d4c5c6 100644 --- a/tests/regression/io_addr/kernel.c +++ b/tests/regression/io_addr/kernel.c @@ -3,10 +3,9 @@ #include #include "common.h" -void kernel_body(int task_id, void* arg) { - struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); - uint32_t* src_ptr = (uint32_t*)_arg->src_ptr; - uint32_t* dst_ptr = (uint32_t*)_arg->dst_ptr; +void kernel_body(int task_id, const kernel_arg_t* arg) { + uint32_t* src_ptr = (uint32_t*)arg->src_ptr; + uint32_t* dst_ptr = (uint32_t*)arg->dst_ptr; int32_t* addr_ptr = (int32_t*)(src_ptr[task_id]); @@ -14,6 +13,6 @@ void kernel_body(int task_id, void* arg) { } void main() { - struct kernel_arg_t* arg = (struct kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR; + const kernel_arg_t* arg = (const kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR; vx_spawn_tasks(arg->num_points, kernel_body, arg); } \ No newline at end of file diff --git a/tests/regression/mstress/Makefile b/tests/regression/mstress/Makefile index 14e40685..024967de 100644 --- a/tests/regression/mstress/Makefile +++ b/tests/regression/mstress/Makefile @@ -45,13 +45,13 @@ run-simx: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-fpga: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-rtlsim: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/regression/mstress/common.h b/tests/regression/mstress/common.h index 843a4a4c..12ed6290 100644 --- a/tests/regression/mstress/common.h +++ b/tests/regression/mstress/common.h @@ -5,13 +5,13 @@ #define NUM_LOADS 8 -struct kernel_arg_t { +typedef struct { uint32_t num_tasks; uint32_t size; uint32_t stride; uint32_t addr_ptr; uint32_t src_ptr; uint32_t dst_ptr; -}; +} kernel_arg_t; #endif \ No newline at end of file diff --git a/tests/regression/mstress/kernel.c b/tests/regression/mstress/kernel.c index c40cb11c..2d2a86b9 100644 --- a/tests/regression/mstress/kernel.c +++ b/tests/regression/mstress/kernel.c @@ -3,12 +3,11 @@ #include #include "common.h" -void kernel_body(int task_id, void* arg) { - struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); - uint32_t stride = _arg->stride; - uint32_t* addr_ptr = (uint32_t*)_arg->addr_ptr; - float* src_ptr = (float*)_arg->src_ptr; - float* dst_ptr = (float*)_arg->dst_ptr; +void kernel_body(int task_id, const kernel_arg_t* arg) { + uint32_t stride = arg->stride; + uint32_t* addr_ptr = (uint32_t*)arg->addr_ptr; + float* src_ptr = (float*)arg->src_ptr; + float* dst_ptr = (float*)arg->dst_ptr; uint32_t offset = task_id * stride; @@ -24,6 +23,6 @@ void kernel_body(int task_id, void* arg) { } void main() { - struct kernel_arg_t* arg = (struct kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR; + const kernel_arg_t* arg = (const kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR; vx_spawn_tasks(arg->num_tasks, kernel_body, arg); } \ No newline at end of file diff --git a/tests/regression/no_mf_ext/Makefile b/tests/regression/no_mf_ext/Makefile index fd43dc85..99384023 100644 --- a/tests/regression/no_mf_ext/Makefile +++ b/tests/regression/no_mf_ext/Makefile @@ -45,13 +45,13 @@ run-simx: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-fpga: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-rtlsim: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/regression/no_mf_ext/common.h b/tests/regression/no_mf_ext/common.h index b22cf16e..f2638122 100644 --- a/tests/regression/no_mf_ext/common.h +++ b/tests/regression/no_mf_ext/common.h @@ -3,10 +3,10 @@ #define KERNEL_ARG_DEV_MEM_ADDR 0x7ffff000 -struct kernel_arg_t { +typedef struct { uint32_t size; uint32_t src_ptr; uint32_t dst_ptr; -}; +} kernel_arg_t; #endif \ No newline at end of file diff --git a/tests/regression/no_mf_ext/kernel.c b/tests/regression/no_mf_ext/kernel.c index 9e074dc3..c15ad5fc 100644 --- a/tests/regression/no_mf_ext/kernel.c +++ b/tests/regression/no_mf_ext/kernel.c @@ -4,7 +4,7 @@ #include "common.h" void main() { - struct kernel_arg_t* arg = (struct kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR; + const kernel_arg_t* arg = (const kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR; uint32_t size = arg->size; int32_t* src_ptr = (int32_t*)arg->src_ptr; diff --git a/tests/regression/no_smem/Makefile b/tests/regression/no_smem/Makefile index 74c3190c..de5a4f78 100644 --- a/tests/regression/no_smem/Makefile +++ b/tests/regression/no_smem/Makefile @@ -47,13 +47,13 @@ run-simx: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-fpga: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-rtlsim: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/regression/no_smem/common.h b/tests/regression/no_smem/common.h index b22cf16e..f2638122 100644 --- a/tests/regression/no_smem/common.h +++ b/tests/regression/no_smem/common.h @@ -3,10 +3,10 @@ #define KERNEL_ARG_DEV_MEM_ADDR 0x7ffff000 -struct kernel_arg_t { +typedef struct { uint32_t size; uint32_t src_ptr; uint32_t dst_ptr; -}; +} kernel_arg_t; #endif \ No newline at end of file diff --git a/tests/regression/no_smem/kernel.c b/tests/regression/no_smem/kernel.c index 9e074dc3..c15ad5fc 100644 --- a/tests/regression/no_smem/kernel.c +++ b/tests/regression/no_smem/kernel.c @@ -4,7 +4,7 @@ #include "common.h" void main() { - struct kernel_arg_t* arg = (struct kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR; + const kernel_arg_t* arg = (const kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR; uint32_t size = arg->size; int32_t* src_ptr = (int32_t*)arg->src_ptr; diff --git a/tests/regression/printf/Makefile b/tests/regression/printf/Makefile index 9e67a639..a7aeb266 100644 --- a/tests/regression/printf/Makefile +++ b/tests/regression/printf/Makefile @@ -45,13 +45,13 @@ run-simx: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-fpga: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-rtlsim: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/regression/printf/common.h b/tests/regression/printf/common.h index f01d3cba..be3af59d 100644 --- a/tests/regression/printf/common.h +++ b/tests/regression/printf/common.h @@ -3,9 +3,9 @@ #define KERNEL_ARG_DEV_MEM_ADDR 0x7ffff000 -struct kernel_arg_t { +typedef struct { uint32_t num_points; uint32_t src_ptr; -}; +} kernel_arg_t; #endif \ No newline at end of file diff --git a/tests/regression/printf/kernel.c b/tests/regression/printf/kernel.c index 284c1abd..2e3b6566 100644 --- a/tests/regression/printf/kernel.c +++ b/tests/regression/printf/kernel.c @@ -4,13 +4,12 @@ #include #include "common.h" -void kernel_body(int task_id, void* arg) { - struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); - int* src_ptr = (int*)_arg->src_ptr; +void kernel_body(int task_id, const kernel_arg_t* arg) { + int* src_ptr = (int*)arg->src_ptr; vx_printf("task=%d, value=%d\n", task_id, src_ptr[task_id]); } void main() { - struct kernel_arg_t* arg = (struct kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR; + const kernel_arg_t* arg = (const kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR; vx_spawn_tasks(arg->num_points, kernel_body, arg); } \ No newline at end of file diff --git a/tests/regression/printf/main.cpp b/tests/regression/printf/main.cpp index 3ac7c91b..11b9fc50 100644 --- a/tests/regression/printf/main.cpp +++ b/tests/regression/printf/main.cpp @@ -58,9 +58,7 @@ void cleanup() { } } -int run_test(const kernel_arg_t& kernel_arg, - uint32_t buf_size, - uint32_t num_points) { +int run_test() { // start device std::cout << "start device" << std::endl; RT_CHECK(vx_start(device)); @@ -137,7 +135,7 @@ int main(int argc, char *argv[]) { // run tests std::cout << "run tests" << std::endl; - RT_CHECK(run_test(kernel_arg, buf_size, num_points)); + RT_CHECK(run_test()); // cleanup std::cout << "cleanup" << std::endl; diff --git a/tests/regression/sort/Makefile b/tests/regression/sort/Makefile index e4e8a25c..ef4d86f0 100644 --- a/tests/regression/sort/Makefile +++ b/tests/regression/sort/Makefile @@ -45,13 +45,13 @@ run-simx: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-fpga: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-rtlsim: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/regression/sort/common.h b/tests/regression/sort/common.h index 73247b2c..6346c58e 100644 --- a/tests/regression/sort/common.h +++ b/tests/regression/sort/common.h @@ -3,10 +3,10 @@ #define KERNEL_ARG_DEV_MEM_ADDR 0x7ffff000 -struct kernel_arg_t { +typedef struct { uint32_t num_points; uint32_t src_ptr; uint32_t dst_ptr; -}; +} kernel_arg_t; #endif \ No newline at end of file diff --git a/tests/regression/sort/kernel.c b/tests/regression/sort/kernel.c index ceac1a26..d89a9cb7 100644 --- a/tests/regression/sort/kernel.c +++ b/tests/regression/sort/kernel.c @@ -20,11 +20,10 @@ int __attribute__((noinline)) __smaller(int index, int tid, int32_t cur_value, i return ret; } -void kernel_body(int task_id, void* arg) { - struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); - uint32_t num_points = _arg->num_points; - int32_t* src_ptr = (int32_t*)_arg->src_ptr; - int32_t* dst_ptr = (int32_t*)_arg->dst_ptr; +void kernel_body(int task_id, const kernel_arg_t* arg) { + uint32_t num_points = arg->num_points; + int32_t* src_ptr = (int32_t*)arg->src_ptr; + int32_t* dst_ptr = (int32_t*)arg->dst_ptr; int32_t ref_value = src_ptr[task_id]; @@ -38,6 +37,6 @@ void kernel_body(int task_id, void* arg) { } void main() { - struct kernel_arg_t* arg = (struct kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR; + const kernel_arg_t* arg = (const kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR; vx_spawn_tasks(arg->num_points, kernel_body, arg); } \ No newline at end of file diff --git a/tests/riscv/isa/Makefile b/tests/riscv/isa/Makefile index f7488899..fba3bdd1 100644 --- a/tests/riscv/isa/Makefile +++ b/tests/riscv/isa/Makefile @@ -1,13 +1,18 @@ ALL_TESTS := $(wildcard *.hex) +D_TESTS := $(wildcard *ud-p-*.hex) V_TESTS := $(wildcard *-v-*.hex) -EXCLUDED_TESTS := $(V_TESTS) rv32si-p-scall.hex rv32si-p-sbreak.hex rv32mi-p-breakpoint.hex rv32ud-p-fclass.hex rv32ua-p-amomax_w.hex rv32ua-p-amoxor_w.hex rv32ud-p-ldst.hex rv32ua-p-amoor_w.hex rv32mi-p-ma_addr.hex rv32ud-p-fdiv.hex rv32ud-p-fcmp.hex rv32mi-p-mcsr.hex rv32ua-p-amoswap_w.hex rv32mi-p-ma_fetch.hex rv32mi-p-csr.hex rv32ua-p-amoadd_w.hex rv32si-p-dirty.hex rv32ud-p-fcvt.hex rv32ui-p-fence_i.hex rv32si-p-csr.hex rv32mi-p-shamt.hex rv32ua-p-amomin_w.hex rv32ua-p-lrsc.hex rv32ud-p-fmadd.hex rv32ud-p-fadd.hex rv32si-p-wfi.hex rv32ua-p-amomaxu_w.hex rv32si-p-ma_fetch.hex rv32ud-p-fmin.hex rv32mi-p-illegal.hex rv32uc-p-rvc.hex rv32mi-p-sbreak.hex rv32ua-p-amominu_w.hex rv32ua-p-amoand_w.hex +EXCLUDED_TESTS := $(V_TESTS) $(D_TESTS) rv32si-p-scall.hex rv32si-p-sbreak.hex rv32mi-p-breakpoint.hex rv32ua-p-amomax_w.hex rv32ua-p-amoxor_w.hex rv32ua-p-amoor_w.hex rv32mi-p-ma_addr.hex rv32mi-p-mcsr.hex rv32ua-p-amoswap_w.hex rv32mi-p-ma_fetch.hex rv32mi-p-csr.hex rv32ua-p-amoadd_w.hex rv32si-p-dirty.hex rv32ui-p-fence_i.hex rv32si-p-csr.hex rv32mi-p-shamt.hex rv32ua-p-amomin_w.hex rv32ua-p-lrsc.hex rv32si-p-wfi.hex rv32ua-p-amomaxu_w.hex rv32si-p-ma_fetch.hex rv32mi-p-illegal.hex rv32uc-p-rvc.hex rv32mi-p-sbreak.hex rv32ua-p-amominu_w.hex rv32ua-p-amoand_w.hex TESTS := $(filter-out $(EXCLUDED_TESTS), $(ALL_TESTS)) +all: + run-simx: - $(foreach test, $(TESTS), ../../../simX/simX -r -a rv32i -c 1 -i $(test) || exit;) + $(foreach test, $(TESTS), ../../../sim/simX/simX -r -a rv32i -c 1 -i $(test) || exit;) run-rtlsim: - $(foreach test, $(TESTS), ../../../hw/simulate/obj_dir/VVortex -r $(test) || exit;) \ No newline at end of file + $(foreach test, $(TESTS), ../../../sim/rtlsim/rtlsim -r $(test) || exit;) + +clean: \ No newline at end of file diff --git a/tests/runtime/fibonacci/Makefile b/tests/runtime/fibonacci/Makefile index 0eaa9592..cd5195e0 100644 --- a/tests/runtime/fibonacci/Makefile +++ b/tests/runtime/fibonacci/Makefile @@ -15,25 +15,25 @@ PROJECT = fibonacci SRCS = main.cpp -all: $(PROJECT).elf $(PROJECT).hex $(PROJECT).dump +all: $(PROJECT).elf $(PROJECT).bin $(PROJECT).dump $(PROJECT).dump: $(PROJECT).elf $(DP) -D $(PROJECT).elf > $(PROJECT).dump -$(PROJECT).hex: $(PROJECT).elf - $(CP) -O ihex $(PROJECT).elf $(PROJECT).hex +$(PROJECT).bin: $(PROJECT).elf + $(CP) -O binary $(PROJECT).elf $(PROJECT).bin $(PROJECT).elf: $(SRCS) $(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf -run-rtlsim: $(PROJECT).hex - ../../../hw/simulate/obj_dir/VVortex $(PROJECT).hex +run-rtlsim: $(PROJECT).bin + ../../../sim/rtlsim/rtlsim $(PROJECT).bin -run-simx: $(PROJECT).hex - ../../../simX/simX -a rv32i -c 1 -i $(PROJECT).hex +run-simx: $(PROJECT).bin + ../../../sim/simX/simX -a rv32i -c 1 -i $(PROJECT).bin .depend: $(SRCS) $(CC) $(CFLAGS) -MM $^ > .depend; clean: - rm -rf *.elf *.hex *.dump .depend + rm -rf *.elf *.bin *.dump .depend diff --git a/tests/runtime/hello/Makefile b/tests/runtime/hello/Makefile index c585e882..43e768b6 100644 --- a/tests/runtime/hello/Makefile +++ b/tests/runtime/hello/Makefile @@ -15,25 +15,25 @@ PROJECT = hello SRCS = main.cpp -all: $(PROJECT).elf $(PROJECT).hex $(PROJECT).dump +all: $(PROJECT).elf $(PROJECT).bin $(PROJECT).dump $(PROJECT).dump: $(PROJECT).elf $(DP) -D $(PROJECT).elf > $(PROJECT).dump -$(PROJECT).hex: $(PROJECT).elf - $(CP) -O ihex $(PROJECT).elf $(PROJECT).hex +$(PROJECT).bin: $(PROJECT).elf + $(CP) -O binary $(PROJECT).elf $(PROJECT).bin $(PROJECT).elf: $(SRCS) $(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf -run-rtlsim: $(PROJECT).hex - ../../../hw/simulate/obj_dir/VVortex $(PROJECT).hex +run-rtlsim: $(PROJECT).bin + ../../../sim/rtlsim/rtlsim $(PROJECT).bin -run-simx: $(PROJECT).hex - ../../../simX/simX -a rv32i -c 1 -i $(PROJECT).hex +run-simx: $(PROJECT).bin + ../../../sim/simX/simX -a rv32i -c 1 -i $(PROJECT).bin .depend: $(SRCS) $(CC) $(CFLAGS) -MM $^ > .depend; clean: - rm -rf *.elf *.hex *.dump .depend + rm -rf *.elf *.bin *.dump .depend diff --git a/tests/runtime/simple/Makefile b/tests/runtime/simple/Makefile index 79620a20..dabb4cc0 100644 --- a/tests/runtime/simple/Makefile +++ b/tests/runtime/simple/Makefile @@ -6,7 +6,7 @@ AR = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-gcc-ar DP = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-objdump CP = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-objcopy -CFLAGS += -march=rv32imf -mabi=ilp32f -O3 -Wstack-usage=1024 -ffreestanding -nostartfiles -fdata-sections -ffunction-sections +CFLAGS += -march=rv32imf -mabi=ilp32f -O3 -Wstack-usage=1024 -ffreestanding -nostartfiles -fdata-sections -ffunction-sections -fpermissive CFLAGS += -I$(VORTEX_RT_PATH)/include -I$(VORTEX_RT_PATH)/../hw LDFLAGS += -Wl,-Bstatic,-T,$(VORTEX_RT_PATH)/linker/vx_link.ld -Wl,--gc-sections $(VORTEX_RT_PATH)/libvortexrt.a @@ -15,25 +15,25 @@ PROJECT = simple SRCS = main.cpp tests.cpp -all: $(PROJECT).elf $(PROJECT).hex $(PROJECT).dump +all: $(PROJECT).elf $(PROJECT).bin $(PROJECT).dump $(PROJECT).dump: $(PROJECT).elf $(DP) -D $(PROJECT).elf > $(PROJECT).dump -$(PROJECT).hex: $(PROJECT).elf - $(CP) -O ihex $(PROJECT).elf $(PROJECT).hex +$(PROJECT).bin: $(PROJECT).elf + $(CP) -O binary $(PROJECT).elf $(PROJECT).bin $(PROJECT).elf: $(SRCS) $(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf -run-rtlsim: $(PROJECT).hex - ../../../hw/simulate/obj_dir/VVortex $(PROJECT).hex +run-rtlsim: $(PROJECT).bin + ../../../sim/rtlsim/rtlsim $(PROJECT).bin -run-simx: $(PROJECT).hex - ../../../simX/simX -a rv32i -c 1 -i $(PROJECT).hex +run-simx: $(PROJECT).bin + ../../../sim/simX/simX -a rv32i -c 1 -i $(PROJECT).bin .depend: $(SRCS) $(CC) $(CFLAGS) -MM $^ > .depend; clean: - rm -rf *.elf *.hex *.dump .depend + rm -rf *.elf *.bin *.dump .depend diff --git a/tests/runtime/simple/main.cpp b/tests/runtime/simple/main.cpp index c0723fb0..2f38eba6 100644 --- a/tests/runtime/simple/main.cpp +++ b/tests/runtime/simple/main.cpp @@ -4,8 +4,6 @@ int main() { int errors = 0; - vx_printf("Simple Test\n"); - errors += test_global_memory(); errors += test_stack_memory(); @@ -14,12 +12,20 @@ int main() { errors += test_tmc(); + errors += test_pred(); + errors += test_divergence(); errors += test_wsapwn(); errors += test_spawn_tasks(); + errors += test_serial(); + + errors += test_tmask(); + + errors += test_barrier(); + if (0 == errors) { vx_printf("Passed!\n"); } else { diff --git a/tests/runtime/simple/tests.cpp b/tests/runtime/simple/tests.cpp index 6db97399..912df0b9 100644 --- a/tests/runtime/simple/tests.cpp +++ b/tests/runtime/simple/tests.cpp @@ -1,12 +1,13 @@ #include "tests.h" #include +#include #include #include #include -int check_error(const int* buffer, int size) { +int __attribute__ ((noinline)) check_error(const int* buffer, int offset, int size) { int errors = 0; - for (int i = 0; i < size; i++) { + for (int i = offset; i < size; i++) { int value = buffer[i]; int ref_value = 65 + i; if (value == ref_value) { @@ -19,37 +20,42 @@ int check_error(const int* buffer, int size) { return errors; } +int __attribute__ ((noinline)) make_select_tmask(int tid) { + return (1 << tid); +} + +int __attribute__ ((noinline)) make_full_tmask(int num_threads) { + return (1 << num_threads) - 1; +} + /////////////////////////////////////////////////////////////////////////////// #define GLOBAL_MEM_SZ 8 int global_buffer[GLOBAL_MEM_SZ]; -int test_global_memory() { - int errors = 0; - - vx_printf("Global Memory test\n"); +int test_global_memory() { + vx_printf("Global Memory Test\n"); for (int i = 0; i < GLOBAL_MEM_SZ; i++) { global_buffer[i] = 65 + i; } - return check_error(global_buffer, GLOBAL_MEM_SZ); + return check_error(global_buffer, 0, GLOBAL_MEM_SZ); } /////////////////////////////////////////////////////////////////////////////// int test_stack_memory() { + vx_printf("Stack Memory Test\n"); + static const int STACK_MEM_SZ = 8; int stack_buffer[STACK_MEM_SZ]; - int errors = 0; - - vx_printf("Stack Memory test\n"); for (int i = 0; i < STACK_MEM_SZ; i++) { stack_buffer[i] = 65 + i; } - return check_error(stack_buffer, STACK_MEM_SZ); + return check_error(stack_buffer, 0, STACK_MEM_SZ); } /////////////////////////////////////////////////////////////////////////////// @@ -57,92 +63,123 @@ int test_stack_memory() { int test_shared_memory() { static const int SHARED_MEM_SZ = 8; int* shared_buffer = (int*)(SMEM_BASE_ADDR-(SMEM_SIZE-SHARED_MEM_SZ-4)); - int errors = 0; - vx_printf("Shared Memory test\n"); + vx_printf("Shared Memory Test\n"); for (int i = 0; i < SHARED_MEM_SZ; i++) { shared_buffer[i] = 65 + i; } - return check_error(shared_buffer, SHARED_MEM_SZ); + return check_error(shared_buffer, 0, SHARED_MEM_SZ); } /////////////////////////////////////////////////////////////////////////////// -int tmc_buffer[NUM_THREADS]; +int tmc_buffer[8]; -int test_tmc() { - int errors = 0; - - vx_printf("Thread mask test\n"); - - vx_tmc(NUM_THREADS); +void __attribute__ ((noinline)) do_tmc() { unsigned tid = vx_thread_id(); tmc_buffer[tid] = 65 + tid; +} + +int test_tmc() { + vx_printf("TMC Test\n"); + + int num_threads = std::min(vx_num_threads(), 8); + int tmask = make_full_tmask(num_threads); + vx_tmc(tmask); + do_tmc(); vx_tmc(1); - return check_error(tmc_buffer, NUM_THREADS); + return check_error(tmc_buffer, 0, num_threads); } /////////////////////////////////////////////////////////////////////////////// -int wspawn_buffer[NUM_WARPS]; +int pred_buffer[8]; -void simple_kernel() { +void __attribute__ ((noinline)) do_pred() { + unsigned tid = vx_thread_id(); + pred_buffer[tid] = 65 + tid; +} + +int test_pred() { + vx_printf("PRED Test\n"); + + int num_threads = std::min(vx_num_threads(), 8); + int tmask = make_full_tmask(num_threads); + + for (int i = 0; i < num_threads; i++) { + pred_buffer[i] = 0; + } + + vx_pred(~1); + do_pred(); + vx_tmc(1); + + int status_n0 = (0 == tmc_buffer[0]); + int status_n1 = check_error(tmc_buffer, 1, num_threads); + return status_n0 && status_n1; +} + +/////////////////////////////////////////////////////////////////////////////// + +int wspawn_buffer[8]; + +void wspawn_kernel() { unsigned wid = vx_warp_id(); wspawn_buffer[wid] = 65 + wid; vx_tmc(0 == wid); } int test_wsapwn() { - vx_printf("test_wspawn\n"); - vx_wspawn(NUM_WARPS, simple_kernel); - simple_kernel(); + vx_printf("Wspawn Test\n"); + int num_warps = std::min(vx_num_warps(), 8); + vx_wspawn(num_warps, wspawn_kernel); + wspawn_kernel(); - return check_error(wspawn_buffer, NUM_WARPS); + return check_error(wspawn_buffer, 0, num_warps); } /////////////////////////////////////////////////////////////////////////////// -#define DIV_BUF_SZ ((NUM_THREADS > 4) ? 4 : NUM_THREADS) -int div_buffer[DIV_BUF_SZ]; +int dvg_buffer[4]; -int test_divergence() { - int errors = 0; - - vx_printf("Control divergence test\n"); - - vx_tmc(DIV_BUF_SZ); +void __attribute__ ((noinline)) do_divergence() { unsigned tid = vx_thread_id(); - bool b = tid < 2; - __if (b) { - bool c = tid < 1; - __if (c) { - div_buffer[tid] = 65; + __if (tid < 2) { + __if (tid < 1) { + dvg_buffer[tid] = 65; } __else { - div_buffer[tid] = 66; + dvg_buffer[tid] = 66; } __endif } __else { - bool c = tid < 3; - __if (c) { - div_buffer[tid] = 67; + __if (tid < 3) { + dvg_buffer[tid] = 67; } __else { - div_buffer[tid] = 68; + dvg_buffer[tid] = 68; } __endif } __endif +} +int test_divergence() { + vx_printf("Control Divergence Test\n"); + + int num_threads = std::min(vx_num_threads(), 4); + int tmask = make_full_tmask(num_threads); + vx_tmc(tmask); + do_divergence(); vx_tmc(1); - return check_error(div_buffer, DIV_BUF_SZ); + return check_error(dvg_buffer, 0, num_threads); } /////////////////////////////////////////////////////////////////////////////// @@ -156,25 +193,111 @@ typedef struct { int st_buffer_src[ST_BUF_SZ]; int st_buffer_dst[ST_BUF_SZ]; -void st_kernel(int task_id, void * arg) { - st_args_t * arguments = (st_args_t *) arg; - arguments->dst[task_id] = arguments->src[task_id]; +void st_kernel(int task_id, const st_args_t * arg) { + arg->dst[task_id] = arg->src[task_id]; } int test_spawn_tasks() { - int error = 0; + vx_printf("SpawnTasks Test\n"); st_args_t arg; arg.src = st_buffer_src; arg.dst = st_buffer_dst; - vx_printf("spawning %d tasks\n", ST_BUF_SZ); - for (int i = 0; i < ST_BUF_SZ; i++) { st_buffer_src[i] = 65 + i; } vx_spawn_tasks(ST_BUF_SZ, st_kernel, &arg); - return check_error(st_buffer_dst, ST_BUF_SZ); + return check_error(st_buffer_dst, 0, ST_BUF_SZ); +} + +/////////////////////////////////////////////////////////////////////////////// + +#define SR_BUF_SZ 8 +typedef struct { + int * buf; +} sr_args_t; + +int sr_buffer[SR_BUF_SZ]; + +void sr_kernel(const sr_args_t * arg) { + int tid = vx_thread_id(); + arg->buf[tid] = 65 + tid; +} + +void __attribute__ ((noinline)) do_serial() { + sr_args_t arg; + arg.buf = sr_buffer; + vx_serial(sr_kernel, &arg); +} + +int test_serial() { + vx_printf("Serial Test\n"); + int num_threads = std::min(vx_num_threads(), 8); + int tmask = make_full_tmask(num_threads); + vx_tmc(tmask); + do_serial(); + vx_tmc(1); + + return check_error(sr_buffer, 0, num_threads); +} + +/////////////////////////////////////////////////////////////////////////////// + +int tmask_buffer[8]; + +int __attribute__ ((noinline)) do_tmask() { + int tid = vx_thread_id(); + int tmask = make_select_tmask(tid); + int cur_tmask = vx_thread_mask(); + tmask_buffer[tid] = (cur_tmask == tmask) ? (65 + tid) : 0; + return tid + 1; +} + +int test_tmask() { + vx_printf("Thread Mask Test\n"); + + // activate all thread to populate shared variables + vx_tmc(-1); + + int num_threads = std::min(vx_num_threads(), 8); + int tid = 0; + +l_start: + int tmask = make_select_tmask(tid); + vx_tmc(tmask); + tid = do_tmask(); + if (tid < num_threads) + goto l_start; + vx_tmc(1); + + return check_error(tmask_buffer, 0, num_threads); +} + +/////////////////////////////////////////////////////////////////////////////// + +int barrier_buffer[8]; +volatile int barrier_ctr; +volatile int barrier_stall; + +void barrier_kernel() { + unsigned wid = vx_warp_id(); + for (int i = 0; i <= (wid * 256); ++i) { + ++barrier_stall; + } + barrier_buffer[wid] = 65 + wid; + vx_barrier(0, barrier_ctr); + vx_tmc(0 == wid); +} + +int test_barrier() { + vx_printf("Barrier Test\n"); + int num_warps = std::min(vx_num_warps(), 8); + barrier_ctr = num_warps; + barrier_stall = 0; + vx_wspawn(num_warps, barrier_kernel); + barrier_kernel(); + return check_error(barrier_buffer, 0, num_warps); } \ No newline at end of file diff --git a/tests/runtime/simple/tests.h b/tests/runtime/simple/tests.h index e6b8b118..b0bd101d 100644 --- a/tests/runtime/simple/tests.h +++ b/tests/runtime/simple/tests.h @@ -9,10 +9,18 @@ int test_shared_memory(); int test_tmc(); +int test_pred(); + int test_divergence(); int test_wsapwn(); int test_spawn_tasks(); +int test_serial(); + +int test_tmask(); + +int test_barrier(); + #endif