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bank area optimization

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This commit is contained in:
Blaise Tine
2021-08-29 02:25:55 -07:00
parent 5392395fba
commit e26cfab04d
2 changed files with 43 additions and 48 deletions
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56
hw/rtl/cache/VX_bank.v vendored
View File

@@ -198,27 +198,6 @@ module VX_bank #(
end end
`endif `endif
wire [`CACHE_LINE_WIDTH-1:0] creq_line_data;
if (`WORDS_PER_LINE > 1) begin
if (NUM_PORTS > 1) begin
reg [`CACHE_LINE_WIDTH-1:0] creq_line_data_r;
always @(*) begin
creq_line_data_r = 'x;
for (integer p = 0; p < NUM_PORTS; p++) begin
if (creq_pmask[p]) begin
creq_line_data_r[creq_wsel[p] * `WORD_WIDTH +: `WORD_WIDTH] = creq_data[p];
end
end
end
assign creq_line_data = creq_line_data_r;
end else begin
assign creq_line_data = {`WORDS_PER_LINE{creq_data}};
end
end else begin
assign creq_line_data = creq_data;
end
VX_pipe_register #( VX_pipe_register #(
.DATAW (1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH + NUM_PORTS * (WORD_SELECT_BITS + WORD_SIZE + `REQS_BITS + 1 + CORE_TAG_WIDTH) + MSHR_ADDR_WIDTH), .DATAW (1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH + NUM_PORTS * (WORD_SELECT_BITS + WORD_SIZE + `REQS_BITS + 1 + CORE_TAG_WIDTH) + MSHR_ADDR_WIDTH),
.RESETW (1) .RESETW (1)
@@ -233,7 +212,7 @@ module VX_bank #(
mshr_enable, mshr_enable,
creq_fire && creq_rw, creq_fire && creq_rw,
mshr_enable ? mshr_addr : (mem_rsp_valid ? mem_rsp_addr : (flush_enable ? `LINE_ADDR_WIDTH'(flush_addr) : creq_addr)), mshr_enable ? mshr_addr : (mem_rsp_valid ? mem_rsp_addr : (flush_enable ? `LINE_ADDR_WIDTH'(flush_addr) : creq_addr)),
(mem_rsp_valid || !WRITE_ENABLE) ? mem_rsp_data : creq_line_data, (mem_rsp_valid || !WRITE_ENABLE) ? mem_rsp_data : `CACHE_LINE_WIDTH'(creq_data),
mshr_enable ? mshr_wsel : creq_wsel, mshr_enable ? mshr_wsel : creq_wsel,
creq_byteen, creq_byteen,
mshr_enable ? mshr_tid : creq_tid, mshr_enable ? mshr_tid : creq_tid,
@@ -315,22 +294,35 @@ module VX_bank #(
wire mreq_push_st1 = (read_st1 && miss_st1 && !mshr_pending_st1) wire mreq_push_st1 = (read_st1 && miss_st1 && !mshr_pending_st1)
|| write_st1; || write_st1;
wire [`WORDS_PER_LINE-1:0][WORD_SIZE-1:0] line_byteen_st1; wire [`CACHE_LINE_WIDTH-1:0] line_wdata_st1;
wire [CACHE_LINE_SIZE-1:0] line_byteen_st1;
wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] creq_data_st1 = wdata_st1[0 +: NUM_PORTS * `WORD_WIDTH];
if (`WORDS_PER_LINE > 1) begin if (`WORDS_PER_LINE > 1) begin
reg [`CACHE_LINE_WIDTH-1:0] line_wdata_r;
reg [CACHE_LINE_SIZE-1:0] line_byteen_r; reg [CACHE_LINE_SIZE-1:0] line_byteen_r;
always @(*) begin always @(*) begin
line_wdata_r = 'x;
line_byteen_r = 0; line_byteen_r = 0;
for (integer p = 0; p < NUM_PORTS; p++) begin if (NUM_PORTS > 1) begin
if ((NUM_PORTS == 1) || pmask_st1[p]) begin for (integer p = 0; p < NUM_PORTS; p++) begin
line_byteen_r[wsel_st1[p] * WORD_SIZE +: WORD_SIZE] = byteen_st1[p]; if (creq_pmask[p]) begin
line_wdata_r[creq_wsel[p] * `WORD_WIDTH +: `WORD_WIDTH] = creq_data_st1[p];
line_byteen_r[wsel_st1[p] * WORD_SIZE +: WORD_SIZE] = byteen_st1[p];
end
end end
end else begin
line_wdata_r = {`WORDS_PER_LINE{creq_data_st1}};
line_byteen_r[wsel_st1[0] * WORD_SIZE +: WORD_SIZE] = byteen_st1[0];
end end
end end
assign line_wdata_st1 = line_wdata_r;
assign line_byteen_st1 = line_byteen_r; assign line_byteen_st1 = line_byteen_r;
end else begin end else begin
assign line_byteen_st1 = byteen_st1;
`UNUSED_VAR (wsel_st1) `UNUSED_VAR (wsel_st1)
assign line_wdata_st1 = creq_data_st1;
assign line_byteen_st1 = byteen_st1;
end end
VX_data_access #( VX_data_access #(
@@ -356,13 +348,14 @@ module VX_bank #(
// reading // reading
.readen (valid_st1 && read_st1), .readen (valid_st1 && read_st1),
.rdata (rdata_st1), .read_data (rdata_st1),
// writing // writing
.writeen (valid_st1 && writeen_st1), .writeen (valid_st1 && writeen_st1),
.is_fill (is_fill_st1), .is_fill (is_fill_st1),
.byteen (line_byteen_st1), .byteen (line_byteen_st1),
.wdata (wdata_st1) .write_data (line_wdata_st1),
.fill_data (wdata_st1)
); );
wire mshr_allocate = creq_fire && ~creq_rw; wire mshr_allocate = creq_fire && ~creq_rw;
@@ -482,6 +475,7 @@ module VX_bank #(
assign mreq_addr = addr_st1; assign mreq_addr = addr_st1;
assign mreq_id = mshr_id_st1; assign mreq_id = mshr_id_st1;
assign mreq_wsel = wsel_st1; assign mreq_wsel = wsel_st1;
assign mreq_data = creq_data_st1;
if (NUM_PORTS > 1) begin if (NUM_PORTS > 1) begin
for (genvar p = 0; p < NUM_PORTS; ++p) begin for (genvar p = 0; p < NUM_PORTS; ++p) begin
@@ -491,10 +485,6 @@ module VX_bank #(
assign mreq_byteen[0] = byteen_st1[0]; assign mreq_byteen[0] = byteen_st1[0];
end end
for (genvar p = 0; p < NUM_PORTS; ++p) begin
assign mreq_data[p] = wdata_st1[wsel_st1[p] * `WORD_WIDTH +: `WORD_WIDTH];
end
VX_fifo_queue #( VX_fifo_queue #(
.DATAW (1 + `LINE_ADDR_WIDTH + MSHR_ADDR_WIDTH + NUM_PORTS * (WORD_SIZE + WORD_SELECT_BITS + `WORD_WIDTH)), .DATAW (1 + `LINE_ADDR_WIDTH + MSHR_ADDR_WIDTH + NUM_PORTS * (WORD_SIZE + WORD_SELECT_BITS + `WORD_WIDTH)),
.SIZE (MREQ_SIZE), .SIZE (MREQ_SIZE),

27
hw/rtl/cache/VX_data_access.v vendored
View File

@@ -32,13 +32,14 @@ module VX_data_access #(
// reading // reading
input wire readen, input wire readen,
output wire [`CACHE_LINE_WIDTH-1:0] rdata, output wire [`CACHE_LINE_WIDTH-1:0] read_data,
// writing // writing
input wire writeen, input wire writeen,
input wire is_fill, input wire is_fill,
input wire [CACHE_LINE_SIZE-1:0] byteen, input wire [CACHE_LINE_SIZE-1:0] byteen,
input wire [`CACHE_LINE_WIDTH-1:0] wdata input wire [`CACHE_LINE_WIDTH-1:0] write_data,
input wire [`CACHE_LINE_WIDTH-1:0] fill_data
); );
`UNUSED_PARAM (CACHE_ID) `UNUSED_PARAM (CACHE_ID)
@@ -50,16 +51,20 @@ module VX_data_access #(
localparam BYTEENW = WRITE_ENABLE ? CACHE_LINE_SIZE : 1; localparam BYTEENW = WRITE_ENABLE ? CACHE_LINE_SIZE : 1;
wire [`LINE_SELECT_BITS-1:0] line_addr; wire [`LINE_SELECT_BITS-1:0] line_addr;
wire [BYTEENW-1:0] byte_enable; wire [`CACHE_LINE_WIDTH-1:0] wdata;
wire [BYTEENW-1:0] wren;
assign line_addr = addr[`LINE_SELECT_BITS-1:0]; assign line_addr = addr[`LINE_SELECT_BITS-1:0];
if (WRITE_ENABLE) begin if (WRITE_ENABLE) begin
assign byte_enable = is_fill ? {BYTEENW{1'b1}} : byteen; assign wren = is_fill ? {BYTEENW{writeen}} : (byteen & {BYTEENW{writeen}});
assign wdata = is_fill ? fill_data : write_data;
end else begin end else begin
`UNUSED_VAR (byteen)
`UNUSED_VAR (is_fill) `UNUSED_VAR (is_fill)
assign byte_enable = 1'b1; `UNUSED_VAR (byteen)
`UNUSED_VAR (write_data)
assign wren = writeen;
assign wdata = fill_data;
end end
VX_sp_ram #( VX_sp_ram #(
@@ -70,10 +75,10 @@ module VX_data_access #(
) data_store ( ) data_store (
.clk (clk), .clk (clk),
.addr (line_addr), .addr (line_addr),
.wren ({BYTEENW{writeen}} & byte_enable), .wren (wren),
.wdata (wdata), .wdata (wdata),
.rden (1'b1), .rden (1'b1),
.rdata (rdata) .rdata (read_data)
); );
`UNUSED_VAR (stall) `UNUSED_VAR (stall)
@@ -82,13 +87,13 @@ module VX_data_access #(
always @(posedge clk) begin always @(posedge clk) begin
if (writeen && ~stall) begin if (writeen && ~stall) begin
if (is_fill) begin if (is_fill) begin
dpi_trace("%d: cache%0d:%0d data-fill: addr=%0h, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr, wdata); dpi_trace("%d: cache%0d:%0d data-fill: addr=%0h, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr, fill_data);
end else begin end else begin
dpi_trace("%d: cache%0d:%0d data-write: addr=%0h, wid=%0d, PC=%0h, byteen=%b, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, byte_enable, line_addr, wdata); dpi_trace("%d: cache%0d:%0d data-write: addr=%0h, wid=%0d, PC=%0h, byteen=%b, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, byte_enable, line_addr, write_data);
end end
end end
if (readen && ~stall) begin if (readen && ~stall) begin
dpi_trace("%d: cache%0d:%0d data-read: addr=%0h, wid=%0d, PC=%0h, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, line_addr, rdata); dpi_trace("%d: cache%0d:%0d data-read: addr=%0h, wid=%0d, PC=%0h, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, line_addr, read_data);
end end
end end
`endif `endif