pipeline refactoring
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@@ -22,7 +22,6 @@ module VX_execute #(
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// inputs
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VX_alu_req_if alu_req_if,
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VX_branch_req_if branch_req_if,
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VX_lsu_req_if lsu_req_if,
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VX_csr_req_if csr_req_if,
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VX_mul_req_if mul_req_if,
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@@ -32,7 +31,6 @@ module VX_execute #(
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VX_branch_ctl_if branch_ctl_if,
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VX_warp_ctl_if warp_ctl_if,
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VX_commit_if alu_commit_if,
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VX_commit_if branch_commit_if,
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VX_commit_if lsu_commit_if,
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VX_commit_if csr_commit_if,
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VX_commit_if mul_commit_if,
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@@ -47,17 +45,8 @@ module VX_execute #(
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.clk (clk),
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.reset (reset),
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.alu_req_if (alu_req_if),
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.alu_commit_if (alu_commit_if)
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);
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VX_branch_unit #(
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.CORE_ID(CORE_ID)
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) branch_unit (
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.clk (clk),
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.reset (reset),
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.branch_req_if (branch_req_if),
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.branch_ctl_if (branch_ctl_if),
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.branch_commit_if(branch_commit_if)
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.alu_commit_if (alu_commit_if)
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);
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VX_lsu_unit #(
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@@ -101,7 +90,7 @@ module VX_execute #(
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.gpu_commit_if (gpu_commit_if)
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);
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assign ebreak = (| branch_req_if.valid) && (branch_req_if.br_op == `BR_EBREAK || branch_req_if.br_op == `BR_ECALL);
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assign ebreak = (| alu_req_if.valid) && (alu_req_if.alu_op == `ALU_EBREAK || alu_req_if.alu_op == `ALU_ECALL);
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`SCOPE_ASSIGN(scope_decode_valid, decode_if.valid);
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`SCOPE_ASSIGN(scope_decode_warp_num, decode_if.warp_num);
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