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fixed write logic in generic_queue_ll

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This commit is contained in:
Blaise Tine
2020-03-07 06:56:11 -05:00
parent 90d10f4b7d
commit ddafe96ca6
3 changed files with 32 additions and 42 deletions
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3
rtl/Makefile
View File

@@ -46,5 +46,8 @@ debug: compdebug
w: VERILATORnoWarnings w: VERILATORnoWarnings
$(MAKECPP) $(MAKECPP)
run: w
(cd obj_dir && ./VVortex)
clean: clean:
rm obj_dir/* rm obj_dir/*

14
rtl/VX_generic_queue_ll.v
View File

@@ -76,6 +76,12 @@ module VX_generic_queue_ll
end end
end end
always @(posedge clk) begin
if (writing) begin
data[wr_ctr_r] <= in_data;
end
end
always @(posedge clk) begin always @(posedge clk) begin
if (reset) begin if (reset) begin
rd_ptr_r <= 0; rd_ptr_r <= 0;
@@ -92,15 +98,13 @@ module VX_generic_queue_ll
end end
end end
if (!(!reading && bypass_r)) begin bypass_r <= writing && (empty_r || (1 == size_r) && reading);
bypass_r <= writing && (empty_r || (1 == size_r && reading)); curr_r <= in_data;
curr_r <= in_data;
end
head_r <= data[reading ? rd_next_ptr_r : rd_ptr_r]; head_r <= data[reading ? rd_next_ptr_r : rd_ptr_r];
end end
end end
assign out_data = bypass_r ? curr_r : head_r; assign out_data = bypass_r ? curr_r : head_r;
assign empty = empty_r; assign empty = empty_r;
assign full = full_r; assign full = full_r;
end end

55
rtl/unit_tests/generic_queue/testbench.v
View File

@@ -10,14 +10,9 @@ module testbench();
reg[3:0] in_data; reg[3:0] in_data;
reg push; reg push;
reg pop; reg pop;
wire io_enq_ready;
wire[3:0] out_data; wire[3:0] out_data;
wire io_deq_valid; wire full;
wire empty;
wire full, empty;
assign io_enq_ready = !full;
assign io_deq_valid = !empty;
VX_generic_queue_ll #(.DATAW(4), .SIZE(4)) dut ( VX_generic_queue_ll #(.DATAW(4), .SIZE(4)) dut (
.clk(clk), .clk(clk),
@@ -34,40 +29,28 @@ module testbench();
end end
initial begin initial begin
$monitor ("%d: clk=%b rst=%b push=%b, pop=%b, din=%h, empty=%b, full=%b, dout=%h", $time, clk, reset, push, pop, in_data, empty, full, out_data); $monitor ("%d: clk=%b rst=%b push=%b, pop=%b, din=%h, empty=%b, full=%b, dout=%h",
#0 clk=0; reset=1; in_data=4'hd; push=1; pop=1; $time, clk, reset, push, pop, in_data, empty, full, out_data);
#1 `check(io_enq_ready, 1); `check(out_data, 4'hd); `check(io_deq_valid, 1); #0 clk=0; reset=1; pop=0; push=0;
#1 `check(io_enq_ready, 1); `check(out_data, 4'hx); `check(io_deq_valid, 0); #2 reset=0; in_data=4'ha; pop=0; push=1;
#0 reset=0; in_data=4'ha; pop=0; #2 `check(full, 0); `check(out_data, 4'ha); `check(empty, 0);
#1 `check(io_enq_ready, 1); `check(out_data, 4'hx); `check(io_deq_valid, 0);
#1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1);
#0 in_data=4'hb; #0 in_data=4'hb;
#1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1); #2 `check(full, 0); `check(out_data, 4'ha); `check(empty, 0);
#1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1);
#0 in_data=4'hc; #0 in_data=4'hc;
#1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1); #2 `check(full, 0); `check(out_data, 4'ha); `check(empty, 0);
#1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1);
#0 in_data=4'hd; #0 in_data=4'hd;
#1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1); #2 `check(full, 1); `check(out_data, 4'ha); `check(empty, 0);
#1 `check(io_enq_ready, 0); `check(out_data, 4'ha); `check(io_deq_valid, 1);
#0 push=0; pop=1; #0 push=0; pop=1;
#1 `check(io_enq_ready, 0); `check(out_data, 4'ha); `check(io_deq_valid, 1); #2 `check(full, 0); `check(out_data, 4'hb); `check(empty, 0);
#1 `check(io_enq_ready, 1); `check(out_data, 4'hb); `check(io_deq_valid, 1); #2 `check(full, 0); `check(out_data, 4'hc); `check(empty, 0);
#1 `check(io_enq_ready, 1); `check(out_data, 4'hb); `check(io_deq_valid, 1); #2 `check(full, 0); `check(out_data, 4'hd); `check(empty, 0);
#1 `check(io_enq_ready, 1); `check(out_data, 4'hc); `check(io_deq_valid, 1); #2 `check(full, 0); `check(out_data, 4'ha); `check(empty, 1);
#1 `check(io_enq_ready, 1); `check(out_data, 4'hc); `check(io_deq_valid, 1); #0 in_data=4'he; push=1; pop=0;
#1 `check(io_enq_ready, 1); `check(out_data, 4'hd); `check(io_deq_valid, 1); #2 `check(full, 0); `check(out_data, 4'he); `check(empty, 0);
#1 `check(io_enq_ready, 1); `check(out_data, 4'hd); `check(io_deq_valid, 1); #0 in_data=4'hf; pop=1;
#1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 0); #2 `check(full, 0); `check(out_data, 4'hf); `check(empty, 0);
#0 in_data=4'ha; push=1; pop=0;
#1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 0);
#1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1);
#0 in_data=4'hb; pop=1;
#1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1);
#1 `check(io_enq_ready, 1); `check(out_data, 4'hb); `check(io_deq_valid, 1);
#0 push=0; #0 push=0;
#1 `check(io_enq_ready, 1); `check(out_data, 4'hb); `check(io_deq_valid, 1); #2 `check(full, 0); `check(out_data, 4'hc); `check(empty, 1);
#1 `check(io_enq_ready, 1); `check(out_data, 4'hc); `check(io_deq_valid, 0);
#1 $finish; #1 $finish;
end end