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pipeline refactoring

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This commit is contained in:
Blaise Tine
2020-07-21 05:22:47 -04:00
parent e2100e9e87
commit dc7efbcfb4
31 changed files with 1437 additions and 6038 deletions
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12
hw/rtl/cache/VX_cache_miss_resrv.v vendored
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@@ -78,13 +78,11 @@ module VX_cache_miss_resrv #(
reg [MRVQ_SIZE-1:0] make_ready_push;
reg [MRVQ_SIZE-1:0] valid_address_match;
genvar i;
generate
for (i = 0; i < MRVQ_SIZE; i++) begin
assign valid_address_match[i] = valid_table[i] ? (addr_table[i] == fill_addr_st1) : 0;
assign make_ready[i] = is_fill_st1 && valid_address_match[i];
end
endgenerate
genvar i;
for (i = 0; i < MRVQ_SIZE; i++) begin
assign valid_address_match[i] = valid_table[i] ? (addr_table[i] == fill_addr_st1) : 0;
assign make_ready[i] = is_fill_st1 && valid_address_match[i];
end
assign pending_hazard = |(valid_address_match);