Made the cache module configurable for multi-instantiation

2020-03-07 00:49:40 -08:00
parent 90d10f4b7d
commit db11bf6990
22 changed files with 1209 additions and 493 deletions
--- a/rtl/interfaces/VX_gpu_dcache_dram_res_inter.v
+++ b/rtl/interfaces/VX_gpu_dcache_dram_res_inter.v
@@ -7,11 +7,15 @@

 `define VX_GPU_DRAM_DCACHE_RES

-interface VX_gpu_dcache_dram_res_inter ();
+interface VX_gpu_dcache_dram_res_inter
+	#(
+		parameter BANK_LINE_SIZE_WORDS = 2
+	)
+	();
 	// DRAM Rsponse
    wire                              dram_fill_rsp;
    wire [31:0]                       dram_fill_rsp_addr;
-    wire [`BANK_LINE_SIZE_RNG][31:0]  dram_fill_rsp_data;
+    wire [BANK_LINE_SIZE_WORDS-1:0][31:0]  dram_fill_rsp_data;

 endinterface