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block ram refactoring (multi-porting supporting and simulation support)

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This commit is contained in:
Blaise Tine
2021-08-26 08:19:44 -07:00
parent 06a6857508
commit d91d56d126
14 changed files with 480 additions and 353 deletions
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274
hw/rtl/libs/VX_dp_ram.v
View File

@@ -2,178 +2,286 @@
`TRACING_OFF
module VX_dp_ram #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter BYTEENW = 1,
parameter OUTPUT_REG = 0,
parameter RWCHECK = 1,
parameter ADDRW = $clog2(SIZE),
parameter FASTRAM = 0,
parameter INITZERO = 0
parameter RD_PORTS = 1,
parameter DATAW = 1,
parameter SIZE = 1,
parameter BYTEENW = 1,
parameter OUTPUT_REG = 0,
parameter NO_RWCHECK = 0,
parameter ADDRW = $clog2(SIZE),
parameter LUTRAM = 0,
parameter INIT_ENABLE = 0,
parameter INIT_FILE = "",
parameter [DATAW-1:0] INIT_VALUE = 0
) (
input wire clk,
input wire [ADDRW-1:0] waddr,
input wire [ADDRW-1:0] raddr,
input wire [BYTEENW-1:0] wren,
input wire [DATAW-1:0] din,
output wire [DATAW-1:0] dout
input wire clk,
input wire [BYTEENW-1:0] wren,
input wire [ADDRW-1:0] waddr,
input wire [DATAW-1:0] wdata,
input wire [RD_PORTS-1:0] rden,
input wire [RD_PORTS-1:0][ADDRW-1:0] raddr,
output wire [RD_PORTS-1:0][DATAW-1:0] rdata
);
`STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter"))
`STATIC_ASSERT(!LUTRAM || (RD_PORTS == 1), ("multi-porting not supported on LUTRAM"))
if (FASTRAM) begin
`define RAM_INITIALIZATION \
if (INIT_ENABLE) begin \
if (INIT_FILE != "") begin \
initial $readmemh(INIT_FILE, ram); \
end else begin \
initial ram = '{default: INIT_VALUE}; \
end \
end
`ifdef SYNTHESIS
if (LUTRAM) begin
if (OUTPUT_REG) begin
reg [DATAW-1:0] dout_r;
reg [DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[waddr][i] <= din[i * 8 +: 8];
ram[waddr][i] <= wdata[i * 8 +: 8];
end
dout_r <= mem[raddr];
if (rden)
rdata_r <= ram[raddr];
end
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
mem[waddr] <= din;
dout_r <= mem[raddr];
ram[waddr] <= wdata;
if (rden)
rdata_r <= ram[raddr];
end
end
assign dout = dout_r;
assign rdata = rdata_r;
end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[waddr][i] <= din[i * 8 +: 8];
ram[waddr][i] <= wdata[i * 8 +: 8];
end
end
assign dout = mem[raddr];
assign rdata = ram[raddr];
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
mem[waddr] <= din;
ram[waddr] <= wdata;
end
assign dout = mem[raddr];
assign rdata = ram[raddr];
end
end
end else begin
if (OUTPUT_REG) begin
reg [DATAW-1:0] dout_r;
reg [RD_PORTS-1:0][DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[waddr][i] <= din[i * 8 +: 8];
ram[waddr][i] <= wdata[i * 8 +: 8];
end
for (integer i = 0; i < RD_PORTS; ++i) begin
if (rden[i])
rdata_r[i] <= ram[raddr[i]];
end
dout_r <= mem[raddr];
end
end else begin
reg [DATAW-1:0] mem [SIZE-1:0];
reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
mem[waddr] <= din;
dout_r <= mem[raddr];
ram[waddr] <= wdata;
for (integer i = 0; i < RD_PORTS; ++i) begin
if (rden[i])
rdata_r[i] <= ram[raddr[i]];
end
end
end
assign dout = dout_r;
assign rdata = rdata_r;
end else begin
if (RWCHECK) begin
`UNUSED_VAR (rden)
if (NO_RWCHECK) begin
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
`NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[waddr][i] <= din[i * 8 +: 8];
ram[waddr][i] <= wdata[i * 8 +: 8];
end
end
assign dout = mem[raddr];
end else begin
reg [DATAW-1:0] mem [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
for (genvar i = 0; i < RD_PORTS; ++i) begin
assign rdata[i] = ram[raddr[i]];
end
end else begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
mem[waddr] <= din;
ram[waddr] <= wdata;
end
for (genvar i = 0; i < RD_PORTS; ++i) begin
assign rdata[i] = ram[raddr[i]];
end
assign dout = mem[raddr];
end
end else begin
if (BYTEENW > 1) begin
`NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[waddr][i] <= din[i * 8 +: 8];
ram[waddr][i] <= wdata[i * 8 +: 8];
end
end
assign dout = mem[raddr];
for (genvar i = 0; i < RD_PORTS; ++i) begin
assign rdata[i] = ram[raddr[i]];
end
end else begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0];
reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
mem[waddr] <= din;
ram[waddr] <= wdata;
end
for (genvar i = 0; i < RD_PORTS; ++i) begin
assign rdata[i] = ram[raddr[i]];
end
assign dout = mem[raddr];
end
end
end
end
`else
if (OUTPUT_REG) begin
reg [RD_PORTS-1:0][DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
ram[waddr][i] <= wdata[i * 8 +: 8];
end
for (integer i = 0; i < RD_PORTS; ++i) begin
if (rden[i])
rdata_r[i] <= ram[raddr[i]];
end
end
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
for (integer i = 0; i < RD_PORTS; ++i) begin
if (rden[i])
rdata_r[i] <= ram[raddr[i]];
end
end
end
assign rdata = rdata_r;
end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
reg [DATAW-1:0] prev_data;
reg [ADDRW-1:0] prev_waddr;
reg prev_write;
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
ram[waddr][i] <= wdata[i * 8 +: 8];
end
prev_write <= (| wren);
prev_data <= ram[waddr];
prev_waddr <= waddr;
end
if (LUTRAM || !NO_RWCHECK) begin
`UNUSED_VAR (prev_write)
`UNUSED_VAR (prev_data)
`UNUSED_VAR (prev_waddr)
for (genvar i = 0; i < RD_PORTS; ++i) begin
assign rdata[i] = ram[raddr[i]];
end
end else begin
for (genvar i = 0; i < RD_PORTS; ++i) begin
assign rdata[i] = (prev_write && (prev_waddr == raddr[i])) ? prev_data : ram[raddr[i]];
end
end
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
reg [DATAW-1:0] prev_data;
reg [ADDRW-1:0] prev_waddr;
reg prev_write;
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
prev_write <= wren;
prev_data <= ram[waddr];
prev_waddr <= waddr;
end
if (LUTRAM || !NO_RWCHECK) begin
`UNUSED_VAR (prev_write)
`UNUSED_VAR (prev_data)
`UNUSED_VAR (prev_waddr)
for (genvar i = 0; i < RD_PORTS; ++i) begin
assign rdata[i] = ram[raddr[i]];
end
end else begin
for (genvar i = 0; i < RD_PORTS; ++i) begin
assign rdata[i] = (prev_write && (prev_waddr == raddr[i])) ? prev_data : ram[raddr[i]];
end
end
end
end
`endif
endmodule
`TRACING_ON

4
hw/rtl/libs/VX_elastic_buffer.v
View File

@@ -5,7 +5,7 @@ module VX_elastic_buffer #(
parameter DATAW = 1,
parameter SIZE = 2,
parameter OUTPUT_REG = 0,
parameter FASTRAM = 0
parameter LUTRAM = 0
) (
input wire clk,
input wire reset,
@@ -56,7 +56,7 @@ module VX_elastic_buffer #(
.DATAW (DATAW),
.SIZE (SIZE),
.OUTPUT_REG (OUTPUT_REG),
.FASTRAM (FASTRAM)
.LUTRAM (LUTRAM)
) queue (
.clk (clk),
.reset (reset),

32
hw/rtl/libs/VX_fifo_queue.v
View File

@@ -9,7 +9,7 @@ module VX_fifo_queue #(
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1),
parameter OUTPUT_REG = 0,
parameter FASTRAM = 1
parameter LUTRAM = 1
) (
input wire clk,
input wire reset,
@@ -157,15 +157,15 @@ module VX_fifo_queue #(
.DATAW (DATAW),
.SIZE (SIZE),
.OUTPUT_REG (0),
.RWCHECK (1),
.FASTRAM (FASTRAM)
.LUTRAM (LUTRAM)
) dp_ram (
.clk(clk),
.waddr(wr_ptr_r),
.raddr(rd_ptr_r),
.wren(push),
.din(data_in),
.dout(data_out)
.wren (push),
.waddr (wr_ptr_r),
.wdata (data_in),
.rden (1'b1),
.raddr (rd_ptr_r),
.rdata (data_out)
);
end else begin
@@ -200,15 +200,15 @@ module VX_fifo_queue #(
.DATAW (DATAW),
.SIZE (SIZE),
.OUTPUT_REG (0),
.RWCHECK (1),
.FASTRAM (FASTRAM)
.LUTRAM (LUTRAM)
) dp_ram (
.clk(clk),
.waddr(wr_ptr_r),
.raddr(rd_ptr_n_r),
.wren(push),
.din(data_in),
.dout(dout)
.clk (clk),
.wren (push),
.waddr (wr_ptr_r),
.wdata (data_in),
.rden (1'b1),
.raddr (rd_ptr_n_r),
.rdata (dout)
);
always @(posedge clk) begin

28
hw/rtl/libs/VX_index_buffer.v
View File

@@ -2,10 +2,10 @@
`TRACING_OFF
module VX_index_buffer #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter FASTRAM = 1,
parameter ADDRW = `LOG2UP(SIZE)
parameter DATAW = 1,
parameter SIZE = 1,
parameter LUTRAM = 1,
parameter ADDRW = `LOG2UP(SIZE)
) (
input wire clk,
input wire reset,
@@ -68,17 +68,17 @@ module VX_index_buffer #(
end
VX_dp_ram #(
.DATAW(DATAW),
.SIZE(SIZE),
.RWCHECK(1),
.FASTRAM(FASTRAM)
.DATAW (DATAW),
.SIZE (SIZE),
.LUTRAM (LUTRAM)
) data_table (
.clk(clk),
.waddr(write_addr),
.raddr(read_addr),
.wren(acquire_slot),
.din(write_data),
.dout(read_data)
.clk (clk),
.wren (acquire_slot),
.waddr (write_addr),
.wdata (write_data),
.rden (1'b1),
.raddr (read_addr),
.rdata (read_data)
);
assign write_addr = write_addr_r;

242
hw/rtl/libs/VX_sp_ram.v
View File

@@ -2,177 +2,259 @@
`TRACING_OFF
module VX_sp_ram #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter BYTEENW = 1,
parameter OUTPUT_REG = 0,
parameter RWCHECK = 1,
parameter ADDRW = $clog2(SIZE),
parameter FASTRAM = 0,
parameter INITZERO = 0
) (
input wire clk,
input wire [ADDRW-1:0] addr,
parameter DATAW = 1,
parameter SIZE = 1,
parameter BYTEENW = 1,
parameter OUTPUT_REG = 0,
parameter NO_RWCHECK = 0,
parameter ADDRW = $clog2(SIZE),
parameter LUTRAM = 0,
parameter INIT_ENABLE = 0,
parameter INIT_FILE = "",
parameter [DATAW-1:0] INIT_VALUE = 0
) (
input wire clk,
input wire [ADDRW-1:0] addr,
input wire [BYTEENW-1:0] wren,
input wire [DATAW-1:0] din,
output wire [DATAW-1:0] dout
input wire [DATAW-1:0] wdata,
input wire rden,
output wire [DATAW-1:0] rdata
);
`STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter"))
if (FASTRAM) begin
`define RAM_INITIALIZATION \
if (INIT_ENABLE) begin \
if (INIT_FILE != "") begin \
initial $readmemh(INIT_FILE, ram); \
end else begin \
initial ram = '{default: INIT_VALUE}; \
end \
end
`ifdef SYNTHESIS
if (LUTRAM) begin
if (OUTPUT_REG) begin
reg [DATAW-1:0] dout_r;
reg [DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[addr][i] <= din[i * 8 +: 8];
ram[addr][i] <= wdata[i * 8 +: 8];
end
dout_r <= mem[addr];
if (rden)
rdata_r <= ram[addr];
end
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
mem[addr] <= din;
dout_r <= mem[addr];
ram[addr] <= wdata;
if (rden)
rdata_r <= ram[addr];
end
end
assign dout = dout_r;
assign rdata = rdata_r;
end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[addr][i] <= din[i * 8 +: 8];
ram[addr][i] <= wdata[i * 8 +: 8];
end
end
assign dout = mem[addr];
assign rdata = ram[addr];
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
mem[addr] <= din;
ram[addr] <= wdata;
end
assign dout = mem[addr];
assign rdata = ram[addr];
end
end
end else begin
if (OUTPUT_REG) begin
reg [DATAW-1:0] dout_r;
reg [DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[addr][i] <= din[i * 8 +: 8];
ram[addr][i] <= wdata[i * 8 +: 8];
end
dout_r <= mem[addr];
if (rden)
rdata_r <= ram[addr];
end
end else begin
reg [DATAW-1:0] mem [SIZE-1:0];
reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
mem[addr] <= din;
dout_r <= mem[addr];
ram[addr] <= wdata;
if (rden)
rdata_r <= ram[addr];
end
end
assign dout = dout_r;
assign rdata = rdata_r;
end else begin
if (RWCHECK) begin
`UNUSED_VAR (rden)
if (NO_RWCHECK) begin
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
`NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[addr][i] <= din[i * 8 +: 8];
ram[addr][i] <= wdata[i * 8 +: 8];
end
end
assign dout = mem[addr];
assign rdata = ram[addr];
end else begin
reg [DATAW-1:0] mem [SIZE-1:0];
`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
mem[addr] <= din;
ram[addr] <= wdata;
end
assign dout = mem[addr];
assign rdata = ram[addr];
end
end else begin
if (BYTEENW > 1) begin
`NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[addr][i] <= din[i * 8 +: 8];
ram[addr][i] <= wdata[i * 8 +: 8];
end
end
assign dout = mem[addr];
assign rdata = ram[addr];
end else begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0];
reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
mem[addr] <= din;
ram[addr] <= wdata;
end
assign dout = mem[addr];
assign rdata = ram[addr];
end
end
end
end
`else
if (OUTPUT_REG) begin
reg [DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
ram[addr][i] <= wdata[i * 8 +: 8];
end
if (rden)
rdata_r <= ram[addr];
end
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
if (rden)
rdata_r <= ram[addr];
end
end
assign rdata = rdata_r;
end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
reg [DATAW-1:0] prev_data;
reg [ADDRW-1:0] prev_addr;
reg prev_write;
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
ram[addr][i] <= wdata[i * 8 +: 8];
end
prev_write <= (| wren);
prev_data <= ram[addr];
prev_addr <= addr;
end
if (LUTRAM || !NO_RWCHECK) begin
`UNUSED_VAR (prev_write)
`UNUSED_VAR (prev_data)
`UNUSED_VAR (prev_addr)
assign rdata = ram[addr];
end else begin
assign rdata = (prev_write && (prev_addr == addr)) ? prev_data : ram[addr];
end
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
reg [DATAW-1:0] prev_data;
reg [ADDRW-1:0] prev_addr;
reg prev_write;
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
prev_write <= wren;
prev_data <= ram[addr];
prev_addr <= addr;
end
if (LUTRAM || !NO_RWCHECK) begin
`UNUSED_VAR (prev_write)
`UNUSED_VAR (prev_data)
`UNUSED_VAR (prev_addr)
assign rdata = ram[addr];
end else begin
assign rdata = (prev_write && (prev_addr == addr)) ? prev_data : ram[addr];
end
end
end
`endif
endmodule
`TRACING_ON