remove tab spaces
This commit is contained in:
Blaise Tine
134
hw/rtl/VX_lsu.v
134
hw/rtl/VX_lsu.v
@@ -1,87 +1,89 @@
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`include "VX_define.vh"
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module VX_lsu (
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input wire clk,
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input wire reset,
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input wire no_slot_mem,
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VX_lsu_req_if lsu_req_if,
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input wire clk,
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input wire reset,
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input wire no_slot_mem,
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VX_lsu_req_if lsu_req_if,
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// Write back to GPR
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VX_inst_mem_wb_if mem_wb_if,
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// Write back to GPR
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VX_inst_mem_wb_if mem_wb_if,
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VX_gpu_dcache_rsp_if dcache_rsp_if,
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VX_gpu_dcache_req_if dcache_req_if,
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output wire delay
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VX_gpu_dcache_rsp_if dcache_rsp_if,
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VX_gpu_dcache_req_if dcache_req_if,
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output wire delay
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);
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// Generate Addresses
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wire[`NUM_THREADS-1:0][31:0] address;
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VX_lsu_addr_gen VX_lsu_addr_gen (
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.base_address (lsu_req_if.base_address),
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.offset (lsu_req_if.offset),
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.address (address)
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);
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// Generate Addresses
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wire[`NUM_THREADS-1:0][31:0] address;
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VX_lsu_addr_gen VX_lsu_addr_gen (
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.base_address (lsu_req_if.base_address),
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.offset (lsu_req_if.offset),
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.address (address)
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);
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wire[`NUM_THREADS-1:0][31:0] use_address;
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wire[`NUM_THREADS-1:0][31:0] use_store_data;
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wire[`NUM_THREADS-1:0] use_valid;
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wire[2:0] use_mem_read;
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wire[2:0] use_mem_write;
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wire[4:0] use_rd;
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wire[`NW_BITS-1:0] use_warp_num;
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wire[1:0] use_wb;
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wire[31:0] use_pc;
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wire[`NUM_THREADS-1:0][31:0] use_address;
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wire[`NUM_THREADS-1:0][31:0] use_store_data;
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wire[`NUM_THREADS-1:0] use_valid;
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wire[2:0] use_mem_read;
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wire[2:0] use_mem_write;
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wire[4:0] use_rd;
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wire[`NW_BITS-1:0] use_warp_num;
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wire[1:0] use_wb;
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wire[31:0] use_pc;
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wire zero = 0;
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wire zero = 0;
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VX_generic_register #(
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.N(45 + `NW_BITS-1 + 1 + `NUM_THREADS*65)
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) lsu_buffer(
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.clk (clk),
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.reset(reset),
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.stall(delay),
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.flush(zero),
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.in ({address , lsu_req_if.store_data, lsu_req_if.valid, lsu_req_if.mem_read, lsu_req_if.mem_write, lsu_req_if.rd, lsu_req_if.warp_num, lsu_req_if.wb, lsu_req_if.lsu_pc}),
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.out ({use_address, use_store_data , use_valid , use_mem_read , use_mem_write , use_rd , use_warp_num , use_wb , use_pc })
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);
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VX_generic_register #(
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.N(45 + `NW_BITS-1 + 1 + `NUM_THREADS*65)
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) lsu_buffer(
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.clk (clk),
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.reset(reset),
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.stall(delay),
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.flush(zero),
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.in ({address , lsu_req_if.store_data, lsu_req_if.valid, lsu_req_if.mem_read, lsu_req_if.mem_write, lsu_req_if.rd, lsu_req_if.warp_num, lsu_req_if.wb, lsu_req_if.lsu_pc}),
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.out ({use_address, use_store_data , use_valid , use_mem_read , use_mem_write , use_rd , use_warp_num , use_wb , use_pc })
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);
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// Core Request
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assign dcache_req_if.core_req_valid = use_valid;
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assign dcache_req_if.core_req_addr = use_address;
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assign dcache_req_if.core_req_data = use_store_data;
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assign dcache_req_if.core_req_read = {`NUM_THREADS{use_mem_read}};
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assign dcache_req_if.core_req_write = {`NUM_THREADS{use_mem_write}};
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assign dcache_req_if.core_req_rd = use_rd;
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assign dcache_req_if.core_req_wb = {`NUM_THREADS{use_wb}};
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assign dcache_req_if.core_req_warp_num = use_warp_num;
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assign dcache_req_if.core_req_pc = use_pc;
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// Core Request
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assign dcache_req_if.core_req_valid = use_valid;
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assign dcache_req_if.core_req_addr = use_address;
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assign dcache_req_if.core_req_data = use_store_data;
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assign dcache_req_if.core_req_read = {`NUM_THREADS{use_mem_read}};
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assign dcache_req_if.core_req_write = {`NUM_THREADS{use_mem_write}};
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assign dcache_req_if.core_req_rd = use_rd;
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assign dcache_req_if.core_req_wb = {`NUM_THREADS{use_wb}};
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assign dcache_req_if.core_req_warp_num = use_warp_num;
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assign dcache_req_if.core_req_pc = use_pc;
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// Core can't accept response
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assign dcache_rsp_if.core_rsp_ready = ~no_slot_mem;
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// Core can't accept response
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assign dcache_rsp_if.core_rsp_ready = ~no_slot_mem;
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// Cache can't accept request
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assign delay = ~dcache_req_if.core_req_ready;
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// Cache can't accept request
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assign delay = ~dcache_req_if.core_req_ready;
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// Core Response
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assign mem_wb_if.rd = dcache_rsp_if.core_rsp_read;
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assign mem_wb_if.wb = dcache_rsp_if.core_rsp_write;
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assign mem_wb_if.wb_valid = dcache_rsp_if.core_rsp_valid;
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assign mem_wb_if.wb_warp_num = dcache_rsp_if.core_rsp_warp_num;
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assign mem_wb_if.loaded_data = dcache_rsp_if.core_rsp_data;
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wire[(`LOG2UP(`NUM_THREADS))-1:0] use_pc_index;
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// Core Response
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assign mem_wb_if.rd = dcache_rsp_if.core_rsp_read;
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assign mem_wb_if.wb = dcache_rsp_if.core_rsp_write;
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assign mem_wb_if.wb_valid = dcache_rsp_if.core_rsp_valid;
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assign mem_wb_if.wb_warp_num = dcache_rsp_if.core_rsp_warp_num;
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assign mem_wb_if.loaded_data = dcache_rsp_if.core_rsp_data;
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wire[(`LOG2UP(`NUM_THREADS))-1:0] use_pc_index;
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`DEBUG_BEGIN
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wire found;
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wire found;
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`DEBUG_END
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VX_generic_priority_encoder #(.N(`NUM_THREADS)) pick_first_pc(
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.valids(dcache_rsp_if.core_rsp_valid),
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.index (use_pc_index),
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.found (found)
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);
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VX_generic_priority_encoder #(
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.N(`NUM_THREADS)
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) pick_first_pc (
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.valids(dcache_rsp_if.core_rsp_valid),
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.index (use_pc_index),
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.found (found)
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);
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assign mem_wb_if.mem_wb_pc = dcache_rsp_if.core_rsp_pc[use_pc_index];
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assign mem_wb_if.mem_wb_pc = dcache_rsp_if.core_rsp_pc[use_pc_index];
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endmodule // Memory
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