remove tab spaces
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Blaise Tine
@@ -1,84 +1,84 @@
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`include "VX_define.vh"
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module VX_csr_data (
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input wire clk, // Clock
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input wire reset,
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input wire clk, // Clock
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input wire reset,
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input wire[`CSR_ADDR_SIZE-1:0] read_csr_address,
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input wire write_valid,
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input wire[`CSR_WIDTH-1:0] write_csr_data,
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input wire[`CSR_ADDR_SIZE-1:0] read_csr_address,
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input wire write_valid,
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input wire[`CSR_WIDTH-1:0] write_csr_data,
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`IGNORE_WARNINGS_BEGIN
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// We use a smaller storage for CSRs than the standard 4KB in RISC-V
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input wire[`CSR_ADDR_SIZE-1:0] write_csr_address,
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input wire[`CSR_ADDR_SIZE-1:0] write_csr_address,
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`IGNORE_WARNINGS_END
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output wire[31:0] read_csr_data,
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output wire[31:0] read_csr_data,
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// For instruction retire counting
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input wire writeback_valid
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// For instruction retire counting
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input wire writeback_valid
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);
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// wire[`NUM_THREADS-1:0][31:0] thread_ids;
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// wire[`NUM_THREADS-1:0][31:0] warp_ids;
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// wire[`NUM_THREADS-1:0][31:0] thread_ids;
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// wire[`NUM_THREADS-1:0][31:0] warp_ids;
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// genvar cur_t;
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// for (cur_t = 0; cur_t < `NUM_THREADS; cur_t = cur_t + 1) begin
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// assign thread_ids[cur_t] = cur_t;
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// end
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// genvar cur_t;
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// for (cur_t = 0; cur_t < `NUM_THREADS; cur_t = cur_t + 1) begin
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// assign thread_ids[cur_t] = cur_t;
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// end
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// genvar cur_tw;
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// for (cur_tw = 0; cur_tw < `NUM_THREADS; cur_tw = cur_tw + 1) begin
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// assign warp_ids[cur_tw] = {{(31-`NW_BITS-1){1'b0}}, in_read_warp_num};
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// end
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// genvar cur_tw;
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// for (cur_tw = 0; cur_tw < `NUM_THREADS; cur_tw = cur_tw + 1) begin
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// assign warp_ids[cur_tw] = {{(31-`NW_BITS-1){1'b0}}, in_read_warp_num};
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// end
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reg [`CSR_WIDTH-1:0] csr[`NUM_CSRS-1:0];
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reg [`CSR_WIDTH-1:0] csr[`NUM_CSRS-1:0];
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reg [63:0] cycle;
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reg [63:0] instret;
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reg [63:0] cycle;
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reg [63:0] instret;
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wire read_cycle;
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wire read_cycleh;
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wire read_instret;
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wire read_instreth;
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wire read_cycle;
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wire read_cycleh;
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wire read_instret;
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wire read_instreth;
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assign read_cycle = read_csr_address == `CSR_CYCL_L;
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assign read_cycleh = read_csr_address == `CSR_CYCL_H;
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assign read_instret = read_csr_address == `CSR_INST_L;
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assign read_instreth = read_csr_address == `CSR_INST_H;
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assign read_cycle = read_csr_address == `CSR_CYCL_L;
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assign read_cycleh = read_csr_address == `CSR_CYCL_H;
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assign read_instret = read_csr_address == `CSR_INST_L;
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assign read_instreth = read_csr_address == `CSR_INST_H;
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wire [$clog2(`NUM_CSRS)-1:0] read_addr, write_addr;
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wire [$clog2(`NUM_CSRS)-1:0] read_addr, write_addr;
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// cast address to physical CSR range
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assign read_addr = $size(read_addr)'(read_csr_address);
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assign write_addr = $size(write_addr)'(write_csr_address);
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// cast address to physical CSR range
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assign read_addr = $size(read_addr)'(read_csr_address);
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assign write_addr = $size(write_addr)'(write_csr_address);
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// wire thread_select = read_csr_address == 12'h20;
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// wire warp_select = read_csr_address == 12'h21;
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// wire thread_select = read_csr_address == 12'h20;
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// wire warp_select = read_csr_address == 12'h21;
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// assign read_csr_data = thread_select ? thread_ids :
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// warp_select ? warp_ids :
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// 0;
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// assign read_csr_data = thread_select ? thread_ids :
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// warp_select ? warp_ids :
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// 0;
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genvar curr_e;
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genvar curr_e;
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always @(posedge clk) begin
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if (reset) begin
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cycle <= 0;
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instret <= 0;
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end else begin
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cycle <= cycle + 1;
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if (write_valid) begin
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csr[write_addr] <= write_csr_data;
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end
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if (writeback_valid) begin
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instret <= instret + 1;
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end
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end
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end
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always @(posedge clk) begin
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if (reset) begin
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cycle <= 0;
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instret <= 0;
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end else begin
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cycle <= cycle + 1;
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if (write_valid) begin
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csr[write_addr] <= write_csr_data;
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end
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if (writeback_valid) begin
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instret <= instret + 1;
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end
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end
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end
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assign read_csr_data = read_cycle ? cycle[31:0] :
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read_cycleh ? cycle[63:32] :
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read_instret ? instret[31:0] :
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read_instreth ? instret[63:32] :
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{{20{1'b0}}, csr[read_addr]};
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assign read_csr_data = read_cycle ? cycle[31:0] :
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read_cycleh ? cycle[63:32] :
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read_instret ? instret[31:0] :
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read_instreth ? instret[63:32] :
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{{20{1'b0}}, csr[read_addr]};
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endmodule : VX_csr_data
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