minor update
This commit is contained in:
18
hw/rtl/cache/VX_miss_resrv.v
vendored
18
hw/rtl/cache/VX_miss_resrv.v
vendored
@@ -71,8 +71,6 @@ module VX_miss_resrv #(
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output wire dequeue_snp_inv_st0,
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output wire dequeue_snp_inv_st0,
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input wire dequeue_st3
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input wire dequeue_st3
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);
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);
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wire [`MSHR_DATA_WIDTH-1:0] data_table;
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reg [`LINE_ADDR_WIDTH-1:0] addr_table [MSHR_SIZE-1:0];
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reg [`LINE_ADDR_WIDTH-1:0] addr_table [MSHR_SIZE-1:0];
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reg [MSHR_SIZE-1:0] valid_table;
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reg [MSHR_SIZE-1:0] valid_table;
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@@ -95,15 +93,7 @@ module VX_miss_resrv #(
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assign dequeue_valid_st0 = dequeue_ready;
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assign dequeue_valid_st0 = dequeue_ready;
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assign dequeue_addr_st0 = addr_table[schedule_ptr];
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assign dequeue_addr_st0 = addr_table[schedule_ptr];
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assign {dequeue_data_st0,
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dequeue_tid_st0,
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dequeue_tag_st0,
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dequeue_rw_st0,
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dequeue_byteen_st0,
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dequeue_wsel_st0,
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dequeue_is_snp_st0,
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dequeue_snp_inv_st0} = data_table;
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wire mshr_push = enqueue_st3 && !enqueue_is_mshr_st3;
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wire mshr_push = enqueue_st3 && !enqueue_is_mshr_st3;
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wire [`LOG2UP(MSHR_SIZE)-1:0] head_ptr_n = head_ptr + $bits(head_ptr)'(1);
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wire [`LOG2UP(MSHR_SIZE)-1:0] head_ptr_n = head_ptr + $bits(head_ptr)'(1);
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@@ -164,15 +154,15 @@ module VX_miss_resrv #(
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.BYTEENW(1),
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.BYTEENW(1),
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.BUFFERED(0),
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.BUFFERED(0),
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.RWCHECK(1)
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.RWCHECK(1)
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) metadata (
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) datatable (
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.clk(clk),
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.clk(clk),
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.waddr(tail_ptr),
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.waddr(tail_ptr),
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.raddr(schedule_ptr),
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.raddr(schedule_ptr),
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.wren(mshr_push),
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.wren(mshr_push),
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.byteen(1'b1),
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.byteen(1'b1),
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.rden(1'b1),
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.rden(1'b1),
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.din({enqueue_data_st3, enqueue_tid_st3, enqueue_tag_st3, enqueue_rw_st3, enqueue_byteen_st3, enqueue_wsel_st3, enqueue_is_snp_st3, enqueue_snp_inv_st3}),
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.din({enqueue_data_st3, enqueue_tid_st3, enqueue_tag_st3, enqueue_rw_st3, enqueue_byteen_st3, enqueue_wsel_st3, enqueue_is_snp_st3, enqueue_snp_inv_st3}),
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.dout(data_table)
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.dout({dequeue_data_st0, dequeue_tid_st0, dequeue_tag_st0, dequeue_rw_st0, dequeue_byteen_st0, dequeue_wsel_st0, dequeue_is_snp_st0, dequeue_snp_inv_st0})
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);
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);
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`ifdef DBG_PRINT_CACHE_MSHR
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`ifdef DBG_PRINT_CACHE_MSHR
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@@ -65,7 +65,7 @@ module VX_cam_buffer #(
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.SIZE(SIZE),
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.SIZE(SIZE),
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.BUFFERED(0),
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.BUFFERED(0),
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.RWCHECK(0)
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.RWCHECK(0)
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) req_metadata (
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) data_table (
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.clk(clk),
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.clk(clk),
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.waddr(write_addr),
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.waddr(write_addr),
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.raddr(read_addr),
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.raddr(read_addr),
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