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scope refactoring + snoop invalidate

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This commit is contained in:
Blaise Tine
2020-06-12 00:04:31 -07:00
parent 19f263c772
commit d6b0ef2b3c
44 changed files with 652 additions and 589 deletions
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62
hw/rtl/VX_gpr.v
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@@ -3,40 +3,40 @@
module VX_gpr (
input wire clk,
input wire reset,
input wire valid_write_request,
input wire write_ce,
VX_gpr_read_if gpr_read_if,
VX_wb_if writeback_if,
output wire[`NUM_THREADS-1:0][`NUM_GPRS-1:0] a_reg_data,
output wire[`NUM_THREADS-1:0][`NUM_GPRS-1:0] b_reg_data
output wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] a_reg_data,
output wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] b_reg_data
);
wire[`NUM_THREADS-1:0][`NUM_GPRS-1:0] a_reg_data_uqual;
wire[`NUM_THREADS-1:0][`NUM_GPRS-1:0] b_reg_data_uqual;
wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] a_reg_data_uqual;
wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] b_reg_data_uqual;
assign a_reg_data = (gpr_read_if.rs1 != 0) ? a_reg_data_uqual : 0;
assign b_reg_data = (gpr_read_if.rs2 != 0) ? b_reg_data_uqual : 0;
wire write_enable = valid_write_request && ((writeback_if.wb != 0));
wire write_enable = write_ce && ((writeback_if.wb != 0));
`ifndef ASIC
VX_gpr_ram gpr_ram (
.we (write_enable),
.clk (clk),
.reset (reset),
.waddr (writeback_if.rd),
.raddr1(gpr_read_if.rs1),
.raddr2(gpr_read_if.rs2),
.be (writeback_if.valid),
.wdata (writeback_if.data),
.q1 (a_reg_data_uqual),
.q2 (b_reg_data_uqual)
.we (write_enable),
.clk (clk),
.reset (reset),
.waddr (writeback_if.rd),
.raddr1 (gpr_read_if.rs1),
.raddr2 (gpr_read_if.rs2),
.be (writeback_if.valid),
.wdata (writeback_if.data),
.q1 (a_reg_data_uqual),
.q2 (b_reg_data_uqual)
);
`else
wire going_to_write = write_enable & (| writeback_if.wb_valid);
wire[`NUM_THREADS-1:0][`NUM_GPRS-1:0] write_bit_mask;
wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] write_bit_mask;
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin
@@ -44,31 +44,27 @@ module VX_gpr (
assign write_bit_mask[i] = {`NUM_GPRS{~local_write}};
end
// wire cenb = !going_to_write;
wire cenb = 0;
wire cenb = 0;
wire cena_1 = 0;
wire cena_2 = 0;
// wire cena_1 = (gpr_read_if.rs1 == 0);
// wire cena_2 = (gpr_read_if.rs2 == 0);
wire cena_1 = 0;
wire cena_2 = 0;
wire[`NUM_THREADS-1:0][`NUM_GPRS-1:0] temp_a;
wire[`NUM_THREADS-1:0][`NUM_GPRS-1:0] temp_b;
wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] tmp_a;
wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] tmp_b;
`ifndef SYN
genvar j;
for (i = 0; i < `NUM_THREADS; i++) begin
for (j = 0; j < `NUM_GPRS; j++) begin
assign a_reg_data_uqual[i][j] = ((temp_a[i][j] === 1'dx) || cena_1 )? 1'b0 : temp_a[i][j];
assign b_reg_data_uqual[i][j] = ((temp_b[i][j] === 1'dx) || cena_2) ? 1'b0 : temp_b[i][j];
assign a_reg_data_uqual[i][j] = ((tmp_a[i][j] === 1'dx) || cena_1) ? 1'b0 : tmp_a[i][j];
assign b_reg_data_uqual[i][j] = ((tmp_b[i][j] === 1'dx) || cena_2) ? 1'b0 : tmp_b[i][j];
end
end
`else
assign a_reg_data_uqual = temp_a;
assign b_reg_data_uqual = temp_b;
assign a_reg_data_uqual = tmp_a;
assign b_reg_data_uqual = tmp_b;
`endif
wire[`NUM_THREADS-1:0][`NUM_GPRS-1:0] to_write = writeback_if.write_data;
wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] to_write = writeback_if.write_data;
for (i = 0; i < 'NT; i=i+4)
begin
@@ -79,7 +75,7 @@ module VX_gpr (
.CENYB(),
.WENYB(),
.AYB(),
.QA(temp_a[(i+3):(i)]),
.QA(tmp_a[(i+3):(i)]),
.SOA(),
.SOB(),
.CLKA(clk),
@@ -116,7 +112,7 @@ module VX_gpr (
.CENYB(),
.WENYB(),
.AYB(),
.QA(temp_b[(i+3):(i)]),
.QA(tmp_b[(i+3):(i)]),
.SOA(),
.SOB(),
.CLKA(clk),