cache req datapath optimizations

2020-12-08 02:58:08 -08:00
parent 268ad15098
commit d5fa82f5e4
17 changed files with 393 additions and 410 deletions
--- a/hw/rtl/libs/VX_cam_buffer.v
+++ b/hw/rtl/libs/VX_cam_buffer.v
@@ -52,9 +52,7 @@ module VX_cam_buffer #(
            write_addr_r <= ADDRW'(1'b0);
        end else begin
            if (release_slot) begin
-                assert(0 == free_slots[release_addr]) else begin 
-                    $display("%t: releasing invalid slot at port %d", $time, release_addr);
-                end
+                assert(0 == free_slots[release_addr]) else $error("%t: releasing invalid slot at port %d", $time, release_addr);
            end
            free_slots   <= free_slots_n;
            write_addr_r <= free_index;