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cache req datapath optimizations

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This commit is contained in:
Blaise Tine
2020-12-08 02:58:08 -08:00
parent 268ad15098
commit d5fa82f5e4
17 changed files with 393 additions and 410 deletions
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19
hw/rtl/cache/VX_bank.v vendored
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@@ -264,7 +264,9 @@ module VX_bank #(
.full (creq_full)
);
reg [$clog2(MSHR_SIZE+1)-1:0] mshr_pending_size;
reg [$clog2(MSHR_SIZE+1)-1:0] mshr_pending_size;
wire [$clog2(MSHR_SIZE+1)-1:0] mshr_pending_size_n;
reg mshr_going_full;
wire mshr_pop;
wire mshr_valid_st0;
wire[`REQS_BITS-1:0] mshr_tid_st0;
@@ -346,14 +348,12 @@ module VX_bank #(
wire dreq_push_stall;
wire srsq_push_stall;
wire pipeline_stall;
wire is_mshr_miss_st2 = valid_st2 && is_mshr_st2 && (miss_st2 || force_miss_st2);
wire is_mshr_miss_st3 = valid_st3 && is_mshr_st3 && (miss_st3 || force_miss_st3);
wire creq_commit = valid_st1 && core_req_hit_st1 && !pipeline_stall;
wire mshr_going_full = (mshr_pending_size == MSHR_SIZE);
// determine which queue to pop next in piority order
wire mshr_pop_unqual = mshr_valid_st0;
wire drsq_pop_unqual = !mshr_pop_unqual && !drsq_empty;
@@ -367,13 +367,16 @@ module VX_bank #(
assign sreq_pop = sreq_pop_unqual && !pipeline_stall;
// MSHR pending size
assign mshr_pending_size_n = mshr_pending_size +
((creq_pop && !creq_commit) ? 1 : ((creq_commit && !creq_pop) ? -1 : 0));
always @(posedge clk) begin
if (reset) begin
mshr_pending_size <= 0;
mshr_going_full <= 0;
end else begin
mshr_pending_size <= mshr_pending_size +
((creq_pop && !creq_commit) ? 1 : ((creq_commit && !creq_pop) ? -1 : 0));
end
mshr_pending_size <= mshr_pending_size_n;
mshr_going_full <= (mshr_pending_size_n == MSHR_SIZE);
end
end
assign is_mshr_st0 = mshr_pop_unqual;
@@ -736,7 +739,7 @@ end
.enqueue_byteen_st3 (req_byteen_st3),
.enqueue_is_snp_st3 (is_snp_st3),
.enqueue_snp_inv_st3(snp_inv_st3),
.enqueue_mshr_st3 (is_mshr_st3),
.enqueue_is_mshr_st3(is_mshr_st3),
.enqueue_ready_st3 (mshr_init_ready_state_st3),
.enqueue_full (mshr_full),

65
hw/rtl/cache/VX_cache.v vendored
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@@ -39,11 +39,11 @@ module VX_cache #(
// Enable cache flush
parameter FLUSH_ENABLE = 1,
// size of tag id in core request tag
parameter CORE_TAG_ID_BITS = $clog2(MSHR_SIZE),
// core request tag size
parameter CORE_TAG_WIDTH = CORE_TAG_ID_BITS,
parameter CORE_TAG_WIDTH = $clog2(MSHR_SIZE),
// size of tag id in core request tag
parameter CORE_TAG_ID_BITS = 0,
// dram request tag size
parameter DRAM_TAG_WIDTH = (32 - $clog2(BANK_LINE_SIZE)),
@@ -63,13 +63,13 @@ module VX_cache #(
input wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr,
input wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_req_data,
input wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
output wire core_req_ready,
output wire [`CORE_REQ_TAG_COUNT-1:0] core_req_ready,
// Core response
output wire [NUM_REQS-1:0] core_rsp_valid,
output wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data,
output wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag,
input wire core_rsp_ready,
input wire [`CORE_REQ_TAG_COUNT-1:0] core_rsp_ready,
// DRAM request
output wire dram_req_valid,
@@ -139,9 +139,10 @@ module VX_cache #(
VX_cache_core_req_bank_sel #(
.BANK_LINE_SIZE (BANK_LINE_SIZE),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE (WORD_SIZE),
.NUM_REQS (NUM_REQS)
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE (WORD_SIZE),
.NUM_REQS (NUM_REQS),
.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS)
) cache_core_req_bank_sel (
.core_req_valid (core_req_valid),
.core_req_addr (core_req_addr),
@@ -197,7 +198,7 @@ module VX_cache #(
wire curr_bank_miss;
// Core Req
assign curr_bank_core_req_valid = (per_bank_valid[i] & {NUM_REQS{core_req_ready}});
assign curr_bank_core_req_valid = per_bank_valid[i];
assign curr_bank_core_req_addr = core_req_addr;
assign curr_bank_core_req_rw = core_req_rw;
assign curr_bank_core_req_byteen = core_req_byteen;
@@ -355,18 +356,18 @@ module VX_cache #(
end
VX_stream_arbiter #(
.NUM_REQS(NUM_BANKS),
.DATAW(`DRAM_ADDR_WIDTH + 1 + BANK_LINE_SIZE + `BANK_LINE_WIDTH),
.BUFFERED(NUM_BANKS >= 4)
.NUM_REQS (NUM_BANKS),
.DATAW (`DRAM_ADDR_WIDTH + 1 + BANK_LINE_SIZE + `BANK_LINE_WIDTH),
.OUT_BUFFER (NUM_BANKS >= 4)
) dram_req_arb (
.clk (clk),
.reset (reset),
.valid_in (per_bank_dram_req_valid),
.data_in (data_in),
.ready_in (per_bank_dram_req_ready),
.valid_out (dram_req_valid),
.data_out ({dram_req_addr, dram_req_rw, dram_req_byteen, dram_req_data}),
.ready_out (dram_req_ready)
.clk (clk),
.reset (reset),
.valid_in (per_bank_dram_req_valid),
.data_in (data_in),
.ready_in (per_bank_dram_req_ready),
.valid_out (dram_req_valid),
.data_out ({dram_req_addr, dram_req_rw, dram_req_byteen, dram_req_data}),
.ready_out (dram_req_ready)
);
end else begin
`UNUSED_VAR (per_bank_dram_req_valid)
@@ -385,18 +386,18 @@ module VX_cache #(
if (FLUSH_ENABLE) begin
VX_stream_arbiter #(
.NUM_REQS(NUM_BANKS),
.DATAW(SNP_TAG_WIDTH),
.BUFFERED(NUM_BANKS >= 4)
.NUM_REQS (NUM_BANKS),
.DATAW (SNP_TAG_WIDTH),
.OUT_BUFFER (NUM_BANKS >= 4)
) snp_rsp_arb (
.clk (clk),
.reset (reset),
.valid_in (per_bank_snp_rsp_valid),
.data_in (per_bank_snp_rsp_tag),
.ready_in (per_bank_snp_rsp_ready),
.valid_out (snp_rsp_valid),
.data_out (snp_rsp_tag),
.ready_out (snp_rsp_ready)
.clk (clk),
.reset (reset),
.valid_in (per_bank_snp_rsp_valid),
.data_in (per_bank_snp_rsp_tag),
.ready_in (per_bank_snp_rsp_ready),
.valid_out (snp_rsp_valid),
.data_out (snp_rsp_tag),
.ready_out (snp_rsp_ready)
);
end else begin
`UNUSED_VAR (per_bank_snp_rsp_valid)

2
hw/rtl/cache/VX_cache_config.vh vendored
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@@ -15,7 +15,7 @@
`define REQ_INST_META_WIDTH (`REQ_TAG_WIDTH + 1 + WORD_SIZE + `REQS_BITS)
// data metadata word_sel is_snp snp_inv
`define MSHR_METADATA_WIDTH (`WORD_WIDTH + `REQ_INST_META_WIDTH + `UP(`WORD_SELECT_WIDTH) + 1 + 1)
`define MSHR_DATA_WIDTH (`WORD_WIDTH + `REQ_INST_META_WIDTH + `UP(`WORD_SELECT_WIDTH) + 1 + 1)
`define BANK_BITS `LOG2UP(NUM_BANKS)

73
hw/rtl/cache/VX_cache_core_req_bank_sel.v vendored
View File

@@ -8,53 +8,72 @@ module VX_cache_core_req_bank_sel #(
// Number of banks
parameter NUM_BANKS = 1,
// Number of Word requests per cycle
parameter NUM_REQS = 1
parameter NUM_REQS = 1,
// size of tag id in core request tag
parameter CORE_TAG_ID_BITS = 1
) (
input wire [NUM_REQS-1:0] core_req_valid,
input wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr,
output wire core_req_ready,
output wire [`CORE_REQ_TAG_COUNT-1:0] core_req_ready,
output wire [NUM_BANKS-1:0][NUM_REQS-1:0] per_bank_valid,
input wire [NUM_BANKS-1:0] per_bank_ready
);
if (NUM_BANKS > 1) begin
reg [NUM_BANKS-1:0][NUM_REQS-1:0] per_bank_valid_r;
reg [NUM_BANKS-1:0] per_bank_ready_ignore;
reg [NUM_BANKS-1:0] per_bank_ready_other;
always @(*) begin
per_bank_valid_r = 0;
per_bank_ready_other = {NUM_BANKS{1'b1}};
per_bank_ready_ignore = {NUM_BANKS{1'b1}};
for (integer i = 0; i < NUM_BANKS; i++) begin
for (integer j = 0; j < NUM_BANKS; j++) begin
if (i != j) begin
per_bank_ready_other[i] &= (per_bank_ready[j] | per_bank_ready_ignore[j]);
end
end
end
reg [NUM_BANKS-1:0][NUM_REQS-1:0] per_bank_valid_r;
always @(*) begin
per_bank_valid_r = 0;
for (integer i = 0; i < NUM_REQS; i++) begin
per_bank_valid_r[core_req_addr[i][`BANK_SELECT_ADDR_RNG]][i] = core_req_valid[i];
per_bank_ready_ignore[core_req_addr[i][`BANK_SELECT_ADDR_RNG]] = 1'b0;
end
end
for (genvar i = 0; i < NUM_BANKS; i++) begin
for (genvar j = 0; j < NUM_REQS; j++) begin
assign per_bank_valid[i][j] = per_bank_valid_r[i][j] & per_bank_ready_other[i];
end
end
if (CORE_TAG_ID_BITS != 0) begin
reg [NUM_BANKS-1:0] per_bank_ready_other, per_bank_ready_ignore;
always @(*) begin
per_bank_ready_other = {NUM_BANKS{1'b1}};
per_bank_ready_ignore = {NUM_BANKS{1'b1}};
assign core_req_ready = & (per_bank_ready | per_bank_ready_ignore);
for (integer i = 0; i < NUM_REQS; i++) begin
per_bank_ready_ignore[core_req_addr[i][`BANK_SELECT_ADDR_RNG]] = 1'b0;
end
for (integer i = 0; i < NUM_BANKS; i++) begin
for (integer j = 0; j < NUM_BANKS; j++) begin
if (i != j) begin
per_bank_ready_other[i] &= (per_bank_ready[j] | per_bank_ready_ignore[j]);
end
end
end
end
for (genvar i = 0; i < NUM_BANKS; i++) begin
for (genvar j = 0; j < NUM_REQS; j++) begin
assign per_bank_valid[i][j] = per_bank_valid_r[i][j] && per_bank_ready_other[i];
end
end
assign core_req_ready[0] = & (per_bank_ready | per_bank_ready_ignore);
end else begin
assign per_bank_valid = per_bank_valid_r;
for (genvar i = 0; i < NUM_REQS; i++) begin
assign core_req_ready[i] = per_bank_ready[core_req_addr[i][`BANK_SELECT_ADDR_RNG]];
end
end
end else begin
`UNUSED_VAR (core_req_addr)
assign per_bank_valid = core_req_valid;
assign core_req_ready = per_bank_ready;
assign core_req_ready[0] = per_bank_ready;
end

77
hw/rtl/cache/VX_cache_core_rsp_merge.v vendored
View File

@@ -26,18 +26,20 @@ module VX_cache_core_rsp_merge #(
output wire [NUM_REQS-1:0] core_rsp_valid,
output wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag,
output wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data,
input wire core_rsp_ready
input wire [`CORE_REQ_TAG_COUNT-1:0] core_rsp_ready
);
if (NUM_BANKS > 1) begin
reg [NUM_REQS-1:0] core_rsp_valid_unqual;
reg [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag_unqual;
reg [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data_unqual;
reg [NUM_BANKS-1:0] core_rsp_bank_select;
if (CORE_TAG_ID_BITS != 0) begin
reg [CORE_TAG_WIDTH-1:0] core_rsp_tag_unqual;
reg [CORE_TAG_ID_BITS-1:0] sel_tag_id;
wire stall = ~core_rsp_ready && (| core_rsp_valid);
always @(*) begin
core_rsp_valid_unqual = 0;
@@ -60,13 +62,32 @@ module VX_cache_core_rsp_merge #(
&& (per_bank_core_rsp_tag[i][CORE_TAG_ID_BITS-1:0] == sel_tag_id)) begin
core_rsp_valid_unqual[per_bank_core_rsp_tid[i]] = 1;
core_rsp_data_unqual[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i];
core_rsp_bank_select[i] = 1;
core_rsp_bank_select[i] = ~stall;
end
end
end
VX_generic_register #(
.N(NUM_REQS + (NUM_REQS *`WORD_WIDTH) + CORE_TAG_WIDTH),
.R(NUM_REQS)
) pipe_reg (
.clk (clk),
.reset (reset),
.stall (stall),
.flush (1'b0),
.data_in ({core_rsp_valid_unqual, core_rsp_data_unqual, core_rsp_tag_unqual}),
.data_out ({core_rsp_valid, core_rsp_data, core_rsp_tag})
);
for (genvar i = 0; i < NUM_BANKS; i++) begin
assign per_bank_core_rsp_ready[i] = core_rsp_bank_select[i];
end
end else begin
reg [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag_unqual;
reg [NUM_REQS-1:0] stall;
always @(*) begin
core_rsp_valid_unqual = 0;
core_rsp_tag_unqual = 'x;
@@ -79,29 +100,32 @@ module VX_cache_core_rsp_merge #(
core_rsp_valid_unqual[per_bank_core_rsp_tid[i]] = 1;
core_rsp_tag_unqual[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_tag[i];
core_rsp_data_unqual[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i];
core_rsp_bank_select[i] = 1;
core_rsp_bank_select[i] = ~stall[per_bank_core_rsp_tid[i]];
end
end
end
end
for (genvar i = 0; i < NUM_REQS; i++) begin
wire stall = ~core_rsp_ready && (| core_rsp_valid);
assign stall[i] = ~core_rsp_ready[i] && core_rsp_valid[i];
VX_generic_register #(
.N(NUM_REQS + (NUM_REQS *`WORD_WIDTH) + (`CORE_REQ_TAG_COUNT * CORE_TAG_WIDTH)),
.R(NUM_REQS)
) pipe_reg (
.clk (clk),
.reset (reset),
.stall (stall),
.flush (1'b0),
.data_in ({core_rsp_valid_unqual, core_rsp_data_unqual, core_rsp_tag_unqual}),
.data_out ({core_rsp_valid, core_rsp_data, core_rsp_tag})
);
VX_generic_register #(
.N(1 + `WORD_WIDTH + CORE_TAG_WIDTH),
.R(1)
) pipe_reg (
.clk (clk),
.reset (reset),
.stall (stall[i]),
.flush (1'b0),
.data_in ({core_rsp_valid_unqual[i], core_rsp_data_unqual[i], core_rsp_tag_unqual[i]}),
.data_out ({core_rsp_valid[i], core_rsp_data[i], core_rsp_tag[i]})
);
end
for (genvar i = 0; i < NUM_BANKS; i++) begin
assign per_bank_core_rsp_ready[i] = core_rsp_bank_select[i];
end
for (genvar i = 0; i < NUM_BANKS; i++) begin
assign per_bank_core_rsp_ready[i] = core_rsp_bank_select[i] && ~stall;
end
end else begin
@@ -116,14 +140,19 @@ module VX_cache_core_rsp_merge #(
reg [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data_unqual;
if (CORE_TAG_ID_BITS != 0) begin
always @(*) begin
core_rsp_valid_unqual = 0;
core_rsp_tag_unqual = per_bank_core_rsp_tag[0];
core_rsp_data_unqual = 'x;
core_rsp_valid_unqual[per_bank_core_rsp_tid[0]] = per_bank_core_rsp_valid;
core_rsp_data_unqual[per_bank_core_rsp_tid[0]] = per_bank_core_rsp_data[0];
end
end
assign per_bank_core_rsp_ready[0] = core_rsp_ready;
end else begin
always @(*) begin
core_rsp_valid_unqual = 0;
core_rsp_tag_unqual = 'x;
@@ -131,14 +160,16 @@ module VX_cache_core_rsp_merge #(
core_rsp_valid_unqual[per_bank_core_rsp_tid[0]] = per_bank_core_rsp_valid;
core_rsp_tag_unqual[per_bank_core_rsp_tid[0]] = per_bank_core_rsp_tag[0];
core_rsp_data_unqual[per_bank_core_rsp_tid[0]] = per_bank_core_rsp_data[0];
end
end
assign per_bank_core_rsp_ready[0] = core_rsp_ready[per_bank_core_rsp_tid[0]];
end
assign core_rsp_valid = core_rsp_valid_unqual;
assign core_rsp_tag = core_rsp_tag_unqual;
assign core_rsp_data = core_rsp_data_unqual;
assign per_bank_core_rsp_ready[0] = core_rsp_ready;
end else begin
`UNUSED_VAR(per_bank_core_rsp_tid)

21
hw/rtl/cache/VX_miss_resrv.v vendored
View File

@@ -48,7 +48,7 @@ module VX_miss_resrv #(
input wire[WORD_SIZE-1:0] enqueue_byteen_st3,
input wire enqueue_is_snp_st3,
input wire enqueue_snp_inv_st3,
input wire enqueue_mshr_st3,
input wire enqueue_is_mshr_st3,
input wire enqueue_ready_st3,
output wire enqueue_full,
@@ -71,7 +71,7 @@ module VX_miss_resrv #(
output wire dequeue_snp_inv_st0,
input wire dequeue_st3
);
wire [`MSHR_METADATA_WIDTH-1:0] metadata_table;
wire [`MSHR_DATA_WIDTH-1:0] data_table;
reg [`LINE_ADDR_WIDTH-1:0] addr_table [MSHR_SIZE-1:0];
@@ -91,7 +91,7 @@ module VX_miss_resrv #(
assign pending_hazard_st0 = (| valid_address_match);
wire dequeue_ready = valid_table[schedule_ptr] && ready_table[schedule_ptr];
wire dequeue_ready = ready_table[schedule_ptr];
assign dequeue_valid_st0 = dequeue_ready;
assign dequeue_addr_st0 = addr_table[schedule_ptr];
@@ -102,9 +102,9 @@ module VX_miss_resrv #(
dequeue_byteen_st0,
dequeue_wsel_st0,
dequeue_is_snp_st0,
dequeue_snp_inv_st0} = metadata_table;
dequeue_snp_inv_st0} = data_table;
wire mshr_push = enqueue_st3 && !enqueue_mshr_st3;
wire mshr_push = enqueue_st3 && !enqueue_is_mshr_st3;
wire [`LOG2UP(MSHR_SIZE)-1:0] head_ptr_n = head_ptr + $bits(head_ptr)'(1);
@@ -124,7 +124,7 @@ module VX_miss_resrv #(
if (enqueue_st3) begin
assert(!enqueue_full);
if (enqueue_mshr_st3) begin
if (enqueue_is_mshr_st3) begin
// returning missed msrq entry, restore schedule
valid_table[restore_ptr] <= 1;
ready_table[restore_ptr] <= enqueue_ready_st3;
@@ -146,19 +146,20 @@ module VX_miss_resrv #(
if (schedule_st0) begin
assert(dequeue_valid_st0);
valid_table[schedule_ptr] <= 0;
ready_table[schedule_ptr] <= 0;
schedule_ptr <= schedule_ptr + $bits(schedule_ptr)'(1);
end
end
end
always @(posedge clk) begin
if (enqueue_st3 && !enqueue_mshr_st3) begin
if (enqueue_st3 && !enqueue_is_mshr_st3) begin
addr_table[tail_ptr] <= enqueue_addr_st3;
end
end
VX_dp_ram #(
.DATAW(`MSHR_METADATA_WIDTH),
.DATAW(`MSHR_DATA_WIDTH),
.SIZE(MSHR_SIZE),
.BYTEENW(1),
.BUFFERED(0),
@@ -171,7 +172,7 @@ module VX_miss_resrv #(
.byteen(1'b1),
.rden(1'b1),
.din({enqueue_data_st3, enqueue_tid_st3, enqueue_tag_st3, enqueue_rw_st3, enqueue_byteen_st3, enqueue_wsel_st3, enqueue_is_snp_st3, enqueue_snp_inv_st3}),
.dout(metadata_table)
.dout(data_table)
);
`ifdef DBG_PRINT_CACHE_MSHR
@@ -180,7 +181,7 @@ module VX_miss_resrv #(
if (schedule_st0)
$display("%t: cache%0d:%0d msrq-schedule: addr%0d=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, schedule_ptr, `LINE_TO_BYTE_ADDR(dequeue_addr_st0, BANK_ID), debug_wid_st0, debug_pc_st0);
if (enqueue_st3) begin
if (enqueue_mshr_st3)
if (enqueue_is_mshr_st3)
$display("%t: cache%0d:%0d msrq-restore: addr%0d=%0h, ready=%b", $time, CACHE_ID, BANK_ID, restore_ptr, `LINE_TO_BYTE_ADDR(enqueue_addr_st3, BANK_ID), enqueue_ready_st3);
else
$display("%t: cache%0d:%0d msrq-enq: addr%0d=%0h, ready=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, tail_ptr, `LINE_TO_BYTE_ADDR(enqueue_addr_st3, BANK_ID), enqueue_ready_st3, debug_wid_st3, debug_pc_st3);

33
hw/rtl/cache/VX_snp_forwarder.v vendored
View File

@@ -44,26 +44,6 @@ module VX_snp_forwarder #(
if (NUM_REQS > 1) begin
// Inputs buffering
wire [NUM_REQS-1:0] snp_fwdin_valid_qual;
wire [NUM_REQS-1:0][TAG_OUT_WIDTH-1:0] snp_fwdin_tag_qual;
wire [NUM_REQS-1:0] snp_fwdin_ready_qual;
for (genvar i = 0; i < NUM_REQS; ++i) begin
VX_skid_buffer #(
.DATAW (TAG_OUT_WIDTH),
.PASSTHRU (NUM_REQS < 4)
) snp_fwdin_buffer (
.clk (clk),
.reset (reset),
.valid_in (snp_fwdin_valid[i]),
.data_in (snp_fwdin_tag[i]),
.ready_in (snp_fwdin_ready[i]),
.valid_out (snp_fwdin_valid_qual[i]),
.data_out (snp_fwdin_tag_qual[i]),
.ready_out (snp_fwdin_ready_qual[i])
);
end
reg [REQ_QUAL_BITS:0] pending_cntrs [SREQ_SIZE-1:0];
wire [TAG_OUT_WIDTH-1:0] sfq_write_addr, sfq_read_addr;
@@ -181,15 +161,16 @@ module VX_snp_forwarder #(
assign snp_req_ready = fwdout_ready && !sfq_full && !dispatch_hold;
VX_stream_arbiter #(
.NUM_REQS(NUM_REQS),
.DATAW(TAG_OUT_WIDTH),
.BUFFERED(NUM_REQS >= 4)
.NUM_REQS (NUM_REQS),
.DATAW (TAG_OUT_WIDTH),
.IN_BUFFER (NUM_REQS >= 4),
.OUT_BUFFER (NUM_REQS >= 4)
) snp_fwdin_arb (
.clk (clk),
.reset (reset),
.valid_in (snp_fwdin_valid_qual),
.data_in (snp_fwdin_tag_qual),
.ready_in (snp_fwdin_ready_qual),
.valid_in (snp_fwdin_valid),
.data_in (snp_fwdin_tag),
.ready_in (snp_fwdin_ready),
.valid_out (fwdin_valid),
.data_out (fwdin_tag),
.ready_out (fwdin_ready)