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cache req datapath optimizations

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This commit is contained in:
Blaise Tine
2020-12-08 02:58:08 -08:00
parent 268ad15098
commit d5fa82f5e4
17 changed files with 393 additions and 410 deletions
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91
hw/rtl/VX_cluster.v
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@@ -204,17 +204,17 @@ module VX_cluster #(
.req_tag_out (io_req_tag),
.req_ready_out (io_req_ready),
// input responses
.rsp_valid_in (per_core_io_rsp_valid),
.rsp_data_in (per_core_io_rsp_data),
.rsp_tag_in (per_core_io_rsp_tag),
.rsp_ready_in (per_core_io_rsp_ready),
// output response
.rsp_valid_out (io_rsp_valid),
.rsp_tag_out (io_rsp_tag),
.rsp_data_out (io_rsp_data),
.rsp_ready_out (io_rsp_ready)
// input response
.rsp_valid_in (io_rsp_valid),
.rsp_tag_in (io_rsp_tag),
.rsp_data_in (io_rsp_data),
.rsp_ready_in (io_rsp_ready),
// output responses
.rsp_valid_out (per_core_io_rsp_valid),
.rsp_data_out (per_core_io_rsp_data),
.rsp_tag_out (per_core_io_rsp_tag),
.rsp_ready_out (per_core_io_rsp_ready)
);
VX_csr_io_arb #(
@@ -298,35 +298,30 @@ module VX_cluster #(
if (`L2_ENABLE) begin
wire [`NUM_CORES-1:0] core_dram_rsp_valid;
wire [`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] core_dram_rsp_data;
wire [`NUM_CORES-1:0][`XDRAM_TAG_WIDTH-1:0] core_dram_rsp_tag;
wire core_dram_rsp_ready;
wire [`NUM_CORES-1:0] per_core_dram_req_valid_qual;
wire [`NUM_CORES-1:0] per_core_dram_req_rw_qual;
wire [`NUM_CORES-1:0][`DDRAM_BYTEEN_WIDTH-1:0] per_core_dram_req_byteen_qual;
wire [`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] per_core_dram_req_addr_qual;
wire [`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] per_core_dram_req_data_qual;
wire [`NUM_CORES-1:0][`XDRAM_TAG_WIDTH-1:0] per_core_dram_req_tag_qual;
wire [`NUM_CORES-1:0] per_core_dram_req_ready_qual;
reg [`NUM_CORES-1:0] core_dram_rsp_ready_other;
always @(*) begin
core_dram_rsp_ready_other = {`NUM_CORES{1'b1}};
for (integer i = 0; i < `NUM_CORES; i++) begin
for (integer j = 0; j < `NUM_CORES; j++) begin
if (i != j) begin
core_dram_rsp_ready_other[i] &= (per_core_dram_rsp_ready [j] | !core_dram_rsp_valid [j]);
end
end
end
for (genvar i = 0; i < `NUM_CORES; i++) begin
VX_skid_buffer #(
.DATAW (1 + `DDRAM_BYTEEN_WIDTH + `DDRAM_ADDR_WIDTH + `DDRAM_LINE_WIDTH + `XDRAM_TAG_WIDTH),
.PASSTHRU (`NUM_CORES < 4)
) dram_req_buffer (
.clk (clk),
.reset (reset),
.valid_in (per_core_dram_req_valid[i]),
.data_in ({per_core_dram_req_rw[i], per_core_dram_req_byteen[i], per_core_dram_req_addr[i], per_core_dram_req_data[i], per_core_dram_req_tag[i]}),
.ready_in (per_core_dram_req_ready[i]),
.valid_out (per_core_dram_req_valid_qual[i]),
.data_out ({per_core_dram_req_rw_qual[i], per_core_dram_req_byteen_qual[i], per_core_dram_req_addr_qual[i], per_core_dram_req_data_qual[i], per_core_dram_req_tag_qual[i]}),
.ready_out (per_core_dram_req_ready_qual[i])
);
end
for (genvar i = 0; i < `NUM_CORES; i++) begin
assign per_core_dram_rsp_valid [i] = core_dram_rsp_valid[i] & core_dram_rsp_ready_other [i];
assign per_core_dram_rsp_data [i] = core_dram_rsp_data[i];
assign per_core_dram_rsp_tag [i] = core_dram_rsp_tag[i];
end
assign core_dram_rsp_ready = & (per_core_dram_rsp_ready | ~core_dram_rsp_valid);
wire core_dram_req_ready;
for (genvar i = 0; i < `NUM_CORES; i++) begin
assign per_core_dram_req_ready[i] = core_dram_req_ready;
end
VX_cache #(
.CACHE_ID (`L2CACHE_ID),
.CACHE_SIZE (`L2CACHE_SIZE),
@@ -355,19 +350,19 @@ module VX_cluster #(
.reset (reset),
// Core request
.core_req_valid (per_core_dram_req_valid),
.core_req_rw (per_core_dram_req_rw),
.core_req_byteen (per_core_dram_req_byteen),
.core_req_addr (per_core_dram_req_addr),
.core_req_data (per_core_dram_req_data),
.core_req_tag (per_core_dram_req_tag),
.core_req_ready (core_dram_req_ready),
.core_req_valid (per_core_dram_req_valid_qual),
.core_req_rw (per_core_dram_req_rw_qual),
.core_req_byteen (per_core_dram_req_byteen_qual),
.core_req_addr (per_core_dram_req_addr_qual),
.core_req_data (per_core_dram_req_data_qual),
.core_req_tag (per_core_dram_req_tag_qual),
.core_req_ready (per_core_dram_req_ready_qual),
// Core response
.core_rsp_valid (core_dram_rsp_valid),
.core_rsp_data (core_dram_rsp_data),
.core_rsp_tag (core_dram_rsp_tag),
.core_rsp_ready (core_dram_rsp_ready),
.core_rsp_valid (per_core_dram_rsp_valid),
.core_rsp_data (per_core_dram_rsp_data),
.core_rsp_tag (per_core_dram_rsp_tag),
.core_rsp_ready (per_core_dram_rsp_ready),
// DRAM request
.dram_req_valid (dram_req_valid),