diff --git a/ci/regression.sh b/ci/regression.sh index cc5c8faa..8adb5427 100755 --- a/ci/regression.sh +++ b/ci/regression.sh @@ -33,5 +33,14 @@ CONFIGS=-DSM_ENABLE=0 make -C hw/simulate # using FPNEW core FPU_CORE=FPU_FPNEW ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=demo -# test 128-bit DRAM bus -CONFIGS=-DPLATFORM_PARAM_LOCAL_MEMORY_DATA_SIZE_BITS=4 ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo \ No newline at end of file +# test 128-bit MEM block +CONFIGS=-DMEM_BLOCK_SIZE=16 ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo + +# test 128-bit DRAM block +CONFIGS="-DPLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH=128 -DPLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH=28" ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo + +# test 128-bit MEM and DRAM block +CONFIGS="-DMEM_BLOCK_SIZE=16 -DPLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH=128 -DPLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH=28" ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo + +# test 27-bit DRAM address +CONFIGS=-DPLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH=27 ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo \ No newline at end of file diff --git a/driver/opae/vlsim/vortex_afu_shim.sv b/driver/opae/vlsim/vortex_afu_shim.sv index f299aa79..ed7537c5 100644 --- a/driver/opae/vlsim/vortex_afu_shim.sv +++ b/driver/opae/vlsim/vortex_afu_shim.sv @@ -6,9 +6,7 @@ /* verilator lint_off IMPORTSTAR */ import ccip_if_pkg::*; import local_mem_cfg_pkg::*; -/* verilator lint_on IMPORTSTAR */ - -`define MEM_BLOCK_SIZE LOCAL_MEM_DATA_N_BYTES +/* verilator lint_on IMPORTSTAR */ `include "VX_define.vh" diff --git a/hw/rtl/VX_platform.vh b/hw/rtl/VX_platform.vh index 312d3d58..83eb0891 100644 --- a/hw/rtl/VX_platform.vh +++ b/hw/rtl/VX_platform.vh @@ -70,6 +70,8 @@ `define LOG2UP(x) (((x) > 1) ? $clog2(x) : 1) `define ISPOW2(x) (((x) != 0) && (0 == ((x) & ((x) - 1)))) +`define ABS(x) (($signed(x) < 0) ? (-$signed(x)) : x); + `define MIN(x, y) ((x < y) ? (x) : (y)) `define MAX(x, y) ((x > y) ? (x) : (y)) diff --git a/hw/rtl/afu/VX_avs_wrapper.v b/hw/rtl/afu/VX_avs_wrapper.v index 361bd2fa..ff7d1dd1 100644 --- a/hw/rtl/afu/VX_avs_wrapper.v +++ b/hw/rtl/afu/VX_avs_wrapper.v @@ -1,49 +1,49 @@ `include "VX_define.vh" module VX_avs_wrapper #( - parameter AVS_DATAW = 1, - parameter AVS_ADDRW = 1, - parameter AVS_BURSTW = 1, - parameter AVS_BANKS = 1, - parameter REQ_TAGW = 1, - parameter RD_QUEUE_SIZE = 1, + parameter AVS_DATA_WIDTH = 1, + parameter AVS_ADDR_WIDTH = 1, + parameter AVS_BURST_WIDTH = 1, + parameter AVS_BANKS = 1, + parameter REQ_TAG_WIDTH = 1, + parameter RD_QUEUE_SIZE = 1, - parameter AVS_BYTEENW = (AVS_DATAW / 8), - parameter RD_QUEUE_ADDRW= $clog2(RD_QUEUE_SIZE+1), - parameter AVS_BANKS_BITS= $clog2(AVS_BANKS) + parameter AVS_BYTEENW = (AVS_DATA_WIDTH / 8), + parameter RD_QUEUE_ADDR_WIDTH = $clog2(RD_QUEUE_SIZE+1), + parameter AVS_BANKS_BITS = $clog2(AVS_BANKS) ) ( - input wire clk, - input wire reset, + input wire clk, + input wire reset, // Memory request - input wire mem_req_valid, - input wire mem_req_rw, - input wire [AVS_BYTEENW-1:0] mem_req_byteen, - input wire [AVS_ADDRW-1:0] mem_req_addr, - input wire [AVS_DATAW-1:0] mem_req_data, - input wire [REQ_TAGW-1:0] mem_req_tag, - output wire mem_req_ready, + input wire mem_req_valid, + input wire mem_req_rw, + input wire [AVS_BYTEENW-1:0] mem_req_byteen, + input wire [AVS_ADDR_WIDTH-1:0] mem_req_addr, + input wire [AVS_DATA_WIDTH-1:0] mem_req_data, + input wire [REQ_TAG_WIDTH-1:0] mem_req_tag, + output wire mem_req_ready, // Memory response - output wire mem_rsp_valid, - output wire [AVS_DATAW-1:0] mem_rsp_data, - output wire [REQ_TAGW-1:0] mem_rsp_tag, - input wire mem_rsp_ready, + output wire mem_rsp_valid, + output wire [AVS_DATA_WIDTH-1:0] mem_rsp_data, + output wire [REQ_TAG_WIDTH-1:0] mem_rsp_tag, + input wire mem_rsp_ready, // AVS bus - output wire [AVS_DATAW-1:0] avs_writedata, - input wire [AVS_DATAW-1:0] avs_readdata, - output wire [AVS_ADDRW-1:0] avs_address, - input wire avs_waitrequest, - output wire avs_write, - output wire avs_read, - output wire [AVS_BYTEENW-1:0] avs_byteenable, - output wire [AVS_BURSTW-1:0] avs_burstcount, - input avs_readdatavalid, - output wire [AVS_BANKS_BITS-1:0] avs_bankselect + output wire [AVS_DATA_WIDTH-1:0] avs_writedata, + input wire [AVS_DATA_WIDTH-1:0] avs_readdata, + output wire [AVS_ADDR_WIDTH-1:0] avs_address, + input wire avs_waitrequest, + output wire avs_write, + output wire avs_read, + output wire [AVS_BYTEENW-1:0] avs_byteenable, + output wire [AVS_BURST_WIDTH-1:0] avs_burstcount, + input avs_readdatavalid, + output wire [AVS_BANKS_BITS-1:0] avs_bankselect ); reg [AVS_BANKS_BITS-1:0] avs_bankselect_r; - reg [AVS_BURSTW-1:0] avs_burstcount_r; + reg [AVS_BURST_WIDTH-1:0] avs_burstcount_r; wire avs_reqq_push = mem_req_valid && mem_req_ready && !mem_req_rw; wire avs_reqq_pop = mem_rsp_valid && mem_rsp_ready; @@ -53,7 +53,7 @@ module VX_avs_wrapper #( wire avs_rspq_empty; wire rsp_queue_going_full; - wire [RD_QUEUE_ADDRW-1:0] rsp_queue_size; + wire [RD_QUEUE_ADDR_WIDTH-1:0] rsp_queue_size; VX_pending_size #( .SIZE (RD_QUEUE_SIZE) ) pending_size ( @@ -73,7 +73,7 @@ module VX_avs_wrapper #( end VX_fifo_queue #( - .DATAW (REQ_TAGW), + .DATAW (REQ_TAG_WIDTH), .SIZE (RD_QUEUE_SIZE) ) rd_req_queue ( .clk (clk), @@ -90,7 +90,7 @@ module VX_avs_wrapper #( ); VX_fifo_queue #( - .DATAW (AVS_DATAW), + .DATAW (AVS_DATA_WIDTH), .SIZE (RD_QUEUE_SIZE) ) rd_rsp_queue ( .clk (clk), diff --git a/hw/rtl/afu/VX_cci_to_mem.v b/hw/rtl/afu/VX_to_mem.v similarity index 100% rename from hw/rtl/afu/VX_cci_to_mem.v rename to hw/rtl/afu/VX_to_mem.v diff --git a/hw/rtl/afu/vortex_afu.sv b/hw/rtl/afu/vortex_afu.sv index 78269ee7..392c775d 100644 --- a/hw/rtl/afu/vortex_afu.sv +++ b/hw/rtl/afu/vortex_afu.sv @@ -44,16 +44,13 @@ localparam RESET_DELAY = 3; localparam LMEM_LINE_WIDTH = $bits(t_local_mem_data); localparam LMEM_ADDR_WIDTH = $bits(t_local_mem_addr); localparam LMEM_BURST_CTRW = $bits(t_local_mem_burst_cnt); -localparam LMEM_LINE_LW = $clog2(LMEM_LINE_WIDTH); localparam CCI_LINE_WIDTH = $bits(t_ccip_clData); +localparam CCI_LINE_SIZE = CCI_LINE_WIDTH / 8; localparam CCI_ADDR_WIDTH = 32 - $clog2(CCI_LINE_WIDTH / 8); -localparam VX_MEM_LINE_LW = $clog2(`VX_MEM_LINE_WIDTH); -localparam VX_MEM_LINE_IDX = (LMEM_LINE_LW - VX_MEM_LINE_LW); - localparam AVS_RD_QUEUE_SIZE = 16; -localparam AVS_REQ_TAGW = `VX_MEM_TAG_WIDTH + VX_MEM_LINE_IDX; +localparam AVS_REQ_TAGW = `MAX(`VX_MEM_TAG_WIDTH, `VX_MEM_TAG_WIDTH + ($clog2(LMEM_LINE_WIDTH) - $clog2(`VX_MEM_LINE_WIDTH))); localparam CCI_RD_WINDOW_SIZE = 8; localparam CCI_RD_QUEUE_SIZE = 2 * CCI_RD_WINDOW_SIZE; @@ -451,6 +448,137 @@ end // AVS Controller ///////////////////////////////////////////////////////////// +wire cci_mem_rd_req_valid; +wire cci_mem_wr_req_valid; +wire [CCI_ADDR_WIDTH-1:0] cci_mem_rd_req_addr; +wire [CCI_ADDR_WIDTH-1:0] cci_mem_wr_req_addr; +wire [CCI_RD_RQ_DATAW-1:0] cci_rdq_dout; +wire cci_mem_req_ready; + +wire cci_mem_req_valid; +wire cci_mem_req_rw; +wire [CCI_ADDR_WIDTH-1:0] cci_mem_req_addr; +wire cci_mem_req_tag = 1'b0; + +wire cci_mem_rsp_valid; +wire [CCI_LINE_WIDTH-1:0] cci_mem_rsp_data; +wire cci_mem_rsp_tag; +wire cci_mem_rsp_ready; + +`UNUSED_VAR (cci_mem_rsp_tag) + +assign cci_mem_req_rw = (CMD_MEM_WRITE == state); +assign cci_mem_req_valid = cci_mem_req_rw ? cci_mem_wr_req_valid : cci_mem_rd_req_valid; +assign cci_mem_req_addr = cci_mem_req_rw ? cci_mem_wr_req_addr : cci_mem_rd_req_addr; + +//-- + +wire cci_mem_req_arb_valid; +wire cci_mem_req_arb_rw; +t_local_mem_byte_mask cci_mem_req_arb_byteen; +t_local_mem_addr cci_mem_req_arb_addr; +t_local_mem_data cci_mem_req_arb_data; +wire [AVS_REQ_TAGW-1:0] cci_mem_req_arb_tag; +wire cci_mem_req_arb_ready; + +wire cci_mem_rsp_arb_valid; +t_local_mem_data cci_mem_rsp_arb_data; +wire [AVS_REQ_TAGW-1:0] cci_mem_rsp_arb_tag; +wire cci_mem_rsp_arb_ready; + +VX_to_mem #( + .SRC_DATA_WIDTH (CCI_LINE_WIDTH), + .DST_DATA_WIDTH (LMEM_LINE_WIDTH), + .SRC_ADDR_WIDTH (CCI_ADDR_WIDTH), + .DST_ADDR_WIDTH (LMEM_ADDR_WIDTH), + .SRC_TAG_WIDTH (1), + .DST_TAG_WIDTH (AVS_REQ_TAGW) +) cci_to_mem ( + .clk (clk), + .reset (reset), + + .mem_req_valid_in (cci_mem_req_valid), + .mem_req_addr_in (cci_mem_req_addr), + .mem_req_rw_in (cci_mem_req_rw), + .mem_req_byteen_in ({CCI_LINE_SIZE{1'b1}}), + .mem_req_data_in (cci_rdq_dout[CCI_RD_RQ_DATAW-1:CCI_RD_RQ_TAGW]), + .mem_req_tag_in (cci_mem_req_tag), + .mem_req_ready_in (cci_mem_req_ready), + + .mem_req_valid_out (cci_mem_req_arb_valid), + .mem_req_addr_out (cci_mem_req_arb_addr), + .mem_req_rw_out (cci_mem_req_arb_rw), + .mem_req_byteen_out (cci_mem_req_arb_byteen), + .mem_req_data_out (cci_mem_req_arb_data), + .mem_req_tag_out (cci_mem_req_arb_tag), + .mem_req_ready_out (cci_mem_req_arb_ready), + + .mem_rsp_valid_in (cci_mem_rsp_arb_valid), + .mem_rsp_data_in (cci_mem_rsp_arb_data), + .mem_rsp_tag_in (cci_mem_rsp_arb_tag), + .mem_rsp_ready_in (cci_mem_rsp_arb_ready), + + .mem_rsp_valid_out (cci_mem_rsp_valid), + .mem_rsp_data_out (cci_mem_rsp_data), + .mem_rsp_tag_out (cci_mem_rsp_tag), + .mem_rsp_ready_out (cci_mem_rsp_ready) +); + +//-- + +wire vx_mem_req_arb_valid; +wire vx_mem_req_arb_rw; +t_local_mem_byte_mask vx_mem_req_arb_byteen; +t_local_mem_addr vx_mem_req_arb_addr; +t_local_mem_data vx_mem_req_arb_data; +wire [AVS_REQ_TAGW-1:0] vx_mem_req_arb_tag; +wire vx_mem_req_arb_ready; + +wire vx_mem_rsp_arb_valid; +t_local_mem_data vx_mem_rsp_arb_data; +wire [AVS_REQ_TAGW-1:0] vx_mem_rsp_arb_tag; +wire vx_mem_rsp_arb_ready; + +VX_to_mem #( + .SRC_DATA_WIDTH (`VX_MEM_LINE_WIDTH), + .DST_DATA_WIDTH (LMEM_LINE_WIDTH), + .SRC_ADDR_WIDTH (`VX_MEM_ADDR_WIDTH), + .DST_ADDR_WIDTH (LMEM_ADDR_WIDTH), + .SRC_TAG_WIDTH (`VX_MEM_TAG_WIDTH), + .DST_TAG_WIDTH (AVS_REQ_TAGW) +) vx_to_mem ( + .clk (clk), + .reset (reset), + + .mem_req_valid_in (vx_mem_req_valid && vx_mem_en), + .mem_req_addr_in (vx_mem_req_addr), + .mem_req_rw_in (vx_mem_req_rw), + .mem_req_byteen_in (vx_mem_req_byteen), + .mem_req_data_in (vx_mem_req_data), + .mem_req_tag_in (vx_mem_req_tag), + .mem_req_ready_in (vx_mem_req_ready), + + .mem_req_valid_out (vx_mem_req_arb_valid), + .mem_req_addr_out (vx_mem_req_arb_addr), + .mem_req_rw_out (vx_mem_req_arb_rw), + .mem_req_byteen_out (vx_mem_req_arb_byteen), + .mem_req_data_out (vx_mem_req_arb_data), + .mem_req_tag_out (vx_mem_req_arb_tag), + .mem_req_ready_out (vx_mem_req_arb_ready), + + .mem_rsp_valid_in (vx_mem_rsp_arb_valid), + .mem_rsp_data_in (vx_mem_rsp_arb_data), + .mem_rsp_tag_in (vx_mem_rsp_arb_tag), + .mem_rsp_ready_in (vx_mem_rsp_arb_ready), + + .mem_rsp_valid_out (vx_mem_rsp_valid), + .mem_rsp_data_out (vx_mem_rsp_data), + .mem_rsp_tag_out (vx_mem_rsp_tag), + .mem_rsp_ready_out (vx_mem_rsp_ready) +); + +//-- + wire mem_req_valid; wire mem_req_rw; t_local_mem_byte_mask mem_req_byteen; @@ -464,104 +592,6 @@ t_local_mem_data mem_rsp_data; wire [AVS_REQ_TAGW:0] mem_rsp_tag; wire mem_rsp_ready; -wire cci_mem_req_tmp_valid; -wire cci_mem_req_tmp_rw; -t_local_mem_byte_mask cci_mem_req_tmp_byteen; -t_local_mem_addr cci_mem_req_tmp_addr; -t_local_mem_data cci_mem_req_tmp_data; -wire [AVS_REQ_TAGW-1:0] cci_mem_req_tmp_tag; -wire cci_mem_req_tmp_ready; - -wire cci_mem_rsp_tmp_valid; -t_local_mem_data cci_mem_rsp_tmp_data; -wire [AVS_REQ_TAGW-1:0] cci_mem_rsp_tmp_tag; -wire cci_mem_rsp_tmp_ready; - -wire vx_mem_req_valid_qual; -t_local_mem_addr vx_mem_req_addr_qual; -t_local_mem_byte_mask vx_mem_req_byteen_qual; -t_local_mem_data vx_mem_req_data_qual; -wire [AVS_REQ_TAGW-1:0] vx_mem_req_tag_qual; - -wire [(1 << VX_MEM_LINE_IDX)-1:0][`VX_MEM_LINE_WIDTH-1:0] vx_mem_rsp_data_unqual; -wire [AVS_REQ_TAGW-1:0] vx_mem_rsp_tag_unqual; - -wire cci_mem_rd_req_valid; -wire cci_mem_wr_req_valid; -wire [CCI_ADDR_WIDTH-1:0] cci_mem_rd_req_addr; -wire [CCI_ADDR_WIDTH-1:0] cci_mem_wr_req_addr; -wire [CCI_RD_RQ_DATAW-1:0] cci_rdq_dout; -wire cci_mem_req_ready; - -wire cci_mem_rsp_valid; -wire [CCI_LINE_WIDTH-1:0] cci_mem_rsp_data; -wire [AVS_REQ_TAGW-1:0] cci_mem_rsp_tag; -wire cci_mem_rsp_ready; - -//-- - -VX_cci_to_mem #( - .CCI_DATAW (CCI_LINE_WIDTH), - .CCI_ADDRW (CCI_ADDR_WIDTH), - .AVS_DATAW (LMEM_LINE_WIDTH), - .AVS_ADDRW (LMEM_ADDR_WIDTH), - .TAG_WIDTH (AVS_REQ_TAGW) -) cci_to_mem( - .clk (clk), - .reset (reset), - - .mem_req_valid_in ((CMD_MEM_WRITE == state) ? cci_mem_wr_req_valid : cci_mem_rd_req_valid), - .mem_req_addr_in ((CMD_MEM_WRITE == state) ? cci_mem_wr_req_addr : cci_mem_rd_req_addr), - .mem_req_rw_in ((CMD_MEM_WRITE == state)), - .mem_req_data_in (cci_rdq_dout[CCI_RD_RQ_DATAW-1:CCI_RD_RQ_TAGW]), - .mem_req_tag_in (AVS_REQ_TAGW'(0)), - .mem_req_ready_in (cci_mem_req_ready), - - .mem_req_valid_out (cci_mem_req_tmp_valid), - .mem_req_addr_out (cci_mem_req_tmp_addr), - .mem_req_rw_out (cci_mem_req_tmp_rw), - .mem_req_byteen_out(cci_mem_req_tmp_byteen), - .mem_req_data_out (cci_mem_req_tmp_data), - .mem_req_tag_out (cci_mem_req_tmp_tag), - .mem_req_ready_out (cci_mem_req_tmp_ready), - - .mem_rsp_valid_in (cci_mem_rsp_tmp_valid), - .mem_rsp_data_in (cci_mem_rsp_tmp_data), - .mem_rsp_tag_in (cci_mem_rsp_tmp_tag), - .mem_rsp_ready_in (cci_mem_rsp_tmp_ready), - - .mem_rsp_valid_out (cci_mem_rsp_valid), - .mem_rsp_data_out (cci_mem_rsp_data), - .mem_rsp_tag_out (cci_mem_rsp_tag), - .mem_rsp_ready_out (cci_mem_rsp_ready) -); - -`UNUSED_VAR (cci_mem_rsp_tag) - -//-- - -assign vx_mem_req_valid_qual = vx_mem_req_valid && vx_mem_en; - -assign vx_mem_req_addr_qual = vx_mem_req_addr[`VX_MEM_ADDR_WIDTH-1:`VX_MEM_ADDR_WIDTH-LMEM_ADDR_WIDTH]; - -if (`VX_MEM_LINE_WIDTH != LMEM_LINE_WIDTH) begin - wire [VX_MEM_LINE_IDX-1:0] vx_mem_req_idx = vx_mem_req_addr[VX_MEM_LINE_IDX-1:0]; - wire [VX_MEM_LINE_IDX-1:0] vx_mem_rsp_idx = vx_mem_rsp_tag_unqual[VX_MEM_LINE_IDX-1:0]; - assign vx_mem_req_byteen_qual = 64'(vx_mem_req_byteen) << (6'(vx_mem_req_addr[VX_MEM_LINE_IDX-1:0]) << (VX_MEM_LINE_LW-3)); - assign vx_mem_req_data_qual = LMEM_LINE_WIDTH'(vx_mem_req_data) << ((LMEM_LINE_LW'(vx_mem_req_idx)) << VX_MEM_LINE_LW); - assign vx_mem_req_tag_qual = {vx_mem_req_tag, vx_mem_req_idx}; - assign vx_mem_rsp_data = vx_mem_rsp_data_unqual[vx_mem_rsp_idx]; -end else begin - assign vx_mem_req_byteen_qual = vx_mem_req_byteen; - assign vx_mem_req_tag_qual = vx_mem_req_tag; - assign vx_mem_req_data_qual = vx_mem_req_data; - assign vx_mem_rsp_data = vx_mem_rsp_data_unqual; -end - -assign vx_mem_rsp_tag = vx_mem_rsp_tag_unqual[`VX_MEM_TAG_WIDTH+VX_MEM_LINE_IDX-1:VX_MEM_LINE_IDX]; - -//-- - VX_mem_arb #( .NUM_REQS (2), .DATA_WIDTH (LMEM_LINE_WIDTH), @@ -573,13 +603,13 @@ VX_mem_arb #( .reset (reset), // Source request - .req_valid_in ({cci_mem_req_tmp_valid, vx_mem_req_valid_qual}), - .req_rw_in ({cci_mem_req_tmp_rw, vx_mem_req_rw}), - .req_byteen_in ({cci_mem_req_tmp_byteen, vx_mem_req_byteen_qual}), - .req_addr_in ({cci_mem_req_tmp_addr, vx_mem_req_addr_qual}), - .req_data_in ({cci_mem_req_tmp_data, vx_mem_req_data_qual}), - .req_tag_in ({cci_mem_req_tmp_tag, vx_mem_req_tag_qual}), - .req_ready_in ({cci_mem_req_tmp_ready, vx_mem_req_ready}), + .req_valid_in ({cci_mem_req_arb_valid, vx_mem_req_arb_valid}), + .req_rw_in ({cci_mem_req_arb_rw, vx_mem_req_arb_rw}), + .req_byteen_in ({cci_mem_req_arb_byteen, vx_mem_req_arb_byteen}), + .req_addr_in ({cci_mem_req_arb_addr, vx_mem_req_arb_addr}), + .req_data_in ({cci_mem_req_arb_data, vx_mem_req_arb_data}), + .req_tag_in ({cci_mem_req_arb_tag, vx_mem_req_arb_tag}), + .req_ready_in ({cci_mem_req_arb_ready, vx_mem_req_arb_ready}), // Memory request .req_valid_out (mem_req_valid), @@ -591,10 +621,10 @@ VX_mem_arb #( .req_ready_out (mem_req_ready), // Source response - .rsp_valid_out ({cci_mem_rsp_tmp_valid, vx_mem_rsp_valid}), - .rsp_data_out ({cci_mem_rsp_tmp_data, vx_mem_rsp_data_unqual}), - .rsp_tag_out ({cci_mem_rsp_tmp_tag, vx_mem_rsp_tag_unqual}), - .rsp_ready_out ({cci_mem_rsp_tmp_ready, vx_mem_rsp_ready}), + .rsp_valid_out ({cci_mem_rsp_arb_valid, vx_mem_rsp_arb_valid}), + .rsp_data_out ({cci_mem_rsp_arb_data, vx_mem_rsp_arb_data}), + .rsp_tag_out ({cci_mem_rsp_arb_tag, vx_mem_rsp_arb_tag}), + .rsp_ready_out ({cci_mem_rsp_arb_ready, vx_mem_rsp_arb_ready}), // Memory response .rsp_valid_in (mem_rsp_valid), @@ -606,42 +636,42 @@ VX_mem_arb #( //-- VX_avs_wrapper #( - .AVS_DATAW (LMEM_LINE_WIDTH), - .AVS_ADDRW (LMEM_ADDR_WIDTH), - .AVS_BURSTW (LMEM_BURST_CTRW), - .AVS_BANKS (NUM_LOCAL_MEM_BANKS), - .REQ_TAGW (AVS_REQ_TAGW+1), - .RD_QUEUE_SIZE (AVS_RD_QUEUE_SIZE) + .AVS_DATA_WIDTH (LMEM_LINE_WIDTH), + .AVS_ADDR_WIDTH (LMEM_ADDR_WIDTH), + .AVS_BURST_WIDTH (LMEM_BURST_CTRW), + .AVS_BANKS (NUM_LOCAL_MEM_BANKS), + .REQ_TAG_WIDTH (AVS_REQ_TAGW+1), + .RD_QUEUE_SIZE (AVS_RD_QUEUE_SIZE) ) avs_wrapper ( - .clk (clk), - .reset (reset), + .clk (clk), + .reset (reset), // Memory request - .mem_req_valid (mem_req_valid), - .mem_req_rw (mem_req_rw), - .mem_req_byteen (mem_req_byteen), - .mem_req_addr (mem_req_addr), - .mem_req_data (mem_req_data), - .mem_req_tag (mem_req_tag), - .mem_req_ready (mem_req_ready), + .mem_req_valid (mem_req_valid), + .mem_req_rw (mem_req_rw), + .mem_req_byteen (mem_req_byteen), + .mem_req_addr (mem_req_addr), + .mem_req_data (mem_req_data), + .mem_req_tag (mem_req_tag), + .mem_req_ready (mem_req_ready), // Memory response - .mem_rsp_valid (mem_rsp_valid), - .mem_rsp_data (mem_rsp_data), - .mem_rsp_tag (mem_rsp_tag), - .mem_rsp_ready (mem_rsp_ready), + .mem_rsp_valid (mem_rsp_valid), + .mem_rsp_data (mem_rsp_data), + .mem_rsp_tag (mem_rsp_tag), + .mem_rsp_ready (mem_rsp_ready), // AVS bus - .avs_writedata (avs_writedata), - .avs_readdata (avs_readdata), - .avs_address (avs_address), - .avs_waitrequest (avs_waitrequest), - .avs_write (avs_write), - .avs_read (avs_read), - .avs_byteenable (avs_byteenable), - .avs_burstcount (avs_burstcount), - .avs_readdatavalid (avs_readdatavalid), - .avs_bankselect (mem_bank_select) + .avs_writedata (avs_writedata), + .avs_readdata (avs_readdata), + .avs_address (avs_address), + .avs_waitrequest (avs_waitrequest), + .avs_write (avs_write), + .avs_read (avs_read), + .avs_byteenable (avs_byteenable), + .avs_burstcount (avs_burstcount), + .avs_readdatavalid(avs_readdatavalid), + .avs_bankselect (mem_bank_select) ); // CCI-P Read Request /////////////////////////////////////////////////////////// @@ -714,7 +744,7 @@ always @(posedge clk) begin cci_rd_rsp_ctr <= 0; cci_rd_req_enable <= 0; cci_rd_req_wait <= 0; - cci_mem_wr_req_ctr <= 0; + cci_mem_wr_req_ctr <= 0; cci_mem_wr_req_addr_unqual <= 0; end else begin diff --git a/hw/rtl/afu/vortex_afu.vh b/hw/rtl/afu/vortex_afu.vh index 05a5654e..c92a3a32 100644 --- a/hw/rtl/afu/vortex_afu.vh +++ b/hw/rtl/afu/vortex_afu.vh @@ -9,13 +9,17 @@ `define PLATFORM_PARAM_LOCAL_MEMORY_BANKS 2 `endif -`ifndef PLATFORM_PARAM_LOCAL_MEMORY_DATA_SIZE_BITS -`define PLATFORM_PARAM_LOCAL_MEMORY_DATA_SIZE_BITS 6 +`ifndef PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH +`define PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH 26 `endif -`define PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH (32-`PLATFORM_PARAM_LOCAL_MEMORY_DATA_SIZE_BITS) -`define PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH (8 << `PLATFORM_PARAM_LOCAL_MEMORY_DATA_SIZE_BITS) +`ifndef PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH +`define PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH 512 +`endif + +`ifndef PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH `define PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH 4 +`endif `include "local_mem_cfg_pkg.sv" diff --git a/hw/syn/opae/Makefile b/hw/syn/opae/Makefile index 9e4ea121..38f21fba 100644 --- a/hw/syn/opae/Makefile +++ b/hw/syn/opae/Makefile @@ -3,14 +3,6 @@ FPGA_BUILD_DIR ?= build_fpga DEVICE_FAMILY ?= arria10 RTL_DIR=../../rtl -ifeq ($(DEVICE_FAMILY),arria10) - CFLAGS += -DMEM_BLOCK_SIZE=64 -endif - -ifeq ($(DEVICE_FAMILY),stratix10) - CFLAGS += -DMEM_BLOCK_SIZE=16 -endif - ifeq ($(shell which qsub-synth),) RUN_SYNTH=$(OPAE_PLATFORM_ROOT)/bin/run.sh > build.log 2>&1 & else diff --git a/hw/syn/opae/README b/hw/syn/opae/README index 5e9f9537..c85981c7 100644 --- a/hw/syn/opae/README +++ b/hw/syn/opae/README @@ -63,7 +63,8 @@ qsub-sim make ase # tests -./run_ase.sh build_ase_1c ../../../driver/tests/basic/basic -n128 -t0 +./run_ase.sh build_ase_1c ../../../driver/tests/basic/basic -n1 -t0 +./run_ase.sh build_ase_1c ../../../driver/tests/basic/basic -n1 -t1 ./run_ase.sh build_ase_1c ../../../driver/tests/basic/basic -n16 ./run_ase.sh build_ase_1c ../../../driver/tests/demo/demo -n16 ./run_ase.sh build_ase_1c ../../../driver/tests/dogfood/dogfood -n16 @@ -86,7 +87,7 @@ tar -zcvf run.log.tar.gz run.log tar -zcvf vx_scope.vcd.tar.gz vx_scope.vcd tar -cvjf vx_scope.vcd.tar.bz2 vx_scope.vcd tar -cvjf trace.fst.tar.bz2 trace.fst run.log -tar -cvjf trace.vcd.tar.bz2 trace.vcd run.log +tar -cvjf trace.vcd.tar.bz2 driver/tests/basic/trace.vcd run.log tar -cvjf trace.vcd.tar.bz2 build_ase_1c/work/run.log build_ase_1c/work/trace.vcd # decompress VCD trace