Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
This commit is contained in:
Blaise Tine
341
sim/simx/exe_unit.cpp
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341
sim/simx/exe_unit.cpp
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "exe_unit.h"
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#include <iostream>
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#include <iomanip>
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#include <string.h>
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#include <assert.h>
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#include <util.h>
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#include "debug.h"
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#include "core.h"
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#include "constants.h"
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#include "cache_sim.h"
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using namespace vortex;
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AluUnit::AluUnit(const SimContext& ctx, Core* core) : ExeUnit(ctx, core, "ALU") {}
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void AluUnit::tick() {
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for (uint32_t i = 0; i < ISSUE_WIDTH; ++i) {
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auto& input = Inputs.at(i);
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if (input.empty())
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continue;
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auto& output = Outputs.at(i);
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auto trace = input.front();
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switch (trace->alu_type) {
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case AluType::ARITH:
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case AluType::BRANCH:
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case AluType::SYSCALL:
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case AluType::IMUL:
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output.send(trace, LATENCY_IMUL+1);
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break;
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case AluType::IDIV:
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output.send(trace, XLEN+1);
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break;
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default:
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std::abort();
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}
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DT(3, "pipeline-execute: op=" << trace->alu_type << ", " << *trace);
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if (trace->eop && trace->fetch_stall) {
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assert(core_->stalled_warps_.test(trace->wid));
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core_->stalled_warps_.reset(trace->wid);
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}
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auto time = input.pop();
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core_->perf_stats_.alu_stalls += (SimPlatform::instance().cycles() - time);
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}
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}
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///////////////////////////////////////////////////////////////////////////////
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FpuUnit::FpuUnit(const SimContext& ctx, Core* core) : ExeUnit(ctx, core, "FPU") {}
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void FpuUnit::tick() {
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for (uint32_t i = 0; i < ISSUE_WIDTH; ++i) {
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auto& input = Inputs.at(i);
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if (input.empty())
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continue;
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auto& output = Outputs.at(i);
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auto trace = input.front();
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switch (trace->fpu_type) {
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case FpuType::FNCP:
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output.send(trace, 2);
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break;
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case FpuType::FMA:
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output.send(trace, LATENCY_FMA+1);
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break;
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case FpuType::FDIV:
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output.send(trace, LATENCY_FDIV+1);
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break;
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case FpuType::FSQRT:
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output.send(trace, LATENCY_FSQRT+1);
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break;
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case FpuType::FCVT:
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output.send(trace, LATENCY_FCVT+1);
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break;
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default:
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std::abort();
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}
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DT(3, "pipeline-execute: op=" << trace->fpu_type << ", " << *trace);
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auto time = input.pop();
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core_->perf_stats_.fpu_stalls += (SimPlatform::instance().cycles() - time);
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}
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}
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///////////////////////////////////////////////////////////////////////////////
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LsuUnit::LsuUnit(const SimContext& ctx, Core* core)
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: ExeUnit(ctx, core, "LSU")
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, pending_rd_reqs_(LSUQ_SIZE)
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, num_lanes_(NUM_LSU_LANES)
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, pending_loads_(0)
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, fence_lock_(false)
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, input_idx_(0)
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{}
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void LsuUnit::reset() {
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pending_rd_reqs_.clear();
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pending_loads_ = 0;
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fence_lock_ = false;
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}
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void LsuUnit::tick() {
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core_->perf_stats_.load_latency += pending_loads_;
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// handle dcache response
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for (uint32_t t = 0; t < num_lanes_; ++t) {
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auto& dcache_rsp_port = core_->dcache_rsp_ports.at(t);
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if (dcache_rsp_port.empty())
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continue;
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auto& mem_rsp = dcache_rsp_port.front();
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auto& entry = pending_rd_reqs_.at(mem_rsp.tag);
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auto trace = entry.trace;
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DT(3, "dcache-rsp: tag=" << mem_rsp.tag << ", type=" << trace->lsu_type
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<< ", tid=" << t << ", " << *trace);
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assert(entry.count);
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--entry.count; // track remaining addresses
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if (0 == entry.count) {
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int iw = trace->wid % ISSUE_WIDTH;
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auto& output = Outputs.at(iw);
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output.send(trace, 1);
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pending_rd_reqs_.release(mem_rsp.tag);
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}
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dcache_rsp_port.pop();
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--pending_loads_;
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}
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// handle shared memory response
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for (uint32_t t = 0; t < num_lanes_; ++t) {
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auto& smem_rsp_port = core_->sharedmem_->Outputs.at(t);
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if (smem_rsp_port.empty())
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continue;
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auto& mem_rsp = smem_rsp_port.front();
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auto& entry = pending_rd_reqs_.at(mem_rsp.tag);
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auto trace = entry.trace;
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DT(3, "smem-rsp: tag=" << mem_rsp.tag << ", type=" << trace->lsu_type << ", tid=" << t << ", " << *trace);
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assert(entry.count);
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--entry.count; // track remaining addresses
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if (0 == entry.count) {
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int iw = trace->wid % ISSUE_WIDTH;
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auto& output = Outputs.at(iw);
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output.send(trace, 1);
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pending_rd_reqs_.release(mem_rsp.tag);
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}
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smem_rsp_port.pop();
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--pending_loads_;
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}
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if (fence_lock_) {
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// wait for all pending memory operations to complete
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if (!pending_rd_reqs_.empty())
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return;
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int iw = fence_state_->wid % ISSUE_WIDTH;
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auto& output = Outputs.at(iw);
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output.send(fence_state_, 1);
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fence_lock_ = false;
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DT(3, "fence-unlock: " << fence_state_);
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}
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// check input queue
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for (uint32_t i = 0; i < ISSUE_WIDTH; ++i) {
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int iw = (input_idx_ + i) % ISSUE_WIDTH;
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auto& input = Inputs.at(iw);
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if (input.empty())
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continue;
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auto& output = Outputs.at(iw);
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auto trace = input.front();
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auto trace_data = std::dynamic_pointer_cast<LsuTraceData>(trace->data);
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auto t0 = trace->pid * num_lanes_;
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if (trace->lsu_type == LsuType::FENCE) {
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// schedule fence lock
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fence_state_ = trace;
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fence_lock_ = true;
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DT(3, "fence-lock: " << *trace);
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// remove input
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auto time = input.pop();
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core_->perf_stats_.lsu_stalls += (SimPlatform::instance().cycles() - time);
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break;
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}
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// check pending queue capacity
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if (pending_rd_reqs_.full()) {
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if (!trace->log_once(true)) {
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DT(3, "*** " << this->name() << "-lsu-queue-stall: " << *trace);
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}
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break;
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} else {
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trace->log_once(false);
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}
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bool is_write = (trace->lsu_type == LsuType::STORE);
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// duplicates detection
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bool is_dup = false;
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if (trace->tmask.test(t0)) {
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uint64_t addr_mask = sizeof(uint32_t)-1;
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uint32_t addr0 = trace_data->mem_addrs.at(0).addr & ~addr_mask;
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uint32_t matches = 1;
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for (uint32_t t = 1; t < num_lanes_; ++t) {
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if (!trace->tmask.test(t0 + t))
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continue;
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auto mem_addr = trace_data->mem_addrs.at(t).addr & ~addr_mask;
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matches += (addr0 == mem_addr);
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}
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is_dup = (matches == trace->tmask.count());
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}
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uint32_t addr_count;
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if (is_dup) {
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addr_count = 1;
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} else {
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addr_count = trace->tmask.count();
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}
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auto tag = pending_rd_reqs_.allocate({trace, addr_count});
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for (uint32_t t = 0; t < num_lanes_; ++t) {
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if (!trace->tmask.test(t0 + t))
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continue;
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auto& dcache_req_port = core_->dcache_req_ports.at(t);
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auto mem_addr = trace_data->mem_addrs.at(t);
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auto type = core_->get_addr_type(mem_addr.addr);
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MemReq mem_req;
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mem_req.addr = mem_addr.addr;
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mem_req.write = is_write;
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mem_req.type = type;
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mem_req.tag = tag;
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mem_req.cid = trace->cid;
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mem_req.uuid = trace->uuid;
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dcache_req_port.send(mem_req, 2);
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DT(3, "dcache-req: addr=0x" << std::hex << mem_req.addr << ", tag=" << tag
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<< ", lsu_type=" << trace->lsu_type << ", tid=" << t << ", addr_type=" << mem_req.type << ", " << *trace);
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++pending_loads_;
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++core_->perf_stats_.loads;
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if (is_dup)
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break;
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}
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// do not wait on writes
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if (is_write) {
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pending_rd_reqs_.release(tag);
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output.send(trace, 1);
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++core_->perf_stats_.stores;
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}
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// remove input
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auto time = input.pop();
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core_->perf_stats_.lsu_stalls += (SimPlatform::instance().cycles() - time);
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break; // single block
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}
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++input_idx_;
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}
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///////////////////////////////////////////////////////////////////////////////
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SfuUnit::SfuUnit(const SimContext& ctx, Core* core)
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: ExeUnit(ctx, core, "SFU")
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{}
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void SfuUnit::tick() {
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// handle pending responses
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for (auto pending_rsp : pending_rsps_) {
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if (pending_rsp->empty())
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continue;
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auto trace = pending_rsp->front();
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if (trace->cid != core_->id())
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continue;
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int iw = trace->wid % ISSUE_WIDTH;
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auto& output = Outputs.at(iw);
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output.send(trace, 1);
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pending_rsp->pop();
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}
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// check input queue
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for (uint32_t i = 0; i < ISSUE_WIDTH; ++i) {
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int iw = (input_idx_ + i) % ISSUE_WIDTH;
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auto& input = Inputs.at(iw);
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if (input.empty())
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continue;
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auto& output = Outputs.at(iw);
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auto trace = input.front();
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auto sfu_type = trace->sfu_type;
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bool release_warp = trace->fetch_stall;
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switch (sfu_type) {
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case SfuType::TMC:
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case SfuType::WSPAWN:
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case SfuType::SPLIT:
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case SfuType::JOIN:
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case SfuType::PRED:
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case SfuType::CSRRW:
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case SfuType::CSRRS:
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case SfuType::CSRRC:
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output.send(trace, 1);
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break;
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case SfuType::BAR: {
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output.send(trace, 1);
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auto trace_data = std::dynamic_pointer_cast<SFUTraceData>(trace->data);
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if (trace->eop) {
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core_->barrier(trace_data->bar.id, trace_data->bar.count, trace->wid);
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}
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release_warp = false;
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} break;
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case SfuType::CMOV:
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output.send(trace, 3);
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break;
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default:
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std::abort();
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}
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DT(3, "pipeline-execute: op=" << trace->sfu_type << ", " << *trace);
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if (trace->eop && release_warp) {
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assert(core_->stalled_warps_.test(trace->wid));
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core_->stalled_warps_.reset(trace->wid);
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}
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auto time = input.pop();
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auto stalls = (SimPlatform::instance().cycles() - time);
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core_->perf_stats_.sfu_stalls += stalls;
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break; // single block
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}
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++input_idx_;
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}
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