Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
This commit is contained in:
Blaise Tine
40
hw/syn/xilinx/xrt/scripts/gen_ip.tcl
Normal file
40
hw/syn/xilinx/xrt/scripts/gen_ip.tcl
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@@ -0,0 +1,40 @@
|
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# Copyright © 2019-2023
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
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# Unless required by applicable law or agreed to in writing, software
|
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# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
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||||
|
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if { $::argc != 1 } {
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puts "ERROR: Program \"$::argv0\" requires 1 arguments!\n"
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puts "Usage: $::argv0 <ip_dir>\n"
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exit
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}
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set ip_dir [lindex $::argv 0]
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# IP folder does not exist. Create IP folder
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file mkdir ${ip_dir}
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# create_ip requires that a project is open in memory.
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# Create project but don't do anything with it
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create_project -in_memory
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create_ip -name floating_point -vendor xilinx.com -library ip -version 7.1 -module_name xil_fdiv -dir ${ip_dir}
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set_property -dict [list CONFIG.Component_Name {xil_fdiv} CONFIG.Operation_Type {Divide} CONFIG.Flow_Control {NonBlocking} CONFIG.Has_ACLKEN {true} CONFIG.C_Has_UNDERFLOW {true} CONFIG.C_Has_OVERFLOW {true} CONFIG.C_Has_INVALID_OP {true} CONFIG.C_Has_DIVIDE_BY_ZERO {true} CONFIG.A_Precision_Type {Single} CONFIG.C_A_Exponent_Width {8} CONFIG.C_A_Fraction_Width {24} CONFIG.Result_Precision_Type {Single} CONFIG.C_Result_Exponent_Width {8} CONFIG.C_Result_Fraction_Width {24} CONFIG.C_Mult_Usage {No_Usage} CONFIG.Has_RESULT_TREADY {false} CONFIG.C_Latency {28} CONFIG.C_Rate {1}] [get_ips xil_fdiv]
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create_ip -name floating_point -vendor xilinx.com -library ip -version 7.1 -module_name xil_fsqrt -dir ${ip_dir}
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set_property -dict [list CONFIG.Component_Name {xil_fsqrt} CONFIG.Operation_Type {Square_root} CONFIG.Flow_Control {NonBlocking} CONFIG.Has_ACLKEN {true} CONFIG.C_Has_INVALID_OP {true} CONFIG.A_Precision_Type {Single} CONFIG.C_A_Exponent_Width {8} CONFIG.C_A_Fraction_Width {24} CONFIG.Result_Precision_Type {Single} CONFIG.C_Result_Exponent_Width {8} CONFIG.C_Result_Fraction_Width {24} CONFIG.C_Mult_Usage {No_Usage} CONFIG.Has_RESULT_TREADY {false} CONFIG.C_Latency {28} CONFIG.C_Rate {1}] [get_ips xil_fsqrt]
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create_ip -name floating_point -vendor xilinx.com -library ip -version 7.1 -module_name xil_fma -dir ${ip_dir}
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set_property -dict [list CONFIG.Component_Name {xil_fma} CONFIG.Operation_Type {FMA} CONFIG.Add_Sub_Value {Add} CONFIG.Flow_Control {NonBlocking} CONFIG.Has_ACLKEN {true} CONFIG.C_Has_UNDERFLOW {true} CONFIG.C_Has_OVERFLOW {true} CONFIG.C_Has_INVALID_OP {true} CONFIG.Has_A_TUSER {false} CONFIG.A_Precision_Type {Single} CONFIG.C_A_Exponent_Width {8} CONFIG.C_A_Fraction_Width {24} CONFIG.Result_Precision_Type {Single} CONFIG.C_Result_Exponent_Width {8} CONFIG.C_Result_Fraction_Width {24} CONFIG.C_Mult_Usage {Medium_Usage} CONFIG.Has_RESULT_TREADY {false} CONFIG.C_Latency {16} CONFIG.C_Rate {1} CONFIG.A_TUSER_Width {1}] [get_ips xil_fma]
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generate_target all [get_ips]
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close_project -delete
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40
hw/syn/xilinx/xrt/scripts/gen_xo.tcl
Normal file
40
hw/syn/xilinx/xrt/scripts/gen_xo.tcl
Normal file
@@ -0,0 +1,40 @@
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# Copyright © 2019-2023
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
|
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# You may obtain a copy of the License at
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
|
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# distributed under the License is distributed on an "AS IS" BASIS,
|
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
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# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
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if { $::argc != 5 } {
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puts "ERROR: Program \"$::argv0\" requires 4 arguments!\n"
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puts "Usage: $::argv0 <xoname> <krnl_name> <vcs_file> <tool_dir> <build_dir>\n"
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exit
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}
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set xoname [lindex $::argv 0]
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set krnl_name [lindex $::argv 1]
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set vcs_file [lindex $::argv 2]
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set tool_dir [lindex $::argv 3]
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set build_dir [lindex $::argv 4]
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set script_path [ file dirname [ file normalize [ info script ] ] ]
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if {[file exists "${xoname}"]} {
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file delete -force "${xoname}"
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}
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set argv [list ${build_dir}/ip]
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set argc 1
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source ${script_path}/gen_ip.tcl
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set argv [list ${krnl_name} ${vcs_file} ${tool_dir} ${build_dir}]
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set argc 4
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source ${script_path}/package_kernel.tcl
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package_xo -xo_path ${xoname} -kernel_name ${krnl_name} -ip_directory "${build_dir}/xo/packaged_kernel"
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268
hw/syn/xilinx/xrt/scripts/package_kernel.tcl
Normal file
268
hw/syn/xilinx/xrt/scripts/package_kernel.tcl
Normal file
@@ -0,0 +1,268 @@
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# Copyright © 2019-2023
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#
|
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# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
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# http://www.apache.org/licenses/LICENSE-2.0
|
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#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
if { $::argc != 4 } {
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puts "ERROR: Program \"$::argv0\" requires 4 arguments!\n"
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puts "Usage: $::argv0 <krnl_name> <vcs_file> <tool_dir> <build_dir>\n"
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exit
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}
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set krnl_name [lindex $::argv 0]
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set vcs_file [lindex $::argv 1]
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set tool_dir [lindex $::argv 2]
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set build_dir [lindex $::argv 3]
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set path_to_packaged "${build_dir}/xo/packaged_kernel"
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set path_to_tmp_project "${build_dir}/xo/project"
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source "${tool_dir}/parse_vcs_list.tcl"
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set vlist [parse_vcs_list "${vcs_file}"]
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set vsources_list [lindex $vlist 0]
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set vincludes_list [lindex $vlist 1]
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set vdefines_list [lindex $vlist 2]
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#puts ${vsources_list}
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#puts ${vincludes_list}
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#puts ${vdefines_list}
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# find if chipscope is enabled
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set chipscope 0
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foreach def $vdefines_list {
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set fields [split $def "="]
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set name [lindex $fields 0]
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if { $name == "CHIPSCOPE" } {
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set chipscope 1
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}
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}
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create_project -force kernel_pack $path_to_tmp_project
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add_files -norecurse ${vsources_list}
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set obj [get_filesets sources_1]
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set files [list \
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[file normalize "${build_dir}/ip/xil_fdiv/xil_fdiv.xci"] \
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[file normalize "${build_dir}/ip/xil_fma/xil_fma.xci"] \
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[file normalize "${build_dir}/ip/xil_fsqrt/xil_fsqrt.xci"] \
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]
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add_files -verbose -norecurse -fileset $obj $files
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set_property include_dirs ${vincludes_list} [current_fileset]
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#set_property verilog_define ${vdefines_list} [current_fileset]
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set obj [get_filesets sources_1]
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set_property -verbose -name "top" -value ${krnl_name} -objects $obj
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if { $chipscope == 1 } {
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# hw debugging
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create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_afu
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set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
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CONFIG.C_EN_STRG_QUAL {1} \
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CONFIG.C_DATA_DEPTH {4096} \
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CONFIG.C_NUM_OF_PROBES {2} \
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CONFIG.C_PROBE0_WIDTH {8} \
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CONFIG.C_PROBE1_WIDTH {24} \
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] [get_ips ila_afu]
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generate_target {instantiation_template} [get_files ila_afu.xci]
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set_property generate_synth_checkpoint false [get_files ila_afu.xci]
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create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_fetch
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set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
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CONFIG.C_EN_STRG_QUAL {1} \
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CONFIG.C_DATA_DEPTH {4096} \
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CONFIG.C_NUM_OF_PROBES {3} \
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CONFIG.C_PROBE0_WIDTH {128} \
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CONFIG.C_PROBE1_WIDTH {128} \
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CONFIG.C_PROBE2_WIDTH {128} \
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] [get_ips ila_fetch]
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generate_target {instantiation_template} [get_files ila_fetch.xci]
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set_property generate_synth_checkpoint false [get_files ila_fetch.xci]
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create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_issue
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set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
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CONFIG.C_EN_STRG_QUAL {1} \
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CONFIG.C_DATA_DEPTH {4096} \
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CONFIG.C_NUM_OF_PROBES {2} \
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CONFIG.C_PROBE0_WIDTH {256} \
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CONFIG.C_PROBE1_WIDTH {128} \
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] [get_ips ila_issue]
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generate_target {instantiation_template} [get_files ila_issue.xci]
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set_property generate_synth_checkpoint false [get_files ila_issue.xci]
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create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_lsu
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set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
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CONFIG.C_EN_STRG_QUAL {1} \
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CONFIG.C_DATA_DEPTH {4096} \
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CONFIG.C_NUM_OF_PROBES {4} \
|
||||
CONFIG.C_PROBE0_WIDTH {256} \
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CONFIG.C_PROBE1_WIDTH {128} \
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CONFIG.C_PROBE2_WIDTH {288} \
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CONFIG.C_PROBE3_WIDTH {256} \
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] [get_ips ila_lsu]
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generate_target {instantiation_template} [get_files ila_lsu.xci]
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set_property generate_synth_checkpoint false [get_files ila_lsu.xci]
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create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_msched
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set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
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CONFIG.C_EN_STRG_QUAL {1} \
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CONFIG.C_DATA_DEPTH {4096} \
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CONFIG.C_NUM_OF_PROBES {4} \
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||||
CONFIG.C_PROBE0_WIDTH {128} \
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||||
CONFIG.C_PROBE1_WIDTH {128} \
|
||||
CONFIG.C_PROBE2_WIDTH {128} \
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CONFIG.C_PROBE3_WIDTH {128} \
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] [get_ips ila_msched]
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generate_target {instantiation_template} [get_files ila_msched.xci]
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set_property generate_synth_checkpoint false [get_files ila_msched.xci]
|
||||
|
||||
create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_raster
|
||||
set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
|
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CONFIG.C_EN_STRG_QUAL {1} \
|
||||
CONFIG.C_DATA_DEPTH {4096} \
|
||||
CONFIG.C_NUM_OF_PROBES {2} \
|
||||
CONFIG.C_PROBE0_WIDTH {128} \
|
||||
CONFIG.C_PROBE1_WIDTH {128} \
|
||||
] [get_ips ila_raster]
|
||||
generate_target {instantiation_template} [get_files ila_raster.xci]
|
||||
set_property generate_synth_checkpoint false [get_files ila_raster.xci]
|
||||
}
|
||||
|
||||
update_compile_order -fileset sources_1
|
||||
update_compile_order -fileset sim_1
|
||||
ipx::package_project -root_dir $path_to_packaged -vendor xilinx.com -library RTLKernel -taxonomy /KernelIP -import_files -set_current false
|
||||
ipx::unload_core $path_to_packaged/component.xml
|
||||
ipx::edit_ip_in_project -upgrade true -name tmp_edit_project -directory $path_to_packaged $path_to_packaged/component.xml
|
||||
|
||||
set core [ipx::current_core]
|
||||
|
||||
set_property core_revision 2 $core
|
||||
foreach up [ipx::get_user_parameters] {
|
||||
ipx::remove_user_parameter [get_property NAME $up] $core
|
||||
}
|
||||
|
||||
ipx::associate_bus_interfaces -busif s_axi_ctrl -clock ap_clk $core
|
||||
|
||||
for {set i 0} {$i < 1} {incr i} {
|
||||
ipx::associate_bus_interfaces -busif m_axi_mem_$i -clock ap_clk $core
|
||||
}
|
||||
|
||||
set mem_map [::ipx::add_memory_map -quiet "s_axi_ctrl" $core]
|
||||
set addr_block [::ipx::add_address_block -quiet "reg0" $mem_map]
|
||||
|
||||
set reg [::ipx::add_register "CTRL" $addr_block]
|
||||
set_property description "Control signals" $reg
|
||||
set_property address_offset 0x000 $reg
|
||||
set_property size 32 $reg
|
||||
|
||||
set field [ipx::add_field AP_START $reg]
|
||||
set_property ACCESS {read-write} $field
|
||||
set_property BIT_OFFSET {0} $field
|
||||
set_property BIT_WIDTH {1} $field
|
||||
set_property DESCRIPTION {Control signal Register for 'ap_start'.} $field
|
||||
set_property MODIFIED_WRITE_VALUE {modify} $field
|
||||
|
||||
set field [ipx::add_field AP_DONE $reg]
|
||||
set_property ACCESS {read-only} $field
|
||||
set_property BIT_OFFSET {1} $field
|
||||
set_property BIT_WIDTH {1} $field
|
||||
set_property DESCRIPTION {Control signal Register for 'ap_done'.} $field
|
||||
set_property READ_ACTION {modify} $field
|
||||
|
||||
set field [ipx::add_field AP_IDLE $reg]
|
||||
set_property ACCESS {read-only} $field
|
||||
set_property BIT_OFFSET {2} $field
|
||||
set_property BIT_WIDTH {1} $field
|
||||
set_property DESCRIPTION {Control signal Register for 'ap_idle'.} $field
|
||||
set_property READ_ACTION {modify} $field
|
||||
|
||||
set field [ipx::add_field AP_READY $reg]
|
||||
set_property ACCESS {read-only} $field
|
||||
set_property BIT_OFFSET {3} $field
|
||||
set_property BIT_WIDTH {1} $field
|
||||
set_property DESCRIPTION {Control signal Register for 'ap_ready'.} $field
|
||||
set_property READ_ACTION {modify} $field
|
||||
|
||||
set field [ipx::add_field RESERVED_1 $reg]
|
||||
set_property ACCESS {read-only} $field
|
||||
set_property BIT_OFFSET {4} $field
|
||||
set_property BIT_WIDTH {3} $field
|
||||
set_property DESCRIPTION {Reserved. 0s on read.} $field
|
||||
set_property READ_ACTION {modify} $field
|
||||
|
||||
set field [ipx::add_field AUTO_RESTART $reg]
|
||||
set_property ACCESS {read-write} $field
|
||||
set_property BIT_OFFSET {7} $field
|
||||
set_property BIT_WIDTH {1} $field
|
||||
set_property DESCRIPTION {Control signal Register for 'auto_restart'.} $field
|
||||
set_property MODIFIED_WRITE_VALUE {modify} $field
|
||||
|
||||
set field [ipx::add_field RESERVED_2 $reg]
|
||||
set_property ACCESS {read-only} $field
|
||||
set_property BIT_OFFSET {8} $field
|
||||
set_property BIT_WIDTH {24} $field
|
||||
set_property DESCRIPTION {Reserved. 0s on read.} $field
|
||||
set_property READ_ACTION {modify} $field
|
||||
|
||||
set reg [::ipx::add_register "GIER" $addr_block]
|
||||
set_property description "Global Interrupt Enable Register" $reg
|
||||
set_property address_offset 0x004 $reg
|
||||
set_property size 32 $reg
|
||||
|
||||
set reg [::ipx::add_register "IP_IER" $addr_block]
|
||||
set_property description "IP Interrupt Enable Register" $reg
|
||||
set_property address_offset 0x008 $reg
|
||||
set_property size 32 $reg
|
||||
|
||||
set reg [::ipx::add_register "IP_ISR" $addr_block]
|
||||
set_property description "IP Interrupt Status Register" $reg
|
||||
set_property address_offset 0x00C $reg
|
||||
set_property size 32 $reg
|
||||
|
||||
set reg [::ipx::add_register -quiet "DEV" $addr_block]
|
||||
set_property address_offset 0x010 $reg
|
||||
set_property size [expr {8*8}] $reg
|
||||
|
||||
set reg [::ipx::add_register -quiet "ISA" $addr_block]
|
||||
set_property address_offset 0x01C $reg
|
||||
set_property size [expr {8*8}] $reg
|
||||
|
||||
set reg [::ipx::add_register -quiet "DCR" $addr_block]
|
||||
set_property address_offset 0x028 $reg
|
||||
set_property size [expr {8*8}] $reg
|
||||
|
||||
set reg [::ipx::add_register -quiet "SCP" $addr_block]
|
||||
set_property address_offset 0x034 $reg
|
||||
set_property size [expr {8*8}] $reg
|
||||
|
||||
for {set i 0} {$i < 1} {incr i} {
|
||||
set reg [::ipx::add_register -quiet "MEM_$i" $addr_block]
|
||||
set_property address_offset [expr {0x040 + $i * 12}] $reg
|
||||
set_property size [expr {8*8}] $reg
|
||||
set regparam [::ipx::add_register_parameter -quiet {ASSOCIATED_BUSIF} $reg]
|
||||
set_property value m_axi_mem_$i $regparam
|
||||
}
|
||||
|
||||
set_property slave_memory_map_ref "s_axi_ctrl" [::ipx::get_bus_interfaces -of $core "s_axi_ctrl"]
|
||||
|
||||
set_property xpm_libraries {XPM_CDC XPM_MEMORY XPM_FIFO} $core
|
||||
set_property sdx_kernel true $core
|
||||
set_property sdx_kernel_type rtl $core
|
||||
set_property supported_families { } $core
|
||||
set_property auto_family_support_level level_2 $core
|
||||
|
||||
ipx::create_xgui_files $core
|
||||
ipx::update_checksums $core
|
||||
ipx::check_integrity -kernel $core
|
||||
ipx::save_core $core
|
||||
close_project -delete
|
||||
25
hw/syn/xilinx/xrt/scripts/xsim.tcl
Normal file
25
hw/syn/xilinx/xrt/scripts/xsim.tcl
Normal file
@@ -0,0 +1,25 @@
|
||||
#
|
||||
# Copyright 2021 Xilinx, Inc.
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
|
||||
#log_wave -r *
|
||||
#run all
|
||||
#exit
|
||||
|
||||
open_vcd xsim_dump.vcd
|
||||
log_vcd /*
|
||||
run all
|
||||
close_vcd
|
||||
exit
|
||||
Reference in New Issue
Block a user