Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
This commit is contained in:
Blaise Tine
208
hw/syn/xilinx/test/project_1_files/Vortex_top.v
Normal file
208
hw/syn/xilinx/test/project_1_files/Vortex_top.v
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module Vortex_top #(
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parameter C_M_AXI_GMEM_DATA_WIDTH = 512,
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parameter C_M_AXI_GMEM_ADDR_WIDTH = `XLEN,
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parameter C_M_AXI_GMEM_ID_WIDTH = 32,
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parameter C_M_AXI_MEM_NUM_BANKS = 1
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) (
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input wire clk,
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input wire reset,
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// AXI4 memory interface
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output wire m_axi_mem_awvalid,
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input wire m_axi_mem_awready,
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output wire [C_M_AXI_GMEM_ADDR_WIDTH-1:0] m_axi_mem_awaddr,
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output wire [C_M_AXI_GMEM_ID_WIDTH - 1:0] m_axi_mem_awid,
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output wire [7:0] m_axi_mem_awlen,
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output wire [2:0] m_axi_mem_awsize,
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output wire [1:0] m_axi_mem_awburst,
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output wire [1:0] m_axi_mem_awlock,
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output wire [3:0] m_axi_mem_awcache,
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output wire [2:0] m_axi_mem_awprot,
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output wire [3:0] m_axi_mem_awqos,
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output wire m_axi_mem_wvalid,
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input wire m_axi_mem_wready,
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output wire [C_M_AXI_GMEM_DATA_WIDTH-1:0] m_axi_mem_wdata,
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output wire [C_M_AXI_GMEM_DATA_WIDTH/8-1:0] m_axi_mem_wstrb,
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output wire m_axi_mem_wlast,
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output wire m_axi_mem_arvalid,
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input wire m_axi_mem_arready,
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output wire [C_M_AXI_GMEM_ADDR_WIDTH-1:0] m_axi_mem_araddr,
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output wire [C_M_AXI_GMEM_ID_WIDTH-1:0] m_axi_mem_arid,
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output wire [7:0] m_axi_mem_arlen,
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output wire [2:0] m_axi_mem_arsize,
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output wire [1:0] m_axi_mem_arburst,
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output wire [1:0] m_axi_mem_arlock,
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output wire [3:0] m_axi_mem_arcache,
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output wire [2:0] m_axi_mem_arprot,
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output wire [3:0] m_axi_mem_arqos,
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input wire m_axi_mem_rvalid,
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output wire m_axi_mem_rready,
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input wire [C_M_AXI_GMEM_DATA_WIDTH - 1:0] m_axi_mem_rdata,
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input wire m_axi_mem_rlast,
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input wire [C_M_AXI_GMEM_ID_WIDTH - 1:0] m_axi_mem_rid,
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input wire [1:0] m_axi_mem_rresp,
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input wire m_axi_mem_bvalid,
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output wire m_axi_mem_bready,
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input wire [1:0] m_axi_mem_bresp,
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input wire [C_M_AXI_GMEM_ID_WIDTH - 1:0] m_axi_mem_bid,
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input wire dcr_wr_valid,
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input wire [`VX_DCR_ADDR_WIDTH-1:0] dcr_wr_addr,
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input wire [`VX_DCR_DATA_WIDTH-1:0] dcr_wr_data,
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output wire busy
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);
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wire m_axi_mem_awvalid_a [C_M_AXI_MEM_NUM_BANKS];
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wire m_axi_mem_awready_a [C_M_AXI_MEM_NUM_BANKS];
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wire [C_M_AXI_GMEM_ADDR_WIDTH-1:0] m_axi_mem_awaddr_a [C_M_AXI_MEM_NUM_BANKS];
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wire [C_M_AXI_GMEM_ID_WIDTH - 1:0] m_axi_mem_awid_a [C_M_AXI_MEM_NUM_BANKS];
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wire [7:0] m_axi_mem_awlen_a [C_M_AXI_MEM_NUM_BANKS];
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wire [2:0] m_axi_mem_awsize_a [C_M_AXI_MEM_NUM_BANKS];
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wire [1:0] m_axi_mem_awburst_a [C_M_AXI_MEM_NUM_BANKS];
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wire [1:0] m_axi_mem_awlock_a [C_M_AXI_MEM_NUM_BANKS];
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wire [3:0] m_axi_mem_awcache_a [C_M_AXI_MEM_NUM_BANKS];
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wire [2:0] m_axi_mem_awprot_a [C_M_AXI_MEM_NUM_BANKS];
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wire [3:0] m_axi_mem_awqos_a [C_M_AXI_MEM_NUM_BANKS];
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wire m_axi_mem_wvalid_a [C_M_AXI_MEM_NUM_BANKS];
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wire m_axi_mem_wready_a [C_M_AXI_MEM_NUM_BANKS];
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wire [C_M_AXI_GMEM_DATA_WIDTH-1:0] m_axi_mem_wdata_a [C_M_AXI_MEM_NUM_BANKS];
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wire [C_M_AXI_GMEM_DATA_WIDTH/8-1:0] m_axi_mem_wstrb_a [C_M_AXI_MEM_NUM_BANKS];
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wire m_axi_mem_wlast_a [C_M_AXI_MEM_NUM_BANKS];
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wire m_axi_mem_arvalid_a [C_M_AXI_MEM_NUM_BANKS];
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wire m_axi_mem_arready_a [C_M_AXI_MEM_NUM_BANKS];
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wire [C_M_AXI_GMEM_ADDR_WIDTH-1:0] m_axi_mem_araddr_a [C_M_AXI_MEM_NUM_BANKS];
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wire [C_M_AXI_GMEM_ID_WIDTH-1:0] m_axi_mem_arid_a [C_M_AXI_MEM_NUM_BANKS];
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wire [7:0] m_axi_mem_arlen_a [C_M_AXI_MEM_NUM_BANKS];
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wire [2:0] m_axi_mem_arsize_a [C_M_AXI_MEM_NUM_BANKS];
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wire [1:0] m_axi_mem_arburst_a [C_M_AXI_MEM_NUM_BANKS];
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wire [1:0] m_axi_mem_arlock_a [C_M_AXI_MEM_NUM_BANKS];
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wire [3:0] m_axi_mem_arcache_a [C_M_AXI_MEM_NUM_BANKS];
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wire [2:0] m_axi_mem_arprot_a [C_M_AXI_MEM_NUM_BANKS];
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wire [3:0] m_axi_mem_arqos_a [C_M_AXI_MEM_NUM_BANKS];
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wire m_axi_mem_rvalid_a [C_M_AXI_MEM_NUM_BANKS];
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wire m_axi_mem_rready_a [C_M_AXI_MEM_NUM_BANKS];
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wire [C_M_AXI_GMEM_DATA_WIDTH - 1:0] m_axi_mem_rdata_a [C_M_AXI_MEM_NUM_BANKS];
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wire m_axi_mem_rlast_a [C_M_AXI_MEM_NUM_BANKS];
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wire [C_M_AXI_GMEM_ID_WIDTH - 1:0] m_axi_mem_rid_a [C_M_AXI_MEM_NUM_BANKS];
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wire [1:0] m_axi_mem_rresp_a [C_M_AXI_MEM_NUM_BANKS];
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wire m_axi_mem_bvalid_a [C_M_AXI_MEM_NUM_BANKS];
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wire m_axi_mem_bready_a [C_M_AXI_MEM_NUM_BANKS];
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wire [1:0] m_axi_mem_bresp_a [C_M_AXI_MEM_NUM_BANKS];
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wire [C_M_AXI_GMEM_ID_WIDTH - 1:0] m_axi_mem_bid_a [C_M_AXI_MEM_NUM_BANKS];
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assign m_axi_mem_awvalid = m_axi_mem_awvalid_a[0];
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assign m_axi_mem_awready_a[0] = m_axi_mem_awready;
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assign m_axi_mem_awaddr = m_axi_mem_awaddr_a[0];
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assign m_axi_mem_awid = m_axi_mem_awid_a[0];
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assign m_axi_mem_awlen = m_axi_mem_awlen_a[0];
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assign m_axi_mem_awsize = m_axi_mem_awsize_a[0];
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assign m_axi_mem_awburst = m_axi_mem_awburst_a[0];
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assign m_axi_mem_awlock = m_axi_mem_awlock_a[0];
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assign m_axi_mem_awcache = m_axi_mem_awcache_a[0];
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assign m_axi_mem_awprot = m_axi_mem_awprot_a[0];
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assign m_axi_mem_awqos = m_axi_mem_awqos_a[0];
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assign m_axi_mem_wvalid = m_axi_mem_wvalid_a[0];
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assign m_axi_mem_wready_a[0] = m_axi_mem_wready;
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assign m_axi_mem_wdata = m_axi_mem_wdata_a[0];
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assign m_axi_mem_wstrb = m_axi_mem_wstrb_a[0];
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assign m_axi_mem_wlast = m_axi_mem_wlast_a[0];
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assign m_axi_mem_arvalid = m_axi_mem_arvalid_a[0];
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assign m_axi_mem_arready_a[0] = m_axi_mem_arready;
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assign m_axi_mem_araddr = m_axi_mem_araddr_a[0];
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assign m_axi_mem_arid = m_axi_mem_arid_a[0];
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assign m_axi_mem_arlen = m_axi_mem_arlen_a[0];
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assign m_axi_mem_arsize = m_axi_mem_arsize_a[0];
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assign m_axi_mem_arburst = m_axi_mem_arburst_a[0];
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assign m_axi_mem_arlock = m_axi_mem_arlock_a[0];
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assign m_axi_mem_arcache = m_axi_mem_arcache_a[0];
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assign m_axi_mem_arprot = m_axi_mem_arprot_a[0];
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assign m_axi_mem_arqos = m_axi_mem_arqos_a[0];
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assign m_axi_mem_rvalid_a[0] = m_axi_mem_rvalid;
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assign m_axi_mem_rready = m_axi_mem_rready_a[0];
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assign m_axi_mem_rdata_a[0] = m_axi_mem_rdata;
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assign m_axi_mem_rlast_a[0] = m_axi_mem_rlast;
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assign m_axi_mem_rid_a[0] = m_axi_mem_rid;
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assign m_axi_mem_rresp_a[0] = m_axi_mem_rresp;
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assign m_axi_mem_bvalid_a[0] = m_axi_mem_bvalid;
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assign m_axi_mem_bready = m_axi_mem_bready_a[0];
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assign m_axi_mem_bresp_a[0] = m_axi_mem_bresp;
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assign m_axi_mem_bid_a[0] = m_axi_mem_bid;
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Vortex_axi #(
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.AXI_DATA_WIDTH (C_M_AXI_GMEM_DATA_WIDTH),
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.AXI_ADDR_WIDTH (C_M_AXI_GMEM_ADDR_WIDTH),
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.AXI_TID_WIDTH (C_M_AXI_GMEM_ID_WIDTH)
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) inst (
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.clk (clk),
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.reset (reset),
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.m_axi_awvalid (m_axi_mem_awvalid_a),
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.m_axi_awready (m_axi_mem_awready_a),
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.m_axi_awaddr (m_axi_mem_awaddr_a),
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.m_axi_awid (m_axi_mem_awid_a),
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.m_axi_awlen (m_axi_mem_awlen_a),
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.m_axi_awsize (m_axi_mem_awsize_a),
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.m_axi_awburst (m_axi_mem_awburst_a),
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.m_axi_awlock (m_axi_mem_awlock_a),
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.m_axi_awcache (m_axi_mem_awcache_a),
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.m_axi_awprot (m_axi_mem_awprot_a),
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.m_axi_awqos (m_axi_mem_awqos_a),
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.m_axi_wvalid (m_axi_mem_wvalid_a),
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.m_axi_wready (m_axi_mem_wready_a),
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.m_axi_wdata (m_axi_mem_wdata_a),
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.m_axi_wstrb (m_axi_mem_wstrb_a),
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.m_axi_wlast (m_axi_mem_wlast_a),
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.m_axi_bvalid (m_axi_mem_bvalid_a),
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.m_axi_bready (m_axi_mem_bready_a),
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.m_axi_bid (m_axi_mem_bid_a),
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.m_axi_bresp (m_axi_mem_bresp_a),
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.m_axi_arvalid (m_axi_mem_arvalid_a),
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.m_axi_arready (m_axi_mem_arready_a),
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.m_axi_araddr (m_axi_mem_araddr_a),
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.m_axi_arid (m_axi_mem_arid_a),
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.m_axi_arlen (m_axi_mem_arlen_a),
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.m_axi_arsize (m_axi_mem_arsize_a),
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.m_axi_arburst (m_axi_mem_arburst_a),
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.m_axi_arlock (m_axi_mem_arlock_a),
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.m_axi_arcache (m_axi_mem_arcache_a),
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.m_axi_arprot (m_axi_mem_arprot_a),
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.m_axi_arqos (m_axi_mem_arqos_a),
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.m_axi_rvalid (m_axi_mem_rvalid_a),
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.m_axi_rready (m_axi_mem_rready_a),
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.m_axi_rdata (m_axi_mem_rdata_a),
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.m_axi_rid (m_axi_mem_rid_a),
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.m_axi_rresp (m_axi_mem_rresp_a),
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.m_axi_rlast (m_axi_mem_rlast_a),
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.dcr_wr_valid (dcr_wr_valid),
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.dcr_wr_addr (dcr_wr_addr),
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.dcr_wr_data (dcr_wr_data),
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.busy (busy)
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);
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endmodule
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16386
hw/syn/xilinx/test/project_1_files/kernel.bin.coe
Normal file
16386
hw/syn/xilinx/test/project_1_files/kernel.bin.coe
Normal file
File diff suppressed because it is too large
Load Diff
119
hw/syn/xilinx/test/project_1_files/testbench.v
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119
hw/syn/xilinx/test/project_1_files/testbench.v
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@@ -0,0 +1,119 @@
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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`timescale 10ns / 1ns
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`define CYCLE_TIME 4
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module testbench;
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reg clk;
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reg resetn;
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reg [43:0] cycles;
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reg vx_running;
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reg vx_reset_wait;
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reg vx_busy_wait;
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wire vx_busy;
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reg dcr_wr_valid;
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reg [11:0] dcr_wr_addr;
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reg [31:0] dcr_wr_data;
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design_1_wrapper UUD(
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.clk_100MHz (clk),
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.resetn (resetn),
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.vx_reset (~resetn || ~vx_running),
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.dcr_wr_valid (dcr_wr_valid),
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.dcr_wr_addr (dcr_wr_addr),
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.dcr_wr_data (dcr_wr_data),
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.vx_busy (vx_busy)
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);
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always #(`CYCLE_TIME/2)
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clk = ~clk;
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initial begin
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clk = 1'b0;
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resetn = 1'b0;
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#4 resetn = 1'b1;
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end
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always @(posedge clk) begin
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if (~resetn) begin
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cycles <= 0;
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end else begin
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cycles <= cycles + 1;
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end
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end
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reg [7:0] vx_reset_ctr;
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always @(posedge clk) begin
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if (vx_reset_wait) begin
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vx_reset_ctr <= vx_reset_ctr + 1;
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end else begin
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vx_reset_ctr <= 0;
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end
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end
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always @(posedge clk) begin
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if (~resetn) begin
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vx_running <= 0;
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vx_reset_wait <= 0;
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vx_busy_wait <= 0;
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dcr_wr_valid <= 0;
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dcr_wr_addr <= 0;
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dcr_wr_data <= 0;
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end else begin
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case (cycles)
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1: begin
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dcr_wr_valid <= 1;
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dcr_wr_addr <= `VX_DCR_BASE_STARTUP_ADDR0;
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dcr_wr_data <= `STARTUP_ADDR;
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end
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2: begin
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dcr_wr_valid <= 0;
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dcr_wr_addr <= 0;
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dcr_wr_data <= 0;
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end
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3: begin
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vx_reset_wait <= 1;
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end
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default:;
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endcase
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if (vx_running) begin
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if (vx_busy_wait) begin
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if (vx_busy) begin
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vx_busy_wait <= 0;
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end
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end else begin
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if (~vx_busy) begin
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vx_running <= 0;
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$display("done!");
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$finish;
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end
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end
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end else begin
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if (vx_reset_wait && vx_reset_ctr == (`RESET_DELAY-1)) begin
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$display("start!");
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vx_reset_wait <= 0;
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vx_running <= 1;
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vx_busy_wait <= 1;
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end
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end
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end
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end
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endmodule
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