Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
This commit is contained in:
Blaise Tine
209
hw/rtl/mem/VX_mem_unit.sv
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209
hw/rtl/mem/VX_mem_unit.sv
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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`define SMEM_ADDR_STACK_OPT
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module VX_mem_unit import VX_gpu_pkg::*; #(
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parameter CLUSTER_ID = 0
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) (
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input wire clk,
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input wire reset,
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`ifdef PERF_ENABLE
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VX_mem_perf_if.master mem_perf_if,
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`endif
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VX_mem_bus_if.slave icache_bus_if [`NUM_SOCKETS],
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VX_mem_bus_if.slave dcache_bus_if [`NUM_SOCKETS * DCACHE_NUM_REQS],
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VX_mem_bus_if.master mem_bus_if
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);
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`ifdef PERF_ENABLE
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VX_cache_perf_if perf_icache_if();
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VX_cache_perf_if perf_dcache_if();
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VX_cache_perf_if perf_l2cache_if();
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`endif
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/////////////////////////////// I-Cache ///////////////////////////////////
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VX_mem_bus_if #(
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.DATA_SIZE (ICACHE_LINE_SIZE),
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.TAG_WIDTH (ICACHE_MEM_TAG_WIDTH)
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) icache_mem_bus_if();
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`RESET_RELAY (icache_reset, reset);
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VX_cache_cluster #(
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.INSTANCE_ID ($sformatf("cluster%0d-icache", CLUSTER_ID)),
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.NUM_UNITS (`NUM_ICACHES),
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.NUM_INPUTS (`NUM_SOCKETS),
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.TAG_SEL_IDX (0),
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.CACHE_SIZE (`ICACHE_SIZE),
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.LINE_SIZE (ICACHE_LINE_SIZE),
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.NUM_BANKS (1),
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.NUM_WAYS (`ICACHE_NUM_WAYS),
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.WORD_SIZE (ICACHE_WORD_SIZE),
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.NUM_REQS (1),
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.CRSQ_SIZE (`ICACHE_CRSQ_SIZE),
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.MSHR_SIZE (`ICACHE_MSHR_SIZE),
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.MRSQ_SIZE (`ICACHE_MRSQ_SIZE),
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.MREQ_SIZE (`ICACHE_MREQ_SIZE),
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.TAG_WIDTH (ICACHE_ARB_TAG_WIDTH),
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.UUID_WIDTH (`UUID_WIDTH),
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.WRITE_ENABLE (0),
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.CORE_OUT_REG (2),
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.MEM_OUT_REG (2)
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) icache (
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`ifdef PERF_ENABLE
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.cache_perf_if (perf_icache_if),
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`endif
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.clk (clk),
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.reset (icache_reset),
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.core_bus_if (icache_bus_if),
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.mem_bus_if (icache_mem_bus_if)
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);
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/////////////////////////////// D-Cache ///////////////////////////////////
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VX_mem_bus_if #(
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.DATA_SIZE (DCACHE_LINE_SIZE),
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.TAG_WIDTH (DCACHE_MEM_TAG_WIDTH)
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) dcache_mem_bus_if();
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`RESET_RELAY (dcache_reset, reset);
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VX_cache_cluster #(
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.INSTANCE_ID ($sformatf("cluster%0d-dcache", CLUSTER_ID)),
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.NUM_UNITS (`NUM_DCACHES),
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.NUM_INPUTS (`NUM_SOCKETS),
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.TAG_SEL_IDX (1),
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.CACHE_SIZE (`DCACHE_SIZE),
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.LINE_SIZE (DCACHE_LINE_SIZE),
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.NUM_BANKS (`DCACHE_NUM_BANKS),
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.NUM_WAYS (`DCACHE_NUM_WAYS),
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.WORD_SIZE (DCACHE_WORD_SIZE),
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.NUM_REQS (DCACHE_NUM_REQS),
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.CRSQ_SIZE (`DCACHE_CRSQ_SIZE),
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.MSHR_SIZE (`DCACHE_MSHR_SIZE),
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.MRSQ_SIZE (`DCACHE_MRSQ_SIZE),
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.MREQ_SIZE (`DCACHE_MREQ_SIZE),
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.TAG_WIDTH (DCACHE_ARB_TAG_WIDTH),
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.UUID_WIDTH (`UUID_WIDTH),
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.WRITE_ENABLE (1),
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.NC_ENABLE (1),
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.CORE_OUT_REG (`SM_ENABLED ? 2 : 1),
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.MEM_OUT_REG (2)
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) dcache (
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`ifdef PERF_ENABLE
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.cache_perf_if (perf_dcache_if),
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`endif
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.clk (clk),
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.reset (dcache_reset),
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.core_bus_if (dcache_bus_if),
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.mem_bus_if (dcache_mem_bus_if)
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);
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/////////////////////////////// L2-Cache //////////////////////////////////
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VX_mem_bus_if #(
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.DATA_SIZE (L2_WORD_SIZE),
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.TAG_WIDTH (L2_TAG_WIDTH)
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) l2_mem_bus_if[L2_NUM_REQS]();
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localparam I_MEM_ARB_IDX = 0;
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localparam D_MEM_ARB_IDX = I_MEM_ARB_IDX + 1;
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`ASSIGN_VX_MEM_BUS_IF_X (l2_mem_bus_if[I_MEM_ARB_IDX], icache_mem_bus_if, L1_MEM_TAG_WIDTH, ICACHE_MEM_TAG_WIDTH);
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`ASSIGN_VX_MEM_BUS_IF_X (l2_mem_bus_if[D_MEM_ARB_IDX], dcache_mem_bus_if, L1_MEM_TAG_WIDTH, DCACHE_MEM_TAG_WIDTH);
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`RESET_RELAY (l2_reset, reset);
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VX_cache_wrap #(
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.INSTANCE_ID ($sformatf("cluster%0d-l2cache", CLUSTER_ID)),
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.CACHE_SIZE (`L2_CACHE_SIZE),
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.LINE_SIZE (`L2_LINE_SIZE),
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.NUM_BANKS (`L2_NUM_BANKS),
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.NUM_WAYS (`L2_NUM_WAYS),
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.WORD_SIZE (L2_WORD_SIZE),
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.NUM_REQS (L2_NUM_REQS),
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.CRSQ_SIZE (`L2_CRSQ_SIZE),
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.MSHR_SIZE (`L2_MSHR_SIZE),
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.MRSQ_SIZE (`L2_MRSQ_SIZE),
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.MREQ_SIZE (`L2_MREQ_SIZE),
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.TAG_WIDTH (L1_MEM_TAG_WIDTH),
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.WRITE_ENABLE (1),
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.UUID_WIDTH (`UUID_WIDTH),
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.CORE_OUT_REG (2),
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.MEM_OUT_REG (2),
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.NC_ENABLE (1),
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.PASSTHRU (!`L2_ENABLED)
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) l2cache (
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.clk (clk),
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.reset (l2_reset),
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`ifdef PERF_ENABLE
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.cache_perf_if (perf_l2cache_if),
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`endif
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.core_bus_if (l2_mem_bus_if),
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.mem_bus_if (mem_bus_if)
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);
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`ifdef PERF_ENABLE
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`UNUSED_VAR (perf_dcache_if.mem_stalls)
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`UNUSED_VAR (perf_dcache_if.crsp_stalls)
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assign mem_perf_if.icache_reads = perf_icache_if.reads;
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assign mem_perf_if.icache_read_misses = perf_icache_if.read_misses;
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assign mem_perf_if.dcache_reads = perf_dcache_if.reads;
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assign mem_perf_if.dcache_writes = perf_dcache_if.writes;
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assign mem_perf_if.dcache_read_misses = perf_dcache_if.read_misses;
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assign mem_perf_if.dcache_write_misses= perf_dcache_if.write_misses;
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assign mem_perf_if.dcache_bank_stalls = perf_dcache_if.bank_stalls;
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assign mem_perf_if.dcache_mshr_stalls = perf_dcache_if.mshr_stalls;
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`ifdef L2_ENABLE
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assign mem_perf_if.l2cache_reads = perf_l2cache_if.reads;
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assign mem_perf_if.l2cache_writes = perf_l2cache_if.writes;
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assign mem_perf_if.l2cache_read_misses = perf_l2cache_if.read_misses;
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assign mem_perf_if.l2cache_write_misses= perf_l2cache_if.write_misses;
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assign mem_perf_if.l2cache_bank_stalls = perf_l2cache_if.bank_stalls;
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assign mem_perf_if.l2cache_mshr_stalls = perf_l2cache_if.mshr_stalls;
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`else
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assign mem_perf_if.l2cache_reads = '0;
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assign mem_perf_if.l2cache_writes = '0;
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assign mem_perf_if.l2cache_read_misses = '0;
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assign mem_perf_if.l2cache_write_misses= '0;
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assign mem_perf_if.l2cache_bank_stalls = '0;
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assign mem_perf_if.l2cache_mshr_stalls = '0;
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`endif
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assign mem_perf_if.l3cache_reads = '0;
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assign mem_perf_if.l3cache_writes = '0;
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assign mem_perf_if.l3cache_read_misses = '0;
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assign mem_perf_if.l3cache_write_misses= '0;
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assign mem_perf_if.l3cache_bank_stalls = '0;
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assign mem_perf_if.l3cache_mshr_stalls = '0;
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assign mem_perf_if.mem_reads = '0;
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assign mem_perf_if.mem_writes = '0;
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assign mem_perf_if.mem_latency = '0;
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`endif
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endmodule
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