Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
This commit is contained in:
Blaise Tine
164
hw/rtl/libs/VX_stream_switch.sv
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164
hw/rtl/libs/VX_stream_switch.sv
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_stream_switch #(
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parameter NUM_INPUTS = 1,
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parameter NUM_OUTPUTS = 1,
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parameter DATAW = 1,
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parameter OUT_REG = 0,
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parameter NUM_REQS = (NUM_INPUTS > NUM_OUTPUTS) ? ((NUM_INPUTS + NUM_OUTPUTS - 1) / NUM_OUTPUTS) : ((NUM_OUTPUTS + NUM_INPUTS - 1) / NUM_INPUTS),
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parameter SEL_COUNT = `MIN(NUM_INPUTS, NUM_OUTPUTS),
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parameter LOG_NUM_REQS = `CLOG2(NUM_REQS)
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) (
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input wire clk,
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input wire reset,
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input wire [SEL_COUNT-1:0][`UP(LOG_NUM_REQS)-1:0] sel_in,
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input wire [NUM_INPUTS-1:0] valid_in,
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input wire [NUM_INPUTS-1:0][DATAW-1:0] data_in,
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output wire [NUM_INPUTS-1:0] ready_in,
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output wire [NUM_OUTPUTS-1:0] valid_out,
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output wire [NUM_OUTPUTS-1:0][DATAW-1:0] data_out,
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input wire [NUM_OUTPUTS-1:0] ready_out
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);
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if (NUM_INPUTS > NUM_OUTPUTS) begin
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wire [NUM_OUTPUTS-1:0][NUM_REQS-1:0] valid_in_r;
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wire [NUM_OUTPUTS-1:0][NUM_REQS-1:0][DATAW-1:0] data_in_r;
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for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
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for (genvar j = 0; j < NUM_REQS; ++j) begin
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localparam ii = i * NUM_REQS + j;
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if (ii < NUM_INPUTS) begin
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assign valid_in_r[i][j] = valid_in[ii];
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assign data_in_r[i][j] = data_in[ii];
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end else begin
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assign valid_in_r[i][j] = 0;
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assign data_in_r[i][j] = '0;
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end
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end
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end
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wire [NUM_OUTPUTS-1:0] valid_out_r;
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wire [NUM_OUTPUTS-1:0][DATAW-1:0] data_out_r;
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wire [NUM_OUTPUTS-1:0] ready_out_r;
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for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
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assign valid_out_r[i] = valid_in_r[i][sel_in[i]];
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assign data_out_r[i] = data_in_r[i][sel_in[i]];
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end
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for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
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for (genvar j = 0; j < NUM_REQS; ++j) begin
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localparam ii = i * NUM_REQS + j;
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if (ii < NUM_INPUTS) begin
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assign ready_in[ii] = ready_out_r[i] & (sel_in[i] == LOG_NUM_REQS'(j));
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end
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end
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end
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for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
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`RESET_RELAY_EN (out_buf_reset, reset, (NUM_OUTPUTS > 1));
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VX_elastic_buffer #(
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.DATAW (DATAW),
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.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)),
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.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG))
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) out_buf (
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.clk (clk),
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.reset (out_buf_reset),
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.valid_in (valid_out_r[i]),
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.ready_in (ready_out_r[i]),
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.data_in (data_out_r[i]),
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.data_out (data_out[i]),
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.valid_out (valid_out[i]),
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.ready_out (ready_out[i])
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);
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end
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end else if (NUM_OUTPUTS > NUM_INPUTS) begin
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wire [NUM_INPUTS-1:0][NUM_REQS-1:0] valid_out_r;
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wire [NUM_INPUTS-1:0][NUM_REQS-1:0] ready_out_r;
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for (genvar i = 0; i < NUM_INPUTS; ++i) begin
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for (genvar j = 0; j < NUM_REQS; ++j) begin
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assign valid_out_r[i][j] = valid_in[i] & (sel_in[i] == LOG_NUM_REQS'(j));
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end
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assign ready_in[i] = ready_out_r[i][sel_in[i]];
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end
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for (genvar i = 0; i < NUM_INPUTS; ++i) begin
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for (genvar j = 0; j < NUM_REQS; ++j) begin
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localparam ii = i * NUM_REQS + j;
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if (ii < NUM_OUTPUTS) begin
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`RESET_RELAY (out_buf_reset, reset);
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VX_elastic_buffer #(
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.DATAW (DATAW),
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.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)),
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.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG))
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) out_buf (
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.clk (clk),
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.reset (out_buf_reset),
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.valid_in (valid_out_r[i][j]),
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.ready_in (ready_out_r[i][j]),
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.data_in (data_in[i]),
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.data_out (data_out[ii]),
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.valid_out (valid_out[ii]),
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.ready_out (ready_out[ii])
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);
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end else begin
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`UNUSED_VAR (valid_out_r[i][j])
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assign ready_out_r[i][j] = '0;
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end
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end
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end
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end else begin
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// #Inputs == #Outputs
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`UNUSED_VAR (sel_in)
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for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
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`RESET_RELAY_EN (out_buf_reset, reset, (NUM_OUTPUTS > 1));
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VX_elastic_buffer #(
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.DATAW (DATAW),
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.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)),
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.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG))
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) out_buf (
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.clk (clk),
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.reset (out_buf_reset),
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.valid_in (valid_in[i]),
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.ready_in (ready_in[i]),
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.data_in (data_in[i]),
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.data_out (data_out[i]),
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.valid_out (valid_out[i]),
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.ready_out (ready_out[i])
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);
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end
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end
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endmodule
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`TRACING_ON
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