Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
This commit is contained in:
Blaise Tine
@@ -1,252 +1,60 @@
|
||||
// Copyright © 2019-2023
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
`include "VX_platform.vh"
|
||||
|
||||
`TRACING_OFF
|
||||
module VX_sp_ram #(
|
||||
parameter DATAW = 1,
|
||||
parameter SIZE = 1,
|
||||
parameter BYTEENW = 1,
|
||||
parameter WRENW = 1,
|
||||
parameter OUT_REG = 0,
|
||||
parameter NO_RWCHECK = 0,
|
||||
parameter LUTRAM = 0,
|
||||
parameter ADDRW = $clog2(SIZE),
|
||||
parameter LUTRAM = 0,
|
||||
parameter INIT_ENABLE = 0,
|
||||
parameter INIT_FILE = "",
|
||||
parameter [DATAW-1:0] INIT_VALUE = 0
|
||||
parameter [DATAW-1:0] INIT_VALUE = 0,
|
||||
parameter ADDRW = `LOG2UP(SIZE)
|
||||
) (
|
||||
input wire clk,
|
||||
input wire clk,
|
||||
input wire read,
|
||||
input wire write,
|
||||
input wire [WRENW-1:0] wren,
|
||||
input wire [ADDRW-1:0] addr,
|
||||
input wire [BYTEENW-1:0] wren,
|
||||
input wire [DATAW-1:0] wdata,
|
||||
output wire [DATAW-1:0] rdata
|
||||
);
|
||||
|
||||
`STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter"))
|
||||
|
||||
`define RAM_INITIALIZATION \
|
||||
if (INIT_ENABLE) begin \
|
||||
if (INIT_FILE != "") begin \
|
||||
initial $readmemh(INIT_FILE, ram); \
|
||||
end else begin \
|
||||
initial \
|
||||
for (integer i = 0; i < SIZE; ++i)\
|
||||
ram[i] = INIT_VALUE; \
|
||||
end \
|
||||
end
|
||||
|
||||
`ifdef SYNTHESIS
|
||||
if (LUTRAM) begin
|
||||
if (OUT_REG) begin
|
||||
reg [DATAW-1:0] rdata_r;
|
||||
|
||||
if (BYTEENW > 1) begin
|
||||
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
|
||||
|
||||
`RAM_INITIALIZATION
|
||||
|
||||
always @(posedge clk) begin
|
||||
for (integer i = 0; i < BYTEENW; i++) begin
|
||||
if (wren[i])
|
||||
ram[addr][i] <= wdata[i * 8 +: 8];
|
||||
end
|
||||
rdata_r <= ram[addr];
|
||||
end
|
||||
end else begin
|
||||
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
|
||||
|
||||
`RAM_INITIALIZATION
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (wren)
|
||||
ram[addr] <= wdata;
|
||||
rdata_r <= ram[addr];
|
||||
end
|
||||
end
|
||||
assign rdata = rdata_r;
|
||||
end else begin
|
||||
if (BYTEENW > 1) begin
|
||||
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
|
||||
|
||||
`RAM_INITIALIZATION
|
||||
|
||||
always @(posedge clk) begin
|
||||
for (integer i = 0; i < BYTEENW; i++) begin
|
||||
if (wren[i])
|
||||
ram[addr][i] <= wdata[i * 8 +: 8];
|
||||
end
|
||||
end
|
||||
assign rdata = ram[addr];
|
||||
end else begin
|
||||
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
|
||||
|
||||
`RAM_INITIALIZATION
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (wren)
|
||||
ram[addr] <= wdata;
|
||||
end
|
||||
assign rdata = ram[addr];
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
if (OUT_REG) begin
|
||||
reg [DATAW-1:0] rdata_r;
|
||||
|
||||
if (BYTEENW > 1) begin
|
||||
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
|
||||
|
||||
`RAM_INITIALIZATION
|
||||
|
||||
always @(posedge clk) begin
|
||||
for (integer i = 0; i < BYTEENW; i++) begin
|
||||
if (wren[i])
|
||||
ram[addr][i] <= wdata[i * 8 +: 8];
|
||||
end
|
||||
rdata_r <= ram[addr];
|
||||
end
|
||||
end else begin
|
||||
reg [DATAW-1:0] ram [SIZE-1:0];
|
||||
|
||||
`RAM_INITIALIZATION
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (wren)
|
||||
ram[addr] <= wdata;
|
||||
rdata_r <= ram[addr];
|
||||
end
|
||||
end
|
||||
assign rdata = rdata_r;
|
||||
end else begin
|
||||
if (NO_RWCHECK) begin
|
||||
if (BYTEENW > 1) begin
|
||||
`NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
|
||||
|
||||
`RAM_INITIALIZATION
|
||||
|
||||
always @(posedge clk) begin
|
||||
for (integer i = 0; i < BYTEENW; i++) begin
|
||||
if (wren[i])
|
||||
ram[addr][i] <= wdata[i * 8 +: 8];
|
||||
end
|
||||
end
|
||||
assign rdata = ram[addr];
|
||||
end else begin
|
||||
`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0];
|
||||
|
||||
`RAM_INITIALIZATION
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (wren)
|
||||
ram[addr] <= wdata;
|
||||
end
|
||||
assign rdata = ram[addr];
|
||||
end
|
||||
end else begin
|
||||
if (BYTEENW > 1) begin
|
||||
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
|
||||
|
||||
`RAM_INITIALIZATION
|
||||
|
||||
always @(posedge clk) begin
|
||||
for (integer i = 0; i < BYTEENW; i++) begin
|
||||
if (wren[i])
|
||||
ram[addr][i] <= wdata[i * 8 +: 8];
|
||||
end
|
||||
end
|
||||
assign rdata = ram[addr];
|
||||
end else begin
|
||||
reg [DATAW-1:0] ram [SIZE-1:0];
|
||||
|
||||
`RAM_INITIALIZATION
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (wren)
|
||||
ram[addr] <= wdata;
|
||||
end
|
||||
assign rdata = ram[addr];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
`else
|
||||
if (OUT_REG) begin
|
||||
reg [DATAW-1:0] rdata_r;
|
||||
if (BYTEENW > 1) begin
|
||||
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
|
||||
|
||||
`RAM_INITIALIZATION
|
||||
|
||||
always @(posedge clk) begin
|
||||
for (integer i = 0; i < BYTEENW; i++) begin
|
||||
if (wren[i])
|
||||
ram[addr][i] <= wdata[i * 8 +: 8];
|
||||
end
|
||||
rdata_r <= ram[addr];
|
||||
end
|
||||
end else begin
|
||||
reg [DATAW-1:0] ram [SIZE-1:0];
|
||||
|
||||
`RAM_INITIALIZATION
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (wren)
|
||||
ram[addr] <= wdata;
|
||||
rdata_r <= ram[addr];
|
||||
end
|
||||
end
|
||||
assign rdata = rdata_r;
|
||||
end else begin
|
||||
if (BYTEENW > 1) begin
|
||||
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
|
||||
reg [DATAW-1:0] prev_data;
|
||||
reg [ADDRW-1:0] prev_addr;
|
||||
reg prev_write;
|
||||
|
||||
`RAM_INITIALIZATION
|
||||
|
||||
always @(posedge clk) begin
|
||||
for (integer i = 0; i < BYTEENW; i++) begin
|
||||
if (wren[i])
|
||||
ram[addr][i] <= wdata[i * 8 +: 8];
|
||||
end
|
||||
prev_write <= (| wren);
|
||||
prev_data <= ram[addr];
|
||||
prev_addr <= addr;
|
||||
end
|
||||
|
||||
if (LUTRAM || !NO_RWCHECK) begin
|
||||
`UNUSED_VAR (prev_write)
|
||||
`UNUSED_VAR (prev_data)
|
||||
`UNUSED_VAR (prev_addr)
|
||||
assign rdata = ram[addr];
|
||||
end else begin
|
||||
assign rdata = (prev_write && (prev_addr == addr)) ? prev_data : ram[addr];
|
||||
end
|
||||
end else begin
|
||||
reg [DATAW-1:0] ram [SIZE-1:0];
|
||||
reg [DATAW-1:0] prev_data;
|
||||
reg [ADDRW-1:0] prev_addr;
|
||||
reg prev_write;
|
||||
|
||||
`RAM_INITIALIZATION
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (wren)
|
||||
ram[addr] <= wdata;
|
||||
prev_write <= wren;
|
||||
prev_data <= ram[addr];
|
||||
prev_addr <= addr;
|
||||
end
|
||||
if (LUTRAM || !NO_RWCHECK) begin
|
||||
`UNUSED_VAR (prev_write)
|
||||
`UNUSED_VAR (prev_data)
|
||||
`UNUSED_VAR (prev_addr)
|
||||
assign rdata = ram[addr];
|
||||
end else begin
|
||||
assign rdata = (prev_write && (prev_addr == addr)) ? prev_data : ram[addr];
|
||||
end
|
||||
end
|
||||
end
|
||||
`endif
|
||||
VX_dp_ram #(
|
||||
.DATAW (DATAW),
|
||||
.SIZE (SIZE),
|
||||
.WRENW (WRENW),
|
||||
.OUT_REG (OUT_REG),
|
||||
.NO_RWCHECK (NO_RWCHECK),
|
||||
.LUTRAM (LUTRAM),
|
||||
.INIT_ENABLE (INIT_ENABLE),
|
||||
.INIT_FILE (INIT_FILE),
|
||||
.INIT_VALUE (INIT_VALUE),
|
||||
.ADDRW (ADDRW)
|
||||
) dp_ram (
|
||||
.clk (clk),
|
||||
.read (read),
|
||||
.write (write),
|
||||
.wren (wren),
|
||||
.waddr (addr),
|
||||
.wdata (wdata),
|
||||
.raddr (addr),
|
||||
.rdata (rdata)
|
||||
);
|
||||
|
||||
endmodule
|
||||
`TRACING_ON
|
||||
`TRACING_ON
|
||||
|
||||
Reference in New Issue
Block a user