Vortex 2.0 changes:

+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes

hw/rtl/libs/VX_pipe_register.sv

@@ -1,9 +1,22 @@
+// Copyright © 2019-2023
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+// 
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
 `include "VX_platform.vh"
 
 `TRACING_OFF
 module VX_pipe_register #( 
     parameter DATAW  = 1, 
-    parameter RESETW = DATAW, 
+    parameter RESETW = 0, 
     parameter DEPTH  = 1
 ) (
     input wire              clk,
@@ -12,7 +25,6 @@ module VX_pipe_register #(
     input wire [DATAW-1:0]  data_in,
     output wire [DATAW-1:0] data_out
 );
-
     if (DEPTH == 0) begin        
         `UNUSED_VAR (clk)
         `UNUSED_VAR (reset)
@@ -60,18 +72,22 @@ module VX_pipe_register #(
             assign data_out = {value_r, value_d};
         end
     end else begin
-        VX_shift_register #(
-            .DATAW  (DATAW),
-            .RESETW (RESETW),
-            .DEPTH  (DEPTH)
-        ) shift_reg (
-            .clk      (clk),
-            .reset    (reset),
-            .enable   (enable),
-            .data_in  (data_in),
-            .data_out (data_out)
-        );
+        wire [DEPTH:0][DATAW-1:0] data_delayed;        
+        assign data_delayed[0] = data_in;
+        for (genvar i = 1; i <= DEPTH; ++i) begin
+            VX_pipe_register #(
+                .DATAW  (DATAW),
+                .RESETW (RESETW)
+            ) pipe_reg (
+                .clk      (clk),
+                .reset    (reset),
+                .enable   (enable),
+                .data_in  (data_delayed[i-1]),
+                .data_out (data_delayed[i])
+            );
+        end
+        assign data_out = data_delayed[DEPTH];
     end
 
 endmodule
-`TRACING_ON
+`TRACING_ON