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Vortex 2.0 changes:

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+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
This commit is contained in:
Blaise Tine
2023-10-19 20:51:22 -07:00
parent d69a64c32c
commit d47cccc157
1300 changed files with 247321 additions and 311189 deletions
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81
hw/rtl/libs/VX_divider.sv
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@@ -1,27 +1,40 @@
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_platform.vh"
`TRACING_OFF
module VX_divider #(
parameter WIDTHN = 1,
parameter WIDTHD = 1,
parameter WIDTHQ = 1,
parameter WIDTHR = 1,
parameter NSIGNED = 0,
parameter DSIGNED = 0,
parameter LATENCY = 0
parameter N_WIDTH = 1,
parameter D_WIDTH = 1,
parameter Q_WIDTH = 1,
parameter R_WIDTH = 1,
parameter N_SIGNED = 0,
parameter D_SIGNED = 0,
parameter LATENCY = 0
) (
input wire clk,
input wire enable,
input wire [WIDTHN-1:0] numer,
input wire [WIDTHD-1:0] denom,
output wire [WIDTHQ-1:0] quotient,
output wire [WIDTHR-1:0] remainder
input wire clk,
input wire enable,
input wire [N_WIDTH-1:0] numer,
input wire [D_WIDTH-1:0] denom,
output wire [Q_WIDTH-1:0] quotient,
output wire [R_WIDTH-1:0] remainder
);
`ifdef QUARTUS
wire [WIDTHN-1:0] quotient_unqual;
wire [WIDTHD-1:0] remainder_unqual;
wire [N_WIDTH-1:0] quotient_unqual;
wire [D_WIDTH-1:0] remainder_unqual;
lpm_divide divide (
.clock (clk),
@@ -34,32 +47,32 @@ module VX_divider #(
defparam
divide.lpm_type = "LPM_DIVIDE",
divide.lpm_widthn = WIDTHN,
divide.lpm_widthd = WIDTHD,
divide.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED",
divide.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED",
divide.lpm_widthn = N_WIDTH,
divide.lpm_widthd = D_WIDTH,
divide.lpm_nrepresentation = N_SIGNED ? "SIGNED" : "UNSIGNED",
divide.lpm_drepresentation = D_SIGNED ? "SIGNED" : "UNSIGNED",
divide.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE",
divide.lpm_pipeline = LATENCY;
assign quotient = quotient_unqual [WIDTHQ-1:0];
assign remainder = remainder_unqual [WIDTHR-1:0];
assign quotient = quotient_unqual [Q_WIDTH-1:0];
assign remainder = remainder_unqual [R_WIDTH-1:0];
`else
reg [WIDTHN-1:0] quotient_unqual;
reg [WIDTHD-1:0] remainder_unqual;
reg [N_WIDTH-1:0] quotient_unqual;
reg [D_WIDTH-1:0] remainder_unqual;
always @(*) begin
begin
if (NSIGNED && DSIGNED) begin
if (N_SIGNED && D_SIGNED) begin
quotient_unqual = $signed(numer) / $signed(denom);
remainder_unqual = $signed(numer) % $signed(denom);
end
else if (NSIGNED && !DSIGNED) begin
else if (N_SIGNED && !D_SIGNED) begin
quotient_unqual = $signed(numer) / denom;
remainder_unqual = $signed(numer) % denom;
end
else if (!NSIGNED && DSIGNED) begin
else if (!N_SIGNED && D_SIGNED) begin
quotient_unqual = numer / $signed(denom);
remainder_unqual = numer % $signed(denom);
end
@@ -71,13 +84,13 @@ module VX_divider #(
end
if (LATENCY == 0) begin
assign quotient = quotient_unqual [WIDTHQ-1:0];
assign remainder = remainder_unqual [WIDTHR-1:0];
assign quotient = quotient_unqual [Q_WIDTH-1:0];
assign remainder = remainder_unqual [R_WIDTH-1:0];
end else begin
reg [WIDTHN-1:0] quotient_pipe [LATENCY-1:0];
reg [WIDTHD-1:0] remainder_pipe [LATENCY-1:0];
reg [N_WIDTH-1:0] quotient_pipe [LATENCY-1:0];
reg [D_WIDTH-1:0] remainder_pipe [LATENCY-1:0];
for (genvar i = 0; i < LATENCY; i++) begin
for (genvar i = 0; i < LATENCY; ++i) begin
always @(posedge clk) begin
if (enable) begin
quotient_pipe[i] <= (0 == i) ? quotient_unqual : quotient_pipe[i-1];
@@ -86,11 +99,11 @@ module VX_divider #(
end
end
assign quotient = quotient_pipe[LATENCY-1][WIDTHQ-1:0];
assign remainder = remainder_pipe[LATENCY-1][WIDTHR-1:0];
assign quotient = quotient_pipe[LATENCY-1][Q_WIDTH-1:0];
assign remainder = remainder_pipe[LATENCY-1][R_WIDTH-1:0];
end
`endif
endmodule
`TRACING_ON
`TRACING_ON