Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
This commit is contained in:
Blaise Tine
184
hw/rtl/core/VX_fetch.sv
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184
hw/rtl/core/VX_fetch.sv
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module VX_fetch import VX_gpu_pkg::*; #(
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parameter CORE_ID = 0
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) (
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`SCOPE_IO_DECL
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input wire clk,
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input wire reset,
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// Icache interface
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VX_mem_bus_if.master icache_bus_if,
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// inputs
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VX_schedule_if.slave schedule_if,
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// outputs
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VX_fetch_if.master fetch_if
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);
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`UNUSED_PARAM (CORE_ID)
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`UNUSED_VAR (reset)
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localparam ISW_WIDTH = `LOG2UP(`ISSUE_WIDTH);
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wire icache_req_valid;
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wire [ICACHE_ADDR_WIDTH-1:0] icache_req_addr;
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wire [ICACHE_TAG_WIDTH-1:0] icache_req_tag;
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wire icache_req_ready;
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wire [`UUID_WIDTH-1:0] rsp_uuid;
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wire [`NW_WIDTH-1:0] req_tag, rsp_tag;
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wire icache_req_fire = icache_req_valid && icache_req_ready;
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wire [ISW_WIDTH-1:0] schedule_isw = wid_to_isw(schedule_if.data.wid);
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assign req_tag = schedule_if.data.wid;
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assign {rsp_uuid, rsp_tag} = icache_bus_if.rsp_data.tag;
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wire [`XLEN-1:0] rsp_PC;
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wire [`NUM_THREADS-1:0] rsp_tmask;
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VX_dp_ram #(
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.DATAW (`XLEN + `NUM_THREADS),
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.SIZE (`NUM_WARPS),
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.LUTRAM (1)
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) tag_store (
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.clk (clk),
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.read (1'b1),
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.write (icache_req_fire),
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`UNUSED_PIN (wren),
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.waddr (req_tag),
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.wdata ({schedule_if.data.PC, schedule_if.data.tmask}),
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.raddr (rsp_tag),
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.rdata ({rsp_PC, rsp_tmask})
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);
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// Ensure that the ibuffer doesn't fill up.
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// This resolves potential deadlock if ibuffer fills and the LSU stalls the execute stage due to pending dcache request.
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// This issue is particularly prevalent when the icache and dcache is disabled and both requests share the same bus.
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wire [`ISSUE_WIDTH-1:0] pending_ibuf_full;
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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VX_pending_size #(
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.SIZE (`IBUF_SIZE)
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) pending_reads (
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.clk (clk),
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.reset (reset),
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.incr (icache_req_fire && schedule_isw == i),
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.decr (fetch_if.ibuf_pop[i]),
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.full (pending_ibuf_full[i]),
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`UNUSED_PIN (size),
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`UNUSED_PIN (empty)
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);
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end
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`RUNTIME_ASSERT((!schedule_if.valid || schedule_if.data.PC != 0),
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("%t: *** invalid PC=0x%0h, wid=%0d, tmask=%b (#%0d)", $time, schedule_if.data.PC, schedule_if.data.wid, schedule_if.data.tmask, schedule_if.data.uuid))
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// Icache Request
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wire ibuf_ready = ~pending_ibuf_full[schedule_isw];
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assign icache_req_valid = schedule_if.valid && ibuf_ready;
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assign icache_req_addr = schedule_if.data.PC[`MEM_ADDR_WIDTH-1:2];
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assign icache_req_tag = {schedule_if.data.uuid, req_tag};
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assign schedule_if.ready = icache_req_ready && ibuf_ready;
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VX_elastic_buffer #(
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.DATAW (ICACHE_ADDR_WIDTH + ICACHE_TAG_WIDTH),
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.SIZE (2),
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.OUT_REG (1) // external bus should be registered
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) req_buf (
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.clk (clk),
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.reset (reset),
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.valid_in (icache_req_valid),
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.ready_in (icache_req_ready),
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.data_in ({icache_req_addr, icache_req_tag}),
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.data_out ({icache_bus_if.req_data.addr, icache_bus_if.req_data.tag}),
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.valid_out (icache_bus_if.req_valid),
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.ready_out (icache_bus_if.req_ready)
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);
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assign icache_bus_if.req_data.rw = 0;
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assign icache_bus_if.req_data.byteen = 4'b1111;
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assign icache_bus_if.req_data.data = '0;
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// Icache Response
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assign fetch_if.valid = icache_bus_if.rsp_valid;
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assign fetch_if.data.tmask = rsp_tmask;
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assign fetch_if.data.wid = rsp_tag;
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assign fetch_if.data.PC = rsp_PC;
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assign fetch_if.data.instr = icache_bus_if.rsp_data.data;
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assign fetch_if.data.uuid = rsp_uuid;
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assign icache_bus_if.rsp_ready = fetch_if.ready;
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`ifdef DBG_SCOPE_FETCH
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if (CORE_ID == 0) begin
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`ifdef SCOPE
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wire schedule_fire = schedule_if.valid && schedule_if.ready;
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wire icache_rsp_fire = icache_bus_if.rsp_valid && icache_bus_if.rsp_ready;
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VX_scope_tap #(
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.SCOPE_ID (1),
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.TRIGGERW (4),
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.PROBEW (3*`UUID_WIDTH + 108)
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) scope_tap (
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.clk(clk),
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.reset(scope_reset),
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.start(1'b0),
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.stop(1'b0),
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.triggers({
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reset,
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schedule_fire,
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icache_req_fire,
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icache_rsp_fire
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}),
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.probes({
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schedule_if.data.uuid, schedule_if.data.wid, schedule_if.data.tmask, schedule_if.data.PC,
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icache_bus_if.req_data.tag, icache_bus_if.req_data.byteen, icache_bus_if.req_data.addr,
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icache_bus_if.rsp_data.data, icache_bus_if.rsp_data.tag
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}),
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.bus_in(scope_bus_in),
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.bus_out(scope_bus_out)
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);
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`endif
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`ifdef CHIPSCOPE
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ila_fetch ila_fetch_inst (
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.clk (clk),
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.probe0 ({reset, schedule_if.data.uuid, schedule_if.data.wid, schedule_if.data.tmask, schedule_if.data.PC, schedule_if.ready, schedule_if.valid}),
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.probe1 ({icache_bus_if.req_data.tag, icache_bus_if.req_data.byteen, icache_bus_if.req_data.addr, icache_bus_if.req_ready, icache_bus_if.req_valid}),
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.probe2 ({icache_bus_if.rsp_data.data, icache_bus_if.rsp_data.tag, icache_bus_if.rsp_ready, icache_bus_if.rsp_valid})
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);
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`endif
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end
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`else
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`SCOPE_IO_UNUSED()
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`endif
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`ifdef DBG_TRACE_CORE_ICACHE
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wire schedule_fire = schedule_if.valid && schedule_if.ready;
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wire fetch_fire = fetch_if.valid && fetch_if.ready;
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always @(posedge clk) begin
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if (schedule_fire) begin
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`TRACE(1, ("%d: I$%0d req: wid=%0d, PC=0x%0h, tmask=%b (#%0d)\n", $time, CORE_ID, schedule_if.data.wid, schedule_if.data.PC, schedule_if.data.tmask, schedule_if.data.uuid));
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end
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if (fetch_fire) begin
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`TRACE(1, ("%d: I$%0d rsp: wid=%0d, PC=0x%0h, tmask=%b, instr=0x%0h (#%0d)\n", $time, CORE_ID, fetch_if.data.wid, fetch_if.data.PC, fetch_if.data.tmask, fetch_if.data.instr, fetch_if.data.uuid));
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end
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end
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`endif
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endmodule
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