Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
This commit is contained in:
Blaise Tine
227
hw/rtl/core/VX_dispatch.sv
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227
hw/rtl/core/VX_dispatch.sv
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module VX_dispatch import VX_gpu_pkg::*; #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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`ifdef PERF_ENABLE
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output wire [`PERF_CTR_BITS-1:0] perf_stalls [`NUM_EX_UNITS],
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`endif
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// inputs
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VX_operands_if.slave operands_if [`ISSUE_WIDTH],
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// outputs
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VX_dispatch_if.master alu_dispatch_if [`ISSUE_WIDTH],
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VX_dispatch_if.master lsu_dispatch_if [`ISSUE_WIDTH],
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`ifdef EXT_F_ENABLE
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VX_dispatch_if.master fpu_dispatch_if [`ISSUE_WIDTH],
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`endif
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VX_dispatch_if.master sfu_dispatch_if [`ISSUE_WIDTH]
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);
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`UNUSED_PARAM (CORE_ID)
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localparam DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `INST_OP_BITS + `INST_MOD_BITS + 1 + 1 + 1 + `XLEN + `XLEN + `NR_BITS + (3 * `NUM_THREADS * `XLEN) + `NT_WIDTH;
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wire [`ISSUE_WIDTH-1:0][`NT_WIDTH-1:0] last_active_tid;
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wire [`NUM_THREADS-1:0][`NT_WIDTH-1:0] tids;
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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assign tids[i] = `NT_WIDTH'(i);
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end
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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VX_find_first #(
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.N (`NUM_THREADS),
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.DATAW (`NT_WIDTH),
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.REVERSE (1)
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) last_tid_select (
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.valid_in (operands_if[i].data.tmask),
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.data_in (tids),
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.data_out (last_active_tid[i]),
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`UNUSED_PIN (valid_out)
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);
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end
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// ALU dispatch
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VX_operands_if alu_operands_if[`ISSUE_WIDTH]();
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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assign alu_operands_if[i].valid = operands_if[i].valid && (operands_if[i].data.ex_type == `EX_ALU);
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assign alu_operands_if[i].data = operands_if[i].data;
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`RESET_RELAY (alu_reset, reset);
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VX_elastic_buffer #(
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.DATAW (DATAW),
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.SIZE (2),
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.OUT_REG (2)
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) alu_buffer (
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.clk (clk),
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.reset (alu_reset),
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.valid_in (alu_operands_if[i].valid),
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.ready_in (alu_operands_if[i].ready),
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.data_in (`TO_DISPATCH_DATA(alu_operands_if[i].data, last_active_tid[i])),
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.data_out (alu_dispatch_if[i].data),
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.valid_out (alu_dispatch_if[i].valid),
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.ready_out (alu_dispatch_if[i].ready)
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);
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end
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// LSU dispatch
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VX_operands_if lsu_operands_if[`ISSUE_WIDTH]();
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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assign lsu_operands_if[i].valid = operands_if[i].valid && (operands_if[i].data.ex_type == `EX_LSU);
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assign lsu_operands_if[i].data = operands_if[i].data;
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`RESET_RELAY (lsu_reset, reset);
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VX_elastic_buffer #(
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.DATAW (DATAW),
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.SIZE (2),
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.OUT_REG (2)
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) lsu_buffer (
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.clk (clk),
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.reset (lsu_reset),
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.valid_in (lsu_operands_if[i].valid),
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.ready_in (lsu_operands_if[i].ready),
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.data_in (`TO_DISPATCH_DATA(lsu_operands_if[i].data, last_active_tid[i])),
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.data_out (lsu_dispatch_if[i].data),
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.valid_out (lsu_dispatch_if[i].valid),
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.ready_out (lsu_dispatch_if[i].ready)
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);
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end
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// FPU dispatch
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`ifdef EXT_F_ENABLE
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VX_operands_if fpu_operands_if[`ISSUE_WIDTH]();
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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assign fpu_operands_if[i].valid = operands_if[i].valid && (operands_if[i].data.ex_type == `EX_FPU);
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assign fpu_operands_if[i].data = operands_if[i].data;
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`RESET_RELAY (fpu_reset, reset);
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VX_elastic_buffer #(
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.DATAW (DATAW),
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.SIZE (2),
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.OUT_REG (2)
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) fpu_buffer (
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.clk (clk),
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.reset (fpu_reset),
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.valid_in (fpu_operands_if[i].valid),
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.ready_in (fpu_operands_if[i].ready),
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.data_in (`TO_DISPATCH_DATA(fpu_operands_if[i].data, last_active_tid[i])),
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.data_out (fpu_dispatch_if[i].data),
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.valid_out (fpu_dispatch_if[i].valid),
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.ready_out (fpu_dispatch_if[i].ready)
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);
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end
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`endif
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// SFU dispatch
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VX_operands_if sfu_operands_if[`ISSUE_WIDTH]();
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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assign sfu_operands_if[i].valid = operands_if[i].valid && (operands_if[i].data.ex_type == `EX_SFU);
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assign sfu_operands_if[i].data = operands_if[i].data;
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`RESET_RELAY (sfu_reset, reset);
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VX_elastic_buffer #(
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.DATAW (DATAW),
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.SIZE (2),
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.OUT_REG (2)
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) sfu_buffer (
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.clk (clk),
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.reset (sfu_reset),
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.valid_in (sfu_operands_if[i].valid),
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.ready_in (sfu_operands_if[i].ready),
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.data_in (`TO_DISPATCH_DATA(sfu_operands_if[i].data, last_active_tid[i])),
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.data_out (sfu_dispatch_if[i].data),
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.valid_out (sfu_dispatch_if[i].valid),
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.ready_out (sfu_dispatch_if[i].ready)
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);
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end
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// can take next request?
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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assign operands_if[i].ready = (alu_operands_if[i].ready && (operands_if[i].data.ex_type == `EX_ALU))
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|| (lsu_operands_if[i].ready && (operands_if[i].data.ex_type == `EX_LSU))
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`ifdef EXT_F_ENABLE
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|| (fpu_operands_if[i].ready && (operands_if[i].data.ex_type == `EX_FPU))
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`endif
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|| (sfu_operands_if[i].ready && (operands_if[i].data.ex_type == `EX_SFU));
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end
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`ifdef PERF_ENABLE
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reg [`NUM_EX_UNITS-1:0][`PERF_CTR_BITS-1:0] perf_stalls_n, perf_stalls_r;
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wire [`ISSUE_WIDTH-1:0] operands_stall;
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wire [`ISSUE_WIDTH-1:0][`EX_BITS-1:0] operands_ex_type;
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for (genvar i=0; i < `ISSUE_WIDTH; ++i) begin
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assign operands_stall[i] = operands_if[i].valid && ~operands_if[i].ready;
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assign operands_ex_type[i] = operands_if[i].data.ex_type;
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end
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always @(*) begin
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perf_stalls_n = perf_stalls_r;
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for (integer i=0; i < `ISSUE_WIDTH; ++i) begin
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if (operands_stall[i]) begin
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perf_stalls_n[operands_ex_type[i]] += `PERF_CTR_BITS'(1);
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end
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end
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end
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always @(posedge clk) begin
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if (reset) begin
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perf_stalls_r <= '0;
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end else begin
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perf_stalls_r <= perf_stalls_n;
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end
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end
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for (genvar i=0; i < `NUM_EX_UNITS; ++i) begin
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assign perf_stalls[i] = perf_stalls_r[i];
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end
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`endif
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`ifdef DBG_TRACE_CORE_PIPELINE
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for (genvar i=0; i < `ISSUE_WIDTH; ++i) begin
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always @(posedge clk) begin
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if (operands_if[i].valid && operands_if[i].ready) begin
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`TRACE(1, ("%d: core%0d-issue: wid=%0d, PC=0x%0h, ex=", $time, CORE_ID, wis_to_wid(operands_if[i].data.wis, i), operands_if[i].data.PC));
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trace_ex_type(1, operands_if[i].data.ex_type);
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`TRACE(1, (", mod=%0d, tmask=%b, wb=%b, rd=%0d, rs1_data=", operands_if[i].data.op_mod, operands_if[i].data.tmask, operands_if[i].data.wb, operands_if[i].data.rd));
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`TRACE_ARRAY1D(1, operands_if[i].data.rs1_data, `NUM_THREADS);
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`TRACE(1, (", rs2_data="));
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`TRACE_ARRAY1D(1, operands_if[i].data.rs2_data, `NUM_THREADS);
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`TRACE(1, (", rs3_data="));
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`TRACE_ARRAY1D(1, operands_if[i].data.rs3_data, `NUM_THREADS);
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`TRACE(1, (" (#%0d)\n", operands_if[i].data.uuid));
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end
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end
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end
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`endif
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endmodule
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