Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
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Blaise Tine
172
hw/rtl/core/VX_alu_unit.sv
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172
hw/rtl/core/VX_alu_unit.sv
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module VX_alu_unit #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// Inputs
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VX_dispatch_if.slave dispatch_if [`ISSUE_WIDTH],
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// Outputs
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VX_commit_if.master commit_if [`ISSUE_WIDTH],
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VX_branch_ctl_if.master branch_ctl_if [`NUM_ALU_BLOCKS]
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);
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`UNUSED_PARAM (CORE_ID)
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localparam BLOCK_SIZE = `NUM_ALU_BLOCKS;
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localparam NUM_LANES = `NUM_ALU_LANES;
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localparam PID_BITS = `CLOG2(`NUM_THREADS / NUM_LANES);
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localparam PID_WIDTH = `UP(PID_BITS);
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localparam RSP_ARB_DATAW= `UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + `NR_BITS + 1 + NUM_LANES * `XLEN + PID_WIDTH + 1 + 1;
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localparam RSP_ARB_SIZE = 1 + `EXT_M_ENABLED;
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localparam PARTIAL_BW = (BLOCK_SIZE != `ISSUE_WIDTH) || (NUM_LANES != `NUM_THREADS);
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VX_execute_if #(
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.NUM_LANES (NUM_LANES)
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) execute_if[BLOCK_SIZE]();
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`RESET_RELAY (dispatch_reset, reset);
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VX_dispatch_unit #(
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.BLOCK_SIZE (BLOCK_SIZE),
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.NUM_LANES (NUM_LANES),
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.OUT_REG (PARTIAL_BW ? 1 : 0)
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) dispatch_unit (
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.clk (clk),
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.reset (dispatch_reset),
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.dispatch_if(dispatch_if),
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.execute_if (execute_if)
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);
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VX_commit_if #(
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.NUM_LANES (NUM_LANES)
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) commit_block_if[BLOCK_SIZE]();
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for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin
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wire is_muldiv_op;
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VX_execute_if #(
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.NUM_LANES (NUM_LANES)
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) int_execute_if();
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assign int_execute_if.valid = execute_if[block_idx].valid && ~is_muldiv_op;
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assign int_execute_if.data = execute_if[block_idx].data;
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VX_commit_if #(
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.NUM_LANES (NUM_LANES)
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) int_commit_if();
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`RESET_RELAY (int_reset, reset);
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VX_int_unit #(
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.CORE_ID (CORE_ID),
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.BLOCK_IDX (block_idx),
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.NUM_LANES (NUM_LANES)
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) int_unit (
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.clk (clk),
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.reset (int_reset),
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.execute_if (int_execute_if),
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.branch_ctl_if (branch_ctl_if[block_idx]),
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.commit_if (int_commit_if)
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);
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`ifdef EXT_M_ENABLE
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assign is_muldiv_op = `INST_ALU_IS_M(execute_if[block_idx].data.op_mod);
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`RESET_RELAY (mdv_reset, reset);
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VX_execute_if #(
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.NUM_LANES (NUM_LANES)
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) mdv_execute_if();
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assign mdv_execute_if.valid = execute_if[block_idx].valid && is_muldiv_op;
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assign mdv_execute_if.data = execute_if[block_idx].data;
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VX_commit_if #(
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.NUM_LANES (NUM_LANES)
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) mdv_commit_if();
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VX_muldiv_unit #(
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.CORE_ID (CORE_ID),
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.NUM_LANES (NUM_LANES)
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) mdv_unit (
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.clk (clk),
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.reset (mdv_reset),
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.execute_if (mdv_execute_if),
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.commit_if (mdv_commit_if)
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);
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assign execute_if[block_idx].ready = is_muldiv_op ? mdv_execute_if.ready : int_execute_if.ready;
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`else
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assign is_muldiv_op = 0;
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assign execute_if[block_idx].ready = int_execute_if.ready;
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`endif
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// send response
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VX_stream_arb #(
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.NUM_INPUTS (RSP_ARB_SIZE),
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.DATAW (RSP_ARB_DATAW),
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.OUT_REG (PARTIAL_BW ? 1 : 3)
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) rsp_arb (
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.clk (clk),
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.reset (reset),
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.valid_in ({
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`ifdef EXT_M_ENABLE
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mdv_commit_if.valid,
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`endif
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int_commit_if.valid
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}),
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.ready_in ({
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`ifdef EXT_M_ENABLE
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mdv_commit_if.ready,
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`endif
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int_commit_if.ready
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}),
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.data_in ({
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`ifdef EXT_M_ENABLE
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mdv_commit_if.data,
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`endif
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int_commit_if.data
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}),
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.data_out (commit_block_if[block_idx].data),
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.valid_out (commit_block_if[block_idx].valid),
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.ready_out (commit_block_if[block_idx].ready),
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`UNUSED_PIN (sel_out)
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);
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end
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`RESET_RELAY (commit_reset, reset);
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VX_gather_unit #(
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.BLOCK_SIZE (BLOCK_SIZE),
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.NUM_LANES (NUM_LANES),
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.OUT_REG (PARTIAL_BW ? 3 : 0)
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) gather_unit (
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.clk (clk),
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.reset (commit_reset),
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.commit_in_if (commit_block_if),
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.commit_out_if (commit_if)
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);
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endmodule
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