Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
This commit is contained in:
Blaise Tine
419
hw/rtl/afu/xrt/VX_afu_ctrl.sv
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419
hw/rtl/afu/xrt/VX_afu_ctrl.sv
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "vortex_afu.vh"
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module VX_afu_ctrl #(
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parameter AXI_ADDR_WIDTH = 8,
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parameter AXI_DATA_WIDTH = 32,
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parameter AXI_NUM_BANKS = 1
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) (
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// axi4 lite slave signals
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input wire clk,
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input wire reset,
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input wire clk_en,
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input wire s_axi_awvalid,
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input wire [AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
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output wire s_axi_awready,
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input wire s_axi_wvalid,
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input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata,
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input wire [AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
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output wire s_axi_wready,
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output wire s_axi_bvalid,
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output wire [1:0] s_axi_bresp,
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input wire s_axi_bready,
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input wire s_axi_arvalid,
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input wire [AXI_ADDR_WIDTH-1:0] s_axi_araddr,
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output wire s_axi_arready,
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output wire s_axi_rvalid,
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output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata,
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output wire [1:0] s_axi_rresp,
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input wire s_axi_rready,
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output wire ap_reset,
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output wire ap_start,
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input wire ap_done,
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input wire ap_ready,
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input wire ap_idle,
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output wire interrupt,
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`ifdef SCOPE
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input wire scope_bus_in,
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output wire scope_bus_out,
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`endif
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output wire [63:0] mem_base [AXI_NUM_BANKS],
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output wire dcr_wr_valid,
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output wire [`VX_DCR_ADDR_WIDTH-1:0] dcr_wr_addr,
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output wire [`VX_DCR_DATA_WIDTH-1:0] dcr_wr_data
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);
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// Address Info
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// 0x00 : Control signals
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// bit 0 - ap_start (Read/Write/COH)
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// bit 1 - ap_done (Read/COR)
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// bit 2 - ap_idle (Read)
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// bit 3 - ap_ready (Read)
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// bit 4 - ap_reset (Write)
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// bit 7 - auto_restart (Read/Write)
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// others - reserved
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// 0x04 : Global Interrupt Enable Register
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// bit 0 - Global Interrupt Enable (Read/Write)
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// others - reserved
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// 0x08 : IP Interrupt Enable Register (Read/Write)
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// bit 0 - Channel 0 (ap_done)
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// bit 1 - Channel 1 (ap_ready)
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// others - reserved
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// 0x0c : IP Interrupt Status Register (Read/TOW)
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// bit 0 - Channel 0 (ap_done)
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// bit 1 - Channel 1 (ap_ready)
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// others - reserved
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// 0x10 : Low 32-bit Data signal of DEV_CAPS
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// 0x14 : High 32-bit Data signal of DEV_CAPS
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// 0x18 : Control signal of DEV_CAPS
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// 0x1C : Low 32-bit Data signal of ISA_CAPS
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// 0x20 : High 32-bit Data signal of ISA_CAPS
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// 0x24 : Control signal of ISA_CAPS
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// 0x28 : Low 32-bit Data signal of DCR
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// 0x2C : High 32-bit Data signal of DCR
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// 0x30 : Control signal of DCR
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// 0x34 : Low 32-bit Data signal of SCP
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// 0x38 : High 32-bit Data signal of SCP
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// 0x3C : Control signal of SCP
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// 0x40 : Low 32-bit Data signal of MEM
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// 0x44 : High 32-bit Data signal of MEM
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// 0x48 : Control signal of MEM
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// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
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// Parameters
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localparam
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ADDR_AP_CTRL = 8'h00,
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ADDR_GIE = 8'h04,
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ADDR_IER = 8'h08,
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ADDR_ISR = 8'h0C,
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ADDR_DEV_0 = 8'h10,
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ADDR_DEV_1 = 8'h14,
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ADDR_DEV_CTRL = 8'h18,
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ADDR_ISA_0 = 8'h1C,
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ADDR_ISA_1 = 8'h20,
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ADDR_ISA_CTRL = 8'h24,
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ADDR_DCR_0 = 8'h28,
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ADDR_DCR_1 = 8'h2C,
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ADDR_DCR_CTRL = 8'h30,
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ADDR_SCP_0 = 8'h34,
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ADDR_SCP_1 = 8'h38,
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ADDR_SCP_CTRL = 8'h3C,
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ADDR_MEM_0 = 8'h40,
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ADDR_MEM_1 = 8'h44,
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ADDR_MEM_CTRL = 8'h48,
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ADDR_BITS = 8;
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localparam
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WSTATE_IDLE = 2'd0,
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WSTATE_DATA = 2'd1,
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WSTATE_RESP = 2'd2;
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localparam
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RSTATE_IDLE = 2'd0,
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RSTATE_DATA = 2'd1;
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// device caps
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wire [63:0] dev_caps = {16'b0,
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8'(`SM_ENABLED ? `SMEM_LOG_SIZE : 0),
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16'(`NUM_CORES * `NUM_CLUSTERS),
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8'(`NUM_WARPS),
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8'(`NUM_THREADS),
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8'(`IMPLEMENTATION_ID)};
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wire [63:0] isa_caps = {32'(`MISA_EXT),
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2'(`CLOG2(`XLEN)-4),
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30'(`MISA_STD)};
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reg [1:0] wstate;
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reg [ADDR_BITS-1:0] waddr;
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wire [31:0] wmask;
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wire s_axi_aw_fire;
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wire s_axi_w_fire;
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reg [1:0] rstate;
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reg [31:0] rdata;
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wire [ADDR_BITS-1:0] raddr;
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wire s_axi_ar_fire;
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reg ap_reset_r;
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reg ap_start_r;
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reg auto_restart_r;
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reg gie_r;
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reg [1:0] ier_r;
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reg [1:0] isr_r;
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reg [63:0] mem_r [AXI_NUM_BANKS];
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reg [31:0] dcra_r;
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reg [31:0] dcrv_r;
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reg dcr_wr_valid_r;
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`ifdef SCOPE
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reg [63:0] scope_bus_wdata;
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reg [63:0] scope_bus_rdata;
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reg [5:0] scope_bus_ctr;
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reg cmd_scope_reading;
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reg cmd_scope_writing;
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reg scope_bus_out_r;
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always @(posedge clk) begin
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if (reset) begin
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cmd_scope_reading <= 0;
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cmd_scope_writing <= 0;
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scope_bus_ctr <= '0;
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scope_bus_out_r <= 0;
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end else if (clk_en) begin
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if (s_axi_w_fire && waddr == ADDR_SCP_0) begin
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scope_bus_wdata[31:0] <= (s_axi_wdata & wmask) | (scope_bus_wdata[31:0] & ~wmask);
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end
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if (s_axi_w_fire && waddr == ADDR_SCP_1) begin
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scope_bus_wdata[63:32] <= (s_axi_wdata & wmask) | (scope_bus_wdata[63:32] & ~wmask);
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cmd_scope_writing <= 1;
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scope_bus_out_r <= 1;
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scope_bus_ctr <= 63;
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end
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if (scope_bus_in) begin
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cmd_scope_reading <= 1;
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scope_bus_ctr <= 63;
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end
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if (cmd_scope_reading) begin
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scope_bus_rdata <= {scope_bus_rdata[62:0], scope_bus_in};
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scope_bus_ctr <= scope_bus_ctr - 1;
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if (scope_bus_ctr == 0) begin
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cmd_scope_reading <= 0;
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end
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end
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if (cmd_scope_writing) begin
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scope_bus_out_r <= 1'(scope_bus_wdata >> scope_bus_ctr);
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scope_bus_ctr <= scope_bus_ctr - 1;
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if (scope_bus_ctr == 0) begin
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cmd_scope_writing <= 0;
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end
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end
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end
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end
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assign scope_bus_out = scope_bus_out_r;
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`endif
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// AXI Write
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assign s_axi_awready = (wstate == WSTATE_IDLE);
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assign s_axi_wready = (wstate == WSTATE_DATA);
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assign s_axi_bvalid = (wstate == WSTATE_RESP);
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assign s_axi_bresp = 2'b00; // OKAY
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assign s_axi_aw_fire = s_axi_awvalid && s_axi_awready;
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assign s_axi_w_fire = s_axi_wvalid && s_axi_wready;
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for (genvar i = 0; i < 4; ++i) begin
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assign wmask[8 * i +: 8] = {8{s_axi_wstrb[i]}};
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end
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// wstate
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always @(posedge clk) begin
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if (reset) begin
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wstate <= WSTATE_IDLE;
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end else if (clk_en) begin
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case (wstate)
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WSTATE_IDLE: wstate <= s_axi_awvalid ? WSTATE_DATA : WSTATE_IDLE;
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WSTATE_DATA: wstate <= s_axi_wvalid ? WSTATE_RESP : WSTATE_DATA;
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WSTATE_RESP: wstate <= s_axi_bready ? WSTATE_IDLE : WSTATE_RESP;
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default: wstate <= WSTATE_IDLE;
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endcase
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end
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end
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// waddr
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always @(posedge clk) begin
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if (clk_en) begin
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if (s_axi_aw_fire)
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waddr <= s_axi_awaddr[ADDR_BITS-1:0];
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end
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end
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// wdata
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always @(posedge clk) begin
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if (reset) begin
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ap_start_r <= 0;
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ap_reset_r <= 0;
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auto_restart_r <= 0;
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gie_r <= 0;
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ier_r <= '0;
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isr_r <= '0;
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dcra_r <= '0;
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dcrv_r <= '0;
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dcr_wr_valid_r <= 0;
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for (integer i = 0; i < AXI_NUM_BANKS; ++i) begin
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mem_r[i] <= '0;
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end
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end else if (clk_en) begin
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if (ap_ready)
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ap_start_r <= auto_restart_r;
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dcr_wr_valid_r <= 0;
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if (s_axi_w_fire) begin
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case (waddr)
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ADDR_AP_CTRL: begin
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if (s_axi_wstrb[0]) begin
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if (s_axi_wdata[0])
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ap_start_r <= 1;
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if (s_axi_wdata[4])
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ap_reset_r <= 1;
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if (s_axi_wdata[7])
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auto_restart_r <= 1;
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end
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end
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ADDR_GIE: begin
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if (s_axi_wstrb[0])
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gie_r <= s_axi_wdata[0];
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end
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ADDR_IER: begin
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if (s_axi_wstrb[0])
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ier_r <= s_axi_wdata[1:0];
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end
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ADDR_ISR: begin
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if (s_axi_wstrb[0])
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isr_r <= isr_r ^ s_axi_wdata[1:0];
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end
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ADDR_DCR_0: begin
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dcra_r <= (s_axi_wdata & wmask) | (dcra_r & ~wmask);
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end
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ADDR_DCR_1: begin
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dcrv_r <= (s_axi_wdata & wmask) | (dcrv_r & ~wmask);
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dcr_wr_valid_r <= 1;
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end
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default: begin
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for (integer i = 0; i < AXI_NUM_BANKS; ++i) begin
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if (waddr == (ADDR_MEM_0 + i * 12)) begin
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mem_r[i][31:0] <= (s_axi_wdata & wmask) | (mem_r[i][31:0] & ~wmask);
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end
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if (waddr == (ADDR_MEM_1 + i * 12)) begin
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mem_r[i][63:32] <= (s_axi_wdata & wmask) | (mem_r[i][63:32] & ~wmask);
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end
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end
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end
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endcase
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if (ier_r[0] & ap_done)
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isr_r[0] <= 1'b1;
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if (ier_r[1] & ap_ready)
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isr_r[1] <= 1'b1;
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end
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end
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end
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// AXI Read
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assign s_axi_arready = (rstate == RSTATE_IDLE);
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assign s_axi_rvalid = (rstate == RSTATE_DATA);
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assign s_axi_rdata = rdata;
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assign s_axi_rresp = 2'b00; // OKAY
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assign s_axi_ar_fire = s_axi_arvalid && s_axi_arready;
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assign raddr = s_axi_araddr[ADDR_BITS-1:0];
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// rstate
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always @(posedge clk) begin
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if (reset) begin
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rstate <= RSTATE_IDLE;
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end else if (clk_en) begin
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case (rstate)
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RSTATE_IDLE: rstate <= s_axi_arvalid ? RSTATE_DATA : RSTATE_IDLE;
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RSTATE_DATA: rstate <= (s_axi_rready & s_axi_rvalid) ? RSTATE_IDLE : RSTATE_DATA;
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default: rstate <= RSTATE_IDLE;
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endcase
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end
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end
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// rdata
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always @(posedge clk) begin
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if (clk_en) begin
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if (s_axi_ar_fire) begin
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rdata <= '0;
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case (raddr)
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ADDR_AP_CTRL: begin
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rdata[0] <= ap_start_r;
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rdata[1] <= ap_done;
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rdata[2] <= ap_idle;
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rdata[3] <= ap_ready;
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rdata[7] <= auto_restart_r;
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end
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ADDR_GIE: begin
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rdata <= 32'(gie_r);
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end
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ADDR_IER: begin
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rdata <= 32'(ier_r);
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end
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ADDR_ISR: begin
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rdata <= 32'(isr_r);
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end
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ADDR_DEV_0: begin
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rdata <= dev_caps[31:0];
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end
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ADDR_DEV_1: begin
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rdata <= dev_caps[63:32];
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end
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ADDR_ISA_0: begin
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rdata <= isa_caps[31:0];
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end
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ADDR_ISA_1: begin
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rdata <= isa_caps[63:32];
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end
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`ifdef SCOPE
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ADDR_SCP_0: begin
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rdata <= scope_bus_rdata[31:0];
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end
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ADDR_SCP_1: begin
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rdata <= scope_bus_rdata[63:32];
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end
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`endif
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default:;
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endcase
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end
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end
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end
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assign ap_reset = ap_reset_r;
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assign ap_start = ap_start_r;
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assign interrupt = gie_r & (| isr_r);
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assign mem_base = mem_r;
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assign dcr_wr_valid = dcr_wr_valid_r;
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assign dcr_wr_addr = `VX_DCR_ADDR_WIDTH'(dcra_r);
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assign dcr_wr_data = `VX_DCR_DATA_WIDTH'(dcrv_r);
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endmodule
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