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Vortex 2.0 changes:

Browse Source 
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
This commit is contained in:
Blaise Tine
2023-10-19 20:51:22 -07:00
parent d69a64c32c
commit d47cccc157
1300 changed files with 247321 additions and 311189 deletions
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244
hw/rtl/afu/opae/ccip/ccip_if_pkg.sv Normal file
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// Date: 02/2/2016
// Compliant with CCI-P spec v0.71
package ccip_if_pkg;
//=====================================================================
// CCI-P interface defines
//=====================================================================
parameter CCIP_VERSION_NUMBER = 12'h071;
parameter CCIP_CLADDR_WIDTH = 42;
parameter CCIP_CLDATA_WIDTH = 512;
parameter CCIP_MMIOADDR_WIDTH = 16;
parameter CCIP_MMIODATA_WIDTH = 64;
parameter CCIP_TID_WIDTH = 9;
parameter CCIP_MDATA_WIDTH = 16;
// Number of requests that can be accepted after almost full is asserted.
parameter CCIP_TX_ALMOST_FULL_THRESHOLD = 8;
parameter CCIP_MMIO_RD_TIMEOUT = 512;
parameter CCIP_SYNC_RESET_POLARITY=1; // Active High Reset
// Base types
//----------------------------------------------------------------------
typedef logic [CCIP_CLADDR_WIDTH-1:0] t_ccip_clAddr;
typedef logic [CCIP_CLDATA_WIDTH-1:0] t_ccip_clData;
typedef logic [CCIP_MMIOADDR_WIDTH-1:0] t_ccip_mmioAddr;
typedef logic [CCIP_MMIODATA_WIDTH-1:0] t_ccip_mmioData;
typedef logic [CCIP_TID_WIDTH-1:0] t_ccip_tid;
typedef logic [CCIP_MDATA_WIDTH-1:0] t_ccip_mdata;
typedef logic [1:0] t_ccip_clNum;
typedef logic [2:0] t_ccip_qwIdx;
// Request Type Encodings
//----------------------------------------------------------------------
// Channel 0
typedef enum logic [3:0] {
eREQ_RDLINE_I = 4'h0, // Memory Read with FPGA Cache Hint=Invalid
eREQ_RDLINE_S = 4'h1 // Memory Read with FPGA Cache Hint=Shared
} t_ccip_c0_req;
// Channel 1
typedef enum logic [3:0] {
eREQ_WRLINE_I = 4'h0, // Memory Write with FPGA Cache Hint=Invalid
eREQ_WRLINE_M = 4'h1, // Memory Write with FPGA Cache Hint=Modified
eREQ_WRPUSH_I = 4'h2, // Memory Write with DDIO Hint ** NOT SUPPORTED CURRENTLY **
eREQ_WRFENCE = 4'h4, // Memory Write Fence
// eREQ_ATOMIC = 4'h5, // Atomic operation: Compare-Exchange for Memory Addr ** NOT SUPPORTED CURRENTELY **
eREQ_INTR = 4'h6 // Interrupt the CPU ** NOT SUPPORTED CURRENTLY **
} t_ccip_c1_req;
// Response Type Encodings
//----------------------------------------------------------------------
// Channel 0
typedef enum logic [3:0] {
eRSP_RDLINE = 4'h0, // Memory Read
eRSP_UMSG = 4'h4 // UMsg received
// eRSP_ATOMIC = 4'h5 // Atomic Operation: Compare-Exchange for Memory Addr
} t_ccip_c0_rsp;
// Channel 1
typedef enum logic [3:0] {
eRSP_WRLINE = 4'h0, // Memory Write
eRSP_WRFENCE = 4'h4, // Memory Write Fence
eRSP_INTR = 4'h6 // Interrupt delivered to the CPU ** NOT SUPPORTED CURRENTLY **
} t_ccip_c1_rsp;
//
// Virtual Channel Select
//----------------------------------------------------------------------
typedef enum logic [1:0] {
eVC_VA = 2'b00,
eVC_VL0 = 2'b01,
eVC_VH0 = 2'b10,
eVC_VH1 = 2'b11
} t_ccip_vc;
// Multi-CL Memory Request
//----------------------------------------------------------------------
typedef enum logic [1:0] {
eCL_LEN_1 = 2'b00,
eCL_LEN_2 = 2'b01,
eCL_LEN_4 = 2'b11
} t_ccip_clLen;
//
// Structures for Request and Response headers
//----------------------------------------------------------------------
typedef struct packed {
t_ccip_vc vc_sel;
logic [1:0] rsvd1; // reserved, drive 0
t_ccip_clLen cl_len;
t_ccip_c0_req req_type;
logic [5:0] rsvd0; // reserved, drive 0
t_ccip_clAddr address;
t_ccip_mdata mdata;
} t_ccip_c0_ReqMemHdr;
parameter CCIP_C0TX_HDR_WIDTH = $bits(t_ccip_c0_ReqMemHdr);
typedef struct packed {
logic [5:0] rsvd2;
t_ccip_vc vc_sel;
logic sop;
logic rsvd1; // reserved, drive 0
t_ccip_clLen cl_len;
t_ccip_c1_req req_type;
logic [5:0] rsvd0; // reserved, drive 0
t_ccip_clAddr address;
t_ccip_mdata mdata;
} t_ccip_c1_ReqMemHdr;
parameter CCIP_C1TX_HDR_WIDTH = $bits(t_ccip_c1_ReqMemHdr);
typedef struct packed {
logic [5:0] rsvd2; // reserved, drive 0
t_ccip_vc vc_sel;
logic [3:0] rsvd1; // reserved, drive 0
t_ccip_c1_req req_type;
logic [47:0] rsvd0; // reserved, drive 0
t_ccip_mdata mdata;
}t_ccip_c1_ReqFenceHdr;
typedef struct packed {
t_ccip_vc vc_used;
logic rsvd1; // reserved, don't care
logic hit_miss;
logic [1:0] rsvd0; // reserved, don't care
t_ccip_clNum cl_num;
t_ccip_c0_rsp resp_type;
t_ccip_mdata mdata;
} t_ccip_c0_RspMemHdr;
parameter CCIP_C0RX_HDR_WIDTH = $bits(t_ccip_c0_RspMemHdr);
typedef struct packed {
t_ccip_vc vc_used;
logic rsvd1; // reserved, don't care
logic hit_miss;
logic format;
logic rsvd0; // reserved, don't care
t_ccip_clNum cl_num;
t_ccip_c1_rsp resp_type;
t_ccip_mdata mdata;
} t_ccip_c1_RspMemHdr;
parameter CCIP_C1RX_HDR_WIDTH = $bits(t_ccip_c1_RspMemHdr);
typedef struct packed {
logic [7:0] rsvd0; // reserved, don't care
t_ccip_c1_rsp resp_type;
t_ccip_mdata mdata;
} t_ccip_c1_RspFenceHdr;
// Alternate Channel 0 MMIO request from host :
// MMIO requests arrive on the same channel as read responses, sharing
// t_if_ccip_c0_Rx below. When either mmioRdValid or mmioWrValid is set
// the message is an MMIO request and should be processed by casting
// t_if_ccip_c0_Rx.hdr to t_ccip_c0_ReqMmioHdr.
typedef struct packed {
t_ccip_mmioAddr address; // 4B aligned Mmio address
logic [1:0] length; // 2'b00- 4B, 2'b01- 8B, 2'b10- 64B
logic rsvd; // reserved, don't care
t_ccip_tid tid;
} t_ccip_c0_ReqMmioHdr;
typedef struct packed {
t_ccip_tid tid; // Returned back from ReqMmioHdr
} t_ccip_c2_RspMmioHdr;
parameter CCIP_C2TX_HDR_WIDTH = $bits(t_ccip_c2_RspMmioHdr);
//------------------------------------------------------------------------
// CCI-P Input & Output bus structures
//
// Users are encouraged to use these for AFU development
//------------------------------------------------------------------------
// Channel 0 : Memory Reads
typedef struct packed {
t_ccip_c0_ReqMemHdr hdr; // Request Header
logic valid; // Request Valid
} t_if_ccip_c0_Tx;
// Channel 1 : Memory Writes, Interrupts, CmpXchg
typedef struct packed {
t_ccip_c1_ReqMemHdr hdr; // Request Header
t_ccip_clData data; // Request Data
logic valid; // Request Wr Valid
} t_if_ccip_c1_Tx;
// Channel 2 : MMIO Read response
typedef struct packed {
t_ccip_c2_RspMmioHdr hdr; // Response Header
logic mmioRdValid; // Response Read Valid
t_ccip_mmioData data; // Response Data
} t_if_ccip_c2_Tx;
// Wrap all Tx channels
typedef struct packed {
t_if_ccip_c0_Tx c0;
t_if_ccip_c1_Tx c1;
t_if_ccip_c2_Tx c2;
} t_if_ccip_Tx;
// Channel 0: Memory Read response, MMIO Request
typedef struct packed {
t_ccip_c0_RspMemHdr hdr; // Rd Response/ MMIO req Header
t_ccip_clData data; // Rd Data / MMIO req Data
// Only one of valid, mmioRdValid and mmioWrValid may be set
// in a cycle. When either mmioRdValid or mmioWrValid are true
// the hdr must be processed specially. See t_ccip_c0_ReqMmioHdr
// above.
logic rspValid; // Rd Response Valid
logic mmioRdValid; // MMIO Read Valid
logic mmioWrValid; // MMIO Write Valid
} t_if_ccip_c0_Rx;
// Channel 1: Memory Writes
typedef struct packed {
t_ccip_c1_RspMemHdr hdr; // Response Header
logic rspValid; // Response Valid
} t_if_ccip_c1_Rx;
// Wrap all channels
typedef struct packed {
logic c0TxAlmFull; // C0 Request Channel Almost Full
logic c1TxAlmFull; // C1 Request Channel Almost Full
t_if_ccip_c0_Rx c0;
t_if_ccip_c1_Rx c1;
} t_if_ccip_Rx;
typedef union packed {
t_ccip_c0_RspMemHdr rspMemHdr;
t_ccip_c0_ReqMmioHdr reqMmioHdr;
} t_if_ccip_c0_RxHdr;
endpackage

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hw/rtl/afu/opae/ccip_interface_reg.sv Normal file
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// Code reused from Intel OPAE's 04_local_memory sample program with changes made to fit Vortex
// Register all interface signals
import ccip_if_pkg::*;
module ccip_interface_reg(
// CCI-P Clocks and Resets
input logic pClk, // 400MHz - CC-P clock domain. Primary Clock
input logic pck_cp2af_softReset_T0, // CCI-P ACTIVE HIGH Soft Reset
input logic [1:0] pck_cp2af_pwrState_T0, // CCI-P AFU Power State
input logic pck_cp2af_error_T0, // CCI-P Protocol Error Detected
// Interface structures
input t_if_ccip_Rx pck_cp2af_sRx_T0, // CCI-P Rx Port
input t_if_ccip_Tx pck_af2cp_sTx_T0, // CCI-P Tx Port
output logic pck_cp2af_softReset_T1,
output logic [1:0] pck_cp2af_pwrState_T1,
output logic pck_cp2af_error_T1,
output t_if_ccip_Rx pck_cp2af_sRx_T1,
output t_if_ccip_Tx pck_af2cp_sTx_T1
);
(* preserve *) logic pck_cp2af_softReset_T0_q;
(* preserve *) logic [1:0] pck_cp2af_pwrState_T0_q;
(* preserve *) logic pck_cp2af_error_T0_q;
(* preserve *) t_if_ccip_Rx pck_cp2af_sRx_T0_q;
(* preserve *) t_if_ccip_Tx pck_af2cp_sTx_T0_q;
always@(posedge pClk)
begin
pck_cp2af_softReset_T0_q <= pck_cp2af_softReset_T0;
pck_cp2af_pwrState_T0_q <= pck_cp2af_pwrState_T0;
pck_cp2af_error_T0_q <= pck_cp2af_error_T0;
pck_cp2af_sRx_T0_q <= pck_cp2af_sRx_T0;
pck_af2cp_sTx_T0_q <= pck_af2cp_sTx_T0;
end
always_comb
begin
pck_cp2af_softReset_T1 = pck_cp2af_softReset_T0_q;
pck_cp2af_pwrState_T1 = pck_cp2af_pwrState_T0_q;
pck_cp2af_error_T1 = pck_cp2af_error_T0_q;
pck_cp2af_sRx_T1 = pck_cp2af_sRx_T0_q;
pck_af2cp_sTx_T1 = pck_af2cp_sTx_T0_q;
end
endmodule

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hw/rtl/afu/opae/ccip_std_afu.sv Normal file
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// Code reused from Intel OPAE's 04_local_memory sample program with changes made to fit Vortex
// Top Level Vortex Driver
// To be done:
// Check how to run this with OPAE. Looks like setup issue
`include "platform_if.vh"
import local_mem_cfg_pkg::*;
module ccip_std_afu #(
parameter NUM_LOCAL_MEM_BANKS = 2
) (
// CCI-P Clocks and Resets
input logic pClk, // Primary CCI-P interface clock.
input logic pClkDiv2, // Aligned, pClk divided by 2.
input logic pClkDiv4, // Aligned, pClk divided by 4.
input logic uClk_usr, // User clock domain. Refer to clock programming guide.
input logic uClk_usrDiv2, // Aligned, user clock divided by 2.
input logic pck_cp2af_softReset, // CCI-P ACTIVE HIGH Soft Reset
input logic [1:0] pck_cp2af_pwrState, // CCI-P AFU Power State
input logic pck_cp2af_error, // CCI-P Protocol Error Detected
// CCI-P structures
input t_if_ccip_Rx pck_cp2af_sRx, // CCI-P Rx Port
output t_if_ccip_Tx pck_af2cp_sTx, // CCI-P Tx Port
// Local memory interface
avalon_mem_if.to_fiu local_mem[NUM_LOCAL_MEM_BANKS]
);
// ====================================================================
// Pick the proper clk and reset, as chosen by the AFU's JSON file
// ====================================================================
// The platform may transform the CCI-P clock from pClk to a clock
// chosen in the AFU's JSON file.
logic clk;
assign clk = `PLATFORM_PARAM_CCI_P_CLOCK;
logic reset;
assign reset = `PLATFORM_PARAM_CCI_P_RESET;
// ====================================================================
// Register signals at interface before consuming them
// ====================================================================
(* noprune *) logic [1:0] cp2af_pwrState_T1;
(* noprune *) logic cp2af_error_T1;
logic reset_T1;
t_if_ccip_Rx cp2af_sRx_T1;
t_if_ccip_Tx af2cp_sTx_T0;
ccip_interface_reg inst_green_ccip_interface_reg
(
.pClk (clk),
.pck_cp2af_softReset_T0 (reset),
.pck_cp2af_pwrState_T0 (pck_cp2af_pwrState),
.pck_cp2af_error_T0 (pck_cp2af_error),
.pck_cp2af_sRx_T0 (pck_cp2af_sRx),
.pck_af2cp_sTx_T0 (af2cp_sTx_T0),
.pck_cp2af_softReset_T1 (reset_T1),
.pck_cp2af_pwrState_T1 (cp2af_pwrState_T1),
.pck_cp2af_error_T1 (cp2af_error_T1),
.pck_cp2af_sRx_T1 (cp2af_sRx_T1),
.pck_af2cp_sTx_T1 (pck_af2cp_sTx)
);
// ====================================================================
// User AFU goes here
// ====================================================================
t_local_mem_byte_mask avs_byteenable [NUM_LOCAL_MEM_BANKS];
logic avs_waitrequest [NUM_LOCAL_MEM_BANKS];
t_local_mem_data avs_readdata [NUM_LOCAL_MEM_BANKS];
logic avs_readdatavalid [NUM_LOCAL_MEM_BANKS];
t_local_mem_burst_cnt avs_burstcount [NUM_LOCAL_MEM_BANKS];
t_local_mem_data avs_writedata [NUM_LOCAL_MEM_BANKS];
t_local_mem_addr avs_address [NUM_LOCAL_MEM_BANKS];
logic avs_write [NUM_LOCAL_MEM_BANKS];
logic avs_read [NUM_LOCAL_MEM_BANKS];
for (genvar b = 0; b < NUM_LOCAL_MEM_BANKS; b++) begin
assign local_mem[b].burstcount = avs_burstcount[b];
assign local_mem[b].writedata = avs_writedata[b];
assign local_mem[b].address = avs_address[b];
assign local_mem[b].byteenable = avs_byteenable[b];
assign local_mem[b].write = avs_write[b];
assign local_mem[b].read = avs_read[b];
assign avs_waitrequest[b] = local_mem[b].waitrequest;
assign avs_readdata[b] = local_mem[b].readdata;
assign avs_readdatavalid[b] = local_mem[b].readdatavalid;
end
vortex_afu #(
.NUM_LOCAL_MEM_BANKS(NUM_LOCAL_MEM_BANKS)
) afu (
.clk (clk),
.reset (reset_T1),
.cp2af_sRxPort (cp2af_sRx_T1),
.af2cp_sTxPort (af2cp_sTx_T0),
.avs_writedata (avs_writedata),
.avs_readdata (avs_readdata),
.avs_address (avs_address),
.avs_waitrequest (avs_waitrequest),
.avs_write (avs_write),
.avs_read (avs_read),
.avs_byteenable (avs_byteenable),
.avs_burstcount (avs_burstcount),
.avs_readdatavalid (avs_readdatavalid)
);
endmodule

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hw/rtl/afu/opae/local_mem_cfg_pkg.sv Normal file
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//
// Copyright (c) 2017, Intel Corporation
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the Intel Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//`include "platform_afu_top_config.vh"
`ifdef PLATFORM_PROVIDES_LOCAL_MEMORY
package local_mem_cfg_pkg;
parameter LOCAL_MEM_VERSION_NUMBER = 1;
parameter LOCAL_MEM_ADDR_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH;
parameter LOCAL_MEM_DATA_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH;
parameter LOCAL_MEM_BURST_CNT_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH;
// Number of bytes in a data line
parameter LOCAL_MEM_DATA_N_BYTES = LOCAL_MEM_DATA_WIDTH / 8;
// Base types
// --------------------------------------------------------------------
typedef logic [LOCAL_MEM_ADDR_WIDTH-1:0] t_local_mem_addr;
typedef logic [LOCAL_MEM_DATA_WIDTH-1:0] t_local_mem_data;
typedef logic [LOCAL_MEM_BURST_CNT_WIDTH-1:0] t_local_mem_burst_cnt;
// Byte-level mask of a data line
typedef logic [LOCAL_MEM_DATA_N_BYTES-1:0] t_local_mem_byte_mask;
endpackage // local_mem_cfg_pkg
`endif // PLATFORM_PROVIDES_LOCAL_MEMORY

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hw/rtl/afu/opae/vortex_afu.sv Normal file
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hw/rtl/afu/opae/vortex_afu.vh Normal file
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// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`ifndef VORTEX_AFU_VH
`define VORTEX_AFU_VH
`define AFU_ACCEL_NAME "vortex_afu"
`define AFU_ACCEL_UUID 128'h35F9452B_25C2_434C_93D5_6F8C60DB361C
`define AFU_IMAGE_CMD_MEM_READ 1
`define AFU_IMAGE_CMD_MEM_WRITE 2
`define AFU_IMAGE_CMD_RUN 3
`define AFU_IMAGE_CMD_DCR_WRITE 4
`define AFU_IMAGE_CMD_MAX_VALUE 4
`define AFU_IMAGE_MMIO_CMD_TYPE 10
`define AFU_IMAGE_MMIO_CMD_ARG0 12
`define AFU_IMAGE_MMIO_CMD_ARG1 14
`define AFU_IMAGE_MMIO_CMD_ARG2 16
`define AFU_IMAGE_MMIO_STATUS 18
`define AFU_IMAGE_MMIO_SCOPE_READ 20
`define AFU_IMAGE_MMIO_SCOPE_WRITE 22
`define AFU_IMAGE_MMIO_DEV_CAPS 24
`define AFU_IMAGE_MMIO_ISA_CAPS 26
`define AFU_IMAGE_POWER 0
`define AFU_TOP_IFC "ccip_std_afu_avalon_mm"
`endif // VORTEX_AFU_VH