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FPU float<->int conversion optimization

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This commit is contained in:
Blaise Tine
2020-12-29 15:37:45 -08:00
parent e83c4638a0
commit d44144f72f
53 changed files with 993 additions and 4953 deletions
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2
hw/rtl/libs/VX_elastic_buffer.v
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@@ -34,7 +34,7 @@ module VX_elastic_buffer #(
wire push = valid_in && ready_in;
wire pop = valid_out && ready_out;
VX_generic_queue #(
VX_fifo_queue #(
.DATAW (DATAW),
.SIZE (SIZE),
.BUFFERED (BUFFERED),

2
hw/rtl/libs/VX_generic_queue.v → hw/rtl/libs/VX_fifo_queue.v
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@@ -1,6 +1,6 @@
`include "VX_platform.vh"
module VX_generic_queue #(
module VX_fifo_queue #(
parameter DATAW = 1,
parameter SIZE = 2,
parameter ADDRW = $clog2(SIZE),

45
hw/rtl/libs/VX_generic_register.v
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@@ -1,45 +0,0 @@
`include "VX_platform.vh"
module VX_generic_register #(
parameter N = 1,
parameter R = N,
parameter PASSTHRU = 0
) (
input wire clk,
input wire reset,
input wire stall,
input wire flush,
input wire[N-1:0] data_in,
output wire[N-1:0] data_out
);
if (PASSTHRU) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (stall)
assign data_out = flush ? N'(0) : data_in;
end else begin
reg [N-1:0] value;
if (R != 0) begin
always @(posedge clk) begin
if (~stall) begin
value <= data_in;
end
if (reset || flush) begin
value[N-1:N-R] <= R'(0);
end
end
end else begin
`UNUSED_VAR (reset)
`UNUSED_VAR (flush)
always @(posedge clk) begin
if (~stall) begin
value <= data_in;
end
end
end
assign data_out = value;
end
endmodule

2
hw/rtl/libs/VX_index_buffer.v
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@@ -28,7 +28,7 @@ module VX_index_buffer #(
wire [ADDRW-1:0] free_index;
VX_priority_encoder #(
.N(SIZE)
.DATAW (SIZE)
) free_slots_encoder (
.data_in (free_slots_n),
.data_out (free_index),

27
hw/rtl/libs/VX_lzc.v Normal file
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@@ -0,0 +1,27 @@
`include "VX_platform.vh"
module VX_lzc #(
parameter DATAW = 1,
parameter LDATAW = `LOG2UP(DATAW)
) (
input wire [DATAW-1:0] data_in,
output wire [LDATAW-1:0] data_out,
output wire valid_out
);
reg [LDATAW-1:0] data_out_r;
always @(*) begin
data_out_r = 'x;
for (integer i = DATAW-1; i >= 0; --i) begin
if (data_in[i]) begin
data_out_r = LDATAW'(DATAW-1-i);
break;
end
end
end
assign data_out = data_out_r;
assign valid_out = (| data_in);
endmodule

53
hw/rtl/libs/VX_pipe_register.v Normal file
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@@ -0,0 +1,53 @@
`include "VX_platform.vh"
module VX_pipe_register #(
parameter DATAW = 1,
parameter RESETW = DATAW,
parameter DEPTH = 1
) (
input wire clk,
input wire reset,
input wire enable,
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out
);
if (DEPTH == 0) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (enable)
assign data_out = data_in;
end else if (DEPTH == 1) begin
reg [DATAW-1:0] value;
if (RESETW != 0) begin
always @(posedge clk) begin
if (reset) begin
value[DATAW-1:DATAW-RESETW] <= RESETW'(0);
end else if (enable) begin
value <= data_in;
end
end
end else begin
`UNUSED_VAR (reset)
always @(posedge clk) begin
if (enable) begin
value <= data_in;
end
end
end
assign data_out = value;
end else begin
VX_shift_register #(
.DATAW (DATAW),
.RESETW (RESETW),
.DEPTH (DEPTH)
) shift_reg (
.clk (clk),
.reset (reset),
.enable (enable),
.data_in (data_in),
.data_out (data_out)
);
end
endmodule

16
hw/rtl/libs/VX_priority_encoder.v
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@@ -1,20 +1,20 @@
`include "VX_platform.vh"
module VX_priority_encoder #(
parameter N = 1,
parameter LOGN = `LOG2UP(N)
parameter DATAW = 1,
parameter LDATAW = `LOG2UP(DATAW)
) (
input wire [N-1:0] data_in,
output wire [LOGN-1:0] data_out,
output wire valid_out
input wire [DATAW-1:0] data_in,
output wire [LDATAW-1:0] data_out,
output wire valid_out
);
reg [`LOG2UP(N)-1:0] data_out_r;
reg [LDATAW-1:0] data_out_r;
always @(*) begin
data_out_r = 'x;
for (integer i = 0; i < N; i++) begin
for (integer i = 0; i < DATAW; i++) begin
if (data_in[i]) begin
data_out_r = LOGN'(i);
data_out_r = LDATAW'(i);
break;
end
end

2
hw/rtl/libs/VX_shift_register.v
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@@ -76,7 +76,7 @@ endmodule
module VX_shift_register #(
parameter DATAW = 1,
parameter RESETW = DATAW,
parameter RESETW = 0,
parameter DEPTH = 1,
parameter NTAPS = 1,
parameter DEPTHW = $clog2(DEPTH),

9
hw/rtl/libs/VX_skid_buffer.v
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@@ -34,14 +34,13 @@ module VX_skid_buffer #(
wire stall = valid_out && ~ready_out;
VX_generic_register #(
.N (1 + DATAW),
.R (1)
VX_pipe_register #(
.DATAW (1 + DATAW),
.RESETW (1)
) pipe_reg (
.clk (clk),
.reset (reset),
.stall (stall),
.flush (1'b0),
.enable (!stall),
.data_in ({valid_in, data_in}),
.data_out ({valid_out, data_out})
);