wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge branch 'master' into graphics

Browse Source
This commit is contained in:
Blaise Tine
2021-05-26 23:33:06 -07:00
parent f4c52a41fa 321a2c5e1b
commit d42171d2ed
120 changed files with 4269 additions and 2329 deletions
Download Patch File Download Diff File Expand all files Collapse all files

119
hw/syn/modelsim/Makefile Normal file
View File

@@ -0,0 +1,119 @@
ALL:sim
#TOOL INPUT
SRC = \
vortex_dpi.cpp \
vortex_tb.v \
../rtl/VX_user_config.vh \
../rtl/VX_config.vh \
../rtl/VX_define.vh \
../rtl/interfaces/VX_branch_response_inter.v \
../rtl/interfaces/VX_csr_req_inter.v \
../rtl/interfaces/VX_csr_wb_inter.v \
../rtl/interfaces/VX_dcache_request_inter.v \
../rtl/interfaces/VX_dcache_response_inter.v \
../rtl/interfaces/VX_dram_req_rsp_inter.v \
../rtl/interfaces/VX_exec_unit_req_inter.v \
../rtl/interfaces/VX_frE_to_bckE_req_inter.v \
../rtl/interfaces/VX_gpr_data_inter.v \
../rtl/interfaces/VX_gpr_jal_inter.v \
../rtl/interfaces/VX_gpr_read_inter.v \
../rtl/interfaces/VX_gpu_inst_req_inter.v \
../rtl/interfaces/VX_icache_request_inter.v \
../rtl/interfaces/VX_icache_response_inter.v \
../rtl/interfaces/VX_inst_exec_wb_inter.v \
../rtl/interfaces/VX_inst_mem_wb_inter.v \
../rtl/interfaces/VX_inst_meta_inter.v \
../rtl/interfaces/VX_jal_response_inter.v \
../rtl/interfaces/VX_join_inter.v \
../rtl/interfaces/VX_lsu_req_inter.v \
../rtl/interfaces/VX_mem_req_inter.v \
../rtl/interfaces/VX_mw_wb_inter.v \
../rtl/interfaces/VX_warp_ctl_inter.v \
../rtl/interfaces/VX_wb_inter.v \
../rtl/interfaces/VX_wstall_inter.v \
../rtl/VX_alu.v \
../rtl/VX_back_end.v \
../rtl/VX_csr_handler.v \
../rtl/VX_csr_wrapper.v \
../rtl/VX_decode.v \
../rtl/VX_dmem_controller.v \
../rtl/VX_execute_unit.v \
../rtl/VX_fetch.v \
../rtl/VX_front_end.v \
../rtl/VX_generic_priority_encoder.v \
../rtl/VX_generic_register.v \
../rtl/VX_generic_stack.v \
../rtl/VX_gpgpu_inst.v \
../rtl/VX_gpr.v \
../rtl/VX_gpr_stage.v \
../rtl/VX_gpr_wrapper.v \
../rtl/VX_inst_multiplex.v \
../rtl/VX_lsu.v \
../rtl/VX_lsu_addr_gen.v \
../rtl/VX_priority_encoder.v \
../rtl/VX_priority_encoder_w_mask.v \
../rtl/VX_scheduler.v \
../rtl/VX_warp.v \
../rtl/VX_countones.v \
../rtl/VX_warp_scheduler.v \
../rtl/VX_writeback.v \
../rtl/Vortex.v \
../rtl/byte_enabled_simple_dual_port_ram.v \
../rtl/cache/VX_Cache_Bank.v \
../rtl/cache/VX_cache_bank_valid.v \
../rtl/cache/VX_cache_data.v \
../rtl/cache/VX_d_cache.v \
../rtl/cache/VX_generic_pe.v \
../rtl/cache/cache_set.v \
../rtl/cache/VX_cache_data_per_index.v \
../rtl/VX_d_e_reg.v \
../rtl/VX_f_d_reg.v \
../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v \
../models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.v \
../models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.v \
../models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1.v \
../models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0.v
# ../models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v
# vortex_dpi.h
CMD= \
-do "VoptFlow = 0; \
vcd file vortex.vcd; \
vcd add -r /vortex_tb/*; \
vcd add -r /vortex/*; \
run -all; \
quit -f"
OPT=-sv -sv12compat
LIB = vortex_lib
# LOG=-logfile vortex_tb.log
LOG=
# setup: source cshrc.modelsim
# vlib
lib:
vlib vortex_lib
comp:
vlog $(OPT) -work $(LIB) $(SRC)
# vlog -O0 -dpiheader vortex_dpi.h $(OPT) -work $(LIB) $(SRC)
sim: comp
# vsim vortex_tb $(LOG) -c -lib $(LIB) $(CMD) > vortex_sim.log
vsim -novopt vortex_tb $(LOG) -c -lib $(LIB) $(CMD) > vortex_sim.log

8
hw/syn/modelsim/cshrc.modelsim Normal file
View File

@@ -0,0 +1,8 @@
setenv PATH "${PATH}:/tools/mentor/modelsim/ms106a/modeltech/bin"
setenv MTI_VCO_MODE 1
if (${?LM_LICENSE_FILE}) then
setenv LM_LICENSE_FILE "1717@ece-linlic.ece.gatech.edu:${LM_LICENSE_FILE}"
else
setenv LM_LICENSE_FILE "1717@ece-linlic.ece.gatech.edu"
endif
setenv MGLS_LICENSE_FILE 1717@ece-linlic.ece.gatech.edu

328
hw/syn/modelsim/vortex_dpi.cpp Normal file
View File

@@ -0,0 +1,328 @@
// #include <iostream>
// #include "VX_define.h"
#include <../simulate/ram.h>
#include <stdio.h>
#include <math.h>
#include "svdpi.h"
#include "../simulate/VX_define.h"
// #include "vortex_dpi.h"
extern "C" {
void load_file (char * filename);
void ibus_driver (bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready);
void dbus_driver (bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready);
void io_handler (bool clk, bool io_valid, unsigned io_data);
void gracefulExit(int);
}
RAM ram;
bool refill;
unsigned refill_addr;
bool i_refill;
unsigned i_refill_addr;
unsigned num_cycles;
unsigned getIndex(int, int, int);
unsigned calculate_bits_per_bank_num(int);
unsigned getIndex(int r, int c, int numCols)
{
return (r * numCols) + c;
}
unsigned calculate_bits_per_bank_num(int num)
{
int shifted_num = 0;
for(int i = 0; i < num; i++){
shifted_num = (shifted_num << 1)| 1 ;
}
return shifted_num;
}
void load_file(char * filename)
{
num_cycles = 0;
// printf("\n\n\n\n**********************\n");
// printf("Inside load_file\n");
fprintf(stderr, "\n\n\n\n**********************\n");
loadHexImage(filename, &ram);
// printf("Filename: %s\n", filename);
refill = false;
i_refill = false;
}
void ibus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready)
{
// Default values
{
s_vpi_vecval * real_i_m_readdata = (s_vpi_vecval *) i_m_readdata;
(*i_m_ready) = false;
for (int i = 0; i < cache_banks; i++)
{
for (int j = 0; j < num_words_per_block; j++)
{
unsigned index = getIndex(i,j, num_words_per_block);
real_i_m_readdata[index].aval = 0x506070;
// svGetArrElemPtr2(i_m_readdata, i, j);
// svPutLogicArrElem2VecVal(i_m_readdata, i, j);
// i_m_readdata[getIndex(i,j, num_words_per_block)] = 0;
}
}
}
if (clk)
{
// Do nothing on positive edge
}
else
{
if (i_refill)
{
// svGetArrElemPtr2((*i_m_readdata), 0,0);
// fprintf(stderr, "--------------------------------\n");
i_refill = false;
*i_m_ready = true;
s_vpi_vecval * real_i_m_readdata = (s_vpi_vecval *) i_m_readdata;
for (int curr_e = 0; curr_e < (cache_banks*num_words_per_block); curr_e++)
{
unsigned new_addr = i_refill_addr + (4*curr_e);
unsigned addr_without_byte = new_addr >> 2;
unsigned bits_per_bank = (int)log2(cache_banks);
// unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank);
unsigned maskbits_per_bank = cache_banks - 1;
unsigned bank_num = addr_without_byte & maskbits_per_bank;
unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank;
unsigned offset_num = addr_wihtout_bank & (num_words_per_block-1);
unsigned value;
ram.getWord(new_addr, &value);
fprintf(stdout, "-------- (%x) i_m_readdata[%d][%d] (%d) = %x\n", new_addr, bank_num, offset_num, curr_e, value);
unsigned index = getIndex(bank_num,offset_num, num_words_per_block);
// fprintf(stderr, "Index: %d (%d, %d) = %x\n", index, bank_num, offset_num, value);
real_i_m_readdata[index].aval = value;
}
}
else
{
if (o_m_valid)
{
s_vpi_vecval * real_o_m_writedata = (s_vpi_vecval *) o_m_writedata;
if (o_m_read_or_write)
{
// fprintf(stderr, "++++++++++++++++++++++++++++++++\n");
for (int curr_e = 0; curr_e < (cache_banks*num_words_per_block); curr_e++)
{
unsigned new_addr = (o_m_evict_addr) + (4*curr_e);
unsigned addr_without_byte = new_addr >> 2;
unsigned bits_per_bank = (int)log2(cache_banks);
// unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank);
unsigned maskbits_per_bank = cache_banks - 1;
unsigned bank_num = addr_without_byte & maskbits_per_bank;
unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank;
unsigned offset_num = addr_wihtout_bank & (num_words_per_block-1);
// unsigned offset_num = addr_wihtout_bank & 0x3;
unsigned index = getIndex(bank_num,offset_num, num_words_per_block);
unsigned new_value = real_o_m_writedata[index].aval;
// new_value = (unsigned *) svGetArrElemPtr2(o_m_writedata, bank_num, offset_num);
// new_value = getElem(o_m_writedata, index);
// unsigned new_value = o_m_writedata[getIndex(bank_num,offset_num, num_words_per_block)];
ram.writeWord( new_addr, &new_value);
fprintf(stdout, "+++++++ (%x) writeback[%d][%d] (%d) = %x\n", new_addr, bank_num, offset_num, curr_e, new_value);
}
}
// Respond next cycle
i_refill = true;
i_refill_addr = o_m_read_addr;
}
}
}
}
void dbus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready)
{
// Default values
{
s_vpi_vecval * real_i_m_readdata = (s_vpi_vecval *) i_m_readdata;
(*i_m_ready) = false;
for (int i = 0; i < cache_banks; i++)
{
for (int j = 0; j < num_words_per_block; j++)
{
unsigned index = getIndex(i,j, num_words_per_block);
real_i_m_readdata[index].aval = 0x506070;
// svGetArrElemPtr2(i_m_readdata, i, j);
// svPutLogicArrElem2VecVal(i_m_readdata, i, j);
// i_m_readdata[getIndex(i,j, num_words_per_block)] = 0;
}
}
}
if (clk)
{
// Do nothing on positive edge
}
else
{
if (refill)
{
// svGetArrElemPtr2((*i_m_readdata), 0,0);
// fprintf(stderr, "--------------------------------\n");
refill = false;
*i_m_ready = true;
s_vpi_vecval * real_i_m_readdata = (s_vpi_vecval *) i_m_readdata;
for (int curr_e = 0; curr_e < (cache_banks*num_words_per_block); curr_e++)
{
unsigned new_addr = refill_addr + (4*curr_e);
unsigned addr_without_byte = new_addr >> 2;
unsigned bits_per_bank = (int)log2(cache_banks);
// unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank);
unsigned maskbits_per_bank = cache_banks - 1;
unsigned bank_num = addr_without_byte & maskbits_per_bank;
unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank;
unsigned offset_num = addr_wihtout_bank & (num_words_per_block-1);
unsigned value;
ram.getWord(new_addr, &value);
fprintf(stdout, "-------- (%x) i_m_readdata[%d][%d] (%d) = %x\n", new_addr, bank_num, offset_num, curr_e, value);
unsigned index = getIndex(bank_num,offset_num, num_words_per_block);
// fprintf(stderr, "Index: %d (%d, %d) = %x\n", index, bank_num, offset_num, value);
real_i_m_readdata[index].aval = value;
}
}
else
{
if (o_m_valid)
{
s_vpi_vecval * real_o_m_writedata = (s_vpi_vecval *) o_m_writedata;
if (o_m_read_or_write)
{
// fprintf(stderr, "++++++++++++++++++++++++++++++++\n");
for (int curr_e = 0; curr_e < (cache_banks*num_words_per_block); curr_e++)
{
unsigned new_addr = (o_m_evict_addr) + (4*curr_e);
unsigned addr_without_byte = new_addr >> 2;
unsigned bits_per_bank = (int)log2(cache_banks);
// unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank);
unsigned maskbits_per_bank = cache_banks - 1;
unsigned bank_num = addr_without_byte & maskbits_per_bank;
unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank;
unsigned offset_num = addr_wihtout_bank & (num_words_per_block-1);
// unsigned offset_num = addr_wihtout_bank & 0x3;
unsigned index = getIndex(bank_num,offset_num, num_words_per_block);
unsigned new_value = real_o_m_writedata[index].aval;
// new_value = (unsigned *) svGetArrElemPtr2(o_m_writedata, bank_num, offset_num);
// new_value = getElem(o_m_writedata, index);
// unsigned new_value = o_m_writedata[getIndex(bank_num,offset_num, num_words_per_block)];
ram.writeWord( new_addr, &new_value);
fprintf(stdout, "+++++++ (%x) writeback[%d][%d] (%d) = %x\n", new_addr, bank_num, offset_num, curr_e, new_value);
}
}
// Respond next cycle
refill = true;
refill_addr = o_m_read_addr;
}
}
}
}
void io_handler(bool clk, bool io_valid, unsigned io_data)
{
// printf("Inside io_handler\n");
if (clk)
{
// Do nothing
}
else
{
if (io_valid)
{
uint32_t data_write = (uint32_t) (io_data);
fprintf(stderr, "%c", (char) data_write);
fflush(stderr);
}
}
}
void gracefulExit(int cycles)
{
fprintf(stderr, "*********************\n\n");
fprintf(stderr, "DPI Cycle Num: %d\tVerilog Cycle Num: %d\n", num_cycles, cycles);
}

8
hw/syn/modelsim/vortex_dpi.h Normal file
View File

@@ -0,0 +1,8 @@
extern "C" {
void load_file (char * filename);
void dbus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready);
void ibus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready);
void io_handler (bool clk, bool io_valid, unsigned io_data);
void gracefulExit();
}

153
hw/syn/modelsim/vortex_tb.v Normal file
View File

@@ -0,0 +1,153 @@
`include "VX_define.vh"
//`define NUM_BANKS 8
//`define NUM_WORDS_PER_BLOCK 4
`define ARM_UD_MODEL
`timescale 1ns/1ps
import "DPI-C" load_file = function void load_file(input string filename);
/*
import "DPI-C" ibus_driver = function void ibus_driver(input logic clk, input int pc_addr,
output int instruction);
*/
import "DPI-C" ibus_driver = function void ibus_driver( input logic clk,
input int o_m_read_addr,
input int o_m_evict_addr,
input logic o_m_valid,
input reg[31:0] o_m_writedata[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0],
input logic o_m_read_or_write,
input int cache_banks,
input int words_per_block,
// Rsp
output reg[31:0] i_m_readdata[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0],
output logic i_m_ready);
import "DPI-C" dbus_driver = function void dbus_driver( input logic clk,
input int o_m_read_addr,
input int o_m_evict_addr,
input logic o_m_valid,
input reg[31:0] o_m_writedata[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0],
input logic o_m_read_or_write,
input int cache_banks,
input int words_per_block,
// Rsp
output reg[31:0] i_m_readdata[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0],
output logic i_m_ready);
import "DPI-C" io_handler = function void io_handler(input logic clk, input logic io_valid, input int io_data);
import "DPI-C" gracefulExit = function void gracefulExit(input int cycle_num);
module vortex_tb (
);
int cycle_num;
reg clk;
reg reset;
reg[31:0] icache_response_instruction;
reg[31:0] icache_request_pc_address;
// IO
reg io_valid;
reg[31:0] io_data;
// Req
reg [31:0] o_m_read_addr_d;
reg [31:0] o_m_evict_addr_d;
reg o_m_valid_d;
reg [31:0] o_m_writedata_d[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0];
reg o_m_read_or_write_d;
// Rsp
reg [31:0] i_m_readdata_d[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0];
reg i_m_ready_d;
// Req
reg [31:0] o_m_read_addr_i;
reg [31:0] o_m_evict_addr_i;
reg o_m_valid_i;
reg [31:0] o_m_writedata_i[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0];
reg o_m_read_or_write_i;
// Rsp
reg [31:0] i_m_readdata_i[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0];
reg i_m_ready_i;
reg out_ebreak;
reg[31:0] hi;
initial begin
// $fdumpfile("vortex1.vcd");
load_file("../../runtime/tests/simple/simple_main_if.hex");
$dumpvars(0, vortex_tb);
reset = 1;
clk = 0;
#5 reset = 1;
clk = 1;
cycle_num = 0;
end
Vortex vortex(
.clk (clk),
.reset (reset),
.icache_response_instruction (icache_response_instruction),
.icache_request_pc_address (icache_request_pc_address),
.io_valid (io_valid),
.io_data (io_data),
.m_read_addr_d (o_m_read_addr_d),
.m_evict_addr_d (o_m_evict_addr_d),
.m_valid_d (o_m_valid_d),
.m_writedata_d (o_m_writedata_d),
.m_read_or_write_d (o_m_read_or_write_d),
.m_readdata_d (i_m_readdata_d),
.m_ready_d (i_m_ready_d),
.m_read_addr (o_m_read_addr_i),
.m_evict_addr (o_m_evict_addr_i),
.m_valid (o_m_valid_i),
.writedata (o_m_writedata_i),
.m_read_or_write (o_m_read_or_write_i),
.m_readdata (i_m_readdata_i),
.m_ready (i_m_ready_i),
.ebreak (out_ebreak)
);
always @(negedge clk) begin
ibus_driver(clk, o_m_read_addr_i, o_m_evict_addr_i, o_m_valid_i, o_m_writedata_i, o_m_read_or_write_i, `ICACHE_BANKS, `ICACHE_NUM_WORDS_PER_BLOCK, i_m_readdata_i, i_m_ready_i);
dbus_driver(clk, o_m_read_addr_d, o_m_evict_addr_d, o_m_valid_d, o_m_writedata_d, o_m_read_or_write_d, `DCACHE_BANKS, `DCACHE_NUM_WORDS_PER_BLOCK, i_m_readdata_d, i_m_ready_d);
io_handler (clk, io_valid, io_data);
end
always @(posedge clk) begin
if (out_ebreak) begin
gracefulExit(cycle_num);
#40 $finish;
end
end
always @(posedge clk) begin
cycle_num = cycle_num + 1;
end
always @(clk) begin
if (reset) begin
reset = 0;
clk = 0;
end
#5 clk <= !clk;
end
endmodule

191
hw/syn/opae/Makefile
View File

@@ -1,32 +1,114 @@
ASE_BUILD_DIR=build_ase
FPGA_BUILD_DIR=build_fpga
DEVICE_FAMILY ?= arria10
ASE_BUILD_DIR ?= build_ase_$(DEVICE_FAMILY)
FPGA_BUILD_DIR ?= build_fpga_$(DEVICE_FAMILY)
RTL_DIR=../../rtl
ifeq (, $(shell which qsub-synth))
ifeq ($(shell which qsub-synth),)
RUN_SYNTH=$(OPAE_PLATFORM_ROOT)/bin/run.sh > build.log 2>&1 &
else
RUN_SYNTH=qsub-synth
endif
# control RTL debug print states
DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE
DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_ICACHE
DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_DCACHE
DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_BANK
DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSHR
DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_TAG
DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_DATA
DBG_PRINT_FLAGS += -DDBG_PRINT_MEM
DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE
DBG_PRINT_FLAGS += -DDBG_PRINT_AVS
DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE
DBG_FLAGS += $(DBG_PRINT_FLAGS)
DBG_FLAGS += -DDBG_CACHE_REQ_INFO
CONFIG1 := -DNUM_CLUSTERS=1 -DNUM_CORES=1 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
CONFIG2 := -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
CONFIG4 := -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
CONFIG8 := -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
CONFIG16 := -DNUM_CLUSTERS=4 -DNUM_CORES=4 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
CONFIG32 := -DNUM_CLUSTERS=4 -DNUM_CORES=8 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
CONFIG64 := -DNUM_CLUSTERS=8 -DNUM_CORES=8 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)
RTL_INCLUDE = -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache $(FPU_INCLUDE) -I$(RTL_DIR) -I$(RTL_DIR)/afu
CFLAGS += $(RTL_INCLUDE)
# Debugigng
ifdef DEBUG
CFLAGS += $(DBG_FLAGS)
else
CFLAGS += -DNDEBUG
endif
# Enable scope analyzer
ifdef SCOPE
CFLAGS += -DSCOPE
endif
# Enable perf counters
ifdef PERF
CFLAGS += -DPERF_ENABLE
endif
all: ase-1c
gen_sources_a10:
./gen_sources.sh arria10 > sources.txt
$(ASE_BUILD_DIR)_1c/Makefile:
afu_sim_setup -s setup.cfg $(ASE_BUILD_DIR)_1c
gen_sources_s10:
./gen_sources.sh stratix10 > sources.txt
$(ASE_BUILD_DIR)_2c/Makefile:
afu_sim_setup -s setup.cfg $(ASE_BUILD_DIR)_2c
ase-1c: gen_sources_a10 setup-ase-1c
make -C $(ASE_BUILD_DIR)_1c
cp $(RTL_DIR)/fp_cores/altera/arria10/*.hex $(ASE_BUILD_DIR)_1c/work
$(ASE_BUILD_DIR)_4c/Makefile:
afu_sim_setup -s setup.cfg $(ASE_BUILD_DIR)_4c
ase-2c: gen_sources_a10 setup-ase-2c
make -C $(ASE_BUILD_DIR)_2c
cp $(RTL_DIR)/fp_cores/altera/arria10/*.hex $(ASE_BUILD_DIR)_2c/work
$(FPGA_BUILD_DIR)_1c/build/dcp.qpf:
afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_1c
ase-4c: gen_sources_a10 setup-ase-4c
make -C $(ASE_BUILD_DIR)_4c
cp $(RTL_DIR)/fp_cores/altera/arria10/*.hex $(ASE_BUILD_DIR)_4c/work
$(FPGA_BUILD_DIR)_2c/build/dcp.qpf:
afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_2c
$(FPGA_BUILD_DIR)_4c/build/dcp.qpf:
afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_4c
$(FPGA_BUILD_DIR)_8c/build/dcp.qpf:
afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_8c
$(FPGA_BUILD_DIR)_16c/build/dcp.qpf:
afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_16c
$(FPGA_BUILD_DIR)_32c/build/dcp.qpf:
afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_32c
$(FPGA_BUILD_DIR)_64c/build/dcp.qpf:
afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_64c
gen-sources-1c:
./gen_sources.sh $(CFLAGS) $(CONFIG1) > sources.txt
gen-sources-2c:
./gen_sources.sh $(CFLAGS) $(CONFIG2) > sources.txt
gen-sources-4c:
./gen_sources.sh $(CFLAGS) $(CONFIG4) > sources.txt
gen-sources-8c:
./gen_sources.sh $(CFLAGS) $(CONFIG8) > sources.txt
gen-sources-16c:
./gen_sources.sh $(CFLAGS) $(CONFIG16) > sources.txt
gen-sources-32c:
./gen_sources.sh $(CFLAGS) $(CONFIG32) > sources.txt
gen-sources-64c:
./gen_sources.sh $(CFLAGS) $(CONFIG64) > sources.txt
# setup
setup-ase-1c: $(ASE_BUILD_DIR)_1c/Makefile
@@ -34,36 +116,6 @@ setup-ase-2c: $(ASE_BUILD_DIR)_2c/Makefile
setup-ase-4c: $(ASE_BUILD_DIR)_4c/Makefile
$(ASE_BUILD_DIR)_1c/Makefile:
afu_sim_setup -s sources_1c.txt $(ASE_BUILD_DIR)_1c
$(ASE_BUILD_DIR)_2c/Makefile:
afu_sim_setup -s sources_2c.txt $(ASE_BUILD_DIR)_2c
$(ASE_BUILD_DIR)_4c/Makefile:
afu_sim_setup -s sources_4c.txt $(ASE_BUILD_DIR)_4c
fpga-1c: gen_sources_a10 setup-fpga-1c
cd $(FPGA_BUILD_DIR)_1c && $(RUN_SYNTH)
fpga-2c: gen_sources_a10 setup-fpga-2c
cd $(FPGA_BUILD_DIR)_2c && $(RUN_SYNTH)
fpga-4c: gen_sources_a10 setup-fpga-4c
cd $(FPGA_BUILD_DIR)_4c && $(RUN_SYNTH)
fpga-8c: gen_sources_a10 setup-fpga-8c
cd $(FPGA_BUILD_DIR)_8c && $(RUN_SYNTH)
fpga-16c: gen_sources_a10 setup-fpga-16c
cd $(FPGA_BUILD_DIR)_16c && $(RUN_SYNTH)
fpga-32c: gen_sources_s10 setup-fpga-32c
cd $(FPGA_BUILD_DIR)_32c && $(RUN_SYNTH)
fpga-64c: gen_sources_s10 setup-fpga-64c
cd $(FPGA_BUILD_DIR)_64c && $(RUN_SYNTH)
setup-fpga-1c: $(FPGA_BUILD_DIR)_1c/build/dcp.qpf
setup-fpga-2c: $(FPGA_BUILD_DIR)_2c/build/dcp.qpf
@@ -78,35 +130,42 @@ setup-fpga-32c: $(FPGA_BUILD_DIR)_32c/build/dcp.qpf
setup-fpga-64c: $(FPGA_BUILD_DIR)_64c/build/dcp.qpf
$(FPGA_BUILD_DIR)_1c/build/dcp.qpf:
afu_synth_setup -s sources_1c.txt $(FPGA_BUILD_DIR)_1c
# build
$(FPGA_BUILD_DIR)_2c/build/dcp.qpf:
afu_synth_setup -s sources_2c.txt $(FPGA_BUILD_DIR)_2c
ase-1c: gen-sources-1c setup-ase-1c
make -C $(ASE_BUILD_DIR)_1c
cp $(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)/*.hex $(ASE_BUILD_DIR)_1c/work
$(FPGA_BUILD_DIR)_4c/build/dcp.qpf:
afu_synth_setup -s sources_4c.txt $(FPGA_BUILD_DIR)_4c
ase-2c: gen-sources-2c setup-ase-2c
make -C $(ASE_BUILD_DIR)_2c
cp $(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)/*.hex $(ASE_BUILD_DIR)_2c/work
$(FPGA_BUILD_DIR)_8c/build/dcp.qpf:
afu_synth_setup -s sources_8c.txt $(FPGA_BUILD_DIR)_8c
ase-4c: gen-sources-4c setup-ase-4c
make -C $(ASE_BUILD_DIR)_4c
cp $(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)/*.hex $(ASE_BUILD_DIR)_4c/work
$(FPGA_BUILD_DIR)_16c/build/dcp.qpf:
afu_synth_setup -s sources_16c.txt $(FPGA_BUILD_DIR)_16c
fpga-1c: gen-sources-1c setup-fpga-1c
cd $(FPGA_BUILD_DIR)_1c && $(RUN_SYNTH)
$(FPGA_BUILD_DIR)_32c/build/dcp.qpf:
afu_synth_setup -s sources_32c.txt $(FPGA_BUILD_DIR)_32c
fpga-2c: gen-sources-2c setup-fpga-2c
cd $(FPGA_BUILD_DIR)_2c && $(RUN_SYNTH)
$(FPGA_BUILD_DIR)_64c/build/dcp.qpf:
afu_synth_setup -s sources_64c.txt $(FPGA_BUILD_DIR)_64c
fpga-4c: gen-sources-4c setup-fpga-4c
cd $(FPGA_BUILD_DIR)_4c && $(RUN_SYNTH)
run-ase-1c:
cd $(ASE_BUILD_DIR)_1c && make sim
fpga-8c: gen-sources-8c setup-fpga-8c
cd $(FPGA_BUILD_DIR)_8c && $(RUN_SYNTH)
run-ase-2c:
cd $(ASE_BUILD_DIR)_2c && make sim
fpga-16c: gen-sources-16c setup-fpga-16c
cd $(FPGA_BUILD_DIR)_16c && $(RUN_SYNTH)
run-ase-4c:
cd $(ASE_BUILD_DIR)_4c && make sim
fpga-32c: gen-sources-32c setup-fpga-32c
cd $(FPGA_BUILD_DIR)_32c && $(RUN_SYNTH)
fpga-64c: gen-sources-64c setup-fpga-64c
cd $(FPGA_BUILD_DIR)_64c && $(RUN_SYNTH)
# cleanup
clean-ase-1c:
rm -rf $(ASE_BUILD_DIR)_1c sources.txt

37
hw/syn/opae/README
View File

@@ -44,6 +44,9 @@ fpgaconf vortex_afu.gbs
# If this says Multiple ports. Then use --bus with fpgaconf. #bus info can be found by fpgainfo port
fpgaconf --bus 0xaf vortex_afu.gbs
# get portid
fpgainfo port
# Running the Test case
cd /driver/tests/basic
make run-fpga
@@ -60,11 +63,13 @@ qsub-sim
make ase
# tests
./run_ase.sh build_ase_1c ../../../driver/tests/basic/basic -n16
./run_ase.sh build_ase_1c ../../../driver/tests/demo/demo -n16
./run_ase.sh build_ase_1c ../../../driver/tests/dogfood/dogfood -n16
./run_ase.sh build_ase_1c ../../../benchmarks/opencl/vecadd/vecadd
./run_ase.sh build_ase_1c ../../../benchmarks/opencl/sgemm/sgemm -n4
./run_ase.sh build_ase_arria10_1c ../../../driver/tests/basic/basic -n1 -t0
./run_ase.sh build_ase_arria10_1c ../../../driver/tests/basic/basic -n1 -t1
./run_ase.sh build_ase_arria10_1c ../../../driver/tests/basic/basic -n16
./run_ase.sh build_ase_arria10_1c ../../../driver/tests/demo/demo -n16
./run_ase.sh build_ase_arria10_1c ../../../driver/tests/dogfood/dogfood -n16
./run_ase.sh build_ase_arria10_1c ../../../benchmarks/opencl/vecadd/vecadd
./run_ase.sh build_ase_arria10_1c ../../../benchmarks/opencl/sgemm/sgemm -n4
# modify "vsim_run.tcl" to dump VCD trace
vcd file trace.vcd
@@ -75,17 +80,10 @@ run -all
tar -zcvf output_files_1c.tar.gz `find ./build_fpga_1c -type f \( -iname \*.rpt -o -iname \*.txt -o -iname \*summary -o -iname \*.log \)`
# compress VCD trace
tar -zcvf vortex.vcd.tar.gz ./build_ase_1c/work/vortex.vcd
tar -zcvf trace.vcd.tar.gz obj_dir/trace.vcd
tar -zcvf trace.fst.tar.gz trace.fst run.log
tar -zcvf run.log.tar.gz run.log
tar -cvjf vortex.vcd.tar.bz2 build_ase_1c/work/vortex.vcd
tar -zcvf vortex.vcd.tar.gz build_ase_1c/work/vortex.vcd
tar -zcvf run.log.tar.gz build_ase_1c/work/run.log
tar -zcvf vx_scope.vcd.tar.gz vx_scope.vcd
tar -cvjf vx_scope.vcd.tar.bz2 vx_scope.vcd
tar -cvjf trace.fst.tar.bz2 trace.fst run.log
tar -cvjf trace.vcd.tar.bz2 trace.vcd run.log
tar -cvjf trace.vcd.tar.bz2 build_ase_arria10_1c/work/run.log build_ase_arria10_1c/work/trace.vcd
# decompress VCD trace
tar -zxvf vortex.vcd.tar.gz
@@ -95,15 +93,4 @@ tar -xvf vortex.vcd.tar.bz2
lsof +D build_ase_1c
# quick off synthesis
make -C unittest clean && make -C unittest > unittest/build.log 2>&1 &
make -C pipeline clean && make -C pipeline > pipeline/build.log 2>&1 &
make -C cache clean && make -C cache > cache/build.log 2>&1 &
make -C core clean && make -C core > core/build.log 2>&1 &
make -C vortex clean && make -C vortex > vortex/build.log 2>&1 &
make -C top1 clean && make -C top1 > top1/build.log 2>&1 &
make -C top2 clean && make -C top2 > top2/build.log 2>&1 &
make -C top4 clean && make -C top4 > top4/build.log 2>&1 &
make -C top8 clean && make -C top8 > top8/build.log 2>&1 &
make -C top16 clean && make -C top16 > top16/build.log 2>&1 &
make -C top32 clean && make -C top32 > top32/build.log 2>&1 &
make -C top64 clean && make -C top64 > top64/build.log 2>&1 &
make core

69
hw/syn/opae/gen_sources.sh
View File

@@ -1,39 +1,46 @@
#!/bin/bash
rtl_dir="../../rtl"
exclude_list="VX_fpu_fpnew.v"
file_list=""
macros=()
includes=()
add_dirs()
{
for dir in $*; do
echo "+incdir+$dir"
for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f); do
exclude=0
for fe in $exclude_list; do
if [[ $file =~ $fe ]]; then
exclude=1
fi
done
if [[ $exclude == 0 ]]; then
file_list="$file_list $file"
# parse command arguments
while getopts D:I:h flag
do
case "${flag}" in
D) macros+=( ${OPTARG} );;
I) includes+=( ${OPTARG} );;
h) echo "Usage: [-D macro] [-I include] [-h help]"
exit 0
;;
\?)
echo "Invalid option: -$OPTARG" 1>&2
exit 1
;;
esac
done
# dump macros
for value in ${macros[@]}; do
echo "+define+$value"
done
# dump include directories
for dir in ${includes[@]}; do
echo "+incdir+$dir"
done
# dump source files
for dir in ${includes[@]}; do
for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f); do
exclude=0
for fe in $exclude_list; do
if [[ $file =~ $fe ]]; then
exclude=1
fi
done
if [[ $exclude == 0 ]]; then
echo $file
fi
done
}
add_files()
{
for file in $*; do
file_list="$file_list $file"
done
}
add_dirs $rtl_dir/fp_cores/altera/$1
add_dirs $rtl_dir/libs $rtl_dir/interfaces $rtl_dir/fp_cores $rtl_dir/cache $rtl_dir/tex_unit $rtl_dir $rtl_dir/afu
# dump file list
for file in $file_list; do
echo $file
done

3
hw/syn/opae/sources_4c.txt → hw/syn/opae/setup.cfg
View File

@@ -1,8 +1,5 @@
+define+NUM_CORES=4
+define+SYNTHESIS
+define+QUARTUS
#+define+PERF_ENABLE
vortex_afu.json
QI:vortex_afu.qsf

12
hw/syn/opae/sources_16c.txt
View File

@@ -1,12 +0,0 @@
+define+NUM_CORES=4
+define+NUM_CLUSTERS=4
#+define+L3_ENABLE=1
+define+SYNTHESIS
+define+QUARTUS
#+define+PERF_ENABLE
vortex_afu16.json
QI:vortex_afu.qsf
C:sources.txt

24
hw/syn/opae/sources_1c.txt
View File

@@ -1,24 +0,0 @@
+define+NUM_CORES=1
+define+SYNTHESIS
+define+QUARTUS
#+define+SCOPE
#+define+PERF_ENABLE
#+define+DBG_PRINT_CORE_ICACHE
#+define+DBG_PRINT_CORE_DCACHE
#+define+DBG_PRINT_CACHE_BANK
#+define+DBG_PRINT_CACHE_MSHR
#+define+DBG_PRINT_CACHE_TAG
#+define+DBG_PRINT_CACHE_DATA
#+define+DBG_PRINT_DRAM
#+define+DBG_PRINT_PIPELINE
#+define+DBG_PRINT_OPAE
#+define+DBG_PRINT_AVS
#+define+DBG_PRINT_SCOPE
#+define+DBG_CACHE_REQ_INFO
vortex_afu.json
QI:vortex_afu.qsf
C:sources.txt

10
hw/syn/opae/sources_2c.txt
View File

@@ -1,10 +0,0 @@
+define+NUM_CORES=2
+define+SYNTHESIS
+define+QUARTUS
#+define+PERF_ENABLE
vortex_afu.json
QI:vortex_afu.qsf
C:sources.txt

14
hw/syn/opae/sources_32c.txt
View File

@@ -1,14 +0,0 @@
+define+NUM_CORES=8
+define+NUM_CLUSTERS=4
#+define+L3_ENABLE=1
+define+GLOBAL_BLOCK_SIZE=16
+define+SYNTHESIS
+define+QUARTUS
#+define+PERF_ENABLE
vortex_afu.json
QI:vortex_afu.qsf
C:sources.txt

14
hw/syn/opae/sources_64c.txt
View File

@@ -1,14 +0,0 @@
+define+NUM_CORES=8
+define+NUM_CLUSTERS=8
#+define+L3_ENABLE=1
+define+GLOBAL_BLOCK_SIZE=16
+define+SYNTHESIS
+define+QUARTUS
#+define+PERF_ENABLE
vortex_afu.json
QI:vortex_afu.qsf
C:sources.txt

12
hw/syn/opae/sources_8c.txt
View File

@@ -1,12 +0,0 @@
+define+NUM_CORES=4
+define+NUM_CLUSTERS=2
#+define+L3_ENABLE=1
+define+SYNTHESIS
+define+QUARTUS
#+define+PERF_ENABLE
vortex_afu8.json
QI:vortex_afu.qsf
C:sources.txt

3
hw/syn/quartus/.gitignore vendored
View File

@@ -1,6 +1,9 @@
/unittest/*
!/unittest/Makefile
/smem/*
!/smem/Makefile
/cache/*
!/cache/Makefile

57
hw/syn/quartus/Makefile
View File

@@ -1,37 +1,68 @@
.PHONY: unittest pipeline cache core vortex top1 top2 top4 top8 top16 top32 top64
BUILDIR ?= build
.PHONY: unittest pipeline smem cache core vortex top1 top2 top4 top8 top16 top32 top64
unittest:
$(MAKE) -C unittest clean && $(MAKE) -C unittest > unittest/build.log 2>&1 &
mkdir -p unittest/$(BUILDIR)
cp unittest/Makefile unittest/$(BUILDIR)
$(MAKE) -C unittest/$(BUILDIR) clean && $(MAKE) -C unittest/$(BUILDIR) > unittest//$(BUILDIR)build.log 2>&1 &
pipeline:
$(MAKE) -C pipeline clean && $(MAKE) -C pipeline > pipeline/build.log 2>&1 &
mkdir -p pipeline/$(BUILDIR)
cp pipeline/Makefile pipeline/$(BUILDIR)
$(MAKE) -C pipeline/$(BUILDIR) clean && $(MAKE) -C pipeline/$(BUILDIR) > pipeline/$(BUILDIR)/build.log 2>&1 &
smem:
mkdir -p smem/$(BUILDIR)
cp smem/Makefile smem/$(BUILDIR)
$(MAKE) -C smem/$(BUILDIR) clean && $(MAKE) -C smem/$(BUILDIR) > smem/$(BUILDIR)/build.log 2>&1 &
cache:
$(MAKE) -C cache clean && $(MAKE) -C cache > cache/build.log 2>&1 &
mkdir -p cache/$(BUILDIR)
cp cache/Makefile cache/$(BUILDIR)
$(MAKE) -C cache/$(BUILDIR) clean && $(MAKE) -C cache/$(BUILDIR) > cache/$(BUILDIR)/build.log 2>&1 &
core:
$(MAKE) -C core clean && $(MAKE) -C core > core/build.log 2>&1 &
mkdir -p core/$(BUILDIR)
cp core/Makefile core/$(BUILDIR)
$(MAKE) -C core/$(BUILDIR) clean && $(MAKE) -C core/$(BUILDIR) > core/$(BUILDIR)/build.log 2>&1 &
vortex:
$(MAKE) -C vortex clean && $(MAKE) -C vortex > vortex/build.log 2>&1 &
mkdir -p vortex/$(BUILDIR)
cp vortex/Makefile vortex/$(BUILDIR)
$(MAKE) -C vortex/$(BUILDIR) clean && $(MAKE) -C vortex/$(BUILDIR) > vortex/$(BUILDIR)/build.log 2>&1 &
top1:
$(MAKE) -C top1 clean && $(MAKE) -C top1 > top1/build.log 2>&1 &
mkdir -p top1/$(BUILDIR)
cp top1/Makefile top1/$(BUILDIR)
$(MAKE) -C top1/$(BUILDIR) clean && $(MAKE) -C top1/$(BUILDIR) > top1/$(BUILDIR)/build.log 2>&1 &
top2:
$(MAKE) -C top2 clean && $(MAKE) -C top2 > top2/build.log 2>&1 &
mkdir -p top2/$(BUILDIR)
cp top2/Makefile top2/$(BUILDIR)
$(MAKE) -C top2/$(BUILDIR) clean && $(MAKE) -C top2/$(BUILDIR) > top2/$(BUILDIR)/build.log 2>&1 &
top4:
$(MAKE) -C top4 clean && $(MAKE) -C top4 > top4/build.log 2>&1 &
mkdir -p top4/$(BUILDIR)
cp top4/Makefile top4/$(BUILDIR)
$(MAKE) -C top4/$(BUILDIR) clean && $(MAKE) -C top4/$(BUILDIR) > top4/$(BUILDIR)/build.log 2>&1 &
top8:
$(MAKE) -C top8 clean && $(MAKE) -C top8 > top8/build.log 2>&1 &
mkdir -p top8/$(BUILDIR)
cp top8/Makefile top8/$(BUILDIR)
$(MAKE) -C top8/$(BUILDIR) clean && $(MAKE) -C top8/$(BUILDIR) > top8/$(BUILDIR)/build.log 2>&1 &
top16:
$(MAKE) -C top16 clean && $(MAKE) -C top16 > top16/build.log 2>&1 &
mkdir -p top16/$(BUILDIR)
cp top16/Makefile top16/$(BUILDIR)
$(MAKE) -C top16/$(BUILDIR) clean && $(MAKE) -C top16/$(BUILDIR) > top16/$(BUILDIR)build.log 2>&1 &
top32:
$(MAKE) -C top32 clean && $(MAKE) -C top32 > top32/build.log 2>&1 &
mkdir -p top32/$(BUILDIR)
cp top32/Makefile top32/$(BUILDIR)
$(MAKE) -C top32/$(BUILDIR) clean && $(MAKE) -C top32/$(BUILDIR) > top32/$(BUILDIR)/build.log 2>&1 &
top64:
$(MAKE) -C top64 clean && $(MAKE) -C top64 > top64/build.log 2>&1 &
mkdir -p top64/$(BUILDIR)
cp top64/Makefile top64/$(BUILDIR)
$(MAKE) -C top64/$(BUILDIR) clean && $(MAKE) -C top64/$(BUILDIR) > top64/$(BUILDIR)/build.log 2>&1 &

12
hw/syn/quartus/cache/Makefile vendored
View File

@@ -1,14 +1,12 @@
# Part, Family
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
PROJECT = VX_cache
TOP_LEVEL_ENTITY = VX_cache
SRC_FILE = VX_cache.v
RTL_DIR = ../../../../rtl
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
RTL_DIR=../../../rtl
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
# Executable Configuration
@@ -53,7 +51,7 @@ smart.log: $(PROJECT_FILES)
# Project initialization
$(PROJECT_FILES):
quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "$(RTL_INCLUDE)"
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../../project.sdc -inc "$(RTL_INCLUDE)"
syn.chg:
$(STAMP) syn.chg

18
hw/syn/quartus/core/Makefile
View File

@@ -1,13 +1,17 @@
# Part, Family
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
PROJECT = Core
TOP_LEVEL_ENTITY = VX_core
SRC_FILE = VX_core.v
RTL_DIR = ../../../../rtl
RTL_DIR=../../../rtl
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(RTL_DIR)/fp_cores/altera/arria10;$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
#FAMILY = "Stratix 10"
#DEVICE = 1SX280HN2F43E2VG
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
TEX_INCLUDE = $(RTL_DIR)/tex_unit
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(FPU_INCLUDE);$(TEX_INCLUDE)
@@ -55,7 +59,7 @@ smart.log: $(PROJECT_FILES)
# Project initialization
$(PROJECT_FILES):
quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)"
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)"
syn.chg:
$(STAMP) syn.chg

26
hw/syn/quartus/pipeline/Makefile
View File

@@ -1,22 +1,22 @@
# Part, Family
PROJECT = VX_pipeline
TOP_LEVEL_ENTITY = VX_pipeline
SRC_FILE = VX_pipeline.v
RTL_DIR = ../../../rtl
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
DEVICE = 10AX115N3F40E2SG
FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
PROJECT = Core
TOP_LEVEL_ENTITY = VX_core
SRC_FILE = VX_core.v
#FAMILY = "Stratix 10"
#DEVICE = 1SX280HN2F43E2VG
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
RTL_DIR=../../../rtl
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(RTL_DIR)/fp_cores/altera/arria10;$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
TEX_INCLUDE = $(RTL_DIR)/tex_unit
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(FPU_INCLUDE);$(TEX_INCLUDE)
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
# Part, Family
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
# Executable Configuration
SYN_ARGS = --parallel --read_settings_files=on
FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
@@ -59,7 +59,7 @@ smart.log: $(PROJECT_FILES)
# Project initialization
$(PROJECT_FILES):
quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)"
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)"
syn.chg:
$(STAMP) syn.chg
@@ -74,7 +74,7 @@ asm.chg:
$(STAMP) asm.chg
timing: $(PROJECT_FILES)
quartus_sh -t ../timing-html.tcl -project $(PROJECT)
quartus_sh -t ../../timing-html.tcl -project $(PROJECT)
program: $(PROJECT).sof
quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof"

72
hw/syn/quartus/smem/Makefile Executable file
View File

@@ -0,0 +1,72 @@
PROJECT = VX_shared_mem
TOP_LEVEL_ENTITY = VX_shared_mem
SRC_FILE = VX_shared_mem.v
RTL_DIR = ../../../../rtl
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
# Executable Configuration
SYN_ARGS = --parallel --read_settings_files=on
FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
ASM_ARGS =
STA_ARGS = --parallel --do_report_timing
# Build targets
all: $(PROJECT).sta.rpt
syn: $(PROJECT).syn.rpt
fit: $(PROJECT).fit.rpt
asm: $(PROJECT).asm.rpt
sta: $(PROJECT).sta.rpt
smart: smart.log
# Target implementations
STAMP = echo done >
$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
quartus_syn $(PROJECT) $(SYN_ARGS)
$(STAMP) fit.chg
$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
quartus_fit $(PROJECT) $(FIT_ARGS)
$(STAMP) asm.chg
$(STAMP) sta.chg
$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
quartus_asm $(PROJECT) $(ASM_ARGS)
$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
quartus_sta $(PROJECT) $(STA_ARGS)
smart.log: $(PROJECT_FILES)
quartus_sh --determine_smart_action $(PROJECT) > smart.log
# Project initialization
$(PROJECT_FILES):
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../../project.sdc -inc "$(RTL_INCLUDE)"
syn.chg:
$(STAMP) syn.chg
fit.chg:
$(STAMP) fit.chg
sta.chg:
$(STAMP) sta.chg
asm.chg:
$(STAMP) asm.chg
program: $(PROJECT).sof
quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof"
clean:
rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox

20
hw/syn/quartus/top1/Makefile
View File

@@ -1,16 +1,16 @@
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
FPU_CORE_PATH=../../../rtl/fp_cores/altera/arria10
#FAMILY = "Stratix 10"
#DEVICE = 1SX280HN2F43E2VG
#FPU_CORE_PATH=../../../rtl/fp_cores/altera/stratix10
PROJECT = vortex_afu
TOP_LEVEL_ENTITY = vortex_afu
SRC_FILE = vortex_afu.sv
RTL_DIR = ../../../../rtl
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
#FAMILY = "Stratix 10"
#DEVICE = 1SX280HN2F43E2VG
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
RTL_DIR=../../../rtl
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
TEX_INCLUDE = $(RTL_DIR)/tex_unit
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;../../../rtl/afu;../../../rtl/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)
@@ -59,7 +59,7 @@ smart.log: $(PROJECT_FILES)
# Project initialization
$(PROJECT_FILES):
quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=1"
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=1"
syn.chg:
$(STAMP) syn.chg

20
hw/syn/quartus/top16/Makefile
View File

@@ -1,16 +1,16 @@
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
FPU_CORE_PATH=../../../rtl/fp_cores/altera/arria10
#FAMILY = "Stratix 10"
#DEVICE = 1SX280HN2F43E2VG
#FPU_CORE_PATH=../../../rtl/fp_cores/altera/stratix10
PROJECT = vortex_afu
TOP_LEVEL_ENTITY = vortex_afu
SRC_FILE = vortex_afu.sv
RTL_DIR = ../../../../rtl
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
#FAMILY = "Stratix 10"
#DEVICE = 1SX280HN2F43E2VG
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
RTL_DIR=../../../rtl
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
TEX_INCLUDE = $(RTL_DIR)/tex_unit
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;../../../rtl/afu;../../../rtl/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)
@@ -59,7 +59,7 @@ smart.log: $(PROJECT_FILES)
# Project initialization
$(PROJECT_FILES):
quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" -set "NUM_CLUSTERS=4"
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" -set "NUM_CLUSTERS=4"
syn.chg:
$(STAMP) syn.chg

20
hw/syn/quartus/top2/Makefile
View File

@@ -1,16 +1,16 @@
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
FPU_CORE_PATH=../../../rtl/fp_cores/altera/arria10
#FAMILY = "Stratix 10"
#DEVICE = 1SX280HN2F43E2VG
#FPU_CORE_PATH=../../../rtl/fp_cores/altera/stratix10
PROJECT = vortex_afu
TOP_LEVEL_ENTITY = vortex_afu
SRC_FILE = vortex_afu.sv
RTL_DIR = ../../../../rtl
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
FPU_CORE_PATH=$(RTL_DIR)/fp_cores/altera/arria10
#FAMILY = "Stratix 10"
#DEVICE = 1SX280HN2F43E2VG
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
RTL_DIR=../../../rtl
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
TEX_INCLUDE = $(RTL_DIR)/tex_unit
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;../../../rtl/afu;../../../rtl/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)
@@ -59,7 +59,7 @@ smart.log: $(PROJECT_FILES)
# Project initialization
$(PROJECT_FILES):
quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=2"
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=2"
syn.chg:
$(STAMP) syn.chg

20
hw/syn/quartus/top32/Makefile
View File

@@ -1,16 +1,16 @@
#FAMILY = "Arria 10"
#DEVICE = 10AX115N3F40E2SG
#FPU_CORE_PATH=../../../rtl/fp_cores/altera/arria10
FAMILY = "Stratix 10"
DEVICE = 1SX280HN2F43E2VG
FPU_CORE_PATH=../../../rtl/fp_cores/altera/stratix10
PROJECT = vortex_afu
TOP_LEVEL_ENTITY = vortex_afu
SRC_FILE = vortex_afu.sv
RTL_DIR = ../../../../rtl
#FAMILY = "Arria 10"
#DEVICE = 10AX115N3F40E2SG
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
FAMILY = "Stratix 10"
DEVICE = 1SX280HN2F43E2VG
FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
RTL_DIR=../../../rtl
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
TEX_INCLUDE = $(RTL_DIR)/tex_unit
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;../../../rtl/afu;../../../rtl/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)
@@ -59,7 +59,7 @@ smart.log: $(PROJECT_FILES)
# Project initialization
$(PROJECT_FILES):
quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" -set "NUM_CLUSTERS=8"
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" -set "NUM_CLUSTERS=8"
syn.chg:
$(STAMP) syn.chg

20
hw/syn/quartus/top4/Makefile
View File

@@ -1,16 +1,16 @@
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
FPU_CORE_PATH=../../../rtl/fp_cores/altera/arria10
#FAMILY = "Stratix 10"
#DEVICE = 1SX280HN2F43E2VG
#FPU_CORE_PATH=../../../rtl/fp_cores/altera/stratix10
PROJECT = vortex_afu
TOP_LEVEL_ENTITY = vortex_afu
SRC_FILE = vortex_afu.sv
RTL_DIR = ../../../../rtl
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
#FAMILY = "Stratix 10"
#DEVICE = 1SX280HN2F43E2VG
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
RTL_DIR=../../../rtl
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
TEX_INCLUDE = $(RTL_DIR)/tex_unit
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;../../../rtl/afu;../../../rtl/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)
@@ -59,7 +59,7 @@ smart.log: $(PROJECT_FILES)
# Project initialization
$(PROJECT_FILES):
quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4"
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4"
syn.chg:
$(STAMP) syn.chg

20
hw/syn/quartus/top64/Makefile
View File

@@ -1,16 +1,16 @@
#FAMILY = "Arria 10"
#DEVICE = 10AX115N3F40E2SG
#FPU_CORE_PATH=../../../rtl/fp_cores/altera/arria10
FAMILY = "Stratix 10"
DEVICE = 1SX280HN2F43E2VG
FPU_CORE_PATH=../../../rtl/fp_cores/altera/stratix10
PROJECT = vortex_afu
TOP_LEVEL_ENTITY = vortex_afu
SRC_FILE = vortex_afu.sv
RTL_DIR=../../../../rtl
#FAMILY = "Arria 10"
#DEVICE = 10AX115N3F40E2SG
#FPU_CORE_PATH=$(RTL_DIR)/fp_cores/altera/arria10
FAMILY = "Stratix 10"
DEVICE = 1SX280HN2F43E2VG
FPU_CORE_PATH=$(RTL_DIR)/fp_cores/altera/stratix10
RTL_DIR=../../../rtl
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
TEX_INCLUDE = $(RTL_DIR)/tex_unit
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;../../../rtl/afu;../../../rtl/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)
@@ -59,7 +59,7 @@ smart.log: $(PROJECT_FILES)
# Project initialization
$(PROJECT_FILES):
quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=8" -set "NUM_CLUSTERS=8"
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=8" -set "NUM_CLUSTERS=8"
syn.chg:
$(STAMP) syn.chg

20
hw/syn/quartus/top8/Makefile
View File

@@ -1,16 +1,16 @@
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
FPU_CORE_PATH=../../../rtl/fp_cores/altera/arria10
#FAMILY = "Stratix 10"
#DEVICE = 1SX280HN2F43E2VG
#FPU_CORE_PATH=../../../rtl/fp_cores/altera/stratix10
PROJECT = vortex_afu
TOP_LEVEL_ENTITY = vortex_afu
SRC_FILE = vortex_afu.sv
RTL_DIR = ../../../../rtl
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
#FAMILY = "Stratix 10"
#DEVICE = 1SX280HN2F43E2VG
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
RTL_DIR=../../../rtl
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
TEX_INCLUDE = $(RTL_DIR)/tex_unit
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;../../../rtl/afu;../../../rtl/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)
@@ -59,7 +59,7 @@ smart.log: $(PROJECT_FILES)
# Project initialization
$(PROJECT_FILES):
quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" -set "NUM_CLUSTERS=2"
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" -set "NUM_CLUSTERS=2"
syn.chg:
$(STAMP) syn.chg

18
hw/syn/quartus/unittest/Makefile
View File

@@ -1,13 +1,19 @@
PROJECT = Unittest
TOP_LEVEL_ENTITY = VX_cache_core_req_bank_sel
SRC_FILE = VX_cache_core_req_bank_sel.v
FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera/arria10;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src
RTL_INCLUDE = $(FPU_INCLUDE);../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
RTL_DIR = ../../../../rtl
# Part, Family
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
DEVICE = 10AX115N3F40E2SG
FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
#FAMILY = "Stratix 10"
#DEVICE = 1SX280HN2F43E2VG
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
RTL_INCLUDE = $(FPU_INCLUDE);$(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
# Executable Configuration
SYN_ARGS = --parallel --read_settings_files=on
@@ -51,7 +57,7 @@ smart.log: $(PROJECT_FILES)
# Project initialization
$(PROJECT_FILES):
quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)"
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)"
syn.chg:
$(STAMP) syn.chg

20
hw/syn/quartus/vortex/Makefile
View File

@@ -1,16 +1,16 @@
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
FPU_CORE_PATH=../../../rtl/fp_cores/altera/arria10
#FAMILY = "Stratix 10"
#DEVICE = 1SX280HN2F43E2VG
#FPU_CORE_PATH=../../../rtl/fp_cores/altera/stratix10
PROJECT = Vortex
TOP_LEVEL_ENTITY = Vortex
SRC_FILE = Vortex.sv
RTL_DIR = ../../../../rtl
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
#FAMILY = "Stratix 10"
#DEVICE = 1SX280HN2F43E2VG
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
RTL_DIR=../../../rtl
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
TEX_INCLUDE = $(RTL_DIR)/tex_unit
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(FPU_INCLUDE);$(TEX_INCLUDE)
@@ -59,7 +59,7 @@ smart.log: $(PROJECT_FILES)
# Project initialization
$(PROJECT_FILES):
quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)"
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)"
syn.chg:
$(STAMP) syn.chg