memory interface refactoring

2021-07-20 21:06:55 -07:00
parent 80cf1f26f9
commit d3b788784a
14 changed files with 144 additions and 144 deletions
--- a/hw/rtl/interfaces/VX_mem_rsp_if.v
+++ b/hw/rtl/interfaces/VX_mem_rsp_if.v
@@ -0,0 +1,18 @@
+`ifndef VX_CACHE_MEM_RSP_IF
+`define VX_CACHE_MEM_RSP_IF
+
+`include "../cache/VX_cache_define.vh"
+
+interface VX_cache_mem_rsp_if #(
+    parameter MEM_LINE_WIDTH = 1,
+    parameter MEM_TAG_WIDTH  = 1
+) ();
+
+    wire                        valid;    
+    wire [MEM_LINE_WIDTH-1:0]   data;
+    wire [MEM_TAG_WIDTH-1:0]    tag;  
+    wire                        ready;      
+
+endinterface
+
+`endif