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memory interface refactoring

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This commit is contained in:
Blaise Tine
2021-07-20 21:06:55 -07:00
parent 80cf1f26f9
commit d3b788784a
14 changed files with 144 additions and 144 deletions
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76
hw/rtl/VX_core.v
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@@ -31,13 +31,13 @@ module VX_core #(
VX_perf_memsys_if perf_memsys_if();
`endif
VX_cache_mem_req_if #(
VX_mem_req_if #(
.MEM_LINE_WIDTH(`DMEM_LINE_WIDTH),
.MEM_ADDR_WIDTH(`DMEM_ADDR_WIDTH),
.MEM_TAG_WIDTH(`XMEM_TAG_WIDTH)
) mem_req_if();
VX_cache_mem_rsp_if #(
VX_mem_rsp_if #(
.MEM_LINE_WIDTH(`DMEM_LINE_WIDTH),
.MEM_TAG_WIDTH(`XMEM_TAG_WIDTH)
) mem_rsp_if();
@@ -57,27 +57,27 @@ module VX_core #(
//--
VX_dcache_core_req_if #(
VX_dcache_req_if #(
.NUM_REQS(`DNUM_REQS),
.WORD_SIZE(`DWORD_SIZE),
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH)
) dcache_core_req_if();
) dcache_req_if();
VX_dcache_core_rsp_if #(
VX_dcache_rsp_if #(
.NUM_REQS(`DNUM_REQS),
.WORD_SIZE(`DWORD_SIZE),
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH)
) dcache_core_rsp_if();
) dcache_rsp_if();
VX_icache_core_req_if #(
VX_icache_req_if #(
.WORD_SIZE(`IWORD_SIZE),
.CORE_TAG_WIDTH(`ICORE_TAG_WIDTH)
) icache_core_req_if();
) icache_req_if();
VX_icache_core_rsp_if #(
VX_icache_rsp_if #(
.WORD_SIZE(`IWORD_SIZE),
.CORE_TAG_WIDTH(`ICORE_TAG_WIDTH)
) icache_core_rsp_if();
) icache_rsp_if();
VX_pipeline #(
.CORE_ID(CORE_ID)
@@ -91,32 +91,32 @@ module VX_core #(
.reset(reset),
// Dcache core request
.dcache_req_valid (dcache_core_req_if.valid),
.dcache_req_rw (dcache_core_req_if.rw),
.dcache_req_byteen (dcache_core_req_if.byteen),
.dcache_req_addr (dcache_core_req_if.addr),
.dcache_req_data (dcache_core_req_if.data),
.dcache_req_tag (dcache_core_req_if.tag),
.dcache_req_ready (dcache_core_req_if.ready),
.dcache_req_valid (dcache_req_if.valid),
.dcache_req_rw (dcache_req_if.rw),
.dcache_req_byteen (dcache_req_if.byteen),
.dcache_req_addr (dcache_req_if.addr),
.dcache_req_data (dcache_req_if.data),
.dcache_req_tag (dcache_req_if.tag),
.dcache_req_ready (dcache_req_if.ready),
// Dcache core reponse
.dcache_rsp_valid (dcache_core_rsp_if.valid),
.dcache_rsp_tmask (dcache_core_rsp_if.tmask),
.dcache_rsp_data (dcache_core_rsp_if.data),
.dcache_rsp_tag (dcache_core_rsp_if.tag),
.dcache_rsp_ready (dcache_core_rsp_if.ready),
.dcache_rsp_valid (dcache_rsp_if.valid),
.dcache_rsp_tmask (dcache_rsp_if.tmask),
.dcache_rsp_data (dcache_rsp_if.data),
.dcache_rsp_tag (dcache_rsp_if.tag),
.dcache_rsp_ready (dcache_rsp_if.ready),
// Icache core request
.icache_req_valid (icache_core_req_if.valid),
.icache_req_addr (icache_core_req_if.addr),
.icache_req_tag (icache_core_req_if.tag),
.icache_req_ready (icache_core_req_if.ready),
.icache_req_valid (icache_req_if.valid),
.icache_req_addr (icache_req_if.addr),
.icache_req_tag (icache_req_if.tag),
.icache_req_ready (icache_req_if.ready),
// Icache core reponse
.icache_rsp_valid (icache_core_rsp_if.valid),
.icache_rsp_data (icache_core_rsp_if.data),
.icache_rsp_tag (icache_core_rsp_if.tag),
.icache_rsp_ready (icache_core_rsp_if.ready),
.icache_rsp_valid (icache_rsp_if.valid),
.icache_rsp_data (icache_rsp_if.data),
.icache_rsp_tag (icache_rsp_if.tag),
.icache_rsp_ready (icache_rsp_if.ready),
// Status
.busy(busy)
@@ -132,20 +132,20 @@ module VX_core #(
.perf_memsys_if (perf_memsys_if),
`endif
.clk (clk),
.reset (reset),
.clk (clk),
.reset (reset),
// Core <-> Dcache
.dcache_core_req_if (dcache_core_req_if),
.dcache_core_rsp_if (dcache_core_rsp_if),
.dcache_req_if (dcache_req_if),
.dcache_rsp_if (dcache_rsp_if),
// Core <-> Icache
.icache_core_req_if (icache_core_req_if),
.icache_core_rsp_if (icache_core_rsp_if),
.icache_req_if (icache_req_if),
.icache_rsp_if (icache_rsp_if),
// Memory
.mem_req_if (mem_req_if),
.mem_rsp_if (mem_rsp_if)
.mem_req_if (mem_req_if),
.mem_rsp_if (mem_rsp_if)
);
endmodule