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round robin arbiter + auto buffered queue + fixed dcache arbiter

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This commit is contained in:
Blaise Tine
2020-06-20 17:56:04 -04:00
parent 9c157e4929
commit d3440de403
30 changed files with 339 additions and 209 deletions
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43
hw/rtl/libs/VX_fixed_arbiter.v Normal file
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@@ -0,0 +1,43 @@
`include "VX_define.vh"
module VX_fixed_arbiter #(
parameter N = 0
) (
input wire clk,
input wire reset,
input wire [N-1:0] requests,
output wire [`LOG2UP(N)-1:0] grant_index,
output wire [N-1:0] grant_onehot,
output wire grant_valid
);
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
if (N == 1) begin
assign grant_index = 0;
assign grant_onehot = requests;
assign grant_valid = requests[0];
end else begin
reg [N-1:0] grant_onehot_r;
VX_priority_encoder # (
.N(N)
) priority_encoder (
.data_in (requests),
.data_out (grant_index),
.valid_out (grant_valid)
);
always @(*) begin
grant_onehot_r = N'(0);
grant_onehot_r[grant_index] = 1;
end
assign grant_onehot = grant_onehot_r;
end
endmodule

22
hw/rtl/libs/VX_generic_priority_encoder.v
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@@ -1,22 +0,0 @@
`include "VX_define.vh"
module VX_generic_priority_encoder #(
parameter N = 1
) (
input wire[N-1:0] valids,
output reg[(`LOG2UP(N))-1:0] index,
output reg found
);
integer i;
always @(*) begin
index = 0;
found = 0;
for (i = N-1; i >= 0; i = i - 1) begin
if (valids[i]) begin
index = i[(`LOG2UP(N))-1:0];
found = 1;
end
end
end
endmodule

2
hw/rtl/libs/VX_generic_queue.v
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@@ -3,7 +3,7 @@
module VX_generic_queue #(
parameter DATAW,
parameter SIZE = 16,
parameter BUFFERED_OUTPUT = 1
parameter BUFFERED_OUTPUT = (SIZE > 8)
) (
input wire clk,
input wire reset,

86
hw/rtl/libs/VX_matrix_arbiter.v
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@@ -5,49 +5,67 @@ module VX_matrix_arbiter #(
) (
input wire clk,
input wire reset,
input wire [N-1:0] requests,
output wire grant_valid,
input wire [N-1:0] requests,
output wire [`LOG2UP(N)-1:0] grant_index,
output wire [N-1:0] grant_onehot,
output wire [`LOG2UP(N)-1:0] grant_index
output wire grant_valid
);
reg [N-1:0] state [0:N-1];
wire [N-1:0] dis [0:N-1];
if (N == 1) begin
genvar i, j;
for (i = 0; i < N; ++i) begin
for (j = i + 1; j < N; ++j) begin
always @(posedge clk) begin
if (reset) begin
state[i][j] <= 0;
end else begin
state[i][j] <= (state[i][j] || grant_onehot[j]) && ~grant_onehot[i];
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
assign grant_index = 0;
assign grant_onehot = requests;
assign grant_valid = requests[0];
end else begin
reg [N-1:1] state [0:N-1];
wire [N-1:0] pri [0:N-1];
genvar i, j;
for (i = 0; i < N; ++i) begin
for (j = 0; j < N; ++j) begin
if (j > i) begin
assign pri[j][i] = requests[i] & state[i][j];
end
else if (j < i) begin
assign pri[j][i] = requests[i] & ~state[j][i];
end
else begin
assign pri[j][i] = 0;
end
end
assign grant_onehot[i] = requests[i] & ~(| pri[i]);
end
for (i = 0; i < N; ++i) begin
for (j = i + 1; j < N; ++j) begin
always @(posedge clk) begin
if (reset) begin
state[i][j] <= 0;
end
else begin
state[i][j] <= (state[i][j] || grant_onehot[j]) && ~grant_onehot[i];
end
end
end
end
end
for (i = 0; i < N; ++i) begin
for (j = 0; j < N; ++j) begin
if (j > i) begin
assign dis[j][i] = requests[i] & state[i][j];
end else if (j < i) begin
assign dis[j][i] = requests[i] & ~state[j][i];
end else begin
assign dis[j][i] = 0;
end
end
VX_encoder_onehot #(
.N(N)
) encoder (
.onehot (grant_onehot),
`UNUSED_PIN (valid),
.value (grant_index)
);
assign grant_valid = (| requests);
assign grant_onehot[i] = requests[i] & ~(| dis[i]);
end
VX_encoder_onehot #(
.N(N)
) encoder (
.onehot(grant_onehot),
.valid(grant_valid),
.value(grant_index)
);
endmodule

24
hw/rtl/libs/VX_priority_encoder.v
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@@ -3,26 +3,20 @@
module VX_priority_encoder #(
parameter N
) (
input wire [N-1:0] valids,
output wire [`LOG2UP(N)-1:0] index,
output wire found
input wire [N-1:0] data_in,
output reg [`LOG2UP(N)-1:0] data_out,
output reg valid_out
);
reg [`LOG2UP(N)-1:0] index_r;
reg found_r;
integer i;
always @(*) begin
index_r = 0;
found_r = 0;
for (i = `NUM_WARPS-1; i >= 0; i = i - 1) begin
if (valids[i]) begin
index_r = `NW_BITS'(i);
found_r = 1;
data_out = 0;
valid_out = 0;
for (i = N-1; i >= 0; i = i - 1) begin
if (data_in[i]) begin
data_out = `LOG2UP(N)'(i);
valid_out = 1;
end
end
end
assign index = index_r;
assign found = found_r;
endmodule

58
hw/rtl/libs/VX_rr_arbiter.v Normal file
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@@ -0,0 +1,58 @@
`include "VX_define.vh"
module VX_rr_arbiter #(
parameter N = 0
) (
input wire clk,
input wire reset,
input wire [N-1:0] requests,
output wire [`LOG2UP(N)-1:0] grant_index,
output wire [N-1:0] grant_onehot,
output wire grant_valid
);
if (N == 1) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
assign grant_index = 0;
assign grant_onehot = requests;
assign grant_valid = requests[0];
end else begin
reg [`CLOG2(N)-1:0] grant_table [0:N-1];
reg [`CLOG2(N)-1:0] state;
reg [N-1:0] grant_onehot_r;
integer i, j;
always @(*) begin
for (i = 0; i < N; ++i) begin
grant_table[i] = `CLOG2(N)'(i);
for (j = 0; j < N; ++j) begin
if (requests[(i+j) % N]) begin
grant_table[i] = `CLOG2(N)'((i+j) % N);
end
end
end
grant_onehot_r = N'(0);
grant_onehot_r[grant_index] = 1;
end
always @(posedge clk) begin
if (reset) begin
state <= 0;
end
else begin
state <= grant_index;
end
end
assign grant_index = grant_table[state];
assign grant_onehot = grant_onehot_r;
assign grant_valid = (| requests);
end
endmodule