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cache area optimization + IPC boost from 4.24 => 4.42

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This commit is contained in:
Blaise Tine
2021-07-26 21:24:27 -07:00
parent b307c40ae7
commit d2aa228a34
4 changed files with 12 additions and 12 deletions
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18
hw/rtl/VX_config.vh
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@@ -250,7 +250,7 @@
// Core Request Queue Size
`ifndef ICREQ_SIZE
`define ICREQ_SIZE 4
`define ICREQ_SIZE 0
`endif
// Core Response Queue Size
@@ -270,7 +270,7 @@
// Memory Response Queue Size
`ifndef IMRSQ_SIZE
`define IMRSQ_SIZE 4
`define IMRSQ_SIZE 0
`endif
// Dcache Configurable Knobs //////////////////////////////////////////////////
@@ -292,7 +292,7 @@
// Core Request Queue Size
`ifndef DCREQ_SIZE
`define DCREQ_SIZE 4
`define DCREQ_SIZE 0
`endif
// Core Response Queue Size
@@ -312,7 +312,7 @@
// Memory Response Queue Size
`ifndef DMRSQ_SIZE
`define DMRSQ_SIZE `MAX(4, `DNUM_BANKS)
`define DMRSQ_SIZE 0
`endif
// SM Configurable Knobs //////////////////////////////////////////////////////
@@ -334,7 +334,7 @@
// Core Request Queue Size
`ifndef SCREQ_SIZE
`define SCREQ_SIZE 4
`define SCREQ_SIZE 2
`endif
// Core Response Queue Size
@@ -356,7 +356,7 @@
// Core Request Queue Size
`ifndef L2CREQ_SIZE
`define L2CREQ_SIZE 4
`define L2CREQ_SIZE 0
`endif
// Core Response Queue Size
@@ -376,7 +376,7 @@
// Memory Response Queue Size
`ifndef L2MRSQ_SIZE
`define L2MRSQ_SIZE `MAX(4, (`L2NUM_BANKS * 2))
`define L2MRSQ_SIZE 0
`endif
// L3cache Configurable Knobs /////////////////////////////////////////////////
@@ -393,7 +393,7 @@
// Core Request Queue Size
`ifndef L3CREQ_SIZE
`define L3CREQ_SIZE 4
`define L3CREQ_SIZE 0
`endif
// Core Response Queue Size
@@ -413,7 +413,7 @@
// Memory Response Queue Size
`ifndef L3MRSQ_SIZE
`define L3MRSQ_SIZE `MAX(4, (`L3NUM_BANKS * 2))
`define L3MRSQ_SIZE 0
`endif
`endif