hw unit tests fixes
This commit is contained in:
Blaise Tine
@@ -334,157 +334,3 @@ module VX_core import VX_gpu_pkg::*; #(
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`endif
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endmodule
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///////////////////////////////////////////////////////////////////////////////
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module VX_core_top
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import VX_gpu_pkg::*;
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#(
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parameter CORE_ID = 0
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) (
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// Clock
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input wire clk,
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input wire reset,
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input wire dcr_write_valid,
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input wire [`VX_DCR_ADDR_WIDTH-1:0] dcr_write_addr,
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input wire [`VX_DCR_DATA_WIDTH-1:0] dcr_write_data,
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output wire [DCACHE_NUM_REQS-1:0] dcache_req_valid,
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output wire [DCACHE_NUM_REQS-1:0] dcache_req_rw,
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output wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE-1:0] dcache_req_byteen,
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output wire [DCACHE_NUM_REQS-1:0][DCACHE_ADDR_WIDTH-1:0] dcache_req_addr,
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output wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE*8-1:0] dcache_req_data,
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output wire [DCACHE_NUM_REQS-1:0][DCACHE_NOSM_TAG_WIDTH-1:0] dcache_req_tag,
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input wire [DCACHE_NUM_REQS-1:0] dcache_req_ready,
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input wire [DCACHE_NUM_REQS-1:0] dcache_rsp_valid,
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input wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE*8-1:0] dcache_rsp_data,
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input wire [DCACHE_NUM_REQS-1:0][DCACHE_NOSM_TAG_WIDTH-1:0] dcache_rsp_tag,
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output wire [DCACHE_NUM_REQS-1:0] dcache_rsp_ready,
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output wire icache_req_valid,
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output wire icache_req_rw,
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output wire [ICACHE_WORD_SIZE-1:0] icache_req_byteen,
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output wire [ICACHE_ADDR_WIDTH-1:0] icache_req_addr,
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output wire [ICACHE_WORD_SIZE*8-1:0] icache_req_data,
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output wire [ICACHE_TAG_WIDTH-1:0] icache_req_tag,
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input wire icache_req_ready,
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input wire icache_rsp_valid,
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input wire [ICACHE_WORD_SIZE*8-1:0] icache_rsp_data,
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input wire [ICACHE_TAG_WIDTH-1:0] icache_rsp_tag,
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output wire icache_rsp_ready,
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`ifdef GBAR_ENABLE
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output wire gbar_req_valid,
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output wire [`NB_WIDTH-1:0] gbar_req_id,
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output wire [`NC_WIDTH-1:0] gbar_req_size_m1,
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output wire [`NC_WIDTH-1:0] gbar_req_core_id,
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input wire gbar_req_ready,
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input wire gbar_rsp_valid,
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input wire [`NB_WIDTH-1:0] gbar_rsp_id,
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`endif
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// simulation helper signals
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output wire sim_ebreak,
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output wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value,
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// Status
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output wire busy
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);
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`ifdef GBAR_ENABLE
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VX_gbar_bus_if gbar_bus_if();
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assign gbar_req_valid = gbar_bus_if.req_valid;
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assign gbar_req_id = gbar_bus_if.req_id;
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assign gbar_req_size_m1 = gbar_bus_if.req_size_m1;
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assign gbar_req_core_id = gbar_bus_if.req_core_id;
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assign gbar_bus_if.req_ready = gbar_req_ready;
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assign gbar_bus_if.rsp_valid = gbar_rsp_valid;
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assign gbar_bus_if.rsp_id = gbar_rsp_id;
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`endif
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VX_dcr_bus_if dcr_bus_if();
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assign dcr_bus_if.write_valid = dcr_write_valid;
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assign dcr_bus_if.write_addr = dcr_write_addr;
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assign dcr_bus_if.write_data = dcr_write_data;
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VX_mem_bus_if #(
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.DATA_SIZE (DCACHE_WORD_SIZE),
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.TAG_WIDTH (DCACHE_NOSM_TAG_WIDTH)
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) dcache_bus_if[DCACHE_NUM_REQS]();
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for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin
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assign dcache_req_valid[i] = dcache_bus_if[i].req_valid;
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assign dcache_req_rw[i] = dcache_bus_if[i].req_data.rw;
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assign dcache_req_byteen[i] = dcache_bus_if[i].req_data.byteen;
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assign dcache_req_addr[i] = dcache_bus_if[i].req_data.addr;
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assign dcache_req_data[i] = dcache_bus_if[i].req_data.data;
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assign dcache_req_tag[i] = dcache_bus_if[i].req_data.tag;
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assign dcache_bus_if[i].req_ready = dcache_req_ready[i];
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assign dcache_bus_if[i].rsp_valid = dcache_rsp_valid[i];
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assign dcache_bus_if[i].rsp_data.tag = dcache_rsp_tag[i];
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assign dcache_bus_if[i].rsp_data.data = dcache_rsp_data[i];
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assign dcache_rsp_ready[i] = dcache_bus_if[i].rsp_ready;
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end
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VX_mem_bus_if #(
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.DATA_SIZE (ICACHE_WORD_SIZE),
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.TAG_WIDTH (ICACHE_TAG_WIDTH)
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) icache_bus_if();
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assign icache_req_valid = icache_bus_if.req_valid;
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assign icache_req_rw = icache_bus_if.req_data.rw;
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assign icache_req_byteen = icache_bus_if.req_data.byteen;
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assign icache_req_addr = icache_bus_if.req_data.addr;
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assign icache_req_data = icache_bus_if.req_data.data;
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assign icache_req_tag = icache_bus_if.req_data.tag;
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assign icache_bus_if.req_ready = icache_req_ready;
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assign icache_bus_if.rsp_valid = icache_rsp_valid;
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assign icache_bus_if.rsp_data.tag = icache_rsp_tag;
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assign icache_bus_if.rsp_data.data = icache_rsp_data;
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assign icache_rsp_ready = icache_bus_if.rsp_ready;
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`ifdef PERF_ENABLE
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VX_mem_perf_if mem_perf_if();
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`endif
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`ifdef SCOPE
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wire [0:0] scope_reset_w = 1'b0;
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wire [0:0] scope_bus_in_w = 1'b0;
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wire [0:0] scope_bus_out_w;
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`UNUSED_VAR (scope_bus_out_w)
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`endif
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VX_core #(
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.CORE_ID (0)
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) core (
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`SCOPE_IO_BIND (0)
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.clk (clk),
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.reset (reset),
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`ifdef PERF_ENABLE
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.mem_perf_if (mem_perf_if),
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`endif
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.dcr_bus_if (dcr_bus_if),
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.dcache_bus_if (dcache_bus_if),
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.icache_bus_if (icache_bus_if),
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`ifdef GBAR_ENABLE
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.gbar_bus_if (gbar_bus_if),
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`endif
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.sim_ebreak (sim_ebreak),
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.sim_wb_value (sim_wb_value),
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.busy (busy)
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);
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endmodule
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168
hw/rtl/core/VX_core_top.sv
Normal file
168
hw/rtl/core/VX_core_top.sv
Normal file
@@ -0,0 +1,168 @@
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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`ifdef EXT_F_ENABLE
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`include "VX_fpu_define.vh"
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`endif
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module VX_core_top import VX_gpu_pkg::*; #(
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parameter CORE_ID = 0
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) (
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// Clock
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input wire clk,
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input wire reset,
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input wire dcr_write_valid,
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input wire [`VX_DCR_ADDR_WIDTH-1:0] dcr_write_addr,
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input wire [`VX_DCR_DATA_WIDTH-1:0] dcr_write_data,
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output wire [DCACHE_NUM_REQS-1:0] dcache_req_valid,
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output wire [DCACHE_NUM_REQS-1:0] dcache_req_rw,
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output wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE-1:0] dcache_req_byteen,
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output wire [DCACHE_NUM_REQS-1:0][DCACHE_ADDR_WIDTH-1:0] dcache_req_addr,
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output wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE*8-1:0] dcache_req_data,
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output wire [DCACHE_NUM_REQS-1:0][DCACHE_NOSM_TAG_WIDTH-1:0] dcache_req_tag,
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input wire [DCACHE_NUM_REQS-1:0] dcache_req_ready,
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input wire [DCACHE_NUM_REQS-1:0] dcache_rsp_valid,
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input wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE*8-1:0] dcache_rsp_data,
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input wire [DCACHE_NUM_REQS-1:0][DCACHE_NOSM_TAG_WIDTH-1:0] dcache_rsp_tag,
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output wire [DCACHE_NUM_REQS-1:0] dcache_rsp_ready,
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output wire icache_req_valid,
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output wire icache_req_rw,
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output wire [ICACHE_WORD_SIZE-1:0] icache_req_byteen,
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output wire [ICACHE_ADDR_WIDTH-1:0] icache_req_addr,
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output wire [ICACHE_WORD_SIZE*8-1:0] icache_req_data,
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output wire [ICACHE_TAG_WIDTH-1:0] icache_req_tag,
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input wire icache_req_ready,
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input wire icache_rsp_valid,
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input wire [ICACHE_WORD_SIZE*8-1:0] icache_rsp_data,
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input wire [ICACHE_TAG_WIDTH-1:0] icache_rsp_tag,
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output wire icache_rsp_ready,
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`ifdef GBAR_ENABLE
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output wire gbar_req_valid,
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output wire [`NB_WIDTH-1:0] gbar_req_id,
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output wire [`NC_WIDTH-1:0] gbar_req_size_m1,
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output wire [`NC_WIDTH-1:0] gbar_req_core_id,
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input wire gbar_req_ready,
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input wire gbar_rsp_valid,
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input wire [`NB_WIDTH-1:0] gbar_rsp_id,
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`endif
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// simulation helper signals
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output wire sim_ebreak,
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output wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value,
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// Status
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output wire busy
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);
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`ifdef GBAR_ENABLE
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VX_gbar_bus_if gbar_bus_if();
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assign gbar_req_valid = gbar_bus_if.req_valid;
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assign gbar_req_id = gbar_bus_if.req_id;
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assign gbar_req_size_m1 = gbar_bus_if.req_size_m1;
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assign gbar_req_core_id = gbar_bus_if.req_core_id;
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assign gbar_bus_if.req_ready = gbar_req_ready;
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assign gbar_bus_if.rsp_valid = gbar_rsp_valid;
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assign gbar_bus_if.rsp_id = gbar_rsp_id;
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`endif
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VX_dcr_bus_if dcr_bus_if();
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assign dcr_bus_if.write_valid = dcr_write_valid;
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assign dcr_bus_if.write_addr = dcr_write_addr;
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assign dcr_bus_if.write_data = dcr_write_data;
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VX_mem_bus_if #(
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.DATA_SIZE (DCACHE_WORD_SIZE),
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.TAG_WIDTH (DCACHE_NOSM_TAG_WIDTH)
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) dcache_bus_if[DCACHE_NUM_REQS]();
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for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin
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assign dcache_req_valid[i] = dcache_bus_if[i].req_valid;
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assign dcache_req_rw[i] = dcache_bus_if[i].req_data.rw;
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assign dcache_req_byteen[i] = dcache_bus_if[i].req_data.byteen;
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assign dcache_req_addr[i] = dcache_bus_if[i].req_data.addr;
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assign dcache_req_data[i] = dcache_bus_if[i].req_data.data;
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assign dcache_req_tag[i] = dcache_bus_if[i].req_data.tag;
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assign dcache_bus_if[i].req_ready = dcache_req_ready[i];
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assign dcache_bus_if[i].rsp_valid = dcache_rsp_valid[i];
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assign dcache_bus_if[i].rsp_data.tag = dcache_rsp_tag[i];
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assign dcache_bus_if[i].rsp_data.data = dcache_rsp_data[i];
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assign dcache_rsp_ready[i] = dcache_bus_if[i].rsp_ready;
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end
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VX_mem_bus_if #(
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.DATA_SIZE (ICACHE_WORD_SIZE),
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.TAG_WIDTH (ICACHE_TAG_WIDTH)
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) icache_bus_if();
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assign icache_req_valid = icache_bus_if.req_valid;
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assign icache_req_rw = icache_bus_if.req_data.rw;
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assign icache_req_byteen = icache_bus_if.req_data.byteen;
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assign icache_req_addr = icache_bus_if.req_data.addr;
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assign icache_req_data = icache_bus_if.req_data.data;
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assign icache_req_tag = icache_bus_if.req_data.tag;
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assign icache_bus_if.req_ready = icache_req_ready;
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assign icache_bus_if.rsp_valid = icache_rsp_valid;
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assign icache_bus_if.rsp_data.tag = icache_rsp_tag;
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assign icache_bus_if.rsp_data.data = icache_rsp_data;
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assign icache_rsp_ready = icache_bus_if.rsp_ready;
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`ifdef PERF_ENABLE
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VX_mem_perf_if mem_perf_if();
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`endif
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`ifdef SCOPE
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wire [0:0] scope_reset_w = 1'b0;
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wire [0:0] scope_bus_in_w = 1'b0;
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wire [0:0] scope_bus_out_w;
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`UNUSED_VAR (scope_bus_out_w)
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`endif
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VX_core #(
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.CORE_ID (CORE_ID)
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) core (
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`SCOPE_IO_BIND (0)
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.clk (clk),
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.reset (reset),
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`ifdef PERF_ENABLE
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.mem_perf_if (mem_perf_if),
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`endif
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.dcr_bus_if (dcr_bus_if),
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.dcache_bus_if (dcache_bus_if),
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.icache_bus_if (icache_bus_if),
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`ifdef GBAR_ENABLE
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.gbar_bus_if (gbar_bus_if),
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`endif
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.sim_ebreak (sim_ebreak),
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.sim_wb_value (sim_wb_value),
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.busy (busy)
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);
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endmodule
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