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adding input buffering to bus arbiters to reduce backpressure delay propagation

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This commit is contained in:
Blaise Tine
2020-12-05 17:31:29 -08:00
parent 13a5370254
commit d0f2a3984d
17 changed files with 480 additions and 338 deletions
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77
hw/rtl/libs/VX_skid_buffer.v
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@@ -1,7 +1,8 @@
`include "VX_platform.vh"
module VX_skid_buffer #(
parameter DATAW = 1
parameter DATAW = 1,
parameter PASSTHRU = 0
) (
input wire clk,
input wire reset,
@@ -13,42 +14,56 @@ module VX_skid_buffer #(
output wire [DATAW-1:0] data_out,
input wire ready_out,
output wire valid_out
);
reg [DATAW-1:0] data_out_r;
reg [DATAW-1:0] buffer;
reg valid_out_r;
reg use_buffer;
wire push = valid_in && ready_in;
always @(posedge clk) begin
if (reset) begin
valid_out_r <= 0;
use_buffer <= 0;
end else begin
if (ready_out) begin
use_buffer <= 0;
);
if (PASSTHRU) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
assign valid_out = valid_in;
assign data_out = data_in;
assign ready_in = ready_out;
end else begin
reg [DATAW-1:0] data_out_r;
reg [DATAW-1:0] buffer;
reg valid_out_r;
reg use_buffer;
wire push = valid_in && ready_in;
always @(posedge clk) begin
if (reset) begin
valid_out_r <= 0;
use_buffer <= 0;
end else begin
if (ready_out) begin
use_buffer <= 0;
end
if (push && valid_out_r && !ready_out) begin
assert(!use_buffer);
use_buffer <= 1;
end
if (!valid_out_r || ready_out) begin
valid_out_r <= valid_in || use_buffer;
end
end
if (push && valid_out_r && !ready_out) begin
assert(!use_buffer);
use_buffer <= 1;
if (push) begin
buffer <= data_in;
end
if (!valid_out_r || ready_out) begin
valid_out_r <= valid_in || use_buffer;
data_out_r <= use_buffer ? buffer : data_in;
end
end
if (push) begin
buffer <= data_in;
end
if (!valid_out_r || ready_out) begin
data_out_r <= use_buffer ? buffer : data_in;
end
assign ready_in = !use_buffer;
assign valid_out = valid_out_r;
assign data_out = data_out_r;
end
assign ready_in = !use_buffer;
assign valid_out = valid_out_r;
assign data_out = data_out_r;
endmodule