adding input buffering to bus arbiters to reduce backpressure delay propagation
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@@ -6,9 +6,9 @@ module VX_rr_arbiter #(
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parameter LOG_NUM_REQS = $clog2(NUM_REQS)
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) (
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input wire clk,
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input wire reset,
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input wire [NUM_REQS-1:0] requests,
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input wire reset,
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input wire enable,
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input wire [NUM_REQS-1:0] requests,
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output wire [LOG_NUM_REQS-1:0] grant_index,
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output wire [NUM_REQS-1:0] grant_onehot,
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output wire grant_valid
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