adding input buffering to bus arbiters to reduce backpressure delay propagation
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16
hw/rtl/cache/VX_cache.v
vendored
16
hw/rtl/cache/VX_cache.v
vendored
@@ -361,11 +361,11 @@ module VX_cache #(
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) dram_req_arb (
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.clk (clk),
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.reset (reset),
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.valid_in (per_bank_dram_req_valid),
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.valid_out (dram_req_valid),
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.data_in (data_in),
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.data_out ({dram_req_addr, dram_req_rw, dram_req_byteen, dram_req_data}),
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.ready_in (per_bank_dram_req_ready),
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.valid_in (per_bank_dram_req_valid),
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.data_in (data_in),
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.ready_in (per_bank_dram_req_ready),
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.valid_out (dram_req_valid),
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.data_out ({dram_req_addr, dram_req_rw, dram_req_byteen, dram_req_data}),
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.ready_out (dram_req_ready)
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);
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end else begin
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@@ -392,10 +392,10 @@ module VX_cache #(
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.clk (clk),
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.reset (reset),
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.valid_in (per_bank_snp_rsp_valid),
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.valid_out (snp_rsp_valid),
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.data_in (per_bank_snp_rsp_tag),
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.data_out (snp_rsp_tag),
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.ready_in (per_bank_snp_rsp_ready),
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.ready_in (per_bank_snp_rsp_ready),
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.valid_out (snp_rsp_valid),
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.data_out (snp_rsp_tag),
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.ready_out (snp_rsp_ready)
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);
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end else begin
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