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adding input buffering to bus arbiters to reduce backpressure delay propagation

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This commit is contained in:
Blaise Tine
2020-12-05 17:31:29 -08:00
parent 13a5370254
commit d0f2a3984d
17 changed files with 480 additions and 338 deletions
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16
hw/rtl/cache/VX_cache.v vendored
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@@ -361,11 +361,11 @@ module VX_cache #(
) dram_req_arb (
.clk (clk),
.reset (reset),
.valid_in (per_bank_dram_req_valid),
.valid_out (dram_req_valid),
.data_in (data_in),
.data_out ({dram_req_addr, dram_req_rw, dram_req_byteen, dram_req_data}),
.ready_in (per_bank_dram_req_ready),
.valid_in (per_bank_dram_req_valid),
.data_in (data_in),
.ready_in (per_bank_dram_req_ready),
.valid_out (dram_req_valid),
.data_out ({dram_req_addr, dram_req_rw, dram_req_byteen, dram_req_data}),
.ready_out (dram_req_ready)
);
end else begin
@@ -392,10 +392,10 @@ module VX_cache #(
.clk (clk),
.reset (reset),
.valid_in (per_bank_snp_rsp_valid),
.valid_out (snp_rsp_valid),
.data_in (per_bank_snp_rsp_tag),
.data_out (snp_rsp_tag),
.ready_in (per_bank_snp_rsp_ready),
.ready_in (per_bank_snp_rsp_ready),
.valid_out (snp_rsp_valid),
.data_out (snp_rsp_tag),
.ready_out (snp_rsp_ready)
);
end else begin

10
hw/rtl/cache/VX_cache_core_req_bank_sel.v vendored
View File

@@ -18,6 +18,7 @@ module VX_cache_core_req_bank_sel #(
input wire [NUM_BANKS-1:0] per_bank_ready
);
if (NUM_BANKS > 1) begin
reg [NUM_BANKS-1:0][NUM_REQS-1:0] per_bank_valid_r;
reg [NUM_BANKS-1:0] per_bank_ready_ignore;
reg [NUM_BANKS-1:0] per_bank_ready_other;
@@ -29,8 +30,9 @@ module VX_cache_core_req_bank_sel #(
for (integer i = 0; i < NUM_BANKS; i++) begin
for (integer j = 0; j < NUM_BANKS; j++) begin
if (i != j)
if (i != j) begin
per_bank_ready_other[i] &= (per_bank_ready[j] | per_bank_ready_ignore[j]);
end
end
end
@@ -45,11 +47,15 @@ module VX_cache_core_req_bank_sel #(
assign per_bank_valid[i][j] = per_bank_valid_r[i][j] & per_bank_ready_other[i];
end
end
assign core_req_ready = & (per_bank_ready | per_bank_ready_ignore);
end else begin
end else begin
`UNUSED_VAR (core_req_addr)
assign per_bank_valid = core_req_valid;
assign core_req_ready = per_bank_ready;
end
endmodule

9
hw/rtl/cache/VX_cache_core_rsp_merge.v vendored
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@@ -42,10 +42,11 @@ module VX_cache_core_rsp_merge #(
always @(*) begin
core_rsp_valid_unqual = 0;
core_rsp_tag_unqual = 'x;
sel_tag_id = 'x;
core_rsp_data_unqual = 'x;
core_rsp_bank_select = 0;
core_rsp_data_unqual = 'x;
core_rsp_bank_select = 0;
sel_tag_id = 'x;
for (integer i = 0; i < NUM_BANKS; i++) begin
if (per_bank_core_rsp_valid[i]) begin
core_rsp_tag_unqual = per_bank_core_rsp_tag[i];
@@ -90,7 +91,7 @@ module VX_cache_core_rsp_merge #(
VX_generic_register #(
.N(NUM_REQS + (NUM_REQS *`WORD_WIDTH) + (`CORE_REQ_TAG_COUNT * CORE_TAG_WIDTH)),
.R(NUM_REQS),
.PASSTHRU(NUM_BANKS <= 2)
.PASSTHRU(NUM_BANKS < 4)
) pipe_reg (
.clk (clk),
.reset (reset),

42
hw/rtl/cache/VX_snp_forwarder.v vendored
View File

@@ -27,16 +27,16 @@ module VX_snp_forwarder #(
input wire snp_rsp_ready,
// Snoop Forwarding out
output wire [NUM_REQS-1:0] snp_fwdout_valid,
output wire [NUM_REQS-1:0] snp_fwdout_valid,
output wire [NUM_REQS-1:0][DST_ADDR_WIDTH-1:0] snp_fwdout_addr,
output wire [NUM_REQS-1:0] snp_fwdout_inv,
output wire [NUM_REQS-1:0][LOG_SNRQ_SIZE-1:0] snp_fwdout_tag,
input wire [NUM_REQS-1:0] snp_fwdout_ready,
output wire [NUM_REQS-1:0] snp_fwdout_inv,
output wire [NUM_REQS-1:0][LOG_SNRQ_SIZE-1:0] snp_fwdout_tag,
input wire [NUM_REQS-1:0] snp_fwdout_ready,
// Snoop forwarding in
input wire [NUM_REQS-1:0] snp_fwdin_valid,
input wire [NUM_REQS-1:0] snp_fwdin_valid,
input wire [NUM_REQS-1:0][LOG_SNRQ_SIZE-1:0] snp_fwdin_tag,
output wire [NUM_REQS-1:0] snp_fwdin_ready
output wire [NUM_REQS-1:0] snp_fwdin_ready
);
localparam ADDR_DIFF = DST_ADDR_WIDTH - SRC_ADDR_WIDTH;
localparam NUM_REQUESTS_QUAL = NUM_REQS * (1 << ADDR_DIFF);
@@ -44,6 +44,26 @@ module VX_snp_forwarder #(
`STATIC_ASSERT(NUM_REQS > 1, ("invalid value"))
// Inputs buffering
wire [NUM_REQS-1:0] snp_fwdin_valid_qual;
wire [NUM_REQS-1:0][LOG_SNRQ_SIZE-1:0] snp_fwdin_tag_qual;
wire [NUM_REQS-1:0] snp_fwdin_ready_qual;
for (genvar i = 0; i < NUM_REQS; ++i) begin
VX_skid_buffer #(
.DATAW (LOG_SNRQ_SIZE),
.PASSTHRU (NUM_REQS < 4)
) snp_fwdin_buffer (
.clk (clk),
.reset (reset),
.valid_in (snp_fwdin_valid[i]),
.data_in (snp_fwdin_tag[i]),
.ready_in (snp_fwdin_ready[i]),
.valid_out (snp_fwdin_valid_qual[i]),
.data_out (snp_fwdin_tag_qual[i]),
.ready_out (snp_fwdin_ready_qual[i])
);
end
reg [REQ_QUAL_BITS:0] pending_cntrs [SNRQ_SIZE-1:0];
wire [LOG_SNRQ_SIZE-1:0] sfq_write_addr, sfq_read_addr;
@@ -167,11 +187,11 @@ module VX_snp_forwarder #(
) snp_fwdin_arb (
.clk (clk),
.reset (reset),
.valid_in (snp_fwdin_valid),
.valid_out (fwdin_valid),
.data_in (snp_fwdin_tag),
.data_out (fwdin_tag),
.ready_in (snp_fwdin_ready),
.valid_in (snp_fwdin_valid_qual),
.data_in (snp_fwdin_tag_qual),
.ready_in (snp_fwdin_ready_qual),
.valid_out (fwdin_valid),
.data_out (fwdin_tag),
.ready_out (fwdin_ready)
);