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adding input buffering to bus arbiters to reduce backpressure delay propagation

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This commit is contained in:
Blaise Tine
2020-12-05 17:31:29 -08:00
parent 13a5370254
commit d0f2a3984d
17 changed files with 480 additions and 338 deletions
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38
hw/rtl/VX_mem_arb.v
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@@ -43,25 +43,47 @@ module VX_mem_arb #(
input wire [DATA_WIDTH-1:0] rsp_data_in,
output wire rsp_ready_in
);
localparam DATAW = TAG_OUT_WIDTH + ADDR_WIDTH + 1 + DATA_SIZE + DATA_WIDTH;
if (NUM_REQS > 1) begin
wire [NUM_REQS-1:0][(TAG_OUT_WIDTH + ADDR_WIDTH + 1 + DATA_SIZE + DATA_WIDTH)-1:0] data_in;
wire [NUM_REQS-1:0][DATAW-1:0] data_in;
for (genvar i = 0; i < NUM_REQS; i++) begin
assign data_in[i] = {{req_tag_in[i], REQS_BITS'(i)}, req_addr_in[i], req_rw_in[i], req_byteen_in[i], req_data_in[i]};
end
// Inputs buffering
wire [NUM_REQS-1:0] req_valid_in_qual;
wire [NUM_REQS-1:0][DATAW-1:0] req_data_in_qual;
wire [NUM_REQS-1:0] req_ready_in_qual;
for (genvar i = 0; i < NUM_REQS; ++i) begin
VX_skid_buffer #(
.DATAW (DATAW),
.PASSTHRU (NUM_REQS < 4)
) req_buffer (
.clk (clk),
.reset (reset),
.valid_in (req_valid_in[i]),
.data_in (data_in[i]),
.ready_in (req_ready_in[i]),
.valid_out (req_valid_in_qual[i]),
.data_out (req_data_in_qual[i]),
.ready_out (req_ready_in_qual[i])
);
end
VX_stream_arbiter #(
.NUM_REQS(NUM_REQS),
.DATAW(TAG_OUT_WIDTH + ADDR_WIDTH + 1 + DATA_SIZE + DATA_WIDTH),
.BUFFERED(NUM_REQS >= 4)
.NUM_REQS (NUM_REQS),
.DATAW (DATAW),
.BUFFERED (NUM_REQS >= 4)
) req_arb (
.clk (clk),
.reset (reset),
.valid_in (req_valid_in),
.valid_in (req_valid_in_qual),
.data_in (req_data_in_qual),
.ready_in (req_ready_in_qual),
.valid_out (req_valid_out),
.data_in (data_in),
.data_out ({req_tag_out, req_addr_out, req_rw_out, req_byteen_out, req_data_out}),
.ready_in (req_ready_in),
.data_out ({req_tag_out, req_addr_out, req_rw_out, req_byteen_out, req_data_out}),
.ready_out (req_ready_out)
);